verilator-4.038/0000775000177100017500000000000013702335701013515 5ustar wsnyderwsnyderverilator-4.038/verilator.txt0000664000177100017500000070412213702335700016272 0ustar wsnyderwsnyderNAME Verilator - Translate and simulate SystemVerilog code using C++/SystemC SYNOPSIS verilator --help verilator --version verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] verilator --lint-only -Wall [source_files.v]... DESCRIPTION The "Verilator" package converts all synthesizable, and many behavioral, Verilog and SystemVerilog designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler. Verilator is typically used as follows: 1. The "verilator" executable is invoked with parameters similar to GCC, Cadence Verilog-XL/NC-Verilog, or Synopsys VCS. "verilator" reads the specified user's SystemVerilog code, lints it, optionally adds coverage and waveform tracing support, and compiles the design into a source level C++ or SystemC "model". The resulting model's C++ or SystemC code is output as .cpp and .h files. This is referred to as "verilating" and the process is "to verilate"; the output is a "verilated" model. 2. For simulation, a small user written C++ wrapper file is required, the "wrapper". This wrapper defines the C++ function `main()` which instantiates the Verilated model as a C++/SystemC object. 3. The user main wrapper, the files created by Verilator, a "runtime library" provided by Verilator, and if applicable the SystemC libraries are then compiled using a C++ compiler to create a simulation executable. 4. The resulting executable will perform the actual simulation, during "simulation runtime". To get started, jump down to the "EXAMPLE C++ EXECUTION" section. ARGUMENT SUMMARY This is a short summary of the arguments to the "verilator" executable. See "VERILATION ARGUMENTS" for the detailed descriptions of these arguments. {file.v} Verilog package, module and top module filenames {file.c/cc/cpp} Optional C++ files to compile in {file.a/o/so} Optional C++ files to link in +1364-1995ext+ Use Verilog 1995 with file extension +1364-2001ext+ Use Verilog 2001 with file extension +1364-2005ext+ Use Verilog 2005 with file extension +1800-2005ext+ Use SystemVerilog 2005 with file extension +1800-2009ext+ Use SystemVerilog 2009 with file extension +1800-2012ext+ Use SystemVerilog 2012 with file extension +1800-2017ext+ Use SystemVerilog 2017 with file extension --assert Enable all assertions --autoflush Flush streams after all $displays --bbox-sys Blackbox unknown $system calls --bbox-unsup Blackbox unsupported language features --bin Override Verilator binary --build Build model executable/library after Verilation -CFLAGS C++ compiler flags for makefile --cc Create C++ output --cdc Clock domain crossing analysis --clk Mark specified signal as clock --make Generate scripts for specified build tool --compiler Tune for specified C++ compiler --converge-limit Tune convergence settle time --coverage Enable all coverage --coverage-line Enable line coverage --coverage-toggle Enable toggle coverage --coverage-user Enable SVL user coverage --coverage-underscore Enable coverage of _signals -D[=] Set preprocessor define --debug Enable debugging --debug-check Enable debugging assertions --no-debug-leak Disable leaking memory in --debug mode --debugi Enable debugging at a specified level --debugi- Enable debugging a source file at a level --default-language Default language to parse +define+= Set preprocessor define --dpi-hdr-only Only produce the DPI header file --dump-defines Show preprocessor defines with -E --dump-tree Enable dumping .tree files --dump-treei Enable dumping .tree files at a level --dump-treei- Enable dumping .tree file at a source file at a level --dump-tree-addrids Use short identifiers instead of addresses -E Preprocess, but do not compile --error-limit Abort after this number of errors --exe Link to create executable -F Parse options from a file, relatively -f Parse options from a file -FI Force include of a file --flatten Force inlining of all modules, tasks and functions -G= Overwrite top-level parameter --gdb Run Verilator under GDB interactively --gdbbt Run Verilator under GDB for backtrace --generate-key Create random key for --protect-key --getenv Get environment variable with defaults --help Display this help -I Directory to search for includes -j Parallelism for --build --gate-stmts Tune gate optimizer depth --if-depth Tune IFDEPTH warning +incdir+ Directory to search for includes --inhibit-sim Create function to turn off sim --inline-mult Tune module inlining -LDFLAGS Linker pre-object flags for makefile --l2-name Verilog scope name of the top module --language Default language standard to parse +libext++[ext]... Extensions for finding modules --lint-only Lint, but do not make output -MAKEFLAGS Options to make during --build --max-num-width Maximum number width (default: 64K) --MMD Create .d dependency files --MP Create phony dependency targets --Mdir Name of output object directory --mod-prefix Name to prepend to lower classes --no-clk Prevent marking specified signal as clock --no-decoration Disable comments and symbol decorations --no-pins64 Don't use vluint64_t's for 33-64 bit sigs --no-skip-identical Disable skipping identical output +notimingchecks Ignored -O0 Disable optimizations -O3 High performance optimizations -O Selectable optimizations -o Name of final executable --no-order-clock-delay Disable ordering clock enable assignments --no-verilate Skip verilation and just compile previously Verilated code. --output-split Split .cpp files into pieces --output-split-cfuncs Split model functions --output-split-ctrace Split tracing functions -P Disable line numbers and blanks with -E --pins-bv Specify types for top level ports --pins-sc-uint Specify types for top level ports --pins-sc-biguint Specify types for top level ports --pins-uint8 Specify types for top level ports --pipe-filter Filter all input through a script --pp-comments Show preprocessor comments with -E --prefix Name of top level class --prof-cfuncs Name functions for profiling --prof-threads Enable generating gantt chart data for threads --protect-key Key for symbol protection --protect-ids Hash identifier names for obscurity --protect-lib Create a DPI protected library --private Debugging; see docs --public Debugging; see docs --public-flat-rw Mark all variables, etc as public_flat_rw -pvalue+= Overwrite toplevel parameter --quiet-exit Don't print the command on failure --relative-includes Resolve includes relative to current file --no-relative-cfuncs Disallow 'this->' in generated functions --report-unoptflat Extra diagnostics for UNOPTFLAT --rr Run Verilator and record with rr --savable Enable model save-restore --sc Create SystemC output --stats Create statistics file --stats-vars Provide statistics on variables -sv Enable SystemVerilog parsing +systemverilogext+ Synonym for +1800-2017ext+ --threads Enable multithreading --threads-dpi Enable multithreaded DPI --threads-max-mtasks Tune maximum mtask partitioning --timescale Sets default timescale --timescale-override Overrides all timescales --top-module Name of top level input module --trace Enable waveform creation --trace-coverage Enable tracing of coverage --trace-depth Depth of tracing --trace-fst Enable FST waveform creation --trace-max-array Maximum bit width for tracing --trace-max-width Maximum array depth for tracing --trace-params Enable tracing of parameters --trace-structs Enable tracing structure names --trace-threads Enable waveform creation on separate threads --trace-underscore Enable tracing of _signals -U Undefine preprocessor define --unroll-count Tune maximum loop iterations --unroll-stmts Tune maximum loop body size --unused-regexp Tune UNUSED lint signals -V Verbose version and config -v Verilog library +verilog1995ext+ Synonym for +1364-1995ext+ +verilog2001ext+ Synonym for +1364-2001ext+ --version Displays program version and exits --vpi Enable VPI compiles --waiver-output Create a waiver file based on the linter warnings -Wall Enable all style warnings -Werror- Convert warnings to errors -Wfuture- Disable unknown message warnings -Wno- Disable warning -Wno-context Disable source context on warnings -Wno-fatal Disable fatal exit on warnings -Wno-lint Disable all lint warnings -Wno-style Disable all style warnings -Wpedantic Warn on compliance-test issues --x-assign Assign non-initial Xs to this value --x-initial Assign initial Xs to this value --x-initial-edge Enable initial X->0 and X->1 edge triggers --xml-only Create XML parser output --xml-output XML output filename -y Directory to search for modules This is a short summary of the simulation runtime arguments, i.e. for the final Verilated simulation runtime models. See "SIMULATION RUNTIME ARGUMENTS" for the detailed description of these arguments. +verilator+debug Enable debugging +verilator+debugi+ Enable debugging at a level +verilator+help Display help +verilator+prof+threads+file+I Set profile filename +verilator+prof+threads+start+I Set profile starting point +verilator+prof+threads+window+I Set profile duration +verilator+rand+reset+I Set random reset technique +verilator+seed+I Set random seed +verilator+noassert Disable assert checking +verilator+V Verbose version and config +verilator+version Show version and exit VERILATION ARGUMENTS The following are the arguments that may be passed to the "verilator" executable. {file.v} Specifies the Verilog file containing the top module to be Verilated. {file.c/.cc/.cpp/.cxx} Used with --exe to specify optional C++ files to be linked in with the Verilog code. The file path should either be absolute, or relative to where the make will be executed from, or add to your makefile's VPATH the appropriate directory to find the file. See also the -CFLAGS and -LDFLAGS options, which are useful when the C++ files need special compiler flags. {file.a/.o/.so} Specifies optional object or library files to be linked in with the Verilog code, as a shorthand for -LDFLAGS "". The file path should either be absolute, or relative to where the make will be executed from, or add to your makefile's VPATH the appropriate directory to find the file. If any files are specified in this way, Verilator will include a make rule that uses these files when linking the *module* executable. This generally is only useful when used with the --exe option. +1364-1995ext+*ext* +1364-2001ext+*ext* +1364-2005ext+*ext* +1800-2005ext+*ext* +1800-2009ext+*ext* +1800-2012ext+*ext* +1800-2017ext+*ext* Specifies the language standard to be used with a specific filename extension, *ext*. For compatibility with other simulators, see also the synonyms "+verilog1995ext+"*ext*, "+verilog2001ext+"*ext*, and "+systemverilogext+"*ext*. For any source file, the language specified by these options takes precedence over any language specified by the "--default-language" or "--language" options. These options take effect in the order they are encountered. Thus the following would use Verilog 1995 for "a.v" and Verilog 2001 for "b.v". verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v These flags are only recommended for legacy mixed language designs, as the preferable option is to edit the code to repair new keywords, or add appropriate "`begin_keywords". Note "`begin_keywords" is a SystemVerilog construct, which specifies *only* the set of keywords to be recognized. This also controls some error messages that vary between language standards. Note at present Verilator tends to be overly permissive, e.g. it will accept many grammar and other semantic extensions which might not be legal when set to an older standard. --assert Enable all assertions. --autoflush After every $display or $fdisplay, flush the output stream. This ensures that messages will appear immediately but may reduce performance. For best performance call "fflush(stdout)" occasionally in the C++ main loop. Defaults to off, which will buffer output as provided by the normal C/C++ standard library IO. --bbox-sys Black box any unknown $system task or function calls. System tasks will simply become no-operations, and system functions will be replaced with unsized zero. Arguments to such functions will be parsed, but not otherwise checked. This prevents errors when linting in the presence of company specific PLI calls. Using this argument will likely cause incorrect simulation. --bbox-unsup Black box some unsupported language features, currently UDP tables, the cmos and tran gate primitives, deassign statements, and mixed edge errors. This may enable linting the rest of the design even when unsupported constructs are present. Using this argument will likely cause incorrect simulation. --bin *filename* Rarely needed. Override the default filename for Verilator itself. When a dependency (.d) file is created, this filename will become a source dependency, such that a change in this binary will have make rebuild the output files. --build After generating the SystemC/C++ code, Verilator will invoke the toolchain to build the model library (and executable when "--exe" is also used). Verilator manages the build itself, and for this --build requires GNU Make to be available on the platform. -CFLAGS *flags* Add specified C compiler flag to the generated makefiles. For multiple flags either pass them as a single argument with space separators quoted in the shell ("-CFLAGS "-a -b""), or use multiple -CFLAGS arguments ("-CFLAGS -a -CFLAGS -b"). When make is run on the generated makefile these will be passed to the C++ compiler (g++/clang++/msvc++). --cc Specifies C++ without SystemC output mode; see also --sc. --cdc Permanently experimental. Perform some clock domain crossing checks and issue related warnings (CDCRSTLOGIC) and then exit; if warnings other than CDC warnings are needed make a second run with --lint-only. Additional warning information is also written to the file {prefix}__cdc.txt. Currently only checks some items that other CDC tools missed; if you have interest in adding more traditional CDC checks, please contact the authors. --clk *signal-name* Sometimes it is quite difficult for Verilator to distinguish clock signals from other data signals. Occasionally the clock signals can end up in the checking list of signals which determines if further evaluation is needed. This will heavily degrade the performance of a Verilated model. With --clk , user can specified root clock into the model, then Verilator will mark the signal as clocker and propagate the clocker attribute automatically to other signals derived from that. In this way, Verilator will try to avoid taking the clocker signal into checking list. Note signal-name is specified by the RTL hierarchy path. For example, v.foo.bar. If the signal is the input to top-module, the directly the signal name. If you find it difficult to find the exact name, try to use "/*verilator clocker*/" in RTL file to mark the signal directly. If clock signals are assigned to vectors and then later used individually, Verilator will attempt to decompose the vector and connect the single-bit clock signals directly. This should be transparent to the user. --make *build-tool* Generates a script for the specified build tool. Supported values are "gmake" for GNU Make and "cmake" for CMake. Both can be specified together. If no build tool is specified, gmake is assumed. The executable of gmake can be configured via environment variable "MAKE". When using --build Verilator takes over the responsibility of building the model library/executable. For this reason --make cannot be specified when using --build. --compiler *compiler-name* Enables workarounds for the specified C++ compiler, either "clang", "gcc", or "msvc". Currently this does not change any performance tuning flags, but it may in the future. clang Tune for clang. This may reduce execution speed as it enables several workarounds to avoid silly hard-coded limits in clang. This includes breaking deep structures as for msvc as described below. gcc Tune for GNU C++, although generated code should work on almost any compliant C++ compiler. Currently the default. msvc Tune for Microsoft Visual C++. This may reduce execution speed as it enables several workarounds to avoid silly hard-coded limits in MSVC++. This includes breaking deeply nested parenthesized expressions into sub-expressions to avoid error C1009, and breaking deep blocks into functions to avoid error C1061. --converge-limit *loops* Rarely needed. Specifies the maximum number of runtime iterations before creating a model failed to converge error. Defaults to 100. --coverage Enables all forms of coverage, alias for "--coverage-line --coverage-toggle --coverage-user". --coverage-line Specifies basic block line coverage analysis code should be inserted. Coverage analysis adds statements at each code flow change point (e.g. at branches). At each such branch a unique counter is incremented. At the end of a test, the counters along with the filename and line number corresponding to each counter are written into logs/coverage.dat. Verilator automatically disables coverage of branches that have a $stop in them, as it is assumed $stop branches contain an error check that should not occur. A /*verilator coverage_block_off*/ comment will perform a similar function on any code in that block or below, or /*verilator coverage_on/coverage_off*/ will disable coverage around lines of code. Note Verilator may over-count combinatorial (non-clocked) blocks when those blocks receive signals which have had the UNOPTFLAT warning disabled; for most accurate results do not disable this warning when using coverage. --coverage-toggle Specifies signal toggle coverage analysis code should be inserted. Every bit of every signal in a module has a counter inserted. The counter will increment on every edge change of the corresponding bit. Signals that are part of tasks or begin/end blocks are considered local variables and are not covered. Signals that begin with underscores, are integers, or are very wide (>256 bits total storage across all dimensions) are also not covered. Hierarchy is compressed, such that if a module is instantiated multiple times, coverage will be summed for that bit across ALL instantiations of that module with the same parameter set. A module instantiated with different parameter values is considered a different module, and will get counted separately. Verilator makes a minimally-intelligent decision about what clock domain the signal goes to, and only looks for edges in that clock domain. This means that edges may be ignored if it is known that the edge could never be seen by the receiving logic. This algorithm may improve in the future. The net result is coverage may be lower than what would be seen by looking at traces, but the coverage is a more accurate representation of the quality of stimulus into the design. There may be edges counted near time zero while the model stabilizes. It's a good practice to zero all coverage just before releasing reset to prevent counting such behavior. A /*verilator coverage_off/on */ comment pair can be used around signals that do not need toggle analysis, such as RAMs and register files. --coverage-underscore Enable coverage of signals that start with an underscore. Normally, these signals are not covered. See also --trace-underscore. --coverage-user Enables user inserted functional coverage. Currently, all functional coverage points are specified using SVA which must be separately enabled with --assert. For example, the following statement will add a coverage point, with the comment "DefaultClock": DefaultClock: cover property (@(posedge clk) cyc==3); -D*var*=*value* Defines the given preprocessor symbol. Similar to +define, but does not allow multiple definitions with a single option using plus signs. +define is fairly standard across Verilog tools while -D is similar to GCC. --debug Select the debug executable of Verilator (if available), and enable more internal assertions (equivalent to "--debug-check"), debugging messages (equivalent to "--debugi 4"), and intermediate form dump files (equivalent to "--dump-treei 3"). --debug-check Rarely needed. Enable internal debugging assertion checks, without changing debug verbosity. Enabled automatically when --debug specified. --no-debug-leak In --debug mode, by default Verilator intentionally leaks AstNode instances instead of freeing them, so that each node pointer is unique in the resulting tree files and dot files. This option disables the leak. This may avoid out-of-memory errors when Verilating large models in --debug mode. Outside of --debug mode, AstNode instances should never be leaked and this option has no effect. --debugi *level* --debugi-*srcfile* *level* Rarely needed - for developer use. Set internal debugging level globally to the specified debug level (1-10) or set the specified Verilator source file to the specified level (e.g. "--debugi-V3Width 9"). Higher levels produce more detailed messages. --default-language *value* Select the language to be used by default when first processing each Verilog file. The language value must be "1364-1995", "1364-2001", "1364-2005", "1800-2005", "1800-2009", "1800-2012" or "1800-2017". Any language associated with a particular file extension (see the various +*lang*ext+ options) will be used in preference to the language specified by --default-language. The --default-language flag is only recommended for legacy code using the same language in all source files, as the preferable option is to edit the code to repair new keywords, or add appropriate "`begin_keywords". For legacy mixed language designs, the various +*lang*ext+ options should be used. If no language is specified, either by this flag or +*lang*ext+ options, then the latest SystemVerilog language (IEEE 1800-2017) is used. +define+*var*=*value* +define+*var*=*value*+*var2*=*value2*... Defines the given preprocessor symbol, or multiple symbols if separated by plus signs. Similar to -D; +define is fairly standard across Verilog tools while -D is similar to GCC. --dpi-hdr-only Only generate the DPI header file. This option has no effect on the name or location of the emitted DPI header file, it is output in "--Mdir" as it would be without this option. --dump-defines With -E, suppress normal output, and instead print a list of all defines existing at the end of pre-processing the input files. Similar to GCC "-dM" option. This also gives you a way of finding out what is predefined in Verilator using the command: touch foo.v ; verilator -E --dump-defines foo.v --dump-tree Rarely needed. Enable writing .tree debug files with dumping level 3, which dumps the standard critical stages. For details on the format see the Verilator Internals manual. --dump-tree is enabled automatically with --debug, so "--debug --no-dump-tree" may be useful if the dump files are large and not desired. --dump-treei *level* --dump-treei-*srcfile* *level* Rarely needed - for developer use. Set internal tree dumping level globally to a specific dumping level or set the specified Verilator source file to the specified tree dumping level (e.g. "--dump-treei-V3Order 9"). Level 0 disables dumps and is equivalent to "--no-dump-tree". Level 9 enables dumping of every stage. --dump-tree-addrids Rarely needed - for developer use. Replace AST node addresses with short identifiers in tree dumps to enhance readability. Each unique pointer value is mapped to a unique identifier, but note that this is not necessarily unique per node instance as an address might get reused by a newly allocated node after a node with the same address has been dumped then freed. -E Preprocess the source code, but do not compile, as with 'gcc -E'. Output is written to standard out. Beware of enabling debugging messages, as they will also go to standard out. --error-limit *value* After this number of errors are encountered during Verilator run, exit. Warnings are not counted in this limit. Defaults to 50. Does not affect simulation runtime errors, for those see +verilator+error+limit. --exe Generate an executable. You will also need to pass additional .cpp files on the command line that implement the main loop for your simulation. -F *file* Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the directory containing the specified file. See also -f. Note -F is fairly standard across Verilog tools. -f *file* Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the current directory. See also -F. Note -f is fairly standard across Verilog tools. The file may contain // comments which are ignored to the end of the line. Any $VAR, $(VAR), or ${VAR} will be replaced with the specified environment variable. -FI *file* Force include of the specified C++ header file. All generated C++ files will insert a #include of the specified file before any other includes. The specified file might be used to contain define prototypes of custom VL_VPRINTF functions, and may need to include verilatedos.h as this file is included before any other standard includes. --flatten Force flattening of the design's hierarchy, with all modules, tasks and functions inlined. Typically used with "--xml-only". Note flattening large designs may require significant CPU time, memory and storage. -G*name*=*value* Overwrites the given parameter of the toplevel module. The value is limited to basic data literals: Verilog integer literals The standard Verilog integer literals are supported, so values like 32'h8, 2'b00, 4 etc. are allowed. Care must be taken that the single quote (I') is properly escaped in an interactive shell, e.g., as -GWIDTH=8\'hx. C integer literals It is also possible to use C integer notation, including hexadecimal (0x..), octal (0..) or binary (0b..) notation. Double literals Double literals must be one of the following styles: - contains a dot (.) (e.g. 1.23) - contains an exponent (e/E) (e.g. 12e3) - contains p/P for hexadecimal floating point in C99 (e.g. 0x123.ABCp1) Strings Strings must be in double quotes (""). They must be escaped properly on the command line, e.g. as -GSTR="\"My String\"" or -GSTR='"My String"'. --gate-stmts *value* Rarely needed. Set the maximum number of statements that may be present in an equation for the gate substitution optimization to inline that equation. --gdb Run Verilator underneath an interactive GDB (or VERILATOR_GDB environment variable value) session. See also --gdbbt. --gdbbt If --debug is specified, run Verilator underneath a GDB process and print a backtrace on exit, then exit GDB immediately. Without --debug or if GDB doesn't seem to work, this flag is ignored. Intended for easy creation of backtraces by users; otherwise see the --gdb flag. --generate-key Generate a true-random key suitable for use with --protect-key, print it, and exit immediately. --getenv *variable* If the variable is declared in the environment, print it and exit immediately. Otherwise, if it's built into Verilator (e.g. VERILATOR_ROOT), print that and exit immediately. Otherwise, print a newline and exit immediately. This can be useful in makefiles. See also -V, and the various *.mk files. --help Displays this message and program version and exits. -I*dir* See -y. --if-depth *value* Rarely needed. Set the depth at which the IFDEPTH warning will fire, defaults to 0 which disables this warning. +incdir+*dir* See -y. --inhibit-sim Rarely needed. Create a "inhibitSim(bool)" function to enable and disable evaluation. This allows an upper level testbench to disable modules that are not important in a given simulation, without needing to recompile or change the SystemC modules instantiated. --inline-mult *value* Tune the inlining of modules. The default value of 2000 specifies that up to 2000 new operations may be added to the model by inlining, if more than this number of operations would result, the module is not inlined. Larger values, or a value < 1 will inline everything, will lead to longer compile times, but potentially faster simulation speed. This setting is ignored for very small modules; they will always be inlined, if allowed. -j Specify the level of parallelism for --build. must be a positive integer specifying the maximum number of parallel build jobs, or can be omitted. When is omitted, the build will not try to limit the number of parallel build jobs but attempt to execute all independent build steps in parallel. -LDFLAGS *flags* Add specified C linker flags to the generated makefiles. For multiple flags either pass them as a single argument with space separators quoted in the shell ("-LDFLAGS "-a -b""), or use multiple -LDFLAGS arguments ("-LDFLAGS -a -LDFLAGS -b"). When make is run on the generated makefile these will be passed to the C++ linker (ld) *after* the primary file being linked. This flag is called -LDFLAGS as that's the traditional name in simulators; it's would have been better called LDLIBS as that's the Makefile variable it controls. (In Make, LDFLAGS is before the first object, LDLIBS after. -L libraries need to be in the Make variable LDLIBS, not LDFLAGS.) --l2-name *value* Instead of using the module name when showing Verilog scope, use the name provided. This allows simplifying some Verilator-embedded modeling methodologies. Default is an l2-name matching the top module. The default before 3.884 was "--l2-name v" For example, the program "module t; initial $display("%m"); endmodule" will show by default "t". With "--l2-name v" it will print "v". --language *value* A synonym for "--default-language", for compatibility with other tools and earlier versions of Verilator. +libext+*ext*+*ext*... Specify the extensions that should be used for finding modules. If for example module *x* is referenced, look in *x*.*ext*. Note +libext+ is fairly standard across Verilog tools. Defaults to .v and .sv. --lint-only Check the files for lint violations only, do not create any other output. You may also want the -Wall option to enable messages that are considered stylistic and not enabled by default. If the design is not to be completely Verilated see also the --bbox-sys and --bbox-unsup options. -MAKEFLAGS When using --build, add the specified flag to the invoked make command line. For multiple flags either pass them as a single argument with space separators quoted in the shell (e.g. "-MAKEFLAGS "-a -b""), or use multiple -MAKEFLAGS arguments (e.g. "-MAKEFLAGS -l -MAKEFLAGS -k"). Use of this option should not be required for simple builds using the host toolchain. --max-num-width *value* Set the maximum number literal width (e.g. in 1024'd22 this it the 1024). Defaults to 64K. --MMD =item --no-MMD Enable/disable creation of .d dependency files, used for make dependency detection, similar to gcc -MMD option. By default this option is enabled for --cc or --sc modes. --MP When creating .d dependency files with --MMD, make phony targets. Similar to gcc -MP option. --Mdir *directory* Specifies the name of the Make object directory. All generated files will be placed in this directory. If not specified, "obj_dir" is used. The directory is created if it does not exist and the parent directories exist; otherwise manually create the Mdir before calling Verilator. --mod-prefix *topname* Specifies the name to prepend to all lower level classes. Defaults to the same as --prefix. --no-clk *signal-name* Prevent the specified signal from being marked as clock. See "--clk". --no-decoration When creating output Verilated code, minimize comments, white space, symbol names and other decorative items, at the cost of greatly reduced readability. This may assist C++ compile times. This will not typically change the ultimate model's performance, but may in some cases. --no-pins64 Backward compatible alias for "--pins-bv 33". --no-relative-cfuncs Disable 'this->' references in generated functions, and instead Verilator will generate absolute references starting from 'vlTOPp->'. This prevents V3Combine from merging functions from multiple instances of the same module, so it can grow the instruction stream. This is a work around for old compilers. Don't set this if your C++ compiler supports __restrict__ properly, as GCC 4.5.x and newer do. For older compilers, test if this switch gives you better performance or not. Compilers which don't honor __restrict__ will suspect that 'this->' references and 'vlTOPp->' references may alias, and may write slow code with extra loads and stores to handle the (imaginary) aliasing. Using only 'vlTOPp->' references allows these old compilers to produce tight code. --no-skip-identical =item --skip-identical Rarely needed. Disables or enables skipping execution of Verilator if all source files are identical, and all output files exist with newer dates. By default this option is enabled for --cc or --sc modes only. +notimingchecks Ignored for compatibility with other simulators. -O0 Disables optimization of the model. -O3 Enables slow optimizations for the code Verilator itself generates (as opposed to "-CFLAGS -O3" which effects the C compiler's optimization. -O3 may improve simulation performance at the cost of compile time. This currently sets --inline-mult -1. -O*optimization-letter* Rarely needed. Enables or disables a specific optimizations, with the optimization selected based on the letter passed. A lowercase letter disables an optimization, an upper case letter enables it. This is intended for debugging use only; see the source code for version-dependent mappings of optimizations to -O letters. -o *executable* Specify the name for the final executable built if using --exe. Defaults to the --prefix if not specified. --no-order-clock-delay Rarely needed. Disables a bug fix for ordering of clock enables with delayed assignments. This flag should only be used when suggested by the developers. --output-split *statements* Enables splitting the output .cpp files into multiple outputs. When a C++ file exceeds the specified number of operations, a new file will be created at the next function boundary. In addition, if the total output code size exceeds the specified value, VM_PARALLEL_BUILDS will be set to 1 by default in the generated make files, making parallel compilation possible. Using --output-split should have only a trivial impact on model performance. But can greatly improve C++ compilation speed. The use of *ccache* (set for you if present at configure time) is also more effective with this option. This option is on by default with a value of 20000. To disable, pass with a value of 0. --output-split-cfuncs *statements* Enables splitting functions in the output .cpp files into multiple functions. When a generated function exceeds the specified number of operations, a new function will be created. With --output-split, this will enable the C++ compiler to compile faster, at a small loss in performance that gets worse with decreasing split values. Note that this option is stronger than --output-split in the sense that --output-split will not split inside a function. Defaults to the value of --output-split, unless explicitly specified. --output-split-ctrace *statements* Similar to --output-split-cfuncs, enables splitting trace functions in the output .cpp files into multiple functions. Defaults to the value of --output-split, unless explicitly specified. -P With -E, disable generation of `line markers and blank lines, similar to GCC -P flag. --pins64 Backward compatible alias for "--pins-bv 65". Note that's a 65, not a 64. --pins-bv *width* Specifies SystemC inputs/outputs of greater than or equal to *width* bits wide should use sc_bv's instead of uint32/vluint64_t's. The default is "--pins-bv 65", and the value must be less than or equal to 65. Versions before Verilator 3.671 defaulted to "--pins-bv 33". The more sc_bv is used, the worse for performance. Use the "/*verilator sc_bv*/" attribute to select specific ports to be sc_bv. --pins-sc-uint Specifies SystemC inputs/outputs of greater than 2 bits wide should use sc_uint between 2 and 64. When combined with the "--pins-sc-biguint" combination, it results in sc_uint being used between 2 and 64 and sc_biguint being used between 65 and 512. --pins-sc-biguint Specifies SystemC inputs/outputs of greater than 65 bits wide should use sc_biguint between 65 and 512, and sc_bv from 513 upwards. When combined with the "--pins-sc-uint" combination, it results in sc_uint being used between 2 and 64 and sc_biguint being used between 65 and 512. --pins-uint8 Specifies SystemC inputs/outputs that are smaller than the --pins-bv setting and 8 bits or less should use uint8_t instead of uint32_t. Likewise pins of width 9-16 will use uint16_t instead of uint32_t. --pipe-filter *command* Rarely needed. Verilator will spawn the specified command as a subprocess pipe, to allow the command to perform custom edits on the Verilog code before it reaches Verilator. Before reading each Verilog file, Verilator will pass the file name to the subprocess' stdin with 'read ""'. The filter may then read the file and perform any filtering it desires, and feeds the new file contents back to Verilator on stdout by first emitting a line defining the length in bytes of the filtered output 'Content-Length: ', followed by the new filtered contents. Output to stderr from the filter feeds through to Verilator's stdout and if the filter exits with non-zero status Verilator terminates. See the t/t_pipe_filter test for an example. To debug the output of the filter, try using the -E option to see preprocessed output. --pp-comments With -E, show comments in preprocessor output. --prefix *topname* Specifies the name of the top level class and makefile. Defaults to V prepended to the name of the --top-module switch, or V prepended to the first Verilog filename passed on the command line. --prof-cfuncs Modify the created C++ functions to support profiling. The functions will be minimized to contain one "basic" statement, generally a single always block or wire statement. (Note this will slow down the executable by ~5%.) Furthermore, the function name will be suffixed with the basename of the Verilog module and line number the statement came from. This allows gprof or oprofile reports to be correlated with the original Verilog source statements. See also verilator_profcfunc. --prof-threads Enable gantt chart data collection for threaded builds. Verilator will record the start and end time of each macro-task across a number of calls to eval. (What is a macro-task? See the Verilator internals document.) When profiling is enabled, the simulation runtime will emit a blurb of profiling data in non-human-friendly form. The "verilator_gantt" script will transform this into a nicer visual format and produce some related statistics. --protect-key *key* Specifies the private key for --protect-ids. For best security this key should be 16 or more random bytes, a reasonable secure choice is the output of "verilator --generate-key". Typically, a key would be created by the user once for a given protected design library, then every Verilator run for subsequent versions of that library would be passed the same --protect-key. Thus, if the input Verilog is similar between library versions (Verilator runs), the Verilated code will likewise be mostly similar. If --protect-key is not specified and a key is needed, Verilator will generate a new key for every Verilator run. As the key is not saved, this is best for security, but means every Verilator run will give vastly different output even for identical input, perhaps harming compile times (and certainly thrashing any *ccache*). --protect-ids Hash any private identifiers (variable, module, and assertion block names that are not on the top level) into hashed random-looking identifiers, resulting after compilation in protected library binaries that expose less design information. This hashing uses the provided or default --protect-key, see important details there. Verilator will also create a {prefix}__idmap.xml file which contains the mapping from the hashed identifiers back to the original identifiers. This idmap file is to be kept private, and is to assist mapping any simulation runtime design assertions, coverage, or trace information, which will report the hashed identifiers, back to the original design's identifier names. Using DPI imports/exports is allowed and generally relatively safe in terms of information disclosed, which is limited to the DPI function prototyptes. Use of the VPI is not recommended as many design details may be exposed, and an INSECURE warning will be issued. --protect-lib *name* Produces C++, Verilog wrappers and a Makefile which can in turn produce a DPI library which can be used by Verilator or other simulators along with the corresponding Verilog wrapper. The Makefile will build both a static and dynamic version of the library named lib*name*.a and lib*name*.so respectively. This is done because some simulators require a dynamic library, but the static library is arguably easier to use if possible. --protect-lib implies --protect-ids. This allows for the secure delivery of sensitive IP without the need for encrypted RTL (i.e. IEEE P1735). See examples/make_protect_lib in the distribution for a demonstration of how to build and use the DPI library. When using --protect-lib it is advised to also use "--timescale-override /1fs" to ensure the model has a time resolution that is always compatible with the time precision of the upper instantiating module. --private Opposite of --public. Is the default; this option exists for backwards compatibility. --public This is only for historical debug use. Using it may result in mis-simulation of generated clocks. Declares all signals and modules public. This will turn off signal optimizations as if all signals had a /*verilator public*/ comments and inlining. This will also turn off inlining as if all modules had a /*verilator public_module*/, unless the module specifically enabled it with /*verilator inline_module*/. --public-flat-rw Declares all variables, ports and wires public as if they had /*verilator public_flat_rw @ ()*/ comments. This will make them VPI accessible by their flat name, but not turn off module inlining. This is particularly useful in combination with --vpi. This may also in some rare cases result in mis-simulation of generated clocks. Instead of this global switch, marking only those signals that need public_flat_rw is typically significantly better performing. -pvalue+*name*=*value* Overwrites the given parameter(s) of the toplevel module. See -G for a detailed description. --quiet-exit When exiting due to an error, do not display the "Exiting due to Errors" nor "Command Failed" messages. --relative-includes When a file references an include file, resolve the filename relative to the path of the referencing file, instead of relative to the current directory. --report-unoptflat Extra diagnostics for UNOPTFLAT warnings. This includes for each loop, the 10 widest variables in the loop, and the 10 most fanned out variables in the loop. These are candidates for splitting into multiple variables to break the loop. In addition produces a GraphViz DOT file of the entire strongly connected components within the source associated with each loop. This is produced irrespective of whether --dump-tree is set. Such graphs may help in analyzing the problem, but can be very large indeed. Various commands exist for viewing and manipulating DOT files. For example the *dot* command can be used to convert a DOT file to a PDF for printing. For example: dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot will generate a PDF Vt_unoptflat_simple_2_35_unoptflat.dot.pdf from the DOT file. As an alternative, the *xdot* command can be used to view DOT files interactively: xdot Vt_unoptflat_simple_2_35_unoptflat.dot --rr Run Verilator and record with rr. See: rr-project.org. --savable Enable including save and restore functions in the generated model. The user code must create a VerilatedSerialize or VerilatedDeserialze object then calling the << or >> operators on the generated model and any other data the process needs saved/restored. These functions are not thread safe, and are typically called only by a main thread. For example: void save_model(const char* filenamep) { VerilatedSave os; os.open(filenamep); os << main_time; // user code must save the timestamp, etc os << *topp; } void restore_model(const char* filenamep) { VerilatedRestore os; os.open(filenamep); os >> main_time; os >> *topp; } --sc Specifies SystemC output mode; see also --cc. --stats Creates a dump file with statistics on the design in {prefix}__stats.txt. --stats-vars Creates more detailed statistics, including a list of all the variables by size (plain --stats just gives a count). See --stats, which is implied by this. --structs-packed Converts all unpacked structures to packed structures and issues a UNPACKED warning. Currently this is the default and --no-structs-packed will not work. Specifying this option allows for forward compatibility when a future version of Verilator no longer always packs unpacked structures. -sv Specifies SystemVerilog language features should be enabled; equivalent to "--language 1800-2005". This option is selected by default, it exists for compatibility with other simulators. +systemverilogext+*ext* A synonym for "+1800-2017ext+"*ext*. --threads *threads* --no-threads With --threads 0 or --no-threads, the default, the generated model is not thread safe. With --threads 1, the generated model is single threaded but may run in a multithreaded environment. With --threads N, where N >= 2, the model is generated to run multithreaded on up to N threads. See "MULTITHREADING". --threads-dpi all --threads-dpi none --threads-dpi pure When using --threads, controls which DPI imported tasks and functions are considered thread safe. With --threads-dpi all, enable Verilator to assume all DPI imports are threadsafe, and to use thread-local storage for communication with DPI, potentially improving performance. Any DPI libraries need appropriate mutexes to avoid undefined behavior. With --threads-dpi none, Verilator assume DPI imports are not thread safe, and Verilator will serialize calls to DPI imports by default, potentially harming performance. With --threads-dpi pure, the default, Verilator assumes DPI pure imports are threadsafe, but non-pure DPI imports are not. --threads-max-mtasks *value* Rarely needed. When using --threads, specify the number of mtasks the model is to be partitioned into. If unspecified, Verilator approximates a good value. --timescale *timeunit*/*timeprecision* Sets default timescale, timeunit and timeprecision for when `timescale does not occur in sources. Default is "1ps/1ps" (to match SystemC). This is overridden by "--timescale-override". --timescale-override *timeunit*/*timeprecision* --timescale-override /*timeprecision* Overrides all `timescales in sources. The timeunit may be left empty to specify only to override the timeprecision, e.g. "/1fs". The time precision must be consistent with SystemC's sc_set_time_resolution, or the C++ code instantiating the Verilated module. As 1fs is the finest time precision it may be desirable to always use a precision of 1fs. --top-module *topname* When the input Verilog contains more than one top level module, specifies the name of the Verilog module to become the top level module, and sets the default for --prefix if not explicitly specified. This is not needed with standard designs with only one top. See also the MULTITOP warning section. --trace Adds waveform tracing code to the model using VCD format. This overrides "--trace-fst". Verilator will generate additional {prefix}__Trace*.cpp files that will need to be compiled. In addition verilated_vcd_sc.cpp (for SystemC traces) or verilated_vcd_c.cpp (for both) must be compiled and linked in. If using the Verilator generated Makefiles, these files will be added to the source file lists for you. If you are not using the Verilator Makefiles, you will need to add these to your Makefile manually. Having tracing compiled in may result in some small performance losses, even when tracing is not turned on during model execution. See also "--trace-threads". --trace-coverage With --trace and --coverage-*, enable tracing to include a traced signal for every --coverage-line or --coverage-user inserted coverage point, to assist in debugging coverage items. Note --coverage-toggle does not get additional signals added, as the original signals being toggle-analyzed are already visible. The added signal will be a 32-bit value which will increment on each coverage occurrence. Due to this, this option may greatly increase trace file sizes and reduce simulation speed. --trace-depth *levels* Specify the number of levels deep to enable tracing, for example --trace-level 1 to only see the top level's signals. Defaults to the entire model. Using a small number will decrease visibility, but greatly improve simulation performance and trace file size. --trace-fst Enable FST waveform tracing in the model. This overrides "--trace". See also "--trace-threads". --trace-max-array *depth* Rarely needed. Specify the maximum array depth of a signal that may be traced. Defaults to 32, as tracing large arrays may greatly slow traced simulations. --trace-max-width *width* Rarely needed. Specify the maximum bit width of a signal that may be traced. Defaults to 256, as tracing large vectors may greatly slow traced simulations. --no-trace-params Disable tracing of parameters. --trace-structs Enable tracing to show the name of packed structure, union, and packed array fields, rather than a single combined packed bus. Due to VCD file format constraints this may result in significantly slower trace times and larger trace files. --trace-threads *threads* Enable waveform tracing using separate threads. This is typically faster in simulation runtime but uses more total compute. This option is independent of, and works with, both "--trace" and "--trace-fst". Different trace formats can take advantage of more trace threads to varying degrees. Currently VCD tracing can utilize at most --trace-threads 1, and FST tracing can utilize at most --trace-threads 2. This overrides "--no-threads". --trace-underscore Enable tracing of signals that start with an underscore. Normally, these signals are not output during tracing. See also --coverage-underscore. -U*var* Undefines the given preprocessor symbol. --unroll-count *loops* Rarely needed. Specifies the maximum number of loop iterations that may be unrolled. See also BLKLOOPINIT warning. --unroll-stmts *statements* Rarely needed. Specifies the maximum number of statements in a loop for that loop to be unrolled. See also BLKLOOPINIT warning. --unused-regexp *regexp* Rarely needed. Specifies a simple regexp with * and ? that if a signal name matches will suppress the UNUSED warning. Defaults to "*unused*". Setting it to "" disables matching. -V Shows the verbose version, including configuration information compiled into Verilator. (Similar to perl -V.) See also --getenv. -v *filename* Read the filename as a Verilog library. Any modules in the file may be used to resolve cell instantiations in the top level module, else ignored. Note -v is fairly standard across Verilog tools. --no-verilate When using --build, disable generation of C++/SystemC code, and execute only the build. This can be useful for rebuilding Verilated code produced by a previous invocation of Verilator. +verilog1995ext+*ext* +verilog2001ext+*ext* Synonyms for "+1364-1995ext+"*ext* and "+1364-2001ext+"*ext* respectively --version Displays program version and exits. --vpi Enable use of VPI and linking against the verilated_vpi.cpp files. --waiver-output Generate a waiver file which contains all waiver statements to suppress the warnings emitted during this Verilator run. This in particular is useful as a starting point for solving linter warnings or suppressing them systematically. The generated file is in the Verilator Configuration format, see "CONFIGURATION FILES", and can directly be consumed by Verilator. The standard file extension is .vlt. -Wall Enable all code style warnings, including code style warnings that are normally disabled by default. Equivalent to "-Wwarn-lint -Wwarn-style". Excludes some specialty warnings, i.e. IMPERFECTSCH. -Werror-*message* Promote the specified warning message into an error message. This is generally to discourage users from violating important site-wide rules, for example "-Werror-NOUNOPTFLAT". -Wfuture-*message* Rarely needed. Suppress unknown Verilator comments or warning messages with the given message code. This is used to allow code written with pragmas for a later version of Verilator to run under a older version; add -Wfuture- arguments for each message code or comment that the new version supports which the older version does not support. -Wno-*message* Disable the specified warning/error message. This will override any lint_on directives in the source, i.e. the warning will still not be printed. -Wno-context Disable showing the suspected context of the warning message by quoting the source text at the suspected location. This can be used to appease tools which process the warning messages but may get confused by lines from the original source. -Wno-fatal When warnings are detected, print them, but do not terminate Verilator. Having warning messages in builds is sloppy. It is strongly recommended you cleanup your code, use inline lint_off, or use -Wno-... flags rather than using this option. -Wno-lint Disable all lint related warning messages, and all style warnings. This is equivalent to "-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED -Wno-WIDTH" plus the list shown for Wno-style. It is strongly recommended you cleanup your code rather than using this option, it is only intended to be use when running test-cases of code received from third parties. -Wno-style Disable all code style related warning messages (note by default they are already disabled). This is equivalent to "-Wno-DECLFILENAME -Wno-DEFPARAM -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY -Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED -Wno-VARHIDDEN". -Wpedantic Warn on any construct demanded by IEEE, and disable all Verilator extensions that may interfere with IEEE compliance to the standard defined with --default-language (etc). Similar to GCC's -Wpedantic. Rarely used, and intended only for strict compliance tests. -Wwarn-*message* Enables the specified warning message. -Wwarn-lint Enable all lint related warning messages (note by default they are already enabled), but do not affect style messages. This is equivalent to "-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASEWITHX -Wwarn-CMPCONST -Wwarn-COLONPLUS -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN -Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH". -Wwarn-style Enable all code style related warning messages. This is equivalent to "-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN -Wwarn-UNUSED -Wwarn-VARHIDDEN". --x-assign 0 --x-assign 1 --x-assign fast (default) --x-assign unique Controls the two-state value that is substituted when an explicit X value is encountered in the source. "--x-assign fast", the default, converts all Xs to whatever is best for performance. "--x-assign 0" converts all Xs to 0s, and is also fast. "--x-assign 1" converts all Xs to 1s, this is nearly as fast as 0, but more likely to find reset bugs as active high logic will fire. Using "--x-assign unique" will result in all explicit Xs being replaced by a constant value determined at runtime. The value is determined by calling a function at initialization time. This enables randomization of Xs with different seeds on different executions. This method is the slowest, but safest for finding reset bugs. If using --x-assign unique, you may want to seed your random number generator such that each regression run gets a different randomization sequence. The simplest is to use the +verilator+seed runtime option. Alternatively use the system's srand48() or for Windows srand() function to do this. You'll probably also want to print any seeds selected, and code to enable rerunning with that same seed so you can reproduce bugs. Note. This option applies only to values which are explicitly written as X in the Verilog source code. Initial values of clocks are set to 0 unless --x-initial-edge is specified. Initial values of all other state holding variables are controlled with --x-initial. --x-initial 0 --x-initial fast --x-initial unique (default) Controls the two-state value that is used to initialize variables that are not otherwise initialized. "--x-initial 0", initializes all otherwise uninitialized variables to zero. "--x-initial unique", the default, initializes variables using a function, which determines the value to use each initialization. This gives greatest flexibility and allows finding reset bugs. See "Unknown states". "--x-initial fast", is best for performance, and initializes all variables to a state Verilator determines is optimal. This may allow further code optimizations, but will likely hide any code bugs relating to missing resets. Note. This option applies only to initial values of variables. Initial values of clocks are set to 0 unless --x-initial-edge is specified. --x-initial-edge Enables emulation of event driven simulators which generally trigger an edge on a transition from X to 1 ("posedge") or X to 0 ("negedge"). Thus the following code, where "rst_n" is uninitialized would set "res_n" to "1'b1" when "rst_n" is first set to zero: reg res_n = 1'b0; always @(negedge rst_n) begin if (rst_n == 1'b0) begin res_n <= 1'b1; end end In Verilator, by default, uninitialized clocks are given a value of zero, so the above "always" block would not trigger. While it is not good practice, there are some designs that rely on X → 0 triggering a "negedge", particularly in reset sequences. Using --x-initial-edge with Verilator will replicate this behavior. It will also ensure that X → 1 triggers a "posedge". Note. Some users have reported that using this option can affect convergence, and that it may be necessary to use --converge-limit to increase the number of convergence iterations. This may be another indication of problems with the modeled design that should be addressed. --xml-only Create XML output only, do not create any other output. The XML format is intended to be used to leverage Verilator's parser and elaboration to feed to other downstream tools. Be aware that the XML format is still evolving; there will be some changes in future versions. --xml-output *filename* Filename for XML output file. Using this option automatically sets --xml-only. -y *dir* Add the directory to the list of directories that should be searched for include files or libraries. The three flags -y, +incdir and -I have similar effect; +incdir and +y are fairly standard across Verilog tools while -I is used by many C++ compilers. Verilator defaults to the current directory ("-y .") and any specified --Mdir, though these default paths are used after any user specified directories. This allows '-y "$(pwd)"' to be used if absolute filenames are desired for error messages instead of relative filenames. SIMULATION RUNTIME ARGUMENTS The following are the arguments that may be passed to a Verilated executable, provided that executable calls Verilated::commandArgs(). All simulation runtime arguments begin with +verilator, so that the user's executable may skip over all +verilator arguments when parsing its command line. +verilator+debug Enable simulation runtime debugging. Equivalent to +verilator+debugi+4. +verilator+debugi+*value* Enable simulation runtime debugging at the provided level. +verilator+error+limit+*value* Set number of non-fatal errors (e.g. assertion failures) before exiting simulation runtime. Also affects number of $stop calls needed before exit. Defaults to 1. +verilator+help Display help and exit. +verilator+prof+threads+file+*filename* When a model was Verilated using --prof-threads, sets the simulation runtime filename to dump to. Defaults to "profile_threads.dat". +verilator+prof+threads+start+*value* When a model was Verilated using --prof-threads, the simulation runtime will wait until $time is at this value (expressed in units of the time precision), then start the profiling warmup, then capturing. Generally this should be set to some time that is well within the normal operation of the simulation, i.e. outside of reset. If 0, the dump is disabled. Defaults to 1. +verilator+prof+threads+window+*value* When a model was Verilated using --prof-threads, after $time reaches +verilator+prof+threads+start, Verilator will warm up the profiling for this number of eval() calls, then will capture the profiling of this number of eval() calls. Defaults to 2, which makes sense for a single-clock-domain module where it's typical to want to capture one posedge eval() and one negedge eval(). +verilator+rand+reset+*value* When a model was Verilated using "-x-initial unique", sets the simulation runtime initialization technique. 0 = Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See "Unknown states". +verilator+seed+*value* For $random and "-x-initial unique", set the simulation runtime random seed value. If zero or not specified picks a value from the system random number generator. +verilator+noassert Disable assert checking per runtime argument. This is the same as calling "Verilated::assertOn(false)" in the model. +verilator+V Shows the verbose version, including configuration information. +verilator+version Displays program version and exits. EXAMPLE C++ EXECUTION We'll compile this example into C++. mkdir test_our cd test_our cat >our.v <<'EOF' module our; initial begin $display("Hello World"); $finish; end endmodule EOF cat >sim_main.cpp <<'EOF' #include "Vour.h" #include "verilated.h" int main(int argc, char** argv, char** env) { Verilated::commandArgs(argc, argv); Vour* top = new Vour; while (!Verilated::gotFinish()) { top->eval(); } delete top; exit(0); } EOF See the README in the source kit for various ways to install or point to Verilator binaries. In brief, if you installed Verilator using the package manager of your operating system, or did a "make install" to place Verilator into your default path, you do not need anything special in your environment, and should not have VERILATOR_ROOT set. However, if you installed Verilator from sources and want to run Verilator out of where you compiled Verilator, you need to point to the kit: # See above; don't do this if using an OS-distributed Verilator export VERILATOR_ROOT=/path/to/where/verilator/was/installed export PATH=$VERILATOR_ROOT/bin:$PATH Now we run Verilator on our little example. verilator -Wall --cc our.v --exe --build sim_main.cpp We can see the source code under the "obj_dir" directory. See the FILES section below for descriptions of some of the files that were created. ls -l obj_dir (Verilator included a default compile rule and link rule, since we used --exe and passed a .cpp file on the Verilator command line. Verilator also then used "make" to build a final executable. You can also write your own compile rules, and run make yourself as we'll show in the SYSTEMC section.) And now we run it obj_dir/Vour And we get as output Hello World - our.v:2: Verilog $finish Really, you're better off writing a Makefile to do all this for you. Then, when your source changes it will automatically run all of these steps; to aid this Verilator can create a makefile dependency file. See the examples directory in the distribution. EXAMPLE SYSTEMC EXECUTION This is an example similar to the above, but using SystemC. mkdir test_our_sc cd test_our_sc cat >our.v <<'EOF' module our (clk); input clk; // Clock is required to get initial activation always @ (posedge clk) begin $display("Hello World"); $finish; end endmodule EOF cat >sc_main.cpp <<'EOF' #include "Vour.h" int sc_main(int argc, char** argv) { Verilated::commandArgs(argc, argv); sc_clock clk ("clk", 10, 0.5, 3, true); Vour* top; top = new Vour("top"); top->clk(clk); while (!Verilated::gotFinish()) { sc_start(1, SC_NS); } delete top; exit(0); } EOF See the README in the source kit for various ways to install or point to Verilator binaries. In brief, if you installed Verilator using the package manager of your operating system, or did a "make install" to place Verilator into your default path, you do not need anything special in your environment, and should not have VERILATOR_ROOT set. However, if you installed Verilator from sources and want to run Verilator out of where you compiled Verilator, you need to point to the kit: # See above; don't do this if using an OS-distributed Verilator export VERILATOR_ROOT=/path/to/where/verilator/was/installed export PATH=$VERILATOR_ROOT/bin:$PATH Now we run Verilator on our little example. verilator -Wall --sc our.v We then can compile it make -j -C obj_dir -f Vour.mk Vour__ALL.a make -j -C obj_dir -f Vour.mk ../sc_main.o verilated.o And link with SystemC. Note your path to the libraries may vary, depending on the operating system. cd obj_dir export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH # Might be needed if SystemC 2.3.0 export SYSTEMC_CXX_FLAGS=-pthread g++ -L$SYSTEMC_LIBDIR ../sc_main.o Vour__ALL.a verilated.o \ -o Vour -lsystemc And now we run it cd .. obj_dir/Vour And we get the same output as the C++ example: Hello World - our.v:2: Verilog $finish Really, you're better off using a Makefile to do all this for you. Then, when your source changes it will automatically run all of these steps. See the examples directory in the distribution. EVALUATION LOOP When using SystemC, evaluation of the Verilated model is managed by the SystemC kernel, and for the most part can be ignored. When using C++, the user must call eval(), or eval_step() and eval_end_step(). 1. When there is a single design instantiated at the C++ level that needs to evaluate, just call designp->eval(). 2. When there are multiple designs instantiated at the C++ level that need to evaluate, call first_designp->eval_step() then ->eval_step() on all other designs. Then call ->eval_end_step() on the first design then all other designs. If there is only a single design, you would call eval_step() then eval_end_step(); in fact eval() described above is just a wrapper which calls these two functions. When eval() is called Verilator looks for changes in clock signals and evaluates related sequential always blocks, such as computing always_ff @ (posedge...) outputs. Then Verilator evaluates combinatorial logic. Note combinatorial logic is not computed before sequential always blocks are computed (for speed reasons). Therefore it is best to set any non-clock inputs up with a separate eval() call before changing clocks. Alternatively, if all always_ff statements use only the posedge of clocks, or all inputs go directly to always_ff statements, as is typical, then you can change non-clock inputs on the negative edge of the input clock, which will be faster as there will be fewer eval() calls. For more information on evaluation, see docs/internals.adoc in the distribution. BENCHMARKING & OPTIMIZATION For best performance, run Verilator with the "-O3 --x-assign fast --x-initial fast --noassert" flags. The -O3 flag will require longer time to run Verilator, and "--x-assign fast --x-initial fast" may increase the risk of reset bugs in trade for performance; see the above documentation for these flags. If using Verilated multithreaded, use "numactl" to ensure you are using non-conflicting hardware resources. See "MULTITHREADING". Minor Verilog code changes can also give big wins. You should not have any UNOPTFLAT warnings from Verilator. Fixing these warnings can result in huge improvements; one user fixed their one UNOPTFLAT warning by making a simple change to a clock latch used to gate clocks and gained a 60% performance improvement. Beyond that, the performance of a Verilated model depends mostly on your C++ compiler and size of your CPU's caches. Experience shows that large models are often limited by the size of the instruction cache, and as such reducing code size if possible can be beneficial. The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT, OPT_FAST, OPT_SLOW and OPT_GLOBAL variables to control optimization. You can set these when compiling the output of Verilator with Make, for example: make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a OPT_FAST specifies optimization flags for those parts of the model that are on the fast path. This is mostly code that is executed every cycle. OPT_SLOW applies to slow-path code, which executes rarely, often only once at the beginning or end of simulation. Note that OPT_SLOW is ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code will be compiled in a single compilation unit using OPT_FAST. See also the "--output-split" option. The OPT_GLOBAL variable applies to common code in the runtime library used by Verilated models (shipped in $VERILATOR_ROOT/include). Additional C++ files passed on the verilator command line use OPT_FAST. The OPT variable applies to all compilation units in addition to the specific OPT_* variables described above. You can also use the -CFLAGS and/or -LDFLAGS options on the verilator command line to pass flags directly to the compiler or linker. The default values of the OPT_* variables are chosen to yield good simulation speed with reasonable C++ compilation times. To this end, OPT_FAST is set to "-Os" by default. Higher optimization such as "-O2" or "-O3" may help (though often they provide only a very small performance benefit), but compile times may be excessively large even with medium sized designs. Compilation times can be improved at the expense of simulation speed by reducing optimization, for example with OPT_FAST="-O0". Often good simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing" but with improved compilation times. Files controlled by OPT_SLOW have little effect on performance and therefore OPT_SLOW is empty by default (equivalent to "-O0") for improved compilation speed. In common use-cases there should be little benefit in changing OPT_SLOW. OPT_GLOBAL is set to "-Os" by default and there should rarely be a need to change it. As the runtime library is small in comparison to a lot of Verilated models, disabling optimization on the runtime library should not have a serious effect on overall compilation time, but may have detrimental effect on simulation speed, especially with tracing. In addition to the above, for best results use OPT="-march=native", the latest Clang compiler (about 10% faster than GCC), and link statically. Generally the answer to which optimization level gives the best user experience depends on the use case and some experimentation can pay dividends. For a speedy debug cycle during development, especially on large designs where C++ compilation speed can dominate, consider using lower optimization to get to an executable faster. For throughput oriented use cases, for example regressions, it is usually worth spending extra compilation time to reduce total CPU time. If you will be running many simulations on a single model, you can investigate profile guided optimization. With GCC, using -fprofile-arcs, then -fbranch-probabilities will yield another 15% or so. Modern compilers also support link-time optimization (LTO), which can help especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in both compilation and link. Note LTO may cause excessive compile times on large designs. Unfortunately, using the optimizer with SystemC files can result in compilation taking several minutes. (The SystemC libraries have many little inlined functions that drive the compiler nuts.) If you are using your own makefiles, you may want to compile the Verilated code with -DVL_INLINE_OPT=inline. This will inline functions, however this requires that all cpp files be compiled in a single compiler run. You may uncover further tuning possibilities by profiling the Verilog code. Use Verilator's --prof-cfuncs, then GCC's -g -pg. You can then run either oprofile or gprof to see where in the C++ code the time is spent. Run the gprof output through verilator_profcfunc and it will tell you what Verilog line numbers on which most of the time is being spent. When done, please let the author know the results. We like to keep tabs on how Verilator compares, and may be able to suggest additional improvements. FILES All output files are placed in the output directory specified with the "--Mdir" option, or "obj_dir" if not specified. Verilator creates the following files in the output directory: For --make gmake, it creates: {prefix}.mk // Make include file for compiling {prefix}_classes.mk // Make include file with class names For --make cmake, it creates: {prefix}.cmake // CMake include script for compiling For -cc and -sc mode, it also creates: {prefix}.cpp // Top level C++ file {prefix}.h // Top level header {prefix}__Slow{__n}.cpp // Constructors and infrequent cold routines {prefix}{__n}.cpp // Additional top C++ files (--output-split) {prefix}{each_verilog_module}.cpp // Lower level internal C++ files {prefix}{each_verilog_module}.h // Lower level internal header files {prefix}{each_verilog_module}{__n}.cpp // Additional lower C++ files (--output-split) In certain debug and other modes, it also creates: {prefix}.xml // XML tree information (--xml) {prefix}__Dpi.cpp // DPI import and export wrappers {prefix}__Dpi.h // DPI import and export declarations {prefix}__Inlines.h // Inline support functions {prefix}__Syms.cpp // Global symbol table C++ {prefix}__Syms.h // Global symbol table header {prefix}__Trace__Slow{__n}.cpp // Wave file generation code (--trace) {prefix}__Trace{__n}.cpp // Wave file generation code (--trace) {prefix}__cdc.txt // Clock Domain Crossing checks (--cdc) {prefix}__stats.txt // Statistics (--stats) {prefix}__idmap.txt // Symbol demangling (--protect-ids) It also creates internal files that can be mostly ignored: {mod_prefix}_{each_verilog_module}{__n}.vpp // Pre-processed verilog {prefix}__ver.d // Make dependencies (-MMD) {prefix}__verFiles.dat // Timestamps for skip-identical {prefix}{misc}.dot // Debugging graph files (--debug) {prefix}{misc}.tree // Debugging files (--debug) After running Make, the C++ compiler may produce the following: verilated{misc}.d // Intermediate dependencies verilated{misc}.o // Intermediate objects {mod_prefix}{misc}.d // Intermediate dependencies {mod_prefix}{misc}.o // Intermediate objects {prefix} // Final executable (w/--exe argument) {prefix}__ALL.a // Library of all Verilated objects {prefix}__ALL.cpp // Include of all code for single compile {prefix}{misc}.d // Intermediate dependencies {prefix}{misc}.o // Intermediate objects ENVIRONMENT LD_LIBRARY_PATH A generic Linux/OS variable specifying what directories have shared object (.so) files. This path should include SystemC and any other shared objects needed at simulation runtime. MAKE Names the executable of the make command invoked when using the --build option. Some operating systems may require "gmake" to this variable to launch GNU make. If this variable is not specified, "make" is used. OBJCACHE Optionally specifies a caching or distribution program to place in front of all runs of the C++ compiler. For example, "ccache". If using distcc or icecc/icecream, they would generally be run under cache; see the documentation for those programs. If OBJCACHE is not set, and at configure time ccache was present, ccache will be used as a default. SYSTEMC Deprecated. Used only if SYSTEMC_INCLUDE or SYSTEMC_LIBDIR is not set. If set, specifies the directory containing the SystemC distribution. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled). SYSTEMC_ARCH Deprecated. Used only if SYSTEMC_LIBDIR is not set. Specifies the architecture name used by the SystemC kit. This is the part after the dash in the lib-{...} directory name created by a 'make' in the SystemC distribution. If not set, Verilator will try to intuit the proper setting, or use the default optionally specified at configure time (before Verilator was compiled). SYSTEMC_CXX_FLAGS Specifies additional flags that are required to be passed to GCC when building the SystemC model. System 2.3.0 may need this set to "-pthread". SYSTEMC_INCLUDE If set, specifies the directory containing the systemc.h header file. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled), or computed from SYSTEMC/include. SYSTEMC_LIBDIR If set, specifies the directory containing the libsystemc.a library. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled), or computed from SYSTEMC/lib-SYSTEMC_ARCH. VERILATOR_BIN If set, specifies an alternative name of the "verilator" binary. May be used for debugging and selecting between multiple operating system builds. VERILATOR_COVERAGE_BIN If set, specifies an alternative name of the "verilator_coverage binary". May be used for debugging and selecting between multiple operating system builds. VERILATOR_GDB If set, the command to run when using the --gdb option, such as "ddd". If not specified, it will use "gdb". VERILATOR_ROOT Specifies the directory containing the distribution kit. This is used to find the executable, Perl library, and include files. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled). It should not be specified if using a pre-compiled Verilator package as the hard-coded value should be correct. CONNECTING TO C++ Verilator creates a *prefix*.h and *prefix*.cpp file for the top level module, together with additional .h and .cpp files for internals. See the examples directory in the kit for examples. After the model is created, there will be a *prefix*.mk file that may be used with Make to produce a *prefix*__ALL.a file with all required objects in it. This is then linked with the user's C++ main loop to create the simulation executable. The user must write the C++ main loop of the simulation. Here is a simple example: #include // Defines common routines #include // Need std::cout #include "Vtop.h" // From Verilating "top.v" Vtop *top; // Instantiation of module vluint64_t main_time = 0; // Current simulation time // This is a 64-bit integer to reduce wrap over issues and // allow modulus. This is in units of the timeprecision // used in Verilog (or from --timescale-override) double sc_time_stamp () { // Called by $time in Verilog return main_time; // converts to double, to match // what SystemC does } int main(int argc, char** argv) { Verilated::commandArgs(argc, argv); // Remember args top = new Vtop; // Create instance top->reset_l = 0; // Set some inputs while (!Verilated::gotFinish()) { if (main_time > 10) { top->reset_l = 1; // Deassert reset } if ((main_time % 10) == 1) { top->clk = 1; // Toggle clock } if ((main_time % 10) == 6) { top->clk = 0; } top->eval(); // Evaluate model cout << top->out << endl; // Read a output main_time++; // Time passes... } top->final(); // Done simulating // // (Though this example doesn't get here) delete top; } Note signals are read and written as member variables of the model. You call the eval() method to evaluate the model. When the simulation is complete call the final() method to execute any SystemVerilog final blocks, and complete any assertions. See "EVALUATION LOOP". CONNECTING TO SYSTEMC Verilator will convert the top level module to a SC_MODULE. This module will plug directly into a SystemC netlist. The SC_MODULE gets the same pinout as the Verilog module, with the following type conversions: Pins of a single bit become bool. Pins 2-32 bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or vluint64_t's depending on the --no-pins64 switch. Wider pins become sc_bv's. (Uints simulate the fastest so are used where possible.) Lower modules are not pure SystemC code. This is a feature, as using the SystemC pin interconnect scheme everywhere would reduce performance by an order of magnitude. DIRECT PROGRAMMING INTERFACE (DPI) Verilator supports SystemVerilog Direct Programming Interface import and export statements. Only the SystemVerilog form ("DPI-C") is supported, not the original Synopsys-only DPI. DPI Example In the SYSTEMC example above, if you wanted to import C++ functions into Verilog, put in our.v: import "DPI-C" function int add (input int a, input int b); initial begin $display("%x + %x = %x", 1, 2, add(1,2)); endtask Then after Verilating, Verilator will create a file Vour__Dpi.h with the prototype to call this function: extern int add (int a, int b); From the sc_main.cpp file (or another .cpp file passed to the Verilator command line, or the link), you'd then: #include "svdpi.h" #include "Vour__Dpi.h" int add(int a, int b) { return a+b; } DPI System Task/Functions Verilator extends the DPI format to allow using the same scheme to efficiently add system functions. Simply use a dollar-sign prefixed system function name for the import, but note it must be escaped. export "DPI-C" function integer \$myRand; initial $display("myRand=%d", $myRand()); Going the other direction, you can export Verilog tasks so they can be called from C++: export "DPI-C" task publicSetBool; task publicSetBool; input bit in_bool; var_bool = in_bool; endtask Then after Verilating, Verilator will create a file Vour__Dpi.h with the prototype to call this function: extern void publicSetBool(svBit in_bool); From the sc_main.cpp file, you'd then: #include "Vour__Dpi.h" publicSetBool(value); Or, alternatively, call the function under the design class. This isn't DPI compatible but is easier to read and better supports multiple designs. #include "Vour__Dpi.h" Vour::publicSetBool(value); // or top->publicSetBool(value); Note that if the DPI task or function accesses any register or net within the RTL, it will require a scope to be set. This can be done using the standard functions within svdpi.h, after the module is instantiated, but before the task(s) and/or function(s) are called. For example, if the top level module is instantiated with the name "dut" and the name references within tasks are all hierarchical (dotted) names with respect to that top level module, then the scope could be set with #include "svdpi.h" ... svSetScope(svGetScopeFromName("TOP.dut")); (Remember that Verilator adds a "TOP" to the top of the module hierarchy.) Scope can also be set from within a DPI imported C function that has been called from Verilog by querying the scope of that function. See the sections on DPI Context Functions and DPI Header Isolation below and the comments within the svdpi.h header for more information. DPI Display Functions Verilator allows writing $display like functions using this syntax: import "DPI-C" function void \$my_display(input string formatted /*verilator sformat*/ ); The /*verilator sformat*/ indicates that this function accepts a $display like format specifier followed by any number of arguments to satisfy the format. DPI Context Functions Verilator supports IEEE DPI Context Functions. Context imports pass the simulator context, including calling scope name, and filename and line number to the C code. For example, in Verilog: import "DPI-C" context function int dpic_line(); initial $display("This is line %d, again, line %d\n", `line, dpic_line()); This will call C++ code which may then use the svGet* functions to read information, in this case the line number of the Verilog statement that invoked the dpic_line function: int dpic_line() { // Get a scope: svScope scope = svGetScope(); const char* scopenamep = svGetNameFromScope(scope); assert(scopenamep); const char* filenamep = ""; int lineno = 0; if (svGetCallerInfo(&filenamep, &lineno)) { printf("dpic_line called from scope %s on line %d\n", scopenamep, lineno); return lineno; } else { return 0; } } See the IEEE Standard for more information. DPI Header Isolation Verilator places the IEEE standard header files such as svdpi.h into a separate include directory, vltstd (VeriLaTor STandarD). When compiling most applications $VERILATOR_ROOT/include/vltstd would be in the include path along with the normal $VERILATOR_ROOT/include. However, when compiling Verilated models into other simulators which have their own svdpi.h and similar standard files with different contents, the vltstd directory should not be included to prevent picking up incompatible definitions. Public Functions Instead of DPI exporting, there's also Verilator public functions, which are slightly faster, but less compatible. VERIFICATION PROCEDURAL INTERFACE (VPI) Verilator supports a very limited subset of the VPI. This subset allows inspection, examination, value change callbacks, and depositing of values to public signals only. VPI is enabled with the verilator --vpi switch. To access signals via the VPI, Verilator must be told exactly which signals are to be accessed. This is done using the Verilator public pragmas documented below. Verilator has an important difference from an event based simulator; signal values that are changed by the VPI will not immediately propagate their values, instead the top level header file's eval() method must be called. Normally this would be part of the normal evaluation (i.e. the next clock edge), not as part of the value change. This makes the performance of VPI routines extremely fast compared to event based simulators, but can confuse some test-benches that expect immediate propagation. Note the VPI by its specified implementation will always be much slower than accessing the Verilator values by direct reference (structure->module->signame), as the VPI accessors perform lookup in functions at simulation runtime requiring at best hundreds of instructions, while the direct references are evaluated by the compiler and result in only a couple of instructions. For signal callbacks to work the main loop of the program must call VerilatedVpi::callValueCbs(). VPI Example In the below example, we have readme marked read-only, and writeme which if written from outside the model will have the same semantics as if it changed on the specified clock edge. cat >our.v <<'EOF' module our (input clk); reg readme /*verilator public_flat_rd*/; reg writeme /*verilator public_flat_rw @(posedge clk) */; initial $finish; endmodule EOF There are many online tutorials and books on the VPI, but an example that accesses the above signal "readme" would be: cat >sim_main.cpp <<'<eval(); VerilatedVpi::callValueCbs(); // For signal callbacks read_and_check(); } delete top; exit(0); } EOF CROSS COMPILATION Verilator supports cross-compiling Verilated code. This is generally used to run Verilator on a Linux system and produce C++ code that is then compiled on Windows. Cross compilation involves up to three different OSes. The build system is where you configured and compiled Verilator, the host system where you run Verilator, and the target system where you compile the Verilated code and run the simulation. Currently, Verilator requires the build and host system type to be the same, though the target system type may be different. To support this, ./configure and make Verilator on the build system. Then, run Verilator on the host system. Finally, the output of Verilator may be compiled on the different target system. To support this, none of the files that Verilator produces will reference any configure generated build-system specific files, such as config.h (which is renamed in Verilator to config_build.h to reduce confusion.) The disadvantage of this approach is that include/verilatedos.h must self-detect the requirements of the target system, rather than using configure. The target system may also require edits to the Makefiles, the simple Makefiles produced by Verilator presume the target system is the same type as the build system. CMake Verilator can be run using CMake, which takes care of both running Verilator and compiling the output. There is a CMake example in the examples/ directory. The following is a minimal CMakeLists.txt that would build the code listed in "EXAMPLE C++ EXECUTION": project(cmake_example) find_package(verilator HINTS $ENV{VERILATOR_ROOT}) add_executable(Vour sim_main.cpp) verilate(Vour SOURCES our.v) find_package will automatically find an installed copy of Verilator, or use a local build if VERILATOR_ROOT is set. It is recommended to use CMake >= 3.12 and the Ninja generator, though other combinations should work. To build with CMake, change to the folder containing CMakeLists.txt and run: mkdir build cd build cmake -GNinja .. ninja Or to build with your system default generator: mkdir build cd build cmake .. cmake --build . If you're building the example you should have an executable to run: ./Vour The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and VERILATOR_BIN to the appropriate values, and also creates a verilate() function. verilate() will automatically create custom commands to run Verilator and add the generated C++ sources to the target specified. verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name] [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE] [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...] [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...]) Lowercase and ... should be replaced with arguments, the uppercase parts delimit the arguments and can be passed in any order, or left out entirely if optional. verilate(target ...) can be called multiple times to add other verilog modules to an executable or library target. When generating Verilated SystemC sources, you should also include the SystemC include directories and link to the SystemC libraries. Verilator's CMake support provides a convenience function to automatically find and link to the SystemC library. It can be used as: verilator_link_systemc(target) where target is the name of your target. The search paths can be configured by setting some variables: - The variables SYSTEMC_INCLUDE and SYSTEMC_LIBDIR to give a direct path to the SystemC include an library path. - SYSTEMC_ROOT to set the installation prefix of an installed SystemC library. - SYSTEMC to set the installation prefix of an installed SystemC library (same as above). - When using Accellera's SystemC with CMake support, a CMake target is available that simplifies the above steps. This will only work if the SystemC installation can be found by CMake. This can be configured by setting the CMAKE_PREFIX_PATH variable during CMake configuration. Don't forget to set the same C++ standard for the Verilated sources as the SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS environment variable. target Name of a target created by add_executable or add_library. SOURCES List of Verilog files to Verilate. Must have at least one file. PREFIX Optional. Sets the Verilator output prefix. Defaults to the name of the first source file with a "V" prepended. Must be unique in each call to verilate(), so this is necessary if you build a module multiple times with different parameters. Must be a valid C++ identifier, i.e. contains no white space and only characters A-Z, a-z, 0-9 or _. TOP_MODULE Optional. Sets the name of the top module. Defaults to the name of the first file in the SOURCES array. TRACE Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS --trace". TRACE_FST Optional. Enables FST tracing if present, equivalent to "VERILATOR_ARGS --trace-fst". SYSTEMC Optional. Enables SystemC mode, defaults to C++ if not specified. COVERAGE Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS --coverage" INCLUDE_DIRS Optional. Sets directories that Verilator searches (same as -y). OPT_SLOW Optional. Set compiler flags for the slow path. You may want to reduce the optimization level to improve compile times with large designs. OPT_FAST Optional. Set compiler flags for the fast path. OPT_GLOBAL Optional. Set compiler flags for the common runtime library used by Verilated models. DIRECTORY Optional. Set the verilator output directory. It is preferable to use the default, which will avoid collisions with other files. VERILATOR_ARGS Optional. Extra arguments to Verilator. Do not specify --Mdir or --prefix here, use DIRECTORY or PREFIX. MULTITHREADING Verilator supports multithreaded simulation models. With --no-threads, the default, the model is not thread safe, and any use of more than one thread calling into one or even different Verilated models may result in unpredictable behavior. This gives the highest single thread performance. With --threads 1, the generated model is single threaded, however the support libraries are multithread safe. This allows different instantiations of model(s) to potentially each be run under a different thread. All threading is the responsibility of the user's C++ testbench. With --threads N, where N is at least 2, the generated model will be designed to run in parallel on N threads. The thread calling eval() provides one of those threads, and the generated model will create and manage the other N-1 threads. It's the client's responsibility not to oversubscribe the available CPU cores. Under CPU oversubscription, the Verilated model should not livelock nor deadlock, however, you can expect performance to be far worse than it would be with proper ratio of threads and CPU cores. The remainder of this section describe behavior with --threads 1 or --threads N (not --no-threads). VL_THREADED is defined when compiling a threaded Verilated module, causing the Verilated support classes become threadsafe. The thread used for constructing a model must be the same thread that calls eval() into the model, this is called the "eval thread". The thread used to perform certain global operations such as saving and tracing must be done by a "main thread". In most cases the eval thread and main thread are the same thread (i.e. the user's top C++ testbench runs on a single thread), but this is not required. The --trace-threads options can be used to produce trace dumps using multiple threads. If --trace-threads is set without --threads, then --trace-threads will imply --threads 1, i.e.: the support libraries will be thread safe. With --trace-threads 0, trace dumps are produced on the main thread. This again gives the highest single thread performance. With --trace-threads N, where N is at least 1, N additional threads will be created and managed by the trace files (e.g.: VerilatedVcdC or VerilatedFstC), to generate the trace dump. The main thread will be released to proceed with execution as soon as possible, though some blocking of the main thread is still necessary while capturing the trace. Different trace formats can utilize a various number of threads. See the --trace-threads option. When running a multithreaded model, the default Linux task scheduler often works against the model, by assuming threads are short lived, and thus often schedules threads using multiple hyperthreads within the same physical core. For best performance use the "numactl" program to (when the threading count fits) select unique physical cores on the same socket. The same applies for --trace-threads as well. As an example, if a model was Verilated with "--threads 4", we consult egrep 'processor|physical id|core id' /proc/cpuinfo To select cores 0, 1, 2, and 3 that are all located on the same socket (0) but different physical cores. (Also useful is "numactl --hardware", or "lscpu" but those doesn't show Hyperthreading cores.) Then we execute numactl -m 0 -C 0,1,2,3 -- verilated_executable_name This will limit memory to socket 0, and threads to cores 0, 1, 2, 3, (presumably on socket 0) optimizing performance. Of course this must be adjusted if you want another simulator using e.g. socket 1, or if you Verilated with a different number of threads. To see what CPUs are actually used, use --prof-threads. Multithreaded Verilog and Library Support $display/$stop/$finish are delayed until the end of an eval() call in order to maintain ordering between threads. This may result in additional tasks completing after the $stop or $finish. If using --coverage, the coverage routines are fully thread safe. If using --dpi, Verilator assumes pure DPI imports are thread safe, balancing performance versus safety. See --threads-dpi. If using --savable, the save/restore classes are not multithreaded and must be called only by the eval thread. If using --sc, the SystemC kernel is not thread safe, therefore the eval thread and main thread must be the same. If using --trace, the tracing classes must be constructed and called from the main thread. If using --vpi, since SystemVerilog VPI was not architected by IEEE to be multithreaded, Verilator requires all VPI calls are only made from the main thread. CONFIGURATION FILES In addition to the command line, warnings and other features may be controlled by configuration files, typically named with the .vlt extension. An example: `verilator_config lint_off -rule WIDTH lint_off -rule CASEX -file "silly_vendor_code.v" This disables WIDTH warnings globally, and CASEX for a specific file. Configuration files are fed through the normal Verilog preprocessor prior to parsing, so `ifdefs, `defines, and comments may be used as if it were normal Verilog code. Note that file or line-specific configuration only applies to files read after the configuration file. It is therefore recommended to pass the configuration file to Verilator as the first file. The grammar of configuration commands is as follows: `verilator_config Take remaining text and treat it as Verilator configuration commands. coverage_on [-file "" [-lines [ - ]]] coverage_off [-file "" [-lines [ - ]]] Enable/disable coverage for the specified filename (or wildcard with '*' or '?', or all files if omitted) and range of line numbers (or all lines if omitted). Often used to ignore an entire module for coverage analysis purposes. lint_on [-rule ] [-file "" [-lines [ - ]]] lint_off [-rule ] [-file "" [-lines [ - ]]] lint_off [-rule ] [-file ""] [-match ""] Enable/disables the specified lint warning, in the specified filename (or wildcard with '*' or '?', or all files if omitted) and range of line numbers (or all lines if omitted). With lint_off using '*' will override any lint_on directives in the source, i.e. the warning will still not be printed. If the -rule is omitted, all lint warnings (see list in -Wno-lint) are enabled/disabled. This will override all later lint warning enables for the specified region. If -match is set the linter warnings are matched against this (wildcard) string and are waived in case they match and iff rule and file (with wildcard) also match. In previous versions -rule was named -msg. The latter is deprecated, but still works with a deprecation info, it may be removed in future versions. tracing_on [-file "" [-lines [ - ]]] tracing_off [-file "" [-lines [ - ]]] Enable/disable waveform tracing for all future signals declared in the specified filename (or wildcard with '*' or '?', or all files if omitted) and range of line numbers (or all lines if omitted). For tracing_off, cells below any module in the files/ranges specified will also not be traced. clock_enable -module "" -var "" Indicate the signal is used to gate a clock, and the user takes responsibility for insuring there are no races related to it. Same as /*verilator clock_enable*/, see "LANGUAGE EXTENSIONS" for more information and an example. clocker -module "" [-task ""] -var "" clocker -module "" [-function ""] -var "" no_clocker -module "" [-task ""] -var "" no_clocker -module "" [-function ""] -var "" Indicate the signal is used as clock or not. This information is used by Verilator to mark the signal as clocker and propagate the clocker attribute automatically to derived signals. See "--clk" for more information. Same as /*verilator clocker*/, see "LANGUAGE EXTENSIONS" for more information. coverage_block_off -module "" -block "" coverage_block_off -file "" -line Specifies the entire begin/end block should be ignored for coverage analysis purposes. Can either be specified as a named block or as a filename and line number. Same as /*verilator coverage_block_off*/, see "LANGUAGE EXTENSIONS" for more information. full_case -file "" -lines parallel_case -file "" -lines Same as "//synopsys full_case" and "//synopsys parallel_case". When these synthesis directives are discovered, Verilator will either formally prove the directive to be true, or failing that, will insert the appropriate code to detect failing cases at simulation runtime and print an "Assertion failed" error message. inline -module "" Specifies the module may be inlined into any modules that use this module. Same as /*verilator inline_module*/, and see that under "LANGUAGE EXTENSIONS" for more information. isolate_assignments -module "" [-task ""] -var "" isolate_assignments -module "" [-function ""] -var "" isolate_assignments -module "" -function "" Used to indicate the assignments to this signal in any blocks should be isolated into new blocks. When there is a large combinatorial block that is resulting in a UNOPTFLAT warning, attaching this to the signal causing a false loop may clear up the problem. Same as /* verilator isolate_assignments */, see "LANGUAGE EXTENSIONS" for more information. no_inline -module "" Specifies the module should not be inlined into any modules that use this module. Same as /*verilator no_inline_module*/, and see that under "LANGUAGE EXTENSIONS" for more information. no_inline [-module ""] -task "" no_inline [-module ""] -function "" Specify the function or task should not be inlined into where it is used. This may reduce the size of the final executable when a task is used a very large number of times. For this flag to work, the task and tasks below it must be pure; they cannot reference any variables outside the task itself. Same as /*verilator no_inline_task*/, see "LANGUAGE EXTENSIONS" for more information. public [-module ""] [-task/-function ""] -var "" public_flat [-module ""] [-task/-function ""] -var "" public_flat_rd [-module ""] [-task/-function ""] -var "" public_flat_rw [-module ""] [-task/-function ""] -var "" "@(edge)" Sets the variable to be public. Same as /*verilator public*/ or /*verilator public_flat*/ etc, see those under "LANGUAGE EXTENSIONS" for more information. sc_bv -module "" [-task ""] -var "" sc_bv -module "" [-function ""] -var "" Sets the port to be of sc_bv<*width*> type, instead of bool, vluint32_t or vluint64_t. Same as /*verilator sc_bv*/, see that under "LANGUAGE EXTENSIONS" for more information. sformat [-module ""] [-task ""] -var "" sformat [-module ""] [-function ""] -var "" Must be applied to the final argument of type "input string" of a function or task to indicate the function or task should pass all remaining arguments through $sformatf. This allows creation of DPI functions with $display like behavior. See the test_regress/t/t_dpi_display.v file for an example. Same as /*verilator sformat*/, see "LANGUAGE EXTENSIONS" for more information. split_var [-module ""] [-task ""] -var "" split_var [-module ""] [-function ""] -var "" Break the variable into multiple pieces typically to resolve UNOPTFLAT performance issues. Typically the variables to attach this to are recommended by Verilator itself, see UNOPTFLAT. Same as /*verilator split_var*/, see "LANGUAGE EXTENSIONS" for more information. LANGUAGE STANDARD SUPPORT Verilog 2001 (IEEE 1364-2001) Support Verilator supports most Verilog 2001 language features. This includes signed numbers, "always @*", generate statements, multidimensional arrays, localparam, and C-style declarations inside port lists. Verilog 2005 (IEEE 1364-2005) Support Verilator supports most Verilog 2005 language features. This includes the `begin_keywords and `end_keywords compiler directives, $clog2, and the uwire keyword. SystemVerilog 2005 (IEEE 1800-2005) Support Verilator supports ==? and !=? operators, ++ and -- in some contexts, $bits, $countbits, $countones, $error, $fatal, $info, $isunknown, $onehot, $onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit, byte, chandle, const, do-while, enum, export, final, import, int, interface, logic, longint, modport, package, program, shortint, struct, time, typedef, union, var, void, priority case/if, and unique case/if. It also supports .name and .* interconnection. Verilator partially supports concurrent assert and cover statements; see the enclosed coverage tests for the syntax which is allowed. SystemVerilog 2012 (IEEE 1800-2012) Support Verilator implements a full SystemVerilog 2012 preprocessor, including function call-like preprocessor defines, default define arguments, `__FILE__, `__LINE__ and `undefineall. Verilator currently has some support for SystemVerilog synthesis constructs. As SystemVerilog features enter common usage they are added; please file a bug if a feature you need is missing. SystemVerilog 2017 (IEEE 1800-2017) Support Verilator supports the 2017 "for" loop constructs, and several minor cleanups made in 1800-2017. Verilog AMS Support Verilator implements a very small subset of Verilog AMS (Verilog Analog and Mixed-Signal Extensions) with the subset corresponding to those VMS keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009 languages. AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS". At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt, string, and wreal. Synthesis Directive Assertion Support With the --assert switch, Verilator reads any "//synopsys full_case" or "//synopsys parallel_case" directives. The same applies to any "//ambit synthesis", "//cadence" or "//pragma" directives of the same form. When these synthesis directives are discovered, Verilator will either formally prove the directive to be true, or failing that, will insert the appropriate code to detect failing cases at simulation runtime and print an "Assertion failed" error message. Verilator likewise also asserts any "unique" or "priority" SystemVerilog keywords on case statement, as well as "unique" on if statements. However, "priority if" is currently simply ignored. LANGUAGE EXTENSIONS The following additional constructs are the extensions Verilator supports on top of standard Verilog code. Using these features outside of comments or `ifdef's may break other tools. `__FILE__ The __FILE__ define expands to the current filename as a string, like C++'s __FILE__. This was incorporated into to the 1800-2009 standard (but supported by Verilator since 2006!) `__LINE__ The __LINE__ define expands to the current filename as a string, like C++'s __LINE__. This was incorporated into to the 1800-2009 standard (but supported by Verilator since 2006!) `error *string* This will report an error when encountered, like C++'s #error. $c(*string*, ...); The string will be embedded directly in the output C++ code at the point where the surrounding Verilog code is compiled. It may either be a standalone statement (with a trailing ; in the string), or a function that returns up to a 32-bit number (without a trailing ;). This can be used to call C++ functions from your Verilog code. String arguments will be put directly into the output C++ code. Expression arguments will have the code to evaluate the expression inserted. Thus to call a C++ function, $c("func(",a,")") will result in 'func(a)' in the output C++ code. For input arguments, rather than hard-coding variable names in the string $c("func(a)"), instead pass the variable as an expression $c("func(",a,")"). This will allow the call to work inside Verilog functions where the variable is flattened out, and also enable other optimizations. If you will be reading or writing any Verilog variables inside the C++ functions, the Verilog signals must be declared with /*verilator public*/. You may also append an arbitrary number to $c, generally the width of the output. [signal_32_bits = $c32("...");] This allows for compatibility with other simulators which require a differently named PLI function name for each different output width. $display, $write, $fdisplay, $fwrite, $sformat, $swrite Format arguments may use C fprintf sizes after the % escape. Per the Verilog standard, %x prints a number with the natural width, and %0x prints a number with minimum width. Verilator extends this so %5x prints 5 digits per the C standard (this is unspecified in Verilog, but was incorporated into the 1800-2009). `coverage_block_off Specifies the entire begin/end block should be ignored for coverage analysis. Must be inside a code block, e.g. within a begin/end pair. Same as /* verilator coverage_block_off */ and "coverage_block_off" in "CONFIGURATION FILES". `systemc_header Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the output .h file's header. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. `systemc_ctor Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the C++ class constructor. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. `systemc_dtor Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the C++ class destructor. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. `systemc_interface Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the C++ class interface. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. `systemc_imp_header Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the header of all files for this C++ class implementation. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. `systemc_implementation Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into a single file of the C++ class implementation. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. If you will be reading or writing any Verilog variables in the C++ functions, the Verilog signals must be declared with /*verilator public*/. See also the public task feature; writing an accessor may result in cleaner code. `SYSTEMVERILOG The SYSTEMVERILOG, SV_COV_START and related standard defines are set by default when --language is 1800-*. `VERILATOR `verilator `verilator3 The VERILATOR, verilator and verilator3 defines are set by default so you may `ifdef around tool specific constructs. `verilator_config Take remaining text up to the next `verilog mode switch and treat it as Verilator configuration commands. `verilog Switch back to processing Verilog code after a `systemc_... mode switch. The Verilog code returns to the last language mode specified with `begin_keywords, or SystemVerilog if none was specified. /*verilator clock_enable*/ Used after a signal declaration to indicate the signal is used to gate a clock, and the user takes responsibility for insuring there are no races related to it. (Typically by adding a latch, and running static timing analysis.) For example: reg enable_r /*verilator clock_enable*/; wire gated_clk = clk & enable_r; always_ff @ (posedge clk) enable_r <= enable_early; The clock_enable attribute will cause the clock gate to be ignored in the scheduling algorithm, sometimes required for correct clock behavior, and always improving performance. It's also a good idea to enable the IMPERFECTSCH warning, to ensure all clock enables are properly recognized. Same as "clock_enable" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator clocker*/ /*verilator no_clocker*/ Used after a signal declaration to indicate the signal is used as clock or not. This information is used by Verilator to mark the signal as clocker and propagate the clocker attribute automatically to derived signals. See "--clk" for more information. Same as "clocker" and "no_clocker" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator coverage_block_off*/ Specifies the entire begin/end block should be ignored for coverage analysis purposes. Same as "coverage_block_off" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator coverage_off*/ Specifies that following lines of code should have coverage disabled. Often used to ignore an entire module for coverage analysis purposes. /*verilator coverage_on*/ Specifies that following lines of code should have coverage re-enabled (if appropriate --coverage flags are passed) after being disabled earlier with /*verilator coverage_off*/. /*verilator inline_module*/ Specifies the module the comment appears in may be inlined into any modules that use this module. This is useful to speed up simulation runtime. Note if using "--public" that signals under inlined submodules will be named *submodule*__DOT__*subsignal* as C++ does not allow "." in signal names. Same as "inline" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator isolate_assignments*/ Used after a signal declaration to indicate the assignments to this signal in any blocks should be isolated into new blocks. When there is a large combinatorial block that is resulting in a UNOPTFLAT warning, attaching this to the signal causing a false loop may clear up the problem. IE, with the following reg splitme /* verilator isolate_assignments*/; // Note the placement of the semicolon above always @* begin if (....) begin splitme = ....; other assignments end end Verilator will internally split the block that assigns to "splitme" into two blocks: It would then internally break it into (sort of): // All assignments excluding those to splitme always @* begin if (....) begin other assignments end end // All assignments to splitme always @* begin if (....) begin splitme = ....; end end Same as "isolate_assignments" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator lint_off *msg**/ Disable the specified warning message for any warnings following the comment. /*verilator lint_on *msg**/ Re-enable the specified warning message for any warnings following the comment. /*verilator lint_restore*/ After a /*verilator lint_save*/, pop the stack containing lint message state. Often this is useful at the bottom of include files. /*verilator lint_save*/ Push the current state of what lint messages are turned on or turned off to a stack. Later meta-comments may then lint_on or lint_off specific messages, then return to the earlier message state by using /*verilator lint_restore*/. For example: // verilator lint_save // verilator lint_off SOME_WARNING ... // code needing SOME_WARNING turned off // verilator lint_restore If SOME_WARNING was on before the lint_off, it will now be restored to on, and if it was off before the lint_off it will remain off. /*verilator no_inline_module*/ Specifies the module the comment appears in should not be inlined into any modules that use this module. Same as "no_inline" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator no_inline_task*/ Used in a function or task variable definition section to specify the function or task should not be inlined into where it is used. This may reduce the size of the final executable when a task is used a very large number of times. For this flag to work, the task and tasks below it must be pure; they cannot reference any variables outside the task itself. Same as "no_inline" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator public*/ (parameter) Used after a parameter declaration to indicate the emitted C code should have the parameter values visible. Due to C++ language restrictions, this may only be used on 64-bit or narrower integral enumerations. parameter [2:0] PARAM /*verilator public*/ = 2'b0; /*verilator public*/ (typedef enum) Used after an enum typedef declaration to indicate the emitted C code should have the enum values visible. Due to C++ language restrictions, this may only be used on 64-bit or narrower integral enumerations. typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/; /*verilator public*/ (variable) Used after an input, output, register, or wire declaration to indicate the signal should be declared so that C code may read or write the value of the signal. This will also declare this module public, otherwise use /*verilator public_flat*/. Instead of using public variables, consider instead making a DPI or public function that accesses the variable. This is nicer as it provides an obvious entry point that is also compatible across simulators. Same as "public" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator public*/ (task/function) Used inside the declaration section of a function or task declaration to indicate the function or task should be made into a C++ function, public to outside callers. Public tasks will be declared as a void C++ function, public functions will get the appropriate non-void (bool, uint32_t, etc) return type. Any input arguments will become C++ arguments to the function. Any output arguments will become C++ reference arguments. Any local registers/integers will become function automatic variables on the stack. Wide variables over 64 bits cannot be function returns, to avoid exposing complexities. However, wide variables can be input/outputs; they will be passed as references to an array of 32-bit numbers. Generally, only the values of stored state (flops) should be written, as the model will NOT notice changes made to variables in these functions. (Same as when a signal is declared public.) You may want to use DPI exports instead, as it's compatible with other simulators. Same as "public" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator public_flat*/ (variable) Used after an input, output, register, or wire declaration to indicate the signal should be declared so that C code may read or write the value of the signal. This will not declare this module public, which means the name of the signal or path to it may change based upon the module inlining which takes place. Same as "public_flat" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator public_flat_rd*/ (variable) Used after an input, output, register, or wire declaration to indicate the signal should be declared public_flat (see above), but read-only. Same as "public_flat_rd" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator public_flat_rw @() */ (variable) Used after an input, output, register, or wire declaration to indicate the signal should be declared public_flat_rd (see above), and also writable, where writes should be considered to have the timing specified by the given sensitivity edge list. Set for all variables, ports and wires using the --public-flat-rw switch. Same as "public_flat_rw" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator public_module*/ Used after a module statement to indicate the module should not be inlined (unless specifically requested) so that C code may access the module. Verilator automatically sets this attribute when the module contains any public signals or `systemc_ directives. Also set for all modules when using the --public switch. Same as "public" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator sc_clock*/ Deprecated. Used after an input declaration to indicate the signal should be declared in SystemC as a sc_clock instead of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 and later do not require clock pins to be sc_clocks and this is no longer needed. /*verilator sc_bv*/ Used after a port declaration. It sets the port to be of sc_bv<*width*> type, instead of bool, vluint32_t or vluint64_t. This may be useful if the port width is parameterized and the instantiating C++ code wants to always have a sc_bv so it can accept any width. In general you should avoid using this attribute when not necessary as with increasing usage of sc_bv the performance decreases significantly. Same as "sc_bv" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator sformat*/ Attached to the final argument of type "input string" of a function or task to indicate the function or task should pass all remaining arguments through $sformatf. This allows creation of DPI functions with $display like behavior. See the test_regress/t/t_dpi_display.v file for an example. Same as "sformat" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator split_var*/ Attached to a variable or a net declaration to break the variable into multiple pieces typically to resolve UNOPTFLAT performance issues. Typically the variables to attach this to are recommended by Verilator itself, see UNOPTFLAT below. For example, Verilator will internally convert a variable with the metacomment such as: logic [7:0] x [0:1] /*verilator split_var*/; To: logic [7:0] x__BRA__0__KET__ /*verilator split_var*/; logic [7:0] x__BRA__1__KET__ /*verilator split_var*/; Note that the generated packed variables retain the split_var metacomment because they may be split into further smaller pieces according to the access patterns. This only supports unpacked arrays, packed arrays, and packed structs of integer types (reg, logic, bit, byte, int...); otherwise if a split was requested but cannot occur a SPLITVAR warning is issued. Splitting large arrays may slow down the Verilation speed, so use this only on variables that require it. Same as "split_var" in configuration files, see "CONFIGURATION FILES" for more information. /*verilator tag */ Attached after a variable or structure member to indicate opaque (to Verilator) text that should be passed through to the XML output as a tag, for use by downstream applications. /*verilator tracing_off*/ Disable waveform tracing for all future signals that are declared in this module, or cells below this module. Often this is placed just after a primitive's module statement, so that the entire module and cells below it are not traced. /*verilator tracing_on*/ Re-enable waveform tracing for all future signals or cells that are declared. LANGUAGE LIMITATIONS There are some limitations and lack of features relative to the major closed-source simulators, by intent. Synthesis Subset Verilator supports the Synthesis subset with other verification constructs being added over time. Verilator also simulates events as Synopsys's Design Compiler would; namely given a block of the form: always @ (x) y = x & z; This will recompute y when there is even a potential for change in x or a change in z, that is when the flops computing x or z evaluate (which is what Design Compiler will synthesize.) A compliant simulator would only calculate y if x changes. We recommend using always_comb to make the code run the same everywhere. Also avoid putting $displays in combo blocks, as they may print multiple times when not desired, even on compliant simulators as event ordering is not specified. Signal Naming To avoid conflicts with C symbol naming, any character in a signal name that is not alphanumeric nor a single underscore will be replaced by __0hh where hh is the hex code of the character. To avoid conflicts with Verilator's internal symbols, any double underscore are replaced with ___05F (5F is the hex code of an underscore.) Bind Verilator only supports "bind" to a target module name, not an instance path. Class Verilator class support is limited but in active development. Verilator supports members, and methods. Verilator does not support class static members, class extend, or class parameters. Dotted cross-hierarchy references Verilator supports dotted references to variables, functions and tasks in different modules. The portion before the dot must have a constant value; for example a[2].b is acceptable, while a[x].b is generally not. References into generated and arrayed instances use the instance names specified in the Verilog standard; arrayed instances are named {cellName}[{instanceNumber}] in Verilog, which becomes {cellname}__BRA__{instanceNumber}__KET__ inside the generated C++ code. Latches Verilator is optimized for edge sensitive (flop based) designs. It will attempt to do the correct thing for latches, but most performance optimizations will be disabled around the latch. Structures and Unions Presently Verilator only supports packed structs and packed unions. Rand and randc tags on members are simply ignored. All structures and unions are represented as a single vector, which means that generating one member of a structure from blocking, and another from non-blocking assignments is unsupported. Time All delays (#) are ignored, as they are in synthesis. Unknown states Verilator is mostly a two state simulator, not a four state simulator. However, it has two features which uncover most initialization bugs (including many that a four state simulator will miss.) Identity comparisons (=== or !==) are converted to standard ==/!= when neither side is a constant. This may make the expression yield a different result compared to a four state simulator. An === comparison to X will always be false, so that Verilog code which checks for uninitialized logic will not fire. Assigning X to a variable will actually assign a constant value as determined by the --x-assign switch. This allows runtime randomization, thus if the value is actually used, the random value should cause downstream errors. Integers also get randomized, even though the Verilog 2001 specification says they initialize to zero. Note however that randomization happens at initialization time and hence during a single simulation run, the same constant (but random) value will be used every time the assignment is executed. All variables, depending on --x-initial setting, are typically randomly initialized using a function. By running several random simulation runs you can determine that reset is working correctly. On the first run, have the function initialize variables to zero. On the second, have it initialize variables to one. On the third and following runs have it initialize them randomly. If the results match, reset works. (Note this is what the hardware will really do.) In practice, just setting all variables to one at startup finds most problems (since typically control signals are active-high). --x-assign applies to variables explicitly initialized or assigned an X. Uninitialized clocks are initialized to zero, while all other state holding variables are initialized to a random value. Event driven simulators will generally trigger an edge on a transition from X to 1 ("posedge") or X to 0 ("negedge"). However, by default, since clocks are initialized to zero, Verilator will not trigger an initial negedge. Some code (particularly for reset) may rely on X->0 triggering an edge. The --x-initial-edge switch enables this behavior. Comparing runs with and without this switch will find such problems. Tri/Inout Verilator converts some simple tristate structures into two state. Pullup, pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are also supported. Simple comparisons with === 1'bz are also supported. An assignment of the form: inout driver; wire driver = (enable) ? output_value : 1'bz; Will be converted to input driver; // Value being driven in from "external" drivers output driver__en; // True if driven from this module output driver__out; // Value being driven from this module External logic will be needed to combine these signals with any external drivers. Tristate drivers are not supported inside functions and tasks; an inout there will be considered a two state variable that is read and written instead of a four state variable. Functions & Tasks All functions and tasks will be inlined (will not become functions in C.) The only support provided is for simple statements in tasks (which may affect global variables). Recursive functions and tasks are not supported. All inputs and outputs are automatic, as if they had the Verilog 2001 "automatic" keyword prepended. (If you don't know what this means, Verilator will do what you probably expect -- what C does. The default behavior of Verilog is different.) Generated Clocks Verilator attempts to deal with generated and gated clocks correctly, however some cases cause problems in the scheduling algorithm which is optimized for performance. The safest option is to have all clocks as primary inputs to the model, or wires directly attached to primary inputs. For proper behavior clock enables may also need the /*verilator clock_enable*/ attribute. Gate Primitives The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are directly converted to behavioral equivalents. The 3-state and MOS gate primitives are not supported. Tables are not supported. Specify blocks All specify blocks and timing checks are ignored. All min:typ:max delays use the typical value. Array Initialization When initializing a large array, you need to use non-delayed assignments. Verilator will tell you when this needs to be fixed; see the BLKLOOPINIT error for more information. Array Out of Bounds Writing a memory element that is outside the bounds specified for the array may cause a different memory element inside the array to be written instead. For power-of-2 sized arrays, Verilator will give a width warning and the address. For non-power-of-2-sizes arrays, index 0 will be written. Reading a memory element that is outside the bounds specified for the array will give a width warning and wrap around the power-of-2 size. For non-power-of-2 sizes, it will return a unspecified constant of the appropriate width. Assertions Verilator is beginning to add support for assertions. Verilator currently only converts assertions to simple "if (...) error" statements, and coverage statements to increment the line counters described in the coverage section. Verilator does not support SEREs yet. All assertion and coverage statements must be simple expressions that complete in one cycle. Encrypted Verilog Open source simulators like Verilator are unable to use encrypted RTL (i.e. IEEE P1735). Talk to your IP vendor about delivering IP blocks via Verilator's --protect-lib feature. Language Keyword Limitations This section describes specific limitations for each language keyword. `__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords, `endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor, `systemc_dtor, `systemc_header, `systemc_imp_header, `systemc_implementation, `systemc_interface, `undef, `verilog Fully supported. always, always_comb, always_ff, always_latch, and, assign, begin, buf, byte, case, casex, casez, default, defparam, do-while, else, end, endcase, endfunction, endgenerate, endmodule, endspecify, endtask, final, for, function, generate, genvar, if, initial, inout, input, int, integer, localparam, logic, longint, macromodule, module, nand, negedge, nor, not, or, output, parameter, posedge, reg, scalared, shortint, signed, supply0, supply1, task, time, tri, typedef, var, vectored, while, wire, xnor, xor Generally supported. ++, -- operators Increment/decrement can only be used as standalone statements or in certain limited cases. '{} operator Assignment patterns with order based, default, constant integer (array) or member identifier (struct/union) keys are supported. Data type keys and keys which are computed from a constant expression are not supported. `uselib Uselib, a vendor specific library specification method, is ignored along with anything following it until the end of that line. cast operator Casting is supported only between simple scalar types, signed and unsigned, not arrays nor structs. chandle Treated as a "longint"; does not yet warn about operations that are specified as illegal on chandles. disable Disable statements may be used only if the block being disabled is a block the disable statement itself is inside. This was commonly used to provide loop break and continue functionality before SystemVerilog added the break and continue keywords. inside Inside expressions may not include unpacked array traversal or $ as an upper bound. Case inside and case matches are also unsupported. interface Interfaces and modports, including with generated data types are supported. Generate blocks around modports are not supported, nor are virtual interfaces nor unnamed interfaces. shortreal Short floating point (shortreal) numbers are converted to real. Most other simulators either do not support float, or convert likewise. specify specparam All specify blocks and timing checks are ignored. uwire Verilator does not perform warning checking on uwires, it treats the uwire keyword as if it were the normal wire keyword. $bits, $countbits, $countones, $error, $fatal, $finish, $info, $isunknown, $onehot, $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, $time, $unsigned, $warning. Generally supported. $dump/$dumpports and related $dumpfile or $dumpports will create a VCD or FST file (which is based on the --trace argument given when the model was Verilated). This will take effect starting at the next eval() call. If you have multiple Verilated designs under the same C model, then this will dump signals only from the design containing the $dumpvars. $dumpvars and $dumpports module identifier is ignored; the traced instances will always start at the top of the design. The levels argument is also ignored, use tracing_on/tracing_off pragmas instead. $dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename argument is ignored, only a single trace file may be active at once. $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and $dumplimit/$dumpportlimit are currently ignored. $finish, $stop The rarely used optional parameter to $finish and $stop is ignored. $fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf Generally supported. $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, $setup, $setuphold, $skew, $timeskew, $width All specify blocks and timing checks are ignored. $monitor, $strobe Monitor and strobe are not supported, convert to always_comb $display or similar. $random $random does not support the optional argument to set the seed. Use the srand function in C to accomplish this, and note there is only one random number generator (not one per module). $readmemb, $readmemh Read memory commands should work properly. Note Verilator and the Verilog specification does not include support for readmem to multi-dimensional arrays. $test$plusargs, $value$plusargs Supported, but the instantiating C++/SystemC testbench must call Verilated::commandArgs(argc, argv); to register the command line before calling $test$plusargs or $value$plusargs. ERRORS AND WARNINGS Warnings may be disabled in three ways. First, when the warning is printed it will include a warning code. Simply surround the offending line with a lint_off/lint_on pair: // verilator lint_off UNSIGNED if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop; // verilator lint_on UNSIGNED Second, warnings may be disabled using a configuration file with a lint_off command. This is useful when a script is suppressing warnings and the Verilog source should not be changed. Warnings may also be globally disabled by invoking Verilator with the "-Wno-*warning*" switch. This should be avoided, as it removes all checking across the designs, and prevents other users from compiling your code without knowing the magic set of disables needed to successfully compile your design. Error and Warning Format Warnings and errors printed by Verilator always match this regular expression: %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.* Errors and warning start with a percent sign (historical heritage from Digital Equipment Corporation). Some errors or warning have a code attached, with meanings described below. Some errors also have a filename, line number and optional column number (starting at column 1 to match GCC). Following the error message, Verilator will typically show the user's source code corresponding to the error, prefixed by the line number and a " | ". Following this is typically an arrow and ~ pointing at the error on the source line directly above. List of all warnings ALWCOMBORDER Warns that an always_comb block has a variable which is set after it is used. This may cause simulation-synthesis mismatches, as not all simulators allow this ordering. always_comb begin a = b; b = 1; end Ignoring this warning will only suppress the lint check, it will simulate correctly. ASSIGNIN Error that an assignment is being made to an input signal. This is almost certainly a mistake, though technically legal. input a; assign a = 1'b1; Ignoring this warning will only suppress the lint check, it will simulate correctly. ASSIGNDLY Warns that you have an assignment statement with a delayed time in front of it, for example: a <= #100 b; assign #100 a = b; Ignoring this warning may make Verilator simulations differ from other simulators, however at one point this was a common style so disabled by default as a code style warning. BLKANDNBLK BLKANDNBLK is an error that a variable comes from a mix of blocking and non-blocking assignments. Generally, this is caused by a register driven by both combo logic and a flop: always @ (posedge clk) foo[0] <= ... always @* foo[1] = ... Simply use a different register for the flop: always @ (posedge clk) foo_flopped[0] <= ... always @* foo[0] = foo_flopped[0]; always @* foo[1] = ... This is not illegal in SystemVerilog, but a violation of good coding practice. Verilator reports this as an error, because ignoring this warning may make Verilator simulations differ from other simulators. It is generally safe to disable this error (with a "// verilator lint_off BLKANDNBLK" metacomment or the -Wno-BLKANDNBLK option) when one of the assignments is inside a public task, or when the blocking and non-blocking assignments have non-overlapping bits and structure members. BLKSEQ This indicates that a blocking assignment (=) is used in a sequential block. Generally non-blocking/delayed assignments (<=) are used in sequential blocks, to avoid the possibility of simulator races. It can be reasonable to do this if the generated signal is used ONLY later in the same block, however this style is generally discouraged as it is error prone. always @ (posedge clk) foo = ... Disabled by default as this is a code style warning; it will simulate correctly. BLKLOOPINIT This indicates that the initialization of an array needs to use non-delayed assignments. This is done in the interest of speed; if delayed assignments were used, the simulator would have to copy large arrays every cycle. (In smaller loops, loop unrolling allows the delayed assignment to work, though it's a bit slower than a non-delayed assignment.) Here's an example always @ (posedge clk) if (~reset_l) begin for (i=0; i<`ARRAY_SIZE; i++) begin array[i] = 0; // Non-delayed for verilator end This message is only seen on large or complicated loops because Verilator generally unrolls small loops. You may want to try increasing --unroll-count (and occasionally --unroll-stmts) which will raise the small loop bar to avoid this error. BOUNDED This indicates that bounded queues (e.g. "var name[$ : 3]") are unsupported. Ignoring this warning may make Verilator simulations differ from other simulators. BSSPACE Warns that a backslash is followed by a space then a newline. Likely the intent was to have a backslash directly followed by a newline (e.g. when making a `define) and there's accidentally white space at the end of the line. If the space is not accidental, suggest removing the backslash in the code as it serves no function. Ignoring this warning will only suppress the lint check, it will simulate correctly. CASEINCOMPLETE Warns that inside a case statement there is a stimulus pattern for which there is no case item specified. This is bad style, if a case is impossible, it's better to have a "default: $stop;" or just "default: ;" so that any design assumption violations will be discovered in simulation. Ignoring this warning will only suppress the lint check, it will simulate correctly. CASEOVERLAP Warns that inside a case statement you have case values which are detected to be overlapping. This is bad style, as moving the order of case values will cause different behavior. Generally the values can be respecified to not overlap. Ignoring this warning will only suppress the lint check, it will simulate correctly. CASEX Warns that it is simply better style to use casez, and "?" in place of "x"'s. See Ignoring this warning will only suppress the lint check, it will simulate correctly. CASEWITHX Warns that a case statement contains a constant with a "x". Verilator is two-state so interpret such items as always false. Note a common error is to use a "X" in a case or casez statement item; often what the user instead intended is to use a casez with "?". Ignoring this warning will only suppress the lint check, it will simulate correctly. CDCRSTLOGIC With --cdc only, warns that asynchronous flop reset terms come from other than primary inputs or flopped outputs, creating the potential for reset glitches. CLKDATA Warns that clock signal is mixed used with/as data signal. The checking for this warning is enabled only if user has explicitly marked some signal as clocker using command line option or in-source meta comment (see "--clk"). The warning can be disabled without affecting the simulation result. But it is recommended to check the warning as this may degrade the performance of the Verilated model. CMPCONST Warns that you are comparing a value in a way that will always be constant. For example "X > 1" will always be true when X is a single bit wide. Ignoring this warning will only suppress the lint check, it will simulate correctly. COLONPLUS Warns that a :+ is seen. Likely the intent was to use +: to select a range of bits. If the intent was a range that is explicitly positive, suggest adding a space, e.g. use ": +". Ignoring this warning will only suppress the lint check, it will simulate correctly. COMBDLY Warns that you have a delayed assignment inside of a combinatorial block. Using delayed assignments in this way is considered bad form, and may lead to the simulator not matching synthesis. If this message is suppressed, Verilator, like synthesis, will convert this to a non-delayed assignment, which may result in logic races or other nasties. See Ignoring this warning may make Verilator simulations differ from other simulators. CONTASSREG Error that a continuous assignment is setting a reg. According to IEEE Verilog, but not SystemVerilog, a wire must be used as the target of continuous assignments. This error is only reported when "--language 1364-1995", "--language 1364-2001", or "--language 1364-2005" is used. Ignoring this error will only suppress the lint check, it will simulate correctly. DECLFILENAME Warns that a module or other declaration's name doesn't match the filename with path and extension stripped that it is declared in. The filename a modules/interfaces/programs is declared in should match the name of the module etc. so that -y directory searching will work. This warning is printed for only the first mismatching module in any given file, and -v library files are ignored. Disabled by default as this is a code style warning; it will simulate correctly. DEFPARAM Warns that the "defparam" statement was deprecated in Verilog 2001 and all designs should now be using the #(...) format to specify parameters. Disabled by default as this is a code style warning; it will simulate correctly. DETECTARRAY Error when Verilator tries to deal with a combinatorial loop that could not be flattened, and which involves a datatype which Verilator cannot handle, such as an unpacked struct or a large unpacked array. This typically occurs when -Wno-UNOPTFLAT has been used to override an UNOPTFLAT warning (see below). The solution is to break the loop, as described for UNOPTFLAT. DIDNOTCONVERGE Error at simulation runtime when model did not properly settle. Verilator sometimes has to evaluate combinatorial logic multiple times, usually around code where a UNOPTFLAT warning was issued, but disabled. For example: always_comb b = ~a; always_comb a = b This code will toggle forever, and thus to prevent an infinite loop, the executable will give the didn't converge error. To debug this, first review any UNOPTFLAT warnings that were ignored. Though typically it is safe to ignore UNOPTFLAT (at a performance cost), at the time of issuing a UNOPTFLAT Verilator did not know if the logic would eventually converge and assumed it would. Next, run Verilator with --prof-cfuncs. Run make on the generated files with "CPP_FLAGS=-DVL_DEBUG", to allow enabling simulation runtime debug messages. Rerun the test. Now just before the convergence error you should see additional output similar to this: CHANGE: filename.v:1: b CHANGE: filename.v:2: a This means that signal b and signal a keep changing, inspect the code that modifies these signals. Note if many signals are getting printed then most likely all of them are oscillating. It may also be that e.g. "a" may be oscillating, then "a" feeds signal "c" which then is also reported as oscillating. Finally, rare, more difficult cases can be debugged like a "C" program; either enter GDB and use its tracing facilities, or edit the generated C++ code to add appropriate prints to see what is going on. ENDLABEL Warns that a label attached to a "end"-something statement does not match the label attached to the block start. Ignoring this warning will only suppress the lint check, it will simulate correctly. GENCLK Deprecated and no longer used as a warning. Used to indicate that the specified signal was is generated inside the model, and also being used as a clock. IFDEPTH Warns that if/if else statements have exceeded the depth specified with --if-depth, as they are likely to result in slow priority encoders. Statements below unique and priority if statements are ignored. Solutions include changing the code to a case statement, or a SystemVerilog 'unique if' or 'priority if'. Disabled by default as this is a code style warning; it will simulate correctly. IGNOREDRETURN Warns that a non-void function is being called as a task, and hence the return value is being ignored. This warning is required by IEEE. The portable way to suppress this warning (in SystemVerilog) is to use a void cast, e.g. void'(function_being_called_as_task()); Ignoring this warning will only suppress the lint check, it will simulate correctly. IMPERFECTSCH Warns that the scheduling of the model is not absolutely perfect, and some manual code edits may result in faster performance. This warning defaults to off, is not part of -Wall, and must be turned on explicitly before the top module statement is processed. IMPLICIT Warns that a wire is being implicitly declared (it is a single bit wide output from a sub-module.) While legal in Verilog, implicit declarations only work for single bit wide signals (not buses), do not allow using a signal before it is implicitly declared by a cell, and can lead to dangling nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for Emacs, available from Ignoring this warning will only suppress the lint check, it will simulate correctly. IMPORTSTAR Warns that an "import *package*::*" statement is in $unit scope. This causes the imported symbols to pollute the global namespace, defeating much of the purpose of having a package. Generally "import ::*" should only be used inside a lower scope such as a package or module. Disabled by default as this is a code style warning; it will simulate correctly. IMPURE Warns that a task or function that has been marked with /*verilator no_inline_task*/ references variables that are not local to the task. Verilator cannot schedule these variables correctly. Ignoring this warning may make Verilator simulations differ from other simulators. INCABSPATH Warns that an `include filename specifies an absolute path. This means the code will not work on any other system with a different file system layout. Instead of using absolute paths, relative paths (preferably without any directory specified whatsoever) should be used, and +incdir used on the command line to specify the top include source directories. Disabled by default as this is a code style warning; it will simulate correctly. INFINITELOOP Warns that a while or for statement has a condition that is always true. and thus results in an infinite loop if the statement ever executes. This might be unintended behavior if the loop body contains statements that in other simulators would make time pass, which Verilator is ignoring due to e.g. STMTDLY warnings being disabled. Ignoring this warning will only suppress the lint check, it will simulate correctly (i.e. hang due to the infinite loop). INITIALDLY Warns that you have a delayed assignment inside of an initial or final block. If this message is suppressed, Verilator will convert this to a non-delayed assignment. See also the COMBDLY warning. Ignoring this warning may make Verilator simulations differ from other simulators. INSECURE Warns that the combination of options selected may be defeating the attempt to protect/obscure identifiers or hide information in the model. Correct the options provided, or inspect the output code to see if the information exposed is acceptable. Ignoring this warning will only suppress the lint check, it will simulate correctly. LITENDIAN Warns that a packed vector is declared with little endian bit numbering (i.e. [0:7]). Big endian bit numbering is now the overwhelming standard, and little numbering is now thus often due to simple oversight instead of intent. Also warns that a cell is declared with little endian range (i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE the bits will likely be backwards from what you expect (i.e. cell [0] will connect to signal bit [N-1] not bit [0]). Ignoring this warning will only suppress the lint check, it will simulate correctly. MODDUP Warns that a module has multiple definitions. Generally this indicates a coding error, or a mistake in a library file and it's good practice to have one module per file (and only put each file once on the command line) to avoid these issues. For some gate level netlists duplicates are sometimes unavoidable, and MODDUP should be disabled. Ignoring this warning will cause the more recent module definition to be discarded. MULTIDRIVEN Warns that the specified signal comes from multiple always blocks. This is often unsupported by synthesis tools, and is considered bad style. It will also cause longer simulation runtimes due to reduced optimizations. Ignoring this warning will only slow simulations, it will simulate correctly. MULTITOP Warns that there are multiple top level modules, that is modules not instantiated by any other module, and both modules were put on the command line (not in a library). Three likely cases: 1. A single module is intended to be the top. This warning then occurs because some low level cell is being read in, but is not really needed as part of the design. The best solution for this situation is to ensure that only the top module is put on the command line without any flags, and all remaining library files are read in as libraries with -v, or are automatically resolved by having filenames that match the module names. 2. A single module is intended to be the top, the name of it is known, and all other modules should be ignored if not part of the design. The best solution is to use the --top-module option to specify the top module's name. All other modules that are not part of the design will be for the most part ignored (they must be clean in syntax and their contents will be removed as part of the Verilog module elaboration process.) 3. Multiple modules are intended to be design tops, e.g. when linting a library file. As multiple modules are desired, disable the MULTITOP warning. All input/outputs will go uniquely to each module, with any conflicting and identical signal names being made unique by adding a prefix based on the top module name followed by __02E (a Verilator-encoded ASCII ".'). This renaming is done even if the two modules' signals seem identical, e.g. multiple modules with a "clk" input. PINCONNECTEMPTY Warns that a cell instantiation has a pin which is connected to .pin_name(), e.g. not another signal, but with an explicit mention of the pin. It may be desirable to disable PINCONNECTEMPTY, as this indicates intention to have a no-connect. Disabled by default as this is a code style warning; it will simulate correctly. PINMISSING Warns that a module has a pin which is not mentioned in a cell instantiation. If a pin is not missing it should still be specified on the cell declaration with a empty connection, using "(.pin_name())". Ignoring this warning will only suppress the lint check, it will simulate correctly. PINNOCONNECT Warns that a cell instantiation has a pin which is not connected to another signal. Disabled by default as this is a code style warning; it will simulate correctly. PROCASSWIRE Error that a procedural assignment is setting a wire. According to IEEE, a var/reg must be used as the target of procedural assignments. REALCVT Warns that a real number is being implicitly rounded to an integer, with possible loss of precision. REDEFMACRO Warns that you have redefined the same macro with a different value, for example: `define MACRO def1 //... `define MACRO otherdef The best solution is to use a different name for the second macro. If this is not possible, add a undef to indicate the code is overriding the value: `define MACRO def1 //... `undef MACRO `define MACRO otherdef SELRANGE Warns that a selection index will go out of bounds: wire vec[6:0]; initial out = vec[7]; // There is no 7 Verilator will assume zero for this value, instead of X. Note that in some cases this warning may be false, when a condition upstream or downstream of the access means the access out of bounds will never execute or be used. wire vec[6:0]; initial begin seven = 7; ... if (seven != 7) out = vec[seven]; // Never will use vec[7] SHORTREAL Warns that Verilator does not support "shortreal" and they will be automatically promoted to "real". The recommendation is to replace any "shortreal" in the code with "real", as "shortreal" is not widely supported across industry tools. Ignoring this warning may make Verilator simulations differ from other simulators, if the increased precision of real affects your model or DPI calls. SPLITVAR Warns that a variable with a "split_var" metacomment was not split. Some possible reasons for this are: * The datatype of the variable is not supported for splitting. (e.g. is a real). * The access pattern of the variable can not be determined statically. (e.g. is accessed as a memory). * The index of the array exceeds the array size. * The variable is accessed from outside using dotted reference. (e.g. top.instance0.variable0 = 1). * The variable is not declared in a module, but in a package or an interface. * The variable is a parameter, localparam, genvar, or queue. * The variable is tristate or bidirectional. (e.g. inout or ref). STMTDLY Warns that you have a statement with a delayed time in front of it, for example: #100 $finish; Ignoring this warning may make Verilator simulations differ from other simulators. SYMRSVDWORD Warning that a symbol matches a C++ reserved word and using this as a symbol name would result in odd C++ compiler errors. You may disable this warning, but the symbol will be renamed by Verilator to avoid the conflict. SYNCASYNCNET Warns that the specified net is used in at least two different always statements with posedge/negedges (i.e. a flop). One usage has the signal in the sensitivity list and body, probably as an async reset, and the other usage has the signal only in the body, probably as a sync reset. Mixing sync and async resets is usually a mistake. The warning may be disabled with a lint_off pragma around the net, or either flopped block. Disabled by default as this is a code style warning; it will simulate correctly. TASKNSVAR Error when a call to a task or function has a output from that task tied to a non-simple signal. Instead connect the task output to a temporary signal of the appropriate width, and use that signal to set the appropriate expression as the next statement. For example: task foo; output sig; ... endtask always @* begin foo(bus_we_select_from[2]); // Will get TASKNSVAR error end Change this to: reg foo_temp_out; always @* begin foo(foo_temp_out); bus_we_select_from[2] = foo_temp_out; end Verilator doesn't do this conversion for you, as some more complicated cases would result in simulator mismatches. TICKCOUNT Warns that the number of ticks to delay a $past variable is greater than 10. At present Verilator effectively creates a flop for each delayed signals, and as such any large counts may lead to large design size increases. Ignoring this warning will only slow simulations, it will simulate correctly. TIMESCALEMOD Error that `timescale is used in some but not all modules. Recommend using --timescale argument, or in front of all modules use: `include "timescale.vh" Then in that file set the timescale. This is an error due to IEEE specifications, but it may be disabled similar to warnings. Ignoring this error may result in a module having an unexpected timescale. UNDRIVEN Warns that the specified signal has no source. Verilator is fairly liberal in the usage calculations; making a signal public, or setting only a single array element marks the entire signal as driven. Disabled by default as this is a code style warning; it will simulate correctly. UNOPT Warns that due to some construct, optimization of the specified signal or block is disabled. The construct should be cleaned up to improve simulation performance. A less obvious case of this is when a module instantiates two submodules. Inside submodule A, signal I is input and signal O is output. Likewise in submodule B, signal O is an input and I is an output. A loop exists and a UNOPT warning will result if AI & AO both come from and go to combinatorial blocks in both submodules, even if they are unrelated always blocks. This affects performance because Verilator would have to evaluate each submodule multiple times to stabilize the signals crossing between the modules. Ignoring this warning will only slow simulations, it will simulate correctly. UNOPTFLAT Warns that due to some construct, optimization of the specified signal is disabled. The signal reported includes a complete scope to the signal; it may be only one particular usage of a multiply instantiated block. The construct should be cleaned up to improve simulation performance; two times better performance may be possible by fixing these warnings. Unlike the UNOPT warning, this occurs after flattening the netlist, and indicates a more basic problem, as the less obvious case described under UNOPT does not apply. Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by synthesis which analyzes interconnection per-bit, but is circular to simulation which analyzes per-bus: wire [2:0] x = {x[1:0], shift_in}; This statement needs to be evaluated multiple times, as a change in "shift_in" requires "x" to be computed 3 times before it becomes stable. This is because a change in "x" requires "x" itself to change value, which causes the warning. For significantly better performance, split this into 2 separate signals: wire [2:0] xout = {x[1:0], shift_in}; and change all receiving logic to instead receive "xout". Alternatively, change it to wire [2:0] x = {xin[1:0], shift_in}; and change all driving logic to instead drive "xin". With this change this assignment needs to be evaluated only once. These sort of changes may also speed up your traditional event driven simulator, as it will result in fewer events per cycle. The most complicated UNOPTFLAT path we've seen was due to low bits of a bus being generated from an always statement that consumed high bits of the same bus processed by another series of always blocks. The fix is the same; split it into two separate signals generated from each block. Another way to resolve this warning is to add a "split_var" metacomment described above. This will cause the variable to be split internally, potentially resolving the conflict. If you run with --report-unoptflat Verilator will suggest possible candidates for "split_var". The UNOPTFLAT warning may also be due to clock enables, identified from the reported path going through a clock gating cell. To fix these, use the clock_enable meta comment described above. The UNOPTFLAT warning may also occur where outputs from a block of logic are independent, but occur in the same always block. To fix this, use the isolate_assignments meta comment described above. To assist in resolving UNOPTFLAT, the option "--report-unoptflat" can be used, which will provide suggestions for variables that can be split up, and a graph of all the nodes connected in the loop. See the Arguments section for more details. Ignoring this warning will only slow simulations, it will simulate correctly. UNOPTTHREADS Warns that the thread scheduler was unable to partition the design to fill the requested number of threads. One workaround is to request fewer threads with "--threads". Another possible workaround is to allow more MTasks in the simulation runtime, by increasing the value of --threads-max-mtasks. More MTasks will result in more communication and synchronization overhead at simulation runtime; the scheduler attempts to minimize the number of MTasks for this reason. Ignoring this warning will only slow simulations, it will simulate correctly. UNPACKED Warns that unpacked structs and unions are not supported. Ignoring this warning will make Verilator treat the structure as packed, which may make Verilator simulations differ from other simulators. This downgrading may also result what would normally be a legal unpacked struct/array inside an unpacked struct/array becoming an illegal unpacked struct/array inside a packed struct/array. UNSIGNED Warns that you are comparing a unsigned value in a way that implies it is signed, for example "X < 0" will always be false when X is unsigned. Ignoring this warning will only suppress the lint check, it will simulate correctly. UNSUPPORTED UNSUPPORTED is an error that the construct might be legal according to IEEE but is not currently supported. This error may be ignored with --bbox-unsup, however this will make the design simulate incorrectly; see the details under --bbox-unsup. UNUSED Warns that the specified signal is never used/consumed. Verilator is fairly liberal in the usage calculations; making a signal public, a signal matching --unused-regexp ("*unused*") or accessing only a single array element marks the entire signal as used. Disabled by default as this is a code style warning; it will simulate correctly. A recommended style for unused nets is to put at the bottom of a file code similar to the following: wire _unused_ok = &{1'b0, sig_not_used_a, sig_not_used_yet_b, // To be fixed 1'b0}; The reduction AND and constant zeros mean the net will always be zero, so won't use simulation runtime. The redundant leading and trailing zeros avoid syntax errors if there are no signals between them. The magic name "unused" (-unused-regexp) is recognized by Verilator and suppresses warnings; if using other lint tools, either teach it to the tool to ignore signals with "unused" in the name, or put the appropriate lint_off around the wire. Having unused signals in one place makes it easy to find what is unused, and reduces the number of lint_off pragmas, reducing bugs. USERINFO, USERWARN, USERERROR, USERFATAL A SystemVerilog elaboration-time assertion print was executed. VARHIDDEN Warns that a task, function, or begin/end block is declaring a variable by the same name as a variable in the upper level module or begin/end block (thus hiding the upper variable from being able to be used.) Rename the variable to avoid confusion when reading the code. Disabled by default as this is a code style warning; it will simulate correctly. WIDTH Warns that based on width rules of Verilog, two operands have different widths. Verilator generally can intuit the common usages of widths, and you shouldn't need to disable this message like you do with most lint programs. Generally other than simple mistakes, you have two solutions: If it's a constant 0 that's 32 bits or less, simply leave it unwidthed. Verilator considers zero to be any width needed. Concatenate leading zeros when doing arithmetic. In the statement wire [5:0] plus_one = from[5:0] + 6'd1 + carry[0]; The best fix, which clarifies intent and will also make all tools happy is: wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0, carry[0]}; Ignoring this warning will only suppress the lint check, it will simulate correctly. WIDTHCONCAT Warns that based on width rules of Verilog, a concatenate or replication has an indeterminate width. In most cases this violates the Verilog rule that widths inside concatenates and replicates must be sized, and should be fixed in the code. wire [63:0] concat = {1, 2}; An example where this is technically legal (though still bad form) is: parameter PAR = 1; wire [63:0] concat = {PAR, PAR}; The correct fix is to either size the 1 ("32'h1"), or add the width to the parameter definition ("parameter [31:0]"), or add the width to the parameter usage ("{PAR[31:0],PAR[31:0]}". The following describes the less obvious errors: Internal Error This error should never occur first, though may occur if earlier warnings or error messages have corrupted the program. If there are no other warnings or errors, submit a bug report. Unsupported: .... This error indicates that you are using a Verilog language construct that is not yet supported in Verilator. See the Limitations chapter. DEPRECATIONS The following deprecated items are scheduled for future removal: Pre-C++11 compiler support Verilator supports pre-C++11 compilers for non-threaded models when configured with --enable-prec11/--enable-prec11-final. This flag will be removed and C++11 compilers will be required for both compiling Verilator and compiling Verilated models no sooner than September 2020. SystemC 2.2 and earlier support Support for SystemC versions 2.2 and earlier including the related sc_clock variable attribute will be removed no sooner than September 2020. The supported versions will be SystemC 2.3.0 (SYSTEMC_VERSION 20111121) and later (presently 2.3.0, 2.3.1, 2.3.2, 2.3.3). Configuration File -msg The -msg argument to lint_off has been replaced with -rule. -msg is planned for removal no sooner than January 2021. XML locations The XML "fl" attribute has been replaced with "loc". "fl" is planned for removal no sooner than January 2021. FAQ/FREQUENTLY ASKED QUESTIONS Can I contribute? Please contribute! Just submit a pull request, or raise an issue to discuss if looking for something to help on. For more information see our contributor agreement. How widely is Verilator used? Verilator is used by many of the largest silicon design companies, and all the way down to college projects. Verilator is one of the "big 4" simulators, meaning one of the 4 main SystemVerilog simulators available, namely the commercial products Synopsys VCS (tm), Mentor Questa/ModelSim (tm), Cadence Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. The three commercial offerings are often collectively called the "big 3" simulators. Does Verilator run under Windows? Yes, using Cygwin. Verilated output also compiles under Microsoft Visual C++, but this is not tested every release. Can you provide binaries? You can install Verilator via the system package manager (apt, yum, etc.) on many Linux distributions, including Debian, Ubuntu, SuSE, Fedora, and others. These packages are provided by the Linux distributions and generally will lag the version of the mainline Verilator repository. If no binary package is available for your distribution, how about you set one up? Please contact the authors for assistance. How can it be faster than (name-a-big-3-closed-source-simulator)? Generally, the implied part of the question is "... with all of the manpower they can put into developing it." Most simulators have to be compliant with the complete IEEE 1364 (Verilog) and IEEE 1800 (SystemVerilog) standards, meaning they have to be event driven. This prevents them from being able to reorder blocks and make netlist-style optimizations, which are where most of the gains come from. You should not be scared by non-compliance. Your synthesis tool isn't compliant with the whole standard to start with, so your simulator need not be either. Verilator is closer to the synthesis interpretation, so this is a good thing for getting working silicon. Will Verilator output remain under my own license? Yes, it's just like using GCC on your programs; this is why Verilator uses the "GNU *Lesser* Public License Version 3" instead of the more typical "GNU Public License". See the licenses for details, but in brief, if you change Verilator itself or the header files Verilator includes, you must make the source code available under the GNU Lesser Public License. However, Verilator output (the Verilated code) only "include"s the licensed files, and so you are NOT required to release any output from Verilator. You also have the option of using the Perl Artistic License, which again does not require you to release your Verilog or generated code, and also allows you to modify Verilator for internal use without distributing the modified version. But please contribute back to the community! One limit is that you cannot under either license release a commercial Verilog simulation product incorporating Verilator without making the source code available. As is standard with Open Source, contributions back to Verilator will be placed under the Verilator copyright and LGPL/Artistic license. Small test cases will be released into the public domain so they can be used anywhere, and large tests under the LGPL/Artistic, unless requested otherwise. Why is running Verilator (to create a model) so slow? Verilator needs more memory than the resulting simulator will require, as Verilator internally creates all of the state of the resulting generated simulator in order to optimize it. If it takes more than a few minutes or so (and you're not using --debug since debug mode is disk bound), see if your machine is paging; most likely you need to run it on a machine with more memory. Very large designs are known to have topped 16GB resident set size. How do I generate waveforms (traces) in C++? See the next question for tracing in SystemC mode. A. Add the --trace switch to Verilator, and in your top level C code, call Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to enable traces, same as with any Verilog simulator. See "examples/make_tracing_c". B. Or, for finer-grained control, or C++ files with multiple Verilated modules you may also create the trace purely from C++. Create a VerilatedVcdC object, and in your main loop call "trace_object->dump(time)" every time step, and finally call "trace_object->close()". You also need to compile verilated_vcd_c.cpp and add it to your link, preferably by adding the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule. This is done for you if using the Verilator --exe flag. Note you can also call ->trace on multiple Verilated objects with the same trace file if you want all data to land in the same output file. #include "verilated_vcd_c.h" ... int main(int argc, char** argv, char** env) { ... Verilated::traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); // Trace 99 levels of hierarchy tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); ... while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += #; tfp->dump(main_time); } tfp->close(); } How do I generate waveforms (traces) in SystemC? A. Add the --trace switch to Verilator, and in your top level sc_main, call Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to enable traces, same as with any Verilog simulator, see the non-SystemC example in "examples/make_tracing_c". This will trace only the module containing the $dumpvar. B. Or, you may create a trace purely from SystemC, which may trace all Verilated designs in the SystemC model. Create a VerilatedVcdSc object as you would create a normal SystemC trace file. For an example, see the call to VerilatedVcdSc in the examples/make_tracing_sc/sc_main.cpp file of the distribution, and below. Alternatively you may use the C++ trace mechanism described in the previous question, note the timescale and timeprecision will be inherited from your SystemC settings. You also need to compile verilated_vcd_sc.cpp and verilated_vcd_c.cpp and add them to your link, preferably by adding the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule. This is done for you if using the Verilator --exe flag. Note you can also call ->trace on multiple Verilated objects with the same trace file if you want all data to land in the same output file. When using SystemC 2.3, the SystemC library must have been built with the experimental simulation phase callback based tracing disabled. This is disabled by default when building SystemC with its configure based build system, but when building SystemC with CMake, you must pass -DENABLE_PHASE_CALLBACKS_TRACING=OFF to disable this feature. #include "verilated_vcd_sc.h" ... int main(int argc, char** argv, char** env) { ... Verilated::traceEverOn(true); VerilatedVcdSc* tfp = new VerilatedVcdSc; topp->trace(tfp, 99); // Trace 99 levels of hierarchy tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); ... sc_start(1); ... tfp->close(); } How do I generate FST waveforms (traces) in C++? FST is a trace file format developed by GTKWave. Verilator provides basic FST support. To dump traces in FST format, add the --trace-fst switch to Verilator and either A. use $dumpfile/$dumpvars in Verilog as described in the VCD example above, or B. in C++ change the include described in the VCD example above: #include "verilated_fst_c.h" VerilatedFstC* tfp = new VerilatedFstC; Note that currently supporting both FST and VCD in a single simulation is impossible, but such requirement should be rare. You can however ifdef around the trace format in your C++ main loop, and select VCD or FST at build time, should you require. How do I generate FST waveforms (aka dumps or traces) in SystemC? The FST library from GTKWave does not currently support SystemC; use VCD format instead. How do I view waveforms (aka dumps or traces)? Verilator creates standard VCD (Value Change Dump) and FST files. VCD files are viewable with the open source GTKWave (recommended) or Dinotrace (legacy) programs, or any of the many closed-source offerings; FST is supported only by GTKWave. How do I reduce the size of large waveform (trace) files? First, instead of calling VerilatedVcdC->open at the beginning of time, delay calling it until the time stamp where you want tracing to begin. Likewise you can also call VerilatedVcdC->open before the end of time (perhaps a short period after you detect a verification error). Next, add /*verilator tracing_off*/ to any very low level modules you never want to trace (such as perhaps library cells). Finally, use the --trace-depth option to limit the depth of tracing, for example --trace-depth 1 to see only the top level signals. Also be sure you write your trace files to a local solid-state drive, instead of to a network drive. Network drives are generally far slower. You can also consider using FST tracing instead of VCD. FST dumps are a fraction of the size of the equivalent VCD. FST tracing can be slower than VCD tracing, but it might be the only option if the VCD file size is prohibitively large. How do I do coverage analysis? Verilator supports both block (line) coverage and user inserted functional coverage. First, run verilator with the --coverage option. If you are using your own makefile, compile the model with the GCC flag -DVM_COVERAGE (if using the makefile provided by Verilator, it will do this for you). At the end of your test, call VerilatedCov::write passing the name of the coverage data file (typically "logs/coverage.dat"). Run each of your tests in different directories. Each test will create a logs/coverage.dat file. After running all of your tests, execute the verilator_coverage tool. The verilator_coverage tool reads the logs/coverage.dat file(s), and creates an annotated source code listing showing code coverage details. For an example, after running 'make test' in the Verilator distribution, see the examples/make_tracing_c/logs directory. Grep for lines starting with '%' to see what lines Verilator believes need more coverage. Info files can be written by verilator_coverage for import to "lcov". This enables use of "genhtml" for HTML reports and importing reports to sites such as . Where is the translate_off command? (How do I ignore a construct?) Translate on/off pragmas are generally a bad idea, as it's easy to have mismatched pairs, and you can't see what another tool sees by just preprocessing the code. Instead, use the preprocessor; Verilator defines the "VERILATOR" define for you, so just wrap the code in an ifndef region: `ifndef VERILATOR Something_Verilator_Dislikes; `endif Most synthesis tools similarly define SYNTHESIS for you. Why do I get "unexpected "do"" or "unexpected "bit"" errors? The words "do", "bit", "ref", "return", and others are reserved keywords in SystemVerilog. Older Verilog code might use these as identifiers. You should change your code to not use them to ensure it works with newer tools. Alternatively, surround them by the Verilog 2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code. `begin_keywords "1364-2001" integer bit; initial bit = 1; `end_keywords If you want the whole design to be parsed as Verilog 2001, please see the "--default-language" option. How do I prevent my assertions from firing during reset? Call Verilated::assertOn(false) before you first call the model, then turn it back on after reset. It defaults to true. When false, all assertions controlled by --assert are disabled. Why do I get "undefined reference to `sc_time_stamp()'"? In C++ (non SystemC) code you need to define this function so that the simulator knows the current time. See the "CONNECTING TO C++" examples. Why do I get "undefined reference to `VL_RAND_RESET_I' or `Verilated::...'"? You need to link your compiled Verilated code against the verilated.cpp file found in the include directory of the Verilator kit. This is one target in the $(VK_GLOBAL_OBJS) make variable, which should be part of your Makefile's link rule. If you use --exe, this is done for you. Is the PLI supported? Only somewhat. More specifically, the common PLI-ish calls $display, $finish, $stop, $time, $write are converted to C++ equivalents. You can also use the "import DPI" SystemVerilog feature to call C code (see the chapter above). There is also limited VPI access to public signals. If you want something more complex, since Verilator emits standard C++ code, you can simply write your own C++ routines that can access and modify signal values without needing any PLI interface code, and call it with $c("{any_c++_statement}"). How do I make a Verilog module that contain a C++ object? You need to add the object to the structure that Verilator creates, then use $c to call a method inside your object. The test_regress/t/t_extend_class files show an example of how to do this. How do I get faster build times? When running make pass the make variable VM_PARALLEL_BUILDS=1 so that builds occur in parallel. Note this is now set by default if an output file was large enough to be split due to the --output-split option. Verilator emits any infrequently executed "cold" routines into separate __Slow.cpp files. This can accelerate compilation as optimization can be disabled on these routines. See the OPT_FAST and OPT_SLOW make variables and the BENCHMARKING & OPTIMIZATION section of the manual. Use a recent compiler. Newer compilers tend to be faster. Compile in parallel on many machines and use caching; see the web for the ccache, distcc and icecream packages. ccache will skip GCC runs between identical source builds, even across different users. If ccache was installed when Verilator was built it is used, or see OBJCACHE environment variable to override this. Also see the --output-split option. To reduce the compile time of classes that use a Verilated module (e.g. a top CPP file) you may wish to add /*verilator no_inline_module*/ to your top level module. This will decrease the amount of code in the model's Verilated class, improving compile times of any instantiating top level C++ code, at a relatively small cost of execution performance. Why do so many files need to recompile when I add a signal? Adding a new signal requires the symbol table to be recompiled. Verilator uses one large symbol table, as that results in 2-3 less assembly instructions for each signal access. This makes the execution time 10-15% faster, but can result in more compilations when something changes. How do I access Verilog functions/tasks in C? Use the SystemVerilog Direct Programming Interface. You write a Verilog function or task with input/outputs that match what you want to call in with C. Then mark that function as a DPI export function. See the DPI chapter in the IEEE Standard. How do I access C++ functions/tasks in Verilog? Use the SystemVerilog Direct Programming Interface. You write a Verilog function or task with input/outputs that match what you want to call in with C. Then mark that function as a DPI import function. See the DPI chapter in the IEEE Standard. How do I access signals in C? The best thing to do is to make a SystemVerilog "export DPI" task or function that accesses that signal, as described in the DPI chapter in the manual and DPI tutorials on the web. This will allow Verilator to better optimize the model and should be portable across simulators. If you really want raw access to the signals, declare the signals you will be accessing with a /*verilator public*/ comment before the closing semicolon. Then scope into the C++ class to read the value of the signal, as you would any other member variable. Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t), 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or 64-bit unsigned long longs (uint64_t) that fits the width of the signal. Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for 1 to 64 bits, and the compiler will properly up-convert smaller entities. Note even signed ports are declared as unsigned; you must sign extend yourself to the appropriate signal width. Signals wider than 64 bits are stored as an array of 32-bit uint32_t's. Thus to read bits 31:0, access signal[0], and for bits 63:32, access signal[1]. Unused bits (for example bit numbers 65-96 of a 65-bit vector) will always be zero. If you change the value you must make sure to pack zeros in the unused bits or core-dumps may result, because Verilator strips array bound checks where it believes them to be unnecessary to improve performance. In the SYSTEMC example above, if you had in our.v: input clk /*verilator public*/; // Note the placement of the semicolon above From the sc_main.cpp file, you'd then: #include "Vour.h" #include "Vour_our.h" cout << "clock is " << top->our->clk << endl; In this example, clk is a bool you can read or set as any other variable. The value of normal signals may be set, though clocks shouldn't be changed by your code or you'll get strange results. Should a module be in Verilog or SystemC? Sometimes there is a block that just interconnects cells, and have a choice as to if you write it in Verilog or SystemC. Everything else being equal, best performance is when Verilator sees all of the design. So, look at the hierarchy of your design, labeling cells as to if they are SystemC or Verilog. Then: A module with only SystemC cells below must be SystemC. A module with a mix of Verilog and SystemC cells below must be SystemC. (As Verilator cannot connect to lower-level SystemC cells.) A module with only Verilog cells below can be either, but for best performance should be Verilog. (The exception is if you have a design that is instantiated many times; in this case Verilating one of the lower modules and instantiating that Verilated cells multiple times into a SystemC module *may* be faster.) BUGS First, check the "LANGUAGE LIMITATIONS" section. Next, try the --debug switch. This will enable additional internal assertions, and may help identify the problem. Finally, reduce your code to the smallest possible routine that exhibits the bug. Even better, create a test in the test_regress/t directory, as follows: cd test_regress cp -p t/t_EXAMPLE.pl t/t_BUG.pl cp -p t/t_EXAMPLE.v t/t_BUG.v There are many hints on how to write a good test in the driver.pl documentation which can be seen by running: cd $VERILATOR_ROOT # Need the original distribution kit test_regress/driver.pl --help Edit t/t_BUG.pl to suit your example; you can do anything you want in the Verilog code there; just make sure it retains the single clk input and no outputs. Now, the following should fail: cd $VERILATOR_ROOT # Need the original distribution kit cd test_regress t/t_BUG.pl # Run on Verilator t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator t/t_BUG.pl --vcs # Run on VCS simulator t/t_BUG.pl --nc|--iv|--ghdl # Likewise on other simulators The test driver accepts a number of options, many of which mirror the main Verilator option. For example the previous test could have been run with debugging enabled. The full set of test options can be seen by running driver.pl --help as shown above. Finally, report the bug using the bug tracker at . The bug will become publicly visible; if this is unacceptable, mail the bug report to "wsnyder@wsnyder.org". HISTORY Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at Digital Equipment Corporation. The Verilog code that was converted to C was then merged with a C based CPU model of the Alpha processor and simulated in a C based environment called CCLI. In 1995 Verilator started being used also for Multimedia and Network Processor development inside Digital. Duane Galbi took over active development of Verilator, and added several performance enhancements. CCLI was still being used as the shell. In 1998, through the efforts of existing DECies, mainly Duane Galbi, Digital graciously agreed to release the source code. (Subject to the code not being resold, which is compatible with the GNU Public License.) In 2001, Wilson Snyder took the kit, and added a SystemC mode, and called it Verilator2. This was the first packaged public release. In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from scratch in C++. This added many optimizations, yielding about a 2-5x performance gain. In 2009, major SystemVerilog and DPI language support was added. In 2018, Verilator 4.000 was released with multithreaded support. Currently, various language features and performance enhancements are added as the need arises. Verilator is now about 3x faster than in 2002, and is faster than most (if not every) other simulator. AUTHORS When possible, please instead report bugs to . Wilson Snyder Major concepts by Paul Wasson, Duane Galbi, John Coiner and Jie Xu. CONTRIBUTORS Many people have provided ideas and other assistance with Verilator. Verilator is receiving major development support from the CHIPS Alliance. Previous major corporate sponsors of Verilator, by providing significant contributions of time or funds included include Atmel Corporation, Cavium Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc., and SiCortex Inc. The people who have contributed major functionality are Byron Bradley, Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, and Wilson Snyder. Major testers included Jeff Dutton, Jonathon Donaldson, Ralf Karge, David Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van Cauwenberghe, Gene Weber, and Clifford Wolf. Some of the people who have provided ideas, and feedback for Verilator include: David Addison, Tariq B. Ahmad, Nikana Anastasiadis, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew Barr, Geoff Barrett, Julius Baxter, Jeremy Bennett, Michael Berman, Victor Besyakov, Moinak Bhattacharyya, David Binderman, Piotr Binkowski, Johan Bjork, David Black, Tymoteusz Blazejczyk, Daniel Bone, Gregg Bouchard, Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Maarten De Braekeleer, Charlie Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, Tony Bybell, Ted Campbell, Chris Candler, Lauren Carlson, Donal Casey, Sebastien Van Cauwenberghe, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean Cross, George Cuan, Joe DErrico, Lukasz Dalek, Laurens van Dam, Gunter Dannoritzer, Ashutosh Das, Bernard Deadman, John Demme, Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Leendert van Doorn, Sebastian Dressler, Alex Duller, Jeff Dutton, Tomas Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein, Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner, Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Amir Gonnen, Chitlesh Goorah, Kai Gossner, Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto, Thomas Hawkins, Mitch Hayenga, Robert Henry, Stephen Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki Honda, Alex Hornung, David Horton, Peter Horvath, Jae Hossell, Alan Hunter, James Hutchinson, Jamie Iles, Ben Jackson, Shareef Jalloq, Krzysztof Jankowski, HyungKi Jeong, Iztok Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Ralf Karge, Dan Katz, Sol Katzman, Ian Kennedy, Jonathan Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot Koch, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, Will Korteland, Wojciech Koszek, Varun Koyyalagunta, David Kravitz, Roland Kruse, Sergey Kvachonok, Charles Eric LaForest, Ed Lander, Steve Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor Lesik, John Li, Eivind Liland, Yu Sheng Lin, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan Lussier, Fred Ma, Duraid Madina, Affe Mao, Julien Margetts, Mark Marshall, Alfonso Martinez, Yves Mathieu, Patrick Maupin, Jason McMullan, Elliot Mednick, Wim Michiels, Miodrag Milanovic, Wai Sum Mong, Peter Monsson, Sean Moore, Dennis Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris Nalbantis, Peter Nelson, Bob Newgard, Cong Van Nguyen, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Aleksander Osman, James Pallister, Vassilis Papaefstathiou, Brad Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter, Niranjan Prabhu, Usha Priyadharshini, Mark Jackson Pulver, Prateek Puri, Marshal Qiao, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Odd Magne Reitan, Frederic Requin, Frederick Requin, Dustin Richmond, Alberto Del Rio, Eric Rippey, Oleg Rodionov, Ludwig Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Jan Egil Ruud, Denis Rystsov, John Sanguinetti, Galen Seitz, Salman Sheikh, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Anderson Ignacio Da Silva, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson, Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki, Howard Su, Emerson Suguimoto, Gene Sullivan, Qingyao Sun, Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede, Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, Viktor Tomov, Steve Tong, Michael Tresidder, Neil Turton, Srini Vemuri, Yuri Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene Weber, David Welch, Thomas J Whatson, Marco Widmer, Leon Wildman, Daniel Wilkerson, Gerald Williams, Trevor Williams, Jan Van Winkel, Jeff Winston, Joshua Wise, Clifford Wolf, Tobias Wolfel, Johan Wouters, Junyi Xi, Ding Xiaoliang, Jie Xu, Mandy Xu, Takatsukasa Y, Luke Yang, and Amir Yazdanbakhsh. Thanks to them, and all those we've missed including above, or wished to remain anonymous. DISTRIBUTION The latest version is available from . Copyright 2003-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. All Verilog and C++/SystemC code quoted within this documentation file are released as Creative Commons Public Domain (CC0). Many example files and test files are likewise released under CC0 into effectively the Public Domain as described in the files themselves. SEE ALSO verilator_coverage, verilator_gantt, verilator_profcfunc, make, "verilator --help" which is the source for this document, and docs/internals.adoc in the distribution. verilator-4.038/configure0000775000177100017500000101553513702334430015434 0ustar wsnyderwsnyder#! /bin/sh # Guess values for system-dependent variables and create Makefiles. # Generated by GNU Autoconf 2.69 for Verilator 4.038 2020-07-11. # # Report bugs to . # # # Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc. # # # This configure script is free software; the Free Software Foundation # gives unlimited permission to copy, distribute and modify it. ## -------------------- ## ## M4sh Initialization. ## ## -------------------- ## # Be more Bourne compatible DUALCASE=1; export DUALCASE # for MKS sh if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which # is contrary to our usage. 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This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief C++ Tracing in FST Format /// //============================================================================= // SPDIFF_OFF // clang-format off #define __STDC_LIMIT_MACROS // UINT64_MAX #include "verilated.h" #include "verilated_fst_c.h" // GTKWave configuration #ifdef VL_TRACE_FST_WRITER_THREAD # define HAVE_LIBPTHREAD # define FST_WRITER_PARALLEL #endif // Include the GTKWave implementation directly #define FST_CONFIG_INCLUDE "fst_config.h" #include "gtkwave/fastlz.c" #include "gtkwave/fstapi.c" #include "gtkwave/lz4.c" #include #include #include #if defined(_WIN32) && !defined(__MINGW32__) && !defined(__CYGWIN__) # include #else # include #endif // clang-format on //============================================================================= // Specialization of the generics for this trace format #define VL_DERIVED_T VerilatedFst #include "verilated_trace_imp.cpp" #undef VL_DERIVED_T //============================================================================= // VerilatedFst VerilatedFst::VerilatedFst(void* fst) : m_fst(fst) , m_symbolp(NULL) , m_strbuf(NULL) {} VerilatedFst::~VerilatedFst() { if (m_fst) fstWriterClose(m_fst); if (m_symbolp) VL_DO_CLEAR(delete[] m_symbolp, m_symbolp = NULL); if (m_strbuf) VL_DO_CLEAR(delete[] m_strbuf, m_strbuf = NULL); } void VerilatedFst::open(const char* filename) VL_MT_UNSAFE { m_assertOne.check(); m_fst = fstWriterCreate(filename, 1); fstWriterSetPackType(m_fst, FST_WR_PT_LZ4); fstWriterSetTimescaleFromString(m_fst, timeResStr().c_str()); // lintok-begin-on-ref #ifdef VL_TRACE_FST_WRITER_THREAD fstWriterSetParallelMode(m_fst, 1); #endif m_curScope.clear(); VerilatedTrace::traceInit(); // Clear the scope stack std::list::iterator it = m_curScope.begin(); while (it != m_curScope.end()) { fstWriterSetUpscope(m_fst); it = m_curScope.erase(it); } // convert m_code2symbol into an array for fast lookup if (!m_symbolp) { m_symbolp = new fstHandle[nextCode()]; for (Code2SymbolType::iterator it = m_code2symbol.begin(); it != m_code2symbol.end(); ++it) { m_symbolp[it->first] = it->second; } } m_code2symbol.clear(); // Allocate string buffer for arrays if (!m_strbuf) { m_strbuf = new char[maxBits() + 32]; } } void VerilatedFst::close() { m_assertOne.check(); VerilatedTrace::close(); fstWriterClose(m_fst); m_fst = NULL; } void VerilatedFst::flush() { VerilatedTrace::flush(); fstWriterFlushContext(m_fst); } void VerilatedFst::emitTimeChange(vluint64_t timeui) { fstWriterEmitTimeChange(m_fst, timeui); } //============================================================================= // Decl void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, vluint32_t elements, unsigned int minValbits, const char** itemNamesp, const char** itemValuesp) { fstEnumHandle enumNum = fstWriterCreateEnumTable(m_fst, name, elements, minValbits, itemNamesp, itemValuesp); m_local2fstdtype[dtypenum] = enumNum; } void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1; VerilatedTrace::declCode(code, bits, false); std::istringstream nameiss(name); std::istream_iterator beg(nameiss); std::istream_iterator end; std::list tokens(beg, end); // Split name std::string symbol_name(tokens.back()); tokens.pop_back(); // Remove symbol name from hierarchy tokens.insert(tokens.begin(), moduleName()); // Add current module to the hierarchy // Find point where current and new scope diverge std::list::iterator cur_it = m_curScope.begin(); std::list::iterator new_it = tokens.begin(); while (cur_it != m_curScope.end() && new_it != tokens.end()) { if (*cur_it != *new_it) break; ++cur_it; ++new_it; } // Go back to the common point while (cur_it != m_curScope.end()) { fstWriterSetUpscope(m_fst); cur_it = m_curScope.erase(cur_it); } // Follow the hierarchy of the new variable from the common scope point while (new_it != tokens.end()) { fstWriterSetScope(m_fst, FST_ST_VCD_SCOPE, new_it->c_str(), NULL); m_curScope.push_back(*new_it); new_it = tokens.erase(new_it); } std::stringstream name_ss; name_ss << symbol_name; if (array) name_ss << "(" << arraynum << ")"; std::string name_str = name_ss.str(); if (dtypenum > 0) { fstEnumHandle enumNum = m_local2fstdtype[dtypenum]; fstWriterEmitEnumTableRef(m_fst, enumNum); } Code2SymbolType::const_iterator it = m_code2symbol.find(code); if (it == m_code2symbol.end()) { // New m_code2symbol[code] = fstWriterCreateVar(m_fst, vartype, vardir, bits, name_str.c_str(), 0); } else { // Alias fstWriterCreateVar(m_fst, vartype, vardir, bits, name_str.c_str(), it->second); } } void VerilatedFst::declBit(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, 0, 0); } void VerilatedFst::declBus(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb); } void VerilatedFst::declQuad(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb); } void VerilatedFst::declArray(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb); } void VerilatedFst::declDouble(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, 63, 0); } // Note: emit* are only ever called from one place (full* in // verilated_trace_imp.cpp, which is included in this file at the top), // so always inline them. VL_ATTR_ALWINLINE void VerilatedFst::emitBit(vluint32_t code, CData newval) { fstWriterEmitValueChange(m_fst, m_symbolp[code], newval ? "1" : "0"); } VL_ATTR_ALWINLINE void VerilatedFst::emitCData(vluint32_t code, CData newval, int bits) { char buf[VL_BYTESIZE]; cvtCDataToStr(buf, newval << (VL_BYTESIZE - bits)); fstWriterEmitValueChange(m_fst, m_symbolp[code], buf); } VL_ATTR_ALWINLINE void VerilatedFst::emitSData(vluint32_t code, SData newval, int bits) { char buf[VL_SHORTSIZE]; cvtSDataToStr(buf, newval << (VL_SHORTSIZE - bits)); fstWriterEmitValueChange(m_fst, m_symbolp[code], buf); } VL_ATTR_ALWINLINE void VerilatedFst::emitIData(vluint32_t code, IData newval, int bits) { char buf[VL_IDATASIZE]; cvtIDataToStr(buf, newval << (VL_IDATASIZE - bits)); fstWriterEmitValueChange(m_fst, m_symbolp[code], buf); } VL_ATTR_ALWINLINE void VerilatedFst::emitQData(vluint32_t code, QData newval, int bits) { char buf[VL_QUADSIZE]; cvtQDataToStr(buf, newval << (VL_QUADSIZE - bits)); fstWriterEmitValueChange(m_fst, m_symbolp[code], buf); } VL_ATTR_ALWINLINE void VerilatedFst::emitWData(vluint32_t code, const WData* newvalp, int bits) { int words = VL_WORDS_I(bits); char* wp = m_strbuf; // Convert the most significant word const int bitsInMSW = VL_BITBIT_E(bits) ? VL_BITBIT_E(bits) : VL_EDATASIZE; cvtEDataToStr(wp, newvalp[--words] << (VL_EDATASIZE - bitsInMSW)); wp += bitsInMSW; // Convert the remaining words while (words > 0) { cvtEDataToStr(wp, newvalp[--words]); wp += VL_EDATASIZE; } fstWriterEmitValueChange(m_fst, m_symbolp[code], m_strbuf); } VL_ATTR_ALWINLINE void VerilatedFst::emitDouble(vluint32_t code, double newval) { fstWriterEmitValueChange(m_fst, m_symbolp[code], &newval); } verilator-4.038/include/verilated_heavy.h0000664000177100017500000004451313702133367020477 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: String include for all Verilated C files /// /// This file is included automatically by Verilator at the top of /// all C++ files it generates. It is used when strings or other /// heavyweight types are required; these contents are not part of /// verilated.h to save compile time when such types aren't used. /// /// Code available from: https://verilator.org /// //************************************************************************* #ifndef _VERILATED_HEAVY_H_ #define _VERILATED_HEAVY_H_ 1 ///< Header Guard #include "verilated.h" #include #include #include #include //=================================================================== // String formatters (required by below containers) extern std::string VL_TO_STRING(CData lhs); extern std::string VL_TO_STRING(SData lhs); extern std::string VL_TO_STRING(IData lhs); extern std::string VL_TO_STRING(QData lhs); inline std::string VL_TO_STRING(const std::string& obj) { return "\"" + obj + "\""; } extern std::string VL_TO_STRING_W(int words, WDataInP obj); //=================================================================== // Readmem/Writemem operation classes class VlReadMem { bool m_hex; // Hex format int m_bits; // Bit width of values const std::string& m_filename; // Filename QData m_end; // End address (as specified by user) FILE* m_fp; // File handle for filename QData m_addr; // Next address to read int m_linenum; // Line number last read from file public: VlReadMem(bool hex, int bits, const std::string& filename, QData start, QData end); ~VlReadMem(); bool isOpen() const { return m_fp != NULL; } int linenum() const { return m_linenum; } bool get(QData& addrr, std::string& valuer); void setData(void* valuep, const std::string& rhs); }; class VlWriteMem { bool m_hex; // Hex format int m_bits; // Bit width of values FILE* m_fp; // File handle for filename QData m_addr; // Next address to write public: VlWriteMem(bool hex, int bits, const std::string& filename, QData start, QData end); ~VlWriteMem(); bool isOpen() const { return m_fp != NULL; } void print(QData addr, bool addrstamp, const void* valuep); }; //=================================================================== // Verilog array container // Similar to std::array, but: // 1. Doesn't require C++11 // 2. Lighter weight, only methods needed by Verilator, to help compile time. // // This is only used when we need an upper-level container and so can't // simply use a C style array (which is just a pointer). template class VlWide { WData m_storage[T_Words]; public: // cppcheck-suppress uninitVar VlWide() {} ~VlWide() {} const WData& at(size_t index) const { return m_storage[index]; } WData& at(size_t index) { return m_storage[index]; } WData* data() { return &m_storage[0]; } const WData* data() const { return &m_storage[0]; } bool operator<(const VlWide& rhs) const { return VL_LT_W(T_Words, data(), rhs.data()); } }; // Convert a C array to std::array reference by pointer magic, without copy. // Data type (second argument) is so the function template can automatically generate. template VlWide& VL_CVT_W_A(WDataInP inp, const VlWide&) { return *((VlWide*)inp); } template std::string VL_TO_STRING(const VlWide& obj) { return VL_TO_STRING_W(T_Words, obj.data()); } //=================================================================== // Verilog associative array container // There are no multithreaded locks on this; the base variable must // be protected by other means // template class VlAssocArray { private: // TYPES typedef std::map Map; public: typedef typename Map::const_iterator const_iterator; private: // MEMBERS Map m_map; // State of the assoc array T_Value m_defaultValue; // Default value public: // CONSTRUCTORS VlAssocArray() { // m_defaultValue isn't defaulted. Caller's constructor must do it. } ~VlAssocArray() {} // Standard copy constructor works. Verilog: assoca = assocb // METHODS T_Value& atDefault() { return m_defaultValue; } // Size of array. Verilog: function int size(), or int num() int size() const { return m_map.size(); } // Clear array. Verilog: function void delete([input index]) void clear() { m_map.clear(); } void erase(const T_Key& index) { m_map.erase(index); } // Return 0/1 if element exists. Verilog: function int exists(input index) int exists(const T_Key& index) const { return m_map.find(index) != m_map.end(); } // Return first element. Verilog: function int first(ref index); int first(T_Key& indexr) const { typename Map::const_iterator it = m_map.begin(); if (it == m_map.end()) return 0; indexr = it->first; return 1; } // Return last element. Verilog: function int last(ref index) int last(T_Key& indexr) const { typename Map::const_reverse_iterator it = m_map.rbegin(); if (it == m_map.rend()) return 0; indexr = it->first; return 1; } // Return next element. Verilog: function int next(ref index) int next(T_Key& indexr) const { typename Map::const_iterator it = m_map.find(indexr); if (VL_UNLIKELY(it == m_map.end())) return 0; ++it; if (VL_UNLIKELY(it == m_map.end())) return 0; indexr = it->first; return 1; } // Return prev element. Verilog: function int prev(ref index) int prev(T_Key& indexr) const { typename Map::const_iterator it = m_map.find(indexr); if (VL_UNLIKELY(it == m_map.end())) return 0; if (VL_UNLIKELY(it == m_map.begin())) return 0; --it; indexr = it->first; return 1; } // Setting. Verilog: assoc[index] = v // Can't just overload operator[] or provide a "at" reference to set, // because we need to be able to insert only when the value is set T_Value& at(const T_Key& index) { typename Map::iterator it = m_map.find(index); if (it == m_map.end()) { std::pair pit = m_map.insert(std::make_pair(index, m_defaultValue)); return pit.first->second; } return it->second; } // Accessing. Verilog: v = assoc[index] const T_Value& at(const T_Key& index) const { typename Map::iterator it = m_map.find(index); if (it == m_map.end()) { return m_defaultValue; } else { return it->second; } } // For save/restore const_iterator begin() const { return m_map.begin(); } const_iterator end() const { return m_map.end(); } // Dumping. Verilog: str = $sformatf("%p", assoc) std::string to_string() const { std::string out = "'{"; std::string comma; for (typename Map::const_iterator it = m_map.begin(); it != m_map.end(); ++it) { out += comma + VL_TO_STRING(it->first) + ":" + VL_TO_STRING(it->second); comma = ", "; } // Default not printed - maybe random init data return out + "} "; } }; template std::string VL_TO_STRING(const VlAssocArray& obj) { return obj.to_string(); } template void VL_READMEM_N(bool hex, int bits, const std::string& filename, VlAssocArray& obj, QData start, QData end) VL_MT_SAFE { VlReadMem rmem(hex, bits, filename, start, end); if (VL_UNLIKELY(!rmem.isOpen())) return; while (true) { QData addr; std::string data; if (rmem.get(addr /*ref*/, data /*ref*/)) { rmem.setData(&(obj.at(addr)), data); } else { break; } } } template void VL_WRITEMEM_N(bool hex, int bits, const std::string& filename, const VlAssocArray& obj, QData start, QData end) VL_MT_SAFE { VlWriteMem wmem(hex, bits, filename, start, end); if (VL_UNLIKELY(!wmem.isOpen())) return; for (typename VlAssocArray::const_iterator it = obj.begin(); it != obj.end(); ++it) { QData addr = it->first; if (addr >= start && addr <= end) wmem.print(addr, true, &(it->second)); } } //=================================================================== // Verilog queue and dynamic array container // There are no multithreaded locks on this; the base variable must // be protected by other means // // Bound here is the maximum size() allowed, e.g. 1 + SystemVerilog bound // For dynamic arrays it is always zero template class VlQueue { private: // TYPES typedef std::deque Deque; public: typedef typename Deque::const_iterator const_iterator; private: // MEMBERS Deque m_deque; // State of the assoc array T_Value m_defaultValue; // Default value public: // CONSTRUCTORS VlQueue() { // m_defaultValue isn't defaulted. Caller's constructor must do it. } ~VlQueue() {} // Standard copy constructor works. Verilog: assoca = assocb // METHODS T_Value& atDefault() { return m_defaultValue; } // Size. Verilog: function int size(), or int num() int size() const { return m_deque.size(); } // Clear array. Verilog: function void delete([input index]) void clear() { m_deque.clear(); } void erase(size_t index) { if (VL_LIKELY(index < m_deque.size())) m_deque.erase(index); } // Dynamic array new[] becomes a renew() void renew(size_t size) { clear(); m_deque.resize(size, atDefault()); } // Dynamic array new[]() becomes a renew_copy() void renew_copy(size_t size, const VlQueue& rhs) { if (size == 0) { clear(); } else { *this = rhs; m_deque.resize(size, atDefault()); } } // function void q.push_front(value) void push_front(const T_Value& value) { m_deque.push_front(value); if (VL_UNLIKELY(T_MaxSize != 0 && m_deque.size() > T_MaxSize)) m_deque.pop_back(); } // function void q.push_back(value) void push_back(const T_Value& value) { if (VL_LIKELY(T_MaxSize == 0 || m_deque.size() < T_MaxSize)) m_deque.push_back(value); } // function value_t q.pop_front(); T_Value pop_front() { if (m_deque.empty()) return m_defaultValue; T_Value v = m_deque.front(); m_deque.pop_front(); return v; } // function value_t q.pop_back(); T_Value pop_back() { if (m_deque.empty()) return m_defaultValue; T_Value v = m_deque.back(); m_deque.pop_back(); return v; } // Setting. Verilog: assoc[index] = v // Can't just overload operator[] or provide a "at" reference to set, // because we need to be able to insert only when the value is set T_Value& at(size_t index) { static T_Value s_throwAway; // Needs to work for dynamic arrays, so does not use T_MaxSize if (VL_UNLIKELY(index >= m_deque.size())) { s_throwAway = atDefault(); return s_throwAway; } else { return m_deque[index]; } } // Accessing. Verilog: v = assoc[index] const T_Value& at(size_t index) const { static T_Value s_throwAway; // Needs to work for dynamic arrays, so does not use T_MaxSize if (VL_UNLIKELY(index >= m_deque.size())) { return atDefault(); } else { return m_deque[index]; } } // function void q.insert(index, value); void insert(size_t index, const T_Value& value) { if (VL_UNLIKELY(index >= m_deque.size())) return; m_deque[index] = value; } // For save/restore const_iterator begin() const { return m_deque.begin(); } const_iterator end() const { return m_deque.end(); } // Dumping. Verilog: str = $sformatf("%p", assoc) std::string to_string() const { std::string out = "'{"; std::string comma; for (typename Deque::const_iterator it = m_deque.begin(); it != m_deque.end(); ++it) { out += comma + VL_TO_STRING(*it); comma = ", "; } return out + "} "; } }; template std::string VL_TO_STRING(const VlQueue& obj) { return obj.to_string(); } //=================================================================== // Verilog class reference container // There are no multithreaded locks on this; the base variable must // be protected by other means // // clang-format off #if (defined(_MSC_VER) && _MSC_VER >= 1900) || (__cplusplus >= 201103L) # define VlClassRef std::shared_ptr #else # define VlClassRef VlClassRef__SystemVerilog_class_support_requires_a_C11_or_newer_compiler #endif // clang-format on template // T typically of type VlClassRef inline T VL_NULL_CHECK(T t, const char* filename, int linenum) { if (VL_UNLIKELY(!t)) Verilated::nullPointerError(filename, linenum); return t; } //====================================================================== // Conversion functions extern std::string VL_CVT_PACK_STR_NW(int lwords, WDataInP lwp) VL_MT_SAFE; inline std::string VL_CVT_PACK_STR_NQ(QData lhs) VL_PURE { WData lw[VL_WQ_WORDS_E]; VL_SET_WQ(lw, lhs); return VL_CVT_PACK_STR_NW(VL_WQ_WORDS_E, lw); } inline std::string VL_CVT_PACK_STR_NN(const std::string& lhs) VL_PURE { return lhs; } inline std::string VL_CVT_PACK_STR_NI(IData lhs) VL_PURE { WData lw[VL_WQ_WORDS_E]; VL_SET_WI(lw, lhs); return VL_CVT_PACK_STR_NW(1, lw); } inline std::string VL_CONCATN_NNN(const std::string& lhs, const std::string& rhs) VL_PURE { return lhs + rhs; } inline std::string VL_REPLICATEN_NNQ(int, int, int, const std::string& lhs, IData rep) VL_PURE { std::string out; out.reserve(lhs.length() * rep); for (unsigned times = 0; times < rep; ++times) out += lhs; return out; } inline std::string VL_REPLICATEN_NNI(int obits, int lbits, int rbits, const std::string& lhs, IData rep) VL_PURE { return VL_REPLICATEN_NNQ(obits, lbits, rbits, lhs, rep); } inline IData VL_LEN_IN(const std::string& ld) { return ld.length(); } extern std::string VL_TOLOWER_NN(const std::string& ld); extern std::string VL_TOUPPER_NN(const std::string& ld); extern IData VL_FERROR_IN(IData fpi, std::string& outputr) VL_MT_SAFE; extern IData VL_FOPEN_NN(const std::string& filename, const std::string& mode) VL_MT_SAFE; extern IData VL_FOPEN_MCD_N(const std::string& filename) VL_MT_SAFE; extern void VL_READMEM_N(bool hex, int bits, QData depth, int array_lsb, const std::string& filename, void* memp, QData start, QData end) VL_MT_SAFE; extern void VL_WRITEMEM_N(bool hex, int bits, QData depth, int array_lsb, const std::string& filename, const void* memp, QData start, QData end) VL_MT_SAFE; extern IData VL_SSCANF_INX(int lbits, const std::string& ld, const char* formatp, ...) VL_MT_SAFE; extern void VL_SFORMAT_X(int obits_ignored, std::string& output, const char* formatp, ...) VL_MT_SAFE; extern std::string VL_SFORMATF_NX(const char* formatp, ...) VL_MT_SAFE; extern void VL_TIMEFORMAT_IINI(int units, int precision, const std::string& suffix, int width) VL_MT_SAFE; extern IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_MT_SAFE; inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, CData& rdr) VL_MT_SAFE { WData rwp[2]; // WData must always be at least 2 IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp); if (got) rdr = rwp[0]; return got; } inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, SData& rdr) VL_MT_SAFE { WData rwp[2]; // WData must always be at least 2 IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp); if (got) rdr = rwp[0]; return got; } inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, IData& rdr) VL_MT_SAFE { WData rwp[2]; IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp); if (got) rdr = rwp[0]; return got; } inline IData VL_VALUEPLUSARGS_INQ(int rbits, const std::string& ld, QData& rdr) VL_MT_SAFE { WData rwp[2]; IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp); if (got) rdr = VL_SET_QW(rwp); return got; } inline IData VL_VALUEPLUSARGS_INQ(int rbits, const std::string& ld, double& rdr) VL_MT_SAFE { WData rwp[2]; IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp); if (got) rdr = VL_CVT_D_Q(VL_SET_QW(rwp)); return got; } extern IData VL_VALUEPLUSARGS_INN(int, const std::string& ld, std::string& rdr) VL_MT_SAFE; //====================================================================== // Strings extern std::string VL_PUTC_N(const std::string& lhs, IData rhs, CData ths) VL_PURE; extern CData VL_GETC_N(const std::string& lhs, IData rhs) VL_PURE; extern std::string VL_SUBSTR_N(const std::string& lhs, IData rhs, IData ths) VL_PURE; inline IData VL_CMP_NN(const std::string& lhs, const std::string& rhs, bool ignoreCase) VL_PURE { // SystemVerilog does not allow a string variable to contain '\0'. // So C functions such as strcmp() can correctly compare strings. int result; if (ignoreCase) { result = VL_STRCASECMP(lhs.c_str(), rhs.c_str()); } else { result = std::strcmp(lhs.c_str(), rhs.c_str()); } return result; } extern IData VL_ATOI_N(const std::string& str, int base) VL_PURE; //====================================================================== // Dumping extern const char* vl_dumpctl_filenamep(bool setit = false, const std::string& filename = "") VL_MT_SAFE; #endif // Guard verilator-4.038/include/verilated_vcd_sc.cpp0000664000177100017500000001351213702133367021152 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Verilator tracing in VCD Format /// //============================================================================= // SPDIFF_OFF #include "verilatedos.h" #include "verilated_vcd_sc.h" // SPDIFF_ON //====================================================================== //====================================================================== //-------------------------------------------------- #if (SYSTEMC_VERSION >= 20050714) // SystemC 2.1.v1 // cppcheck-suppress unusedFunction void VerilatedVcdSc::write_comment(const std::string&) {} void VerilatedVcdSc::trace(const unsigned int&, const std::string&, const char**) {} // clang-format off # define DECL_TRACE_METHOD_A(tp) \ void VerilatedVcdSc::trace(const tp& object, const std::string& name) {} # define DECL_TRACE_METHOD_B(tp) \ void VerilatedVcdSc::trace(const tp& object, const std::string& name, int width) {} # if (SYSTEMC_VERSION >= 20171012) DECL_TRACE_METHOD_A( sc_event ) DECL_TRACE_METHOD_A( sc_time ) # endif DECL_TRACE_METHOD_A( bool ) DECL_TRACE_METHOD_A( sc_dt::sc_bit ) DECL_TRACE_METHOD_A( sc_dt::sc_logic ) DECL_TRACE_METHOD_B( unsigned char ) DECL_TRACE_METHOD_B( unsigned short ) DECL_TRACE_METHOD_B( unsigned int ) DECL_TRACE_METHOD_B( unsigned long ) # ifdef SYSTEMC_64BIT_PATCHES DECL_TRACE_METHOD_B( unsigned long long) # endif DECL_TRACE_METHOD_B( char ) DECL_TRACE_METHOD_B( short ) DECL_TRACE_METHOD_B( int ) DECL_TRACE_METHOD_B( long ) DECL_TRACE_METHOD_B( sc_dt::int64 ) DECL_TRACE_METHOD_B( sc_dt::uint64 ) DECL_TRACE_METHOD_A( float ) DECL_TRACE_METHOD_A( double ) DECL_TRACE_METHOD_A( sc_dt::sc_int_base ) DECL_TRACE_METHOD_A( sc_dt::sc_uint_base ) DECL_TRACE_METHOD_A( sc_dt::sc_signed ) DECL_TRACE_METHOD_A( sc_dt::sc_unsigned ) DECL_TRACE_METHOD_A( sc_dt::sc_fxval ) DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast ) DECL_TRACE_METHOD_A( sc_dt::sc_fxnum ) DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast ) DECL_TRACE_METHOD_A( sc_dt::sc_bv_base ) DECL_TRACE_METHOD_A( sc_dt::sc_lv_base ) // clang-format on //-------------------------------------------------- #elif (SYSTEMC_VERSION > 20011000) // SystemC 2.0.1 // cppcheck-suppress unusedFunction void VerilatedVcdSc::write_comment(const sc_string&) {} void VerilatedVcdSc::trace(const unsigned int&, const sc_string&, const char**) {} #define DECL_TRACE_METHOD_A(tp) \ void VerilatedVcdSc::trace(const tp& object, const sc_string& name) {} #define DECL_TRACE_METHOD_B(tp) \ void VerilatedVcdSc::trace(const tp& object, const sc_string& name, int width) {} // clang-format off DECL_TRACE_METHOD_A( bool ) DECL_TRACE_METHOD_A( sc_bit ) DECL_TRACE_METHOD_A( sc_logic ) DECL_TRACE_METHOD_B( unsigned char ) DECL_TRACE_METHOD_B( unsigned short ) DECL_TRACE_METHOD_B( unsigned int ) DECL_TRACE_METHOD_B( unsigned long ) #ifdef SYSTEMC_64BIT_PATCHES DECL_TRACE_METHOD_B( unsigned long long) #endif #if (SYSTEMC_VERSION > 20041000) DECL_TRACE_METHOD_B( unsigned long long) DECL_TRACE_METHOD_B( long long) #endif DECL_TRACE_METHOD_B( char ) DECL_TRACE_METHOD_B( short ) DECL_TRACE_METHOD_B( int ) DECL_TRACE_METHOD_B( long ) DECL_TRACE_METHOD_A( float ) DECL_TRACE_METHOD_A( double ) DECL_TRACE_METHOD_A( sc_int_base ) DECL_TRACE_METHOD_A( sc_uint_base ) DECL_TRACE_METHOD_A( sc_signed ) DECL_TRACE_METHOD_A( sc_unsigned ) DECL_TRACE_METHOD_A( sc_fxval ) DECL_TRACE_METHOD_A( sc_fxval_fast ) DECL_TRACE_METHOD_A( sc_fxnum ) DECL_TRACE_METHOD_A( sc_fxnum_fast ) DECL_TRACE_METHOD_A( sc_bv_base ) DECL_TRACE_METHOD_A( sc_lv_base ) // clang-format on //-------------------------------------------------- #else // SystemC 1.2.1beta // cppcheck-suppress unusedFunction void VerilatedVcdSc::write_comment(const sc_string&) {} void VerilatedVcdSc::trace(const unsigned int&, const sc_string&, const char**) {} #define DECL_TRACE_METHOD_A(tp) \ void VerilatedVcdSc::trace(const tp& object, const sc_string& name) {} #define DECL_TRACE_METHOD_B(tp) \ void VerilatedVcdSc::trace(const tp& object, const sc_string& name, int width) {} // clang-format off DECL_TRACE_METHOD_A( bool ) DECL_TRACE_METHOD_B( unsigned char ) DECL_TRACE_METHOD_B( short unsigned int ) DECL_TRACE_METHOD_B( unsigned int ) DECL_TRACE_METHOD_B( long unsigned int ) DECL_TRACE_METHOD_B( char ) DECL_TRACE_METHOD_B( short int ) DECL_TRACE_METHOD_B( int ) DECL_TRACE_METHOD_B( long int ) DECL_TRACE_METHOD_A( float ) DECL_TRACE_METHOD_A( double ) DECL_TRACE_METHOD_A( sc_bit ) DECL_TRACE_METHOD_A( sc_logic ) DECL_TRACE_METHOD_A( sc_bool_vector ) DECL_TRACE_METHOD_A( sc_logic_vector ) DECL_TRACE_METHOD_A( sc_signal_bool_vector ) DECL_TRACE_METHOD_A( sc_signal_logic_vector ) DECL_TRACE_METHOD_A( sc_uint_base ) DECL_TRACE_METHOD_A( sc_int_base ) DECL_TRACE_METHOD_A( sc_unsigned ) DECL_TRACE_METHOD_A( sc_signed ) DECL_TRACE_METHOD_A( sc_signal_resolved ) DECL_TRACE_METHOD_A( sc_signal_resolved_vector ) DECL_TRACE_METHOD_A( sc_bv_ns::sc_bv_base ) DECL_TRACE_METHOD_A( sc_bv_ns::sc_lv_base ) // clang-format on #endif #undef DECL_TRACE_METHOD_A #undef DECL_TRACE_METHOD_B //******************************************************************** verilator-4.038/include/verilatedos.h0000664000177100017500000004766613702133367017661 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: Common include for OS portability (verilated & verilator) /// /// This header is used by both the Verilator source code (run on the /// build and host system), and the Verilated output (run on the target /// system). Code needed by only the host system goes into /// config_build.h.in, code needed by Verilated code only goes into /// verilated.h, and code needed by both goes here (verilatedos.h). /// /// Code available from: https://verilator.org /// //************************************************************************* #ifndef _VERILATEDOS_H_ #define _VERILATEDOS_H_ 1 ///< Header Guard // Current clang-format versions botch #ifdef inclusion, so // clang-format off //========================================================================= // Compiler pragma abstraction #ifdef __GNUC__ # define VL_ATTR_ALIGNED(alignment) __attribute__((aligned(alignment))) # define VL_ATTR_ALWINLINE __attribute__((always_inline)) # define VL_ATTR_COLD __attribute__((cold)) # define VL_ATTR_HOT __attribute__((hot)) # define VL_ATTR_NORETURN __attribute__((noreturn)) # define VL_ATTR_PRINTF(fmtArgNum) __attribute__((format(printf, (fmtArgNum), (fmtArgNum) + 1))) # define VL_ATTR_PURE __attribute__((pure)) # define VL_ATTR_UNUSED __attribute__((unused)) # define VL_FUNC __func__ # if defined(__clang__) && defined(VL_THREADED) # define VL_ACQUIRE(...) __attribute__((acquire_capability(__VA_ARGS__))) # define VL_ACQUIRE_SHARED(...) __attribute__((acquire_shared_capability(__VA_ARGS__))) # define VL_RELEASE(...) __attribute__((release_capability(__VA_ARGS__))) # define VL_RELEASE_SHARED(...) __attribute__((release_shared_capability(__VA_ARGS__))) # define VL_TRY_ACQUIRE(...) __attribute__((try_acquire_capability(__VA_ARGS__))) # define VL_TRY_ACQUIRE_SHARED(...) __attribute__((try_acquire_shared_capability(__VA_ARGS__))) # define VL_CAPABILITY(x) __attribute__((capability(x))) # define VL_REQUIRES(x) __attribute__((requires_capability(x))) # define VL_GUARDED_BY(x) __attribute__((guarded_by(x))) # define VL_EXCLUDES(x) __attribute__((locks_excluded(x))) # define VL_SCOPED_CAPABILITY __attribute__((scoped_lockable)) # endif # define VL_LIKELY(x) __builtin_expect(!!(x), 1) # define VL_UNLIKELY(x) __builtin_expect(!!(x), 0) # define VL_UNREACHABLE __builtin_unreachable(); # define VL_PREFETCH_RD(p) __builtin_prefetch((p), 0) # define VL_PREFETCH_RW(p) __builtin_prefetch((p), 1) #elif defined(_MSC_VER) # define VL_FUNC __FUNCTION__ #endif // Defaults for unsupported compiler features #ifndef VL_ATTR_ALIGNED # define VL_ATTR_ALIGNED(alignment) ///< Align structure to specified byte alignment #endif #ifndef VL_ATTR_ALWINLINE # define VL_ATTR_ALWINLINE ///< Inline, even when not optimizing #endif #ifndef VL_ATTR_COLD # define VL_ATTR_COLD ///< Function is rarely executed #endif #ifndef VL_ATTR_HOT # define VL_ATTR_HOT ///< Function is highly executed #endif #ifndef VL_ATTR_NORETURN # define VL_ATTR_NORETURN ///< Function does not ever return #endif #ifndef VL_ATTR_PRINTF # define VL_ATTR_PRINTF(fmtArgNum) ///< Function with printf format checking #endif #ifndef VL_ATTR_PURE # define VL_ATTR_PURE ///< Function is pure (and thus also VL_MT_SAFE) #endif #ifndef VL_ATTR_UNUSED # define VL_ATTR_UNUSED ///< Function that may be never used #endif #ifndef VL_FUNC # define VL_FUNC "__func__" ///< Name of current function for error macros #endif #ifndef VL_CAPABILITY # define VL_ACQUIRE(...) ///< Function requires a capability/lock (-fthread-safety) # define VL_ACQUIRE_SHARED(...) ///< Function aquires a shared capability/lock (-fthread-safety) # define VL_RELEASE(...) ///< Function releases a capability/lock (-fthread-safety) # define VL_RELEASE_SHARED(...) ///< Function releases a shared capability/lock (-fthread-safety) # define VL_TRY_ACQUIRE(...) ///< Function returns bool if aquired a capability (-fthread-safety) # define VL_TRY_ACQUIRE_SHARED(...) ///< Function returns bool if aquired shared (-fthread-safety) # define VL_REQUIRES(x) ///< Function requires a capability inbound (-fthread-safety) # define VL_EXCLUDES(x) ///< Function requires not having a capability inbound (-fthread-safety) # define VL_CAPABILITY(x) ///< Name of capability/lock (-fthread-safety) # define VL_GUARDED_BY(x) ///< Name of mutex protecting this variable (-fthread-safety) # define VL_SCOPED_CAPABILITY ///< Scoped threaded capability/lock (-fthread-safety) #endif #ifndef VL_LIKELY # define VL_LIKELY(x) (!!(x)) ///< Boolean expression more often true than false # define VL_UNLIKELY(x) (!!(x)) ///< Boolean expression more often false than true #endif # define VL_UNCOVERABLE(x) VL_UNLIKELY(x) ///< Boolean expression never hit by users (no coverage) #ifndef VL_UNREACHABLE # define VL_UNREACHABLE ///< Point that may never be reached #endif #ifndef VL_PREFETCH_RD # define VL_PREFETCH_RD(p) ///< Prefetch data with read intent #endif #ifndef VL_PREFETCH_RW # define VL_PREFETCH_RW(p) ///< Prefetch data with read/write intent #endif #ifdef VL_THREADED # if defined(_MSC_VER) && _MSC_VER >= 1900 # define VL_THREAD_LOCAL thread_local # elif defined(__GNUC__) # if (__cplusplus < 201103L) && !defined(VL_THREADED_NO_C11_WARNING) # error "VL_THREADED/--threads support requires C++-11 or newer only; use newer compiler" # endif # else # error "Unsupported compiler for VL_THREADED: No thread-local declarator" # endif # define VL_THREAD_LOCAL thread_local ///< Use new C++ static local thread #else # define VL_THREAD_LOCAL ///< Use new C++ static local thread #endif #define VL_THREAD ///< Deprecated #define VL_STATIC_OR_THREAD static ///< Deprecated #define VL_PURE ///< Comment tag that Function is pure (and thus also VL_MT_SAFE) #define VL_MT_SAFE ///< Comment tag that function is threadsafe when VL_THREADED #define VL_MT_SAFE_POSTINIT ///< Comment tag that function is threadsafe when VL_THREADED, only ///< during normal operation (post-init) #define VL_MT_UNSAFE ///< Comment tag that function is not threadsafe when VL_THREADED #define VL_MT_UNSAFE_ONE ///< Comment tag that function is not threadsafe when VL_THREADED, ///< protected to make sure single-caller #define VL_ULL(c) (c##ULL) ///< Add appropriate suffix to 64-bit constant (deprecated) // This is not necessarily the same as #UL, depending on what the IData typedef is. #define VL_UL(c) (static_cast(c##UL)) ///< Add appropriate suffix to 32-bit constant #if defined(VL_CPPCHECK) || defined(__clang_analyzer__) || __cplusplus < 201103L # define VL_DANGLING(var) #else /// After e.g. delete, set variable to NULL to indicate must not use later # define VL_DANGLING(var) \ do { \ *const_cast(reinterpret_cast(&var)) = NULL; \ } while (false) #endif /// Perform an e.g. delete, then set variable to NULL to indicate must not use later. /// Unlike VL_DO_CLEAR the setting of the variable is only for debug reasons. #define VL_DO_DANGLING(stmt, var) \ do { \ do { \ stmt; \ } while (false); \ VL_DANGLING(var); \ } while (false) /// Perform an e.g. delete, then set variable to NULL as a requirement #define VL_DO_CLEAR(stmt, stmt2) \ do { \ do { \ stmt; \ } while (false); \ do { \ stmt2; \ } while (false); \ } while (false) //========================================================================= // C++-2011 #if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__) || defined(VL_CPPCHECK) # define VL_EQ_DELETE = delete # define vl_unique_ptr std::unique_ptr // By default we use std:: types in C++11. // Define VL_USE_UNORDERED_TYPES to test these pre-C++11 classes # ifdef VL_USE_UNORDERED_TYPES # define VL_INCLUDE_UNORDERED_MAP "verilated_unordered_set_map.h" # define VL_INCLUDE_UNORDERED_SET "verilated_unordered_set_map.h" # else # define vl_unordered_map std::unordered_map # define vl_unordered_set std::unordered_set # define VL_INCLUDE_UNORDERED_MAP # define VL_INCLUDE_UNORDERED_SET # endif # define VL_FINAL final # define VL_MUTABLE mutable # define VL_OVERRIDE override #else # define VL_EQ_DELETE # define vl_unique_ptr std::auto_ptr # define VL_INCLUDE_UNORDERED_MAP "verilated_unordered_set_map.h" # define VL_INCLUDE_UNORDERED_SET "verilated_unordered_set_map.h" # define VL_FINAL # define VL_MUTABLE # define VL_OVERRIDE #endif //========================================================================= // Optimization #ifndef VL_INLINE_OPT # define VL_INLINE_OPT ///< "inline" if compiling all objects in single compiler run #endif //========================================================================= // Internal coverage #ifdef VL_GCOV extern "C" { void __gcov_flush(); // gcc sources gcc/gcov-io.h has the prototype } /// Flush internal code coverage data before e.g. abort() # define VL_GCOV_FLUSH() \ __gcov_flush() #else # define VL_GCOV_FLUSH() #endif //========================================================================= // Warning disabled #ifndef VL_WARNINGS # ifdef _MSC_VER # pragma warning(disable:4099) // C4099: type name first seen using 'class' now seen using 'struct' (V3AstNode) # pragma warning(disable:4100) // C4100: unreferenced formal parameter (L4) # pragma warning(disable:4127) // C4127: conditional expression is constant (L4) # pragma warning(disable:4146) // C4146: unary minus operator applied to unsigned type, result still unsigned # pragma warning(disable:4189) // C4189: local variable is initialized but not referenced (L4) # pragma warning(disable:4244) // C4244: conversion from 'uint64_t' to 'uint_32_t', possible loss of data # pragma warning(disable:4245) // C4245: conversion from 'int' to 'unsigned', signed/unsigned mismatch # pragma warning(disable:4996) // C4996: sscanf/fopen/etc may be unsafe # endif #endif //========================================================================= // Basic integer types #ifdef __MINGW32__ # define __USE_MINGW_ANSI_STDIO 1 // Force old MinGW (GCC 5 and older) to use C99 formats #endif // The inttypes supplied with some GCC & MINGW32 versions requires STDC_FORMAT_MACROS // to be declared in order to get the PRIxx macros used by fstapi.c #define __STDC_FORMAT_MACROS #if defined(__CYGWIN__) # include # include // __WORDSIZE # include // ssize_t typedef unsigned char uint8_t; ///< 8-bit unsigned type (backward compatibility) typedef unsigned short int uint16_t; ///< 16-bit unsigned type (backward compatibility) typedef char vlsint8_t; ///< 8-bit signed type typedef unsigned char vluint8_t; ///< 8-bit unsigned type typedef short int vlsint16_t; ///< 16-bit signed type typedef unsigned short int vluint16_t; ///< 16-bit unsigned type # if defined(__uint32_t_defined) || defined(___int32_t_defined) // Newer Cygwin uint32_t in stdint.h as an unsigned int typedef int32_t vlsint32_t; ///< 32-bit signed type typedef uint32_t vluint32_t; ///< 32-bit unsigned type # else // Older Cygwin has long==uint32_t typedef unsigned long uint32_t; ///< 32-bit unsigned type (backward compatibility) typedef long vlsint32_t; ///< 32-bit signed type typedef unsigned long vluint32_t; ///< 32-bit unsigned type # endif # if defined(__WORDSIZE) && (__WORDSIZE == 64) typedef long vlsint64_t; ///< 64-bit signed type typedef unsigned long vluint64_t; ///< 64-bit unsigned type # else typedef long long vlsint64_t; ///< 64-bit signed type typedef unsigned long long vluint64_t; ///< 64-bit unsigned type # endif #elif defined(_WIN32) && defined(_MSC_VER) typedef unsigned __int8 uint8_t; ///< 8-bit unsigned type (backward compatibility) typedef unsigned __int16 uint16_t; ///< 16-bit unsigned type (backward compatibility) typedef unsigned __int32 uint32_t; ///< 32-bit unsigned type (backward compatibility) typedef signed __int8 vlsint8_t; ///< 8-bit signed type typedef unsigned __int8 vluint8_t; ///< 8-bit unsigned type typedef signed __int16 vlsint16_t; ///< 16-bit signed type typedef unsigned __int16 vluint16_t; ///< 16-bit unsigned type typedef signed __int32 vlsint32_t; ///< 32-bit signed type typedef unsigned __int32 vluint32_t; ///< 32-bit unsigned type typedef signed __int64 vlsint64_t; ///< 64-bit signed type typedef unsigned __int64 vluint64_t; ///< 64-bit unsigned type # ifndef _SSIZE_T_DEFINED # ifdef _WIN64 typedef signed __int64 ssize_t; ///< signed size_t; returned from read() # else typedef signed __int32 ssize_t; ///< signed size_t; returned from read() # endif # endif #else // Linux or compliant Unix flavors, -m64 # include // Solaris # include // Linux and most flavors # include // __WORDSIZE # include // ssize_t typedef char vlsint8_t; ///< 8-bit signed type typedef uint8_t vluint8_t; ///< 8-bit unsigned type typedef short vlsint16_t; ///< 16-bit signed type typedef uint16_t vluint16_t; ///< 16-bit unsigned type typedef int vlsint32_t; ///< 32-bit signed type typedef uint32_t vluint32_t; ///< 32-bit unsigned type # if defined(__WORDSIZE) && (__WORDSIZE == 64) typedef long vlsint64_t; ///< 64-bit signed type typedef unsigned long vluint64_t; ///< 64-bit unsigned type # else typedef long long vlsint64_t; ///< 64-bit signed type typedef unsigned long long vluint64_t; ///< 64-bit unsigned type # endif #endif //========================================================================= // Printing printf/scanf formats // Alas cinttypes isn't that standard yet // Use Microsoft-specific format specifiers for Microsoft Visual C++ only #ifdef _MSC_VER # define VL_PRI64 "I64" #else // use standard C99 format specifiers # if defined(__WORDSIZE) && (__WORDSIZE == 64) # define VL_PRI64 "l" # else # define VL_PRI64 "ll" # endif #endif #if defined(_WIN32) && defined(_MSC_VER) # if (_MSC_VER < 1900) # define VL_SNPRINTF _snprintf # else # define VL_SNPRINTF snprintf # endif # define VL_VSNPRINTF vsnprintf #else # define VL_SNPRINTF snprintf # define VL_VSNPRINTF vsnprintf #endif //========================================================================= // File system functions #ifdef _WIN32 # define VL_DEV_NULL "nul" #else // Linux or compliant Unix flavors # define VL_DEV_NULL "/dev/null" #endif //========================================================================= // Integer size macros #define VL_BYTESIZE 8 ///< Bits in a CData / byte #define VL_SHORTSIZE 16 ///< Bits in a SData / short #define VL_IDATASIZE 32 ///< Bits in a IData / word #define VL_WORDSIZE VL_IDATASIZE ///< Legacy define #define VL_QUADSIZE 64 ///< Bits in a QData / quadword #define VL_EDATASIZE 32 ///< Bits in a EData (WData entry) #define VL_EDATASIZE_LOG2 5 ///< log2(VL_EDATASIZE) #define VL_CACHE_LINE_BYTES 64 ///< Bytes in a cache line (for alignment) /// Bytes this number of bits needs (1 bit=1 byte) #define VL_BYTES_I(nbits) (((nbits) + (VL_BYTESIZE - 1)) / VL_BYTESIZE) /// Words/EDatas this number of bits needs (1 bit=1 word) #define VL_WORDS_I(nbits) (((nbits) + (VL_EDATASIZE - 1)) / VL_EDATASIZE) /// Words/EDatas a quad requires #define VL_WQ_WORDS_E VL_WORDS_I(VL_QUADSIZE) //========================================================================= // Class definition helpers // Used to declare a class as uncopyable; put after a private: #define VL_UNCOPYABLE(Type) \ Type(const Type& other) VL_EQ_DELETE; \ Type& operator=(const Type&) VL_EQ_DELETE //========================================================================= // Verilated function size macros #define VL_MULS_MAX_WORDS 16 ///< Max size in words of MULS operation #define VL_TO_STRING_MAX_WORDS 64 ///< Max size in words of String conversion operation //========================================================================= // Base macros #define VL_SIZEBITS_I (VL_IDATASIZE - 1) ///< Bit mask for bits in a word #define VL_SIZEBITS_Q (VL_QUADSIZE - 1) ///< Bit mask for bits in a quad #define VL_SIZEBITS_E (VL_EDATASIZE - 1) ///< Bit mask for bits in a quad /// Mask for words with 1's where relevant bits are (0=all bits) #define VL_MASK_I(nbits) (((nbits) & VL_SIZEBITS_I) ? ((1U << ((nbits) & VL_SIZEBITS_I)) - 1) : ~0) /// Mask for quads with 1's where relevant bits are (0=all bits) #define VL_MASK_Q(nbits) \ (((nbits) & VL_SIZEBITS_Q) ? ((1ULL << ((nbits) & VL_SIZEBITS_Q)) - 1ULL) : ~0ULL) /// Mask for EData with 1's where relevant bits are (0=all bits) #define VL_MASK_E(nbits) VL_MASK_I(nbits) #define VL_EUL(n) VL_UL(n) ///< Make constant number EData sized #define VL_BITWORD_I(bit) ((bit) / VL_IDATASIZE) ///< Word number for sv DPI vectors #define VL_BITWORD_E(bit) ((bit) >> VL_EDATASIZE_LOG2) ///< Word number for a wide quantity #define VL_BITBIT_I(bit) ((bit) & VL_SIZEBITS_I) ///< Bit number for a bit in a long #define VL_BITBIT_Q(bit) ((bit) & VL_SIZEBITS_Q) ///< Bit number for a bit in a quad #define VL_BITBIT_E(bit) ((bit) & VL_SIZEBITS_E) ///< Bit number for a bit in a EData //========================================================================= // Floating point // #defines, to avoid requiring math.h on all compile runs #ifdef _MSC_VER # define VL_TRUNC(n) (((n) < 0) ? ceil((n)) : floor((n))) # define VL_ROUND(n) (((n) < 0) ? ceil((n)-0.5) : floor((n) + 0.5)) #else # define VL_TRUNC(n) trunc(n) # define VL_ROUND(n) round(n) #endif //========================================================================= // Performance counters /// The vluint64_t argument is loaded with a high-performance counter for profiling /// or 0x0 if not implemented on this platform #if defined(__i386__) || defined(__x86_64__) #define VL_RDTSC(val) \ { \ vluint32_t hi, lo; \ asm volatile("rdtsc" : "=a"(lo), "=d"(hi)); \ (val) = ((vluint64_t)lo) | (((vluint64_t)hi) << 32); \ } #elif defined(__aarch64__) # define VL_RDTSC(val) asm volatile("mrs %[rt],PMCCNTR_EL0" : [rt] "=r"(val)); #else // We just silently ignore unknown OSes, as only leads to missing statistics # define VL_RDTSC(val) (val) = 0; #endif //========================================================================= // Threading related OS-specific functions #if VL_THREADED # ifdef _WIN32 # define WIN32_LEAN_AND_MEAN # define NOMINMAX # include "Windows.h" # define VL_CPU_RELAX() YieldProcessor() # elif defined(__i386__) || defined(__x86_64__) /// For more efficient busy waiting on SMT CPUs, let the processor know /// we're just waiting so it can let another thread run # define VL_CPU_RELAX() asm volatile("rep; nop" ::: "memory") # elif defined(__ia64__) # define VL_CPU_RELAX() asm volatile("hint @pause" ::: "memory") # elif defined(__aarch64__) # define VL_CPU_RELAX() asm volatile("yield" ::: "memory") # elif defined(__powerpc64__) # define VL_CPU_RELAX() asm volatile("or 1, 1, 1; or 2, 2, 2;" ::: "memory") # else # error "Missing VL_CPU_RELAX() definition. Or, don't use VL_THREADED" # endif #endif //========================================================================= // String related OS-specific functions #ifdef _MSC_VER # define VL_STRCASECMP _stricmp #else # define VL_STRCASECMP strcasecmp #endif //========================================================================= // Macros controlling target specific optimizations // Define VL_PORTABLE_ONLY to disable all target specific optimizations #ifndef VL_PORTABLE_ONLY # ifdef __x86_64__ # define VL_X86_64 1 # endif #endif // VL_PORTABLE_ONLY // clang-format on //========================================================================= // Stringify macros #define VL_STRINGIFY(x) VL_STRINGIFY2(x) #define VL_STRINGIFY2(x) #x //========================================================================= #endif // Guard verilator-4.038/include/verilated_fst_c.h0000664000177100017500000001665313702133367020465 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief C++ Tracing in FST Format /// //============================================================================= // SPDIFF_OFF #ifndef _VERILATED_FST_C_H_ #define _VERILATED_FST_C_H_ 1 #include "verilated.h" #include "verilated_trace.h" #include "gtkwave/fstapi.h" #include #include #include #include //============================================================================= // VerilatedFst /// Base class to create a Verilator FST dump /// This is an internally used class - see VerilatedFstC for what to call from applications class VerilatedFst : public VerilatedTrace { private: // Give the superclass access to private bits (to avoid virtual functions) friend class VerilatedTrace; //========================================================================= // FST specific internals typedef std::map Code2SymbolType; typedef std::map Local2FstDtype; void* m_fst; Code2SymbolType m_code2symbol; Local2FstDtype m_local2fstdtype; std::list m_curScope; fstHandle* m_symbolp; ///< same as m_code2symbol, but as an array char* m_strbuf; ///< String buffer long enough to hold maxBits() chars // CONSTRUCTORS VL_UNCOPYABLE(VerilatedFst); void declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb); protected: //========================================================================= // Implementation of VerilatedTrace interface // Implementations of protected virtual methods for VerilatedTrace void emitTimeChange(vluint64_t timeui) VL_OVERRIDE; // Hooks called from VerilatedTrace bool preFullDump() VL_OVERRIDE { return isOpen(); } bool preChangeDump() VL_OVERRIDE { return isOpen(); } // Implementations of duck-typed methods for VerilatedTrace. These are // called from only one place (namely full*) so always inline them. inline void emitBit(vluint32_t code, CData newval); inline void emitCData(vluint32_t code, CData newval, int bits); inline void emitSData(vluint32_t code, SData newval, int bits); inline void emitIData(vluint32_t code, IData newval, int bits); inline void emitQData(vluint32_t code, QData newval, int bits); inline void emitWData(vluint32_t code, const WData* newvalp, int bits); inline void emitDouble(vluint32_t code, double newval); public: //========================================================================= // External interface to client code explicit VerilatedFst(void* fst = NULL); ~VerilatedFst(); /// Open the file; call isOpen() to see if errors void open(const char* filename) VL_MT_UNSAFE; /// Close the file void close() VL_MT_UNSAFE; /// Flush any remaining data to this file void flush() VL_MT_UNSAFE; /// Is file open? bool isOpen() const { return m_fst != NULL; } //========================================================================= // Internal interface to Verilator generated code /// Inside dumping routines, declare a data type void declDTypeEnum(int dtypenum, const char* name, vluint32_t elements, unsigned int minValbits, const char** itemNamesp, const char** itemValuesp); /// Inside dumping routines, declare a signal void declBit(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum); void declBus(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb); void declQuad(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb); void declArray(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb); void declDouble(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum); }; // Declare specialization here as it's used in VerilatedFstC just below template <> void VerilatedTrace::dump(vluint64_t timeui); template <> void VerilatedTrace::set_time_unit(const char* unitp); template <> void VerilatedTrace::set_time_unit(const std::string& unit); template <> void VerilatedTrace::set_time_resolution(const char* unitp); template <> void VerilatedTrace::set_time_resolution(const std::string& unit); //============================================================================= // VerilatedFstC /// Create a FST dump file in C standalone (no SystemC) simulations. /// Also derived for use in SystemC simulations. /// Thread safety: Unless otherwise indicated, every function is VL_MT_UNSAFE_ONE class VerilatedFstC { VerilatedFst m_sptrace; ///< Trace file being created // CONSTRUCTORS VL_UNCOPYABLE(VerilatedFstC); public: explicit VerilatedFstC(void* filep = NULL) : m_sptrace(filep) {} ~VerilatedFstC() { close(); } /// Routines can only be called from one thread; allow next call from different thread void changeThread() { spTrace()->changeThread(); } // ACCESSORS /// Is file open? bool isOpen() const { return m_sptrace.isOpen(); } // METHODS /// Open a new FST file void open(const char* filename) VL_MT_UNSAFE_ONE { m_sptrace.open(filename); } /// Close dump void close() VL_MT_UNSAFE_ONE { m_sptrace.close(); } /// Flush dump void flush() VL_MT_UNSAFE_ONE { m_sptrace.flush(); } /// Write one cycle of dump data void dump(vluint64_t timeui) { m_sptrace.dump(timeui); } /// Write one cycle of dump data - backward compatible and to reduce /// conversion warnings. It's better to use a vluint64_t time instead. void dump(double timestamp) { dump(static_cast(timestamp)); } void dump(vluint32_t timestamp) { dump(static_cast(timestamp)); } void dump(int timestamp) { dump(static_cast(timestamp)); } /// Set time units (s/ms, defaults to ns) /// For Verilated models, these propage from the Verilated default --timeunit void set_time_unit(const char* unitp) { m_sptrace.set_time_unit(unitp); } void set_time_unit(const std::string& unit) { m_sptrace.set_time_unit(unit); } /// Set time resolution (s/ms, defaults to ns) /// For Verilated models, these propage from the Verilated default --timeunit void set_time_resolution(const char* unitp) { m_sptrace.set_time_resolution(unitp); } void set_time_resolution(const std::string& unit) { m_sptrace.set_time_resolution(unit); } /// Internal class access inline VerilatedFst* spTrace() { return &m_sptrace; }; }; #endif // guard verilator-4.038/include/verilated_dpi.h0000664000177100017500000000711613702133367020135 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: Common include for all Verilated C files that use DPI /// /// This file is included automatically by Verilator at the top of /// all C++ files it generates where DPI is used. It contains /// DPI interface functions required by the Verilated code. /// /// Code available from: https://verilator.org /// //************************************************************************* #ifndef _VERILATED_DPI_H_ #define _VERILATED_DPI_H_ 1 ///< Header Guard #include "verilatedos.h" #include "verilated.h" // Also presumably included by caller #include "verilated_sym_props.h" #include "svdpi.h" //=================================================================== // SETTING OPERATORS /// Convert svBitVecVal to Verilator internal data static inline void VL_SET_W_SVBV(int obits, WDataOutP owp, const svBitVecVal* lwp) VL_MT_SAFE { int words = VL_WORDS_I(obits); for (int i = 0; i < words - 1; ++i) owp[i] = lwp[i]; owp[words - 1] = lwp[words - 1] & VL_MASK_I(obits); } static inline QData VL_SET_Q_SVBV(const svBitVecVal* lwp) VL_MT_SAFE { return _VL_SET_QII(lwp[1], lwp[0]); } static inline IData VL_SET_I_SVBV(const svBitVecVal* lwp) VL_MT_SAFE { return lwp[0]; } /// Convert Verilator internal data to svBitVecVal static inline void VL_SET_SVBV_W(int obits, svBitVecVal* owp, WDataInP lwp) VL_MT_SAFE { int words = VL_WORDS_I(obits); for (int i = 0; i < words - 1; ++i) owp[i] = lwp[i]; owp[words - 1] = lwp[words - 1] & VL_MASK_I(obits); } static inline void VL_SET_SVBV_I(int, svBitVecVal* owp, IData ld) VL_MT_SAFE { owp[0] = ld; } static inline void VL_SET_SVBV_Q(int, svBitVecVal* owp, QData ld) VL_MT_SAFE { VL_SET_WQ(owp, ld); } /// Convert svLogicVecVal to Verilator internal data /// Note these functions ignore X/Z in svLogicVecVal static inline void VL_SET_W_SVLV(int obits, WDataOutP owp, const svLogicVecVal* lwp) VL_MT_SAFE { int words = VL_WORDS_I(obits); for (int i = 0; i < words - 1; ++i) owp[i] = lwp[i].aval; owp[words - 1] = lwp[words - 1].aval & VL_MASK_I(obits); } static inline QData VL_SET_Q_SVLV(const svLogicVecVal* lwp) VL_MT_SAFE { return _VL_SET_QII(lwp[1].aval, lwp[0].aval); } static inline IData VL_SET_I_SVLV(const svLogicVecVal* lwp) VL_MT_SAFE { return lwp[0].aval; } /// Convert Verilator internal data to svLogicVecVal /// Note these functions never create X/Z in svLogicVecVal static inline void VL_SET_SVLV_W(int obits, svLogicVecVal* owp, WDataInP lwp) VL_MT_SAFE { int words = VL_WORDS_I(obits); for (int i = 0; i < words; ++i) owp[i].bval = 0; for (int i = 0; i < words - 1; ++i) owp[i].aval = lwp[i]; owp[words - 1].aval = lwp[words - 1] & VL_MASK_I(obits); } static inline void VL_SET_SVLV_I(int, svLogicVecVal* owp, IData ld) VL_MT_SAFE { owp[0].aval = ld; owp[0].bval = 0; } static inline void VL_SET_SVLV_Q(int, svLogicVecVal* owp, QData ld) VL_MT_SAFE { WData lwp[2]; VL_SET_WQ(lwp, ld); owp[0].aval = lwp[0]; owp[0].bval = 0; owp[1].aval = lwp[1]; owp[1].bval = 0; } //====================================================================== #endif // Guard verilator-4.038/include/verilated_vcd_sc.h0000664000177100017500000001742213702133367020623 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Verilator tracing in VCD format /// /// This class is not threadsafe, as the SystemC kernel is not threadsafe. /// //============================================================================= // SPDIFF_OFF #ifndef _VERILATED_VCD_SC_H_ #define _VERILATED_VCD_SC_H_ 1 #include "verilatedos.h" #include "verilated_sc.h" #include "verilated_vcd_c.h" // SPDIFF_ON //============================================================================= // VerilatedVcdSc /// /// This class is passed to the SystemC simulation kernel, just like a /// documented SystemC trace format. class VerilatedVcdSc : sc_trace_file, public VerilatedVcdC { // CONSTRUCTORS VL_UNCOPYABLE(VerilatedVcdSc); public: VerilatedVcdSc() { sc_get_curr_simcontext()->add_trace_file(this); #if (SYSTEMC_VERSION >= 20060505) // We want to avoid a depreciated warning, but still be back compatible. // Turning off the message just for this still results in an // annoying "to turn off" message. sc_time t1sec(1, SC_SEC); if (t1sec.to_default_time_units() != 0) { sc_time tunits(1.0 / t1sec.to_default_time_units(), SC_SEC); spTrace()->set_time_unit(tunits.to_string()); } spTrace()->set_time_resolution(sc_get_time_resolution().to_string()); #elif (SYSTEMC_VERSION > 20011000) // To confuse matters 2.1.beta returns a char* here, while 2.1.v1 returns a std::string // we allow both flavors with overloaded set_time_* functions. spTrace()->set_time_unit(sc_get_default_time_unit().to_string()); spTrace()->set_time_resolution(sc_get_time_resolution().to_string()); #endif } virtual ~VerilatedVcdSc() { close(); } // METHODS /// Called by SystemC simulate() virtual void cycle(bool delta_cycle) { #if (SYSTEMC_VERSION > 20011000) if (!delta_cycle) { this->dump(sc_time_stamp().to_double()); } #else // VCD files must have integer timestamps, so we write all times in // increments of time_resolution if (!delta_cycle) { this->dump(sc_time_stamp().to_double()); } #endif } private: /// Fake outs for linker #ifdef NC_SYSTEMC // Cadence Incisive has these as abstract functions so we must create them virtual void set_time_unit(int exponent10_seconds) {} // deprecated #endif #if defined(NC_SYSTEMC) || (SYSTEMC_VERSION >= 20111100) virtual void set_time_unit(double v, sc_time_unit tu) {} // LCOV_EXCL_LINE #endif //-------------------------------------------------- #if (SYSTEMC_VERSION >= 20050714) // SystemC 2.1.v1 // clang-format off # define DECL_TRACE_METHOD_A(tp) virtual void trace(const tp& object, const std::string& name); # define DECL_TRACE_METHOD_B(tp) \ virtual void trace(const tp& object, const std::string& name, int width); virtual void write_comment(const std::string&); virtual void trace(const unsigned int&, const std::string&, const char**); // Formatting matches that of sc_trace.h # if (SYSTEMC_VERSION >= 20171012) DECL_TRACE_METHOD_A( sc_event ) DECL_TRACE_METHOD_A( sc_time ) # endif DECL_TRACE_METHOD_A( bool ) DECL_TRACE_METHOD_A( sc_dt::sc_bit ) DECL_TRACE_METHOD_A( sc_dt::sc_logic ) DECL_TRACE_METHOD_B( unsigned char ) DECL_TRACE_METHOD_B( unsigned short ) DECL_TRACE_METHOD_B( unsigned int ) DECL_TRACE_METHOD_B( unsigned long ) # ifdef SYSTEMC_64BIT_PATCHES DECL_TRACE_METHOD_B( unsigned long long) # endif DECL_TRACE_METHOD_B( char ) DECL_TRACE_METHOD_B( short ) DECL_TRACE_METHOD_B( int ) DECL_TRACE_METHOD_B( long ) DECL_TRACE_METHOD_B( sc_dt::int64 ) DECL_TRACE_METHOD_B( sc_dt::uint64 ) DECL_TRACE_METHOD_A( float ) DECL_TRACE_METHOD_A( double ) DECL_TRACE_METHOD_A( sc_dt::sc_int_base ) DECL_TRACE_METHOD_A( sc_dt::sc_uint_base ) DECL_TRACE_METHOD_A( sc_dt::sc_signed ) DECL_TRACE_METHOD_A( sc_dt::sc_unsigned ) DECL_TRACE_METHOD_A( sc_dt::sc_fxval ) DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast ) DECL_TRACE_METHOD_A( sc_dt::sc_fxnum ) DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast ) DECL_TRACE_METHOD_A( sc_dt::sc_bv_base ) DECL_TRACE_METHOD_A( sc_dt::sc_lv_base ) // clang-format on //-------------------------------------------------- #elif (SYSTEMC_VERSION > 20011000) // SystemC 2.0.1 // clang-format off # define DECL_TRACE_METHOD_A(tp) virtual void trace(const tp& object, const sc_string& name); # define DECL_TRACE_METHOD_B(tp) \ virtual void trace(const tp& object, const sc_string& name, int width); virtual void write_comment(const sc_string&); virtual void trace(const unsigned int&, const sc_string&, const char**); virtual void delta_cycles(bool) {} virtual void space(int n) {} DECL_TRACE_METHOD_A( bool ) DECL_TRACE_METHOD_A( sc_bit ) DECL_TRACE_METHOD_A( sc_logic ) DECL_TRACE_METHOD_B( unsigned char ) DECL_TRACE_METHOD_B( unsigned short ) DECL_TRACE_METHOD_B( unsigned int ) DECL_TRACE_METHOD_B( unsigned long ) # ifdef SYSTEMC_64BIT_PATCHES DECL_TRACE_METHOD_B( unsigned long long) # endif # if (SYSTEMC_VERSION > 20041000) DECL_TRACE_METHOD_B( unsigned long long) DECL_TRACE_METHOD_B( long long) # endif DECL_TRACE_METHOD_B( char ) DECL_TRACE_METHOD_B( short ) DECL_TRACE_METHOD_B( int ) DECL_TRACE_METHOD_B( long ) DECL_TRACE_METHOD_A( float ) DECL_TRACE_METHOD_A( double ) DECL_TRACE_METHOD_A( sc_int_base ) DECL_TRACE_METHOD_A( sc_uint_base ) DECL_TRACE_METHOD_A( sc_signed ) DECL_TRACE_METHOD_A( sc_unsigned ) DECL_TRACE_METHOD_A( sc_fxval ) DECL_TRACE_METHOD_A( sc_fxval_fast ) DECL_TRACE_METHOD_A( sc_fxnum ) DECL_TRACE_METHOD_A( sc_fxnum_fast ) DECL_TRACE_METHOD_A( sc_bv_base ) DECL_TRACE_METHOD_A( sc_lv_base ) // clang-format on //-------------------------------------------------- #else // SystemC 1.2.1beta // clang-format off # define DECL_TRACE_METHOD_A(tp) virtual void trace(const tp& object, const sc_string& name); # define DECL_TRACE_METHOD_B(tp) \ virtual void trace(const tp& object, const sc_string& name, int width); virtual void write_comment(const sc_string&); virtual void trace(const unsigned int&, const sc_string&, const char**); DECL_TRACE_METHOD_A( bool ) DECL_TRACE_METHOD_B( unsigned char ) DECL_TRACE_METHOD_B( short unsigned int ) DECL_TRACE_METHOD_B( unsigned int ) DECL_TRACE_METHOD_B( long unsigned int ) DECL_TRACE_METHOD_B( char ) DECL_TRACE_METHOD_B( short int ) DECL_TRACE_METHOD_B( int ) DECL_TRACE_METHOD_B( long int ) DECL_TRACE_METHOD_A( float ) DECL_TRACE_METHOD_A( double ) DECL_TRACE_METHOD_A( sc_bit ) DECL_TRACE_METHOD_A( sc_logic ) DECL_TRACE_METHOD_A( sc_bool_vector ) DECL_TRACE_METHOD_A( sc_logic_vector ) DECL_TRACE_METHOD_A( sc_signal_bool_vector ) DECL_TRACE_METHOD_A( sc_signal_logic_vector ) DECL_TRACE_METHOD_A( sc_uint_base ) DECL_TRACE_METHOD_A( sc_int_base ) DECL_TRACE_METHOD_A( sc_unsigned ) DECL_TRACE_METHOD_A( sc_signed ) DECL_TRACE_METHOD_A( sc_signal_resolved ) DECL_TRACE_METHOD_A( sc_signal_resolved_vector ) DECL_TRACE_METHOD_A( sc_bv_ns::sc_bv_base ) DECL_TRACE_METHOD_A( sc_bv_ns::sc_lv_base ) # endif // clang-format on #undef DECL_TRACE_METHOD_A #undef DECL_TRACE_METHOD_B }; #endif // Guard verilator-4.038/include/verilated_trace.h0000664000177100017500000003657413702133367020471 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Tracing functionality common to all formats /// //============================================================================= // SPDIFF_OFF #ifndef _VERILATED_TRACE_H_ #define _VERILATED_TRACE_H_ 1 // clang-format off #include "verilated.h" #include #include #ifdef VL_TRACE_THREADED # include # include # include #endif // clang-format on #ifdef VL_TRACE_THREADED //============================================================================= // Threaded tracing // A simple synchronized first in first out queue template class VerilatedThreadQueue { // LCOV_EXCL_LINE // lcov bug private: VerilatedMutex m_mutex; // Protects m_queue std::condition_variable_any m_cv; std::deque m_queue VL_GUARDED_BY(m_mutex); public: // Put an element at the back of the queue void put(T value) { VerilatedLockGuard lock(m_mutex); m_queue.push_back(value); m_cv.notify_one(); } // Put an element at the front of the queue void put_front(T value) { VerilatedLockGuard lock(m_mutex); m_queue.push_front(value); m_cv.notify_one(); } // Get an element from the front of the queue. Blocks if none available T get() { VerilatedLockGuard lock(m_mutex); m_cv.wait(lock, [this]() VL_REQUIRES(m_mutex) { return !m_queue.empty(); }); assert(!m_queue.empty()); T value = m_queue.front(); m_queue.pop_front(); return value; } // Non blocking get bool tryGet(T& result) { const VerilatedLockGuard lockGuard(m_mutex); if (m_queue.empty()) { return false; } result = m_queue.front(); m_queue.pop_front(); return true; } }; // Commands used by thread tracing. Anonymous enum in class, as we want // it scoped, but we also want the automatic conversion to integer types. class VerilatedTraceCommand { public: // These must all fit in 4 bit at the moment, as the tracing routines // pack parameters in the top bits. enum { CHG_BIT_0 = 0x0, CHG_BIT_1 = 0x1, CHG_CDATA = 0x2, CHG_SDATA = 0x3, CHG_IDATA = 0x4, CHG_QDATA = 0x5, CHG_WDATA = 0x6, CHG_DOUBLE = 0x8, // TODO: full.. TIME_CHANGE = 0xd, END = 0xe, // End of buffer SHUTDOWN = 0xf // Shutdown worker thread, also marks end of buffer }; }; #endif //============================================================================= // VerilatedTrace // VerilatedTrace uses F-bounded polymorphism to access duck-typed // implementations in the format specific derived class, which must be passed // as the type parameter T_Derived template class VerilatedTrace { public: //========================================================================= // Generic tracing internals typedef void (*initCb_t)(void*, T_Derived*, uint32_t); // Type of init callbacks typedef void (*dumpCb_t)(void*, T_Derived*); // Type of all but init callbacks private: struct CallbackRecord { // Note: would make these fields const, but some old STL implementations // (the one in Ubuntu 14.04 with GCC 4.8.4 in particular) use the // assignment operator on inserting into collections, so they don't work // with const fields... union { initCb_t m_initCb; // The callback function dumpCb_t m_dumpCb; // The callback function }; void* m_userp; // The user pointer to pass to the callback (the symbol table) CallbackRecord(initCb_t cb, void* userp) : m_initCb(cb) , m_userp(userp) {} CallbackRecord(dumpCb_t cb, void* userp) : m_dumpCb(cb) , m_userp(userp) {} }; vluint32_t* m_sigs_oldvalp; ///< Old value store vluint64_t m_timeLastDump; ///< Last time we did a dump std::vector m_initCbs; ///< Routines to initialize traciong std::vector m_fullCbs; ///< Routines to perform full dump std::vector m_chgCbs; ///< Routines to perform incremental dump std::vector m_cleanupCbs; ///< Routines to call at the end of dump bool m_fullDump; ///< Whether a full dump is required on the next call to 'dump' vluint32_t m_nextCode; ///< Next code number to assign vluint32_t m_numSignals; ///< Number of distinct signals vluint32_t m_maxBits; ///< Number of bits in the widest signal std::string m_moduleName; ///< Name of module being trace initialized now char m_scopeEscape; double m_timeRes; ///< Time resolution (ns/ms etc) double m_timeUnit; ///< Time units (ns/ms etc) void addCallbackRecord(std::vector& cbVec, CallbackRecord& cbRec); // Equivalent to 'this' but is of the sub-type 'T_Derived*'. Use 'self()->' // to access duck-typed functions to avoid a virtual function call. T_Derived* self() { return static_cast(this); } // Flush any remaining data for this file static void onFlush(void* selfp) VL_MT_UNSAFE_ONE; // Close the file on termination static void onExit(void* selfp) VL_MT_UNSAFE_ONE; #ifdef VL_TRACE_THREADED // Number of total trace buffers that have been allocated vluint32_t m_numTraceBuffers; // Size of trace buffers size_t m_traceBufferSize; // Buffers handed to worker for processing VerilatedThreadQueue m_buffersToWorker; // Buffers returned from worker after processing VerilatedThreadQueue m_buffersFromWorker; // Get a new trace buffer that can be populated. May block if none available vluint32_t* getTraceBuffer(); // Write pointer into current buffer vluint32_t* m_traceBufferWritep; // End of trace buffer vluint32_t* m_traceBufferEndp; // The worker thread itself std::unique_ptr m_workerThread; // The function executed by the worker thread void workerThreadMain(); // Wait until given buffer is placed in m_buffersFromWorker void waitForBuffer(const vluint32_t* bufferp); // Shut down and join worker, if it's running, otherwise do nothing void shutdownWorker(); #endif // CONSTRUCTORS VL_UNCOPYABLE(VerilatedTrace); protected: //========================================================================= // Internals available to format specific implementations VerilatedAssertOneThread m_assertOne; ///< Assert only called from single thread vluint32_t nextCode() const { return m_nextCode; } vluint32_t numSignals() const { return m_numSignals; } vluint32_t maxBits() const { return m_maxBits; } const std::string& moduleName() const { return m_moduleName; } void fullDump(bool value) { m_fullDump = value; } vluint64_t timeLastDump() { return m_timeLastDump; } double timeRes() const { return m_timeRes; } double timeUnit() const { return m_timeUnit; } std::string timeResStr() const; std::string timeUnitStr() const; void traceInit() VL_MT_UNSAFE; void declCode(vluint32_t code, vluint32_t bits, bool tri); /// Is this an escape? bool isScopeEscape(char c) { return isspace(c) || c == m_scopeEscape; } /// Character that splits scopes. Note whitespace are ALWAYS escapes. char scopeEscape() { return m_scopeEscape; } void close(); void flush(); //========================================================================= // Virtual functions to be provided by the format specific implementation // Called when the trace moves forward to a new time point virtual void emitTimeChange(vluint64_t timeui) = 0; // These hooks are called before a full or change based dump is produced. // The return value indicates whether to proceed with the dump. virtual bool preFullDump() = 0; virtual bool preChangeDump() = 0; public: //========================================================================= // External interface to client code explicit VerilatedTrace(); ~VerilatedTrace(); // Set time units (s/ms, defaults to ns) void set_time_unit(const char* unitp); void set_time_unit(const std::string& unit); // Set time resolution (s/ms, defaults to ns) void set_time_resolution(const char* unitp); void set_time_resolution(const std::string& unit); // Call void dump(vluint64_t timeui); //========================================================================= // Non-hot path internal interface to Verilator generated code void addInitCb(initCb_t cb, void* userp) VL_MT_UNSAFE_ONE; void addFullCb(dumpCb_t cb, void* userp) VL_MT_UNSAFE_ONE; void addChgCb(dumpCb_t cb, void* userp) VL_MT_UNSAFE_ONE; void addCleanupCb(dumpCb_t cb, void* userp) VL_MT_UNSAFE_ONE; void changeThread() { m_assertOne.changeThread(); } void module(const std::string& name) VL_MT_UNSAFE_ONE { m_assertOne.check(); m_moduleName = name; } void scopeEscape(char flag) { m_scopeEscape = flag; } //========================================================================= // Hot path internal interface to Verilator generated code // Implementation note: We rely on the following duck-typed implementations // in the derived class T_Derived. These emit* functions record a format // specific trace entry. Normally one would use pure virtual functions for // these here, but we cannot afford dynamic dispatch for calling these as // this is very hot code during tracing. // duck-typed void emitBit(vluint32_t code, CData newval) = 0; // duck-typed void emitCData(vluint32_t code, CData newval, int bits) = 0; // duck-typed void emitSData(vluint32_t code, SData newval, int bits) = 0; // duck-typed void emitIData(vluint32_t code, IData newval, int bits) = 0; // duck-typed void emitQData(vluint32_t code, QData newval, int bits) = 0; // duck-typed void emitWData(vluint32_t code, const WData* newvalp, int bits) = 0; // duck-typed void emitDouble(vluint32_t code, double newval) = 0; vluint32_t* oldp(vluint32_t code) { return m_sigs_oldvalp + code; } // Write to previous value buffer value and emit trace entry. void fullBit(vluint32_t* oldp, CData newval); void fullCData(vluint32_t* oldp, CData newval, int bits); void fullSData(vluint32_t* oldp, SData newval, int bits); void fullIData(vluint32_t* oldp, IData newval, int bits); void fullQData(vluint32_t* oldp, QData newval, int bits); void fullWData(vluint32_t* oldp, const WData* newvalp, int bits); void fullDouble(vluint32_t* oldp, double newval); #ifdef VL_TRACE_THREADED // Threaded tracing. Just dump everything in the trace buffer inline void chgBit(vluint32_t code, CData newval) { m_traceBufferWritep[0] = VerilatedTraceCommand::CHG_BIT_0 | newval; m_traceBufferWritep[1] = code; m_traceBufferWritep += 2; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } inline void chgCData(vluint32_t code, CData newval, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_CDATA; m_traceBufferWritep[1] = code; m_traceBufferWritep[2] = newval; m_traceBufferWritep += 3; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } inline void chgSData(vluint32_t code, SData newval, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_SDATA; m_traceBufferWritep[1] = code; m_traceBufferWritep[2] = newval; m_traceBufferWritep += 3; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } inline void chgIData(vluint32_t code, IData newval, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_IDATA; m_traceBufferWritep[1] = code; m_traceBufferWritep[2] = newval; m_traceBufferWritep += 3; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } inline void chgQData(vluint32_t code, QData newval, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_QDATA; m_traceBufferWritep[1] = code; *reinterpret_cast(m_traceBufferWritep + 2) = newval; m_traceBufferWritep += 4; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } inline void chgWData(vluint32_t code, const WData* newvalp, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_WDATA; m_traceBufferWritep[1] = code; m_traceBufferWritep += 2; for (int i = 0; i < (bits + 31) / 32; ++i) { *m_traceBufferWritep++ = newvalp[i]; } VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } inline void chgDouble(vluint32_t code, double newval) { m_traceBufferWritep[0] = VerilatedTraceCommand::CHG_DOUBLE; m_traceBufferWritep[1] = code; // cppcheck-suppress invalidPointerCast *reinterpret_cast(m_traceBufferWritep + 2) = newval; m_traceBufferWritep += 4; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } #define CHG(name) chg##name##Impl #else #define CHG(name) chg##name #endif // In non-threaded mode, these are called directly by the trace callbacks, // and are called chg*. In threaded mode, they are called by the worker // thread and are called chg*Impl // Check previous dumped value of signal. If changed, then emit trace entry inline void CHG(Bit)(vluint32_t* oldp, CData newval) { const vluint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullBit(oldp, newval); } inline void CHG(CData)(vluint32_t* oldp, CData newval, int bits) { const vluint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullCData(oldp, newval, bits); } inline void CHG(SData)(vluint32_t* oldp, SData newval, int bits) { const vluint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullSData(oldp, newval, bits); } inline void CHG(IData)(vluint32_t* oldp, IData newval, int bits) { const vluint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullIData(oldp, newval, bits); } inline void CHG(QData)(vluint32_t* oldp, QData newval, int bits) { const vluint64_t diff = *reinterpret_cast(oldp) ^ newval; if (VL_UNLIKELY(diff)) fullQData(oldp, newval, bits); } inline void CHG(WData)(vluint32_t* oldp, const WData* newvalp, int bits) { for (int i = 0; i < (bits + 31) / 32; ++i) { if (VL_UNLIKELY(oldp[i] ^ newvalp[i])) { fullWData(oldp, newvalp, bits); return; } } } inline void CHG(Double)(vluint32_t* oldp, double newval) { // cppcheck-suppress invalidPointerCast if (VL_UNLIKELY(*reinterpret_cast(oldp) != newval)) fullDouble(oldp, newval); } #undef CHG }; #endif // guard verilator-4.038/include/verilated_unordered_set_map.h0000664000177100017500000004226113702133367023060 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // DESCRIPTION: Verilator: pre-C++11 replacements for std::unordered_set // and std::unordered_map. // // Code available from: https://verilator.org // //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* //************************************************************************* // This file has clones of the std::unordered_set and std::unordered_map // hash table types. They are here so that Verilator can use hash tables // in pre-C++11 compilers, and the same client code can link against the // std:: types when they are available. // // The implementations in this file do not implement the complete APIs // of the std:: types. Nor are they correct in every detail, // notably, the const_iterators do not enforce constness. We can extend // these implementations to cover more of the std API as needed. // // TODO: In the future, when Verilator requires C++11 to compile, // remove this entire file and switch to the std:: types. // //************************************************************************* #ifndef _VERILATED_UNORDERED_SET_MAP_H_ #define _VERILATED_UNORDERED_SET_MAP_H_ #include "verilatedos.h" #include #include #include // Abstract 'vl_hash' and 'vl_equal_to' templates. template struct vl_hash { size_t operator()(const T& k) const; }; template struct vl_equal_to { bool operator()(const T& a, const T& b) const; }; // Specializations of 'vl_hash' and 'vl_equal_to'. inline size_t vl_hash_bytes(const void* vbufp, size_t nbytes) { const vluint8_t* bufp = static_cast(vbufp); size_t hash = 0; for (size_t i = 0; i < nbytes; i++) { hash = bufp[i] + 31U * hash; // the K&R classic! } return hash; } template <> inline size_t vl_hash::operator()(const int& k) const { return k; } template <> inline bool vl_equal_to::operator()(const int& a, const int& b) const { return a == b; } template <> inline size_t vl_hash::operator()(const unsigned int& k) const { return k; } template <> inline bool vl_equal_to::operator()(const unsigned int& a, const unsigned int& b) const { return a == b; } template <> inline size_t vl_hash::operator()(const std::string& k) const { return vl_hash_bytes(k.data(), k.size()); } template <> inline bool vl_equal_to::operator()(const std::string& a, const std::string& b) const { // Don't scan the strings if the sizes are different. if (a.size() != b.size()) return false; return (0 == a.compare(b)); // Must scan. } template struct vl_hash { size_t operator()(T* kp) const { return ((sizeof(size_t) == sizeof(kp)) ? reinterpret_cast(kp) : vl_hash_bytes(&kp, sizeof(kp))); } }; template struct vl_equal_to { bool operator()(T* ap, T* bp) const { return ap == bp; } }; //=================================================================== // /// Functional clone of the std::unordered_set hash table. template , class T_Equal = vl_equal_to > class vl_unordered_set { public: // TYPES typedef std::list Bucket; enum RehashType { GROW, SHRINK }; template friend class vl_unordered_map; class iterator { protected: // MEMBERS size_t m_bucketIdx; // Bucket this iterator points into typename Bucket::iterator m_bit; // Bucket-local iterator const vl_unordered_set* m_setp; // The containing set public: // CONSTRUCTORS iterator(size_t bucketIdx, typename Bucket::iterator bit, const vl_unordered_set* setp) : m_bucketIdx(bucketIdx) , m_bit(bit) , m_setp(setp) {} // METHODS const T_Key& operator*() const { return *m_bit; } // This should really be 'const T_Key*' type for unordered_set, // however this iterator is shared with unordered_map whose // operator-> returns a non-const ValueType*, so keep this // non-const to avoid having to define a whole separate iterator // for unordered_map. T_Key* operator->() const { return &(*m_bit); } bool operator==(const iterator& other) const { return ((m_bucketIdx == other.m_bucketIdx) && (m_bit == other.m_bit)); } bool operator!=(const iterator& other) const { return (!this->operator==(other)); } void advanceUntilValid() { while (true) { if (m_bit != m_setp->m_bucketsp[m_bucketIdx].end()) { // Valid iterator in this bucket; we're done. return; } // Try the next bucket? m_bucketIdx++; if (m_bucketIdx == m_setp->numBuckets()) { // Ran past the end of buckets, set to end(). *this = m_setp->end(); return; } m_bit = m_setp->m_bucketsp[m_bucketIdx].begin(); } } void operator++() { ++m_bit; advanceUntilValid(); } typename Bucket::iterator bit() const { return m_bit; } }; // TODO: there's no real const enforcement on the 'const_iterator'. typedef iterator const_iterator; private: // MEMBERS size_t m_numElements; // Number of entries present. size_t m_log2Buckets; // Log-base-2 of the number of buckets. mutable Bucket* m_bucketsp; // Hash table buckets. May be NULL; // // we'll allocate it on the fly when // // the first entries are created. Bucket m_emptyBucket; // A fake bucket, used to construct end(). T_Hash m_hash; // Hash function provider. T_Equal m_equal; // Equal-to function provider. public: // CONSTRUCTORS vl_unordered_set() : m_numElements(0) , m_log2Buckets(initLog2Buckets()) , m_bucketsp(NULL) , m_hash() , m_equal() {} vl_unordered_set(const vl_unordered_set& other) : m_numElements(other.m_numElements) , m_log2Buckets(other.m_log2Buckets) , m_bucketsp(NULL) , m_hash() , m_equal() { if (other.m_bucketsp) { m_bucketsp = new Bucket[numBuckets()]; for (size_t i = 0; i < numBuckets(); i++) m_bucketsp[i] = other.m_bucketsp[i]; } } ~vl_unordered_set() { VL_DO_DANGLING(delete[] m_bucketsp, m_bucketsp); } vl_unordered_set& operator=(const vl_unordered_set& other) { if (this != &other) { clear(); delete[] m_bucketsp; m_numElements = other.m_numElements; m_log2Buckets = other.m_log2Buckets; if (other.m_bucketsp) { m_bucketsp = new Bucket[numBuckets()]; for (size_t i = 0; i < numBuckets(); i++) m_bucketsp[i] = other.m_bucketsp[i]; } else { m_bucketsp = NULL; } } return *this; } // METHODS static size_t initLog2Buckets() { return 4; } iterator begin() { if (m_numElements) { initBuckets(); iterator result = iterator(0, m_bucketsp[0].begin(), this); result.advanceUntilValid(); return result; } return end(); } const_iterator begin() const { if (m_numElements) { initBuckets(); const_iterator result = iterator(0, m_bucketsp[0].begin(), this); result.advanceUntilValid(); return result; } return end(); } const_iterator end() const { return iterator(0xFFFFFFFFFFFFFFFFULL, const_cast(m_emptyBucket).begin(), this); } bool empty() const { return m_numElements == 0; } size_t size() const { return m_numElements; } size_t count(const T_Key& key) const { return (find(key) == end()) ? 0 : 1; } size_t hashToBucket(size_t hashVal) const { return hashToBucket(hashVal, m_log2Buckets); } static size_t hashToBucket(size_t hashVal, unsigned log2Buckets) { // Fibonacci hashing, see // https://probablydance.com/2018/06/16/fibonacci-hashing-the-optimization // -that-the-world-forgot-or-a-better-alternative-to-integer-modulo/ // // * The magic numbers below are UINT_MAX/phi where phi is the // golden ratio number (1.618...) for either 64- or 32-bit // values of UINT_MAX. // // * Fibonacci hashing mixes the result of the client's hash // function further. This permits the use of very fast client // hash funcs (like just returning the int or pointer value as // is!) and tolerates crappy client hash functions pretty well. size_t mult = hashVal * ((sizeof(size_t) == 8) ? 11400714819323198485ULL : 2654435769lu); size_t result = (mult >> (((sizeof(size_t) == 8) ? 64 : 32) - log2Buckets)); return result; } iterator find_internal(const T_Key& key, size_t& bucketIdxOut) { size_t hash = m_hash.operator()(key); bucketIdxOut = hashToBucket(hash); initBuckets(); Bucket* bucketp = &m_bucketsp[bucketIdxOut]; for (typename Bucket::iterator it = bucketp->begin(); it != bucketp->end(); ++it) { if (m_equal.operator()(*it, key)) return iterator(bucketIdxOut, it, this); } return end(); } const_iterator find(const T_Key& key) const { size_t bucketIdx; return const_cast(this)->find_internal(key, bucketIdx); } iterator find(const T_Key& key) { size_t bucketIdx; return find_internal(key, bucketIdx); } std::pair insert(const T_Key& val) { size_t bucketIdx; iterator existIt = find_internal(val, bucketIdx); if (existIt != end()) { // Collision with existing element. // // An element may be inserted only if it is not // equal to an existing element. So fail. return std::pair(end(), false); } // No collision, so insert it. m_numElements++; m_bucketsp[bucketIdx].push_front(val); // Compute result iterator. This pointer will be valid // if we don't rehash: iterator result_it(bucketIdx, m_bucketsp[bucketIdx].begin(), this); if (needToRehash(GROW)) { rehash(GROW); // ... since we rehashed, do a lookup to get the result iterator. result_it = find(val); } return std::pair(result_it, true); } iterator erase(iterator it) { iterator next_it = it; ++next_it; erase(*it); return next_it; } size_t erase(const T_Key& key) { size_t bucketIdx; iterator it = find_internal(key, bucketIdx); if (it != end()) { m_bucketsp[bucketIdx].erase(it.bit()); m_numElements--; // Rehashing to handle a shrinking data set is important // for the Scoreboard in V3Partition, which begins tracking // a huge number of vertices and then tracks a successively // smaller number over time. if (needToRehash(SHRINK)) rehash(SHRINK); return 1; } return 0; } void clear() { if (m_bucketsp) { delete[] m_bucketsp; m_bucketsp = NULL; } m_numElements = 0; m_log2Buckets = initLog2Buckets(); } private: size_t numBuckets() const { return (1ULL << m_log2Buckets); } Bucket* getBucket(size_t idx) { initBuckets(); return &m_bucketsp[idx]; } void initBuckets() const { if (!m_bucketsp) m_bucketsp = new Bucket[numBuckets()]; } bool needToRehash(RehashType rt) const { if (rt == GROW) { return ((4 * numBuckets()) < m_numElements); } else { return (numBuckets() > (4 * m_numElements)); } } void rehash(RehashType rt) { size_t new_log2Buckets; if (rt == GROW) { new_log2Buckets = m_log2Buckets + 2; } else { if (m_log2Buckets <= 4) { // On shrink, saturate m_log2Buckets at its // initial size of 2^4 == 16 buckets. Don't risk // underflowing! return; } new_log2Buckets = m_log2Buckets - 2; } size_t new_num_buckets = 1ULL << new_log2Buckets; Bucket* new_bucketsp = new Bucket[new_num_buckets]; for (size_t i = 0; i < numBuckets(); i++) { while (!m_bucketsp[i].empty()) { typename Bucket::iterator bit = m_bucketsp[i].begin(); size_t hash = m_hash.operator()(*bit); size_t new_idx = hashToBucket(hash, new_log2Buckets); // Avoid mallocing one list elem and freeing another; // splice just moves it over. new_bucketsp[new_idx].splice(new_bucketsp[new_idx].begin(), m_bucketsp[i], bit); } } delete[] m_bucketsp; m_bucketsp = new_bucketsp; m_log2Buckets = new_log2Buckets; } }; //=================================================================== // /// Functional clone of the std::unordered_map hash table. template , class T_Equal = vl_equal_to > class vl_unordered_map { private: // TYPES typedef std::pair KeyValPair; class KeyHash { private: T_Hash key_hash; public: KeyHash() {} size_t operator()(const KeyValPair& kv_pair) const { return key_hash.operator()(kv_pair.first); } }; class KeyEqual { private: T_Equal key_eq; public: KeyEqual() {} bool operator()(const KeyValPair& kv_a, const KeyValPair& kv_b) const { return key_eq.operator()(kv_a.first, kv_b.first); } }; // MEMBERS typedef vl_unordered_set MapSet; MapSet m_set; // Wrap this vl_unordered_set which holds all state. public: // CONSTRUCTORS vl_unordered_map() {} ~vl_unordered_map() {} typedef typename MapSet::iterator iterator; typedef typename MapSet::const_iterator const_iterator; // METHODS iterator begin() { return m_set.begin(); } const_iterator begin() const { return m_set.begin(); } const_iterator end() const { return m_set.end(); } bool empty() const { return m_set.empty(); } iterator find(const T_Key& k) { // We can't assume that T_Value() is defined. // ie, this does not work: // return m_set.find(std::make_pair(k, T_Value())); // So, do this instead: T_Hash mapHash; T_Equal mapEq; size_t hash = mapHash.operator()(k); size_t bucketIdxOut = m_set.hashToBucket(hash); typename MapSet::Bucket* bucketp = m_set.getBucket(bucketIdxOut); for (typename MapSet::Bucket::iterator it = bucketp->begin(); it != bucketp->end(); ++it) { if (mapEq.operator()(it->first, k)) return iterator(bucketIdxOut, it, &m_set); } return end(); } const_iterator find(const T_Key& k) const { return const_cast(this)->find(k); } std::pair insert(const KeyValPair& val) { return m_set.insert(val); } iterator erase(iterator it) { return m_set.erase(it); } size_t erase(const T_Key& k) { iterator it = find(k); if (it == end()) return 0; m_set.erase(it); return 1; } T_Value& operator[](const T_Key& k) { // Here we can assume T_Value() is defined, as // std::unordered_map::operator[] relies on it too. KeyValPair dummy = std::make_pair(k, T_Value()); iterator it = m_set.find(dummy); if (it == m_set.end()) it = m_set.insert(dummy).first; // For the 'set', it's generally not safe to modify // the value after deref. For the 'map' though, we know // it's safe to modify the value field and we can allow it: return it->second; } T_Value& at(const T_Key& k) { iterator it = find(k); if (it == end()) { throw std::out_of_range("sorry"); } return it->second; } const T_Value& at(const T_Key& k) const { iterator it = find(k); if (it == end()) { throw std::out_of_range("sorry"); } return it->second; } void clear() { m_set.clear(); } size_t size() const { return m_set.size(); } }; #endif verilator-4.038/include/verilated_dpi.cpp0000664000177100017500000010250613702133367020467 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// /// \file /// \brief Verilator: DPI implementation code /// /// This file must be compiled and linked against all objects /// created from Verilator or called by Verilator that use the DPI. /// /// Code available from: https://verilator.org /// //========================================================================= #define _VERILATED_DPI_CPP_ #include "verilatedos.h" #include "verilated_dpi.h" #include "verilated_imp.h" // On MSVC++ we need svdpi.h to declare exports, not imports #define DPI_PROTOTYPES #undef XXTERN #define XXTERN DPI_EXTERN DPI_DLLESPEC #undef EETERN #define EETERN DPI_EXTERN DPI_DLLESPEC #include "vltstd/svdpi.h" //====================================================================== // Internal macros // Not supported yet #define _VL_SVDPI_UNIMP() \ VL_FATAL_MT(__FILE__, __LINE__, "", \ (std::string("%%Error: Unsupported DPI function: ") + VL_FUNC).c_str()) #define _VL_SVDPI_WARN(...) VL_PRINTF_MT(__VA_ARGS__) // Function requires a "context" in the import declaration #define _VL_SVDPI_CONTEXT_WARN() \ _VL_SVDPI_WARN("%%Warning: DPI C Function called by Verilog DPI import with missing " \ "'context' keyword.\n") //====================================================================== //====================================================================== //====================================================================== // DPI ROUTINES const char* svDpiVersion() { return "1800-2005"; } //====================================================================== // Bit-select utility functions. svBit svGetBitselBit(const svBitVecVal* sp, int bit) { return VL_BITRSHIFT_W(sp, bit) & 1; } svLogic svGetBitselLogic(const svLogicVecVal* sp, int bit) { // Not VL_BITRSHIFT_W as sp is a different structure type // Verilator doesn't support X/Z so only aval return (((sp[VL_BITWORD_I(bit)].aval >> VL_BITBIT_I(bit)) & 1) | (((sp[VL_BITWORD_I(bit)].bval >> VL_BITBIT_I(bit)) & 1) << 1)); } void svPutBitselBit(svBitVecVal* dp, int bit, svBit s) { VL_ASSIGNBIT_WI(32, bit, dp, s); } void svPutBitselLogic(svLogicVecVal* dp, int bit, svLogic s) { // Verilator doesn't support X/Z so only aval dp[VL_BITWORD_I(bit)].aval = ((dp[VL_BITWORD_I(bit)].aval & ~(VL_UL(1) << VL_BITBIT_I(bit))) | ((s & 1) << VL_BITBIT_I(bit))); dp[VL_BITWORD_I(bit)].bval = ((dp[VL_BITWORD_I(bit)].bval & ~(VL_UL(1) << VL_BITBIT_I(bit))) | ((s & 2) >> 1 << VL_BITBIT_I(bit))); } void svGetPartselBit(svBitVecVal* dp, const svBitVecVal* sp, int lsb, int width) { // See also VL_SEL_WWI int msb = lsb + width - 1; int word_shift = VL_BITWORD_I(lsb); if (VL_BITBIT_I(lsb) == 0) { // Just a word extract for (int i = 0; i < VL_WORDS_I(width); ++i) dp[i] = sp[i + word_shift]; } else { int loffset = lsb & VL_SIZEBITS_I; int nbitsfromlow = 32 - loffset; // bits that end up in lword (know loffset!=0) // Middle words int words = VL_WORDS_I(msb - lsb + 1); for (int i = 0; i < words; ++i) { dp[i] = sp[i + word_shift] >> loffset; int upperword = i + word_shift + 1; if (upperword <= static_cast(VL_BITWORD_I(msb))) { dp[i] |= sp[upperword] << nbitsfromlow; } } } // Clean result dp[VL_WORDS_I(width) - 1] &= VL_MASK_I(width); } void svGetPartselLogic(svLogicVecVal* dp, const svLogicVecVal* sp, int lsb, int width) { int msb = lsb + width - 1; int word_shift = VL_BITWORD_I(lsb); if (VL_BITBIT_I(lsb) == 0) { // Just a word extract for (int i = 0; i < VL_WORDS_I(width); ++i) dp[i] = sp[i + word_shift]; } else { int loffset = lsb & VL_SIZEBITS_I; int nbitsfromlow = 32 - loffset; // bits that end up in lword (know loffset!=0) // Middle words int words = VL_WORDS_I(msb - lsb + 1); for (int i = 0; i < words; ++i) { dp[i].aval = sp[i + word_shift].aval >> loffset; dp[i].bval = sp[i + word_shift].bval >> loffset; int upperword = i + word_shift + 1; if (upperword <= static_cast(VL_BITWORD_I(msb))) { dp[i].aval |= sp[upperword].aval << nbitsfromlow; dp[i].bval |= sp[upperword].bval << nbitsfromlow; } } } // Clean result dp[VL_WORDS_I(width) - 1].aval &= VL_MASK_I(width); dp[VL_WORDS_I(width) - 1].bval &= VL_MASK_I(width); } void svPutPartselBit(svBitVecVal* dp, const svBitVecVal s, int lbit, int width) { // See also _VL_INSERT_WI int hbit = lbit + width - 1; int hoffset = VL_BITBIT_I(hbit); int loffset = VL_BITBIT_I(lbit); if (hoffset == VL_SIZEBITS_I && loffset == 0) { // Fast and common case, word based insertion dp[VL_BITWORD_I(lbit)] = s; } else { int hword = VL_BITWORD_I(hbit); int lword = VL_BITWORD_I(lbit); if (hword == lword) { // know < 32 bits because above checks it IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset; dp[lword] = (dp[lword] & ~insmask) | ((s << loffset) & insmask); } else { IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0; IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset; int nbitsonright = 32 - loffset; // bits that end up in lword dp[lword] = (dp[lword] & ~linsmask) | ((s << loffset) & linsmask); dp[hword] = (dp[hword] & ~hinsmask) | ((s >> nbitsonright) & hinsmask); } } } // cppcheck-suppress passedByValue void svPutPartselLogic(svLogicVecVal* dp, const svLogicVecVal s, int lbit, int width) { int hbit = lbit + width - 1; int hoffset = VL_BITBIT_I(hbit); int loffset = VL_BITBIT_I(lbit); if (hoffset == VL_SIZEBITS_I && loffset == 0) { // Fast and common case, word based insertion dp[VL_BITWORD_I(lbit)].aval = s.aval; dp[VL_BITWORD_I(lbit)].bval = s.bval; } else { int hword = VL_BITWORD_I(hbit); int lword = VL_BITWORD_I(lbit); if (hword == lword) { // know < 32 bits because above checks it IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset; dp[lword].aval = (dp[lword].aval & ~insmask) | ((s.aval << loffset) & insmask); dp[lword].bval = (dp[lword].bval & ~insmask) | ((s.bval << loffset) & insmask); } else { IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0; IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset; int nbitsonright = 32 - loffset; // bits that end up in lword dp[lword].aval = (dp[lword].aval & ~linsmask) | ((s.aval << loffset) & linsmask); dp[lword].bval = (dp[lword].bval & ~linsmask) | ((s.bval << loffset) & linsmask); dp[hword].aval = (dp[hword].aval & ~hinsmask) | ((s.aval >> nbitsonright) & hinsmask); dp[hword].bval = (dp[hword].bval & ~hinsmask) | ((s.bval >> nbitsonright) & hinsmask); } } } //====================================================================== // Open array internals static inline const VerilatedDpiOpenVar* _vl_openhandle_varp(const svOpenArrayHandle h) { if (VL_UNLIKELY(!h)) { VL_FATAL_MT(__FILE__, __LINE__, "", "%%Error: DPI svOpenArrayHandle function called with NULL handle"); } const VerilatedDpiOpenVar* varp = reinterpret_cast(h); if (VL_UNLIKELY(!varp->magicOk())) { VL_FATAL_MT(__FILE__, __LINE__, "", "%%Error: DPI svOpenArrayHandle function called with non-Verilator handle"); } return varp; } //====================================================================== // Open array querying functions int svLeft(const svOpenArrayHandle h, int d) { return _vl_openhandle_varp(h)->left(d); } int svRight(const svOpenArrayHandle h, int d) { return _vl_openhandle_varp(h)->right(d); } int svLow(const svOpenArrayHandle h, int d) { return _vl_openhandle_varp(h)->low(d); } int svHigh(const svOpenArrayHandle h, int d) { return _vl_openhandle_varp(h)->high(d); } int svIncrement(const svOpenArrayHandle h, int d) { return _vl_openhandle_varp(h)->increment(d); } int svSize(const svOpenArrayHandle h, int d) { return _vl_openhandle_varp(h)->elements(d); } int svDimensions(const svOpenArrayHandle h) { return _vl_openhandle_varp(h)->udims(); } /// Return pointer to open array data, or NULL if not in IEEE standard C layout void* svGetArrayPtr(const svOpenArrayHandle h) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h); if (VL_UNLIKELY(!varp->isDpiStdLayout())) return NULL; return varp->datap(); } /// Return size of open array, or 0 if not in IEEE standard C layout int svSizeOfArray(const svOpenArrayHandle h) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h); if (VL_UNLIKELY(!varp->isDpiStdLayout())) return 0; // Truncate 64 bits to int; DPI is limited to 4GB return static_cast(varp->totalSize()); } //====================================================================== // Open array access internals static void* _vl_sv_adjusted_datap(const VerilatedDpiOpenVar* varp, int nargs, int indx1, int indx2, int indx3) { void* datap = varp->datap(); if (VL_UNLIKELY(nargs != varp->udims())) { _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function called on" " %d dimensional array using %d dimensional function.\n", varp->udims(), nargs); return NULL; } if (nargs >= 1) { datap = varp->datapAdjustIndex(datap, 1, indx1); if (VL_UNLIKELY(!datap)) { _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function index 1 " "out of bounds; %d outside [%d:%d].\n", indx1, varp->left(1), varp->right(1)); return NULL; } } if (nargs >= 2) { datap = varp->datapAdjustIndex(datap, 2, indx2); if (VL_UNLIKELY(!datap)) { _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function index 2 " "out of bounds; %d outside [%d:%d].\n", indx2, varp->left(2), varp->right(2)); return NULL; } } if (nargs >= 3) { datap = varp->datapAdjustIndex(datap, 3, indx3); if (VL_UNLIKELY(!datap)) { _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function index 3 " "out of bounds; %d outside [%d:%d].\n", indx1, varp->left(3), varp->right(3)); return NULL; } } return datap; } static int _vl_sv_adjusted_bit(const VerilatedDpiOpenVar* varp, int indx) { if (VL_UNLIKELY(indx < varp->low(0) || indx > varp->high(0))) { _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function packed index out of bounds; %d " "outside [%d:%d].\n", indx, varp->left(0), varp->right(0)); return 0; } return indx - varp->low(0); } /// Return pointer to simulator open array element, or NULL if outside range static void* _vl_svGetArrElemPtr(const svOpenArrayHandle h, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h); if (VL_UNLIKELY(!varp->isDpiStdLayout())) return NULL; void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3); return datap; } /// Copy to user bit array from simulator open array static void _vl_svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s); void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3); if (VL_UNLIKELY(!datap)) return; switch (varp->vltype()) { case VLVT_UINT8: d[0] = *(reinterpret_cast(datap)); return; case VLVT_UINT16: d[0] = *(reinterpret_cast(datap)); return; case VLVT_UINT32: d[0] = *(reinterpret_cast(datap)); return; case VLVT_UINT64: { WData lwp[2]; VL_SET_WQ(lwp, *(reinterpret_cast(datap))); d[0] = lwp[0]; d[1] = lwp[1]; break; } case VLVT_WDATA: { WDataOutP wdatap = (reinterpret_cast(datap)); for (int i = 0; i < VL_WORDS_I(varp->packed().elements()); ++i) d[i] = wdatap[i]; return; } default: _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function unsupported datatype (%d).\n", varp->vltype()); return; } } /// Copy to user logic array from simulator open array static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandle s, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s); void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3); if (VL_UNLIKELY(!datap)) return; switch (varp->vltype()) { case VLVT_UINT8: d[0].aval = *(reinterpret_cast(datap)); d[0].bval = 0; return; case VLVT_UINT16: d[0].aval = *(reinterpret_cast(datap)); d[0].bval = 0; return; case VLVT_UINT32: d[0].aval = *(reinterpret_cast(datap)); d[0].bval = 0; return; case VLVT_UINT64: { WData lwp[2]; VL_SET_WQ(lwp, *(reinterpret_cast(datap))); d[0].aval = lwp[0]; d[0].bval = 0; d[1].aval = lwp[1]; d[0].bval = 0; break; } case VLVT_WDATA: { WDataOutP wdatap = (reinterpret_cast(datap)); for (int i = 0; i < VL_WORDS_I(varp->packed().elements()); ++i) { d[i].aval = wdatap[i]; d[i].bval = 0; } return; } default: _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function unsupported datatype (%d).\n", varp->vltype()); return; } } /// Copy to simulator open array from from user bit array static void _vl_svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecVal* s, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d); void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3); if (VL_UNLIKELY(!datap)) return; switch (varp->vltype()) { case VLVT_UINT8: *(reinterpret_cast(datap)) = s[0]; return; case VLVT_UINT16: *(reinterpret_cast(datap)) = s[0]; return; case VLVT_UINT32: *(reinterpret_cast(datap)) = s[0]; return; case VLVT_UINT64: *(reinterpret_cast(datap)) = _VL_SET_QII(s[1], s[0]); break; case VLVT_WDATA: { WDataOutP wdatap = (reinterpret_cast(datap)); for (int i = 0; i < VL_WORDS_I(varp->packed().elements()); ++i) wdatap[i] = s[i]; return; } default: _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function unsupported datatype (%d).\n", varp->vltype()); return; } } /// Copy to simulator open array from from user logic array static void _vl_svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d); void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3); if (VL_UNLIKELY(!datap)) return; switch (varp->vltype()) { case VLVT_UINT8: *(reinterpret_cast(datap)) = s[0].aval; return; case VLVT_UINT16: *(reinterpret_cast(datap)) = s[0].aval; return; case VLVT_UINT32: *(reinterpret_cast(datap)) = s[0].aval; return; case VLVT_UINT64: *(reinterpret_cast(datap)) = _VL_SET_QII(s[1].aval, s[0].aval); break; case VLVT_WDATA: { WDataOutP wdatap = (reinterpret_cast(datap)); for (int i = 0; i < VL_WORDS_I(varp->packed().elements()); ++i) wdatap[i] = s[i].aval; return; } default: _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function unsupported datatype (%d).\n", varp->vltype()); return; } } /// Return bit from simulator open array static svBit _vl_svGetBitArrElem(const svOpenArrayHandle s, int nargs, int indx1, int indx2, int indx3, int indx4) VL_MT_SAFE { // One extra index supported, as need bit number const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s); void* datap; int lsb; if (varp->packed().elements()) { datap = _vl_sv_adjusted_datap(varp, nargs - 1, indx1, indx2, indx3); lsb = _vl_sv_adjusted_bit( varp, ((nargs == 1) ? indx1 : (nargs == 2) ? indx2 : (nargs == 3) ? indx3 : indx4)); } else { datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3); lsb = 0; } if (VL_UNLIKELY(!datap)) return 0; switch (varp->vltype()) { case VLVT_UINT8: return (*(reinterpret_cast(datap)) >> lsb) & 1; case VLVT_UINT16: return (*(reinterpret_cast(datap)) >> lsb) & 1; case VLVT_UINT32: return (*(reinterpret_cast(datap)) >> lsb) & 1; case VLVT_UINT64: return (*(reinterpret_cast(datap)) >> static_cast(lsb)) & 1ULL; case VLVT_WDATA: { WDataOutP wdatap = (reinterpret_cast(datap)); return VL_BITRSHIFT_W(wdatap, lsb) & 1; } default: _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function unsupported datatype (%d).\n", varp->vltype()); return 0; } } /// Update simulator open array from bit static void _vl_svPutBitArrElem(const svOpenArrayHandle d, svBit value, int nargs, int indx1, int indx2, int indx3, int indx4) VL_MT_SAFE { // One extra index supported, as need bit number value &= 1; // Make sure clean const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d); void* datap; int lsb; if (varp->packed().elements()) { datap = _vl_sv_adjusted_datap(varp, nargs - 1, indx1, indx2, indx3); lsb = _vl_sv_adjusted_bit( varp, ((nargs == 1) ? indx1 : (nargs == 2) ? indx2 : (nargs == 3) ? indx3 : indx4)); } else { datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3); lsb = 0; } if (VL_UNLIKELY(!datap)) return; switch (varp->vltype()) { case VLVT_UINT8: VL_ASSIGNBIT_II(-1, lsb, *(reinterpret_cast(datap)), value); return; case VLVT_UINT16: VL_ASSIGNBIT_II(-1, lsb, *(reinterpret_cast(datap)), value); return; case VLVT_UINT32: VL_ASSIGNBIT_II(-1, lsb, *(reinterpret_cast(datap)), value); return; case VLVT_UINT64: VL_ASSIGNBIT_QI(-1, lsb, *(reinterpret_cast(datap)), value); return; case VLVT_WDATA: VL_ASSIGNBIT_WI(-1, lsb, (reinterpret_cast(datap)), value); return; default: _VL_SVDPI_WARN("%%Warning: DPI svOpenArrayHandle function unsupported datatype (%d).\n", varp->vltype()); return; } } //====================================================================== // DPI accessors that simply call above functions void* svGetArrElemPtr(const svOpenArrayHandle h, int indx1, ...) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h); void* datap; va_list ap; va_start(ap, indx1); // va_arg is a macro, so need temporaries as used below switch (varp->udims()) { case 1: datap = _vl_svGetArrElemPtr(h, 1, indx1, 0, 0); break; case 2: { int indx2 = va_arg(ap, int); datap = _vl_svGetArrElemPtr(h, 2, indx1, indx2, 0); break; } case 3: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); datap = _vl_svGetArrElemPtr(h, 3, indx1, indx2, indx3); break; } default: datap = _vl_svGetArrElemPtr(h, -1, 0, 0, 0); break; // Will error } va_end(ap); return datap; } void* svGetArrElemPtr1(const svOpenArrayHandle h, int indx1) { return _vl_svGetArrElemPtr(h, 1, indx1, 0, 0); } void* svGetArrElemPtr2(const svOpenArrayHandle h, int indx1, int indx2) { return _vl_svGetArrElemPtr(h, 2, indx1, indx2, 0); } void* svGetArrElemPtr3(const svOpenArrayHandle h, int indx1, int indx2, int indx3) { return _vl_svGetArrElemPtr(h, 3, indx1, indx2, indx3); } void svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1, ...) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d); va_list ap; va_start(ap, indx1); switch (varp->udims()) { case 1: _vl_svPutBitArrElemVecVal(d, s, 1, indx1, 0, 0); break; case 2: { int indx2 = va_arg(ap, int); _vl_svPutBitArrElemVecVal(d, s, 2, indx1, indx2, 0); break; } case 3: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); _vl_svPutBitArrElemVecVal(d, s, 3, indx1, indx2, indx3); break; } default: _vl_svPutBitArrElemVecVal(d, s, -1, 0, 0, 0); break; // Will error } va_end(ap); } void svPutBitArrElem1VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1) { _vl_svPutBitArrElemVecVal(d, s, 1, indx1, 0, 0); } void svPutBitArrElem2VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1, int indx2) { _vl_svPutBitArrElemVecVal(d, s, 2, indx1, indx2, 0); } void svPutBitArrElem3VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1, int indx2, int indx3) { _vl_svPutBitArrElemVecVal(d, s, 3, indx1, indx2, indx3); } void svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1, ...) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d); va_list ap; va_start(ap, indx1); switch (varp->udims()) { case 1: _vl_svPutLogicArrElemVecVal(d, s, 1, indx1, 0, 0); break; case 2: { int indx2 = va_arg(ap, int); _vl_svPutLogicArrElemVecVal(d, s, 2, indx1, indx2, 0); break; } case 3: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); _vl_svPutLogicArrElemVecVal(d, s, 3, indx1, indx2, indx3); break; } default: _vl_svPutLogicArrElemVecVal(d, s, -1, 0, 0, 0); break; // Will error } va_end(ap); } void svPutLogicArrElem1VecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1) { _vl_svPutLogicArrElemVecVal(d, s, 1, indx1, 0, 0); } void svPutLogicArrElem2VecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1, int indx2) { _vl_svPutLogicArrElemVecVal(d, s, 2, indx1, indx2, 0); } void svPutLogicArrElem3VecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1, int indx2, int indx3) { _vl_svPutLogicArrElemVecVal(d, s, 3, indx1, indx2, indx3); } //====================================================================== // From simulator storage into user space void svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1, ...) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s); va_list ap; va_start(ap, indx1); switch (varp->udims()) { case 1: _vl_svGetBitArrElemVecVal(d, s, 1, indx1, 0, 0); break; case 2: { int indx2 = va_arg(ap, int); _vl_svGetBitArrElemVecVal(d, s, 2, indx1, indx2, 0); break; } case 3: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); _vl_svGetBitArrElemVecVal(d, s, 3, indx1, indx2, indx3); break; } default: _vl_svGetBitArrElemVecVal(d, s, -1, 0, 0, 0); break; // Will error } va_end(ap); } void svGetBitArrElem1VecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1) { _vl_svGetBitArrElemVecVal(d, s, 1, indx1, 0, 0); } void svGetBitArrElem2VecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1, int indx2) { _vl_svGetBitArrElemVecVal(d, s, 2, indx1, indx2, 0); } void svGetBitArrElem3VecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1, int indx2, int indx3) { _vl_svGetBitArrElemVecVal(d, s, 3, indx1, indx2, indx3); } void svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, ...) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s); va_list ap; va_start(ap, indx1); switch (varp->udims()) { case 1: _vl_svGetLogicArrElemVecVal(d, s, 1, indx1, 0, 0); break; case 2: { int indx2 = va_arg(ap, int); _vl_svGetLogicArrElemVecVal(d, s, 2, indx1, indx2, 0); break; } case 3: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); _vl_svGetLogicArrElemVecVal(d, s, 3, indx1, indx2, indx3); break; } default: _vl_svGetLogicArrElemVecVal(d, s, -1, 0, 0, 0); break; // Will error } va_end(ap); } void svGetLogicArrElem1VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1) { _vl_svGetLogicArrElemVecVal(d, s, 1, indx1, 0, 0); } void svGetLogicArrElem2VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, int indx2) { _vl_svGetLogicArrElemVecVal(d, s, 2, indx1, indx2, 0); } void svGetLogicArrElem3VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, int indx2, int indx3) { _vl_svGetLogicArrElemVecVal(d, s, 3, indx1, indx2, indx3); } svBit svGetBitArrElem(const svOpenArrayHandle s, int indx1, ...) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s); svBit out; va_list ap; va_start(ap, indx1); switch (varp->udims()) { case 1: out = _vl_svGetBitArrElem(s, 1, indx1, 0, 0, 0); break; case 2: { int indx2 = va_arg(ap, int); out = _vl_svGetBitArrElem(s, 2, indx1, indx2, 0, 0); break; } case 3: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); out = _vl_svGetBitArrElem(s, 3, indx1, indx2, indx3, 0); break; } case 4: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); int indx4 = va_arg(ap, int); out = _vl_svGetBitArrElem(s, 4, indx1, indx2, indx3, indx4); break; } default: out = _vl_svGetBitArrElem(s, -1, 0, 0, 0, 0); break; // Will error } va_end(ap); return out; } svBit svGetBitArrElem1(const svOpenArrayHandle s, int indx1) { return _vl_svGetBitArrElem(s, 1, indx1, 0, 0, 0); } svBit svGetBitArrElem2(const svOpenArrayHandle s, int indx1, int indx2) { return _vl_svGetBitArrElem(s, 2, indx1, indx2, 0, 0); } svBit svGetBitArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int indx3) { return _vl_svGetBitArrElem(s, 3, indx1, indx2, indx3, 0); } svLogic svGetLogicArrElem(const svOpenArrayHandle s, int indx1, ...) { // Verilator doesn't support X/Z so can just call Bit version const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s); svBit out; va_list ap; va_start(ap, indx1); switch (varp->udims()) { case 1: out = _vl_svGetBitArrElem(s, 1, indx1, 0, 0, 0); break; case 2: { int indx2 = va_arg(ap, int); out = _vl_svGetBitArrElem(s, 2, indx1, indx2, 0, 0); break; } case 3: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); out = _vl_svGetBitArrElem(s, 3, indx1, indx2, indx3, 0); break; } case 4: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); int indx4 = va_arg(ap, int); out = _vl_svGetBitArrElem(s, 4, indx1, indx2, indx3, indx4); break; } default: out = _vl_svGetBitArrElem(s, -1, 0, 0, 0, 0); break; // Will error } va_end(ap); return out; } svLogic svGetLogicArrElem1(const svOpenArrayHandle s, int indx1) { // Verilator doesn't support X/Z so can just call Bit version return svGetBitArrElem1(s, indx1); } svLogic svGetLogicArrElem2(const svOpenArrayHandle s, int indx1, int indx2) { // Verilator doesn't support X/Z so can just call Bit version return svGetBitArrElem2(s, indx1, indx2); } svLogic svGetLogicArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int indx3) { // Verilator doesn't support X/Z so can just call Bit version return svGetBitArrElem3(s, indx1, indx2, indx3); } void svPutBitArrElem(const svOpenArrayHandle d, svBit value, int indx1, ...) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d); va_list ap; va_start(ap, indx1); switch (varp->udims()) { case 1: _vl_svPutBitArrElem(d, value, 1, indx1, 0, 0, 0); break; case 2: { int indx2 = va_arg(ap, int); _vl_svPutBitArrElem(d, value, 2, indx1, indx2, 0, 0); break; } case 3: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); _vl_svPutBitArrElem(d, value, 3, indx1, indx2, indx3, 0); break; } case 4: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); int indx4 = va_arg(ap, int); _vl_svPutBitArrElem(d, value, 4, indx1, indx2, indx3, indx4); break; } default: _vl_svPutBitArrElem(d, value, -1, 0, 0, 0, 0); break; // Will error } va_end(ap); } void svPutBitArrElem1(const svOpenArrayHandle d, svBit value, int indx1) { _vl_svPutBitArrElem(d, value, 1, indx1, 0, 0, 0); } void svPutBitArrElem2(const svOpenArrayHandle d, svBit value, int indx1, int indx2) { _vl_svPutBitArrElem(d, value, 2, indx1, indx2, 0, 0); } void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1, int indx2, int indx3) { _vl_svPutBitArrElem(d, value, 3, indx1, indx2, indx3, 0); } void svPutLogicArrElem(const svOpenArrayHandle d, svLogic value, int indx1, ...) { // Verilator doesn't support X/Z so can just call Bit version const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d); va_list ap; va_start(ap, indx1); switch (varp->udims()) { case 1: _vl_svPutBitArrElem(d, value, 1, indx1, 0, 0, 0); break; case 2: { int indx2 = va_arg(ap, int); _vl_svPutBitArrElem(d, value, 2, indx1, indx2, 0, 0); break; } case 3: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); _vl_svPutBitArrElem(d, value, 3, indx1, indx2, indx3, 0); break; } case 4: { int indx2 = va_arg(ap, int); int indx3 = va_arg(ap, int); int indx4 = va_arg(ap, int); _vl_svPutBitArrElem(d, value, 4, indx1, indx2, indx3, indx4); break; } default: _vl_svPutBitArrElem(d, value, -1, 0, 0, 0, 0); break; // Will error } va_end(ap); } void svPutLogicArrElem1(const svOpenArrayHandle d, svLogic value, int indx1) { // Verilator doesn't support X/Z so can just call Bit version svPutBitArrElem1(d, value, indx1); } void svPutLogicArrElem2(const svOpenArrayHandle d, svLogic value, int indx1, int indx2) { // Verilator doesn't support X/Z so can just call Bit version svPutBitArrElem2(d, value, indx1, indx2); } void svPutLogicArrElem3(const svOpenArrayHandle d, svLogic value, int indx1, int indx2, int indx3) { // Verilator doesn't support X/Z so can just call Bit version svPutBitArrElem3(d, value, indx1, indx2, indx3); } //====================================================================== // Functions for working with DPI context svScope svGetScope() { if (VL_UNLIKELY(!Verilated::dpiInContext())) { _VL_SVDPI_CONTEXT_WARN(); return NULL; } // NOLINTNEXTLINE(google-readability-casting) return (svScope)(Verilated::dpiScope()); } svScope svSetScope(const svScope scope) { const VerilatedScope* prevScopep = Verilated::dpiScope(); const VerilatedScope* vscopep = reinterpret_cast(scope); Verilated::dpiScope(vscopep); // NOLINTNEXTLINE(google-readability-casting) return (svScope)(prevScopep); } const char* svGetNameFromScope(const svScope scope) { const VerilatedScope* vscopep = reinterpret_cast(scope); return vscopep->name(); } svScope svGetScopeFromName(const char* scopeName) { // NOLINTNEXTLINE(google-readability-casting) return (svScope)(VerilatedImp::scopeFind(scopeName)); } int svPutUserData(const svScope scope, void* userKey, void* userData) { VerilatedImp::userInsert(scope, userKey, userData); return 0; } void* svGetUserData(const svScope scope, void* userKey) { return VerilatedImp::userFind(scope, userKey); } int svGetCallerInfo(const char** fileNamepp, int* lineNumberp) { if (VL_UNLIKELY(!Verilated::dpiInContext())) { _VL_SVDPI_CONTEXT_WARN(); return false; } if (VL_LIKELY(fileNamepp)) *fileNamepp = Verilated::dpiFilenamep(); // thread local if (VL_LIKELY(lineNumberp)) *lineNumberp = Verilated::dpiLineno(); // thread local return true; } //====================================================================== // Disables int svIsDisabledState() { return 0; // Disables not implemented } void svAckDisabledState() { // Disables not implemented } verilator-4.038/include/gtkwave/0000775000177100017500000000000013702335701016610 5ustar wsnyderwsnyderverilator-4.038/include/gtkwave/wavealloca.h0000664000177100017500000000262713702133367021112 0ustar wsnyderwsnyder/* * Copyright (c) 1999 Tony Bybell. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * SPDX-License-Identifier: MIT */ #ifndef WAVE_ALLOCA_H #define WAVE_ALLOCA_H #include #ifdef HAVE_ALLOCA_H #include #elif defined(__GNUC__) #ifndef __MINGW32__ #ifndef alloca #define alloca __builtin_alloca #endif #else #include #endif #endif #define wave_alloca alloca #endif verilator-4.038/include/gtkwave/fastlz.c0000664000177100017500000003237113702133367020271 0ustar wsnyderwsnyder/* FastLZ - lightning-fast lossless compression library Copyright (C) 2007 Ariya Hidayat (ariya@kde.org) Copyright (C) 2006 Ariya Hidayat (ariya@kde.org) Copyright (C) 2005 Ariya Hidayat (ariya@kde.org) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. SPDX-License-Identifier: MIT */ #include "fastlz.h" #if !defined(FASTLZ__COMPRESSOR) && !defined(FASTLZ_DECOMPRESSOR) /* * Always check for bound when decompressing. * Generally it is best to leave it defined. */ #define FASTLZ_SAFE /* * Give hints to the compiler for branch prediction optimization. */ #if defined(__GNUC__) && (__GNUC__ > 2) #define FASTLZ_EXPECT_CONDITIONAL(c) (__builtin_expect((c), 1)) #define FASTLZ_UNEXPECT_CONDITIONAL(c) (__builtin_expect((c), 0)) #else #define FASTLZ_EXPECT_CONDITIONAL(c) (c) #define FASTLZ_UNEXPECT_CONDITIONAL(c) (c) #endif /* * Use inlined functions for supported systems. */ #if defined(__GNUC__) || defined(__DMC__) || defined(__POCC__) || defined(__WATCOMC__) || defined(__SUNPRO_C) #define FASTLZ_INLINE inline #elif defined(__BORLANDC__) || defined(_MSC_VER) || defined(__LCC__) #define FASTLZ_INLINE __inline #else #define FASTLZ_INLINE #endif /* * Prevent accessing more than 8-bit at once, except on x86 architectures. */ #if !defined(FASTLZ_STRICT_ALIGN) #define FASTLZ_STRICT_ALIGN #if defined(__i386__) || defined(__386) /* GNU C, Sun Studio */ #undef FASTLZ_STRICT_ALIGN #elif defined(__i486__) || defined(__i586__) || defined(__i686__) || defined(__amd64) /* GNU C */ #undef FASTLZ_STRICT_ALIGN #elif defined(_M_IX86) /* Intel, MSVC */ #undef FASTLZ_STRICT_ALIGN #elif defined(__386) #undef FASTLZ_STRICT_ALIGN #elif defined(_X86_) /* MinGW */ #undef FASTLZ_STRICT_ALIGN #elif defined(__I86__) /* Digital Mars */ #undef FASTLZ_STRICT_ALIGN #endif #endif /* prototypes */ int fastlz_compress(const void* input, int length, void* output); int fastlz_compress_level(int level, const void* input, int length, void* output); int fastlz_decompress(const void* input, int length, void* output, int maxout); #define MAX_COPY 32 #define MAX_LEN 264 /* 256 + 8 */ #define MAX_DISTANCE 8192 #if !defined(FASTLZ_STRICT_ALIGN) #define FASTLZ_READU16(p) *((const flzuint16*)(p)) #else #define FASTLZ_READU16(p) ((p)[0] | (p)[1]<<8) #endif #define HASH_LOG 13 #define HASH_SIZE (1<< HASH_LOG) #define HASH_MASK (HASH_SIZE-1) #define HASH_FUNCTION(v,p) { v = FASTLZ_READU16(p); v ^= FASTLZ_READU16(p+1)^(v>>(16-HASH_LOG));v &= HASH_MASK; } #undef FASTLZ_LEVEL #define FASTLZ_LEVEL 1 #undef FASTLZ_COMPRESSOR #undef FASTLZ_DECOMPRESSOR #define FASTLZ_COMPRESSOR fastlz1_compress #define FASTLZ_DECOMPRESSOR fastlz1_decompress static FASTLZ_INLINE int FASTLZ_COMPRESSOR(const void* input, int length, void* output); static FASTLZ_INLINE int FASTLZ_DECOMPRESSOR(const void* input, int length, void* output, int maxout); #include "fastlz.c" #undef FASTLZ_LEVEL #define FASTLZ_LEVEL 2 #undef MAX_DISTANCE #define MAX_DISTANCE 8191 #define MAX_FARDISTANCE (65535+MAX_DISTANCE-1) #undef FASTLZ_COMPRESSOR #undef FASTLZ_DECOMPRESSOR #define FASTLZ_COMPRESSOR fastlz2_compress #define FASTLZ_DECOMPRESSOR fastlz2_decompress static FASTLZ_INLINE int FASTLZ_COMPRESSOR(const void* input, int length, void* output); static FASTLZ_INLINE int FASTLZ_DECOMPRESSOR(const void* input, int length, void* output, int maxout); #include "fastlz.c" int fastlz_compress(const void* input, int length, void* output) { /* for short block, choose fastlz1 */ if(length < 65536) return fastlz1_compress(input, length, output); /* else... */ return fastlz2_compress(input, length, output); } int fastlz_decompress(const void* input, int length, void* output, int maxout) { /* magic identifier for compression level */ int level = ((*(const flzuint8*)input) >> 5) + 1; if(level == 1) return fastlz1_decompress(input, length, output, maxout); if(level == 2) return fastlz2_decompress(input, length, output, maxout); /* unknown level, trigger error */ return 0; } int fastlz_compress_level(int level, const void* input, int length, void* output) { if(level == 1) return fastlz1_compress(input, length, output); if(level == 2) return fastlz2_compress(input, length, output); return 0; } #else /* !defined(FASTLZ_COMPRESSOR) && !defined(FASTLZ_DECOMPRESSOR) */ static FASTLZ_INLINE int FASTLZ_COMPRESSOR(const void* input, int length, void* output) { const flzuint8* ip = (const flzuint8*) input; const flzuint8* ip_bound = ip + length - 2; const flzuint8* ip_limit = ip + length - 12; flzuint8* op = (flzuint8*) output; const flzuint8* htab[HASH_SIZE]; const flzuint8** hslot; flzuint32 hval; flzuint32 copy; /* sanity check */ if(FASTLZ_UNEXPECT_CONDITIONAL(length < 4)) { if(length) { /* create literal copy only */ *op++ = length-1; ip_bound++; while(ip <= ip_bound) *op++ = *ip++; return length+1; } else return 0; } /* initializes hash table */ for (hslot = htab; hslot < htab + HASH_SIZE; hslot++) *hslot = ip; /* we start with literal copy */ copy = 2; *op++ = MAX_COPY-1; *op++ = *ip++; *op++ = *ip++; /* main loop */ while(FASTLZ_EXPECT_CONDITIONAL(ip < ip_limit)) { const flzuint8* ref; flzuint32 distance; /* minimum match length */ flzuint32 len = 3; /* comparison starting-point */ const flzuint8* anchor = ip; /* check for a run */ #if FASTLZ_LEVEL==2 if(ip[0] == ip[-1] && FASTLZ_READU16(ip-1)==FASTLZ_READU16(ip+1)) { distance = 1; /* ip += 3; */ /* scan-build, never used */ ref = anchor - 1 + 3; goto match; } #endif /* find potential match */ HASH_FUNCTION(hval,ip); hslot = htab + hval; ref = htab[hval]; /* calculate distance to the match */ distance = anchor - ref; /* update hash table */ *hslot = anchor; /* is this a match? check the first 3 bytes */ if(distance==0 || #if FASTLZ_LEVEL==1 (distance >= MAX_DISTANCE) || #else (distance >= MAX_FARDISTANCE) || #endif *ref++ != *ip++ || *ref++!=*ip++ || *ref++!=*ip++) goto literal; #if FASTLZ_LEVEL==2 /* far, needs at least 5-byte match */ if(distance >= MAX_DISTANCE) { if(*ip++ != *ref++ || *ip++!= *ref++) goto literal; len += 2; } match: #endif /* last matched byte */ ip = anchor + len; /* distance is biased */ distance--; if(!distance) { /* zero distance means a run */ flzuint8 x = ip[-1]; while(ip < ip_bound) if(*ref++ != x) break; else ip++; } else for(;;) { /* safe because the outer check against ip limit */ if(*ref++ != *ip++) break; if(*ref++ != *ip++) break; if(*ref++ != *ip++) break; if(*ref++ != *ip++) break; if(*ref++ != *ip++) break; if(*ref++ != *ip++) break; if(*ref++ != *ip++) break; if(*ref++ != *ip++) break; while(ip < ip_bound) if(*ref++ != *ip++) break; break; } /* if we have copied something, adjust the copy count */ if(copy) /* copy is biased, '0' means 1 byte copy */ *(op-copy-1) = copy-1; else /* back, to overwrite the copy count */ op--; /* reset literal counter */ copy = 0; /* length is biased, '1' means a match of 3 bytes */ ip -= 3; len = ip - anchor; /* encode the match */ #if FASTLZ_LEVEL==2 if(distance < MAX_DISTANCE) { if(len < 7) { *op++ = (len << 5) + (distance >> 8); *op++ = (distance & 255); } else { *op++ = (7 << 5) + (distance >> 8); for(len-=7; len >= 255; len-= 255) *op++ = 255; *op++ = len; *op++ = (distance & 255); } } else { /* far away, but not yet in the another galaxy... */ if(len < 7) { distance -= MAX_DISTANCE; *op++ = (len << 5) + 31; *op++ = 255; *op++ = distance >> 8; *op++ = distance & 255; } else { distance -= MAX_DISTANCE; *op++ = (7 << 5) + 31; for(len-=7; len >= 255; len-= 255) *op++ = 255; *op++ = len; *op++ = 255; *op++ = distance >> 8; *op++ = distance & 255; } } #else if(FASTLZ_UNEXPECT_CONDITIONAL(len > MAX_LEN-2)) while(len > MAX_LEN-2) { *op++ = (7 << 5) + (distance >> 8); *op++ = MAX_LEN - 2 - 7 -2; *op++ = (distance & 255); len -= MAX_LEN-2; } if(len < 7) { *op++ = (len << 5) + (distance >> 8); *op++ = (distance & 255); } else { *op++ = (7 << 5) + (distance >> 8); *op++ = len - 7; *op++ = (distance & 255); } #endif /* update the hash at match boundary */ HASH_FUNCTION(hval,ip); htab[hval] = ip++; HASH_FUNCTION(hval,ip); htab[hval] = ip++; /* assuming literal copy */ *op++ = MAX_COPY-1; continue; literal: *op++ = *anchor++; ip = anchor; copy++; if(FASTLZ_UNEXPECT_CONDITIONAL(copy == MAX_COPY)) { copy = 0; *op++ = MAX_COPY-1; } } /* left-over as literal copy */ ip_bound++; while(ip <= ip_bound) { *op++ = *ip++; copy++; if(copy == MAX_COPY) { copy = 0; *op++ = MAX_COPY-1; } } /* if we have copied something, adjust the copy length */ if(copy) *(op-copy-1) = copy-1; else op--; #if FASTLZ_LEVEL==2 /* marker for fastlz2 */ *(flzuint8*)output |= (1 << 5); #endif return op - (flzuint8*)output; } static FASTLZ_INLINE int FASTLZ_DECOMPRESSOR(const void* input, int length, void* output, int maxout) { const flzuint8* ip = (const flzuint8*) input; const flzuint8* ip_limit = ip + length; flzuint8* op = (flzuint8*) output; flzuint8* op_limit = op + maxout; flzuint32 ctrl = (*ip++) & 31; int loop = 1; do { const flzuint8* ref = op; flzuint32 len = ctrl >> 5; flzuint32 ofs = (ctrl & 31) << 8; if(ctrl >= 32) { #if FASTLZ_LEVEL==2 flzuint8 code; #endif len--; ref -= ofs; if (len == 7-1) #if FASTLZ_LEVEL==1 len += *ip++; ref -= *ip++; #else do { code = *ip++; len += code; } while (code==255); code = *ip++; ref -= code; /* match from 16-bit distance */ if(FASTLZ_UNEXPECT_CONDITIONAL(code==255)) if(FASTLZ_EXPECT_CONDITIONAL(ofs==(31 << 8))) { ofs = (*ip++) << 8; ofs += *ip++; ref = op - ofs - MAX_DISTANCE; } #endif #ifdef FASTLZ_SAFE if (FASTLZ_UNEXPECT_CONDITIONAL(op + len + 3 > op_limit)) return 0; if (FASTLZ_UNEXPECT_CONDITIONAL(ref-1 < (flzuint8 *)output)) return 0; #endif if(FASTLZ_EXPECT_CONDITIONAL(ip < ip_limit)) ctrl = *ip++; else loop = 0; if(ref == op) { /* optimize copy for a run */ flzuint8 b = ref[-1]; *op++ = b; *op++ = b; *op++ = b; for(; len; --len) *op++ = b; } else { #if !defined(FASTLZ_STRICT_ALIGN) const flzuint16* p; flzuint16* q; #endif /* copy from reference */ ref--; *op++ = *ref++; *op++ = *ref++; *op++ = *ref++; #if !defined(FASTLZ_STRICT_ALIGN) /* copy a byte, so that now it's word aligned */ if(len & 1) { *op++ = *ref++; len--; } /* copy 16-bit at once */ q = (flzuint16*) op; op += len; p = (const flzuint16*) ref; for(len>>=1; len > 4; len-=4) { *q++ = *p++; *q++ = *p++; *q++ = *p++; *q++ = *p++; } for(; len; --len) *q++ = *p++; #else for(; len; --len) *op++ = *ref++; #endif } } else { ctrl++; #ifdef FASTLZ_SAFE if (FASTLZ_UNEXPECT_CONDITIONAL(op + ctrl > op_limit)) return 0; if (FASTLZ_UNEXPECT_CONDITIONAL(ip + ctrl > ip_limit)) return 0; #endif *op++ = *ip++; for(--ctrl; ctrl; ctrl--) *op++ = *ip++; loop = FASTLZ_EXPECT_CONDITIONAL(ip < ip_limit); if(loop) ctrl = *ip++; } } while(FASTLZ_EXPECT_CONDITIONAL(loop)); return op - (flzuint8*)output; } #endif /* !defined(FASTLZ_COMPRESSOR) && !defined(FASTLZ_DECOMPRESSOR) */ verilator-4.038/include/gtkwave/lz4.h0000664000177100017500000004467013702133367017511 0ustar wsnyderwsnyder/* LZ4 - Fast LZ compression algorithm Header File Copyright (C) 2011-2015, Yann Collet. BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SPDX-License-Identifier: BSD-2-Clause You can contact the author at : - LZ4 source repository : https://github.com/Cyan4973/lz4 - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c */ #pragma once #if defined (__cplusplus) extern "C" { #endif /* * lz4.h provides block compression functions, and gives full buffer control to programmer. * If you need to generate inter-operable compressed data (respecting LZ4 frame specification), * and can let the library handle its own memory, please use lz4frame.h instead. */ /************************************** * Version **************************************/ #define LZ4_VERSION_MAJOR 1 /* for breaking interface changes */ #define LZ4_VERSION_MINOR 7 /* for new (non-breaking) interface capabilities */ #define LZ4_VERSION_RELEASE 1 /* for tweaks, bug-fixes, or development */ #define LZ4_VERSION_NUMBER (LZ4_VERSION_MAJOR *100*100 + LZ4_VERSION_MINOR *100 + LZ4_VERSION_RELEASE) int LZ4_versionNumber (void); /************************************** * Tuning parameter **************************************/ /* * LZ4_MEMORY_USAGE : * Memory usage formula : N->2^N Bytes (examples : 10 -> 1KB; 12 -> 4KB ; 16 -> 64KB; 20 -> 1MB; etc.) * Increasing memory usage improves compression ratio * Reduced memory usage can improve speed, due to cache effect * Default value is 14, for 16KB, which nicely fits into Intel x86 L1 cache */ #define LZ4_MEMORY_USAGE 14 /************************************** * Simple Functions **************************************/ int LZ4_compress_default(const char* source, char* dest, int sourceSize, int maxDestSize); int LZ4_decompress_safe (const char* source, char* dest, int compressedSize, int maxDecompressedSize); /* LZ4_compress_default() : Compresses 'sourceSize' bytes from buffer 'source' into already allocated 'dest' buffer of size 'maxDestSize'. Compression is guaranteed to succeed if 'maxDestSize' >= LZ4_compressBound(sourceSize). It also runs faster, so it's a recommended setting. If the function cannot compress 'source' into a more limited 'dest' budget, compression stops *immediately*, and the function result is zero. As a consequence, 'dest' content is not valid. This function never writes outside 'dest' buffer, nor read outside 'source' buffer. sourceSize : Max supported value is LZ4_MAX_INPUT_VALUE maxDestSize : full or partial size of buffer 'dest' (which must be already allocated) return : the number of bytes written into buffer 'dest' (necessarily <= maxOutputSize) or 0 if compression fails LZ4_decompress_safe() : compressedSize : is the precise full size of the compressed block. maxDecompressedSize : is the size of destination buffer, which must be already allocated. return : the number of bytes decompressed into destination buffer (necessarily <= maxDecompressedSize) If destination buffer is not large enough, decoding will stop and output an error code (<0). If the source stream is detected malformed, the function will stop decoding and return a negative result. This function is protected against buffer overflow exploits, including malicious data packets. It never writes outside output buffer, nor reads outside input buffer. */ /************************************** * Advanced Functions **************************************/ #define LZ4_MAX_INPUT_SIZE 0x7E000000 /* 2 113 929 216 bytes */ #define LZ4_COMPRESSBOUND(isize) ((unsigned)(isize) > (unsigned)LZ4_MAX_INPUT_SIZE ? 0 : (isize) + ((isize)/255) + 16) /* LZ4_compressBound() : Provides the maximum size that LZ4 compression may output in a "worst case" scenario (input data not compressible) This function is primarily useful for memory allocation purposes (destination buffer size). Macro LZ4_COMPRESSBOUND() is also provided for compilation-time evaluation (stack memory allocation for example). Note that LZ4_compress_default() compress faster when dest buffer size is >= LZ4_compressBound(srcSize) inputSize : max supported value is LZ4_MAX_INPUT_SIZE return : maximum output size in a "worst case" scenario or 0, if input size is too large ( > LZ4_MAX_INPUT_SIZE) */ int LZ4_compressBound(int inputSize); /* LZ4_compress_fast() : Same as LZ4_compress_default(), but allows to select an "acceleration" factor. The larger the acceleration value, the faster the algorithm, but also the lesser the compression. It's a trade-off. It can be fine tuned, with each successive value providing roughly +~3% to speed. An acceleration value of "1" is the same as regular LZ4_compress_default() Values <= 0 will be replaced by ACCELERATION_DEFAULT (see lz4.c), which is 1. */ int LZ4_compress_fast (const char* source, char* dest, int sourceSize, int maxDestSize, int acceleration); /* LZ4_compress_fast_extState() : Same compression function, just using an externally allocated memory space to store compression state. Use LZ4_sizeofState() to know how much memory must be allocated, and allocate it on 8-bytes boundaries (using malloc() typically). Then, provide it as 'void* state' to compression function. */ int LZ4_sizeofState(void); int LZ4_compress_fast_extState (void* state, const char* source, char* dest, int inputSize, int maxDestSize, int acceleration); /* LZ4_compress_destSize() : Reverse the logic, by compressing as much data as possible from 'source' buffer into already allocated buffer 'dest' of size 'targetDestSize'. This function either compresses the entire 'source' content into 'dest' if it's large enough, or fill 'dest' buffer completely with as much data as possible from 'source'. *sourceSizePtr : will be modified to indicate how many bytes where read from 'source' to fill 'dest'. New value is necessarily <= old value. return : Nb bytes written into 'dest' (necessarily <= targetDestSize) or 0 if compression fails */ int LZ4_compress_destSize (const char* source, char* dest, int* sourceSizePtr, int targetDestSize); /* LZ4_decompress_fast() : originalSize : is the original and therefore uncompressed size return : the number of bytes read from the source buffer (in other words, the compressed size) If the source stream is detected malformed, the function will stop decoding and return a negative result. Destination buffer must be already allocated. Its size must be a minimum of 'originalSize' bytes. note : This function fully respect memory boundaries for properly formed compressed data. It is a bit faster than LZ4_decompress_safe(). However, it does not provide any protection against intentionally modified data stream (malicious input). Use this function in trusted environment only (data to decode comes from a trusted source). */ int LZ4_decompress_fast (const char* source, char* dest, int originalSize); /* LZ4_decompress_safe_partial() : This function decompress a compressed block of size 'compressedSize' at position 'source' into destination buffer 'dest' of size 'maxDecompressedSize'. The function tries to stop decompressing operation as soon as 'targetOutputSize' has been reached, reducing decompression time. return : the number of bytes decoded in the destination buffer (necessarily <= maxDecompressedSize) Note : this number can be < 'targetOutputSize' should the compressed block to decode be smaller. Always control how many bytes were decoded. If the source stream is detected malformed, the function will stop decoding and return a negative result. This function never writes outside of output buffer, and never reads outside of input buffer. It is therefore protected against malicious data packets */ int LZ4_decompress_safe_partial (const char* source, char* dest, int compressedSize, int targetOutputSize, int maxDecompressedSize); /*********************************************** * Streaming Compression Functions ***********************************************/ #define LZ4_STREAMSIZE_U64 ((1 << (LZ4_MEMORY_USAGE-3)) + 4) #define LZ4_STREAMSIZE (LZ4_STREAMSIZE_U64 * sizeof(long long)) /* * LZ4_stream_t * information structure to track an LZ4 stream. * important : init this structure content before first use ! * note : only allocated directly the structure if you are statically linking LZ4 * If you are using liblz4 as a DLL, please use below construction methods instead. */ typedef struct { long long table[LZ4_STREAMSIZE_U64]; } LZ4_stream_t; /* * LZ4_resetStream * Use this function to init an allocated LZ4_stream_t structure */ void LZ4_resetStream (LZ4_stream_t* streamPtr); /* * LZ4_createStream will allocate and initialize an LZ4_stream_t structure * LZ4_freeStream releases its memory. * In the context of a DLL (liblz4), please use these methods rather than the static struct. * They are more future proof, in case of a change of LZ4_stream_t size. */ LZ4_stream_t* LZ4_createStream(void); int LZ4_freeStream (LZ4_stream_t* streamPtr); /* * LZ4_loadDict * Use this function to load a static dictionary into LZ4_stream. * Any previous data will be forgotten, only 'dictionary' will remain in memory. * Loading a size of 0 is allowed. * Return : dictionary size, in bytes (necessarily <= 64 KB) */ int LZ4_loadDict (LZ4_stream_t* streamPtr, const char* dictionary, int dictSize); /* * LZ4_compress_fast_continue * Compress buffer content 'src', using data from previously compressed blocks as dictionary to improve compression ratio. * Important : Previous data blocks are assumed to still be present and unmodified ! * 'dst' buffer must be already allocated. * If maxDstSize >= LZ4_compressBound(srcSize), compression is guaranteed to succeed, and runs faster. * If not, and if compressed data cannot fit into 'dst' buffer size, compression stops, and function returns a zero. */ int LZ4_compress_fast_continue (LZ4_stream_t* streamPtr, const char* src, char* dst, int srcSize, int maxDstSize, int acceleration); /* * LZ4_saveDict * If previously compressed data block is not guaranteed to remain available at its memory location * save it into a safer place (char* safeBuffer) * Note : you don't need to call LZ4_loadDict() afterwards, * dictionary is immediately usable, you can therefore call LZ4_compress_fast_continue() * Return : saved dictionary size in bytes (necessarily <= dictSize), or 0 if error */ int LZ4_saveDict (LZ4_stream_t* streamPtr, char* safeBuffer, int dictSize); /************************************************ * Streaming Decompression Functions ************************************************/ #define LZ4_STREAMDECODESIZE_U64 4 #define LZ4_STREAMDECODESIZE (LZ4_STREAMDECODESIZE_U64 * sizeof(unsigned long long)) typedef struct { unsigned long long table[LZ4_STREAMDECODESIZE_U64]; } LZ4_streamDecode_t; /* * LZ4_streamDecode_t * information structure to track an LZ4 stream. * init this structure content using LZ4_setStreamDecode or memset() before first use ! * * In the context of a DLL (liblz4) please prefer usage of construction methods below. * They are more future proof, in case of a change of LZ4_streamDecode_t size in the future. * LZ4_createStreamDecode will allocate and initialize an LZ4_streamDecode_t structure * LZ4_freeStreamDecode releases its memory. */ LZ4_streamDecode_t* LZ4_createStreamDecode(void); int LZ4_freeStreamDecode (LZ4_streamDecode_t* LZ4_stream); /* * LZ4_setStreamDecode * Use this function to instruct where to find the dictionary. * Setting a size of 0 is allowed (same effect as reset). * Return : 1 if OK, 0 if error */ int LZ4_setStreamDecode (LZ4_streamDecode_t* LZ4_streamDecode, const char* dictionary, int dictSize); /* *_continue() : These decoding functions allow decompression of multiple blocks in "streaming" mode. Previously decoded blocks *must* remain available at the memory position where they were decoded (up to 64 KB) In the case of a ring buffers, decoding buffer must be either : - Exactly same size as encoding buffer, with same update rule (block boundaries at same positions) In which case, the decoding & encoding ring buffer can have any size, including very small ones ( < 64 KB). - Larger than encoding buffer, by a minimum of maxBlockSize more bytes. maxBlockSize is implementation dependent. It's the maximum size you intend to compress into a single block. In which case, encoding and decoding buffers do not need to be synchronized, and encoding ring buffer can have any size, including small ones ( < 64 KB). - _At least_ 64 KB + 8 bytes + maxBlockSize. In which case, encoding and decoding buffers do not need to be synchronized, and encoding ring buffer can have any size, including larger than decoding buffer. Whenever these conditions are not possible, save the last 64KB of decoded data into a safe buffer, and indicate where it is saved using LZ4_setStreamDecode() */ int LZ4_decompress_safe_continue (LZ4_streamDecode_t* LZ4_streamDecode, const char* source, char* dest, int compressedSize, int maxDecompressedSize); int LZ4_decompress_fast_continue (LZ4_streamDecode_t* LZ4_streamDecode, const char* source, char* dest, int originalSize); /* Advanced decoding functions : *_usingDict() : These decoding functions work the same as a combination of LZ4_setStreamDecode() followed by LZ4_decompress_x_continue() They are stand-alone. They don't need nor update an LZ4_streamDecode_t structure. */ int LZ4_decompress_safe_usingDict (const char* source, char* dest, int compressedSize, int maxDecompressedSize, const char* dictStart, int dictSize); int LZ4_decompress_fast_usingDict (const char* source, char* dest, int originalSize, const char* dictStart, int dictSize); /************************************** * Obsolete Functions **************************************/ /* Deprecate Warnings */ /* Should these warnings messages be a problem, it is generally possible to disable them, with -Wno-deprecated-declarations for gcc or _CRT_SECURE_NO_WARNINGS in Visual for example. You can also define LZ4_DEPRECATE_WARNING_DEFBLOCK. */ #ifndef LZ4_DEPRECATE_WARNING_DEFBLOCK # define LZ4_DEPRECATE_WARNING_DEFBLOCK # define LZ4_GCC_VERSION (__GNUC__ * 100 + __GNUC_MINOR__) # if (LZ4_GCC_VERSION >= 405) || defined(__clang__) # define LZ4_DEPRECATED(message) __attribute__((deprecated(message))) # elif (LZ4_GCC_VERSION >= 301) # define LZ4_DEPRECATED(message) __attribute__((deprecated)) # elif defined(_MSC_VER) # define LZ4_DEPRECATED(message) __declspec(deprecated(message)) # else # pragma message("WARNING: You need to implement LZ4_DEPRECATED for this compiler") # define LZ4_DEPRECATED(message) # endif #endif /* LZ4_DEPRECATE_WARNING_DEFBLOCK */ /* Obsolete compression functions */ /* These functions are planned to start generate warnings by r131 approximately */ int LZ4_compress (const char* source, char* dest, int sourceSize); int LZ4_compress_limitedOutput (const char* source, char* dest, int sourceSize, int maxOutputSize); int LZ4_compress_withState (void* state, const char* source, char* dest, int inputSize); int LZ4_compress_limitedOutput_withState (void* state, const char* source, char* dest, int inputSize, int maxOutputSize); int LZ4_compress_continue (LZ4_stream_t* LZ4_streamPtr, const char* source, char* dest, int inputSize); int LZ4_compress_limitedOutput_continue (LZ4_stream_t* LZ4_streamPtr, const char* source, char* dest, int inputSize, int maxOutputSize); /* Obsolete decompression functions */ /* These function names are completely deprecated and must no longer be used. They are only provided here for compatibility with older programs. - LZ4_uncompress is the same as LZ4_decompress_fast - LZ4_uncompress_unknownOutputSize is the same as LZ4_decompress_safe These function prototypes are now disabled; uncomment them only if you really need them. It is highly recommended to stop using these prototypes and migrate to maintained ones */ /* int LZ4_uncompress (const char* source, char* dest, int outputSize); */ /* int LZ4_uncompress_unknownOutputSize (const char* source, char* dest, int isize, int maxOutputSize); */ /* Obsolete streaming functions; use new streaming interface whenever possible */ LZ4_DEPRECATED("use LZ4_createStream() instead") void* LZ4_create (char* inputBuffer); LZ4_DEPRECATED("use LZ4_createStream() instead") int LZ4_sizeofStreamState(void); LZ4_DEPRECATED("use LZ4_resetStream() instead") int LZ4_resetStreamState(void* state, char* inputBuffer); LZ4_DEPRECATED("use LZ4_saveDict() instead") char* LZ4_slideInputBuffer (void* state); /* Obsolete streaming decoding functions */ LZ4_DEPRECATED("use LZ4_decompress_safe_usingDict() instead") int LZ4_decompress_safe_withPrefix64k (const char* src, char* dst, int compressedSize, int maxDstSize); LZ4_DEPRECATED("use LZ4_decompress_fast_usingDict() instead") int LZ4_decompress_fast_withPrefix64k (const char* src, char* dst, int originalSize); #if defined (__cplusplus) } #endif verilator-4.038/include/gtkwave/fstapi.h0000664000177100017500000004375013702133367020264 0ustar wsnyderwsnyder/* * Copyright (c) 2009-2018 Tony Bybell. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * SPDX-License-Identifier: MIT */ #ifndef FST_API_H #define FST_API_H #ifdef __cplusplus extern "C" { #endif #include #include #include #include #include #include #include #include #define FST_RDLOAD "FSTLOAD | " typedef uint32_t fstHandle; typedef uint32_t fstEnumHandle; enum fstWriterPackType { FST_WR_PT_ZLIB = 0, FST_WR_PT_FASTLZ = 1, FST_WR_PT_LZ4 = 2 }; enum fstFileType { FST_FT_MIN = 0, FST_FT_VERILOG = 0, FST_FT_VHDL = 1, FST_FT_VERILOG_VHDL = 2, FST_FT_MAX = 2 }; enum fstBlockType { FST_BL_HDR = 0, FST_BL_VCDATA = 1, FST_BL_BLACKOUT = 2, FST_BL_GEOM = 3, FST_BL_HIER = 4, FST_BL_VCDATA_DYN_ALIAS = 5, FST_BL_HIER_LZ4 = 6, FST_BL_HIER_LZ4DUO = 7, FST_BL_VCDATA_DYN_ALIAS2 = 8, FST_BL_ZWRAPPER = 254, /* indicates that whole trace is gz wrapped */ FST_BL_SKIP = 255 /* used while block is being written */ }; enum fstScopeType { FST_ST_MIN = 0, FST_ST_VCD_MODULE = 0, FST_ST_VCD_TASK = 1, FST_ST_VCD_FUNCTION = 2, FST_ST_VCD_BEGIN = 3, FST_ST_VCD_FORK = 4, FST_ST_VCD_GENERATE = 5, FST_ST_VCD_STRUCT = 6, FST_ST_VCD_UNION = 7, FST_ST_VCD_CLASS = 8, FST_ST_VCD_INTERFACE = 9, FST_ST_VCD_PACKAGE = 10, FST_ST_VCD_PROGRAM = 11, FST_ST_VHDL_ARCHITECTURE = 12, FST_ST_VHDL_PROCEDURE = 13, FST_ST_VHDL_FUNCTION = 14, FST_ST_VHDL_RECORD = 15, FST_ST_VHDL_PROCESS = 16, FST_ST_VHDL_BLOCK = 17, FST_ST_VHDL_FOR_GENERATE = 18, FST_ST_VHDL_IF_GENERATE = 19, FST_ST_VHDL_GENERATE = 20, FST_ST_VHDL_PACKAGE = 21, FST_ST_MAX = 21, FST_ST_GEN_ATTRBEGIN = 252, FST_ST_GEN_ATTREND = 253, FST_ST_VCD_SCOPE = 254, FST_ST_VCD_UPSCOPE = 255 }; enum fstVarType { FST_VT_MIN = 0, /* start of vartypes */ FST_VT_VCD_EVENT = 0, FST_VT_VCD_INTEGER = 1, FST_VT_VCD_PARAMETER = 2, FST_VT_VCD_REAL = 3, FST_VT_VCD_REAL_PARAMETER = 4, FST_VT_VCD_REG = 5, FST_VT_VCD_SUPPLY0 = 6, FST_VT_VCD_SUPPLY1 = 7, FST_VT_VCD_TIME = 8, FST_VT_VCD_TRI = 9, FST_VT_VCD_TRIAND = 10, FST_VT_VCD_TRIOR = 11, FST_VT_VCD_TRIREG = 12, FST_VT_VCD_TRI0 = 13, FST_VT_VCD_TRI1 = 14, FST_VT_VCD_WAND = 15, FST_VT_VCD_WIRE = 16, FST_VT_VCD_WOR = 17, FST_VT_VCD_PORT = 18, FST_VT_VCD_SPARRAY = 19, /* used to define the rownum (index) port for a sparse array */ FST_VT_VCD_REALTIME = 20, FST_VT_GEN_STRING = 21, /* generic string type (max len is defined dynamically via fstWriterEmitVariableLengthValueChange) */ FST_VT_SV_BIT = 22, FST_VT_SV_LOGIC = 23, FST_VT_SV_INT = 24, /* declare as size = 32 */ FST_VT_SV_SHORTINT = 25, /* declare as size = 16 */ FST_VT_SV_LONGINT = 26, /* declare as size = 64 */ FST_VT_SV_BYTE = 27, /* declare as size = 8 */ FST_VT_SV_ENUM = 28, /* declare as appropriate type range */ FST_VT_SV_SHORTREAL = 29, /* declare and emit same as FST_VT_VCD_REAL (needs to be emitted as double, not a float) */ FST_VT_MAX = 29 /* end of vartypes */ }; enum fstVarDir { FST_VD_MIN = 0, FST_VD_IMPLICIT = 0, FST_VD_INPUT = 1, FST_VD_OUTPUT = 2, FST_VD_INOUT = 3, FST_VD_BUFFER = 4, FST_VD_LINKAGE = 5, FST_VD_MAX = 5 }; enum fstHierType { FST_HT_MIN = 0, FST_HT_SCOPE = 0, FST_HT_UPSCOPE = 1, FST_HT_VAR = 2, FST_HT_ATTRBEGIN = 3, FST_HT_ATTREND = 4, /* FST_HT_TREEBEGIN and FST_HT_TREEEND are not yet used by FST but are currently used when fstHier bridges other formats */ FST_HT_TREEBEGIN = 5, FST_HT_TREEEND = 6, FST_HT_MAX = 6 }; enum fstAttrType { FST_AT_MIN = 0, FST_AT_MISC = 0, /* self-contained: does not need matching FST_HT_ATTREND */ FST_AT_ARRAY = 1, FST_AT_ENUM = 2, FST_AT_PACK = 3, FST_AT_MAX = 3 }; enum fstMiscType { FST_MT_MIN = 0, FST_MT_COMMENT = 0, /* use fstWriterSetComment() to emit */ FST_MT_ENVVAR = 1, /* use fstWriterSetEnvVar() to emit */ FST_MT_SUPVAR = 2, /* use fstWriterCreateVar2() to emit */ FST_MT_PATHNAME = 3, /* reserved for fstWriterSetSourceStem() string -> number management */ FST_MT_SOURCESTEM = 4, /* use fstWriterSetSourceStem() to emit */ FST_MT_SOURCEISTEM = 5, /* use fstWriterSetSourceInstantiationStem() to emit */ FST_MT_VALUELIST = 6, /* use fstWriterSetValueList() to emit, followed by fstWriterCreateVar*() */ FST_MT_ENUMTABLE = 7, /* use fstWriterCreateEnumTable() and fstWriterEmitEnumTableRef() to emit */ FST_MT_UNKNOWN = 8, FST_MT_MAX = 8 }; enum fstArrayType { FST_AR_MIN = 0, FST_AR_NONE = 0, FST_AR_UNPACKED = 1, FST_AR_PACKED = 2, FST_AR_SPARSE = 3, FST_AR_MAX = 3 }; enum fstEnumValueType { FST_EV_SV_INTEGER = 0, FST_EV_SV_BIT = 1, FST_EV_SV_LOGIC = 2, FST_EV_SV_INT = 3, FST_EV_SV_SHORTINT = 4, FST_EV_SV_LONGINT = 5, FST_EV_SV_BYTE = 6, FST_EV_SV_UNSIGNED_INTEGER = 7, FST_EV_SV_UNSIGNED_BIT = 8, FST_EV_SV_UNSIGNED_LOGIC = 9, FST_EV_SV_UNSIGNED_INT = 10, FST_EV_SV_UNSIGNED_SHORTINT = 11, FST_EV_SV_UNSIGNED_LONGINT = 12, FST_EV_SV_UNSIGNED_BYTE = 13, FST_EV_REG = 14, FST_EV_TIME = 15, FST_EV_MAX = 15 }; enum fstPackType { FST_PT_NONE = 0, FST_PT_UNPACKED = 1, FST_PT_PACKED = 2, FST_PT_TAGGED_PACKED = 3, FST_PT_MAX = 3 }; enum fstSupplementalVarType { FST_SVT_MIN = 0, FST_SVT_NONE = 0, FST_SVT_VHDL_SIGNAL = 1, FST_SVT_VHDL_VARIABLE = 2, FST_SVT_VHDL_CONSTANT = 3, FST_SVT_VHDL_FILE = 4, FST_SVT_VHDL_MEMORY = 5, FST_SVT_MAX = 5 }; enum fstSupplementalDataType { FST_SDT_MIN = 0, FST_SDT_NONE = 0, FST_SDT_VHDL_BOOLEAN = 1, FST_SDT_VHDL_BIT = 2, FST_SDT_VHDL_BIT_VECTOR = 3, FST_SDT_VHDL_STD_ULOGIC = 4, FST_SDT_VHDL_STD_ULOGIC_VECTOR = 5, FST_SDT_VHDL_STD_LOGIC = 6, FST_SDT_VHDL_STD_LOGIC_VECTOR = 7, FST_SDT_VHDL_UNSIGNED = 8, FST_SDT_VHDL_SIGNED = 9, FST_SDT_VHDL_INTEGER = 10, FST_SDT_VHDL_REAL = 11, FST_SDT_VHDL_NATURAL = 12, FST_SDT_VHDL_POSITIVE = 13, FST_SDT_VHDL_TIME = 14, FST_SDT_VHDL_CHARACTER = 15, FST_SDT_VHDL_STRING = 16, FST_SDT_MAX = 16, FST_SDT_SVT_SHIFT_COUNT = 10, /* FST_SVT_* is ORed in by fstWriterCreateVar2() to the left after shifting FST_SDT_SVT_SHIFT_COUNT */ FST_SDT_ABS_MAX = ((1<<(FST_SDT_SVT_SHIFT_COUNT))-1) }; struct fstHier { unsigned char htyp; union { /* if htyp == FST_HT_SCOPE */ struct fstHierScope { unsigned char typ; /* FST_ST_MIN ... FST_ST_MAX */ const char *name; const char *component; uint32_t name_length; /* strlen(u.scope.name) */ uint32_t component_length; /* strlen(u.scope.component) */ } scope; /* if htyp == FST_HT_VAR */ struct fstHierVar { unsigned char typ; /* FST_VT_MIN ... FST_VT_MAX */ unsigned char direction; /* FST_VD_MIN ... FST_VD_MAX */ unsigned char svt_workspace; /* zeroed out by FST reader, for client code use */ unsigned char sdt_workspace; /* zeroed out by FST reader, for client code use */ unsigned int sxt_workspace; /* zeroed out by FST reader, for client code use */ const char *name; uint32_t length; fstHandle handle; uint32_t name_length; /* strlen(u.var.name) */ unsigned is_alias : 1; } var; /* if htyp == FST_HT_ATTRBEGIN */ struct fstHierAttr { unsigned char typ; /* FST_AT_MIN ... FST_AT_MAX */ unsigned char subtype; /* from fstMiscType, fstArrayType, fstEnumValueType, fstPackType */ const char *name; uint64_t arg; /* number of array elements, struct members, or some other payload (possibly ignored) */ uint64_t arg_from_name; /* for when name is overloaded as a variable-length integer (FST_AT_MISC + FST_MT_SOURCESTEM) */ uint32_t name_length; /* strlen(u.attr.name) */ } attr; } u; }; struct fstETab { char *name; uint32_t elem_count; char **literal_arr; char **val_arr; }; /* * writer functions */ void fstWriterClose(void *ctx); void * fstWriterCreate(const char *nam, int use_compressed_hier); fstEnumHandle fstWriterCreateEnumTable(void *ctx, const char *name, uint32_t elem_count, unsigned int min_valbits, const char **literal_arr, const char **val_arr); /* used for Verilog/SV */ fstHandle fstWriterCreateVar(void *ctx, enum fstVarType vt, enum fstVarDir vd, uint32_t len, const char *nam, fstHandle aliasHandle); /* future expansion for VHDL and other languages. The variable type, data type, etc map onto the current Verilog/SV one. The "type" string is optional for a more verbose or custom description */ fstHandle fstWriterCreateVar2(void *ctx, enum fstVarType vt, enum fstVarDir vd, uint32_t len, const char *nam, fstHandle aliasHandle, const char *type, enum fstSupplementalVarType svt, enum fstSupplementalDataType sdt); void fstWriterEmitDumpActive(void *ctx, int enable); void fstWriterEmitEnumTableRef(void *ctx, fstEnumHandle handle); void fstWriterEmitValueChange(void *ctx, fstHandle handle, const void *val); void fstWriterEmitValueChange32(void *ctx, fstHandle handle, uint32_t bits, uint32_t val); void fstWriterEmitValueChange64(void *ctx, fstHandle handle, uint32_t bits, uint64_t val); void fstWriterEmitValueChangeVec32(void *ctx, fstHandle handle, uint32_t bits, const uint32_t *val); void fstWriterEmitValueChangeVec64(void *ctx, fstHandle handle, uint32_t bits, const uint64_t *val); void fstWriterEmitVariableLengthValueChange(void *ctx, fstHandle handle, const void *val, uint32_t len); void fstWriterEmitTimeChange(void *ctx, uint64_t tim); void fstWriterFlushContext(void *ctx); int fstWriterGetDumpSizeLimitReached(void *ctx); int fstWriterGetFseekFailed(void *ctx); void fstWriterSetAttrBegin(void *ctx, enum fstAttrType attrtype, int subtype, const char *attrname, uint64_t arg); void fstWriterSetAttrEnd(void *ctx); void fstWriterSetComment(void *ctx, const char *comm); void fstWriterSetDate(void *ctx, const char *dat); void fstWriterSetDumpSizeLimit(void *ctx, uint64_t numbytes); void fstWriterSetEnvVar(void *ctx, const char *envvar); void fstWriterSetFileType(void *ctx, enum fstFileType filetype); void fstWriterSetPackType(void *ctx, enum fstWriterPackType typ); void fstWriterSetParallelMode(void *ctx, int enable); void fstWriterSetRepackOnClose(void *ctx, int enable); /* type = 0 (none), 1 (libz) */ void fstWriterSetScope(void *ctx, enum fstScopeType scopetype, const char *scopename, const char *scopecomp); void fstWriterSetSourceInstantiationStem(void *ctx, const char *path, unsigned int line, unsigned int use_realpath); void fstWriterSetSourceStem(void *ctx, const char *path, unsigned int line, unsigned int use_realpath); void fstWriterSetTimescale(void *ctx, int ts); void fstWriterSetTimescaleFromString(void *ctx, const char *s); void fstWriterSetTimezero(void *ctx, int64_t tim); void fstWriterSetUpscope(void *ctx); void fstWriterSetValueList(void *ctx, const char *vl); void fstWriterSetVersion(void *ctx, const char *vers); /* * reader functions */ void fstReaderClose(void *ctx); void fstReaderClrFacProcessMask(void *ctx, fstHandle facidx); void fstReaderClrFacProcessMaskAll(void *ctx); uint64_t fstReaderGetAliasCount(void *ctx); const char * fstReaderGetCurrentFlatScope(void *ctx); void * fstReaderGetCurrentScopeUserInfo(void *ctx); int fstReaderGetCurrentScopeLen(void *ctx); const char * fstReaderGetDateString(void *ctx); int fstReaderGetDoubleEndianMatchState(void *ctx); uint64_t fstReaderGetDumpActivityChangeTime(void *ctx, uint32_t idx); unsigned char fstReaderGetDumpActivityChangeValue(void *ctx, uint32_t idx); uint64_t fstReaderGetEndTime(void *ctx); int fstReaderGetFacProcessMask(void *ctx, fstHandle facidx); int fstReaderGetFileType(void *ctx); int fstReaderGetFseekFailed(void *ctx); fstHandle fstReaderGetMaxHandle(void *ctx); uint64_t fstReaderGetMemoryUsedByWriter(void *ctx); uint32_t fstReaderGetNumberDumpActivityChanges(void *ctx); uint64_t fstReaderGetScopeCount(void *ctx); uint64_t fstReaderGetStartTime(void *ctx); signed char fstReaderGetTimescale(void *ctx); int64_t fstReaderGetTimezero(void *ctx); uint64_t fstReaderGetValueChangeSectionCount(void *ctx); char * fstReaderGetValueFromHandleAtTime(void *ctx, uint64_t tim, fstHandle facidx, char *buf); uint64_t fstReaderGetVarCount(void *ctx); const char * fstReaderGetVersionString(void *ctx); struct fstHier *fstReaderIterateHier(void *ctx); int fstReaderIterateHierRewind(void *ctx); int fstReaderIterBlocks(void *ctx, void (*value_change_callback)(void *user_callback_data_pointer, uint64_t time, fstHandle facidx, const unsigned char *value), void *user_callback_data_pointer, FILE *vcdhandle); int fstReaderIterBlocks2(void *ctx, void (*value_change_callback)(void *user_callback_data_pointer, uint64_t time, fstHandle facidx, const unsigned char *value), void (*value_change_callback_varlen)(void *user_callback_data_pointer, uint64_t time, fstHandle facidx, const unsigned char *value, uint32_t len), void *user_callback_data_pointer, FILE *vcdhandle); void fstReaderIterBlocksSetNativeDoublesOnCallback(void *ctx, int enable); void * fstReaderOpen(const char *nam); void * fstReaderOpenForUtilitiesOnly(void); const char * fstReaderPopScope(void *ctx); int fstReaderProcessHier(void *ctx, FILE *vcdhandle); const char * fstReaderPushScope(void *ctx, const char *nam, void *user_info); void fstReaderResetScope(void *ctx); void fstReaderSetFacProcessMask(void *ctx, fstHandle facidx); void fstReaderSetFacProcessMaskAll(void *ctx); void fstReaderSetLimitTimeRange(void *ctx, uint64_t start_time, uint64_t end_time); void fstReaderSetUnlimitedTimeRange(void *ctx); void fstReaderSetVcdExtensions(void *ctx, int enable); /* * utility functions */ int fstUtilityBinToEscConvertedLen(const unsigned char *s, int len); /* used for mallocs for fstUtilityBinToEsc() */ int fstUtilityBinToEsc(unsigned char *d, const unsigned char *s, int len); int fstUtilityEscToBin(unsigned char *d, unsigned char *s, int len); struct fstETab *fstUtilityExtractEnumTableFromString(const char *s); void fstUtilityFreeEnumTable(struct fstETab *etab); /* must use to free fstETab properly */ #ifdef __cplusplus } #endif #endif verilator-4.038/include/gtkwave/lz4.c0000664000177100017500000015325413702133367017503 0ustar wsnyderwsnyder/* LZ4 - Fast LZ compression algorithm Copyright (C) 2011-2015, Yann Collet. BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SPDX-License-Identifier: BSD-2-Clause You can contact the author at : - LZ4 source repository : https://github.com/Cyan4973/lz4 - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c */ /************************************** * Tuning parameters **************************************/ /* * HEAPMODE : * Select how default compression functions will allocate memory for their hash table, * in memory stack (0:default, fastest), or in memory heap (1:requires malloc()). */ #define HEAPMODE 0 /* * ACCELERATION_DEFAULT : * Select "acceleration" for LZ4_compress_fast() when parameter value <= 0 */ #define ACCELERATION_DEFAULT 1 /************************************** * CPU Feature Detection **************************************/ /* * LZ4_FORCE_SW_BITCOUNT * Define this parameter if your target system or compiler does not support hardware bit count */ #if defined(_MSC_VER) && defined(_WIN32_WCE) /* Visual Studio for Windows CE does not support Hardware bit count */ # define LZ4_FORCE_SW_BITCOUNT #endif /************************************** * Includes **************************************/ #include "lz4.h" /************************************** * Compiler Options **************************************/ #ifdef _MSC_VER /* Visual Studio */ # define FORCE_INLINE static __forceinline # include # pragma warning(disable : 4127) /* disable: C4127: conditional expression is constant */ # pragma warning(disable : 4293) /* disable: C4293: too large shift (32-bits) */ #else # if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */ # if defined(__GNUC__) || defined(__clang__) # define FORCE_INLINE static inline __attribute__((always_inline)) # else # define FORCE_INLINE static inline # endif # else # define FORCE_INLINE static # endif /* __STDC_VERSION__ */ #endif /* _MSC_VER */ /* LZ4_GCC_VERSION is defined into lz4.h */ #if (LZ4_GCC_VERSION >= 302) || (__INTEL_COMPILER >= 800) || defined(__clang__) # define expect(expr,value) (__builtin_expect ((expr),(value)) ) #else # define expect(expr,value) (expr) #endif #define likely(expr) expect((expr) != 0, 1) #define unlikely(expr) expect((expr) != 0, 0) /************************************** * Memory routines **************************************/ #include /* malloc, calloc, free */ #define ALLOCATOR(n,s) calloc(n,s) #define FREEMEM free #include /* memset, memcpy */ #define MEM_INIT memset /************************************** * Basic Types **************************************/ #if defined (__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */ # include typedef uint8_t BYTE; typedef uint16_t U16; typedef uint32_t U32; typedef int32_t S32; typedef uint64_t U64; #else typedef unsigned char BYTE; typedef unsigned short U16; typedef unsigned int U32; typedef signed int S32; typedef unsigned long long U64; #endif /************************************** * Reading and writing into memory **************************************/ #define STEPSIZE sizeof(size_t) static unsigned LZ4_64bits(void) { return sizeof(void*)==8; } static unsigned LZ4_isLittleEndian(void) { const union { U32 i; BYTE c[4]; } one = { 1 }; /* don't use static : performance detrimental */ return one.c[0]; } static U16 LZ4_read16(const void* memPtr) { U16 val16; memcpy(&val16, memPtr, 2); return val16; } static U16 LZ4_readLE16(const void* memPtr) { if (LZ4_isLittleEndian()) { return LZ4_read16(memPtr); } else { const BYTE* p = (const BYTE*)memPtr; return (U16)((U16)p[0] + (p[1]<<8)); } } static void LZ4_writeLE16(void* memPtr, U16 value) { if (LZ4_isLittleEndian()) { memcpy(memPtr, &value, 2); } else { BYTE* p = (BYTE*)memPtr; p[0] = (BYTE) value; p[1] = (BYTE)(value>>8); } } static U32 LZ4_read32(const void* memPtr) { U32 val32; memcpy(&val32, memPtr, 4); return val32; } static U64 LZ4_read64(const void* memPtr) { U64 val64; memcpy(&val64, memPtr, 8); return val64; } static size_t LZ4_read_ARCH(const void* p) { if (LZ4_64bits()) return (size_t)LZ4_read64(p); else return (size_t)LZ4_read32(p); } static void LZ4_copy4(void* dstPtr, const void* srcPtr) { memcpy(dstPtr, srcPtr, 4); } static void LZ4_copy8(void* dstPtr, const void* srcPtr) { memcpy(dstPtr, srcPtr, 8); } /* customized version of memcpy, which may overwrite up to 7 bytes beyond dstEnd */ static void LZ4_wildCopy(void* dstPtr, const void* srcPtr, void* dstEnd) { BYTE* d = (BYTE*)dstPtr; const BYTE* s = (const BYTE*)srcPtr; BYTE* e = (BYTE*)dstEnd; do { LZ4_copy8(d,s); d+=8; s+=8; } while (d>3); # elif (defined(__clang__) || (LZ4_GCC_VERSION >= 304)) && !defined(LZ4_FORCE_SW_BITCOUNT) return (__builtin_ctzll((U64)val) >> 3); # else static const int DeBruijnBytePos[64] = { 0, 0, 0, 0, 0, 1, 1, 2, 0, 3, 1, 3, 1, 4, 2, 7, 0, 2, 3, 6, 1, 5, 3, 5, 1, 3, 4, 4, 2, 5, 6, 7, 7, 0, 1, 2, 3, 3, 4, 6, 2, 6, 5, 5, 3, 4, 5, 6, 7, 1, 2, 4, 6, 4, 4, 5, 7, 2, 6, 5, 7, 6, 7, 7 }; return DeBruijnBytePos[((U64)((val & -(long long)val) * 0x0218A392CDABBD3FULL)) >> 58]; # endif } else /* 32 bits */ { # if defined(_MSC_VER) && !defined(LZ4_FORCE_SW_BITCOUNT) unsigned long r; _BitScanForward( &r, (U32)val ); return (int)(r>>3); # elif (defined(__clang__) || (LZ4_GCC_VERSION >= 304)) && !defined(LZ4_FORCE_SW_BITCOUNT) return (__builtin_ctz((U32)val) >> 3); # else static const int DeBruijnBytePos[32] = { 0, 0, 3, 0, 3, 1, 3, 0, 3, 2, 2, 1, 3, 2, 0, 1, 3, 3, 1, 2, 2, 2, 2, 0, 3, 1, 2, 0, 1, 0, 1, 1 }; return DeBruijnBytePos[((U32)((val & -(S32)val) * 0x077CB531U)) >> 27]; # endif } } else /* Big Endian CPU */ { if (LZ4_64bits()) { # if defined(_MSC_VER) && defined(_WIN64) && !defined(LZ4_FORCE_SW_BITCOUNT) unsigned long r = 0; _BitScanReverse64( &r, val ); return (unsigned)(r>>3); # elif (defined(__clang__) || (LZ4_GCC_VERSION >= 304)) && !defined(LZ4_FORCE_SW_BITCOUNT) return (__builtin_clzll((U64)val) >> 3); # else unsigned r; if (!(val>>32)) { r=4; } else { r=0; val>>=32; } if (!(val>>16)) { r+=2; val>>=8; } else { val>>=24; } r += (!val); return r; # endif } else /* 32 bits */ { # if defined(_MSC_VER) && !defined(LZ4_FORCE_SW_BITCOUNT) unsigned long r = 0; _BitScanReverse( &r, (unsigned long)val ); return (unsigned)(r>>3); # elif (defined(__clang__) || (LZ4_GCC_VERSION >= 304)) && !defined(LZ4_FORCE_SW_BITCOUNT) return (__builtin_clz((U32)val) >> 3); # else unsigned r; if (!(val>>16)) { r=2; val>>=8; } else { r=0; val>>=24; } r += (!val); return r; # endif } } } static unsigned LZ4_count(const BYTE* pIn, const BYTE* pMatch, const BYTE* pInLimit) { const BYTE* const pStart = pIn; while (likely(pIn compression run slower on incompressible data */ /************************************** * Local Structures and types **************************************/ typedef struct { U32 hashTable[HASH_SIZE_U32]; U32 currentOffset; U32 initCheck; const BYTE* dictionary; BYTE* bufferStart; /* obsolete, used for slideInputBuffer */ U32 dictSize; } LZ4_stream_t_internal; typedef enum { notLimited = 0, limitedOutput = 1 } limitedOutput_directive; typedef enum { byPtr, byU32, byU16 } tableType_t; typedef enum { noDict = 0, withPrefix64k, usingExtDict } dict_directive; typedef enum { noDictIssue = 0, dictSmall } dictIssue_directive; typedef enum { endOnOutputSize = 0, endOnInputSize = 1 } endCondition_directive; typedef enum { full = 0, partial = 1 } earlyEnd_directive; /************************************** * Local Utils **************************************/ int LZ4_versionNumber (void) { return LZ4_VERSION_NUMBER; } int LZ4_compressBound(int isize) { return LZ4_COMPRESSBOUND(isize); } int LZ4_sizeofState() { return LZ4_STREAMSIZE; } /******************************** * Compression functions ********************************/ static U32 LZ4_hashSequence(U32 sequence, tableType_t const tableType) { if (tableType == byU16) return (((sequence) * 2654435761U) >> ((MINMATCH*8)-(LZ4_HASHLOG+1))); else return (((sequence) * 2654435761U) >> ((MINMATCH*8)-LZ4_HASHLOG)); } static const U64 prime5bytes = 889523592379ULL; static U32 LZ4_hashSequence64(size_t sequence, tableType_t const tableType) { const U32 hashLog = (tableType == byU16) ? LZ4_HASHLOG+1 : LZ4_HASHLOG; const U32 hashMask = (1<> (40 - hashLog)) & hashMask; } static U32 LZ4_hashSequenceT(size_t sequence, tableType_t const tableType) { if (LZ4_64bits()) return LZ4_hashSequence64(sequence, tableType); return LZ4_hashSequence((U32)sequence, tableType); } static U32 LZ4_hashPosition(const void* p, tableType_t tableType) { return LZ4_hashSequenceT(LZ4_read_ARCH(p), tableType); } static void LZ4_putPositionOnHash(const BYTE* p, U32 h, void* tableBase, tableType_t const tableType, const BYTE* srcBase) { switch (tableType) { case byPtr: { const BYTE** hashTable = (const BYTE**)tableBase; hashTable[h] = p; return; } case byU32: { U32* hashTable = (U32*) tableBase; hashTable[h] = (U32)(p-srcBase); return; } case byU16: { U16* hashTable = (U16*) tableBase; hashTable[h] = (U16)(p-srcBase); return; } } } static void LZ4_putPosition(const BYTE* p, void* tableBase, tableType_t tableType, const BYTE* srcBase) { U32 h = LZ4_hashPosition(p, tableType); LZ4_putPositionOnHash(p, h, tableBase, tableType, srcBase); } static const BYTE* LZ4_getPositionOnHash(U32 h, void* tableBase, tableType_t tableType, const BYTE* srcBase) { if (tableType == byPtr) { const BYTE** hashTable = (const BYTE**) tableBase; return hashTable[h]; } if (tableType == byU32) { U32* hashTable = (U32*) tableBase; return hashTable[h] + srcBase; } { U16* hashTable = (U16*) tableBase; return hashTable[h] + srcBase; } /* default, to ensure a return */ } static const BYTE* LZ4_getPosition(const BYTE* p, void* tableBase, tableType_t tableType, const BYTE* srcBase) { U32 h = LZ4_hashPosition(p, tableType); return LZ4_getPositionOnHash(h, tableBase, tableType, srcBase); } FORCE_INLINE int LZ4_compress_generic( void* const ctx, const char* const source, char* const dest, const int inputSize, const int maxOutputSize, const limitedOutput_directive outputLimited, const tableType_t tableType, const dict_directive dict, const dictIssue_directive dictIssue, const U32 acceleration) { LZ4_stream_t_internal* const dictPtr = (LZ4_stream_t_internal*)ctx; const BYTE* ip = (const BYTE*) source; const BYTE* base; const BYTE* lowLimit; const BYTE* const lowRefLimit = ip - dictPtr->dictSize; const BYTE* const dictionary = dictPtr->dictionary; const BYTE* const dictEnd = dictionary + dictPtr->dictSize; const size_t dictDelta = dictEnd - (const BYTE*)source; const BYTE* anchor = (const BYTE*) source; const BYTE* const iend = ip + inputSize; const BYTE* const mflimit = iend - MFLIMIT; const BYTE* const matchlimit = iend - LASTLITERALS; BYTE* op = (BYTE*) dest; BYTE* const olimit = op + maxOutputSize; U32 forwardH; size_t refDelta=0; /* Init conditions */ if ((U32)inputSize > (U32)LZ4_MAX_INPUT_SIZE) return 0; /* Unsupported input size, too large (or negative) */ switch(dict) { case noDict: default: base = (const BYTE*)source; lowLimit = (const BYTE*)source; break; case withPrefix64k: base = (const BYTE*)source - dictPtr->currentOffset; lowLimit = (const BYTE*)source - dictPtr->dictSize; break; case usingExtDict: base = (const BYTE*)source - dictPtr->currentOffset; lowLimit = (const BYTE*)source; break; } if ((tableType == byU16) && (inputSize>=LZ4_64Klimit)) return 0; /* Size too large (not within 64K limit) */ if (inputSize> LZ4_skipTrigger); if (unlikely(forwardIp > mflimit)) goto _last_literals; match = LZ4_getPositionOnHash(h, ctx, tableType, base); if (dict==usingExtDict) { if (match<(const BYTE*)source) { refDelta = dictDelta; lowLimit = dictionary; } else { refDelta = 0; lowLimit = (const BYTE*)source; } } forwardH = LZ4_hashPosition(forwardIp, tableType); LZ4_putPositionOnHash(ip, h, ctx, tableType, base); } while ( ((dictIssue==dictSmall) ? (match < lowRefLimit) : 0) || ((tableType==byU16) ? 0 : (match + MAX_DISTANCE < ip)) || (LZ4_read32(match+refDelta) != LZ4_read32(ip)) ); } /* Catch up */ while ((ip>anchor) && (match+refDelta > lowLimit) && (unlikely(ip[-1]==match[refDelta-1]))) { ip--; match--; } { /* Encode Literal length */ unsigned litLength = (unsigned)(ip - anchor); token = op++; if ((outputLimited) && (unlikely(op + litLength + (2 + 1 + LASTLITERALS) + (litLength/255) > olimit))) return 0; /* Check output limit */ if (litLength>=RUN_MASK) { int len = (int)litLength-RUN_MASK; *token=(RUN_MASK<= 255 ; len-=255) *op++ = 255; *op++ = (BYTE)len; } else *token = (BYTE)(litLength< matchlimit) limit = matchlimit; matchLength = LZ4_count(ip+MINMATCH, match+MINMATCH, limit); ip += MINMATCH + matchLength; if (ip==limit) { unsigned more = LZ4_count(ip, (const BYTE*)source, matchlimit); matchLength += more; ip += more; } } else { matchLength = LZ4_count(ip+MINMATCH, match+MINMATCH, matchlimit); ip += MINMATCH + matchLength; } if ((outputLimited) && (unlikely(op + (1 + LASTLITERALS) + (matchLength>>8) > olimit))) return 0; /* Check output limit */ if (matchLength>=ML_MASK) { *token += ML_MASK; matchLength -= ML_MASK; for (; matchLength >= 510 ; matchLength-=510) { *op++ = 255; *op++ = 255; } if (matchLength >= 255) { matchLength-=255; *op++ = 255; } *op++ = (BYTE)matchLength; } else *token += (BYTE)(matchLength); } anchor = ip; /* Test end of chunk */ if (ip > mflimit) break; /* Fill table */ LZ4_putPosition(ip-2, ctx, tableType, base); /* Test next position */ match = LZ4_getPosition(ip, ctx, tableType, base); if (dict==usingExtDict) { if (match<(const BYTE*)source) { refDelta = dictDelta; lowLimit = dictionary; } else { refDelta = 0; lowLimit = (const BYTE*)source; } } LZ4_putPosition(ip, ctx, tableType, base); if ( ((dictIssue==dictSmall) ? (match>=lowRefLimit) : 1) && (match+MAX_DISTANCE>=ip) && (LZ4_read32(match+refDelta)==LZ4_read32(ip)) ) { token=op++; *token=0; goto _next_match; } /* Prepare next loop */ forwardH = LZ4_hashPosition(++ip, tableType); } _last_literals: /* Encode Last Literals */ { const size_t lastRun = (size_t)(iend - anchor); if ((outputLimited) && ((op - (BYTE*)dest) + lastRun + 1 + ((lastRun+255-RUN_MASK)/255) > (U32)maxOutputSize)) return 0; /* Check output limit */ if (lastRun >= RUN_MASK) { size_t accumulator = lastRun - RUN_MASK; *op++ = RUN_MASK << ML_BITS; for(; accumulator >= 255 ; accumulator-=255) *op++ = 255; *op++ = (BYTE) accumulator; } else { *op++ = (BYTE)(lastRun<= LZ4_compressBound(inputSize)) { if (inputSize < LZ4_64Klimit) return LZ4_compress_generic(state, source, dest, inputSize, 0, notLimited, byU16, noDict, noDictIssue, acceleration); else return LZ4_compress_generic(state, source, dest, inputSize, 0, notLimited, LZ4_64bits() ? byU32 : byPtr, noDict, noDictIssue, acceleration); } else { if (inputSize < LZ4_64Klimit) return LZ4_compress_generic(state, source, dest, inputSize, maxOutputSize, limitedOutput, byU16, noDict, noDictIssue, acceleration); else return LZ4_compress_generic(state, source, dest, inputSize, maxOutputSize, limitedOutput, LZ4_64bits() ? byU32 : byPtr, noDict, noDictIssue, acceleration); } } int LZ4_compress_fast(const char* source, char* dest, int inputSize, int maxOutputSize, int acceleration) { #if (HEAPMODE) void* ctxPtr = ALLOCATOR(1, sizeof(LZ4_stream_t)); /* malloc-calloc always properly aligned */ #else LZ4_stream_t ctx; void* ctxPtr = &ctx; #endif int result = LZ4_compress_fast_extState(ctxPtr, source, dest, inputSize, maxOutputSize, acceleration); #if (HEAPMODE) FREEMEM(ctxPtr); #endif return result; } int LZ4_compress_default(const char* source, char* dest, int inputSize, int maxOutputSize) { return LZ4_compress_fast(source, dest, inputSize, maxOutputSize, 1); } /* hidden debug function */ /* strangely enough, gcc generates faster code when this function is uncommented, even if unused */ int LZ4_compress_fast_force(const char* source, char* dest, int inputSize, int maxOutputSize, int acceleration) { LZ4_stream_t ctx; LZ4_resetStream(&ctx); if (inputSize < LZ4_64Klimit) return LZ4_compress_generic(&ctx, source, dest, inputSize, maxOutputSize, limitedOutput, byU16, noDict, noDictIssue, acceleration); else return LZ4_compress_generic(&ctx, source, dest, inputSize, maxOutputSize, limitedOutput, LZ4_64bits() ? byU32 : byPtr, noDict, noDictIssue, acceleration); } /******************************** * destSize variant ********************************/ static int LZ4_compress_destSize_generic( void* const ctx, const char* const src, char* const dst, int* const srcSizePtr, const int targetDstSize, const tableType_t tableType) { const BYTE* ip = (const BYTE*) src; const BYTE* base = (const BYTE*) src; const BYTE* lowLimit = (const BYTE*) src; const BYTE* anchor = ip; const BYTE* const iend = ip + *srcSizePtr; const BYTE* const mflimit = iend - MFLIMIT; const BYTE* const matchlimit = iend - LASTLITERALS; BYTE* op = (BYTE*) dst; BYTE* const oend = op + targetDstSize; BYTE* const oMaxLit = op + targetDstSize - 2 /* offset */ - 8 /* because 8+MINMATCH==MFLIMIT */ - 1 /* token */; BYTE* const oMaxMatch = op + targetDstSize - (LASTLITERALS + 1 /* token */); BYTE* const oMaxSeq = oMaxLit - 1 /* token */; U32 forwardH; /* Init conditions */ if (targetDstSize < 1) return 0; /* Impossible to store anything */ if ((U32)*srcSizePtr > (U32)LZ4_MAX_INPUT_SIZE) return 0; /* Unsupported input size, too large (or negative) */ if ((tableType == byU16) && (*srcSizePtr>=LZ4_64Klimit)) return 0; /* Size too large (not within 64K limit) */ if (*srcSizePtr> LZ4_skipTrigger); if (unlikely(forwardIp > mflimit)) goto _last_literals; match = LZ4_getPositionOnHash(h, ctx, tableType, base); forwardH = LZ4_hashPosition(forwardIp, tableType); LZ4_putPositionOnHash(ip, h, ctx, tableType, base); } while ( ((tableType==byU16) ? 0 : (match + MAX_DISTANCE < ip)) || (LZ4_read32(match) != LZ4_read32(ip)) ); } /* Catch up */ while ((ip>anchor) && (match > lowLimit) && (unlikely(ip[-1]==match[-1]))) { ip--; match--; } { /* Encode Literal length */ unsigned litLength = (unsigned)(ip - anchor); token = op++; if (op + ((litLength+240)/255) + litLength > oMaxLit) { /* Not enough space for a last match */ op--; goto _last_literals; } if (litLength>=RUN_MASK) { unsigned len = litLength - RUN_MASK; *token=(RUN_MASK<= 255 ; len-=255) *op++ = 255; *op++ = (BYTE)len; } else *token = (BYTE)(litLength< oMaxMatch) { /* Match description too long : reduce it */ matchLength = (15-1) + (oMaxMatch-op) * 255; } /*printf("offset %5i, matchLength%5i \n", (int)(ip-match), matchLength + MINMATCH);*/ ip += MINMATCH + matchLength; if (matchLength>=ML_MASK) { *token += ML_MASK; matchLength -= ML_MASK; while (matchLength >= 255) { matchLength-=255; *op++ = 255; } *op++ = (BYTE)matchLength; } else *token += (BYTE)(matchLength); } anchor = ip; /* Test end of block */ if (ip > mflimit) break; if (op > oMaxSeq) break; /* Fill table */ LZ4_putPosition(ip-2, ctx, tableType, base); /* Test next position */ match = LZ4_getPosition(ip, ctx, tableType, base); LZ4_putPosition(ip, ctx, tableType, base); if ( (match+MAX_DISTANCE>=ip) && (LZ4_read32(match)==LZ4_read32(ip)) ) { token=op++; *token=0; goto _next_match; } /* Prepare next loop */ forwardH = LZ4_hashPosition(++ip, tableType); } _last_literals: /* Encode Last Literals */ { size_t lastRunSize = (size_t)(iend - anchor); if (op + 1 /* token */ + ((lastRunSize+240)/255) /* litLength */ + lastRunSize /* literals */ > oend) { /* adapt lastRunSize to fill 'dst' */ lastRunSize = (oend-op) - 1; lastRunSize -= (lastRunSize+240)/255; } ip = anchor + lastRunSize; if (lastRunSize >= RUN_MASK) { size_t accumulator = lastRunSize - RUN_MASK; *op++ = RUN_MASK << ML_BITS; for(; accumulator >= 255 ; accumulator-=255) *op++ = 255; *op++ = (BYTE) accumulator; } else { *op++ = (BYTE)(lastRunSize<= LZ4_compressBound(*srcSizePtr)) /* compression success is guaranteed */ { return LZ4_compress_fast_extState(state, src, dst, *srcSizePtr, targetDstSize, 1); } else { if (*srcSizePtr < LZ4_64Klimit) return LZ4_compress_destSize_generic(state, src, dst, srcSizePtr, targetDstSize, byU16); else return LZ4_compress_destSize_generic(state, src, dst, srcSizePtr, targetDstSize, LZ4_64bits() ? byU32 : byPtr); } } int LZ4_compress_destSize(const char* src, char* dst, int* srcSizePtr, int targetDstSize) { #if (HEAPMODE) void* ctx = ALLOCATOR(1, sizeof(LZ4_stream_t)); /* malloc-calloc always properly aligned */ #else LZ4_stream_t ctxBody; void* ctx = &ctxBody; #endif int result = LZ4_compress_destSize_extState(ctx, src, dst, srcSizePtr, targetDstSize); #if (HEAPMODE) FREEMEM(ctx); #endif return result; } /******************************** * Streaming functions ********************************/ LZ4_stream_t* LZ4_createStream(void) { LZ4_stream_t* lz4s = (LZ4_stream_t*)ALLOCATOR(8, LZ4_STREAMSIZE_U64); LZ4_STATIC_ASSERT(LZ4_STREAMSIZE >= sizeof(LZ4_stream_t_internal)); /* A compilation error here means LZ4_STREAMSIZE is not large enough */ LZ4_resetStream(lz4s); return lz4s; } void LZ4_resetStream (LZ4_stream_t* LZ4_stream) { MEM_INIT(LZ4_stream, 0, sizeof(LZ4_stream_t)); } int LZ4_freeStream (LZ4_stream_t* LZ4_stream) { FREEMEM(LZ4_stream); return (0); } #define HASH_UNIT sizeof(size_t) int LZ4_loadDict (LZ4_stream_t* LZ4_dict, const char* dictionary, int dictSize) { LZ4_stream_t_internal* dict = (LZ4_stream_t_internal*) LZ4_dict; const BYTE* p = (const BYTE*)dictionary; const BYTE* const dictEnd = p + dictSize; const BYTE* base; if ((dict->initCheck) || (dict->currentOffset > 1 GB)) /* Uninitialized structure, or reuse overflow */ LZ4_resetStream(LZ4_dict); if (dictSize < (int)HASH_UNIT) { dict->dictionary = NULL; dict->dictSize = 0; return 0; } if ((dictEnd - p) > 64 KB) p = dictEnd - 64 KB; dict->currentOffset += 64 KB; base = p - dict->currentOffset; dict->dictionary = p; dict->dictSize = (U32)(dictEnd - p); dict->currentOffset += dict->dictSize; while (p <= dictEnd-HASH_UNIT) { LZ4_putPosition(p, dict->hashTable, byU32, base); p+=3; } return dict->dictSize; } static void LZ4_renormDictT(LZ4_stream_t_internal* LZ4_dict, const BYTE* src) { if ((LZ4_dict->currentOffset > 0x80000000) || ((size_t)LZ4_dict->currentOffset > (size_t)src)) /* address space overflow */ { /* rescale hash table */ U32 delta = LZ4_dict->currentOffset - 64 KB; const BYTE* dictEnd = LZ4_dict->dictionary + LZ4_dict->dictSize; int i; for (i=0; ihashTable[i] < delta) LZ4_dict->hashTable[i]=0; else LZ4_dict->hashTable[i] -= delta; } LZ4_dict->currentOffset = 64 KB; if (LZ4_dict->dictSize > 64 KB) LZ4_dict->dictSize = 64 KB; LZ4_dict->dictionary = dictEnd - LZ4_dict->dictSize; } } int LZ4_compress_fast_continue (LZ4_stream_t* LZ4_stream, const char* source, char* dest, int inputSize, int maxOutputSize, int acceleration) { LZ4_stream_t_internal* streamPtr = (LZ4_stream_t_internal*)LZ4_stream; const BYTE* const dictEnd = streamPtr->dictionary + streamPtr->dictSize; const BYTE* smallest = (const BYTE*) source; if (streamPtr->initCheck) return 0; /* Uninitialized structure detected */ if ((streamPtr->dictSize>0) && (smallest>dictEnd)) smallest = dictEnd; LZ4_renormDictT(streamPtr, smallest); if (acceleration < 1) acceleration = ACCELERATION_DEFAULT; /* Check overlapping input/dictionary space */ { const BYTE* sourceEnd = (const BYTE*) source + inputSize; if ((sourceEnd > streamPtr->dictionary) && (sourceEnd < dictEnd)) { streamPtr->dictSize = (U32)(dictEnd - sourceEnd); if (streamPtr->dictSize > 64 KB) streamPtr->dictSize = 64 KB; if (streamPtr->dictSize < 4) streamPtr->dictSize = 0; streamPtr->dictionary = dictEnd - streamPtr->dictSize; } } /* prefix mode : source data follows dictionary */ if (dictEnd == (const BYTE*)source) { int result; if ((streamPtr->dictSize < 64 KB) && (streamPtr->dictSize < streamPtr->currentOffset)) result = LZ4_compress_generic(LZ4_stream, source, dest, inputSize, maxOutputSize, limitedOutput, byU32, withPrefix64k, dictSmall, acceleration); else result = LZ4_compress_generic(LZ4_stream, source, dest, inputSize, maxOutputSize, limitedOutput, byU32, withPrefix64k, noDictIssue, acceleration); streamPtr->dictSize += (U32)inputSize; streamPtr->currentOffset += (U32)inputSize; return result; } /* external dictionary mode */ { int result; if ((streamPtr->dictSize < 64 KB) && (streamPtr->dictSize < streamPtr->currentOffset)) result = LZ4_compress_generic(LZ4_stream, source, dest, inputSize, maxOutputSize, limitedOutput, byU32, usingExtDict, dictSmall, acceleration); else result = LZ4_compress_generic(LZ4_stream, source, dest, inputSize, maxOutputSize, limitedOutput, byU32, usingExtDict, noDictIssue, acceleration); streamPtr->dictionary = (const BYTE*)source; streamPtr->dictSize = (U32)inputSize; streamPtr->currentOffset += (U32)inputSize; return result; } } /* Hidden debug function, to force external dictionary mode */ int LZ4_compress_forceExtDict (LZ4_stream_t* LZ4_dict, const char* source, char* dest, int inputSize) { LZ4_stream_t_internal* streamPtr = (LZ4_stream_t_internal*)LZ4_dict; int result; const BYTE* const dictEnd = streamPtr->dictionary + streamPtr->dictSize; const BYTE* smallest = dictEnd; if (smallest > (const BYTE*) source) smallest = (const BYTE*) source; LZ4_renormDictT((LZ4_stream_t_internal*)LZ4_dict, smallest); result = LZ4_compress_generic(LZ4_dict, source, dest, inputSize, 0, notLimited, byU32, usingExtDict, noDictIssue, 1); streamPtr->dictionary = (const BYTE*)source; streamPtr->dictSize = (U32)inputSize; streamPtr->currentOffset += (U32)inputSize; return result; } int LZ4_saveDict (LZ4_stream_t* LZ4_dict, char* safeBuffer, int dictSize) { LZ4_stream_t_internal* dict = (LZ4_stream_t_internal*) LZ4_dict; const BYTE* previousDictEnd = dict->dictionary + dict->dictSize; if ((U32)dictSize > 64 KB) dictSize = 64 KB; /* useless to define a dictionary > 64 KB */ if ((U32)dictSize > dict->dictSize) dictSize = dict->dictSize; memmove(safeBuffer, previousDictEnd - dictSize, dictSize); dict->dictionary = (const BYTE*)safeBuffer; dict->dictSize = (U32)dictSize; return dictSize; } /******************************* * Decompression functions *******************************/ /* * This generic decompression function cover all use cases. * It shall be instantiated several times, using different sets of directives * Note that it is essential this generic function is really inlined, * in order to remove useless branches during compilation optimization. */ FORCE_INLINE int LZ4_decompress_generic( const char* const source, char* const dest, int inputSize, int outputSize, /* If endOnInput==endOnInputSize, this value is the max size of Output Buffer. */ int endOnInput, /* endOnOutputSize, endOnInputSize */ int partialDecoding, /* full, partial */ int targetOutputSize, /* only used if partialDecoding==partial */ int dict, /* noDict, withPrefix64k, usingExtDict */ const BYTE* const lowPrefix, /* == dest if dict == noDict */ const BYTE* const dictStart, /* only if dict==usingExtDict */ const size_t dictSize /* note : = 0 if noDict */ ) { /* Local Variables */ const BYTE* ip = (const BYTE*) source; const BYTE* const iend = ip + inputSize; BYTE* op = (BYTE*) dest; BYTE* const oend = op + outputSize; BYTE* cpy; BYTE* oexit = op + targetOutputSize; const BYTE* const lowLimit = lowPrefix - dictSize; const BYTE* const dictEnd = (const BYTE*)dictStart + dictSize; const size_t dec32table[] = {4, 1, 2, 1, 4, 4, 4, 4}; const size_t dec64table[] = {0, 0, 0, (size_t)-1, 0, 1, 2, 3}; const int safeDecode = (endOnInput==endOnInputSize); const int checkOffset = ((safeDecode) && (dictSize < (int)(64 KB))); /* Special cases */ if ((partialDecoding) && (oexit> oend-MFLIMIT)) oexit = oend-MFLIMIT; /* targetOutputSize too high => decode everything */ if ((endOnInput) && (unlikely(outputSize==0))) return ((inputSize==1) && (*ip==0)) ? 0 : -1; /* Empty output buffer */ if ((!endOnInput) && (unlikely(outputSize==0))) return (*ip==0?1:-1); /* Main Loop */ while (1) { unsigned token; size_t length; const BYTE* match; /* get literal length */ token = *ip++; if ((length=(token>>ML_BITS)) == RUN_MASK) { unsigned s; do { s = *ip++; length += s; } while (likely((endOnInput)?ip(partialDecoding?oexit:oend-MFLIMIT)) || (ip+length>iend-(2+1+LASTLITERALS))) ) || ((!endOnInput) && (cpy>oend-COPYLENGTH))) { if (partialDecoding) { if (cpy > oend) goto _output_error; /* Error : write attempt beyond end of output buffer */ if ((endOnInput) && (ip+length > iend)) goto _output_error; /* Error : read attempt beyond end of input buffer */ } else { if ((!endOnInput) && (cpy != oend)) goto _output_error; /* Error : block decoding must stop exactly there */ if ((endOnInput) && ((ip+length != iend) || (cpy > oend))) goto _output_error; /* Error : input must be consumed */ } memcpy(op, ip, length); ip += length; op += length; break; /* Necessarily EOF, due to parsing restrictions */ } LZ4_wildCopy(op, ip, cpy); ip += length; op = cpy; /* get offset */ match = cpy - LZ4_readLE16(ip); ip+=2; if ((checkOffset) && (unlikely(match < lowLimit))) goto _output_error; /* Error : offset outside destination buffer */ /* get matchlength */ length = token & ML_MASK; if (length == ML_MASK) { unsigned s; do { if ((endOnInput) && (ip > iend-LASTLITERALS)) goto _output_error; s = *ip++; length += s; } while (s==255); if ((safeDecode) && unlikely((size_t)(op+length)<(size_t)op)) goto _output_error; /* overflow detection */ } length += MINMATCH; /* check external dictionary */ if ((dict==usingExtDict) && (match < lowPrefix)) { if (unlikely(op+length > oend-LASTLITERALS)) goto _output_error; /* doesn't respect parsing restriction */ if (length <= (size_t)(lowPrefix-match)) { /* match can be copied as a single segment from external dictionary */ match = dictEnd - (lowPrefix-match); memmove(op, match, length); op += length; } else { /* match encompass external dictionary and current segment */ size_t copySize = (size_t)(lowPrefix-match); memcpy(op, dictEnd - copySize, copySize); op += copySize; copySize = length - copySize; if (copySize > (size_t)(op-lowPrefix)) /* overlap within current segment */ { BYTE* const endOfMatch = op + copySize; const BYTE* copyFrom = lowPrefix; while (op < endOfMatch) *op++ = *copyFrom++; } else { memcpy(op, lowPrefix, copySize); op += copySize; } } continue; } /* copy repeated sequence */ cpy = op + length; if (unlikely((op-match)<8)) { const size_t dec64 = dec64table[op-match]; op[0] = match[0]; op[1] = match[1]; op[2] = match[2]; op[3] = match[3]; match += dec32table[op-match]; LZ4_copy4(op+4, match); op += 8; match -= dec64; } else { LZ4_copy8(op, match); op+=8; match+=8; } if (unlikely(cpy>oend-12)) { if (cpy > oend-LASTLITERALS) goto _output_error; /* Error : last LASTLITERALS bytes must be literals */ if (op < oend-8) { LZ4_wildCopy(op, match, oend-8); match += (oend-8) - op; op = oend-8; } while (opprefixSize = (size_t) dictSize; lz4sd->prefixEnd = (const BYTE*) dictionary + dictSize; lz4sd->externalDict = NULL; lz4sd->extDictSize = 0; return 1; } /* *_continue() : These decoding functions allow decompression of multiple blocks in "streaming" mode. Previously decoded blocks must still be available at the memory position where they were decoded. If it's not possible, save the relevant part of decoded data into a safe buffer, and indicate where it stands using LZ4_setStreamDecode() */ int LZ4_decompress_safe_continue (LZ4_streamDecode_t* LZ4_streamDecode, const char* source, char* dest, int compressedSize, int maxOutputSize) { LZ4_streamDecode_t_internal* lz4sd = (LZ4_streamDecode_t_internal*) LZ4_streamDecode; int result; if (lz4sd->prefixEnd == (BYTE*)dest) { result = LZ4_decompress_generic(source, dest, compressedSize, maxOutputSize, endOnInputSize, full, 0, usingExtDict, lz4sd->prefixEnd - lz4sd->prefixSize, lz4sd->externalDict, lz4sd->extDictSize); if (result <= 0) return result; lz4sd->prefixSize += result; lz4sd->prefixEnd += result; } else { lz4sd->extDictSize = lz4sd->prefixSize; lz4sd->externalDict = lz4sd->prefixEnd - lz4sd->extDictSize; result = LZ4_decompress_generic(source, dest, compressedSize, maxOutputSize, endOnInputSize, full, 0, usingExtDict, (BYTE*)dest, lz4sd->externalDict, lz4sd->extDictSize); if (result <= 0) return result; lz4sd->prefixSize = result; lz4sd->prefixEnd = (BYTE*)dest + result; } return result; } int LZ4_decompress_fast_continue (LZ4_streamDecode_t* LZ4_streamDecode, const char* source, char* dest, int originalSize) { LZ4_streamDecode_t_internal* lz4sd = (LZ4_streamDecode_t_internal*) LZ4_streamDecode; int result; if (lz4sd->prefixEnd == (BYTE*)dest) { result = LZ4_decompress_generic(source, dest, 0, originalSize, endOnOutputSize, full, 0, usingExtDict, lz4sd->prefixEnd - lz4sd->prefixSize, lz4sd->externalDict, lz4sd->extDictSize); if (result <= 0) return result; lz4sd->prefixSize += originalSize; lz4sd->prefixEnd += originalSize; } else { lz4sd->extDictSize = lz4sd->prefixSize; lz4sd->externalDict = (BYTE*)dest - lz4sd->extDictSize; result = LZ4_decompress_generic(source, dest, 0, originalSize, endOnOutputSize, full, 0, usingExtDict, (BYTE*)dest, lz4sd->externalDict, lz4sd->extDictSize); if (result <= 0) return result; lz4sd->prefixSize = originalSize; lz4sd->prefixEnd = (BYTE*)dest + originalSize; } return result; } /* Advanced decoding functions : *_usingDict() : These decoding functions work the same as "_continue" ones, the dictionary must be explicitly provided within parameters */ FORCE_INLINE int LZ4_decompress_usingDict_generic(const char* source, char* dest, int compressedSize, int maxOutputSize, int safe, const char* dictStart, int dictSize) { if (dictSize==0) return LZ4_decompress_generic(source, dest, compressedSize, maxOutputSize, safe, full, 0, noDict, (BYTE*)dest, NULL, 0); if (dictStart+dictSize == dest) { if (dictSize >= (int)(64 KB - 1)) return LZ4_decompress_generic(source, dest, compressedSize, maxOutputSize, safe, full, 0, withPrefix64k, (BYTE*)dest-64 KB, NULL, 0); return LZ4_decompress_generic(source, dest, compressedSize, maxOutputSize, safe, full, 0, noDict, (BYTE*)dest-dictSize, NULL, 0); } return LZ4_decompress_generic(source, dest, compressedSize, maxOutputSize, safe, full, 0, usingExtDict, (BYTE*)dest, (const BYTE*)dictStart, dictSize); } int LZ4_decompress_safe_usingDict(const char* source, char* dest, int compressedSize, int maxOutputSize, const char* dictStart, int dictSize) { return LZ4_decompress_usingDict_generic(source, dest, compressedSize, maxOutputSize, 1, dictStart, dictSize); } int LZ4_decompress_fast_usingDict(const char* source, char* dest, int originalSize, const char* dictStart, int dictSize) { return LZ4_decompress_usingDict_generic(source, dest, 0, originalSize, 0, dictStart, dictSize); } /* debug function */ int LZ4_decompress_safe_forceExtDict(const char* source, char* dest, int compressedSize, int maxOutputSize, const char* dictStart, int dictSize) { return LZ4_decompress_generic(source, dest, compressedSize, maxOutputSize, endOnInputSize, full, 0, usingExtDict, (BYTE*)dest, (const BYTE*)dictStart, dictSize); } /*************************************************** * Obsolete Functions ***************************************************/ /* obsolete compression functions */ int LZ4_compress_limitedOutput(const char* source, char* dest, int inputSize, int maxOutputSize) { return LZ4_compress_default(source, dest, inputSize, maxOutputSize); } int LZ4_compress(const char* source, char* dest, int inputSize) { return LZ4_compress_default(source, dest, inputSize, LZ4_compressBound(inputSize)); } int LZ4_compress_limitedOutput_withState (void* state, const char* src, char* dst, int srcSize, int dstSize) { return LZ4_compress_fast_extState(state, src, dst, srcSize, dstSize, 1); } int LZ4_compress_withState (void* state, const char* src, char* dst, int srcSize) { return LZ4_compress_fast_extState(state, src, dst, srcSize, LZ4_compressBound(srcSize), 1); } int LZ4_compress_limitedOutput_continue (LZ4_stream_t* LZ4_stream, const char* src, char* dst, int srcSize, int maxDstSize) { return LZ4_compress_fast_continue(LZ4_stream, src, dst, srcSize, maxDstSize, 1); } int LZ4_compress_continue (LZ4_stream_t* LZ4_stream, const char* source, char* dest, int inputSize) { return LZ4_compress_fast_continue(LZ4_stream, source, dest, inputSize, LZ4_compressBound(inputSize), 1); } /* These function names are deprecated and should no longer be used. They are only provided here for compatibility with older user programs. - LZ4_uncompress is totally equivalent to LZ4_decompress_fast - LZ4_uncompress_unknownOutputSize is totally equivalent to LZ4_decompress_safe */ int LZ4_uncompress (const char* source, char* dest, int outputSize) { return LZ4_decompress_fast(source, dest, outputSize); } int LZ4_uncompress_unknownOutputSize (const char* source, char* dest, int isize, int maxOutputSize) { return LZ4_decompress_safe(source, dest, isize, maxOutputSize); } /* Obsolete Streaming functions */ int LZ4_sizeofStreamState() { return LZ4_STREAMSIZE; } static void LZ4_init(LZ4_stream_t_internal* lz4ds, BYTE* base) { MEM_INIT(lz4ds, 0, LZ4_STREAMSIZE); lz4ds->bufferStart = base; } int LZ4_resetStreamState(void* state, char* inputBuffer) { if ((((size_t)state) & 3) != 0) return 1; /* Error : pointer is not aligned on 4-bytes boundary */ LZ4_init((LZ4_stream_t_internal*)state, (BYTE*)inputBuffer); return 0; } void* LZ4_create (char* inputBuffer) { void* lz4ds = ALLOCATOR(8, LZ4_STREAMSIZE_U64); LZ4_init ((LZ4_stream_t_internal*)lz4ds, (BYTE*)inputBuffer); return lz4ds; } char* LZ4_slideInputBuffer (void* LZ4_Data) { LZ4_stream_t_internal* ctx = (LZ4_stream_t_internal*)LZ4_Data; int dictSize = LZ4_saveDict((LZ4_stream_t*)LZ4_Data, (char*)ctx->bufferStart, 64 KB); return (char*)(ctx->bufferStart + dictSize); } /* Obsolete streaming decompression functions */ int LZ4_decompress_safe_withPrefix64k(const char* source, char* dest, int compressedSize, int maxOutputSize) { return LZ4_decompress_generic(source, dest, compressedSize, maxOutputSize, endOnInputSize, full, 0, withPrefix64k, (BYTE*)dest - 64 KB, NULL, 64 KB); } int LZ4_decompress_fast_withPrefix64k(const char* source, char* dest, int originalSize) { return LZ4_decompress_generic(source, dest, 0, originalSize, endOnOutputSize, full, 0, withPrefix64k, (BYTE*)dest - 64 KB, NULL, 64 KB); } #endif /* LZ4_COMMONDEFS_ONLY */ verilator-4.038/include/gtkwave/fstapi.c0000664000177100017500000075377113702133367020272 0ustar wsnyderwsnyder/* * Copyright (c) 2009-2018 Tony Bybell. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * SPDX-License-Identifier: MIT */ /* * possible disables: * * FST_DYNAMIC_ALIAS_DISABLE : dynamic aliases are not processed * FST_DYNAMIC_ALIAS2_DISABLE : new encoding for dynamic aliases is not generated * FST_WRITEX_DISABLE : fast write I/O routines are disabled * * possible enables: * * FST_DEBUG : not for production use, only enable for development * FST_REMOVE_DUPLICATE_VC : glitch removal (has writer performance impact) * HAVE_LIBPTHREAD -> FST_WRITER_PARALLEL : enables inclusion of parallel writer code * FST_DO_MISALIGNED_OPS (defined automatically for x86 and some others) : CPU architecture can handle misaligned loads/stores * _WAVE_HAVE_JUDY : use Judy arrays instead of Jenkins (undefine if LGPL is not acceptable) * */ #ifndef FST_CONFIG_INCLUDE # define FST_CONFIG_INCLUDE #endif #include FST_CONFIG_INCLUDE #include "fstapi.h" #include "fastlz.h" #include "lz4.h" #include #ifndef HAVE_LIBPTHREAD #undef FST_WRITER_PARALLEL #endif #ifdef FST_WRITER_PARALLEL #include #endif #ifdef __MINGW32__ #include #endif #ifdef HAVE_ALLOCA_H #include #elif defined(__GNUC__) #ifndef __MINGW32__ #ifndef alloca #define alloca __builtin_alloca #endif #else #include #endif #elif defined(_MSC_VER) #include #define alloca _alloca #endif #ifndef PATH_MAX #define PATH_MAX (4096) #endif /* note that Judy versus Jenkins requires more experimentation: they are */ /* functionally equivalent though it appears Jenkins is slightly faster. */ /* in addition, Jenkins is not bound by the LGPL. */ #ifdef _WAVE_HAVE_JUDY #include #else /* should be more than enough for fstWriterSetSourceStem() */ #define FST_PATH_HASHMASK ((1UL << 16) - 1) typedef const void *Pcvoid_t; typedef void *Pvoid_t; typedef void **PPvoid_t; #define JudyHSIns(a,b,c,d) JenkinsIns((a),(b),(c),(hashmask)) #define JudyHSFreeArray(a,b) JenkinsFree((a),(hashmask)) void JenkinsFree(void *base_i, uint32_t hashmask); void **JenkinsIns(void *base_i, const unsigned char *mem, uint32_t length, uint32_t hashmask); #endif #ifndef FST_WRITEX_DISABLE #define FST_WRITEX_MAX (64 * 1024) #else #define fstWritex(a,b,c) fstFwrite((b), (c), 1, fv) #endif /* these defines have a large impact on writer speed when a model has a */ /* huge number of symbols. as a default, use 128MB and increment when */ /* every 1M signals are defined. */ #define FST_BREAK_SIZE (1UL << 27) #define FST_BREAK_ADD_SIZE (1UL << 22) #define FST_BREAK_SIZE_MAX (1UL << 31) #define FST_ACTIVATE_HUGE_BREAK (1000000) #define FST_ACTIVATE_HUGE_INC (1000000) #define FST_WRITER_STR "fstWriter" #define FST_ID_NAM_SIZ (512) #define FST_ID_NAM_ATTR_SIZ (65536+4096) #define FST_DOUBLE_ENDTEST (2.7182818284590452354) #define FST_HDR_SIM_VERSION_SIZE (128) #define FST_HDR_DATE_SIZE (119) #define FST_HDR_FILETYPE_SIZE (1) #define FST_HDR_TIMEZERO_SIZE (8) #define FST_GZIO_LEN (32768) #define FST_HDR_FOURPACK_DUO_SIZE (4*1024*1024) #if defined(__i386__) || defined(__x86_64__) || defined(_AIX) #define FST_DO_MISALIGNED_OPS #endif #if defined(__APPLE__) && defined(__MACH__) #define FST_MACOSX #include #endif #ifdef __GNUC__ /* Boolean expression more often true than false */ #define FST_LIKELY(x) __builtin_expect(!!(x), 1) /* Boolean expression more often false than true */ #define FST_UNLIKELY(x) __builtin_expect(!!(x), 0) #else #define FST_LIKELY(x) (!!(x)) #define FST_UNLIKELY(x) (!!(x)) #endif #define FST_APIMESS "FSTAPI | " /***********************/ /*** ***/ /*** common function ***/ /*** ***/ /***********************/ #ifdef __MINGW32__ #include #ifndef HAVE_FSEEKO #define ftello ftell #define fseeko fseek #endif #endif /* * the recoded "extra" values... * note that FST_RCV_Q is currently unused and is for future expansion. * its intended use is as another level of escape such that any arbitrary * value can be stored as the value: { time_delta, 8 bits, FST_RCV_Q }. * this is currently not implemented so that the branchless decode is: * uint32_t shcnt = 2 << (vli & 1); tdelta = vli >> shcnt; */ #define FST_RCV_X (1 | (0<<1)) #define FST_RCV_Z (1 | (1<<1)) #define FST_RCV_H (1 | (2<<1)) #define FST_RCV_U (1 | (3<<1)) #define FST_RCV_W (1 | (4<<1)) #define FST_RCV_L (1 | (5<<1)) #define FST_RCV_D (1 | (6<<1)) #define FST_RCV_Q (1 | (7<<1)) #define FST_RCV_STR "xzhuwl-?" /* 01234567 */ /* * prevent old file overwrite when currently being read */ static FILE *unlink_fopen(const char *nam, const char *mode) { unlink(nam); return(fopen(nam, mode)); } /* * system-specific temp file handling */ #ifdef __MINGW32__ static FILE* tmpfile_open(char **nam) { char *fname = NULL; TCHAR szTempFileName[MAX_PATH]; TCHAR lpTempPathBuffer[MAX_PATH]; DWORD dwRetVal = 0; UINT uRetVal = 0; FILE *fh = NULL; if(nam) /* cppcheck warning fix: nam is always defined, so this is not needed */ { dwRetVal = GetTempPath(MAX_PATH, lpTempPathBuffer); if((dwRetVal > MAX_PATH) || (dwRetVal == 0)) { fprintf(stderr, FST_APIMESS "GetTempPath() failed in " __FILE__ " line %d, exiting.\n", __LINE__); exit(255); } else { uRetVal = GetTempFileName(lpTempPathBuffer, TEXT("FSTW"), 0, szTempFileName); if (uRetVal == 0) { fprintf(stderr, FST_APIMESS "GetTempFileName() failed in " __FILE__ " line %d, exiting.\n", __LINE__); exit(255); } else { fname = strdup(szTempFileName); } } if(fname) { *nam = fname; fh = unlink_fopen(fname, "w+b"); } } return(fh); } #else static FILE* tmpfile_open(char **nam) { FILE *f = tmpfile(); /* replace with mkstemp() + fopen(), etc if this is not good enough */ if(nam) { *nam = NULL; } return(f); } #endif static void tmpfile_close(FILE **f, char **nam) { if(f) { if(*f) { fclose(*f); *f = NULL; } } if(nam) { if(*nam) { unlink(*nam); free(*nam); *nam = NULL; } } } /*****************************************/ /* * to remove warn_unused_result compile time messages * (in the future there needs to be results checking) */ static size_t fstFread(void *buf, size_t siz, size_t cnt, FILE *fp) { return(fread(buf, siz, cnt, fp)); } static size_t fstFwrite(const void *buf, size_t siz, size_t cnt, FILE *fp) { return(fwrite(buf, siz, cnt, fp)); } static int fstFtruncate(int fd, off_t length) { return(ftruncate(fd, length)); } /* * realpath compatibility */ static char *fstRealpath(const char *path, char *resolved_path) { #if defined __USE_BSD || defined __USE_XOPEN_EXTENDED || defined __CYGWIN__ || defined HAVE_REALPATH #if (defined(__MACH__) && defined(__APPLE__)) if(!resolved_path) { resolved_path = (char *)malloc(PATH_MAX+1); /* fixes bug on Leopard when resolved_path == NULL */ } #endif return(realpath(path, resolved_path)); #else #ifdef __MINGW32__ if(!resolved_path) { resolved_path = (char *)malloc(PATH_MAX+1); } return(_fullpath(resolved_path, path, PATH_MAX)); #else (void)path; (void)resolved_path; return(NULL); #endif #endif } /* * mmap compatibility */ #if defined __CYGWIN__ || defined __MINGW32__ #include #define fstMmap(__addr,__len,__prot,__flags,__fd,__off) fstMmap2((__len), (__fd), (__off)) #define fstMunmap(__addr,__len) free(__addr) static void *fstMmap2(size_t __len, int __fd, off_t __off) { (void)__off; unsigned char *pnt = (unsigned char *)malloc(__len); off_t cur_offs = lseek(__fd, 0, SEEK_CUR); size_t i; lseek(__fd, 0, SEEK_SET); for(i=0;i<__len;i+=SSIZE_MAX) { read(__fd, pnt + i, ((__len - i) >= SSIZE_MAX) ? SSIZE_MAX : (__len - i)); } lseek(__fd, cur_offs, SEEK_SET); return(pnt); } #else #include #if defined(__SUNPRO_C) #define FST_CADDR_T_CAST (caddr_t) #else #define FST_CADDR_T_CAST #endif #define fstMmap(__addr,__len,__prot,__flags,__fd,__off) (void*)mmap(FST_CADDR_T_CAST (__addr),(__len),(__prot),(__flags),(__fd),(__off)) #define fstMunmap(__addr,__len) { if(__addr) munmap(FST_CADDR_T_CAST (__addr),(__len)); } #endif /* * regular and variable-length integer access functions */ #ifdef FST_DO_MISALIGNED_OPS #define fstGetUint32(x) (*(uint32_t *)(x)) #else static uint32_t fstGetUint32(unsigned char *mem) { uint32_t u32; unsigned char *buf = (unsigned char *)(&u32); buf[0] = mem[0]; buf[1] = mem[1]; buf[2] = mem[2]; buf[3] = mem[3]; return(*(uint32_t *)buf); } #endif static int fstWriterUint64(FILE *handle, uint64_t v) { unsigned char buf[8]; int i; for(i=7;i>=0;i--) { buf[i] = v & 0xff; v >>= 8; } fstFwrite(buf, 8, 1, handle); return(8); } static uint64_t fstReaderUint64(FILE *f) { uint64_t val = 0; unsigned char buf[sizeof(uint64_t)]; unsigned int i; fstFread(buf, sizeof(uint64_t), 1, f); for(i=0;i>7)) /* determine len to avoid temp buffer copying to cut down on load-hit-store */ { cnt++; } pnt -= cnt; spnt = pnt; cnt--; for(i=0;i>7; *(spnt++) = ((unsigned char)v) | 0x80; v = nxt; } *spnt = (unsigned char)v; return(pnt); } static unsigned char *fstCopyVarint64ToRight(unsigned char *pnt, uint64_t v) { uint64_t nxt; while((nxt = v>>7)) { *(pnt++) = ((unsigned char)v) | 0x80; v = nxt; } *(pnt++) = (unsigned char)v; return(pnt); } static uint64_t fstGetVarint64(unsigned char *mem, int *skiplen) { unsigned char *mem_orig = mem; uint64_t rc = 0; while(*mem & 0x80) { mem++; } *skiplen = mem - mem_orig + 1; for(;;) { rc <<= 7; rc |= (uint64_t)(*mem & 0x7f); if(mem == mem_orig) { break; } mem--; } return(rc); } static uint32_t fstReaderVarint32(FILE *f) { unsigned char buf[5]; unsigned char *mem = buf; uint32_t rc = 0; int ch; do { ch = fgetc(f); *(mem++) = ch; } while(ch & 0x80); mem--; for(;;) { rc <<= 7; rc |= (uint32_t)(*mem & 0x7f); if(mem == buf) { break; } mem--; } return(rc); } static uint32_t fstReaderVarint32WithSkip(FILE *f, uint32_t *skiplen) { unsigned char buf[5]; unsigned char *mem = buf; uint32_t rc = 0; int ch; do { ch = fgetc(f); *(mem++) = ch; } while(ch & 0x80); *skiplen = mem - buf; mem--; for(;;) { rc <<= 7; rc |= (uint32_t)(*mem & 0x7f); if(mem == buf) { break; } mem--; } return(rc); } static uint64_t fstReaderVarint64(FILE *f) { unsigned char buf[16]; unsigned char *mem = buf; uint64_t rc = 0; int ch; do { ch = fgetc(f); *(mem++) = ch; } while(ch & 0x80); mem--; for(;;) { rc <<= 7; rc |= (uint64_t)(*mem & 0x7f); if(mem == buf) { break; } mem--; } return(rc); } static int fstWriterVarint(FILE *handle, uint64_t v) { uint64_t nxt; unsigned char buf[10]; /* ceil(64/7) = 10 */ unsigned char *pnt = buf; int len; while((nxt = v>>7)) { *(pnt++) = ((unsigned char)v) | 0x80; v = nxt; } *(pnt++) = (unsigned char)v; len = pnt-buf; fstFwrite(buf, len, 1, handle); return(len); } /* signed integer read/write routines are currently unused */ static int64_t fstGetSVarint64(unsigned char *mem, int *skiplen) { unsigned char *mem_orig = mem; int64_t rc = 0; const int64_t one = 1; const int siz = sizeof(int64_t) * 8; int shift = 0; unsigned char byt; do { byt = *(mem++); rc |= ((int64_t)(byt & 0x7f)) << shift; shift += 7; } while(byt & 0x80); if((shift>= 7; if (((!v) && (!(byt & 0x40))) || ((v == -1) && (byt & 0x40))) { more = 0; byt &= 0x7f; } *(pnt++) = byt; } while(more); len = pnt-buf; fstFwrite(buf, len, 1, handle); return(len); } #endif /***********************/ /*** ***/ /*** writer function ***/ /*** ***/ /***********************/ /* * private structs */ struct fstBlackoutChain { struct fstBlackoutChain *next; uint64_t tim; unsigned active : 1; }; struct fstWriterContext { FILE *handle; FILE *hier_handle; FILE *geom_handle; FILE *valpos_handle; FILE *curval_handle; FILE *tchn_handle; unsigned char *vchg_mem; off_t hier_file_len; uint32_t *valpos_mem; unsigned char *curval_mem; unsigned char *outval_mem; /* for two-state / Verilator-style value changes */ uint32_t outval_alloc_siz; char *filename; fstHandle maxhandle; fstHandle numsigs; uint32_t maxvalpos; unsigned vc_emitted : 1; unsigned is_initial_time : 1; unsigned fourpack : 1; unsigned fastpack : 1; int64_t timezero; off_t section_header_truncpos; uint32_t tchn_cnt, tchn_idx; uint64_t curtime; uint64_t firsttime; uint32_t vchg_siz; uint32_t vchg_alloc_siz; uint32_t secnum; off_t section_start; uint32_t numscopes; double nan; /* nan value for uninitialized doubles */ struct fstBlackoutChain *blackout_head; struct fstBlackoutChain *blackout_curr; uint32_t num_blackouts; uint64_t dump_size_limit; unsigned char filetype; /* default is 0, FST_FT_VERILOG */ unsigned compress_hier : 1; unsigned repack_on_close : 1; unsigned skip_writing_section_hdr : 1; unsigned size_limit_locked : 1; unsigned section_header_only : 1; unsigned flush_context_pending : 1; unsigned parallel_enabled : 1; unsigned parallel_was_enabled : 1; /* should really be semaphores, but are bytes to cut down on read-modify-write window size */ unsigned char already_in_flush; /* in case control-c handlers interrupt */ unsigned char already_in_close; /* in case control-c handlers interrupt */ #ifdef FST_WRITER_PARALLEL pthread_mutex_t mutex; pthread_t thread; pthread_attr_t thread_attr; struct fstWriterContext *xc_parent; #endif unsigned in_pthread : 1; size_t fst_orig_break_size; size_t fst_orig_break_add_size; size_t fst_break_size; size_t fst_break_add_size; size_t fst_huge_break_size; fstHandle next_huge_break; Pvoid_t path_array; uint32_t path_array_count; unsigned fseek_failed : 1; char *geom_handle_nam; char *valpos_handle_nam; char *curval_handle_nam; char *tchn_handle_nam; fstEnumHandle max_enumhandle; }; static int fstWriterFseeko(struct fstWriterContext *xc, FILE *stream, off_t offset, int whence) { int rc = fseeko(stream, offset, whence); if(rc<0) { xc->fseek_failed = 1; #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "Seek to #%" PRId64 " (whence = %d) failed!\n", offset, whence); perror("Why"); #endif } return(rc); } static uint32_t fstWriterUint32WithVarint32(struct fstWriterContext *xc, uint32_t *u, uint32_t v, const void *dbuf, uint32_t siz) { unsigned char *buf = xc->vchg_mem + xc->vchg_siz; unsigned char *pnt = buf; uint32_t nxt; uint32_t len; #ifdef FST_DO_MISALIGNED_OPS (*(uint32_t *)(pnt)) = (*(uint32_t *)(u)); #else memcpy(pnt, u, sizeof(uint32_t)); #endif pnt += 4; while((nxt = v>>7)) { *(pnt++) = ((unsigned char)v) | 0x80; v = nxt; } *(pnt++) = (unsigned char)v; memcpy(pnt, dbuf, siz); len = pnt-buf + siz; return(len); } static uint32_t fstWriterUint32WithVarint32AndLength(struct fstWriterContext *xc, uint32_t *u, uint32_t v, const void *dbuf, uint32_t siz) { unsigned char *buf = xc->vchg_mem + xc->vchg_siz; unsigned char *pnt = buf; uint32_t nxt; uint32_t len; #ifdef FST_DO_MISALIGNED_OPS (*(uint32_t *)(pnt)) = (*(uint32_t *)(u)); #else memcpy(pnt, u, sizeof(uint32_t)); #endif pnt += 4; while((nxt = v>>7)) { *(pnt++) = ((unsigned char)v) | 0x80; v = nxt; } *(pnt++) = (unsigned char)v; v = siz; while((nxt = v>>7)) { *(pnt++) = ((unsigned char)v) | 0x80; v = nxt; } *(pnt++) = (unsigned char)v; memcpy(pnt, dbuf, siz); len = pnt-buf + siz; return(len); } /* * header bytes, write here so defines are set up before anything else * that needs to use them */ static void fstWriterEmitHdrBytes(struct fstWriterContext *xc) { char vbuf[FST_HDR_SIM_VERSION_SIZE]; char dbuf[FST_HDR_DATE_SIZE]; double endtest = FST_DOUBLE_ENDTEST; time_t walltime; #define FST_HDR_OFFS_TAG (0) fputc(FST_BL_HDR, xc->handle); /* +0 tag */ #define FST_HDR_OFFS_SECLEN (FST_HDR_OFFS_TAG + 1) fstWriterUint64(xc->handle, 329); /* +1 section length */ #define FST_HDR_OFFS_START_TIME (FST_HDR_OFFS_SECLEN + 8) fstWriterUint64(xc->handle, 0); /* +9 start time */ #define FST_HDR_OFFS_END_TIME (FST_HDR_OFFS_START_TIME + 8) fstWriterUint64(xc->handle, 0); /* +17 end time */ #define FST_HDR_OFFS_ENDIAN_TEST (FST_HDR_OFFS_END_TIME + 8) fstFwrite(&endtest, 8, 1, xc->handle); /* +25 endian test for reals */ #define FST_HDR_OFFS_MEM_USED (FST_HDR_OFFS_ENDIAN_TEST + 8) fstWriterUint64(xc->handle, xc->fst_break_size);/* +33 memory used by writer */ #define FST_HDR_OFFS_NUM_SCOPES (FST_HDR_OFFS_MEM_USED + 8) fstWriterUint64(xc->handle, 0); /* +41 scope creation count */ #define FST_HDR_OFFS_NUM_VARS (FST_HDR_OFFS_NUM_SCOPES + 8) fstWriterUint64(xc->handle, 0); /* +49 var creation count */ #define FST_HDR_OFFS_MAXHANDLE (FST_HDR_OFFS_NUM_VARS + 8) fstWriterUint64(xc->handle, 0); /* +57 max var idcode */ #define FST_HDR_OFFS_SECTION_CNT (FST_HDR_OFFS_MAXHANDLE + 8) fstWriterUint64(xc->handle, 0); /* +65 vc section count */ #define FST_HDR_OFFS_TIMESCALE (FST_HDR_OFFS_SECTION_CNT + 8) fputc((-9)&255, xc->handle); /* +73 timescale 1ns */ #define FST_HDR_OFFS_SIM_VERSION (FST_HDR_OFFS_TIMESCALE + 1) memset(vbuf, 0, FST_HDR_SIM_VERSION_SIZE); strcpy(vbuf, FST_WRITER_STR); fstFwrite(vbuf, FST_HDR_SIM_VERSION_SIZE, 1, xc->handle); /* +74 version */ #define FST_HDR_OFFS_DATE (FST_HDR_OFFS_SIM_VERSION + FST_HDR_SIM_VERSION_SIZE) memset(dbuf, 0, FST_HDR_DATE_SIZE); time(&walltime); strcpy(dbuf, asctime(localtime(&walltime))); fstFwrite(dbuf, FST_HDR_DATE_SIZE, 1, xc->handle); /* +202 date */ /* date size is deliberately overspecified at 119 bytes (originally 128) in order to provide backfill for new args */ #define FST_HDR_OFFS_FILETYPE (FST_HDR_OFFS_DATE + FST_HDR_DATE_SIZE) fputc(xc->filetype, xc->handle); /* +321 filetype */ #define FST_HDR_OFFS_TIMEZERO (FST_HDR_OFFS_FILETYPE + FST_HDR_FILETYPE_SIZE) fstWriterUint64(xc->handle, xc->timezero); /* +322 timezero */ #define FST_HDR_LENGTH (FST_HDR_OFFS_TIMEZERO + FST_HDR_TIMEZERO_SIZE) /* +330 next section starts here */ fflush(xc->handle); } /* * mmap functions */ static void fstWriterMmapSanity(void *pnt, const char *file, int line, const char *usage) { #if !defined(__CYGWIN__) && !defined(__MINGW32__) if(pnt == MAP_FAILED) { fprintf(stderr, "fstMmap() assigned to %s failed: errno: %d, file %s, line %d.\n", usage, errno, file, line); perror("Why"); pnt = NULL; } #endif } static void fstWriterCreateMmaps(struct fstWriterContext *xc) { off_t curpos = ftello(xc->handle); fflush(xc->hier_handle); /* write out intermediate header */ fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_START_TIME, SEEK_SET); fstWriterUint64(xc->handle, xc->firsttime); fstWriterUint64(xc->handle, xc->curtime); fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_NUM_SCOPES, SEEK_SET); fstWriterUint64(xc->handle, xc->numscopes); fstWriterUint64(xc->handle, xc->numsigs); fstWriterUint64(xc->handle, xc->maxhandle); fstWriterUint64(xc->handle, xc->secnum); fstWriterFseeko(xc, xc->handle, curpos, SEEK_SET); fflush(xc->handle); /* do mappings */ if(!xc->valpos_mem) { fflush(xc->valpos_handle); errno = 0; if(xc->maxhandle) { fstWriterMmapSanity(xc->valpos_mem = (uint32_t *)fstMmap(NULL, xc->maxhandle * 4 * sizeof(uint32_t), PROT_READ|PROT_WRITE, MAP_SHARED, fileno(xc->valpos_handle), 0), __FILE__, __LINE__, "xc->valpos_mem"); } } if(!xc->curval_mem) { fflush(xc->curval_handle); errno = 0; if(xc->maxvalpos) { fstWriterMmapSanity(xc->curval_mem = (unsigned char *)fstMmap(NULL, xc->maxvalpos, PROT_READ|PROT_WRITE, MAP_SHARED, fileno(xc->curval_handle), 0), __FILE__, __LINE__, "xc->curval_handle"); } } } static void fstDestroyMmaps(struct fstWriterContext *xc, int is_closing) { #if !defined __CYGWIN__ && !defined __MINGW32__ (void)is_closing; #endif fstMunmap(xc->valpos_mem, xc->maxhandle * 4 * sizeof(uint32_t)); xc->valpos_mem = NULL; #if defined __CYGWIN__ || defined __MINGW32__ if(xc->curval_mem) { if(!is_closing) /* need to flush out for next emulated mmap() read */ { unsigned char *pnt = xc->curval_mem; int __fd = fileno(xc->curval_handle); off_t cur_offs = lseek(__fd, 0, SEEK_CUR); size_t i; size_t __len = xc->maxvalpos; lseek(__fd, 0, SEEK_SET); for(i=0;i<__len;i+=SSIZE_MAX) { write(__fd, pnt + i, ((__len - i) >= SSIZE_MAX) ? SSIZE_MAX : (__len - i)); } lseek(__fd, cur_offs, SEEK_SET); } } #endif fstMunmap(xc->curval_mem, xc->maxvalpos); xc->curval_mem = NULL; } /* * set up large and small memory usages * crossover point in model is FST_ACTIVATE_HUGE_BREAK number of signals */ static void fstDetermineBreakSize(struct fstWriterContext *xc) { #if defined(__linux__) || defined(FST_MACOSX) int was_set = 0; #ifdef __linux__ FILE *f = fopen("/proc/meminfo", "rb"); if(f) { char buf[257]; char *s; while(!feof(f)) { buf[0] = 0; s = fgets(buf, 256, f); if(s && *s) { if(!strncmp(s, "MemTotal:", 9)) { size_t v = atol(s+10); v *= 1024; /* convert to bytes */ v /= 8; /* chop down to 1/8 physical memory */ if(v > FST_BREAK_SIZE) { if(v > FST_BREAK_SIZE_MAX) { v = FST_BREAK_SIZE_MAX; } xc->fst_huge_break_size = v; was_set = 1; break; } } } } fclose(f); } if(!was_set) { xc->fst_huge_break_size = FST_BREAK_SIZE; } #else int mib[2]; int64_t v; size_t length; mib[0] = CTL_HW; mib[1] = HW_MEMSIZE; length = sizeof(int64_t); if(!sysctl(mib, 2, &v, &length, NULL, 0)) { v /= 8; if(v > (int64_t)FST_BREAK_SIZE) { if(v > (int64_t)FST_BREAK_SIZE_MAX) { v = FST_BREAK_SIZE_MAX; } xc->fst_huge_break_size = v; was_set = 1; } } if(!was_set) { xc->fst_huge_break_size = FST_BREAK_SIZE; } #endif #else xc->fst_huge_break_size = FST_BREAK_SIZE; #endif xc->fst_break_size = xc->fst_orig_break_size = FST_BREAK_SIZE; xc->fst_break_add_size = xc->fst_orig_break_add_size = FST_BREAK_ADD_SIZE; xc->next_huge_break = FST_ACTIVATE_HUGE_BREAK; } /* * file creation and close */ void *fstWriterCreate(const char *nam, int use_compressed_hier) { struct fstWriterContext *xc = (struct fstWriterContext *)calloc(1, sizeof(struct fstWriterContext)); xc->compress_hier = use_compressed_hier; fstDetermineBreakSize(xc); if((!nam)|| (!(xc->handle=unlink_fopen(nam, "w+b")))) { free(xc); xc=NULL; } else { int flen = strlen(nam); char *hf = (char *)calloc(1, flen + 6); memcpy(hf, nam, flen); strcpy(hf + flen, ".hier"); xc->hier_handle = unlink_fopen(hf, "w+b"); xc->geom_handle = tmpfile_open(&xc->geom_handle_nam); /* .geom */ xc->valpos_handle = tmpfile_open(&xc->valpos_handle_nam); /* .offs */ xc->curval_handle = tmpfile_open(&xc->curval_handle_nam); /* .bits */ xc->tchn_handle = tmpfile_open(&xc->tchn_handle_nam); /* .tchn */ xc->vchg_alloc_siz = xc->fst_break_size + xc->fst_break_add_size; xc->vchg_mem = (unsigned char *)malloc(xc->vchg_alloc_siz); if(xc->hier_handle && xc->geom_handle && xc->valpos_handle && xc->curval_handle && xc->vchg_mem && xc->tchn_handle) { xc->filename = strdup(nam); xc->is_initial_time = 1; fstWriterEmitHdrBytes(xc); xc->nan = strtod("NaN", NULL); #ifdef FST_WRITER_PARALLEL pthread_mutex_init(&xc->mutex, NULL); pthread_attr_init(&xc->thread_attr); pthread_attr_setdetachstate(&xc->thread_attr, PTHREAD_CREATE_DETACHED); #endif } else { fclose(xc->handle); if(xc->hier_handle) { fclose(xc->hier_handle); unlink(hf); } tmpfile_close(&xc->geom_handle, &xc->geom_handle_nam); tmpfile_close(&xc->valpos_handle, &xc->valpos_handle_nam); tmpfile_close(&xc->curval_handle, &xc->curval_handle_nam); tmpfile_close(&xc->tchn_handle, &xc->tchn_handle_nam); free(xc->vchg_mem); free(xc); xc=NULL; } free(hf); } return(xc); } /* * generation and writing out of value change data sections */ static void fstWriterEmitSectionHeader(void *ctx) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { unsigned long destlen; unsigned char *dmem; int rc; destlen = xc->maxvalpos; dmem = (unsigned char *)malloc(compressBound(destlen)); rc = compress2(dmem, &destlen, xc->curval_mem, xc->maxvalpos, 4); /* was 9...which caused performance drag on traces with many signals */ fputc(FST_BL_SKIP, xc->handle); /* temporarily tag the section, use FST_BL_VCDATA on finalize */ xc->section_start = ftello(xc->handle); #ifdef FST_WRITER_PARALLEL if(xc->xc_parent) xc->xc_parent->section_start = xc->section_start; #endif xc->section_header_only = 1; /* indicates truncate might be needed */ fstWriterUint64(xc->handle, 0); /* placeholder = section length */ fstWriterUint64(xc->handle, xc->is_initial_time ? xc->firsttime : xc->curtime); /* begin time of section */ fstWriterUint64(xc->handle, xc->curtime); /* end time of section (placeholder) */ fstWriterUint64(xc->handle, 0); /* placeholder = amount of buffer memory required in reader for full vc traversal */ fstWriterVarint(xc->handle, xc->maxvalpos); /* maxvalpos = length of uncompressed data */ if((rc == Z_OK) && (destlen < xc->maxvalpos)) { fstWriterVarint(xc->handle, destlen); /* length of compressed data */ } else { fstWriterVarint(xc->handle, xc->maxvalpos); /* length of (unable to be) compressed data */ } fstWriterVarint(xc->handle, xc->maxhandle); /* max handle associated with this data (in case of dynamic facility adds) */ if((rc == Z_OK) && (destlen < xc->maxvalpos)) { fstFwrite(dmem, destlen, 1, xc->handle); } else /* comparison between compressed / decompressed len tells if compressed */ { fstFwrite(xc->curval_mem, xc->maxvalpos, 1, xc->handle); } free(dmem); } } /* * only to be called directly by fst code...otherwise must * be synced up with time changes */ #ifdef FST_WRITER_PARALLEL static void fstWriterFlushContextPrivate2(void *ctx) #else static void fstWriterFlushContextPrivate(void *ctx) #endif { #ifdef FST_DEBUG int cnt = 0; #endif unsigned int i; unsigned char *vchg_mem; FILE *f; off_t fpos, indxpos, endpos; uint32_t prevpos; int zerocnt; unsigned char *scratchpad; unsigned char *scratchpnt; unsigned char *tmem; off_t tlen; off_t unc_memreq = 0; /* for reader */ unsigned char *packmem; unsigned int packmemlen; uint32_t *vm4ip; struct fstWriterContext *xc = (struct fstWriterContext *)ctx; #ifdef FST_WRITER_PARALLEL struct fstWriterContext *xc2 = xc->xc_parent; #else struct fstWriterContext *xc2 = xc; #endif #ifndef FST_DYNAMIC_ALIAS_DISABLE Pvoid_t PJHSArray = (Pvoid_t) NULL; #ifndef _WAVE_HAVE_JUDY uint32_t hashmask = xc->maxhandle; hashmask |= hashmask >> 1; hashmask |= hashmask >> 2; hashmask |= hashmask >> 4; hashmask |= hashmask >> 8; hashmask |= hashmask >> 16; #endif #endif if((xc->vchg_siz <= 1)||(xc->already_in_flush)) return; xc->already_in_flush = 1; /* should really do this with a semaphore */ xc->section_header_only = 0; scratchpad = (unsigned char *)malloc(xc->vchg_siz); vchg_mem = xc->vchg_mem; f = xc->handle; fstWriterVarint(f, xc->maxhandle); /* emit current number of handles */ fputc(xc->fourpack ? '4' : (xc->fastpack ? 'F' : 'Z'), f); fpos = 1; packmemlen = 1024; /* maintain a running "longest" allocation to */ packmem = (unsigned char *)malloc(packmemlen); /* prevent continual malloc...free every loop iter */ for(i=0;imaxhandle;i++) { vm4ip = &(xc->valpos_mem[4*i]); if(vm4ip[2]) { uint32_t offs = vm4ip[2]; uint32_t next_offs; unsigned int wrlen; vm4ip[2] = fpos; scratchpnt = scratchpad + xc->vchg_siz; /* build this buffer backwards */ if(vm4ip[1] <= 1) { if(vm4ip[1] == 1) { wrlen = fstGetVarint32Length(vchg_mem + offs + 4); /* used to advance and determine wrlen */ #ifndef FST_REMOVE_DUPLICATE_VC xc->curval_mem[vm4ip[0]] = vchg_mem[offs + 4 + wrlen]; /* checkpoint variable */ #endif while(offs) { unsigned char val; uint32_t time_delta, rcv; next_offs = fstGetUint32(vchg_mem + offs); offs += 4; time_delta = fstGetVarint32(vchg_mem + offs, (int *)&wrlen); val = vchg_mem[offs+wrlen]; offs = next_offs; switch(val) { case '0': case '1': rcv = ((val&1)<<1) | (time_delta<<2); break; /* pack more delta bits in for 0/1 vchs */ case 'x': case 'X': rcv = FST_RCV_X | (time_delta<<4); break; case 'z': case 'Z': rcv = FST_RCV_Z | (time_delta<<4); break; case 'h': case 'H': rcv = FST_RCV_H | (time_delta<<4); break; case 'u': case 'U': rcv = FST_RCV_U | (time_delta<<4); break; case 'w': case 'W': rcv = FST_RCV_W | (time_delta<<4); break; case 'l': case 'L': rcv = FST_RCV_L | (time_delta<<4); break; default: rcv = FST_RCV_D | (time_delta<<4); break; } scratchpnt = fstCopyVarint32ToLeft(scratchpnt, rcv); } } else { /* variable length */ /* fstGetUint32 (next_offs) + fstGetVarint32 (time_delta) + fstGetVarint32 (len) + payload */ unsigned char *pnt; uint32_t record_len; uint32_t time_delta; while(offs) { next_offs = fstGetUint32(vchg_mem + offs); offs += 4; pnt = vchg_mem + offs; offs = next_offs; time_delta = fstGetVarint32(pnt, (int *)&wrlen); pnt += wrlen; record_len = fstGetVarint32(pnt, (int *)&wrlen); pnt += wrlen; scratchpnt -= record_len; memcpy(scratchpnt, pnt, record_len); scratchpnt = fstCopyVarint32ToLeft(scratchpnt, record_len); scratchpnt = fstCopyVarint32ToLeft(scratchpnt, (time_delta << 1)); /* reserve | 1 case for future expansion */ } } } else { wrlen = fstGetVarint32Length(vchg_mem + offs + 4); /* used to advance and determine wrlen */ #ifndef FST_REMOVE_DUPLICATE_VC memcpy(xc->curval_mem + vm4ip[0], vchg_mem + offs + 4 + wrlen, vm4ip[1]); /* checkpoint variable */ #endif while(offs) { unsigned int idx; char is_binary = 1; unsigned char *pnt; uint32_t time_delta; next_offs = fstGetUint32(vchg_mem + offs); offs += 4; time_delta = fstGetVarint32(vchg_mem + offs, (int *)&wrlen); pnt = vchg_mem+offs+wrlen; offs = next_offs; for(idx=0;idxvchg_siz - scratchpnt; unc_memreq += wrlen; if(wrlen > 32) { unsigned long destlen = wrlen; unsigned char *dmem; unsigned int rc; if(!xc->fastpack) { if(wrlen <= packmemlen) { dmem = packmem; } else { free(packmem); dmem = packmem = (unsigned char *)malloc(compressBound(packmemlen = wrlen)); } rc = compress2(dmem, &destlen, scratchpnt, wrlen, 4); if(rc == Z_OK) { #ifndef FST_DYNAMIC_ALIAS_DISABLE PPvoid_t pv = JudyHSIns(&PJHSArray, dmem, destlen, NULL); if(*pv) { uint32_t pvi = (intptr_t)(*pv); vm4ip[2] = -pvi; } else { *pv = (void *)(intptr_t)(i+1); #endif fpos += fstWriterVarint(f, wrlen); fpos += destlen; fstFwrite(dmem, destlen, 1, f); #ifndef FST_DYNAMIC_ALIAS_DISABLE } #endif } else { #ifndef FST_DYNAMIC_ALIAS_DISABLE PPvoid_t pv = JudyHSIns(&PJHSArray, scratchpnt, wrlen, NULL); if(*pv) { uint32_t pvi = (intptr_t)(*pv); vm4ip[2] = -pvi; } else { *pv = (void *)(intptr_t)(i+1); #endif fpos += fstWriterVarint(f, 0); fpos += wrlen; fstFwrite(scratchpnt, wrlen, 1, f); #ifndef FST_DYNAMIC_ALIAS_DISABLE } #endif } } else { /* this is extremely conservative: fastlz needs +5% for worst case, lz4 needs siz+(siz/255)+16 */ if(((wrlen * 2) + 2) <= packmemlen) { dmem = packmem; } else { free(packmem); dmem = packmem = (unsigned char *)malloc(packmemlen = (wrlen * 2) + 2); } rc = (xc->fourpack) ? LZ4_compress((char *)scratchpnt, (char *)dmem, wrlen) : fastlz_compress(scratchpnt, wrlen, dmem); if(rc < destlen) { #ifndef FST_DYNAMIC_ALIAS_DISABLE PPvoid_t pv = JudyHSIns(&PJHSArray, dmem, rc, NULL); if(*pv) { uint32_t pvi = (intptr_t)(*pv); vm4ip[2] = -pvi; } else { *pv = (void *)(intptr_t)(i+1); #endif fpos += fstWriterVarint(f, wrlen); fpos += rc; fstFwrite(dmem, rc, 1, f); #ifndef FST_DYNAMIC_ALIAS_DISABLE } #endif } else { #ifndef FST_DYNAMIC_ALIAS_DISABLE PPvoid_t pv = JudyHSIns(&PJHSArray, scratchpnt, wrlen, NULL); if(*pv) { uint32_t pvi = (intptr_t)(*pv); vm4ip[2] = -pvi; } else { *pv = (void *)(intptr_t)(i+1); #endif fpos += fstWriterVarint(f, 0); fpos += wrlen; fstFwrite(scratchpnt, wrlen, 1, f); #ifndef FST_DYNAMIC_ALIAS_DISABLE } #endif } } } else { #ifndef FST_DYNAMIC_ALIAS_DISABLE PPvoid_t pv = JudyHSIns(&PJHSArray, scratchpnt, wrlen, NULL); if(*pv) { uint32_t pvi = (intptr_t)(*pv); vm4ip[2] = -pvi; } else { *pv = (void *)(intptr_t)(i+1); #endif fpos += fstWriterVarint(f, 0); fpos += wrlen; fstFwrite(scratchpnt, wrlen, 1, f); #ifndef FST_DYNAMIC_ALIAS_DISABLE } #endif } /* vm4ip[3] = 0; ...redundant with clearing below */ #ifdef FST_DEBUG cnt++; #endif } } #ifndef FST_DYNAMIC_ALIAS_DISABLE JudyHSFreeArray(&PJHSArray, NULL); #endif free(packmem); packmem = NULL; /* packmemlen = 0; */ /* scan-build */ prevpos = 0; zerocnt = 0; free(scratchpad); scratchpad = NULL; indxpos = ftello(f); xc->secnum++; #ifndef FST_DYNAMIC_ALIAS2_DISABLE if(1) { uint32_t prev_alias = 0; for(i=0;imaxhandle;i++) { vm4ip = &(xc->valpos_mem[4*i]); if(vm4ip[2]) { if(zerocnt) { fpos += fstWriterVarint(f, (zerocnt << 1)); zerocnt = 0; } if(vm4ip[2] & 0x80000000) { if(vm4ip[2] != prev_alias) { fpos += fstWriterSVarint(f, (((int64_t)((int32_t)(prev_alias = vm4ip[2]))) << 1) | 1); } else { fpos += fstWriterSVarint(f, (0 << 1) | 1); } } else { fpos += fstWriterSVarint(f, ((vm4ip[2] - prevpos) << 1) | 1); prevpos = vm4ip[2]; } vm4ip[2] = 0; vm4ip[3] = 0; /* clear out tchn idx */ } else { zerocnt++; } } } else #endif { for(i=0;imaxhandle;i++) { vm4ip = &(xc->valpos_mem[4*i]); if(vm4ip[2]) { if(zerocnt) { fpos += fstWriterVarint(f, (zerocnt << 1)); zerocnt = 0; } if(vm4ip[2] & 0x80000000) { fpos += fstWriterVarint(f, 0); /* signal, note that using a *signed* varint would be more efficient than this byte escape! */ fpos += fstWriterVarint(f, (-(int32_t)vm4ip[2])); } else { fpos += fstWriterVarint(f, ((vm4ip[2] - prevpos) << 1) | 1); prevpos = vm4ip[2]; } vm4ip[2] = 0; vm4ip[3] = 0; /* clear out tchn idx */ } else { zerocnt++; } } } if(zerocnt) { /* fpos += */ fstWriterVarint(f, (zerocnt << 1)); /* scan-build */ } #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "value chains: %d\n", cnt); #endif xc->vchg_mem[0] = '!'; xc->vchg_siz = 1; endpos = ftello(xc->handle); fstWriterUint64(xc->handle, endpos-indxpos); /* write delta index position at very end of block */ /*emit time changes for block */ fflush(xc->tchn_handle); tlen = ftello(xc->tchn_handle); fstWriterFseeko(xc, xc->tchn_handle, 0, SEEK_SET); errno = 0; fstWriterMmapSanity(tmem = (unsigned char *)fstMmap(NULL, tlen, PROT_READ|PROT_WRITE, MAP_SHARED, fileno(xc->tchn_handle), 0), __FILE__, __LINE__, "tmem"); if(tmem) { unsigned long destlen = tlen; unsigned char *dmem = (unsigned char *)malloc(compressBound(destlen)); int rc = compress2(dmem, &destlen, tmem, tlen, 9); if((rc == Z_OK) && (((off_t)destlen) < tlen)) { fstFwrite(dmem, destlen, 1, xc->handle); } else /* comparison between compressed / decompressed len tells if compressed */ { fstFwrite(tmem, tlen, 1, xc->handle); destlen = tlen; } free(dmem); fstMunmap(tmem, tlen); fstWriterUint64(xc->handle, tlen); /* uncompressed */ fstWriterUint64(xc->handle, destlen); /* compressed */ fstWriterUint64(xc->handle, xc->tchn_cnt); /* number of time items */ } xc->tchn_cnt = xc->tchn_idx = 0; fstWriterFseeko(xc, xc->tchn_handle, 0, SEEK_SET); fstFtruncate(fileno(xc->tchn_handle), 0); /* write block trailer */ endpos = ftello(xc->handle); fstWriterFseeko(xc, xc->handle, xc->section_start, SEEK_SET); fstWriterUint64(xc->handle, endpos - xc->section_start); /* write block length */ fstWriterFseeko(xc, xc->handle, 8, SEEK_CUR); /* skip begin time */ fstWriterUint64(xc->handle, xc->curtime); /* write end time for section */ fstWriterUint64(xc->handle, unc_memreq); /* amount of buffer memory required in reader for full traversal */ fflush(xc->handle); fstWriterFseeko(xc, xc->handle, xc->section_start-1, SEEK_SET); /* write out FST_BL_VCDATA over FST_BL_SKIP */ #ifndef FST_DYNAMIC_ALIAS_DISABLE #ifndef FST_DYNAMIC_ALIAS2_DISABLE fputc(FST_BL_VCDATA_DYN_ALIAS2, xc->handle); #else fputc(FST_BL_VCDATA_DYN_ALIAS, xc->handle); #endif #else fputc(FST_BL_VCDATA, xc->handle); #endif fflush(xc->handle); fstWriterFseeko(xc, xc->handle, endpos, SEEK_SET); /* seek to end of file */ xc2->section_header_truncpos = endpos; /* cache in case of need to truncate */ if(xc->dump_size_limit) { if(endpos >= ((off_t)xc->dump_size_limit)) { xc2->skip_writing_section_hdr = 1; xc2->size_limit_locked = 1; xc2->is_initial_time = 1; /* to trick emit value and emit time change */ #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "<< dump file size limit reached, stopping dumping >>\n"); #endif } } if(!xc2->skip_writing_section_hdr) { fstWriterEmitSectionHeader(xc); /* emit next section header */ } fflush(xc->handle); xc->already_in_flush = 0; } #ifdef FST_WRITER_PARALLEL static void *fstWriterFlushContextPrivate1(void *ctx) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; pthread_mutex_lock(&(xc->xc_parent->mutex)); fstWriterFlushContextPrivate2(xc); #ifdef FST_REMOVE_DUPLICATE_VC free(xc->curval_mem); #endif free(xc->valpos_mem); free(xc->vchg_mem); tmpfile_close(&xc->tchn_handle, &xc->tchn_handle_nam); free(xc); xc->xc_parent->in_pthread = 0; pthread_mutex_unlock(&(xc->xc_parent->mutex)); return(NULL); } static void fstWriterFlushContextPrivate(void *ctx) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc->parallel_enabled) { struct fstWriterContext *xc2 = (struct fstWriterContext *)malloc(sizeof(struct fstWriterContext)); unsigned int i; pthread_mutex_lock(&xc->mutex); pthread_mutex_unlock(&xc->mutex); xc->xc_parent = xc; memcpy(xc2, xc, sizeof(struct fstWriterContext)); xc2->valpos_mem = (uint32_t *)malloc(xc->maxhandle * 4 * sizeof(uint32_t)); memcpy(xc2->valpos_mem, xc->valpos_mem, xc->maxhandle * 4 * sizeof(uint32_t)); /* curval mem is updated in the thread */ #ifdef FST_REMOVE_DUPLICATE_VC xc2->curval_mem = (unsigned char *)malloc(xc->maxvalpos); memcpy(xc2->curval_mem, xc->curval_mem, xc->maxvalpos); #endif xc->vchg_mem = (unsigned char *)malloc(xc->vchg_alloc_siz); xc->vchg_mem[0] = '!'; xc->vchg_siz = 1; for(i=0;imaxhandle;i++) { uint32_t *vm4ip = &(xc->valpos_mem[4*i]); vm4ip[2] = 0; /* zero out offset val */ vm4ip[3] = 0; /* zero out last time change val */ } xc->tchn_cnt = xc->tchn_idx = 0; xc->tchn_handle = tmpfile_open(&xc->tchn_handle_nam); /* child thread will deallocate file/name */ fstWriterFseeko(xc, xc->tchn_handle, 0, SEEK_SET); fstFtruncate(fileno(xc->tchn_handle), 0); xc->section_header_only = 0; xc->secnum++; while (xc->in_pthread) { pthread_mutex_lock(&xc->mutex); pthread_mutex_unlock(&xc->mutex); }; pthread_mutex_lock(&xc->mutex); xc->in_pthread = 1; pthread_mutex_unlock(&xc->mutex); pthread_create(&xc->thread, &xc->thread_attr, fstWriterFlushContextPrivate1, xc2); } else { if(xc->parallel_was_enabled) /* conservatively block */ { pthread_mutex_lock(&xc->mutex); pthread_mutex_unlock(&xc->mutex); } xc->xc_parent = xc; fstWriterFlushContextPrivate2(xc); } } #endif /* * queues up a flush context operation */ void fstWriterFlushContext(void *ctx) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { if(xc->tchn_idx > 1) { xc->flush_context_pending = 1; } } } /* * close out FST file */ void fstWriterClose(void *ctx) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; #ifdef FST_WRITER_PARALLEL if(xc) { pthread_mutex_lock(&xc->mutex); pthread_mutex_unlock(&xc->mutex); } #endif if(xc && !xc->already_in_close && !xc->already_in_flush) { unsigned char *tmem = NULL; off_t fixup_offs, tlen, hlen; xc->already_in_close = 1; /* never need to zero this out as it is freed at bottom */ if(xc->section_header_only && xc->section_header_truncpos && (xc->vchg_siz <= 1) && (!xc->is_initial_time)) { fstFtruncate(fileno(xc->handle), xc->section_header_truncpos); fstWriterFseeko(xc, xc->handle, xc->section_header_truncpos, SEEK_SET); xc->section_header_only = 0; } else { xc->skip_writing_section_hdr = 1; if(!xc->size_limit_locked) { if(FST_UNLIKELY(xc->is_initial_time)) /* simulation time never advanced so mock up the changes as time zero ones */ { fstHandle dupe_idx; fstWriterEmitTimeChange(xc, 0); /* emit some time change just to have one */ for(dupe_idx = 0; dupe_idx < xc->maxhandle; dupe_idx++) /* now clone the values */ { fstWriterEmitValueChange(xc, dupe_idx+1, xc->curval_mem + xc->valpos_mem[4*dupe_idx]); } } fstWriterFlushContextPrivate(xc); #ifdef FST_WRITER_PARALLEL pthread_mutex_lock(&xc->mutex); pthread_mutex_unlock(&xc->mutex); while (xc->in_pthread) { pthread_mutex_lock(&xc->mutex); pthread_mutex_unlock(&xc->mutex); }; #endif } } fstDestroyMmaps(xc, 1); if(xc->outval_mem) { free(xc->outval_mem); xc->outval_mem = NULL; xc->outval_alloc_siz = 0; } /* write out geom section */ fflush(xc->geom_handle); tlen = ftello(xc->geom_handle); errno = 0; if(tlen) { fstWriterMmapSanity(tmem = (unsigned char *)fstMmap(NULL, tlen, PROT_READ|PROT_WRITE, MAP_SHARED, fileno(xc->geom_handle), 0), __FILE__, __LINE__, "tmem"); } if(tmem) { unsigned long destlen = tlen; unsigned char *dmem = (unsigned char *)malloc(compressBound(destlen)); int rc = compress2(dmem, &destlen, tmem, tlen, 9); if((rc != Z_OK) || (((off_t)destlen) > tlen)) { destlen = tlen; } fixup_offs = ftello(xc->handle); fputc(FST_BL_SKIP, xc->handle); /* temporary tag */ fstWriterUint64(xc->handle, destlen + 24); /* section length */ fstWriterUint64(xc->handle, tlen); /* uncompressed */ /* compressed len is section length - 24 */ fstWriterUint64(xc->handle, xc->maxhandle); /* maxhandle */ fstFwrite((((off_t)destlen) != tlen) ? dmem : tmem, destlen, 1, xc->handle); fflush(xc->handle); fstWriterFseeko(xc, xc->handle, fixup_offs, SEEK_SET); fputc(FST_BL_GEOM, xc->handle); /* actual tag */ fstWriterFseeko(xc, xc->handle, 0, SEEK_END); /* move file pointer to end for any section adds */ fflush(xc->handle); free(dmem); fstMunmap(tmem, tlen); } if(xc->num_blackouts) { uint64_t cur_bl = 0; off_t bpos, eos; uint32_t i; fixup_offs = ftello(xc->handle); fputc(FST_BL_SKIP, xc->handle); /* temporary tag */ bpos = fixup_offs + 1; fstWriterUint64(xc->handle, 0); /* section length */ fstWriterVarint(xc->handle, xc->num_blackouts); for(i=0;inum_blackouts;i++) { fputc(xc->blackout_head->active, xc->handle); fstWriterVarint(xc->handle, xc->blackout_head->tim - cur_bl); cur_bl = xc->blackout_head->tim; xc->blackout_curr = xc->blackout_head->next; free(xc->blackout_head); xc->blackout_head = xc->blackout_curr; } eos = ftello(xc->handle); fstWriterFseeko(xc, xc->handle, bpos, SEEK_SET); fstWriterUint64(xc->handle, eos - bpos); fflush(xc->handle); fstWriterFseeko(xc, xc->handle, fixup_offs, SEEK_SET); fputc(FST_BL_BLACKOUT, xc->handle); /* actual tag */ fstWriterFseeko(xc, xc->handle, 0, SEEK_END); /* move file pointer to end for any section adds */ fflush(xc->handle); } if(xc->compress_hier) { off_t hl, eos; gzFile zhandle; int zfd; int fourpack_duo = 0; #ifndef __MINGW32__ char *fnam = (char *)malloc(strlen(xc->filename) + 5 + 1); #endif fixup_offs = ftello(xc->handle); fputc(FST_BL_SKIP, xc->handle); /* temporary tag */ hlen = ftello(xc->handle); fstWriterUint64(xc->handle, 0); /* section length */ fstWriterUint64(xc->handle, xc->hier_file_len); /* uncompressed length */ if(!xc->fourpack) { unsigned char *mem = (unsigned char *)malloc(FST_GZIO_LEN); zfd = dup(fileno(xc->handle)); fflush(xc->handle); zhandle = gzdopen(zfd, "wb4"); if(zhandle) { fstWriterFseeko(xc, xc->hier_handle, 0, SEEK_SET); for(hl = 0; hl < xc->hier_file_len; hl += FST_GZIO_LEN) { unsigned len = ((xc->hier_file_len - hl) > FST_GZIO_LEN) ? FST_GZIO_LEN : (xc->hier_file_len - hl); fstFread(mem, len, 1, xc->hier_handle); gzwrite(zhandle, mem, len); } gzclose(zhandle); } else { close(zfd); } free(mem); } else { int lz4_maxlen; unsigned char *mem; unsigned char *hmem = NULL; int packed_len; fflush(xc->handle); lz4_maxlen = LZ4_compressBound(xc->hier_file_len); mem = (unsigned char *)malloc(lz4_maxlen); errno = 0; if(xc->hier_file_len) { fstWriterMmapSanity(hmem = (unsigned char *)fstMmap(NULL, xc->hier_file_len, PROT_READ|PROT_WRITE, MAP_SHARED, fileno(xc->hier_handle), 0), __FILE__, __LINE__, "hmem"); } packed_len = LZ4_compress((char *)hmem, (char *)mem, xc->hier_file_len); fstMunmap(hmem, xc->hier_file_len); fourpack_duo = (!xc->repack_on_close) && (xc->hier_file_len > FST_HDR_FOURPACK_DUO_SIZE); /* double pack when hierarchy is large */ if(fourpack_duo) /* double packing with LZ4 is faster than gzip */ { unsigned char *mem_duo; int lz4_maxlen_duo; int packed_len_duo; lz4_maxlen_duo = LZ4_compressBound(packed_len); mem_duo = (unsigned char *)malloc(lz4_maxlen_duo); packed_len_duo = LZ4_compress((char *)mem, (char *)mem_duo, packed_len); fstWriterVarint(xc->handle, packed_len); /* 1st round compressed length */ fstFwrite(mem_duo, packed_len_duo, 1, xc->handle); free(mem_duo); } else { fstFwrite(mem, packed_len, 1, xc->handle); } free(mem); } fstWriterFseeko(xc, xc->handle, 0, SEEK_END); eos = ftello(xc->handle); fstWriterFseeko(xc, xc->handle, hlen, SEEK_SET); fstWriterUint64(xc->handle, eos - hlen); fflush(xc->handle); fstWriterFseeko(xc, xc->handle, fixup_offs, SEEK_SET); fputc(xc->fourpack ? ( fourpack_duo ? FST_BL_HIER_LZ4DUO : FST_BL_HIER_LZ4) : FST_BL_HIER, xc->handle); /* actual tag now also == compression type */ fstWriterFseeko(xc, xc->handle, 0, SEEK_END); /* move file pointer to end for any section adds */ fflush(xc->handle); #ifndef __MINGW32__ sprintf(fnam, "%s.hier", xc->filename); unlink(fnam); free(fnam); #endif } /* finalize out header */ fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_START_TIME, SEEK_SET); fstWriterUint64(xc->handle, xc->firsttime); fstWriterUint64(xc->handle, xc->curtime); fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_NUM_SCOPES, SEEK_SET); fstWriterUint64(xc->handle, xc->numscopes); fstWriterUint64(xc->handle, xc->numsigs); fstWriterUint64(xc->handle, xc->maxhandle); fstWriterUint64(xc->handle, xc->secnum); fflush(xc->handle); tmpfile_close(&xc->tchn_handle, &xc->tchn_handle_nam); free(xc->vchg_mem); xc->vchg_mem = NULL; tmpfile_close(&xc->curval_handle, &xc->curval_handle_nam); tmpfile_close(&xc->valpos_handle, &xc->valpos_handle_nam); tmpfile_close(&xc->geom_handle, &xc->geom_handle_nam); if(xc->hier_handle) { fclose(xc->hier_handle); xc->hier_handle = NULL; } if(xc->handle) { if(xc->repack_on_close) { FILE *fp; off_t offpnt, uclen; int flen = strlen(xc->filename); char *hf = (char *)calloc(1, flen + 5); strcpy(hf, xc->filename); strcpy(hf+flen, ".pak"); fp = fopen(hf, "wb"); if(fp) { gzFile dsth; int zfd; char gz_membuf[FST_GZIO_LEN]; fstWriterFseeko(xc, xc->handle, 0, SEEK_END); uclen = ftello(xc->handle); fputc(FST_BL_ZWRAPPER, fp); fstWriterUint64(fp, 0); fstWriterUint64(fp, uclen); fflush(fp); fstWriterFseeko(xc, xc->handle, 0, SEEK_SET); zfd = dup(fileno(fp)); dsth = gzdopen(zfd, "wb4"); if(dsth) { for(offpnt = 0; offpnt < uclen; offpnt += FST_GZIO_LEN) { size_t this_len = ((uclen - offpnt) > FST_GZIO_LEN) ? FST_GZIO_LEN : (uclen - offpnt); fstFread(gz_membuf, this_len, 1, xc->handle); gzwrite(dsth, gz_membuf, this_len); } gzclose(dsth); } else { close(zfd); } fstWriterFseeko(xc, fp, 0, SEEK_END); offpnt = ftello(fp); fstWriterFseeko(xc, fp, 1, SEEK_SET); fstWriterUint64(fp, offpnt - 1); fclose(fp); fclose(xc->handle); xc->handle = NULL; unlink(xc->filename); rename(hf, xc->filename); } else { xc->repack_on_close = 0; fclose(xc->handle); xc->handle = NULL; } free(hf); } else { fclose(xc->handle); xc->handle = NULL; } } #ifdef __MINGW32__ { int flen = strlen(xc->filename); char *hf = (char *)calloc(1, flen + 6); strcpy(hf, xc->filename); if(xc->compress_hier) { strcpy(hf + flen, ".hier"); unlink(hf); /* no longer needed as a section now exists for this */ } free(hf); } #endif #ifdef FST_WRITER_PARALLEL pthread_mutex_destroy(&xc->mutex); pthread_attr_destroy(&xc->thread_attr); #endif if(xc->path_array) { #ifndef _WAVE_HAVE_JUDY const uint32_t hashmask = FST_PATH_HASHMASK; #endif JudyHSFreeArray(&(xc->path_array), NULL); } free(xc->filename); xc->filename = NULL; free(xc); } } /* * functions to set miscellaneous header/block information */ void fstWriterSetDate(void *ctx, const char *dat) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { char s[FST_HDR_DATE_SIZE]; off_t fpos = ftello(xc->handle); int len = strlen(dat); fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_DATE, SEEK_SET); memset(s, 0, FST_HDR_DATE_SIZE); memcpy(s, dat, (len < FST_HDR_DATE_SIZE) ? len : FST_HDR_DATE_SIZE); fstFwrite(s, FST_HDR_DATE_SIZE, 1, xc->handle); fflush(xc->handle); fstWriterFseeko(xc, xc->handle, fpos, SEEK_SET); } } void fstWriterSetVersion(void *ctx, const char *vers) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc && vers) { char s[FST_HDR_SIM_VERSION_SIZE]; off_t fpos = ftello(xc->handle); int len = strlen(vers); fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_SIM_VERSION, SEEK_SET); memset(s, 0, FST_HDR_SIM_VERSION_SIZE); memcpy(s, vers, (len < FST_HDR_SIM_VERSION_SIZE) ? len : FST_HDR_SIM_VERSION_SIZE); fstFwrite(s, FST_HDR_SIM_VERSION_SIZE, 1, xc->handle); fflush(xc->handle); fstWriterFseeko(xc, xc->handle, fpos, SEEK_SET); } } void fstWriterSetFileType(void *ctx, enum fstFileType filetype) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { if(/*(filetype >= FST_FT_MIN) &&*/ (filetype <= FST_FT_MAX)) { off_t fpos = ftello(xc->handle); xc->filetype = filetype; fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_FILETYPE, SEEK_SET); fputc(xc->filetype, xc->handle); fflush(xc->handle); fstWriterFseeko(xc, xc->handle, fpos, SEEK_SET); } } } static void fstWriterSetAttrDoubleArgGeneric(void *ctx, int typ, uint64_t arg1, uint64_t arg2) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { unsigned char buf[11]; /* ceil(64/7) = 10 + null term */ unsigned char *pnt = fstCopyVarint64ToRight(buf, arg1); if(arg1) { *pnt = 0; /* this converts any *nonzero* arg1 when made a varint into a null-term string */ } fstWriterSetAttrBegin(xc, FST_AT_MISC, typ, (char *)buf, arg2); } } static void fstWriterSetAttrGeneric(void *ctx, const char *comm, int typ, uint64_t arg) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc && comm) { char *s = strdup(comm); char *sf = s; while(*s) { if((*s == '\n') || (*s == '\r')) *s = ' '; s++; } fstWriterSetAttrBegin(xc, FST_AT_MISC, typ, sf, arg); free(sf); } } static void fstWriterSetSourceStem_2(void *ctx, const char *path, unsigned int line, unsigned int use_realpath, int typ) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc && path && path[0]) { uint64_t sidx = 0; int slen = strlen(path); #ifndef _WAVE_HAVE_JUDY const uint32_t hashmask = FST_PATH_HASHMASK; const unsigned char *path2 = (const unsigned char *)path; PPvoid_t pv; #else char *path2 = (char *)alloca(slen + 1); /* judy lacks const qualifier in its JudyHSIns definition */ PPvoid_t pv; strcpy(path2, path); #endif pv = JudyHSIns(&(xc->path_array), path2, slen, NULL); if(*pv) { sidx = (intptr_t)(*pv); } else { char *rp = NULL; sidx = ++xc->path_array_count; *pv = (void *)(intptr_t)(xc->path_array_count); if(use_realpath) { rp = fstRealpath( #ifndef _WAVE_HAVE_JUDY (const char *) #endif path2, NULL); } fstWriterSetAttrGeneric(xc, rp ? rp : #ifndef _WAVE_HAVE_JUDY (const char *) #endif path2, FST_MT_PATHNAME, sidx); if(rp) { free(rp); } } fstWriterSetAttrDoubleArgGeneric(xc, typ, sidx, line); } } void fstWriterSetSourceStem(void *ctx, const char *path, unsigned int line, unsigned int use_realpath) { fstWriterSetSourceStem_2(ctx, path, line, use_realpath, FST_MT_SOURCESTEM); } void fstWriterSetSourceInstantiationStem(void *ctx, const char *path, unsigned int line, unsigned int use_realpath) { fstWriterSetSourceStem_2(ctx, path, line, use_realpath, FST_MT_SOURCEISTEM); } void fstWriterSetComment(void *ctx, const char *comm) { fstWriterSetAttrGeneric(ctx, comm, FST_MT_COMMENT, 0); } void fstWriterSetValueList(void *ctx, const char *vl) { fstWriterSetAttrGeneric(ctx, vl, FST_MT_VALUELIST, 0); } void fstWriterSetEnvVar(void *ctx, const char *envvar) { fstWriterSetAttrGeneric(ctx, envvar, FST_MT_ENVVAR, 0); } void fstWriterSetTimescale(void *ctx, int ts) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { off_t fpos = ftello(xc->handle); fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_TIMESCALE, SEEK_SET); fputc(ts & 255, xc->handle); fflush(xc->handle); fstWriterFseeko(xc, xc->handle, fpos, SEEK_SET); } } void fstWriterSetTimescaleFromString(void *ctx, const char *s) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc && s) { int mat = 0; int seconds_exp = -9; int tv = atoi(s); const char *pnt = s; while(*pnt) { switch(*pnt) { case 'm': seconds_exp = -3; mat = 1; break; case 'u': seconds_exp = -6; mat = 1; break; case 'n': seconds_exp = -9; mat = 1; break; case 'p': seconds_exp = -12; mat = 1; break; case 'f': seconds_exp = -15; mat = 1; break; case 'a': seconds_exp = -18; mat = 1; break; case 'z': seconds_exp = -21; mat = 1; break; case 's': seconds_exp = 0; mat = 1; break; default: break; } if(mat) break; pnt++; } if(tv == 10) { seconds_exp++; } else if(tv == 100) { seconds_exp+=2; } fstWriterSetTimescale(ctx, seconds_exp); } } void fstWriterSetTimezero(void *ctx, int64_t tim) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { off_t fpos = ftello(xc->handle); fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_TIMEZERO, SEEK_SET); fstWriterUint64(xc->handle, (xc->timezero = tim)); fflush(xc->handle); fstWriterFseeko(xc, xc->handle, fpos, SEEK_SET); } } void fstWriterSetPackType(void *ctx, enum fstWriterPackType typ) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { xc->fastpack = (typ != FST_WR_PT_ZLIB); xc->fourpack = (typ == FST_WR_PT_LZ4); } } void fstWriterSetRepackOnClose(void *ctx, int enable) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { xc->repack_on_close = (enable != 0); } } void fstWriterSetParallelMode(void *ctx, int enable) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { xc->parallel_was_enabled |= xc->parallel_enabled; /* make sticky */ xc->parallel_enabled = (enable != 0); #ifndef FST_WRITER_PARALLEL if(xc->parallel_enabled) { fprintf(stderr, FST_APIMESS "fstWriterSetParallelMode(), FST_WRITER_PARALLEL not enabled during compile, exiting.\n"); exit(255); } #endif } } void fstWriterSetDumpSizeLimit(void *ctx, uint64_t numbytes) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { xc->dump_size_limit = numbytes; } } int fstWriterGetDumpSizeLimitReached(void *ctx) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { return(xc->size_limit_locked != 0); } return(0); } int fstWriterGetFseekFailed(void *ctx) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { return(xc->fseek_failed != 0); } return(0); } /* * writer attr/scope/var creation: * fstWriterCreateVar2() is used to dump VHDL or other languages, but the * underlying variable needs to map to Verilog/SV via the proper fstVarType vt */ fstHandle fstWriterCreateVar2(void *ctx, enum fstVarType vt, enum fstVarDir vd, uint32_t len, const char *nam, fstHandle aliasHandle, const char *type, enum fstSupplementalVarType svt, enum fstSupplementalDataType sdt) { fstWriterSetAttrGeneric(ctx, type ? type : "", FST_MT_SUPVAR, (svt<valpos_mem) { fstDestroyMmaps(xc, 0); } fputc(vt, xc->hier_handle); fputc(vd, xc->hier_handle); nlen = strlen(nam); fstFwrite(nam, nlen, 1, xc->hier_handle); fputc(0, xc->hier_handle); xc->hier_file_len += (nlen+3); if((vt == FST_VT_VCD_REAL) || (vt == FST_VT_VCD_REAL_PARAMETER) || (vt == FST_VT_VCD_REALTIME) || (vt == FST_VT_SV_SHORTREAL)) { is_real = 1; len = 8; /* recast number of bytes to that of what a double is */ } else { is_real = 0; if(vt == FST_VT_GEN_STRING) { len = 0; } } xc->hier_file_len += fstWriterVarint(xc->hier_handle, len); if(aliasHandle > xc->maxhandle) aliasHandle = 0; xc->hier_file_len += fstWriterVarint(xc->hier_handle, aliasHandle); xc->numsigs++; if(xc->numsigs == xc->next_huge_break) { if(xc->fst_break_size < xc->fst_huge_break_size) { xc->next_huge_break += FST_ACTIVATE_HUGE_INC; xc->fst_break_size += xc->fst_orig_break_size; xc->fst_break_add_size += xc->fst_orig_break_add_size; xc->vchg_alloc_siz = xc->fst_break_size + xc->fst_break_add_size; if(xc->vchg_mem) { xc->vchg_mem = (unsigned char *)realloc(xc->vchg_mem, xc->vchg_alloc_siz); } } } if(!aliasHandle) { uint32_t zero = 0; if(len) { fstWriterVarint(xc->geom_handle, !is_real ? len : 0); /* geom section encodes reals as zero byte */ } else { fstWriterVarint(xc->geom_handle, 0xFFFFFFFF); /* geom section encodes zero len as 32b -1 */ } fstFwrite(&xc->maxvalpos, sizeof(uint32_t), 1, xc->valpos_handle); fstFwrite(&len, sizeof(uint32_t), 1, xc->valpos_handle); fstFwrite(&zero, sizeof(uint32_t), 1, xc->valpos_handle); fstFwrite(&zero, sizeof(uint32_t), 1, xc->valpos_handle); if(!is_real) { for(i=0;icurval_handle); } } else { fstFwrite(&xc->nan, 8, 1, xc->curval_handle); /* initialize doubles to NaN rather than x */ } xc->maxvalpos+=len; xc->maxhandle++; return(xc->maxhandle); } else { return(aliasHandle); } } return(0); } void fstWriterSetScope(void *ctx, enum fstScopeType scopetype, const char *scopename, const char *scopecomp) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { fputc(FST_ST_VCD_SCOPE, xc->hier_handle); if(/*(scopetype < FST_ST_VCD_MODULE) ||*/ (scopetype > FST_ST_MAX)) { scopetype = FST_ST_VCD_MODULE; } fputc(scopetype, xc->hier_handle); fprintf(xc->hier_handle, "%s%c%s%c", scopename ? scopename : "", 0, scopecomp ? scopecomp : "", 0); if(scopename) { xc->hier_file_len += strlen(scopename); } if(scopecomp) { xc->hier_file_len += strlen(scopecomp); } xc->hier_file_len += 4; /* FST_ST_VCD_SCOPE + scopetype + two string terminating zeros */ xc->numscopes++; } } void fstWriterSetUpscope(void *ctx) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { fputc(FST_ST_VCD_UPSCOPE, xc->hier_handle); xc->hier_file_len++; } } void fstWriterSetAttrBegin(void *ctx, enum fstAttrType attrtype, int subtype, const char *attrname, uint64_t arg) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { fputc(FST_ST_GEN_ATTRBEGIN, xc->hier_handle); if(/*(attrtype < FST_AT_MISC) ||*/ (attrtype > FST_AT_MAX)) { attrtype = FST_AT_MISC; subtype = FST_MT_UNKNOWN; } fputc(attrtype, xc->hier_handle); switch(attrtype) { case FST_AT_ARRAY: if((subtype < FST_AR_NONE) || (subtype > FST_AR_MAX)) subtype = FST_AR_NONE; break; case FST_AT_ENUM: if((subtype < FST_EV_SV_INTEGER) || (subtype > FST_EV_MAX)) subtype = FST_EV_SV_INTEGER; break; case FST_AT_PACK: if((subtype < FST_PT_NONE) || (subtype > FST_PT_MAX)) subtype = FST_PT_NONE; break; case FST_AT_MISC: default: break; } fputc(subtype, xc->hier_handle); fprintf(xc->hier_handle, "%s%c", attrname ? attrname : "", 0); if(attrname) { xc->hier_file_len += strlen(attrname); } xc->hier_file_len += 4; /* FST_ST_GEN_ATTRBEGIN + type + subtype + string terminating zero */ xc->hier_file_len += fstWriterVarint(xc->hier_handle, arg); } } void fstWriterSetAttrEnd(void *ctx) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { fputc(FST_ST_GEN_ATTREND, xc->hier_handle); xc->hier_file_len++; } } fstEnumHandle fstWriterCreateEnumTable(void *ctx, const char *name, uint32_t elem_count, unsigned int min_valbits, const char **literal_arr, const char **val_arr) { fstEnumHandle handle = 0; unsigned int *literal_lens = NULL; unsigned int *val_lens = NULL; int lit_len_tot = 0; int val_len_tot = 0; int name_len; char elem_count_buf[16]; int elem_count_len; int total_len; int pos = 0; char *attr_str = NULL; if(ctx && name && literal_arr && val_arr && (elem_count != 0)) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; uint32_t i; name_len = strlen(name); elem_count_len = sprintf(elem_count_buf, "%" PRIu32, elem_count); literal_lens = (unsigned int *)calloc(elem_count, sizeof(unsigned int)); val_lens = (unsigned int *)calloc(elem_count, sizeof(unsigned int)); for(i=0;i 0) { if(val_lens[i] < min_valbits) { val_len_tot += (min_valbits - val_lens[i]); /* additional converted len is same for '0' character */ } } } total_len = name_len + 1 + elem_count_len + 1 + lit_len_tot + elem_count + val_len_tot + elem_count; attr_str = (char*)malloc(total_len); pos = 0; memcpy(attr_str+pos, name, name_len); pos += name_len; attr_str[pos++] = ' '; memcpy(attr_str+pos, elem_count_buf, elem_count_len); pos += elem_count_len; attr_str[pos++] = ' '; for(i=0;i 0) { if(val_lens[i] < min_valbits) { memset(attr_str+pos, '0', min_valbits - val_lens[i]); pos += (min_valbits - val_lens[i]); } } pos += fstUtilityBinToEsc((unsigned char*)attr_str+pos, (unsigned char*)val_arr[i], val_lens[i]); attr_str[pos++] = ' '; } attr_str[pos-1] = 0; #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "fstWriterCreateEnumTable() total_len: %d, pos: %d\n", total_len, pos); fprintf(stderr, FST_APIMESS "*%s*\n", attr_str); #endif fstWriterSetAttrBegin(xc, FST_AT_MISC, FST_MT_ENUMTABLE, attr_str, handle = ++xc->max_enumhandle); free(attr_str); free(val_lens); free(literal_lens); } return(handle); } void fstWriterEmitEnumTableRef(void *ctx, fstEnumHandle handle) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc && handle) { fstWriterSetAttrBegin(xc, FST_AT_MISC, FST_MT_ENUMTABLE, NULL, handle); } } /* * value and time change emission */ void fstWriterEmitValueChange(void *ctx, fstHandle handle, const void *val) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; const unsigned char *buf = (const unsigned char *)val; uint32_t offs; int len; if(FST_LIKELY((xc) && (handle <= xc->maxhandle))) { uint32_t fpos; uint32_t *vm4ip; if(FST_UNLIKELY(!xc->valpos_mem)) { xc->vc_emitted = 1; fstWriterCreateMmaps(xc); } handle--; /* move starting at 1 index to starting at 0 */ vm4ip = &(xc->valpos_mem[4*handle]); len = vm4ip[1]; if(FST_LIKELY(len)) /* len of zero = variable length, use fstWriterEmitVariableLengthValueChange */ { if(FST_LIKELY(!xc->is_initial_time)) { fpos = xc->vchg_siz; if(FST_UNLIKELY((fpos + len + 10) > xc->vchg_alloc_siz)) { xc->vchg_alloc_siz += (xc->fst_break_add_size + len); /* +len added in the case of extremely long vectors and small break add sizes */ xc->vchg_mem = (unsigned char *)realloc(xc->vchg_mem, xc->vchg_alloc_siz); if(FST_UNLIKELY(!xc->vchg_mem)) { fprintf(stderr, FST_APIMESS "Could not realloc() in fstWriterEmitValueChange, exiting.\n"); exit(255); } } #ifdef FST_REMOVE_DUPLICATE_VC offs = vm4ip[0]; if(len != 1) { if((vm4ip[3]==xc->tchn_idx)&&(vm4ip[2])) { unsigned char *old_value = xc->vchg_mem + vm4ip[2] + 4; /* the +4 skips old vm4ip[2] value */ while(*(old_value++) & 0x80) { /* skips over varint encoded "xc->tchn_idx - vm4ip[3]" */ } memcpy(old_value, buf, len); /* overlay new value */ memcpy(xc->curval_mem + offs, buf, len); return; } else { if(!memcmp(xc->curval_mem + offs, buf, len)) { if(!xc->curtime) { int i; for(i=0;icurval_mem + offs, buf, len); } else { if((vm4ip[3]==xc->tchn_idx)&&(vm4ip[2])) { unsigned char *old_value = xc->vchg_mem + vm4ip[2] + 4; /* the +4 skips old vm4ip[2] value */ while(*(old_value++) & 0x80) { /* skips over varint encoded "xc->tchn_idx - vm4ip[3]" */ } *old_value = *buf; /* overlay new value */ *(xc->curval_mem + offs) = *buf; return; } else { if((*(xc->curval_mem + offs)) == (*buf)) { if(!xc->curtime) { if(*buf != 'x') return; } else { return; } } } *(xc->curval_mem + offs) = *buf; } #endif xc->vchg_siz += fstWriterUint32WithVarint32(xc, &vm4ip[2], xc->tchn_idx - vm4ip[3], buf, len); /* do one fwrite op only */ vm4ip[3] = xc->tchn_idx; vm4ip[2] = fpos; } else { offs = vm4ip[0]; memcpy(xc->curval_mem + offs, buf, len); } } } } void fstWriterEmitValueChange32(void *ctx, fstHandle handle, uint32_t bits, uint32_t val) { char buf[32]; char *s = buf; uint32_t i; for (i = 0; i < bits; ++i) { *s++ = '0' + ((val >> (bits - i - 1)) & 1); } fstWriterEmitValueChange(ctx, handle, buf); } void fstWriterEmitValueChange64(void *ctx, fstHandle handle, uint32_t bits, uint64_t val) { char buf[64]; char *s = buf; uint32_t i; for (i = 0; i < bits; ++i) { *s++ = '0' + ((val >> (bits - i - 1)) & 1); } fstWriterEmitValueChange(ctx, handle, buf); } void fstWriterEmitValueChangeVec32(void *ctx, fstHandle handle, uint32_t bits, const uint32_t *val) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if (FST_UNLIKELY(bits <= 32)) { fstWriterEmitValueChange32(ctx, handle, bits, val[0]); } else if(FST_LIKELY(xc)) { int bq = bits / 32; int br = bits & 31; int i; int w; uint32_t v; unsigned char* s; if (FST_UNLIKELY(bits > xc->outval_alloc_siz)) { xc->outval_alloc_siz = bits*2 + 1; xc->outval_mem = (unsigned char*)realloc(xc->outval_mem, xc->outval_alloc_siz); if (FST_UNLIKELY(!xc->outval_mem)) { fprintf(stderr, FST_APIMESS "Could not realloc() in fstWriterEmitValueChangeVec32, exiting.\n"); exit(255); } } s = xc->outval_mem; { w = bq; v = val[w]; for (i = 0; i < br; ++i) { *s++ = '0' + ((v >> (br - i - 1)) & 1); } } for (w = bq - 1; w >= 0; --w) { v = val[w]; for (i = (32 - 4); i >= 0; i -= 4) { s[0] = '0' + ((v >> (i + 3)) & 1); s[1] = '0' + ((v >> (i + 2)) & 1); s[2] = '0' + ((v >> (i + 1)) & 1); s[3] = '0' + ((v >> (i + 0)) & 1); s += 4; } } fstWriterEmitValueChange(ctx, handle, xc->outval_mem); } } void fstWriterEmitValueChangeVec64(void *ctx, fstHandle handle, uint32_t bits, const uint64_t *val) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if (FST_UNLIKELY(bits <= 64)) { fstWriterEmitValueChange64(ctx, handle, bits, val[0]); } else if(FST_LIKELY(xc)) { int bq = bits / 64; int br = bits & 63; int i; int w; uint32_t v; unsigned char* s; if (FST_UNLIKELY(bits > xc->outval_alloc_siz)) { xc->outval_alloc_siz = bits*2 + 1; xc->outval_mem = (unsigned char*)realloc(xc->outval_mem, xc->outval_alloc_siz); if (FST_UNLIKELY(!xc->outval_mem)) { fprintf(stderr, FST_APIMESS "Could not realloc() in fstWriterEmitValueChangeVec64, exiting.\n"); exit(255); } } s = xc->outval_mem; { w = bq; v = val[w]; for (i = 0; i < br; ++i) { *s++ = '0' + ((v >> (br - i - 1)) & 1); } } for (w = bq - 1; w >= 0; --w) { v = val[w]; for (i = (64 - 4); i >= 0; i -= 4) { s[0] = '0' + ((v >> (i + 3)) & 1); s[1] = '0' + ((v >> (i + 2)) & 1); s[2] = '0' + ((v >> (i + 1)) & 1); s[3] = '0' + ((v >> (i + 0)) & 1); s += 4; } } fstWriterEmitValueChange(ctx, handle, xc->outval_mem); } } void fstWriterEmitVariableLengthValueChange(void *ctx, fstHandle handle, const void *val, uint32_t len) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; const unsigned char *buf = (const unsigned char *)val; if(FST_LIKELY((xc) && (handle <= xc->maxhandle))) { uint32_t fpos; uint32_t *vm4ip; if(FST_UNLIKELY(!xc->valpos_mem)) { xc->vc_emitted = 1; fstWriterCreateMmaps(xc); } handle--; /* move starting at 1 index to starting at 0 */ vm4ip = &(xc->valpos_mem[4*handle]); /* there is no initial time dump for variable length value changes */ if(FST_LIKELY(!vm4ip[1])) /* len of zero = variable length */ { fpos = xc->vchg_siz; if(FST_UNLIKELY((fpos + len + 10 + 5) > xc->vchg_alloc_siz)) { xc->vchg_alloc_siz += (xc->fst_break_add_size + len + 5); /* +len added in the case of extremely long vectors and small break add sizes */ xc->vchg_mem = (unsigned char *)realloc(xc->vchg_mem, xc->vchg_alloc_siz); if(FST_UNLIKELY(!xc->vchg_mem)) { fprintf(stderr, FST_APIMESS "Could not realloc() in fstWriterEmitVariableLengthValueChange, exiting.\n"); exit(255); } } xc->vchg_siz += fstWriterUint32WithVarint32AndLength(xc, &vm4ip[2], xc->tchn_idx - vm4ip[3], buf, len); /* do one fwrite op only */ vm4ip[3] = xc->tchn_idx; vm4ip[2] = fpos; } } } void fstWriterEmitTimeChange(void *ctx, uint64_t tim) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; unsigned int i; int skip = 0; if(xc) { if(FST_UNLIKELY(xc->is_initial_time)) { if(xc->size_limit_locked) /* this resets xc->is_initial_time to one */ { return; } if(!xc->valpos_mem) { fstWriterCreateMmaps(xc); } skip = 1; xc->firsttime = (xc->vc_emitted) ? 0: tim; xc->curtime = 0; xc->vchg_mem[0] = '!'; xc->vchg_siz = 1; fstWriterEmitSectionHeader(xc); for(i=0;imaxhandle;i++) { xc->valpos_mem[4*i+2] = 0; /* zero out offset val */ xc->valpos_mem[4*i+3] = 0; /* zero out last time change val */ } xc->is_initial_time = 0; } else { if((xc->vchg_siz >= xc->fst_break_size) || (xc->flush_context_pending)) { xc->flush_context_pending = 0; fstWriterFlushContextPrivate(xc); xc->tchn_cnt++; fstWriterVarint(xc->tchn_handle, xc->curtime); } } if(!skip) { xc->tchn_idx++; } fstWriterVarint(xc->tchn_handle, tim - xc->curtime); xc->tchn_cnt++; xc->curtime = tim; } } void fstWriterEmitDumpActive(void *ctx, int enable) { struct fstWriterContext *xc = (struct fstWriterContext *)ctx; if(xc) { struct fstBlackoutChain *b = (struct fstBlackoutChain *)calloc(1, sizeof(struct fstBlackoutChain)); b->tim = xc->curtime; b->active = (enable != 0); xc->num_blackouts++; if(xc->blackout_curr) { xc->blackout_curr->next = b; xc->blackout_curr = b; } else { xc->blackout_head = b; xc->blackout_curr = b; } } } /***********************/ /*** ***/ /*** reader function ***/ /*** ***/ /***********************/ /* * private structs */ static const char *vartypes[] = { "event", "integer", "parameter", "real", "real_parameter", "reg", "supply0", "supply1", "time", "tri", "triand", "trior", "trireg", "tri0", "tri1", "wand", "wire", "wor", "port", "sparray", "realtime", "string", "bit", "logic", "int", "shortint", "longint", "byte", "enum", "shortreal" }; static const char *modtypes[] = { "module", "task", "function", "begin", "fork", "generate", "struct", "union", "class", "interface", "package", "program", "vhdl_architecture", "vhdl_procedure", "vhdl_function", "vhdl_record", "vhdl_process", "vhdl_block", "vhdl_for_generate", "vhdl_if_generate", "vhdl_generate", "vhdl_package" }; static const char *attrtypes[] = { "misc", "array", "enum", "class" }; static const char *arraytypes[] = { "none", "unpacked", "packed", "sparse" }; static const char *enumvaluetypes[] = { "integer", "bit", "logic", "int", "shortint", "longint", "byte", "unsigned_integer", "unsigned_bit", "unsigned_logic", "unsigned_int", "unsigned_shortint", "unsigned_longint", "unsigned_byte" }; static const char *packtypes[] = { "none", "unpacked", "packed", "tagged_packed" }; struct fstCurrHier { struct fstCurrHier *prev; void *user_info; int len; }; struct fstReaderContext { /* common entries */ FILE *f, *fh; uint64_t start_time, end_time; uint64_t mem_used_by_writer; uint64_t scope_count; uint64_t var_count; fstHandle maxhandle; uint64_t num_alias; uint64_t vc_section_count; uint32_t *signal_lens; /* maxhandle sized */ unsigned char *signal_typs; /* maxhandle sized */ unsigned char *process_mask; /* maxhandle-based, bitwise sized */ uint32_t longest_signal_value_len; /* longest len value encountered */ unsigned char *temp_signal_value_buf; /* malloced for len in longest_signal_value_len */ signed char timescale; unsigned char filetype; unsigned use_vcd_extensions : 1; unsigned double_endian_match : 1; unsigned native_doubles_for_cb : 1; unsigned contains_geom_section : 1; unsigned contains_hier_section : 1; /* valid for hier_pos */ unsigned contains_hier_section_lz4duo : 1; /* valid for hier_pos (contains_hier_section_lz4 always also set) */ unsigned contains_hier_section_lz4 : 1; /* valid for hier_pos */ unsigned limit_range_valid : 1; /* valid for limit_range_start, limit_range_end */ char version[FST_HDR_SIM_VERSION_SIZE + 1]; char date[FST_HDR_DATE_SIZE + 1]; int64_t timezero; char *filename, *filename_unpacked; off_t hier_pos; uint32_t num_blackouts; uint64_t *blackout_times; unsigned char *blackout_activity; uint64_t limit_range_start, limit_range_end; /* entries specific to read value at time functions */ unsigned rvat_data_valid : 1; uint64_t *rvat_time_table; uint64_t rvat_beg_tim, rvat_end_tim; unsigned char *rvat_frame_data; uint64_t rvat_frame_maxhandle; off_t *rvat_chain_table; uint32_t *rvat_chain_table_lengths; uint64_t rvat_vc_maxhandle; off_t rvat_vc_start; uint32_t *rvat_sig_offs; int rvat_packtype; uint32_t rvat_chain_len; unsigned char *rvat_chain_mem; fstHandle rvat_chain_facidx; uint32_t rvat_chain_pos_tidx; uint32_t rvat_chain_pos_idx; uint64_t rvat_chain_pos_time; unsigned rvat_chain_pos_valid : 1; /* entries specific to hierarchy traversal */ struct fstHier hier; struct fstCurrHier *curr_hier; fstHandle current_handle; char *curr_flat_hier_nam; int flat_hier_alloc_len; unsigned do_rewind : 1; char str_scope_nam[FST_ID_NAM_SIZ+1]; char str_scope_comp[FST_ID_NAM_SIZ+1]; unsigned fseek_failed : 1; /* self-buffered I/O for writes */ #ifndef FST_WRITEX_DISABLE int writex_pos; int writex_fd; unsigned char writex_buf[FST_WRITEX_MAX]; #endif char *f_nam; char *fh_nam; }; int fstReaderFseeko(struct fstReaderContext *xc, FILE *stream, off_t offset, int whence) { int rc = fseeko(stream, offset, whence); if(rc<0) { xc->fseek_failed = 1; #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "Seek to #%" PRId64 " (whence = %d) failed!\n", offset, whence); perror("Why"); #endif } return(rc); } #ifndef FST_WRITEX_DISABLE static void fstWritex(struct fstReaderContext *xc, void *v, int len) { unsigned char *s = (unsigned char *)v; if(len) { if(len < FST_WRITEX_MAX) { if(xc->writex_pos + len >= FST_WRITEX_MAX) { fstWritex(xc, NULL, 0); } memcpy(xc->writex_buf + xc->writex_pos, s, len); xc->writex_pos += len; } else { fstWritex(xc, NULL, 0); if (write(xc->writex_fd, s, len)) { }; } } else { if(xc->writex_pos) { if(write(xc->writex_fd, xc->writex_buf, xc->writex_pos)) { }; xc->writex_pos = 0; } } } #endif /* * scope -> flat name handling */ static void fstReaderDeallocateScopeData(struct fstReaderContext *xc) { struct fstCurrHier *chp; free(xc->curr_flat_hier_nam); xc->curr_flat_hier_nam = NULL; while(xc->curr_hier) { chp = xc->curr_hier->prev; free(xc->curr_hier); xc->curr_hier = chp; } } const char *fstReaderGetCurrentFlatScope(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { return(xc->curr_flat_hier_nam ? xc->curr_flat_hier_nam : ""); } else { return(NULL); } } void *fstReaderGetCurrentScopeUserInfo(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { return(xc->curr_hier ? xc->curr_hier->user_info : NULL); } else { return(NULL); } } const char *fstReaderPopScope(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc && xc->curr_hier) { struct fstCurrHier *ch = xc->curr_hier; if(xc->curr_hier->prev) { xc->curr_flat_hier_nam[xc->curr_hier->prev->len] = 0; } else { *xc->curr_flat_hier_nam = 0; } xc->curr_hier = xc->curr_hier->prev; free(ch); return(xc->curr_flat_hier_nam ? xc->curr_flat_hier_nam : ""); } return(NULL); } void fstReaderResetScope(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { while(fstReaderPopScope(xc)); /* remove any already-built scoping info */ } } const char *fstReaderPushScope(void *ctx, const char *nam, void *user_info) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { struct fstCurrHier *ch = (struct fstCurrHier *)malloc(sizeof(struct fstCurrHier)); int chl = xc->curr_hier ? xc->curr_hier->len : 0; int len = chl + 1 + strlen(nam); if(len >= xc->flat_hier_alloc_len) { xc->curr_flat_hier_nam = xc->curr_flat_hier_nam ? (char *)realloc(xc->curr_flat_hier_nam, len+1) : (char *)malloc(len+1); } if(chl) { xc->curr_flat_hier_nam[chl] = '.'; strcpy(xc->curr_flat_hier_nam + chl + 1, nam); } else { strcpy(xc->curr_flat_hier_nam, nam); len--; } ch->len = len; ch->prev = xc->curr_hier; ch->user_info = user_info; xc->curr_hier = ch; return(xc->curr_flat_hier_nam); } return(NULL); } int fstReaderGetCurrentScopeLen(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc && xc->curr_hier) { return(xc->curr_hier->len); } return(0); } int fstReaderGetFseekFailed(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { return(xc->fseek_failed != 0); } return(0); } /* * iter mask manipulation util functions */ int fstReaderGetFacProcessMask(void *ctx, fstHandle facidx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { facidx--; if(facidxmaxhandle) { int process_idx = facidx/8; int process_bit = facidx&7; return( (xc->process_mask[process_idx]&(1<maxhandle) { int idx = facidx/8; int bitpos = facidx&7; xc->process_mask[idx] |= (1<maxhandle) { int idx = facidx/8; int bitpos = facidx&7; xc->process_mask[idx] &= (~(1<process_mask, 0xff, (xc->maxhandle+7)/8); } } void fstReaderClrFacProcessMaskAll(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { memset(xc->process_mask, 0x00, (xc->maxhandle+7)/8); } } /* * various utility read/write functions */ signed char fstReaderGetTimescale(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->timescale : 0); } uint64_t fstReaderGetStartTime(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->start_time : 0); } uint64_t fstReaderGetEndTime(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->end_time : 0); } uint64_t fstReaderGetMemoryUsedByWriter(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->mem_used_by_writer : 0); } uint64_t fstReaderGetScopeCount(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->scope_count : 0); } uint64_t fstReaderGetVarCount(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->var_count : 0); } fstHandle fstReaderGetMaxHandle(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->maxhandle : 0); } uint64_t fstReaderGetAliasCount(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->num_alias : 0); } uint64_t fstReaderGetValueChangeSectionCount(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->vc_section_count : 0); } int fstReaderGetDoubleEndianMatchState(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->double_endian_match : 0); } const char *fstReaderGetVersionString(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->version : NULL); } const char *fstReaderGetDateString(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->date : NULL); } int fstReaderGetFileType(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? (int)xc->filetype : (int)FST_FT_VERILOG); } int64_t fstReaderGetTimezero(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->timezero : 0); } uint32_t fstReaderGetNumberDumpActivityChanges(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; return(xc ? xc->num_blackouts : 0); } uint64_t fstReaderGetDumpActivityChangeTime(void *ctx, uint32_t idx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc && (idx < xc->num_blackouts) && (xc->blackout_times)) { return(xc->blackout_times[idx]); } else { return(0); } } unsigned char fstReaderGetDumpActivityChangeValue(void *ctx, uint32_t idx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc && (idx < xc->num_blackouts) && (xc->blackout_activity)) { return(xc->blackout_activity[idx]); } else { return(0); } } void fstReaderSetLimitTimeRange(void *ctx, uint64_t start_time, uint64_t end_time) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { xc->limit_range_valid = 1; xc->limit_range_start = start_time; xc->limit_range_end = end_time; } } void fstReaderSetUnlimitedTimeRange(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { xc->limit_range_valid = 0; } } void fstReaderSetVcdExtensions(void *ctx, int enable) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { xc->use_vcd_extensions = (enable != 0); } } void fstReaderIterBlocksSetNativeDoublesOnCallback(void *ctx, int enable) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { xc->native_doubles_for_cb = (enable != 0); } } /* * hierarchy processing */ static void fstVcdID(char *buf, unsigned int value) { char *pnt = buf; /* zero is illegal for a value...it is assumed they start at one */ while (value) { value--; *(pnt++) = (char)('!' + value % 94); value = value / 94; } *pnt = 0; } static int fstVcdIDForFwrite(char *buf, unsigned int value) { char *pnt = buf; /* zero is illegal for a value...it is assumed they start at one */ while (value) { value--; *(pnt++) = (char)('!' + value % 94); value = value / 94; } return(pnt - buf); } static int fstReaderRecreateHierFile(struct fstReaderContext *xc) { int pass_status = 1; if(!xc->fh) { off_t offs_cache = ftello(xc->f); char *fnam = (char *)malloc(strlen(xc->filename) + 6 + 16 + 32 + 1); unsigned char *mem = (unsigned char *)malloc(FST_GZIO_LEN); off_t hl, uclen; off_t clen = 0; gzFile zhandle = NULL; int zfd; int htyp = FST_BL_SKIP; /* can't handle both set at once should never happen in a real file */ if(!xc->contains_hier_section_lz4 && xc->contains_hier_section) { htyp = FST_BL_HIER; } else if(xc->contains_hier_section_lz4 && !xc->contains_hier_section) { htyp = xc->contains_hier_section_lz4duo ? FST_BL_HIER_LZ4DUO : FST_BL_HIER_LZ4; } sprintf(fnam, "%s.hier_%d_%p", xc->filename, getpid(), (void *)xc); fstReaderFseeko(xc, xc->f, xc->hier_pos, SEEK_SET); uclen = fstReaderUint64(xc->f); #ifndef __MINGW32__ fflush(xc->f); #endif if(htyp == FST_BL_HIER) { fstReaderFseeko(xc, xc->f, xc->hier_pos, SEEK_SET); uclen = fstReaderUint64(xc->f); #ifndef __MINGW32__ fflush(xc->f); #endif zfd = dup(fileno(xc->f)); zhandle = gzdopen(zfd, "rb"); if(!zhandle) { close(zfd); free(mem); free(fnam); return(0); } } else if((htyp == FST_BL_HIER_LZ4) || (htyp == FST_BL_HIER_LZ4DUO)) { fstReaderFseeko(xc, xc->f, xc->hier_pos - 8, SEEK_SET); /* get section len */ clen = fstReaderUint64(xc->f) - 16; uclen = fstReaderUint64(xc->f); #ifndef __MINGW32__ fflush(xc->f); #endif } #ifndef __MINGW32__ xc->fh = fopen(fnam, "w+b"); if(!xc->fh) #endif { xc->fh = tmpfile_open(&xc->fh_nam); free(fnam); fnam = NULL; if(!xc->fh) { tmpfile_close(&xc->fh, &xc->fh_nam); free(mem); return(0); } } #ifndef __MINGW32__ if(fnam) unlink(fnam); #endif if(htyp == FST_BL_HIER) { for(hl = 0; hl < uclen; hl += FST_GZIO_LEN) { size_t len = ((uclen - hl) > FST_GZIO_LEN) ? FST_GZIO_LEN : (uclen - hl); size_t gzreadlen = gzread(zhandle, mem, len); /* rc should equal len... */ size_t fwlen; if(gzreadlen != len) { pass_status = 0; break; } fwlen = fstFwrite(mem, len, 1, xc->fh); if(fwlen != 1) { pass_status = 0; break; } } gzclose(zhandle); } else if(htyp == FST_BL_HIER_LZ4DUO) { unsigned char *lz4_cmem = (unsigned char *)malloc(clen); unsigned char *lz4_ucmem = (unsigned char *)malloc(uclen); unsigned char *lz4_ucmem2; uint64_t uclen2; int skiplen2 = 0; fstFread(lz4_cmem, clen, 1, xc->f); uclen2 = fstGetVarint64(lz4_cmem, &skiplen2); lz4_ucmem2 = (unsigned char *)malloc(uclen2); pass_status = (uclen2 == (uint64_t)LZ4_decompress_safe_partial ((char *)lz4_cmem + skiplen2, (char *)lz4_ucmem2, clen - skiplen2, uclen2, uclen2)); if(pass_status) { pass_status = (uclen == LZ4_decompress_safe_partial ((char *)lz4_ucmem2, (char *)lz4_ucmem, uclen2, uclen, uclen)); if(fstFwrite(lz4_ucmem, uclen, 1, xc->fh) != 1) { pass_status = 0; } } free(lz4_ucmem2); free(lz4_ucmem); free(lz4_cmem); } else if(htyp == FST_BL_HIER_LZ4) { unsigned char *lz4_cmem = (unsigned char *)malloc(clen); unsigned char *lz4_ucmem = (unsigned char *)malloc(uclen); fstFread(lz4_cmem, clen, 1, xc->f); pass_status = (uclen == LZ4_decompress_safe_partial ((char *)lz4_cmem, (char *)lz4_ucmem, clen, uclen, uclen)); if(fstFwrite(lz4_ucmem, uclen, 1, xc->fh) != 1) { pass_status = 0; } free(lz4_ucmem); free(lz4_cmem); } else /* FST_BL_SKIP */ { pass_status = 0; if(xc->fh) { fclose(xc->fh); xc->fh = NULL; /* needed in case .hier file is missing and there are no hier sections */ } } free(mem); free(fnam); fstReaderFseeko(xc, xc->f, offs_cache, SEEK_SET); } return(pass_status); } int fstReaderIterateHierRewind(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; int pass_status = 0; if(xc) { pass_status = 1; if(!xc->fh) { pass_status = fstReaderRecreateHierFile(xc); } xc->do_rewind = 1; } return(pass_status); } struct fstHier *fstReaderIterateHier(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; int isfeof; fstHandle alias; char *pnt; int ch; if(!xc) return(NULL); if(!xc->fh) { if(!fstReaderRecreateHierFile(xc)) { return(NULL); } } if(xc->do_rewind) { xc->do_rewind = 0; xc->current_handle = 0; fstReaderFseeko(xc, xc->fh, 0, SEEK_SET); clearerr(xc->fh); } if(!(isfeof=feof(xc->fh))) { int tag = fgetc(xc->fh); switch(tag) { case FST_ST_VCD_SCOPE: xc->hier.htyp = FST_HT_SCOPE; xc->hier.u.scope.typ = fgetc(xc->fh); xc->hier.u.scope.name = pnt = xc->str_scope_nam; while((ch = fgetc(xc->fh))) { *(pnt++) = ch; }; /* scopename */ *pnt = 0; xc->hier.u.scope.name_length = pnt - xc->hier.u.scope.name; xc->hier.u.scope.component = pnt = xc->str_scope_comp; while((ch = fgetc(xc->fh))) { *(pnt++) = ch; }; /* scopecomp */ *pnt = 0; xc->hier.u.scope.component_length = pnt - xc->hier.u.scope.component; break; case FST_ST_VCD_UPSCOPE: xc->hier.htyp = FST_HT_UPSCOPE; break; case FST_ST_GEN_ATTRBEGIN: xc->hier.htyp = FST_HT_ATTRBEGIN; xc->hier.u.attr.typ = fgetc(xc->fh); xc->hier.u.attr.subtype = fgetc(xc->fh); xc->hier.u.attr.name = pnt = xc->str_scope_nam; while((ch = fgetc(xc->fh))) { *(pnt++) = ch; }; /* scopename */ *pnt = 0; xc->hier.u.attr.name_length = pnt - xc->hier.u.scope.name; xc->hier.u.attr.arg = fstReaderVarint64(xc->fh); if(xc->hier.u.attr.typ == FST_AT_MISC) { if((xc->hier.u.attr.subtype == FST_MT_SOURCESTEM)||(xc->hier.u.attr.subtype == FST_MT_SOURCEISTEM)) { int sidx_skiplen_dummy = 0; xc->hier.u.attr.arg_from_name = fstGetVarint64((unsigned char *)xc->str_scope_nam, &sidx_skiplen_dummy); } } break; case FST_ST_GEN_ATTREND: xc->hier.htyp = FST_HT_ATTREND; break; case FST_VT_VCD_EVENT: case FST_VT_VCD_INTEGER: case FST_VT_VCD_PARAMETER: case FST_VT_VCD_REAL: case FST_VT_VCD_REAL_PARAMETER: case FST_VT_VCD_REG: case FST_VT_VCD_SUPPLY0: case FST_VT_VCD_SUPPLY1: case FST_VT_VCD_TIME: case FST_VT_VCD_TRI: case FST_VT_VCD_TRIAND: case FST_VT_VCD_TRIOR: case FST_VT_VCD_TRIREG: case FST_VT_VCD_TRI0: case FST_VT_VCD_TRI1: case FST_VT_VCD_WAND: case FST_VT_VCD_WIRE: case FST_VT_VCD_WOR: case FST_VT_VCD_PORT: case FST_VT_VCD_SPARRAY: case FST_VT_VCD_REALTIME: case FST_VT_GEN_STRING: case FST_VT_SV_BIT: case FST_VT_SV_LOGIC: case FST_VT_SV_INT: case FST_VT_SV_SHORTINT: case FST_VT_SV_LONGINT: case FST_VT_SV_BYTE: case FST_VT_SV_ENUM: case FST_VT_SV_SHORTREAL: xc->hier.htyp = FST_HT_VAR; xc->hier.u.var.svt_workspace = FST_SVT_NONE; xc->hier.u.var.sdt_workspace = FST_SDT_NONE; xc->hier.u.var.sxt_workspace = 0; xc->hier.u.var.typ = tag; xc->hier.u.var.direction = fgetc(xc->fh); xc->hier.u.var.name = pnt = xc->str_scope_nam; while((ch = fgetc(xc->fh))) { *(pnt++) = ch; }; /* varname */ *pnt = 0; xc->hier.u.var.name_length = pnt - xc->hier.u.var.name; xc->hier.u.var.length = fstReaderVarint32(xc->fh); if(tag == FST_VT_VCD_PORT) { xc->hier.u.var.length -= 2; /* removal of delimiting spaces */ xc->hier.u.var.length /= 3; /* port -> signal size adjust */ } alias = fstReaderVarint32(xc->fh); if(!alias) { xc->current_handle++; xc->hier.u.var.handle = xc->current_handle; xc->hier.u.var.is_alias = 0; } else { xc->hier.u.var.handle = alias; xc->hier.u.var.is_alias = 1; } break; default: isfeof = 1; break; } } return(!isfeof ? &xc->hier : NULL); } int fstReaderProcessHier(void *ctx, FILE *fv) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; char *str; char *pnt; int ch, scopetype; int vartype; uint32_t len, alias; /* uint32_t maxvalpos=0; */ unsigned int num_signal_dyn = 65536; int attrtype, subtype; uint64_t attrarg; fstHandle maxhandle_scanbuild; if(!xc) return(0); xc->longest_signal_value_len = 32; /* arbitrarily set at 32...this is much longer than an expanded double */ if(!xc->fh) { if(!fstReaderRecreateHierFile(xc)) { return(0); } } str = (char *)malloc(FST_ID_NAM_ATTR_SIZ+1); if(fv) { char time_dimension[2] = {0, 0}; int time_scale = 1; fprintf(fv, "$date\n\t%s\n$end\n", xc->date); fprintf(fv, "$version\n\t%s\n$end\n", xc->version); if(xc->timezero) fprintf(fv, "$timezero\n\t%" PRId64 "\n$end\n", xc->timezero); switch(xc->timescale) { case 2: time_scale = 100; time_dimension[0] = 0; break; case 1: time_scale = 10; /* fallthrough */ case 0: time_dimension[0] = 0; break; case -1: time_scale = 100; time_dimension[0] = 'm'; break; case -2: time_scale = 10; /* fallthrough */ case -3: time_dimension[0] = 'm'; break; case -4: time_scale = 100; time_dimension[0] = 'u'; break; case -5: time_scale = 10; /* fallthrough */ case -6: time_dimension[0] = 'u'; break; case -10: time_scale = 100; time_dimension[0] = 'p'; break; case -11: time_scale = 10; /* fallthrough */ case -12: time_dimension[0] = 'p'; break; case -13: time_scale = 100; time_dimension[0] = 'f'; break; case -14: time_scale = 10; /* fallthrough */ case -15: time_dimension[0] = 'f'; break; case -16: time_scale = 100; time_dimension[0] = 'a'; break; case -17: time_scale = 10; /* fallthrough */ case -18: time_dimension[0] = 'a'; break; case -19: time_scale = 100; time_dimension[0] = 'z'; break; case -20: time_scale = 10; /* fallthrough */ case -21: time_dimension[0] = 'z'; break; case -7: time_scale = 100; time_dimension[0] = 'n'; break; case -8: time_scale = 10; /* fallthrough */ case -9: default: time_dimension[0] = 'n'; break; } if(fv) fprintf(fv, "$timescale\n\t%d%ss\n$end\n", time_scale, time_dimension); } xc->maxhandle = 0; xc->num_alias = 0; free(xc->signal_lens); xc->signal_lens = (uint32_t *)malloc(num_signal_dyn*sizeof(uint32_t)); free(xc->signal_typs); xc->signal_typs = (unsigned char *)malloc(num_signal_dyn*sizeof(unsigned char)); fstReaderFseeko(xc, xc->fh, 0, SEEK_SET); while(!feof(xc->fh)) { int tag = fgetc(xc->fh); switch(tag) { case FST_ST_VCD_SCOPE: scopetype = fgetc(xc->fh); if((scopetype < FST_ST_MIN) || (scopetype > FST_ST_MAX)) scopetype = FST_ST_VCD_MODULE; pnt = str; while((ch = fgetc(xc->fh))) { *(pnt++) = ch; }; /* scopename */ *pnt = 0; while(fgetc(xc->fh)) { }; /* scopecomp */ if(fv) fprintf(fv, "$scope %s %s $end\n", modtypes[scopetype], str); break; case FST_ST_VCD_UPSCOPE: if(fv) fprintf(fv, "$upscope $end\n"); break; case FST_ST_GEN_ATTRBEGIN: attrtype = fgetc(xc->fh); subtype = fgetc(xc->fh); pnt = str; while((ch = fgetc(xc->fh))) { *(pnt++) = ch; }; /* attrname */ *pnt = 0; if(!str[0]) { strcpy(str, "\"\""); } attrarg = fstReaderVarint64(xc->fh); if(fv && xc->use_vcd_extensions) { switch(attrtype) { case FST_AT_ARRAY: if((subtype < FST_AR_NONE) || (subtype > FST_AR_MAX)) subtype = FST_AR_NONE; fprintf(fv, "$attrbegin %s %s %s %" PRId64 " $end\n", attrtypes[attrtype], arraytypes[subtype], str, attrarg); break; case FST_AT_ENUM: if((subtype < FST_EV_SV_INTEGER) || (subtype > FST_EV_MAX)) subtype = FST_EV_SV_INTEGER; fprintf(fv, "$attrbegin %s %s %s %" PRId64 " $end\n", attrtypes[attrtype], enumvaluetypes[subtype], str, attrarg); break; case FST_AT_PACK: if((subtype < FST_PT_NONE) || (subtype > FST_PT_MAX)) subtype = FST_PT_NONE; fprintf(fv, "$attrbegin %s %s %s %" PRId64 " $end\n", attrtypes[attrtype], packtypes[subtype], str, attrarg); break; case FST_AT_MISC: default: attrtype = FST_AT_MISC; if(subtype == FST_MT_COMMENT) { fprintf(fv, "$comment\n\t%s\n$end\n", str); } else { if((subtype == FST_MT_SOURCESTEM)||(subtype == FST_MT_SOURCEISTEM)) { int sidx_skiplen_dummy = 0; uint64_t sidx = fstGetVarint64((unsigned char *)str, &sidx_skiplen_dummy); fprintf(fv, "$attrbegin %s %02x %" PRId64 " %" PRId64 " $end\n", attrtypes[attrtype], subtype, sidx, attrarg); } else { fprintf(fv, "$attrbegin %s %02x %s %" PRId64 " $end\n", attrtypes[attrtype], subtype, str, attrarg); } } break; } } break; case FST_ST_GEN_ATTREND: if(fv && xc->use_vcd_extensions) fprintf(fv, "$attrend $end\n"); break; case FST_VT_VCD_EVENT: case FST_VT_VCD_INTEGER: case FST_VT_VCD_PARAMETER: case FST_VT_VCD_REAL: case FST_VT_VCD_REAL_PARAMETER: case FST_VT_VCD_REG: case FST_VT_VCD_SUPPLY0: case FST_VT_VCD_SUPPLY1: case FST_VT_VCD_TIME: case FST_VT_VCD_TRI: case FST_VT_VCD_TRIAND: case FST_VT_VCD_TRIOR: case FST_VT_VCD_TRIREG: case FST_VT_VCD_TRI0: case FST_VT_VCD_TRI1: case FST_VT_VCD_WAND: case FST_VT_VCD_WIRE: case FST_VT_VCD_WOR: case FST_VT_VCD_PORT: case FST_VT_VCD_SPARRAY: case FST_VT_VCD_REALTIME: case FST_VT_GEN_STRING: case FST_VT_SV_BIT: case FST_VT_SV_LOGIC: case FST_VT_SV_INT: case FST_VT_SV_SHORTINT: case FST_VT_SV_LONGINT: case FST_VT_SV_BYTE: case FST_VT_SV_ENUM: case FST_VT_SV_SHORTREAL: vartype = tag; /* vardir = */ fgetc(xc->fh); /* unused in VCD reader, but need to advance read pointer */ pnt = str; while((ch = fgetc(xc->fh))) { *(pnt++) = ch; }; /* varname */ *pnt = 0; len = fstReaderVarint32(xc->fh); alias = fstReaderVarint32(xc->fh); if(!alias) { if(xc->maxhandle == num_signal_dyn) { num_signal_dyn *= 2; xc->signal_lens = (uint32_t *)realloc(xc->signal_lens, num_signal_dyn*sizeof(uint32_t)); xc->signal_typs = (unsigned char *)realloc(xc->signal_typs, num_signal_dyn*sizeof(unsigned char)); } xc->signal_lens[xc->maxhandle] = len; xc->signal_typs[xc->maxhandle] = vartype; /* maxvalpos+=len; */ if(len > xc->longest_signal_value_len) { xc->longest_signal_value_len = len; } if((vartype == FST_VT_VCD_REAL) || (vartype == FST_VT_VCD_REAL_PARAMETER) || (vartype == FST_VT_VCD_REALTIME) || (vartype == FST_VT_SV_SHORTREAL)) { len = (vartype != FST_VT_SV_SHORTREAL) ? 64 : 32; xc->signal_typs[xc->maxhandle] = FST_VT_VCD_REAL; } if(fv) { char vcdid_buf[16]; uint32_t modlen = (vartype != FST_VT_VCD_PORT) ? len : ((len - 2) / 3); fstVcdID(vcdid_buf, xc->maxhandle+1); fprintf(fv, "$var %s %" PRIu32 " %s %s $end\n", vartypes[vartype], modlen, vcdid_buf, str); } xc->maxhandle++; } else { if((vartype == FST_VT_VCD_REAL) || (vartype == FST_VT_VCD_REAL_PARAMETER) || (vartype == FST_VT_VCD_REALTIME) || (vartype == FST_VT_SV_SHORTREAL)) { len = (vartype != FST_VT_SV_SHORTREAL) ? 64 : 32; xc->signal_typs[xc->maxhandle] = FST_VT_VCD_REAL; } if(fv) { char vcdid_buf[16]; uint32_t modlen = (vartype != FST_VT_VCD_PORT) ? len : ((len - 2) / 3); fstVcdID(vcdid_buf, alias); fprintf(fv, "$var %s %" PRIu32 " %s %s $end\n", vartypes[vartype], modlen, vcdid_buf, str); } xc->num_alias++; } break; default: break; } } if(fv) fprintf(fv, "$enddefinitions $end\n"); maxhandle_scanbuild = xc->maxhandle ? xc->maxhandle : 1; /*scan-build warning suppression, in reality we have at least one signal */ xc->signal_lens = (uint32_t *)realloc(xc->signal_lens, maxhandle_scanbuild*sizeof(uint32_t)); xc->signal_typs = (unsigned char *)realloc(xc->signal_typs, maxhandle_scanbuild*sizeof(unsigned char)); free(xc->process_mask); xc->process_mask = (unsigned char *)calloc(1, (maxhandle_scanbuild+7)/8); free(xc->temp_signal_value_buf); xc->temp_signal_value_buf = (unsigned char *)malloc(xc->longest_signal_value_len + 1); xc->var_count = xc->maxhandle + xc->num_alias; free(str); return(1); } /* * reader file open/close functions */ int fstReaderInit(struct fstReaderContext *xc) { off_t blkpos = 0; off_t endfile; uint64_t seclen; int sectype; uint64_t vc_section_count_actual = 0; int hdr_incomplete = 0; int hdr_seen = 0; int gzread_pass_status = 1; sectype = fgetc(xc->f); if(sectype == FST_BL_ZWRAPPER) { FILE *fcomp; off_t offpnt, uclen; char gz_membuf[FST_GZIO_LEN]; gzFile zhandle; int zfd; int flen = strlen(xc->filename); char *hf; seclen = fstReaderUint64(xc->f); uclen = fstReaderUint64(xc->f); if(!seclen) return(0); /* not finished compressing, this is a failed read */ hf = (char *)calloc(1, flen + 16 + 32 + 1); sprintf(hf, "%s.upk_%d_%p", xc->filename, getpid(), (void *)xc); fcomp = fopen(hf, "w+b"); if(!fcomp) { fcomp = tmpfile_open(&xc->f_nam); free(hf); hf = NULL; if(!fcomp) { tmpfile_close(&fcomp, &xc->f_nam); return(0); } } #if defined(FST_MACOSX) setvbuf(fcomp, (char *)NULL, _IONBF, 0); /* keeps gzip from acting weird in tandem with fopen */ #endif #ifdef __MINGW32__ setvbuf(fcomp, (char *)NULL, _IONBF, 0); /* keeps gzip from acting weird in tandem with fopen */ xc->filename_unpacked = hf; #else if(hf) { unlink(hf); free(hf); } #endif fstReaderFseeko(xc, xc->f, 1+8+8, SEEK_SET); #ifndef __MINGW32__ fflush(xc->f); #endif zfd = dup(fileno(xc->f)); zhandle = gzdopen(zfd, "rb"); if(zhandle) { for(offpnt = 0; offpnt < uclen; offpnt += FST_GZIO_LEN) { size_t this_len = ((uclen - offpnt) > FST_GZIO_LEN) ? FST_GZIO_LEN : (uclen - offpnt); size_t gzreadlen = gzread(zhandle, gz_membuf, this_len); size_t fwlen; if(gzreadlen != this_len) { gzread_pass_status = 0; break; } fwlen = fstFwrite(gz_membuf, this_len, 1, fcomp); if(fwlen != 1) { gzread_pass_status = 0; break; } } gzclose(zhandle); } else { close(zfd); } fflush(fcomp); fclose(xc->f); xc->f = fcomp; } if(gzread_pass_status) { fstReaderFseeko(xc, xc->f, 0, SEEK_END); endfile = ftello(xc->f); while(blkpos < endfile) { fstReaderFseeko(xc, xc->f, blkpos, SEEK_SET); sectype = fgetc(xc->f); seclen = fstReaderUint64(xc->f); if(sectype == EOF) { break; } if((hdr_incomplete) && (!seclen)) { break; } if(!hdr_seen && (sectype != FST_BL_HDR)) { break; } blkpos++; if(sectype == FST_BL_HDR) { if(!hdr_seen) { int ch; double dcheck; xc->start_time = fstReaderUint64(xc->f); xc->end_time = fstReaderUint64(xc->f); hdr_incomplete = (xc->start_time == 0) && (xc->end_time == 0); fstFread(&dcheck, 8, 1, xc->f); xc->double_endian_match = (dcheck == FST_DOUBLE_ENDTEST); if(!xc->double_endian_match) { union { unsigned char rvs_buf[8]; double d; } vu; unsigned char *dcheck_alias = (unsigned char *)&dcheck; int rvs_idx; for(rvs_idx=0;rvs_idx<8;rvs_idx++) { vu.rvs_buf[rvs_idx] = dcheck_alias[7-rvs_idx]; } if(vu.d != FST_DOUBLE_ENDTEST) { break; /* either corrupt file or wrong architecture (offset +33 also functions as matchword) */ } } hdr_seen = 1; xc->mem_used_by_writer = fstReaderUint64(xc->f); xc->scope_count = fstReaderUint64(xc->f); xc->var_count = fstReaderUint64(xc->f); xc->maxhandle = fstReaderUint64(xc->f); xc->num_alias = xc->var_count - xc->maxhandle; xc->vc_section_count = fstReaderUint64(xc->f); ch = fgetc(xc->f); xc->timescale = (signed char)ch; fstFread(xc->version, FST_HDR_SIM_VERSION_SIZE, 1, xc->f); xc->version[FST_HDR_SIM_VERSION_SIZE] = 0; fstFread(xc->date, FST_HDR_DATE_SIZE, 1, xc->f); xc->date[FST_HDR_DATE_SIZE] = 0; ch = fgetc(xc->f); xc->filetype = (unsigned char)ch; xc->timezero = fstReaderUint64(xc->f); } } else if((sectype == FST_BL_VCDATA) || (sectype == FST_BL_VCDATA_DYN_ALIAS) || (sectype == FST_BL_VCDATA_DYN_ALIAS2)) { if(hdr_incomplete) { uint64_t bt = fstReaderUint64(xc->f); xc->end_time = fstReaderUint64(xc->f); if(!vc_section_count_actual) { xc->start_time = bt; } } vc_section_count_actual++; } else if(sectype == FST_BL_GEOM) { if(!hdr_incomplete) { uint64_t clen = seclen - 24; uint64_t uclen = fstReaderUint64(xc->f); unsigned char *ucdata = (unsigned char *)malloc(uclen); unsigned char *pnt = ucdata; unsigned int i; xc->contains_geom_section = 1; xc->maxhandle = fstReaderUint64(xc->f); xc->longest_signal_value_len = 32; /* arbitrarily set at 32...this is much longer than an expanded double */ free(xc->process_mask); xc->process_mask = (unsigned char *)calloc(1, (xc->maxhandle+7)/8); if(clen != uclen) { unsigned char *cdata = (unsigned char *)malloc(clen); unsigned long destlen = uclen; unsigned long sourcelen = clen; int rc; fstFread(cdata, clen, 1, xc->f); rc = uncompress(ucdata, &destlen, cdata, sourcelen); if(rc != Z_OK) { fprintf(stderr, FST_APIMESS "fstReaderInit(), geom uncompress rc = %d, exiting.\n", rc); exit(255); } free(cdata); } else { fstFread(ucdata, uclen, 1, xc->f); } free(xc->signal_lens); xc->signal_lens = (uint32_t *)malloc(sizeof(uint32_t) * xc->maxhandle); free(xc->signal_typs); xc->signal_typs = (unsigned char *)malloc(sizeof(unsigned char) * xc->maxhandle); for(i=0;imaxhandle;i++) { int skiplen; uint64_t val = fstGetVarint32(pnt, &skiplen); pnt += skiplen; if(val) { xc->signal_lens[i] = (val != 0xFFFFFFFF) ? val : 0; xc->signal_typs[i] = FST_VT_VCD_WIRE; if(xc->signal_lens[i] > xc->longest_signal_value_len) { xc->longest_signal_value_len = xc->signal_lens[i]; } } else { xc->signal_lens[i] = 8; /* backpatch in real */ xc->signal_typs[i] = FST_VT_VCD_REAL; /* xc->longest_signal_value_len handled above by overly large init size */ } } free(xc->temp_signal_value_buf); xc->temp_signal_value_buf = (unsigned char *)malloc(xc->longest_signal_value_len + 1); free(ucdata); } } else if(sectype == FST_BL_HIER) { xc->contains_hier_section = 1; xc->hier_pos = ftello(xc->f); } else if(sectype == FST_BL_HIER_LZ4DUO) { xc->contains_hier_section_lz4 = 1; xc->contains_hier_section_lz4duo = 1; xc->hier_pos = ftello(xc->f); } else if(sectype == FST_BL_HIER_LZ4) { xc->contains_hier_section_lz4 = 1; xc->hier_pos = ftello(xc->f); } else if(sectype == FST_BL_BLACKOUT) { uint32_t i; uint64_t cur_bl = 0; uint64_t delta; xc->num_blackouts = fstReaderVarint32(xc->f); free(xc->blackout_times); xc->blackout_times = (uint64_t *)calloc(xc->num_blackouts, sizeof(uint64_t)); free(xc->blackout_activity); xc->blackout_activity = (unsigned char *)calloc(xc->num_blackouts, sizeof(unsigned char)); for(i=0;inum_blackouts;i++) { xc->blackout_activity[i] = fgetc(xc->f) != 0; delta = fstReaderVarint64(xc->f); cur_bl += delta; xc->blackout_times[i] = cur_bl; } } blkpos += seclen; if(!hdr_seen) break; } if(hdr_seen) { if(xc->vc_section_count != vc_section_count_actual) { xc->vc_section_count = vc_section_count_actual; } if(!xc->contains_geom_section) { fstReaderProcessHier(xc, NULL); /* recreate signal_lens/signal_typs info */ } } } return(hdr_seen); } void *fstReaderOpenForUtilitiesOnly(void) { struct fstReaderContext *xc = (struct fstReaderContext *)calloc(1, sizeof(struct fstReaderContext)); return(xc); } void *fstReaderOpen(const char *nam) { struct fstReaderContext *xc = (struct fstReaderContext *)calloc(1, sizeof(struct fstReaderContext)); if((!nam)||(!(xc->f=fopen(nam, "rb")))) { free(xc); xc=NULL; } else { int flen = strlen(nam); char *hf = (char *)calloc(1, flen + 6); int rc; #if defined(__MINGW32__) || defined(FST_MACOSX) setvbuf(xc->f, (char *)NULL, _IONBF, 0); /* keeps gzip from acting weird in tandem with fopen */ #endif memcpy(hf, nam, flen); strcpy(hf + flen, ".hier"); xc->fh = fopen(hf, "rb"); free(hf); xc->filename = strdup(nam); rc = fstReaderInit(xc); if((rc) && (xc->vc_section_count) && (xc->maxhandle) && ((xc->fh)||(xc->contains_hier_section||(xc->contains_hier_section_lz4)))) { /* more init */ xc->do_rewind = 1; } else { fstReaderClose(xc); xc = NULL; } } return(xc); } static void fstReaderDeallocateRvatData(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { free(xc->rvat_chain_mem); xc->rvat_chain_mem = NULL; free(xc->rvat_frame_data); xc->rvat_frame_data = NULL; free(xc->rvat_time_table); xc->rvat_time_table = NULL; free(xc->rvat_chain_table); xc->rvat_chain_table = NULL; free(xc->rvat_chain_table_lengths); xc->rvat_chain_table_lengths = NULL; xc->rvat_data_valid = 0; } } void fstReaderClose(void *ctx) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; if(xc) { fstReaderDeallocateScopeData(xc); fstReaderDeallocateRvatData(xc); free(xc->rvat_sig_offs); xc->rvat_sig_offs = NULL; free(xc->process_mask); xc->process_mask = NULL; free(xc->blackout_times); xc->blackout_times = NULL; free(xc->blackout_activity); xc->blackout_activity = NULL; free(xc->temp_signal_value_buf); xc->temp_signal_value_buf = NULL; free(xc->signal_typs); xc->signal_typs = NULL; free(xc->signal_lens); xc->signal_lens = NULL; free(xc->filename); xc->filename = NULL; if(xc->fh) { tmpfile_close(&xc->fh, &xc->fh_nam); } if(xc->f) { tmpfile_close(&xc->f, &xc->f_nam); if(xc->filename_unpacked) { unlink(xc->filename_unpacked); free(xc->filename_unpacked); } } free(xc); } } /* * read processing */ /* normal read which re-interleaves the value change data */ int fstReaderIterBlocks(void *ctx, void (*value_change_callback)(void *user_callback_data_pointer, uint64_t time, fstHandle facidx, const unsigned char *value), void *user_callback_data_pointer, FILE *fv) { return(fstReaderIterBlocks2(ctx, value_change_callback, NULL, user_callback_data_pointer, fv)); } int fstReaderIterBlocks2(void *ctx, void (*value_change_callback)(void *user_callback_data_pointer, uint64_t time, fstHandle facidx, const unsigned char *value), void (*value_change_callback_varlen)(void *user_callback_data_pointer, uint64_t time, fstHandle facidx, const unsigned char *value, uint32_t len), void *user_callback_data_pointer, FILE *fv) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; uint64_t previous_time = UINT64_MAX; uint64_t *time_table = NULL; uint64_t tsec_nitems; unsigned int secnum = 0; int blocks_skipped = 0; off_t blkpos = 0; uint64_t seclen, beg_tim; #ifdef FST_DEBUG uint64_t end_tim; #endif uint64_t frame_uclen, frame_clen, frame_maxhandle, vc_maxhandle; off_t vc_start; off_t indx_pntr, indx_pos; off_t *chain_table = NULL; uint32_t *chain_table_lengths = NULL; unsigned char *chain_cmem; unsigned char *pnt; long chain_clen; fstHandle idx, pidx=0, i; uint64_t pval; uint64_t vc_maxhandle_largest = 0; uint64_t tsec_uclen = 0, tsec_clen = 0; int sectype; uint64_t mem_required_for_traversal; unsigned char *mem_for_traversal = NULL; uint32_t traversal_mem_offs; uint32_t *scatterptr, *headptr, *length_remaining; uint32_t cur_blackout = 0; int packtype; unsigned char *mc_mem = NULL; uint32_t mc_mem_len; /* corresponds to largest value encountered in chain_table_lengths[i] */ int dumpvars_state = 0; if(!xc) return(0); scatterptr = (uint32_t *)calloc(xc->maxhandle, sizeof(uint32_t)); headptr = (uint32_t *)calloc(xc->maxhandle, sizeof(uint32_t)); length_remaining = (uint32_t *)calloc(xc->maxhandle, sizeof(uint32_t)); if(fv) { #ifndef FST_WRITEX_DISABLE fflush(fv); setvbuf(fv, (char *) NULL, _IONBF, 0); /* even buffered IO is slow so disable it and use our own routines that don't need seeking */ xc->writex_fd = fileno(fv); #endif } for(;;) { uint32_t *tc_head = NULL; traversal_mem_offs = 0; fstReaderFseeko(xc, xc->f, blkpos, SEEK_SET); sectype = fgetc(xc->f); seclen = fstReaderUint64(xc->f); if((sectype == EOF) || (sectype == FST_BL_SKIP)) { #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "<< EOF >>\n"); #endif break; } blkpos++; if((sectype != FST_BL_VCDATA) && (sectype != FST_BL_VCDATA_DYN_ALIAS) && (sectype != FST_BL_VCDATA_DYN_ALIAS2)) { blkpos += seclen; continue; } if(!seclen) break; beg_tim = fstReaderUint64(xc->f); #ifdef FST_DEBUG end_tim = #endif fstReaderUint64(xc->f); if(xc->limit_range_valid) { if(beg_tim < xc->limit_range_start) { blocks_skipped++; blkpos += seclen; continue; } if(beg_tim > xc->limit_range_end) /* likely the compare in for(i=0;if); mem_for_traversal = (unsigned char *)malloc(mem_required_for_traversal + 66); /* add in potential fastlz overhead */ #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "sec: %u seclen: %d begtim: %d endtim: %d\n", secnum, (int)seclen, (int)beg_tim, (int)end_tim); fprintf(stderr, FST_APIMESS "mem_required_for_traversal: %d\n", (int)mem_required_for_traversal); #endif /* process time block */ { unsigned char *ucdata; unsigned char *cdata; unsigned long destlen /* = tsec_uclen */; /* scan-build */ unsigned long sourcelen /*= tsec_clen */; /* scan-build */ int rc; unsigned char *tpnt; uint64_t tpval; unsigned int ti; if(fstReaderFseeko(xc, xc->f, blkpos + seclen - 24, SEEK_SET) != 0) break; tsec_uclen = fstReaderUint64(xc->f); tsec_clen = fstReaderUint64(xc->f); tsec_nitems = fstReaderUint64(xc->f); #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "time section unc: %d, com: %d (%d items)\n", (int)tsec_uclen, (int)tsec_clen, (int)tsec_nitems); #endif if(tsec_clen > seclen) break; /* corrupted tsec_clen: by definition it can't be larger than size of section */ ucdata = (unsigned char *)malloc(tsec_uclen); if(!ucdata) break; /* malloc fail as tsec_uclen out of range from corrupted file */ destlen = tsec_uclen; sourcelen = tsec_clen; fstReaderFseeko(xc, xc->f, -24 - ((off_t)tsec_clen), SEEK_CUR); if(tsec_uclen != tsec_clen) { cdata = (unsigned char *)malloc(tsec_clen); fstFread(cdata, tsec_clen, 1, xc->f); rc = uncompress(ucdata, &destlen, cdata, sourcelen); if(rc != Z_OK) { fprintf(stderr, FST_APIMESS "fstReaderIterBlocks2(), tsec uncompress rc = %d, exiting.\n", rc); exit(255); } free(cdata); } else { fstFread(ucdata, tsec_uclen, 1, xc->f); } free(time_table); time_table = (uint64_t *)calloc(tsec_nitems, sizeof(uint64_t)); tpnt = ucdata; tpval = 0; for(ti=0;tif, blkpos+32, SEEK_SET); frame_uclen = fstReaderVarint64(xc->f); frame_clen = fstReaderVarint64(xc->f); frame_maxhandle = fstReaderVarint64(xc->f); if(secnum == 0) { if((beg_tim != time_table[0]) || (blocks_skipped)) { unsigned char *mu = (unsigned char *)malloc(frame_uclen); uint32_t sig_offs = 0; if(fv) { char wx_buf[32]; int wx_len; if(beg_tim) { if(dumpvars_state == 1) { wx_len = sprintf(wx_buf, "$end\n"); fstWritex(xc, wx_buf, wx_len); dumpvars_state = 2; } wx_len = sprintf(wx_buf, "#%" PRIu64 "\n", beg_tim); fstWritex(xc, wx_buf, wx_len); if(!dumpvars_state) { wx_len = sprintf(wx_buf, "$dumpvars\n"); fstWritex(xc, wx_buf, wx_len); dumpvars_state = 1; } } if((xc->num_blackouts)&&(cur_blackout != xc->num_blackouts)) { if(beg_tim == xc->blackout_times[cur_blackout]) { wx_len = sprintf(wx_buf, "$dump%s $end\n", (xc->blackout_activity[cur_blackout++]) ? "on" : "off"); fstWritex(xc, wx_buf, wx_len); } } } if(frame_uclen == frame_clen) { fstFread(mu, frame_uclen, 1, xc->f); } else { unsigned char *mc = (unsigned char *)malloc(frame_clen); int rc; unsigned long destlen = frame_uclen; unsigned long sourcelen = frame_clen; fstFread(mc, sourcelen, 1, xc->f); rc = uncompress(mu, &destlen, mc, sourcelen); if(rc != Z_OK) { fprintf(stderr, FST_APIMESS "fstReaderIterBlocks2(), frame uncompress rc: %d, exiting.\n", rc); exit(255); } free(mc); } for(idx=0;idxprocess_mask[process_idx]&(1<signal_lens[idx] <= 1) { if(xc->signal_lens[idx] == 1) { unsigned char val = mu[sig_offs]; if(value_change_callback) { xc->temp_signal_value_buf[0] = val; xc->temp_signal_value_buf[1] = 0; value_change_callback(user_callback_data_pointer, beg_tim, idx+1, xc->temp_signal_value_buf); } else { if(fv) { char vcd_id[16]; int vcdid_len = fstVcdIDForFwrite(vcd_id+1, idx+1); vcd_id[0] = val; /* collapse 3 writes into one I/O call */ vcd_id[vcdid_len + 1] = '\n'; fstWritex(xc, vcd_id, vcdid_len + 2); } } } else { /* variable-length ("0" length) records have no initial state */ } } else { if(xc->signal_typs[idx] != FST_VT_VCD_REAL) { if(value_change_callback) { memcpy(xc->temp_signal_value_buf, mu+sig_offs, xc->signal_lens[idx]); xc->temp_signal_value_buf[xc->signal_lens[idx]] = 0; value_change_callback(user_callback_data_pointer, beg_tim, idx+1, xc->temp_signal_value_buf); } else { if(fv) { char vcd_id[16]; int vcdid_len = fstVcdIDForFwrite(vcd_id+1, idx+1); vcd_id[0] = (xc->signal_typs[idx] != FST_VT_VCD_PORT) ? 'b' : 'p'; fstWritex(xc, vcd_id, 1); fstWritex(xc,mu+sig_offs, xc->signal_lens[idx]); vcd_id[0] = ' '; /* collapse 3 writes into one I/O call */ vcd_id[vcdid_len + 1] = '\n'; fstWritex(xc, vcd_id, vcdid_len + 2); } } } else { double d; unsigned char *clone_d; unsigned char *srcdata = mu+sig_offs; if(value_change_callback) { if(xc->native_doubles_for_cb) { if(xc->double_endian_match) { clone_d = srcdata; } else { int j; clone_d = (unsigned char *)&d; for(j=0;j<8;j++) { clone_d[j] = srcdata[7-j]; } } value_change_callback(user_callback_data_pointer, beg_tim, idx+1, clone_d); } else { clone_d = (unsigned char *)&d; if(xc->double_endian_match) { memcpy(clone_d, srcdata, 8); } else { int j; for(j=0;j<8;j++) { clone_d[j] = srcdata[7-j]; } } sprintf((char *)xc->temp_signal_value_buf, "%.16g", d); value_change_callback(user_callback_data_pointer, beg_tim, idx+1, xc->temp_signal_value_buf); } } else { if(fv) { char vcdid_buf[16]; char wx_buf[64]; int wx_len; clone_d = (unsigned char *)&d; if(xc->double_endian_match) { memcpy(clone_d, srcdata, 8); } else { int j; for(j=0;j<8;j++) { clone_d[j] = srcdata[7-j]; } } fstVcdID(vcdid_buf, idx+1); wx_len = sprintf(wx_buf, "r%.16g %s\n", d, vcdid_buf); fstWritex(xc, wx_buf, wx_len); } } } } } sig_offs += xc->signal_lens[idx]; } free(mu); fstReaderFseeko(xc, xc->f, -((off_t)frame_clen), SEEK_CUR); } } fstReaderFseeko(xc, xc->f, (off_t)frame_clen, SEEK_CUR); /* skip past compressed data */ vc_maxhandle = fstReaderVarint64(xc->f); vc_start = ftello(xc->f); /* points to '!' character */ packtype = fgetc(xc->f); #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "frame_uclen: %d, frame_clen: %d, frame_maxhandle: %d\n", (int)frame_uclen, (int)frame_clen, (int)frame_maxhandle); fprintf(stderr, FST_APIMESS "vc_maxhandle: %d, packtype: %c\n", (int)vc_maxhandle, packtype); #endif indx_pntr = blkpos + seclen - 24 -tsec_clen -8; fstReaderFseeko(xc, xc->f, indx_pntr, SEEK_SET); chain_clen = fstReaderUint64(xc->f); indx_pos = indx_pntr - chain_clen; #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "indx_pos: %d (%d bytes)\n", (int)indx_pos, (int)chain_clen); #endif chain_cmem = (unsigned char *)malloc(chain_clen); if(!chain_cmem) goto block_err; fstReaderFseeko(xc, xc->f, indx_pos, SEEK_SET); fstFread(chain_cmem, chain_clen, 1, xc->f); if(vc_maxhandle > vc_maxhandle_largest) { free(chain_table); free(chain_table_lengths); vc_maxhandle_largest = vc_maxhandle; chain_table = (off_t *)calloc((vc_maxhandle+1), sizeof(off_t)); chain_table_lengths = (uint32_t *)calloc((vc_maxhandle+1), sizeof(uint32_t)); } if(!chain_table || !chain_table_lengths) goto block_err; pnt = chain_cmem; idx = 0; pval = 0; if(sectype == FST_BL_VCDATA_DYN_ALIAS2) { uint32_t prev_alias = 0; do { int skiplen; if(*pnt & 0x01) { int64_t shval = fstGetSVarint64(pnt, &skiplen) >> 1; if(shval > 0) { pval = chain_table[idx] = pval + shval; if(idx) { chain_table_lengths[pidx] = pval - chain_table[pidx]; } pidx = idx++; } else if(shval < 0) { chain_table[idx] = 0; /* need to explicitly zero as calloc above might not run */ chain_table_lengths[idx] = prev_alias = shval; /* because during this loop iter would give stale data! */ idx++; } else { chain_table[idx] = 0; /* need to explicitly zero as calloc above might not run */ chain_table_lengths[idx] = prev_alias; /* because during this loop iter would give stale data! */ idx++; } } else { uint64_t val = fstGetVarint32(pnt, &skiplen); fstHandle loopcnt = val >> 1; for(i=0;i> 1); if(idx) { chain_table_lengths[pidx] = pval - chain_table[pidx]; } pidx = idx++; } else { fstHandle loopcnt = val >> 1; for(i=0;i xc->maxhandle) idx = xc->maxhandle; for(i=0;iprocess_mask[process_idx]&(1<f, vc_start + chain_table[i], SEEK_SET); val = fstReaderVarint32WithSkip(xc->f, &skiplen); if(val) { unsigned char *mu = mem_for_traversal + traversal_mem_offs; /* uncomp: dst */ unsigned char *mc; /* comp: src */ unsigned long destlen = val; unsigned long sourcelen = chain_table_lengths[i]; if(mc_mem_len < chain_table_lengths[i]) { free(mc_mem); mc_mem = (unsigned char *)malloc(mc_mem_len = chain_table_lengths[i]); } mc = mc_mem; fstFread(mc, chain_table_lengths[i], 1, xc->f); switch(packtype) { case '4': rc = (destlen == (unsigned long)LZ4_decompress_safe_partial((char *)mc, (char *)mu, sourcelen, destlen, destlen)) ? Z_OK : Z_DATA_ERROR; break; case 'F': fastlz_decompress(mc, sourcelen, mu, destlen); /* rc appears unreliable */ break; default: rc = uncompress(mu, &destlen, mc, sourcelen); break; } /* data to process is for(j=0;jf); /* data to process is for(j=0;jsignal_lens[i] == 1) { uint32_t vli = fstGetVarint32NoSkip(mem_for_traversal + headptr[i]); uint32_t shcnt = 2 << (vli & 1); tdelta = vli >> shcnt; } else { uint32_t vli = fstGetVarint32NoSkip(mem_for_traversal + headptr[i]); tdelta = vli >> 1; } scatterptr[i] = tc_head[tdelta]; tc_head[tdelta] = i+1; } } } free(mc_mem); /* there is no usage below for this, no real need to clear out mc_mem or mc_mem_len */ for(i=0;ilimit_range_valid) { if(time_table[i] > xc->limit_range_end) { break; } } if(dumpvars_state == 1) { wx_len = sprintf(wx_buf, "$end\n"); fstWritex(xc, wx_buf, wx_len); dumpvars_state = 2; } wx_len = sprintf(wx_buf, "#%" PRIu64 "\n", time_table[i]); fstWritex(xc, wx_buf, wx_len); if(!dumpvars_state) { wx_len = sprintf(wx_buf, "$dumpvars\n"); fstWritex(xc, wx_buf, wx_len); dumpvars_state = 1; } if((xc->num_blackouts)&&(cur_blackout != xc->num_blackouts)) { if(time_table[i] == xc->blackout_times[cur_blackout]) { wx_len = sprintf(wx_buf, "$dump%s $end\n", (xc->blackout_activity[cur_blackout++]) ? "on" : "off"); fstWritex(xc, wx_buf, wx_len); } } previous_time = time_table[i]; } } while(tc_head[i]) { idx = tc_head[i] - 1; vli = fstGetVarint32(mem_for_traversal + headptr[idx], &skiplen); if(xc->signal_lens[idx] <= 1) { if(xc->signal_lens[idx] == 1) { unsigned char val; if(!(vli & 1)) { /* tdelta = vli >> 2; */ /* scan-build */ val = ((vli >> 1) & 1) | '0'; } else { /* tdelta = vli >> 4; */ /* scan-build */ val = FST_RCV_STR[((vli >> 1) & 7)]; } if(value_change_callback) { xc->temp_signal_value_buf[0] = val; xc->temp_signal_value_buf[1] = 0; value_change_callback(user_callback_data_pointer, time_table[i], idx+1, xc->temp_signal_value_buf); } else { if(fv) { char vcd_id[16]; int vcdid_len = fstVcdIDForFwrite(vcd_id+1, idx+1); vcd_id[0] = val; vcd_id[vcdid_len+1] = '\n'; fstWritex(xc, vcd_id, vcdid_len+2); } } headptr[idx] += skiplen; length_remaining[idx] -= skiplen; tc_head[i] = scatterptr[idx]; scatterptr[idx] = 0; if(length_remaining[idx]) { int shamt; vli = fstGetVarint32NoSkip(mem_for_traversal + headptr[idx]); shamt = 2 << (vli & 1); tdelta = vli >> shamt; scatterptr[idx] = tc_head[i+tdelta]; tc_head[i+tdelta] = idx+1; } } else { unsigned char *vdata; uint32_t len; vli = fstGetVarint32(mem_for_traversal + headptr[idx], &skiplen); len = fstGetVarint32(mem_for_traversal + headptr[idx] + skiplen, &skiplen2); /* tdelta = vli >> 1; */ /* scan-build */ skiplen += skiplen2; vdata = mem_for_traversal + headptr[idx] + skiplen; if(!(vli & 1)) { if(value_change_callback_varlen) { value_change_callback_varlen(user_callback_data_pointer, time_table[i], idx+1, vdata, len); } else { if(fv) { char vcd_id[16]; int vcdid_len; vcd_id[0] = 's'; fstWritex(xc, vcd_id, 1); vcdid_len = fstVcdIDForFwrite(vcd_id+1, idx+1); { unsigned char *vesc = (unsigned char *)malloc(len*4 + 1); int vlen = fstUtilityBinToEsc(vesc, vdata, len); fstWritex(xc, vesc, vlen); free(vesc); } vcd_id[0] = ' '; vcd_id[vcdid_len + 1] = '\n'; fstWritex(xc, vcd_id, vcdid_len+2); } } } skiplen += len; headptr[idx] += skiplen; length_remaining[idx] -= skiplen; tc_head[i] = scatterptr[idx]; scatterptr[idx] = 0; if(length_remaining[idx]) { vli = fstGetVarint32NoSkip(mem_for_traversal + headptr[idx]); tdelta = vli >> 1; scatterptr[idx] = tc_head[i+tdelta]; tc_head[i+tdelta] = idx+1; } } } else { uint32_t len = xc->signal_lens[idx]; unsigned char *vdata; vli = fstGetVarint32(mem_for_traversal + headptr[idx], &skiplen); /* tdelta = vli >> 1; */ /* scan-build */ vdata = mem_for_traversal + headptr[idx] + skiplen; if(xc->signal_typs[idx] != FST_VT_VCD_REAL) { if(!(vli & 1)) { int byte = 0; int bit; unsigned int j; for(j=0;j> bit) & 1) | '0'; xc->temp_signal_value_buf[j] = ch; } xc->temp_signal_value_buf[j] = 0; if(value_change_callback) { value_change_callback(user_callback_data_pointer, time_table[i], idx+1, xc->temp_signal_value_buf); } else { if(fv) { unsigned char ch_bp = (xc->signal_typs[idx] != FST_VT_VCD_PORT) ? 'b' : 'p'; fstWritex(xc, &ch_bp, 1); fstWritex(xc, xc->temp_signal_value_buf, len); } } len = byte+1; } else { if(value_change_callback) { memcpy(xc->temp_signal_value_buf, vdata, len); xc->temp_signal_value_buf[len] = 0; value_change_callback(user_callback_data_pointer, time_table[i], idx+1, xc->temp_signal_value_buf); } else { if(fv) { unsigned char ch_bp = (xc->signal_typs[idx] != FST_VT_VCD_PORT) ? 'b' : 'p'; fstWritex(xc, &ch_bp, 1); fstWritex(xc, vdata, len); } } } } else { double d; unsigned char *clone_d /*= (unsigned char *)&d */; /* scan-build */ unsigned char buf[8]; unsigned char *srcdata; if(!(vli & 1)) /* very rare case, but possible */ { int bit; int j; for(j=0;j<8;j++) { unsigned char ch; bit = 7 - (j & 7); ch = ((vdata[0] >> bit) & 1) | '0'; buf[j] = ch; } len = 1; srcdata = buf; } else { srcdata = vdata; } if(value_change_callback) { if(xc->native_doubles_for_cb) { if(xc->double_endian_match) { clone_d = srcdata; } else { int j; clone_d = (unsigned char *)&d; for(j=0;j<8;j++) { clone_d[j] = srcdata[7-j]; } } value_change_callback(user_callback_data_pointer, time_table[i], idx+1, clone_d); } else { clone_d = (unsigned char *)&d; if(xc->double_endian_match) { memcpy(clone_d, srcdata, 8); } else { int j; for(j=0;j<8;j++) { clone_d[j] = srcdata[7-j]; } } sprintf((char *)xc->temp_signal_value_buf, "%.16g", d); value_change_callback(user_callback_data_pointer, time_table[i], idx+1, xc->temp_signal_value_buf); } } else { if(fv) { char wx_buf[32]; int wx_len; clone_d = (unsigned char *)&d; if(xc->double_endian_match) { memcpy(clone_d, srcdata, 8); } else { int j; for(j=0;j<8;j++) { clone_d[j] = srcdata[7-j]; } } wx_len = sprintf(wx_buf, "r%.16g", d); fstWritex(xc, wx_buf, wx_len); } } } if(fv) { char vcd_id[16]; int vcdid_len = fstVcdIDForFwrite(vcd_id+1, idx+1); vcd_id[0] = ' '; vcd_id[vcdid_len+1] = '\n'; fstWritex(xc, vcd_id, vcdid_len+2); } skiplen += len; headptr[idx] += skiplen; length_remaining[idx] -= skiplen; tc_head[i] = scatterptr[idx]; scatterptr[idx] = 0; if(length_remaining[idx]) { vli = fstGetVarint32NoSkip(mem_for_traversal + headptr[idx]); tdelta = vli >> 1; scatterptr[idx] = tc_head[i+tdelta]; tc_head[i+tdelta] = idx+1; } } } } block_err: free(tc_head); free(chain_cmem); free(mem_for_traversal); mem_for_traversal = NULL; secnum++; if(secnum == xc->vc_section_count) break; /* in case file is growing, keep with original block count */ blkpos += seclen; } if(mem_for_traversal) free(mem_for_traversal); /* scan-build */ free(length_remaining); free(headptr); free(scatterptr); if(chain_table) free(chain_table); if(chain_table_lengths) free(chain_table_lengths); free(time_table); #ifndef FST_WRITEX_DISABLE if(fv) { fstWritex(xc, NULL, 0); } #endif return(1); } /* rvat functions */ static char *fstExtractRvatDataFromFrame(struct fstReaderContext *xc, fstHandle facidx, char *buf) { if(facidx >= xc->rvat_frame_maxhandle) { return(NULL); } if(xc->signal_lens[facidx] == 1) { buf[0] = (char)xc->rvat_frame_data[xc->rvat_sig_offs[facidx]]; buf[1] = 0; } else { if(xc->signal_typs[facidx] != FST_VT_VCD_REAL) { memcpy(buf, xc->rvat_frame_data + xc->rvat_sig_offs[facidx], xc->signal_lens[facidx]); buf[xc->signal_lens[facidx]] = 0; } else { double d; unsigned char *clone_d = (unsigned char *)&d; unsigned char *srcdata = xc->rvat_frame_data + xc->rvat_sig_offs[facidx]; if(xc->double_endian_match) { memcpy(clone_d, srcdata, 8); } else { int j; for(j=0;j<8;j++) { clone_d[j] = srcdata[7-j]; } } sprintf((char *)buf, "%.16g", d); } } return(buf); } char *fstReaderGetValueFromHandleAtTime(void *ctx, uint64_t tim, fstHandle facidx, char *buf) { struct fstReaderContext *xc = (struct fstReaderContext *)ctx; off_t blkpos = 0, prev_blkpos; uint64_t beg_tim, end_tim, beg_tim2, end_tim2; int sectype; unsigned int secnum = 0; uint64_t seclen; uint64_t tsec_uclen = 0, tsec_clen = 0; uint64_t tsec_nitems; uint64_t frame_uclen, frame_clen; #ifdef FST_DEBUG uint64_t mem_required_for_traversal; #endif off_t indx_pntr, indx_pos; long chain_clen; unsigned char *chain_cmem; unsigned char *pnt; fstHandle idx, pidx=0, i; uint64_t pval; if((!xc) || (!facidx) || (facidx > xc->maxhandle) || (!buf) || (!xc->signal_lens[facidx-1])) { return(NULL); } if(!xc->rvat_sig_offs) { uint32_t cur_offs = 0; xc->rvat_sig_offs = (uint32_t *)calloc(xc->maxhandle, sizeof(uint32_t)); for(i=0;imaxhandle;i++) { xc->rvat_sig_offs[i] = cur_offs; cur_offs += xc->signal_lens[i]; } } if(xc->rvat_data_valid) { if((xc->rvat_beg_tim <= tim) && (tim <= xc->rvat_end_tim)) { goto process_value; } fstReaderDeallocateRvatData(xc); } xc->rvat_chain_pos_valid = 0; for(;;) { fstReaderFseeko(xc, xc->f, (prev_blkpos = blkpos), SEEK_SET); sectype = fgetc(xc->f); seclen = fstReaderUint64(xc->f); if((sectype == EOF) || (sectype == FST_BL_SKIP) || (!seclen)) { return(NULL); /* if this loop exits on break, it's successful */ } blkpos++; if((sectype != FST_BL_VCDATA) && (sectype != FST_BL_VCDATA_DYN_ALIAS) && (sectype != FST_BL_VCDATA_DYN_ALIAS2)) { blkpos += seclen; continue; } beg_tim = fstReaderUint64(xc->f); end_tim = fstReaderUint64(xc->f); if((beg_tim <= tim) && (tim <= end_tim)) { if((tim == end_tim) && (tim != xc->end_time)) { off_t cached_pos = ftello(xc->f); fstReaderFseeko(xc, xc->f, blkpos, SEEK_SET); sectype = fgetc(xc->f); seclen = fstReaderUint64(xc->f); beg_tim2 = fstReaderUint64(xc->f); end_tim2 = fstReaderUint64(xc->f); if(((sectype != FST_BL_VCDATA)&&(sectype != FST_BL_VCDATA_DYN_ALIAS)&&(sectype != FST_BL_VCDATA_DYN_ALIAS2)) || (!seclen) || (beg_tim2 != tim)) { blkpos = prev_blkpos; break; } beg_tim = beg_tim2; end_tim = end_tim2; fstReaderFseeko(xc, xc->f, cached_pos, SEEK_SET); } break; } blkpos += seclen; secnum++; } xc->rvat_beg_tim = beg_tim; xc->rvat_end_tim = end_tim; #ifdef FST_DEBUG mem_required_for_traversal = #endif fstReaderUint64(xc->f); #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "rvat sec: %u seclen: %d begtim: %d endtim: %d\n", secnum, (int)seclen, (int)beg_tim, (int)end_tim); fprintf(stderr, FST_APIMESS "mem_required_for_traversal: %d\n", (int)mem_required_for_traversal); #endif /* process time block */ { unsigned char *ucdata; unsigned char *cdata; unsigned long destlen /* = tsec_uclen */; /* scan-build */ unsigned long sourcelen /* = tsec_clen */; /* scan-build */ int rc; unsigned char *tpnt; uint64_t tpval; unsigned int ti; fstReaderFseeko(xc, xc->f, blkpos + seclen - 24, SEEK_SET); tsec_uclen = fstReaderUint64(xc->f); tsec_clen = fstReaderUint64(xc->f); tsec_nitems = fstReaderUint64(xc->f); #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "time section unc: %d, com: %d (%d items)\n", (int)tsec_uclen, (int)tsec_clen, (int)tsec_nitems); #endif ucdata = (unsigned char *)malloc(tsec_uclen); destlen = tsec_uclen; sourcelen = tsec_clen; fstReaderFseeko(xc, xc->f, -24 - ((off_t)tsec_clen), SEEK_CUR); if(tsec_uclen != tsec_clen) { cdata = (unsigned char *)malloc(tsec_clen); fstFread(cdata, tsec_clen, 1, xc->f); rc = uncompress(ucdata, &destlen, cdata, sourcelen); if(rc != Z_OK) { fprintf(stderr, FST_APIMESS "fstReaderGetValueFromHandleAtTime(), tsec uncompress rc = %d, exiting.\n", rc); exit(255); } free(cdata); } else { fstFread(ucdata, tsec_uclen, 1, xc->f); } xc->rvat_time_table = (uint64_t *)calloc(tsec_nitems, sizeof(uint64_t)); tpnt = ucdata; tpval = 0; for(ti=0;tirvat_time_table[ti] = tpval + val; tpnt += skiplen; } free(ucdata); } fstReaderFseeko(xc, xc->f, blkpos+32, SEEK_SET); frame_uclen = fstReaderVarint64(xc->f); frame_clen = fstReaderVarint64(xc->f); xc->rvat_frame_maxhandle = fstReaderVarint64(xc->f); xc->rvat_frame_data = (unsigned char *)malloc(frame_uclen); if(frame_uclen == frame_clen) { fstFread(xc->rvat_frame_data, frame_uclen, 1, xc->f); } else { unsigned char *mc = (unsigned char *)malloc(frame_clen); int rc; unsigned long destlen = frame_uclen; unsigned long sourcelen = frame_clen; fstFread(mc, sourcelen, 1, xc->f); rc = uncompress(xc->rvat_frame_data, &destlen, mc, sourcelen); if(rc != Z_OK) { fprintf(stderr, FST_APIMESS "fstReaderGetValueFromHandleAtTime(), frame decompress rc: %d, exiting.\n", rc); exit(255); } free(mc); } xc->rvat_vc_maxhandle = fstReaderVarint64(xc->f); xc->rvat_vc_start = ftello(xc->f); /* points to '!' character */ xc->rvat_packtype = fgetc(xc->f); #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "frame_uclen: %d, frame_clen: %d, frame_maxhandle: %d\n", (int)frame_uclen, (int)frame_clen, (int)xc->rvat_frame_maxhandle); fprintf(stderr, FST_APIMESS "vc_maxhandle: %d\n", (int)xc->rvat_vc_maxhandle); #endif indx_pntr = blkpos + seclen - 24 -tsec_clen -8; fstReaderFseeko(xc, xc->f, indx_pntr, SEEK_SET); chain_clen = fstReaderUint64(xc->f); indx_pos = indx_pntr - chain_clen; #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "indx_pos: %d (%d bytes)\n", (int)indx_pos, (int)chain_clen); #endif chain_cmem = (unsigned char *)malloc(chain_clen); fstReaderFseeko(xc, xc->f, indx_pos, SEEK_SET); fstFread(chain_cmem, chain_clen, 1, xc->f); xc->rvat_chain_table = (off_t *)calloc((xc->rvat_vc_maxhandle+1), sizeof(off_t)); xc->rvat_chain_table_lengths = (uint32_t *)calloc((xc->rvat_vc_maxhandle+1), sizeof(uint32_t)); pnt = chain_cmem; idx = 0; pval = 0; if(sectype == FST_BL_VCDATA_DYN_ALIAS2) { uint32_t prev_alias = 0; do { int skiplen; if(*pnt & 0x01) { int64_t shval = fstGetSVarint64(pnt, &skiplen) >> 1; if(shval > 0) { pval = xc->rvat_chain_table[idx] = pval + shval; if(idx) { xc->rvat_chain_table_lengths[pidx] = pval - xc->rvat_chain_table[pidx]; } pidx = idx++; } else if(shval < 0) { xc->rvat_chain_table[idx] = 0; /* need to explicitly zero as calloc above might not run */ xc->rvat_chain_table_lengths[idx] = prev_alias = shval; /* because during this loop iter would give stale data! */ idx++; } else { xc->rvat_chain_table[idx] = 0; /* need to explicitly zero as calloc above might not run */ xc->rvat_chain_table_lengths[idx] = prev_alias; /* because during this loop iter would give stale data! */ idx++; } } else { uint64_t val = fstGetVarint32(pnt, &skiplen); fstHandle loopcnt = val >> 1; for(i=0;irvat_chain_table[idx++] = 0; } } pnt += skiplen; } while (pnt != (chain_cmem + chain_clen)); } else { do { int skiplen; uint64_t val = fstGetVarint32(pnt, &skiplen); if(!val) { pnt += skiplen; val = fstGetVarint32(pnt, &skiplen); xc->rvat_chain_table[idx] = 0; xc->rvat_chain_table_lengths[idx] = -val; idx++; } else if(val&1) { pval = xc->rvat_chain_table[idx] = pval + (val >> 1); if(idx) { xc->rvat_chain_table_lengths[pidx] = pval - xc->rvat_chain_table[pidx]; } pidx = idx++; } else { fstHandle loopcnt = val >> 1; for(i=0;irvat_chain_table[idx++] = 0; } } pnt += skiplen; } while (pnt != (chain_cmem + chain_clen)); } free(chain_cmem); xc->rvat_chain_table[idx] = indx_pos - xc->rvat_vc_start; xc->rvat_chain_table_lengths[pidx] = xc->rvat_chain_table[idx] - xc->rvat_chain_table[pidx]; for(i=0;irvat_chain_table_lengths[i]; if((v32 < 0) && (!xc->rvat_chain_table[i])) { v32 = -v32; v32--; if(((uint32_t)v32) < i) /* sanity check */ { xc->rvat_chain_table[i] = xc->rvat_chain_table[v32]; xc->rvat_chain_table_lengths[i] = xc->rvat_chain_table_lengths[v32]; } } } #ifdef FST_DEBUG fprintf(stderr, FST_APIMESS "decompressed chain idx len: %" PRIu32 "\n", idx); #endif xc->rvat_data_valid = 1; /* all data at this point is loaded or resident in fst cache, process and return appropriate value */ process_value: if(facidx > xc->rvat_vc_maxhandle) { return(NULL); } facidx--; /* scale down for array which starts at zero */ if(((tim == xc->rvat_beg_tim)&&(!xc->rvat_chain_table[facidx])) || (!xc->rvat_chain_table[facidx])) { return(fstExtractRvatDataFromFrame(xc, facidx, buf)); } if(facidx != xc->rvat_chain_facidx) { if(xc->rvat_chain_mem) { free(xc->rvat_chain_mem); xc->rvat_chain_mem = NULL; xc->rvat_chain_pos_valid = 0; } } if(!xc->rvat_chain_mem) { uint32_t skiplen; fstReaderFseeko(xc, xc->f, xc->rvat_vc_start + xc->rvat_chain_table[facidx], SEEK_SET); xc->rvat_chain_len = fstReaderVarint32WithSkip(xc->f, &skiplen); if(xc->rvat_chain_len) { unsigned char *mu = (unsigned char *)malloc(xc->rvat_chain_len); unsigned char *mc = (unsigned char *)malloc(xc->rvat_chain_table_lengths[facidx]); unsigned long destlen = xc->rvat_chain_len; unsigned long sourcelen = xc->rvat_chain_table_lengths[facidx]; int rc = Z_OK; fstFread(mc, xc->rvat_chain_table_lengths[facidx], 1, xc->f); switch(xc->rvat_packtype) { case '4': rc = (destlen == (unsigned long)LZ4_decompress_safe_partial((char *)mc, (char *)mu, sourcelen, destlen, destlen)) ? Z_OK : Z_DATA_ERROR; break; case 'F': fastlz_decompress(mc, sourcelen, mu, destlen); /* rc appears unreliable */ break; default: rc = uncompress(mu, &destlen, mc, sourcelen); break; } free(mc); if(rc != Z_OK) { fprintf(stderr, FST_APIMESS "fstReaderGetValueFromHandleAtTime(), rvat decompress clen: %d (rc=%d), exiting.\n", (int)xc->rvat_chain_len, rc); exit(255); } /* data to process is for(j=0;jrvat_chain_mem = mu; } else { int destlen = xc->rvat_chain_table_lengths[facidx] - skiplen; unsigned char *mu = (unsigned char *)malloc(xc->rvat_chain_len = destlen); fstFread(mu, destlen, 1, xc->f); /* data to process is for(j=0;jrvat_chain_mem = mu; } xc->rvat_chain_facidx = facidx; } /* process value chain here */ { uint32_t tidx = 0, ptidx = 0; uint32_t tdelta; int skiplen; unsigned int iprev = xc->rvat_chain_len; uint32_t pvli = 0; int pskip = 0; if((xc->rvat_chain_pos_valid)&&(tim >= xc->rvat_chain_pos_time)) { i = xc->rvat_chain_pos_idx; tidx = xc->rvat_chain_pos_tidx; } else { i = 0; tidx = 0; xc->rvat_chain_pos_time = xc->rvat_beg_tim; } if(xc->signal_lens[facidx] == 1) { while(irvat_chain_len) { uint32_t vli = fstGetVarint32(xc->rvat_chain_mem + i, &skiplen); uint32_t shcnt = 2 << (vli & 1); tdelta = vli >> shcnt; if(xc->rvat_time_table[tidx + tdelta] <= tim) { iprev = i; pvli = vli; ptidx = tidx; /* pskip = skiplen; */ /* scan-build */ tidx += tdelta; i+=skiplen; } else { break; } } if(iprev != xc->rvat_chain_len) { xc->rvat_chain_pos_tidx = ptidx; xc->rvat_chain_pos_idx = iprev; xc->rvat_chain_pos_time = tim; xc->rvat_chain_pos_valid = 1; if(!(pvli & 1)) { buf[0] = ((pvli >> 1) & 1) | '0'; } else { buf[0] = FST_RCV_STR[((pvli >> 1) & 7)]; } buf[1] = 0; return(buf); } else { return(fstExtractRvatDataFromFrame(xc, facidx, buf)); } } else { while(irvat_chain_len) { uint32_t vli = fstGetVarint32(xc->rvat_chain_mem + i, &skiplen); tdelta = vli >> 1; if(xc->rvat_time_table[tidx + tdelta] <= tim) { iprev = i; pvli = vli; ptidx = tidx; pskip = skiplen; tidx += tdelta; i+=skiplen; if(!(pvli & 1)) { i+=((xc->signal_lens[facidx]+7)/8); } else { i+=xc->signal_lens[facidx]; } } else { break; } } if(iprev != xc->rvat_chain_len) { unsigned char *vdata = xc->rvat_chain_mem + iprev + pskip; xc->rvat_chain_pos_tidx = ptidx; xc->rvat_chain_pos_idx = iprev; xc->rvat_chain_pos_time = tim; xc->rvat_chain_pos_valid = 1; if(xc->signal_typs[facidx] != FST_VT_VCD_REAL) { if(!(pvli & 1)) { int byte = 0; int bit; unsigned int j; for(j=0;jsignal_lens[facidx];j++) { unsigned char ch; byte = j/8; bit = 7 - (j & 7); ch = ((vdata[byte] >> bit) & 1) | '0'; buf[j] = ch; } buf[j] = 0; return(buf); } else { memcpy(buf, vdata, xc->signal_lens[facidx]); buf[xc->signal_lens[facidx]] = 0; return(buf); } } else { double d; unsigned char *clone_d = (unsigned char *)&d; unsigned char bufd[8]; unsigned char *srcdata; if(!(pvli & 1)) /* very rare case, but possible */ { int bit; int j; for(j=0;j<8;j++) { unsigned char ch; bit = 7 - (j & 7); ch = ((vdata[0] >> bit) & 1) | '0'; bufd[j] = ch; } srcdata = bufd; } else { srcdata = vdata; } if(xc->double_endian_match) { memcpy(clone_d, srcdata, 8); } else { int j; for(j=0;j<8;j++) { clone_d[j] = srcdata[7-j]; } } sprintf(buf, "r%.16g", d); return(buf); } } else { return(fstExtractRvatDataFromFrame(xc, facidx, buf)); } } } /* return(NULL); */ } /**********************************************************************/ #ifndef _WAVE_HAVE_JUDY /***********************/ /*** ***/ /*** jenkins hash ***/ /*** ***/ /***********************/ /* -------------------------------------------------------------------- mix -- mix 3 32-bit values reversibly. For every delta with one or two bits set, and the deltas of all three high bits or all three low bits, whether the original value of a,b,c is almost all zero or is uniformly distributed, * If mix() is run forward or backward, at least 32 bits in a,b,c have at least 1/4 probability of changing. * If mix() is run forward, every bit of c will change between 1/3 and 2/3 of the time. (Well, 22/100 and 78/100 for some 2-bit deltas.) mix() was built out of 36 single-cycle latency instructions in a structure that could supported 2x parallelism, like so: a -= b; a -= c; x = (c>>13); b -= c; a ^= x; b -= a; x = (a<<8); c -= a; b ^= x; c -= b; x = (b>>13); ... Unfortunately, superscalar Pentiums and Sparcs can't take advantage of that parallelism. They've also turned some of those single-cycle latency instructions into multi-cycle latency instructions. Still, this is the fastest good hash I could find. There were about 2^^68 to choose from. I only looked at a billion or so. -------------------------------------------------------------------- */ #define mix(a,b,c) \ { \ a -= b; a -= c; a ^= (c>>13); \ b -= c; b -= a; b ^= (a<<8); \ c -= a; c -= b; c ^= (b>>13); \ a -= b; a -= c; a ^= (c>>12); \ b -= c; b -= a; b ^= (a<<16); \ c -= a; c -= b; c ^= (b>>5); \ a -= b; a -= c; a ^= (c>>3); \ b -= c; b -= a; b ^= (a<<10); \ c -= a; c -= b; c ^= (b>>15); \ } /* -------------------------------------------------------------------- j_hash() -- hash a variable-length key into a 32-bit value k : the key (the unaligned variable-length array of bytes) len : the length of the key, counting by bytes initval : can be any 4-byte value Returns a 32-bit value. Every bit of the key affects every bit of the return value. Every 1-bit and 2-bit delta achieves avalanche. About 6*len+35 instructions. The best hash table sizes are powers of 2. There is no need to do mod a prime (mod is sooo slow!). If you need less than 32 bits, use a bitmask. For example, if you need only 10 bits, do h = (h & hashmask(10)); In which case, the hash table should have hashsize(10) elements. If you are hashing n strings (uint8_t **)k, do it like this: for (i=0, h=0; i= 12) { a += (k[0] +((uint32_t)k[1]<<8) +((uint32_t)k[2]<<16) +((uint32_t)k[3]<<24)); b += (k[4] +((uint32_t)k[5]<<8) +((uint32_t)k[6]<<16) +((uint32_t)k[7]<<24)); c += (k[8] +((uint32_t)k[9]<<8) +((uint32_t)k[10]<<16)+((uint32_t)k[11]<<24)); mix(a,b,c); k += 12; len -= 12; } /*------------------------------------- handle the last 11 bytes */ c += length; switch(len) /* all the case statements fall through */ { case 11: c+=((uint32_t)k[10]<<24); /* fallthrough */ case 10: c+=((uint32_t)k[9]<<16); /* fallthrough */ case 9 : c+=((uint32_t)k[8]<<8); /* fallthrough */ /* the first byte of c is reserved for the length */ case 8 : b+=((uint32_t)k[7]<<24); /* fallthrough */ case 7 : b+=((uint32_t)k[6]<<16); /* fallthrough */ case 6 : b+=((uint32_t)k[5]<<8); /* fallthrough */ case 5 : b+=k[4]; /* fallthrough */ case 4 : a+=((uint32_t)k[3]<<24); /* fallthrough */ case 3 : a+=((uint32_t)k[2]<<16); /* fallthrough */ case 2 : a+=((uint32_t)k[1]<<8); /* fallthrough */ case 1 : a+=k[0]; /* case 0: nothing left to add */ } mix(a,b,c); /*-------------------------------------------- report the result */ return(c); } /********************************************************************/ /***************************/ /*** ***/ /*** judy HS emulation ***/ /*** ***/ /***************************/ struct collchain_t { struct collchain_t *next; void *payload; uint32_t fullhash, length; unsigned char mem[1]; }; void **JenkinsIns(void *base_i, const unsigned char *mem, uint32_t length, uint32_t hashmask) { struct collchain_t ***base = (struct collchain_t ***)base_i; uint32_t hf, h; struct collchain_t **ar; struct collchain_t *chain, *pchain; if(!*base) { *base = (struct collchain_t **)calloc(1, (hashmask + 1) * sizeof(void *)); } ar = *base; h = (hf = j_hash(mem, length, length)) & hashmask; pchain = chain = ar[h]; while(chain) { if((chain->fullhash == hf) && (chain->length == length) && !memcmp(chain->mem, mem, length)) { if(pchain != chain) /* move hit to front */ { pchain->next = chain->next; chain->next = ar[h]; ar[h] = chain; } return(&(chain->payload)); } pchain = chain; chain = chain->next; } chain = (struct collchain_t *)calloc(1, sizeof(struct collchain_t) + length - 1); memcpy(chain->mem, mem, length); chain->fullhash = hf; chain->length = length; chain->next = ar[h]; ar[h] = chain; return(&(chain->payload)); } void JenkinsFree(void *base_i, uint32_t hashmask) { struct collchain_t ***base = (struct collchain_t ***)base_i; uint32_t h; struct collchain_t **ar; struct collchain_t *chain, *chain_next; if(base && *base) { ar = *base; for(h=0;h<=hashmask;h++) { chain = ar[h]; while(chain) { chain_next = chain->next; free(chain); chain = chain_next; } } free(*base); *base = NULL; } } #endif /**********************************************************************/ /************************/ /*** ***/ /*** utility function ***/ /*** ***/ /************************/ int fstUtilityBinToEscConvertedLen(const unsigned char *s, int len) { const unsigned char *src = s; int dlen = 0; int i; for(i=0;i ' ') && (src[i] <= '~')) /* no white spaces in output */ { dlen++; } else { dlen += 4; } break; } } return(dlen); } int fstUtilityBinToEsc(unsigned char *d, const unsigned char *s, int len) { const unsigned char *src = s; unsigned char *dst = d; unsigned char val; int i; for(i=0;i ' ') && (src[i] <= '~')) /* no white spaces in output */ { *(dst++) = src[i]; } else { val = src[i]; *(dst++) = '\\'; *(dst++) = (val/64) + '0'; val = val & 63; *(dst++) = (val/8) + '0'; val = val & 7; *(dst++) = (val) + '0'; } break; } } return(dst - d); } /* * this overwrites the original string if the destination pointer is NULL */ int fstUtilityEscToBin(unsigned char *d, unsigned char *s, int len) { unsigned char *src = s; unsigned char *dst = (!d) ? s : (s = d); unsigned char val[3]; int i; for(i=0;i='A')&&(val[0]<='F')) ? (val[0] - 'A' + 10) : (val[0] - '0'); val[1] = ((val[1]>='A')&&(val[1]<='F')) ? (val[1] - 'A' + 10) : (val[1] - '0'); *(dst++) = val[0] * 16 + val[1]; break; case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': val[0] = src[ i] - '0'; val[1] = src[++i] - '0'; val[2] = src[++i] - '0'; *(dst++) = val[0] * 64 + val[1] * 8 + val[2]; break; default: *(dst++) = src[i]; break; } } } return(dst - s); } struct fstETab *fstUtilityExtractEnumTableFromString(const char *s) { struct fstETab *et = NULL; int num_spaces = 0; int i; int newlen; if(s) { const char *csp = strchr(s, ' '); int cnt = atoi(csp+1); for(;;) { csp = strchr(csp+1, ' '); if(csp) { num_spaces++; } else { break; } } if(num_spaces == (2*cnt)) { char *sp, *sp2; et = (struct fstETab*)calloc(1, sizeof(struct fstETab)); et->elem_count = cnt; et->name = strdup(s); et->literal_arr = (char**)calloc(cnt, sizeof(char *)); et->val_arr = (char**)calloc(cnt, sizeof(char *)); sp = strchr(et->name, ' '); *sp = 0; sp = strchr(sp+1, ' '); for(i=0;iliteral_arr[i] = sp+1; sp = sp2; newlen = fstUtilityEscToBin(NULL, (unsigned char*)et->literal_arr[i], strlen(et->literal_arr[i])); et->literal_arr[i][newlen] = 0; } for(i=0;ival_arr[i] = sp+1; sp = sp2; newlen = fstUtilityEscToBin(NULL, (unsigned char*)et->val_arr[i], strlen(et->val_arr[i])); et->val_arr[i][newlen] = 0; } } } return(et); } void fstUtilityFreeEnumTable(struct fstETab *etab) { if(etab) { free(etab->literal_arr); free(etab->val_arr); free(etab->name); free(etab); } } verilator-4.038/include/gtkwave/fst_config.h0000664000177100017500000000065513702133367021114 0ustar wsnyderwsnyder/* This file specifically for FST usage */ /* config.h. Generated from config.h.in by configure. */ /* config.h.in. Generated from configure.ac by autoheader. */ /* Define to 1 if you have and it should be used (not on Ultrix). */ #if !defined(__MINGW32__) && !defined(__FreeBSD__) # define HAVE_ALLOCA_H 1 #endif /* Define to 1 if fseeko (and presumably ftello) exists and is declared. */ #define HAVE_FSEEKO 1 verilator-4.038/include/gtkwave/fastlz.h0000664000177100017500000000714513702133367020277 0ustar wsnyderwsnyder/* FastLZ - lightning-fast lossless compression library Copyright (C) 2007 Ariya Hidayat (ariya@kde.org) Copyright (C) 2006 Ariya Hidayat (ariya@kde.org) Copyright (C) 2005 Ariya Hidayat (ariya@kde.org) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. SPDX-License-Identifier: MIT */ #ifndef FASTLZ_H #define FASTLZ_H #include #define flzuint8 uint8_t #define flzuint16 uint16_t #define flzuint32 uint32_t #define FASTLZ_VERSION 0x000100 #define FASTLZ_VERSION_MAJOR 0 #define FASTLZ_VERSION_MINOR 0 #define FASTLZ_VERSION_REVISION 0 #define FASTLZ_VERSION_STRING "0.1.0" #if defined (__cplusplus) extern "C" { #endif /** Compress a block of data in the input buffer and returns the size of compressed block. The size of input buffer is specified by length. The minimum input buffer size is 16. The output buffer must be at least 5% larger than the input buffer and can not be smaller than 66 bytes. If the input is not compressible, the return value might be larger than length (input buffer size). The input buffer and the output buffer can not overlap. */ int fastlz_compress(const void* input, int length, void* output); /** Decompress a block of compressed data and returns the size of the decompressed block. If error occurs, e.g. the compressed data is corrupted or the output buffer is not large enough, then 0 (zero) will be returned instead. The input buffer and the output buffer can not overlap. Decompression is memory safe and guaranteed not to write the output buffer more than what is specified in maxout. */ int fastlz_decompress(const void* input, int length, void* output, int maxout); /** Compress a block of data in the input buffer and returns the size of compressed block. The size of input buffer is specified by length. The minimum input buffer size is 16. The output buffer must be at least 5% larger than the input buffer and can not be smaller than 66 bytes. If the input is not compressible, the return value might be larger than length (input buffer size). The input buffer and the output buffer can not overlap. Compression level can be specified in parameter level. At the moment, only level 1 and level 2 are supported. Level 1 is the fastest compression and generally useful for short data. Level 2 is slightly slower but it gives better compression ratio. Note that the compressed data, regardless of the level, can always be decompressed using the function fastlz_decompress above. */ int fastlz_compress_level(int level, const void* input, int length, void* output); #if defined (__cplusplus) } #endif #endif /* FASTLZ_H */ verilator-4.038/include/verilated_cov_key.h0000664000177100017500000001622013702133367021014 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Coverage item keys /// //============================================================================= #ifndef _VERILATED_COV_KEY_H_ #define _VERILATED_COV_KEY_H_ 1 #include "verilatedos.h" #include //============================================================================= // Data used to edit below file, using vlcovgen #define VLCOVGEN_ITEM(string_parsed_by_vlcovgen) // clang-format off VLCOVGEN_ITEM("name=>'col0_name', short=>'C0', group=>1, default=>undef, descr=>'The column title for the header line of this column'") VLCOVGEN_ITEM("name=>'col1_name', short=>'C1', group=>1, default=>undef, ") VLCOVGEN_ITEM("name=>'col2_name', short=>'C2', group=>1, default=>undef, ") VLCOVGEN_ITEM("name=>'col3_name', short=>'C3', group=>1, default=>undef, ") VLCOVGEN_ITEM("name=>'column', short=>'n', group=>1, default=>0, descr=>'Column number for the item. Used to disambiguate multiple coverage points on the same line number'") VLCOVGEN_ITEM("name=>'filename', short=>'f', group=>1, default=>undef, descr=>'Filename of the item'") VLCOVGEN_ITEM("name=>'groupdesc', short=>'d', group=>1, default=>'', descr=>'Description of the covergroup this item belongs to'") VLCOVGEN_ITEM("name=>'groupname', short=>'g', group=>1, default=>'', descr=>'Group name of the covergroup this item belongs to'") VLCOVGEN_ITEM("name=>'groupcmt', short=>'O', group=>1, default=>'', ") VLCOVGEN_ITEM("name=>'linescov', short=>'S', group=>1, default=>'', descr=>'List of comma-separated lines covered'") VLCOVGEN_ITEM("name=>'per_instance',short=>'P', group=>1, default=>0, descr=>'True if every hierarchy is independently counted; otherwise all hierarchies will be combined into a single count'") VLCOVGEN_ITEM("name=>'row0_name', short=>'R0', group=>1, default=>undef, descr=>'The row title for the header line of this row'") VLCOVGEN_ITEM("name=>'row1_name', short=>'R1', group=>1, default=>undef, ") VLCOVGEN_ITEM("name=>'row2_name', short=>'R2', group=>1, default=>undef, ") VLCOVGEN_ITEM("name=>'row3_name', short=>'R3', group=>1, default=>undef, ") VLCOVGEN_ITEM("name=>'table', short=>'T', group=>1, default=>undef, descr=>'The name of the table for automatically generated tables'") VLCOVGEN_ITEM("name=>'thresh', short=>'s', group=>1, default=>undef, ") VLCOVGEN_ITEM("name=>'type', short=>'t', group=>1, default=>'', descr=>'Type of coverage (block, line, fsm, etc)'") // Bin attributes VLCOVGEN_ITEM("name=>'col0', short=>'c0', group=>0, default=>undef, descr=>'The (enumeration) value name for this column in a table cross' ") VLCOVGEN_ITEM("name=>'col1', short=>'c1', group=>0, default=>undef, ") VLCOVGEN_ITEM("name=>'col2', short=>'c2', group=>0, default=>undef, ") VLCOVGEN_ITEM("name=>'col3', short=>'c3', group=>0, default=>undef, ") VLCOVGEN_ITEM("name=>'comment', short=>'o', group=>0, default=>'', descr=>'Textual description for the item'") VLCOVGEN_ITEM("name=>'hier', short=>'h', group=>0, default=>'', descr=>'Hierarchy path name for the item'") VLCOVGEN_ITEM("name=>'limit', short=>'L', group=>0, default=>undef, ") VLCOVGEN_ITEM("name=>'lineno', short=>'l', group=>0, default=>0, descr=>'Line number for the item'") VLCOVGEN_ITEM("name=>'row0', short=>'r0', group=>0, default=>undef, descr=>'The (enumeration) value name for this row in a table cross'") VLCOVGEN_ITEM("name=>'row1', short=>'r1', group=>0, default=>undef, ") VLCOVGEN_ITEM("name=>'row2', short=>'r2', group=>0, default=>undef, ") VLCOVGEN_ITEM("name=>'row3', short=>'r3', group=>0, default=>undef, ") VLCOVGEN_ITEM("name=>'weight', short=>'w', group=>0, default=>undef, descr=>'For totaling items, weight of this item'") // clang-format on // VLCOVGEN_CIK_AUTO_EDIT_BEGIN #define VL_CIK_COL0 "c0" #define VL_CIK_COL0_NAME "C0" #define VL_CIK_COL1 "c1" #define VL_CIK_COL1_NAME "C1" #define VL_CIK_COL2 "c2" #define VL_CIK_COL2_NAME "C2" #define VL_CIK_COL3 "c3" #define VL_CIK_COL3_NAME "C3" #define VL_CIK_COLUMN "n" #define VL_CIK_COMMENT "o" #define VL_CIK_FILENAME "f" #define VL_CIK_GROUPCMT "O" #define VL_CIK_GROUPDESC "d" #define VL_CIK_GROUPNAME "g" #define VL_CIK_HIER "h" #define VL_CIK_LIMIT "L" #define VL_CIK_LINENO "l" #define VL_CIK_LINESCOV "S" #define VL_CIK_PER_INSTANCE "P" #define VL_CIK_ROW0 "r0" #define VL_CIK_ROW0_NAME "R0" #define VL_CIK_ROW1 "r1" #define VL_CIK_ROW1_NAME "R1" #define VL_CIK_ROW2 "r2" #define VL_CIK_ROW2_NAME "R2" #define VL_CIK_ROW3 "r3" #define VL_CIK_ROW3_NAME "R3" #define VL_CIK_TABLE "T" #define VL_CIK_THRESH "s" #define VL_CIK_TYPE "t" #define VL_CIK_WEIGHT "w" // VLCOVGEN_CIK_AUTO_EDIT_END //============================================================================= // VerilatedCovKey /// Verilator coverage global class. /// This class is thread safe. class VerilatedCovKey { public: static std::string shortKey(const std::string& key) VL_PURE { // VLCOVGEN_SHORT_AUTO_EDIT_BEGIN if (key == "col0") return VL_CIK_COL0; if (key == "col0_name") return VL_CIK_COL0_NAME; if (key == "col1") return VL_CIK_COL1; if (key == "col1_name") return VL_CIK_COL1_NAME; if (key == "col2") return VL_CIK_COL2; if (key == "col2_name") return VL_CIK_COL2_NAME; if (key == "col3") return VL_CIK_COL3; if (key == "col3_name") return VL_CIK_COL3_NAME; if (key == "column") return VL_CIK_COLUMN; if (key == "comment") return VL_CIK_COMMENT; if (key == "filename") return VL_CIK_FILENAME; if (key == "groupcmt") return VL_CIK_GROUPCMT; if (key == "groupdesc") return VL_CIK_GROUPDESC; if (key == "groupname") return VL_CIK_GROUPNAME; if (key == "hier") return VL_CIK_HIER; if (key == "limit") return VL_CIK_LIMIT; if (key == "lineno") return VL_CIK_LINENO; if (key == "linescov") return VL_CIK_LINESCOV; if (key == "per_instance") return VL_CIK_PER_INSTANCE; if (key == "row0") return VL_CIK_ROW0; if (key == "row0_name") return VL_CIK_ROW0_NAME; if (key == "row1") return VL_CIK_ROW1; if (key == "row1_name") return VL_CIK_ROW1_NAME; if (key == "row2") return VL_CIK_ROW2; if (key == "row2_name") return VL_CIK_ROW2_NAME; if (key == "row3") return VL_CIK_ROW3; if (key == "row3_name") return VL_CIK_ROW3_NAME; if (key == "table") return VL_CIK_TABLE; if (key == "thresh") return VL_CIK_THRESH; if (key == "type") return VL_CIK_TYPE; if (key == "weight") return VL_CIK_WEIGHT; // VLCOVGEN_SHORT_AUTO_EDIT_END return key; } }; #endif // guard verilator-4.038/include/verilated_syms.h0000664000177100017500000000426213702133367020353 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: Include to allow symbol inspection /// /// This file is for inclusion by files that need to inspect the symbol /// table. It is not included in verilated.h (instead see /// verilated_sym_props.h) as it requires some heavyweight C++ classes. /// /// These classes are thread safe and read only. It is constructed only /// when a model is built (from the main thread). /// /// Code available from: https://verilator.org /// //************************************************************************* #ifndef _VERILATED_SYMS_H_ #define _VERILATED_SYMS_H_ 1 ///< Header Guard #include "verilatedos.h" #include "verilated_heavy.h" #include "verilated_sym_props.h" #include #include //====================================================================== /// Types /// Class to sort maps keyed by const char*'s struct VerilatedCStrCmp { bool operator()(const char* a, const char* b) const { return std::strcmp(a, b) < 0; } }; /// Map of sorted scope names to find associated scope class class VerilatedScopeNameMap : public std::map { public: VerilatedScopeNameMap() {} ~VerilatedScopeNameMap() {} }; /// Map of sorted variable names to find associated variable class class VerilatedVarNameMap : public std::map { public: VerilatedVarNameMap() {} ~VerilatedVarNameMap() {} }; typedef std::vector VerilatedScopeVector; class VerilatedHierarchyMap : public std::map { public: VerilatedHierarchyMap() {} ~VerilatedHierarchyMap() {} }; #endif // Guard verilator-4.038/include/verilated.cpp0000664000177100017500000031562213702133367017640 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// /// \file /// \brief Verilator: Linked against all applications using Verilated source. /// /// This file must be compiled and linked against all objects /// created from Verilator. /// /// Code available from: https://verilator.org /// //========================================================================= #define _VERILATED_CPP_ #include "verilatedos.h" #include "verilated_imp.h" #include "verilated_config.h" #include #include #include #include #include // mkdir #include #include // clang-format off #if defined(_WIN32) || defined(__MINGW32__) # include // mkdir #endif // clang-format on #define VL_VALUE_STRING_MAX_WIDTH 8192 ///< Max static char array for VL_VALUE_STRING //=========================================================================== // Static sanity checks (when get C++11 can use static_assert) typedef union { // cppcheck-suppress unusedStructMember // Unused as is assertion char vluint8_incorrect[(sizeof(vluint8_t) == 1) ? 1 : -1]; // cppcheck-suppress unusedStructMember // Unused as is assertion char vluint16_incorrect[(sizeof(vluint16_t) == 2) ? 1 : -1]; // cppcheck-suppress unusedStructMember // Unused as is assertion char vluint32_incorrect[(sizeof(vluint32_t) == 4) ? 1 : -1]; // cppcheck-suppress unusedStructMember // Unused as is assertion char vluint64_incorrect[(sizeof(vluint64_t) == 8) ? 1 : -1]; } vl_static_checks_t; //=========================================================================== // Global variables // Slow path variables VerilatedMutex Verilated::m_mutex; // Keep below together in one cache line Verilated::Serialized Verilated::s_s; Verilated::NonSerialized Verilated::s_ns; VL_THREAD_LOCAL Verilated::ThreadLocal Verilated::t_s; Verilated::CommandArgValues Verilated::s_args; VerilatedImp VerilatedImp::s_s; //=========================================================================== // User definable functions // Note a TODO is a future version of the API will pass a structure so that // the calling arguments allow for extension #ifndef VL_USER_FINISH ///< Define this to override this function void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { if (false && hier) {} VL_PRINTF( // Not VL_PRINTF_MT, already on main thread "- %s:%d: Verilog $finish\n", filename, linenum); if (Verilated::gotFinish()) { VL_PRINTF( // Not VL_PRINTF_MT, already on main thread "- %s:%d: Second verilog $finish, exiting\n", filename, linenum); Verilated::runFlushCallbacks(); Verilated::runExitCallbacks(); exit(0); } Verilated::gotFinish(true); } #endif #ifndef VL_USER_STOP ///< Define this to override this function void vl_stop(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { Verilated::gotFinish(true); Verilated::runFlushCallbacks(); vl_fatal(filename, linenum, hier, "Verilog $stop"); } #endif #ifndef VL_USER_FATAL ///< Define this to override this function void vl_fatal(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_UNSAFE { if (false && hier) {} Verilated::gotFinish(true); if (filename && filename[0]) { // Not VL_PRINTF_MT, already on main thread VL_PRINTF("%%Error: %s:%d: %s\n", filename, linenum, msg); } else { VL_PRINTF("%%Error: %s\n", msg); } Verilated::runFlushCallbacks(); VL_PRINTF("Aborting...\n"); // Not VL_PRINTF_MT, already on main thread // Second flush in case VL_PRINTF does something needing a flush Verilated::runFlushCallbacks(); // Callbacks prior to termination Verilated::runExitCallbacks(); abort(); } #endif #ifndef VL_USER_STOP_MAYBE ///< Define this to override this function void vl_stop_maybe(const char* filename, int linenum, const char* hier, bool maybe) VL_MT_UNSAFE { Verilated::errorCountInc(); if (maybe && Verilated::errorCount() < Verilated::errorLimit()) { VL_PRINTF( // Not VL_PRINTF_MT, already on main thread "-Info: %s:%d: %s\n", filename, linenum, "Verilog $stop, ignored due to +verilator+error+limit"); } else { vl_stop(filename, linenum, hier); } } #endif //=========================================================================== // Wrapper to call certain functions via messages when multithreaded void VL_FINISH_MT(const char* filename, int linenum, const char* hier) VL_MT_SAFE { #ifdef VL_THREADED VerilatedThreadMsgQueue::post(VerilatedMsg([=]() { // vl_finish(filename, linenum, hier); })); #else vl_finish(filename, linenum, hier); #endif } void VL_STOP_MT(const char* filename, int linenum, const char* hier, bool maybe) VL_MT_SAFE { #ifdef VL_THREADED VerilatedThreadMsgQueue::post(VerilatedMsg([=]() { // vl_stop_maybe(filename, linenum, hier, maybe); })); #else vl_stop_maybe(filename, linenum, hier, maybe); #endif } void VL_FATAL_MT(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_SAFE { #ifdef VL_THREADED VerilatedThreadMsgQueue::post(VerilatedMsg([=]() { // vl_fatal(filename, linenum, hier, msg); })); #else vl_fatal(filename, linenum, hier, msg); #endif } //=========================================================================== // Debug prints /// sprintf but return as string (this isn't fast, for print messages only) std::string _vl_string_vprintf(const char* formatp, va_list ap) VL_MT_SAFE { va_list aq; va_copy(aq, ap); int len = VL_VSNPRINTF(NULL, 0, formatp, aq); va_end(aq); if (VL_UNLIKELY(len < 1)) return ""; char* bufp = new char[len + 1]; VL_VSNPRINTF(bufp, len + 1, formatp, ap); std::string out = std::string(bufp, len); delete[] bufp; return out; } vluint64_t _vl_dbg_sequence_number() VL_MT_SAFE { #ifdef VL_THREADED static std::atomic sequence; #else static vluint64_t sequence = 0; #endif return ++sequence; } vluint32_t VL_THREAD_ID() VL_MT_SAFE { #ifdef VL_THREADED // Alternative is to use std::this_thread::get_id, but that returns a // hard-to-read number and is very slow static std::atomic s_nextId(0); static VL_THREAD_LOCAL vluint32_t t_myId = ++s_nextId; return t_myId; #else return 0; #endif } void VL_DBG_MSGF(const char* formatp, ...) VL_MT_SAFE { // We're still using c printf formats instead of operator<< so we can avoid the heavy // includes that otherwise would be required in every Verilated module va_list ap; va_start(ap, formatp); std::string out = _vl_string_vprintf(formatp, ap); va_end(ap); // printf("-imm-V{t%d,%" VL_PRI64 "d}%s", VL_THREAD_ID(), _vl_dbg_sequence_number(), // out.c_str()); // Using VL_PRINTF not VL_PRINTF_MT so that we can call VL_DBG_MSGF // from within the guts of the thread execution machinery (and it goes // to the screen and not into the queues we're debugging) VL_PRINTF("-V{t%u,%" VL_PRI64 "u}%s", VL_THREAD_ID(), _vl_dbg_sequence_number(), out.c_str()); } #ifdef VL_THREADED void VL_PRINTF_MT(const char* formatp, ...) VL_MT_SAFE { va_list ap; va_start(ap, formatp); std::string out = _vl_string_vprintf(formatp, ap); va_end(ap); VerilatedThreadMsgQueue::post(VerilatedMsg([=]() { // VL_PRINTF("%s", out.c_str()); })); } #endif //=========================================================================== // Overall class init Verilated::Serialized::Serialized() { s_debug = 0; s_calcUnusedSigs = false; s_gotFinish = false; s_assertOn = true; s_fatalOnVpiError = true; // retains old default behaviour s_errorCount = 0; s_errorLimit = 1; s_randReset = 0; s_randSeed = 0; s_timeunit = VL_TIME_UNIT; // Initial value until overriden by _Vconfigure s_timeprecision = VL_TIME_PRECISION; // Initial value until overriden by _Vconfigure } Verilated::NonSerialized::NonSerialized() { s_profThreadsStart = 1; s_profThreadsWindow = 2; s_profThreadsFilenamep = strdup("profile_threads.dat"); } Verilated::NonSerialized::~NonSerialized() { if (s_profThreadsFilenamep) { VL_DO_CLEAR(free(const_cast(s_profThreadsFilenamep)), s_profThreadsFilenamep = NULL); } } size_t Verilated::serialized2Size() VL_PURE { return sizeof(VerilatedImp::s_s.m_ser); } void* Verilated::serialized2Ptr() VL_MT_UNSAFE { return &VerilatedImp::s_s.m_ser; } //=========================================================================== // Random -- Mostly called at init time, so not inline. static vluint32_t vl_sys_rand32() VL_MT_UNSAFE { // Return random 32-bits using system library. // Used only to construct seed for Verilator's PNRG. #if defined(_WIN32) && !defined(__CYGWIN__) // Windows doesn't have lrand48(), although Cygwin does. return (rand() << 16) ^ rand(); #else return (lrand48() << 16) ^ lrand48(); #endif } vluint64_t vl_rand64() VL_MT_SAFE { static VerilatedMutex s_mutex; static VL_THREAD_LOCAL bool t_seeded = false; static VL_THREAD_LOCAL vluint64_t t_state[2]; if (VL_UNLIKELY(!t_seeded)) { t_seeded = true; { const VerilatedLockGuard lock(s_mutex); if (Verilated::randSeed() != 0) { t_state[0] = ((static_cast(Verilated::randSeed()) << 32) ^ (static_cast(Verilated::randSeed()))); t_state[1] = ((static_cast(Verilated::randSeed()) << 32) ^ (static_cast(Verilated::randSeed()))); } else { t_state[0] = ((static_cast(vl_sys_rand32()) << 32) ^ (static_cast(vl_sys_rand32()))); t_state[1] = ((static_cast(vl_sys_rand32()) << 32) ^ (static_cast(vl_sys_rand32()))); } // Fix state as algorithm is slow to randomize if many zeros // This causes a loss of ~ 1 bit of seed entropy, no big deal if (VL_COUNTONES_I(t_state[0]) < 10) t_state[0] = ~t_state[0]; if (VL_COUNTONES_I(t_state[1]) < 10) t_state[1] = ~t_state[1]; } } // Xoroshiro128+ algorithm vluint64_t result = t_state[0] + t_state[1]; t_state[1] ^= t_state[0]; t_state[0] = (((t_state[0] << 55) | (t_state[0] >> 9)) ^ t_state[1] ^ (t_state[1] << 14)); t_state[1] = (t_state[1] << 36) | (t_state[1] >> 28); return result; } IData VL_RANDOM_I(int obits) VL_MT_SAFE { return vl_rand64() & VL_MASK_I(obits); } QData VL_RANDOM_Q(int obits) VL_MT_SAFE { return vl_rand64() & VL_MASK_Q(obits); } // VL_RANDOM_W currently unused as $random always 32 bits, left for backwards compatibility // LCOV_EXCL_START WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp) VL_MT_SAFE { for (int i = 0; i < VL_WORDS_I(obits); ++i) { if (i < (VL_WORDS_I(obits) - 1)) { outwp[i] = vl_rand64(); } else { outwp[i] = vl_rand64() & VL_MASK_E(obits); } } return outwp; } // LCOV_EXCL_STOP IData VL_RAND_RESET_I(int obits) VL_MT_SAFE { if (Verilated::randReset() == 0) return 0; IData data = ~0; if (Verilated::randReset() != 1) { // if 2, randomize data = VL_RANDOM_I(obits); } data &= VL_MASK_I(obits); return data; } QData VL_RAND_RESET_Q(int obits) VL_MT_SAFE { if (Verilated::randReset() == 0) return 0; QData data = ~0ULL; if (Verilated::randReset() != 1) { // if 2, randomize data = VL_RANDOM_Q(obits); } data &= VL_MASK_Q(obits); return data; } WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp) VL_MT_SAFE { for (int i = 0; i < VL_WORDS_I(obits); ++i) { if (i < (VL_WORDS_I(obits) - 1)) { outwp[i] = VL_RAND_RESET_I(32); } else { outwp[i] = VL_RAND_RESET_I(32) & VL_MASK_E(obits); } } return outwp; } WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp) VL_MT_SAFE { for (int i = 0; i < VL_WORDS_I(obits); ++i) outwp[i] = 0; return outwp; } //=========================================================================== // Debug void _VL_DEBUG_PRINT_W(int lbits, WDataInP iwp) VL_MT_SAFE { VL_PRINTF_MT(" Data: w%d: ", lbits); for (int i = VL_WORDS_I(lbits) - 1; i >= 0; --i) VL_PRINTF_MT("%08x ", iwp[i]); VL_PRINTF_MT("\n"); } //=========================================================================== // Slow math WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, bool is_modulus) VL_MT_SAFE { // See Knuth Algorithm D. Computes u/v = q.r // This isn't massively tuned, as wide division is rare // for debug see V3Number version // Requires clean input int words = VL_WORDS_I(lbits); for (int i = 0; i < words; ++i) owp[i] = 0; // Find MSB and check for zero. int umsbp1 = VL_MOSTSETBITP1_W(words, lwp); // dividend int vmsbp1 = VL_MOSTSETBITP1_W(words, rwp); // divisor if (VL_UNLIKELY(vmsbp1 == 0) // rwp==0 so division by zero. Return 0. || VL_UNLIKELY(umsbp1 == 0)) { // 0/x so short circuit and return 0 return owp; } int uw = VL_WORDS_I(umsbp1); // aka "m" in the algorithm int vw = VL_WORDS_I(vmsbp1); // aka "n" in the algorithm if (vw == 1) { // Single divisor word breaks rest of algorithm vluint64_t k = 0; for (int j = uw - 1; j >= 0; --j) { vluint64_t unw64 = ((k << 32ULL) + static_cast(lwp[j])); owp[j] = unw64 / static_cast(rwp[0]); k = unw64 - static_cast(owp[j]) * static_cast(rwp[0]); } if (is_modulus) { owp[0] = k; for (int i = 1; i < words; ++i) owp[i] = 0; } return owp; } // +1 word as we may shift during normalization vluint32_t un[VL_MULS_MAX_WORDS + 1]; // Fixed size, as MSVC++ doesn't allow [words] here vluint32_t vn[VL_MULS_MAX_WORDS + 1]; // v normalized // Zero for ease of debugging and to save having to zero for shifts // Note +1 as loop will use extra word for (int i = 0; i < words + 1; ++i) { un[i] = vn[i] = 0; } // Algorithm requires divisor MSB to be set // Copy and shift to normalize divisor so MSB of vn[vw-1] is set int s = 31 - VL_BITBIT_I(vmsbp1 - 1); // shift amount (0...31) vluint32_t shift_mask = s ? 0xffffffff : 0; // otherwise >> 32 won't mask the value for (int i = vw - 1; i > 0; --i) { vn[i] = (rwp[i] << s) | (shift_mask & (rwp[i - 1] >> (32 - s))); } vn[0] = rwp[0] << s; // Copy and shift dividend by same amount; may set new upper word if (s) { un[uw] = lwp[uw - 1] >> (32 - s); } else { un[uw] = 0; } for (int i = uw - 1; i > 0; --i) { un[i] = (lwp[i] << s) | (shift_mask & (lwp[i - 1] >> (32 - s))); } un[0] = lwp[0] << s; // Main loop for (int j = uw - vw; j >= 0; --j) { // Estimate vluint64_t unw64 = (static_cast(un[j + vw]) << 32ULL | static_cast(un[j + vw - 1])); vluint64_t qhat = unw64 / static_cast(vn[vw - 1]); vluint64_t rhat = unw64 - qhat * static_cast(vn[vw - 1]); again: if (qhat >= 0x100000000ULL || ((qhat * vn[vw - 2]) > ((rhat << 32ULL) + un[j + vw - 2]))) { qhat = qhat - 1; rhat = rhat + vn[vw - 1]; if (rhat < 0x100000000ULL) goto again; } vlsint64_t t = 0; // Must be signed vluint64_t k = 0; for (int i = 0; i < vw; ++i) { vluint64_t p = qhat * vn[i]; // Multiply by estimate t = un[i + j] - k - (p & 0xFFFFFFFFULL); // Subtract un[i + j] = t; k = (p >> 32ULL) - (t >> 32ULL); } t = un[j + vw] - k; un[j + vw] = t; owp[j] = qhat; // Save quotient digit if (t < 0) { // Over subtracted; correct by adding back owp[j]--; k = 0; for (int i = 0; i < vw; ++i) { t = static_cast(un[i + j]) + static_cast(vn[i]) + k; un[i + j] = t; k = t >> 32ULL; } un[j + vw] = un[j + vw] + k; } } if (is_modulus) { // modulus // Need to reverse normalization on copy to output for (int i = 0; i < vw; ++i) { owp[i] = (un[i] >> s) | (shift_mask & (un[i + 1] << (32 - s))); } for (int i = vw; i < words; ++i) owp[i] = 0; return owp; } else { // division return owp; } } WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { // obits==lbits, rbits can be different owp[0] = 1; for (int i = 1; i < VL_WORDS_I(obits); i++) owp[i] = 0; // cppcheck-suppress variableScope WData powstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here WData lastpowstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here WData lastoutstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here // cppcheck-suppress variableScope VL_ASSIGN_W(obits, powstore, lwp); for (int bit = 0; bit < rbits; bit++) { if (bit > 0) { // power = power*power VL_ASSIGN_W(obits, lastpowstore, powstore); VL_MUL_W(VL_WORDS_I(obits), powstore, lastpowstore, lastpowstore); } if (VL_BITISSET_W(rwp, bit)) { // out *= power VL_ASSIGN_W(obits, lastoutstore, owp); VL_MUL_W(VL_WORDS_I(obits), owp, lastoutstore, powstore); } } return owp; } WDataOutP VL_POW_WWQ(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, QData rhs) VL_MT_SAFE { WData rhsw[VL_WQ_WORDS_E]; VL_SET_WQ(rhsw, rhs); return VL_POW_WWW(obits, lbits, rbits, owp, lwp, rhsw); } QData VL_POW_QQW(int, int, int rbits, QData lhs, WDataInP rwp) VL_MT_SAFE { // Skip check for rhs == 0, as short-circuit doesn't save time if (VL_UNLIKELY(lhs == 0)) return 0; QData power = lhs; QData out = 1ULL; for (int bit = 0; bit < rbits; ++bit) { if (bit > 0) power = power * power; if (VL_BITISSET_W(rwp, bit)) out *= power; } return out; } WDataOutP VL_POWSS_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, bool lsign, bool rsign) VL_MT_SAFE { // obits==lbits, rbits can be different if (rsign && VL_SIGN_W(rbits, rwp)) { int words = VL_WORDS_I(obits); VL_ZERO_W(obits, owp); EData lor = 0; // 0=all zeros, ~0=all ones, else mix for (int i = 1; i < (words - 1); ++i) { lor |= lwp[i]; } lor |= ((lwp[words - 1] == VL_MASK_E(rbits)) ? ~VL_EUL(0) : 0); if (lor == 0 && lwp[0] == 0) { // "X" so return 0 return owp; } else if (lor == 0 && lwp[0] == 1) { // 1 owp[0] = 1; return owp; } else if (lsign && lor == ~VL_EUL(0) && lwp[0] == ~VL_EUL(0)) { // -1 if (rwp[0] & 1) { // -1^odd=-1 return VL_ALLONES_W(obits, owp); } else { // -1^even=1 owp[0] = 1; return owp; } } return 0; } return VL_POW_WWW(obits, rbits, rbits, owp, lwp, rwp); } WDataOutP VL_POWSS_WWQ(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, QData rhs, bool lsign, bool rsign) VL_MT_SAFE { WData rhsw[VL_WQ_WORDS_E]; VL_SET_WQ(rhsw, rhs); return VL_POWSS_WWW(obits, lbits, rbits, owp, lwp, rhsw, lsign, rsign); } QData VL_POWSS_QQW(int obits, int, int rbits, QData lhs, WDataInP rwp, bool lsign, bool rsign) VL_MT_SAFE { // Skip check for rhs == 0, as short-circuit doesn't save time if (rsign && VL_SIGN_W(rbits, rwp)) { if (lhs == 0) { return 0; // "X" } else if (lhs == 1) { return 1; } else if (lsign && lhs == VL_MASK_Q(obits)) { // -1 if (rwp[0] & 1) { return VL_MASK_Q(obits); // -1^odd=-1 } else { return 1; // -1^even=1 } } return 0; } return VL_POW_QQW(obits, rbits, rbits, lhs, rwp); } //=========================================================================== // Formatting /// Output a string representation of a wide number std::string VL_DECIMAL_NW(int width, WDataInP lwp) VL_MT_SAFE { int maxdecwidth = (width + 3) * 4 / 3; // Or (maxdecwidth+7)/8], but can't have more than 4 BCD bits per word WData bcd[VL_VALUE_STRING_MAX_WIDTH / 4 + 2]; VL_ZERO_RESET_W(maxdecwidth, bcd); WData tmp[VL_VALUE_STRING_MAX_WIDTH / 4 + 2]; WData tmp2[VL_VALUE_STRING_MAX_WIDTH / 4 + 2]; int from_bit = width - 1; // Skip all leading zeros for (; from_bit >= 0 && !(VL_BITRSHIFT_W(lwp, from_bit) & 1); --from_bit) {} // Double-dabble algorithm for (; from_bit >= 0; --from_bit) { // Any digits >= 5 need an add 3 (via tmp) for (int nibble_bit = 0; nibble_bit < maxdecwidth; nibble_bit += 4) { if ((VL_BITRSHIFT_W(bcd, nibble_bit) & 0xf) >= 5) { VL_ZERO_RESET_W(maxdecwidth, tmp2); tmp2[VL_BITWORD_E(nibble_bit)] |= VL_EUL(0x3) << VL_BITBIT_E(nibble_bit); VL_ASSIGN_W(maxdecwidth, tmp, bcd); VL_ADD_W(VL_WORDS_I(maxdecwidth), bcd, tmp, tmp2); } } // Shift; bcd = bcd << 1 VL_ASSIGN_W(maxdecwidth, tmp, bcd); VL_SHIFTL_WWI(maxdecwidth, maxdecwidth, 32, bcd, tmp, 1); // bcd[0] = lwp[from_bit] if (VL_BITISSET_W(lwp, from_bit)) bcd[0] |= 1; } std::string output; int lsb = (maxdecwidth - 1) & ~3; for (; lsb > 0; lsb -= 4) { // Skip leading zeros if (VL_BITRSHIFT_W(bcd, lsb) & 0xf) break; } for (; lsb >= 0; lsb -= 4) { output += ('0' + (VL_BITRSHIFT_W(bcd, lsb) & 0xf)); // 0..9 } return output; } std::string _vl_vsformat_time(char* tmp, double ld, bool left, size_t width) { // Double may lose precision, but sc_time_stamp has similar limit std::string suffix = VerilatedImp::timeFormatSuffix(); int userUnits = VerilatedImp::timeFormatUnits(); // 0..-15 int fracDigits = VerilatedImp::timeFormatPrecision(); // 0..N int prec = Verilated::timeprecision(); // 0..-15 int shift = prec - userUnits + fracDigits; // 0..-15 double shiftd = vl_time_multiplier(shift); double scaled = ld * shiftd; QData fracDiv = static_cast(vl_time_multiplier(fracDigits)); QData whole = static_cast(scaled) / fracDiv; QData fraction = static_cast(scaled) % fracDiv; int digits = 0; if (!fracDigits) { digits = sprintf(tmp, "%" VL_PRI64 "u%s", whole, suffix.c_str()); } else { digits = sprintf(tmp, "%" VL_PRI64 "u.%0*" VL_PRI64 "u%s", whole, fracDigits, fraction, suffix.c_str()); } int needmore = width - digits; std::string padding; if (needmore > 0) padding.append(needmore, ' '); // Pad with spaces return left ? (tmp + padding) : (padding + tmp); } // Do a va_arg returning a quad, assuming input argument is anything less than wide #define _VL_VA_ARG_Q(ap, bits) (((bits) <= VL_IDATASIZE) ? va_arg(ap, IData) : va_arg(ap, QData)) void _vl_vsformat(std::string& output, const char* formatp, va_list ap) VL_MT_SAFE { // Format a Verilog $write style format into the output list // The format must be pre-processed (and lower cased) by Verilator // Arguments are in "width, arg-value (or WDataIn* if wide)" form // // Note uses a single buffer internally; presumes only one usage per printf // Note also assumes variables < 64 are not wide, this assumption is // sometimes not true in low-level routines written here in verilated.cpp static VL_THREAD_LOCAL char tmp[VL_VALUE_STRING_MAX_WIDTH]; const char* pctp = NULL; // Most recent %##.##g format bool inPct = false; bool widthSet = false; bool left = false; size_t width = 0; for (const char* pos = formatp; *pos; ++pos) { if (!inPct && pos[0] == '%') { pctp = pos; inPct = true; widthSet = false; width = 0; } else if (!inPct) { // Normal text // Fast-forward to next escape and add to output const char* ep = pos; while (ep[0] && ep[0] != '%') ep++; if (ep != pos) { output.append(pos, ep - pos); pos += ep - pos - 1; } } else { // Format character inPct = false; char fmt = pos[0]; switch (fmt) { case '0': // FALLTHRU case '1': // FALLTHRU case '2': // FALLTHRU case '3': // FALLTHRU case '4': // FALLTHRU case '5': // FALLTHRU case '6': // FALLTHRU case '7': // FALLTHRU case '8': // FALLTHRU case '9': inPct = true; // Get more digits widthSet = true; width = width * 10 + (fmt - '0'); break; case '-': left = true; inPct = true; // Get more digits break; case '.': inPct = true; // Get more digits break; case '%': // output += '%'; break; case 'N': { // "C" string with name of module, add . if needed const char* cstrp = va_arg(ap, const char*); if (VL_LIKELY(*cstrp)) { output += cstrp; output += '.'; } break; } case 'S': { // "C" string const char* cstrp = va_arg(ap, const char*); output += cstrp; break; } case '@': { // Verilog/C++ string va_arg(ap, int); // # bits is ignored const std::string* cstrp = va_arg(ap, const std::string*); std::string padding; if (width > cstrp->size()) padding.append(width - cstrp->size(), ' '); output += left ? (*cstrp + padding) : (padding + *cstrp); break; } case 'e': case 'f': case 'g': case '^': { // Realtime const int lbits = va_arg(ap, int); double d = va_arg(ap, double); if (lbits) {} // UNUSED - always 64 if (fmt == '^') { // Realtime if (!widthSet) width = VerilatedImp::timeFormatWidth(); output += _vl_vsformat_time(tmp, d, left, width); } else { std::string fmt(pctp, pos - pctp + 1); sprintf(tmp, fmt.c_str(), d); output += tmp; } break; } default: { // Deal with all read-and-print somethings const int lbits = va_arg(ap, int); QData ld = 0; WData qlwp[VL_WQ_WORDS_E]; WDataInP lwp = NULL; if (lbits <= VL_QUADSIZE) { ld = _VL_VA_ARG_Q(ap, lbits); VL_SET_WQ(qlwp, ld); lwp = qlwp; } else { lwp = va_arg(ap, WDataInP); ld = lwp[0]; } int lsb = lbits - 1; if (widthSet && width == 0) { while (lsb && !VL_BITISSET_W(lwp, lsb)) --lsb; } switch (fmt) { case 'c': { IData charval = ld & 0xff; output += static_cast(charval); break; } case 's': { std::string field; for (; lsb >= 0; --lsb) { lsb = (lsb / 8) * 8; // Next digit IData charval = VL_BITRSHIFT_W(lwp, lsb) & 0xff; field += (charval == 0) ? ' ' : charval; } std::string padding; if (width > field.size()) padding.append(width - field.size(), ' '); output += left ? (field + padding) : (padding + field); break; } case 'd': { // Signed decimal int digits = 0; std::string append; if (lbits <= VL_QUADSIZE) { digits = sprintf(tmp, "%" VL_PRI64 "d", static_cast(VL_EXTENDS_QQ(lbits, lbits, ld))); append = tmp; } else { if (VL_SIGN_E(lbits, lwp[VL_WORDS_I(lbits) - 1])) { WData neg[VL_VALUE_STRING_MAX_WIDTH / 4 + 2]; VL_NEGATE_W(VL_WORDS_I(lbits), neg, lwp); append = std::string("-") + VL_DECIMAL_NW(lbits, neg); } else { append = VL_DECIMAL_NW(lbits, lwp); } digits = append.length(); } int needmore = width - digits; std::string padding; if (needmore > 0) { if (pctp && pctp[0] && pctp[1] == '0') { // %0 padding.append(needmore, '0'); // Pre-pad zero } else { padding.append(needmore, ' '); // Pre-pad spaces } } output += left ? (append + padding) : (padding + append); break; } case '#': { // Unsigned decimal int digits = 0; std::string append; if (lbits <= VL_QUADSIZE) { digits = sprintf(tmp, "%" VL_PRI64 "u", ld); append = tmp; } else { append = VL_DECIMAL_NW(lbits, lwp); digits = append.length(); } int needmore = width - digits; std::string padding; if (needmore > 0) { if (pctp && pctp[0] && pctp[1] == '0') { // %0 padding.append(needmore, '0'); // Pre-pad zero } else { padding.append(needmore, ' '); // Pre-pad spaces } } output += left ? (append + padding) : (padding + append); break; } case 't': { // Time if (!widthSet) width = VerilatedImp::timeFormatWidth(); output += _vl_vsformat_time(tmp, static_cast(ld), left, width); break; } case 'b': for (; lsb >= 0; --lsb) output += (VL_BITRSHIFT_W(lwp, lsb) & 1) + '0'; break; case 'o': for (; lsb >= 0; --lsb) { lsb = (lsb / 3) * 3; // Next digit // Octal numbers may span more than one wide word, // so we need to grab each bit separately and check for overrun // Octal is rare, so we'll do it a slow simple way output += static_cast( '0' + ((VL_BITISSETLIMIT_W(lwp, lbits, lsb + 0)) ? 1 : 0) + ((VL_BITISSETLIMIT_W(lwp, lbits, lsb + 1)) ? 2 : 0) + ((VL_BITISSETLIMIT_W(lwp, lbits, lsb + 2)) ? 4 : 0)); } break; case 'u': case 'z': { // Packed 4-state const bool is_4_state = (fmt == 'z'); output.reserve(output.size() + ((is_4_state ? 2 : 1) * VL_WORDS_I(lbits))); int bytes_to_go = VL_BYTES_I(lbits); int bit = 0; while (bytes_to_go > 0) { const int wr_bytes = std::min(4, bytes_to_go); for (int byte = 0; byte < wr_bytes; byte++, bit += 8) output += static_cast(VL_BITRSHIFT_W(lwp, bit) & 0xff); output.append(4 - wr_bytes, static_cast(0)); if (is_4_state) output.append(4, static_cast(0)); bytes_to_go -= wr_bytes; } break; } case 'v': // Strength; assume always strong for (lsb = lbits - 1; lsb >= 0; --lsb) { if (VL_BITRSHIFT_W(lwp, lsb) & 1) { output += "St1 "; } else { output += "St0 "; } } break; case 'x': for (; lsb >= 0; --lsb) { lsb = (lsb / 4) * 4; // Next digit IData charval = VL_BITRSHIFT_W(lwp, lsb) & 0xf; output += "0123456789abcdef"[charval]; } break; default: std::string msg = std::string("Unknown _vl_vsformat code: ") + pos[0]; VL_FATAL_MT(__FILE__, __LINE__, "", msg.c_str()); break; } // switch } } // switch } } } static inline bool _vl_vsss_eof(FILE* fp, int floc) VL_MT_SAFE { if (fp) { return feof(fp) ? true : false; // true : false to prevent MSVC++ warning } else { return floc < 0; } } static inline void _vl_vsss_advance(FILE* fp, int& floc) VL_MT_SAFE { if (fp) { fgetc(fp); } else { floc -= 8; } } static inline int _vl_vsss_peek(FILE* fp, int& floc, WDataInP fromp, const std::string& fstr) VL_MT_SAFE { // Get a character without advancing if (fp) { int data = fgetc(fp); if (data == EOF) return EOF; ungetc(data, fp); return data; } else { if (floc < 0) return EOF; floc = floc & ~7; // Align to closest character if (fromp == NULL) { return fstr[fstr.length() - 1 - (floc >> 3)]; } else { return VL_BITRSHIFT_W(fromp, floc) & 0xff; } } } static inline void _vl_vsss_skipspace(FILE* fp, int& floc, WDataInP fromp, const std::string& fstr) VL_MT_SAFE { while (true) { int c = _vl_vsss_peek(fp, floc, fromp, fstr); if (c == EOF || !isspace(c)) return; _vl_vsss_advance(fp, floc); } } static inline void _vl_vsss_read_str(FILE* fp, int& floc, WDataInP fromp, const std::string& fstr, char* tmpp, const char* acceptp) VL_MT_SAFE { // Read into tmp, consisting of characters from acceptp list char* cp = tmpp; while (true) { int c = _vl_vsss_peek(fp, floc, fromp, fstr); if (c == EOF || isspace(c)) break; if (acceptp && NULL == strchr(acceptp, c)) break; // String - allow anything if (acceptp) c = tolower(c); // Non-strings we'll simplify *cp++ = c; _vl_vsss_advance(fp, floc); } *cp++ = '\0'; // VL_DBG_MSGF(" _read got='"< 0) { const int c = _vl_vsss_peek(fp, floc, fromp, fstr); if (c == EOF) return NULL; if (!inhibit) *beginp++ = c; _vl_vsss_advance(fp, floc); } return beginp; } static inline void _vl_vsss_setbit(WDataOutP owp, int obits, int lsb, int nbits, IData ld) VL_MT_SAFE { for (; nbits && lsb < obits; nbits--, lsb++, ld >>= 1) { VL_ASSIGNBIT_WI(0, lsb, owp, ld & 1); } } static inline void _vl_vsss_based(WDataOutP owp, int obits, int baseLog2, const char* strp, size_t posstart, size_t posend) VL_MT_SAFE { // Read in base "2^^baseLog2" digits from strp[posstart..posend-1] into owp of size obits. int lsb = 0; for (int i = 0, pos = static_cast(posend) - 1; i < obits && pos >= static_cast(posstart); --pos) { // clang-format off switch (tolower (strp[pos])) { case 'x': case 'z': case '?': // FALLTHRU case '0': lsb += baseLog2; break; case '1': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 1); lsb += baseLog2; break; case '2': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 2); lsb += baseLog2; break; case '3': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 3); lsb += baseLog2; break; case '4': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 4); lsb += baseLog2; break; case '5': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 5); lsb += baseLog2; break; case '6': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 6); lsb += baseLog2; break; case '7': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 7); lsb += baseLog2; break; case '8': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 8); lsb += baseLog2; break; case '9': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 9); lsb += baseLog2; break; case 'a': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 10); lsb += baseLog2; break; case 'b': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 11); lsb += baseLog2; break; case 'c': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 12); lsb += baseLog2; break; case 'd': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 13); lsb += baseLog2; break; case 'e': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 14); lsb += baseLog2; break; case 'f': _vl_vsss_setbit(owp, obits, lsb, baseLog2, 15); lsb += baseLog2; break; case '_': break; } // clang-format on } } IData _vl_vsscanf(FILE* fp, // If a fscanf int fbits, WDataInP fromp, // Else if a sscanf const std::string& fstr, // if a sscanf to string const char* formatp, va_list ap) VL_MT_SAFE { // Read a Verilog $sscanf/$fscanf style format into the output list // The format must be pre-processed (and lower cased) by Verilator // Arguments are in "width, arg-value (or WDataIn* if wide)" form static VL_THREAD_LOCAL char tmp[VL_VALUE_STRING_MAX_WIDTH]; int floc = fbits - 1; IData got = 0; bool inPct = false; bool inIgnore = false; const char* pos = formatp; for (; *pos && !_vl_vsss_eof(fp, floc); ++pos) { // VL_DBG_MSGF("_vlscan fmt='"< VL_QUADSIZE) owp = va_arg(ap, WDataOutP); for (int i = 0; i < VL_WORDS_I(obits); ++i) owp[i] = 0; switch (fmt) { case 'c': { int c = _vl_vsss_peek(fp, floc, fromp, fstr); if (c == EOF) goto done; _vl_vsss_advance(fp, floc); owp[0] = c; break; } case 's': { _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, tmp, NULL); if (!tmp[0]) goto done; int lpos = (static_cast(strlen(tmp))) - 1; int lsb = 0; for (int i = 0; i < obits && lpos >= 0; --lpos) { _vl_vsss_setbit(owp, obits, lsb, 8, tmp[lpos]); lsb += 8; } break; } case 'd': { // Signed decimal _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, tmp, "0123456789+-xXzZ?_"); if (!tmp[0]) goto done; vlsint64_t ld = 0; sscanf(tmp, "%30" VL_PRI64 "d", &ld); VL_SET_WQ(owp, ld); break; } case 'f': case 'e': case 'g': { // Real number _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, tmp, "+-.0123456789eE"); if (!tmp[0]) goto done; // cppcheck-suppress unusedStructMember // It's used union { double r; vlsint64_t ld; } u; u.r = strtod(tmp, NULL); VL_SET_WQ(owp, u.ld); break; } case 't': // FALLTHRU // Time case '#': { // Unsigned decimal _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, tmp, "0123456789+-xXzZ?_"); if (!tmp[0]) goto done; QData ld = 0; sscanf(tmp, "%30" VL_PRI64 "u", &ld); VL_SET_WQ(owp, ld); break; } case 'b': { _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, tmp, "01xXzZ?_"); if (!tmp[0]) goto done; _vl_vsss_based(owp, obits, 1, tmp, 0, strlen(tmp)); break; } case 'o': { _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, tmp, "01234567xXzZ?_"); if (!tmp[0]) goto done; _vl_vsss_based(owp, obits, 3, tmp, 0, strlen(tmp)); break; } case 'x': { _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, tmp, "0123456789abcdefABCDEFxXzZ?_"); if (!tmp[0]) goto done; _vl_vsss_based(owp, obits, 4, tmp, 0, strlen(tmp)); break; } case 'u': { // Read packed 2-value binary data const int bytes = VL_BYTES_I(obits); char* out = reinterpret_cast(owp); if (!_vl_vsss_read_bin(fp, floc, fromp, fstr, out, bytes)) goto done; const int last = bytes % 4; if (last != 0 && !_vl_vsss_read_bin(fp, floc, fromp, fstr, out, 4 - last, true)) goto done; break; } case 'z': { // Read packed 4-value binary data char* out = reinterpret_cast(owp); int bytes = VL_BYTES_I(obits); while (bytes > 0) { const int abytes = std::min(4, bytes); // aval (4B) read {0, 1} state out = _vl_vsss_read_bin(fp, floc, fromp, fstr, out, abytes); if (!out) goto done; // bval (4B) disregard {X, Z} state and align to new 8B boundary. out = _vl_vsss_read_bin(fp, floc, fromp, fstr, out, 8 - abytes, true); if (!out) goto done; bytes -= abytes; } break; } default: std::string msg = std::string("Unknown _vl_vsscanf code: ") + pos[0]; VL_FATAL_MT(__FILE__, __LINE__, "", msg.c_str()); break; } // switch if (!inIgnore) ++got; // Reload data if non-wide (if wide, we put it in the right place directly) if (obits == 0) { // Due to inIgnore } else if (obits <= VL_BYTESIZE) { CData* p = va_arg(ap, CData*); *p = owp[0]; } else if (obits <= VL_SHORTSIZE) { SData* p = va_arg(ap, SData*); *p = owp[0]; } else if (obits <= VL_IDATASIZE) { IData* p = va_arg(ap, IData*); *p = owp[0]; } else if (obits <= VL_QUADSIZE) { QData* p = va_arg(ap, QData*); *p = VL_SET_QW(owp); } } } // switch } } done: return got; } //=========================================================================== // File I/O FILE* VL_CVT_I_FP(IData lhs) VL_MT_SAFE { // Expected non-MCD case; returns null on MCD descriptors. return VerilatedImp::fdToFp(lhs); } void _VL_VINT_TO_STRING(int obits, char* destoutp, WDataInP sourcep) VL_MT_SAFE { // See also VL_DATA_TO_STRING_NW int lsb = obits - 1; bool start = true; char* destp = destoutp; for (; lsb >= 0; --lsb) { lsb = (lsb / 8) * 8; // Next digit IData charval = VL_BITRSHIFT_W(sourcep, lsb) & 0xff; if (!start || charval) { *destp++ = (charval == 0) ? ' ' : charval; start = false; // Drop leading 0s } } *destp = '\0'; // Terminate if (!start) { // Drop trailing spaces while (isspace(*(destp - 1)) && destp > destoutp) *--destp = '\0'; } } void _VL_STRING_TO_VINT(int obits, void* destp, size_t srclen, const char* srcp) VL_MT_SAFE { // Convert C string to Verilog format size_t bytes = VL_BYTES_I(obits); char* op = reinterpret_cast(destp); if (srclen > bytes) srclen = bytes; // Don't overflow destination size_t i = 0; for (i = 0; i < srclen; ++i) { *op++ = srcp[srclen - 1 - i]; } for (; i < bytes; ++i) { *op++ = 0; } } IData VL_FGETS_IXI(int obits, void* destp, IData fpi) VL_MT_SAFE { // While threadsafe, each thread can only access different file handles FILE* fp = VL_CVT_I_FP(fpi); if (VL_UNLIKELY(!fp)) return 0; // The string needs to be padded with 0's in unused spaces in front of // any read data. This means we can't know in what location the first // character will finally live, so we need to copy. Yuk. IData bytes = VL_BYTES_I(obits); char buffer[VL_TO_STRING_MAX_WORDS * VL_EDATASIZE + 1]; // V3Emit has static check that bytes < VL_TO_STRING_MAX_WORDS, but be safe if (VL_UNCOVERABLE(bytes > VL_TO_STRING_MAX_WORDS * VL_EDATASIZE)) { VL_FATAL_MT(__FILE__, __LINE__, "", "Internal: fgets buffer overrun"); // LCOV_EXCL_LINE } // We don't use fgets, as we must read \0s. IData got = 0; char* cp = buffer; while (got < bytes) { int c = getc(fp); // getc() is threadsafe if (c == EOF) break; *cp++ = c; got++; if (c == '\n') break; } _VL_STRING_TO_VINT(obits, destp, got, buffer); return got; } IData VL_FERROR_IN(IData, std::string& outputr) VL_MT_SAFE { // We ignore lhs/fpi - IEEE says "most recent error" so probably good enough IData ret = errno; outputr = std::string(::strerror(ret)); return ret; } IData VL_FOPEN_NN(const std::string& filename, const std::string& mode) { return VerilatedImp::fdNew(filename.c_str(), mode.c_str()); } IData VL_FOPEN_MCD_N(const std::string& filename) VL_MT_SAFE { return VerilatedImp::fdNewMcd(filename.c_str()); } void VL_FFLUSH_I(IData fdi) VL_MT_SAFE { VerilatedImp::fdFlush(fdi); } IData VL_FSEEK_I(IData fdi, IData offset, IData origin) VL_MT_SAFE { return VerilatedImp::fdSeek(fdi, offset, origin); } IData VL_FTELL_I(IData fdi) VL_MT_SAFE { return VerilatedImp::fdTell(fdi); } void VL_FCLOSE_I(IData fdi) VL_MT_SAFE { // While threadsafe, each thread can only access different file handles VerilatedImp::fdClose(fdi); } void VL_FFLUSH_ALL() VL_MT_SAFE { fflush(stdout); } void VL_SFORMAT_X(int obits, CData& destr, const char* formatp, ...) VL_MT_SAFE { static VL_THREAD_LOCAL std::string output; // static only for speed output = ""; va_list ap; va_start(ap, formatp); _vl_vsformat(output, formatp, ap); va_end(ap); _VL_STRING_TO_VINT(obits, &destr, output.length(), output.c_str()); } void VL_SFORMAT_X(int obits, SData& destr, const char* formatp, ...) VL_MT_SAFE { static VL_THREAD_LOCAL std::string output; // static only for speed output = ""; va_list ap; va_start(ap, formatp); _vl_vsformat(output, formatp, ap); va_end(ap); _VL_STRING_TO_VINT(obits, &destr, output.length(), output.c_str()); } void VL_SFORMAT_X(int obits, IData& destr, const char* formatp, ...) VL_MT_SAFE { static VL_THREAD_LOCAL std::string output; // static only for speed output = ""; va_list ap; va_start(ap, formatp); _vl_vsformat(output, formatp, ap); va_end(ap); _VL_STRING_TO_VINT(obits, &destr, output.length(), output.c_str()); } void VL_SFORMAT_X(int obits, QData& destr, const char* formatp, ...) VL_MT_SAFE { static VL_THREAD_LOCAL std::string output; // static only for speed output = ""; va_list ap; va_start(ap, formatp); _vl_vsformat(output, formatp, ap); va_end(ap); _VL_STRING_TO_VINT(obits, &destr, output.length(), output.c_str()); } void VL_SFORMAT_X(int obits, void* destp, const char* formatp, ...) VL_MT_SAFE { static VL_THREAD_LOCAL std::string output; // static only for speed output = ""; va_list ap; va_start(ap, formatp); _vl_vsformat(output, formatp, ap); va_end(ap); _VL_STRING_TO_VINT(obits, destp, output.length(), output.c_str()); } void VL_SFORMAT_X(int obits_ignored, std::string& output, const char* formatp, ...) VL_MT_SAFE { if (obits_ignored) {} output = ""; va_list ap; va_start(ap, formatp); _vl_vsformat(output, formatp, ap); va_end(ap); } std::string VL_SFORMATF_NX(const char* formatp, ...) VL_MT_SAFE { static VL_THREAD_LOCAL std::string output; // static only for speed output = ""; va_list ap; va_start(ap, formatp); _vl_vsformat(output, formatp, ap); va_end(ap); return output; } void VL_WRITEF(const char* formatp, ...) VL_MT_SAFE { static VL_THREAD_LOCAL std::string output; // static only for speed output = ""; va_list ap; va_start(ap, formatp); _vl_vsformat(output, formatp, ap); va_end(ap); VL_PRINTF_MT("%s", output.c_str()); } void VL_FWRITEF(IData fpi, const char* formatp, ...) VL_MT_SAFE { // While threadsafe, each thread can only access different file handles static VL_THREAD_LOCAL std::string output; // static only for speed output = ""; va_list ap; va_start(ap, formatp); _vl_vsformat(output, formatp, ap); va_end(ap); VerilatedImp::fdWrite(fpi, output); } IData VL_FSCANF_IX(IData fpi, const char* formatp, ...) VL_MT_SAFE { // While threadsafe, each thread can only access different file handles FILE* fp = VL_CVT_I_FP(fpi); if (VL_UNLIKELY(!fp)) return 0; va_list ap; va_start(ap, formatp); IData got = _vl_vsscanf(fp, 0, NULL, "", formatp, ap); va_end(ap); return got; } IData VL_SSCANF_IIX(int lbits, IData ld, const char* formatp, ...) VL_MT_SAFE { WData fnw[VL_WQ_WORDS_E]; VL_SET_WI(fnw, ld); va_list ap; va_start(ap, formatp); IData got = _vl_vsscanf(NULL, lbits, fnw, "", formatp, ap); va_end(ap); return got; } IData VL_SSCANF_IQX(int lbits, QData ld, const char* formatp, ...) VL_MT_SAFE { WData fnw[VL_WQ_WORDS_E]; VL_SET_WQ(fnw, ld); va_list ap; va_start(ap, formatp); IData got = _vl_vsscanf(NULL, lbits, fnw, "", formatp, ap); va_end(ap); return got; } IData VL_SSCANF_IWX(int lbits, WDataInP lwp, const char* formatp, ...) VL_MT_SAFE { va_list ap; va_start(ap, formatp); IData got = _vl_vsscanf(NULL, lbits, lwp, "", formatp, ap); va_end(ap); return got; } IData VL_SSCANF_INX(int, const std::string& ld, const char* formatp, ...) VL_MT_SAFE { va_list ap; va_start(ap, formatp); IData got = _vl_vsscanf(NULL, ld.length() * 8, NULL, ld, formatp, ap); va_end(ap); return got; } IData VL_FREAD_I(int width, int array_lsb, int array_size, void* memp, IData fpi, IData start, IData count) VL_MT_SAFE { // While threadsafe, each thread can only access different file handles FILE* fp = VL_CVT_I_FP(fpi); if (VL_UNLIKELY(!fp)) return 0; if (count > (array_size - (start - array_lsb))) count = array_size - (start - array_lsb); // Prep for reading IData read_count = 0; IData read_elements = 0; int start_shift = (width - 1) & ~7; // bit+7:bit gets first character int shift = start_shift; // Read the data // We process a character at a time, as then we don't need to deal // with changing buffer sizes dynamically, etc. while (true) { int c = fgetc(fp); if (VL_UNLIKELY(c == EOF)) break; // Shift value in IData entry = read_elements + start - array_lsb; if (width <= 8) { CData* datap = &(reinterpret_cast(memp))[entry]; if (shift == start_shift) { *datap = 0; } *datap |= (c << shift) & VL_MASK_I(width); } else if (width <= 16) { SData* datap = &(reinterpret_cast(memp))[entry]; if (shift == start_shift) { *datap = 0; } *datap |= (c << shift) & VL_MASK_I(width); } else if (width <= VL_IDATASIZE) { IData* datap = &(reinterpret_cast(memp))[entry]; if (shift == start_shift) { *datap = 0; } *datap |= (c << shift) & VL_MASK_I(width); } else if (width <= VL_QUADSIZE) { QData* datap = &(reinterpret_cast(memp))[entry]; if (shift == start_shift) { *datap = 0; } *datap |= ((static_cast(c) << static_cast(shift)) & VL_MASK_Q(width)); } else { WDataOutP datap = &(reinterpret_cast(memp))[entry * VL_WORDS_I(width)]; if (shift == start_shift) VL_ZERO_RESET_W(width, datap); datap[VL_BITWORD_E(shift)] |= (static_cast(c) << VL_BITBIT_E(shift)); } // Prep for next ++read_count; shift -= 8; if (shift < 0) { shift = start_shift; ++read_elements; if (VL_UNLIKELY(read_elements >= count)) break; } } return read_count; } IData VL_SYSTEM_IQ(QData lhs) VL_MT_SAFE { WData lhsw[VL_WQ_WORDS_E]; VL_SET_WQ(lhsw, lhs); return VL_SYSTEM_IW(VL_WQ_WORDS_E, lhsw); } IData VL_SYSTEM_IW(int lhswords, WDataInP lhsp) VL_MT_SAFE { char filenamez[VL_TO_STRING_MAX_WORDS * VL_EDATASIZE + 1]; _VL_VINT_TO_STRING(lhswords * VL_EDATASIZE, filenamez, lhsp); int code = system(filenamez); // Yes, system() is threadsafe return code >> 8; // Want exit status } IData VL_TESTPLUSARGS_I(const char* formatp) VL_MT_SAFE { const std::string& match = VerilatedImp::argPlusMatch(formatp); return match.empty() ? 0 : 1; } IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_MT_SAFE { std::string prefix; bool inPct = false; bool done = false; char fmt = ' '; for (const char* posp = ld.c_str(); !done && *posp; ++posp) { if (!inPct && posp[0] == '%') { inPct = true; } else if (!inPct) { // Normal text prefix += *posp; } else { // Format character switch (tolower(*posp)) { case '%': prefix += *posp; inPct = false; break; default: fmt = *posp; done = true; break; } } } const std::string& match = VerilatedImp::argPlusMatch(prefix.c_str()); const char* dp = match.c_str() + 1 /*leading + */ + prefix.length(); if (match.empty()) return 0; VL_ZERO_RESET_W(rbits, rwp); switch (tolower(fmt)) { case 'd': { vlsint64_t lld = 0; sscanf(dp, "%30" VL_PRI64 "d", &lld); VL_SET_WQ(rwp, lld); break; } case 'b': _vl_vsss_based(rwp, rbits, 1, dp, 0, strlen(dp)); break; case 'o': _vl_vsss_based(rwp, rbits, 3, dp, 0, strlen(dp)); break; case 'h': // FALLTHRU case 'x': _vl_vsss_based(rwp, rbits, 4, dp, 0, strlen(dp)); break; case 's': { // string/no conversion for (int i = 0, lsb = 0, posp = static_cast(strlen(dp)) - 1; i < rbits && posp >= 0; --posp) { _vl_vsss_setbit(rwp, rbits, lsb, 8, dp[posp]); lsb += 8; } break; } case 'e': { double temp = 0.F; sscanf(dp, "%le", &temp); VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); break; } case 'f': { double temp = 0.F; sscanf(dp, "%lf", &temp); VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); break; } case 'g': { double temp = 0.F; sscanf(dp, "%lg", &temp); VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); break; } default: // Other simulators simply return 0 in these cases and don't error out return 0; } _VL_CLEAN_INPLACE_W(rbits, rwp); return 1; } IData VL_VALUEPLUSARGS_INN(int, const std::string& ld, std::string& rdr) VL_MT_SAFE { std::string prefix; bool inPct = false; bool done = false; for (const char* posp = ld.c_str(); !done && *posp; ++posp) { if (!inPct && posp[0] == '%') { inPct = true; } else if (!inPct) { // Normal text prefix += *posp; } else { // Format character switch (tolower(*posp)) { case '%': prefix += *posp; inPct = false; break; default: // done = true; break; } } } const std::string& match = VerilatedImp::argPlusMatch(prefix.c_str()); const char* dp = match.c_str() + 1 /*leading + */ + prefix.length(); if (match.empty()) return 0; rdr = std::string(dp); return 1; } const char* vl_mc_scan_plusargs(const char* prefixp) VL_MT_SAFE { const std::string& match = VerilatedImp::argPlusMatch(prefixp); static VL_THREAD_LOCAL char outstr[VL_VALUE_STRING_MAX_WIDTH]; if (match.empty()) return NULL; outstr[0] = '\0'; strncat(outstr, match.c_str() + strlen(prefixp) + 1, // +1 to skip the "+" VL_VALUE_STRING_MAX_WIDTH - 1); return outstr; } //=========================================================================== // Heavy string functions std::string VL_TO_STRING(CData lhs) { return VL_SFORMATF_NX("'h%0x", 8, lhs); } std::string VL_TO_STRING(SData lhs) { return VL_SFORMATF_NX("'h%0x", 16, lhs); } std::string VL_TO_STRING(IData lhs) { return VL_SFORMATF_NX("'h%0x", 32, lhs); } std::string VL_TO_STRING(QData lhs) { return VL_SFORMATF_NX("'h%0x", 64, lhs); } std::string VL_TO_STRING_W(int words, WDataInP obj) { return VL_SFORMATF_NX("'h%0x", words * VL_EDATASIZE, obj); } std::string VL_TOLOWER_NN(const std::string& ld) VL_MT_SAFE { std::string out = ld; for (std::string::iterator it = out.begin(); it != out.end(); ++it) *it = tolower(*it); return out; } std::string VL_TOUPPER_NN(const std::string& ld) VL_MT_SAFE { std::string out = ld; for (std::string::iterator it = out.begin(); it != out.end(); ++it) *it = toupper(*it); return out; } std::string VL_CVT_PACK_STR_NW(int lwords, WDataInP lwp) VL_MT_SAFE { // See also _VL_VINT_TO_STRING char destout[VL_TO_STRING_MAX_WORDS * VL_EDATASIZE + 1]; int obits = lwords * VL_EDATASIZE; int lsb = obits - 1; bool start = true; char* destp = destout; int len = 0; for (; lsb >= 0; --lsb) { lsb = (lsb / 8) * 8; // Next digit IData charval = VL_BITRSHIFT_W(lwp, lsb) & 0xff; if (!start || charval) { *destp++ = (charval == 0) ? ' ' : charval; len++; start = false; // Drop leading 0s } } return std::string(destout, len); } std::string VL_PUTC_N(const std::string& lhs, IData rhs, CData ths) VL_PURE { std::string lstring = lhs; const vlsint32_t rhs_s = rhs; // To signed value // 6.16.2:str.putc(i, c) does not change the value when i < 0 || i >= str.len() || c == 0 if (0 <= rhs_s && rhs < lhs.length() && ths != 0) lstring[rhs] = ths; return lstring; } CData VL_GETC_N(const std::string& lhs, IData rhs) VL_PURE { CData v = 0; const vlsint32_t rhs_s = rhs; // To signed value // 6.16.3:str.getc(i) returns 0 if i < 0 || i >= str.len() if (0 <= rhs_s && rhs < lhs.length()) v = lhs[rhs]; return v; } std::string VL_SUBSTR_N(const std::string& lhs, IData rhs, IData ths) VL_PURE { const vlsint32_t rhs_s = rhs; // To signed value const vlsint32_t ths_s = ths; // To signed value // 6.16.8:str.substr(i, j) returns an empty string when i < 0 || j < i || j >= str.len() if (rhs_s < 0 || ths_s < rhs_s || ths >= lhs.length()) return ""; // Second parameter of std::string::substr(i, n) is length, not position as in SystemVerilog return lhs.substr(rhs, ths - rhs + 1); } IData VL_ATOI_N(const std::string& str, int base) VL_PURE { std::string str_mod = str; // IEEE 1800-2017 6.16.9 says '_' may exist. str_mod.erase(std::remove(str_mod.begin(), str_mod.end(), '_'), str_mod.end()); errno = 0; long v = std::strtol(str_mod.c_str(), NULL, base); if (errno != 0) v = 0; return static_cast(v); } //=========================================================================== // Dumping const char* vl_dumpctl_filenamep(bool setit, const std::string& filename) VL_MT_SAFE { // This function performs both accessing and setting so it's easy to make an in-function static static VL_THREAD_LOCAL std::string t_filename; if (setit) { t_filename = filename; } else { static VL_THREAD_LOCAL bool t_warned = false; if (VL_UNLIKELY(t_filename.empty() && !t_warned)) { t_warned = true; VL_PRINTF_MT("%%Warning: $dumpvar ignored as not proceeded by $dumpfile\n"); return ""; } } return t_filename.c_str(); } //=========================================================================== // Readmem/writemem static const char* memhFormat(int nBits) { assert((nBits >= 1) && (nBits <= 32)); static VL_THREAD_LOCAL char buf[32]; switch ((nBits - 1) / 4) { case 0: VL_SNPRINTF(buf, 32, "%%01x"); break; case 1: VL_SNPRINTF(buf, 32, "%%02x"); break; case 2: VL_SNPRINTF(buf, 32, "%%03x"); break; case 3: VL_SNPRINTF(buf, 32, "%%04x"); break; case 4: VL_SNPRINTF(buf, 32, "%%05x"); break; case 5: VL_SNPRINTF(buf, 32, "%%06x"); break; case 6: VL_SNPRINTF(buf, 32, "%%07x"); break; case 7: VL_SNPRINTF(buf, 32, "%%08x"); break; default: assert(false); break; // LCOV_EXCL_LINE } return buf; } static const char* formatBinary(int nBits, vluint32_t bits) { assert((nBits >= 1) && (nBits <= 32)); static VL_THREAD_LOCAL char buf[64]; for (int i = 0; i < nBits; i++) { bool isOne = bits & (1 << (nBits - 1 - i)); buf[i] = (isOne ? '1' : '0'); } buf[nBits] = '\0'; return buf; } VlReadMem::VlReadMem(bool hex, int bits, const std::string& filename, QData start, QData end) : m_hex(hex) , m_bits(bits) , m_filename(filename) , m_end(end) , m_addr(start) , m_linenum(0) { m_fp = fopen(filename.c_str(), "r"); if (VL_UNLIKELY(!m_fp)) { // We don't report the Verilog source filename as it slow to have to pass it down VL_FATAL_MT(filename.c_str(), 0, "", "$readmem file not found"); // cppcheck-suppress resourceLeak // m_fp is NULL - bug in cppcheck return; } } VlReadMem::~VlReadMem() { if (m_fp) { fclose(m_fp); m_fp = NULL; } } bool VlReadMem::get(QData& addrr, std::string& valuer) { if (VL_UNLIKELY(!m_fp)) return false; valuer = ""; // Prep for reading bool indata = false; bool ignore_to_eol = false; bool ignore_to_cmt = false; bool reading_addr = false; int lastc = ' '; // Read the data // We process a character at a time, as then we don't need to deal // with changing buffer sizes dynamically, etc. while (true) { int c = fgetc(m_fp); if (VL_UNLIKELY(c == EOF)) break; // printf("%d: Got '%c' Addr%lx IN%d IgE%d IgC%d\n", // m_linenum, c, m_addr, indata, ignore_to_eol, ignore_to_cmt); // See if previous data value has completed, and if so return if (c == '_') continue; // Ignore _ e.g. inside a number if (indata && !isxdigit(c) && c != 'x' && c != 'X') { // printf("Got data @%lx = %s\n", m_addr, valuer.c_str()); ungetc(c, m_fp); addrr = m_addr; ++m_addr; return true; } // Parse line if (c == '\n') { ++m_linenum; ignore_to_eol = false; reading_addr = false; } else if (c == '\t' || c == ' ' || c == '\r' || c == '\f') { reading_addr = false; } // Skip // comments and detect /* comments else if (ignore_to_cmt && lastc == '*' && c == '/') { ignore_to_cmt = false; reading_addr = false; } else if (!ignore_to_eol && !ignore_to_cmt) { if (lastc == '/' && c == '*') { ignore_to_cmt = true; } else if (lastc == '/' && c == '/') { ignore_to_eol = true; } else if (c == '/') { // Part of /* or // } else if (c == '#') { ignore_to_eol = true; } else if (c == '@') { reading_addr = true; m_addr = 0; } // Check for hex or binary digits as file format requests else if (isxdigit(c) || (!reading_addr && (c == 'x' || c == 'X'))) { c = tolower(c); int value = (c >= 'a' ? (c == 'x' ? VL_RAND_RESET_I(4) : (c - 'a' + 10)) : (c - '0')); if (reading_addr) { // Decode @ addresses m_addr = (m_addr << 4) + value; } else { indata = true; valuer += static_cast(c); // printf(" Value width=%d @%x = %c\n", width, m_addr, c); if (VL_UNLIKELY(value > 1 && !m_hex)) { VL_FATAL_MT(m_filename.c_str(), m_linenum, "", "$readmemb (binary) file contains hex characters"); } } } else { VL_FATAL_MT(m_filename.c_str(), m_linenum, "", "$readmem file syntax error"); } } lastc = c; } if (VL_UNLIKELY(m_end != ~0ULL && m_addr <= m_end)) { VL_FATAL_MT(m_filename.c_str(), m_linenum, "", "$readmem file ended before specified final address (IEEE 2017 21.4)"); } return false; // EOF } void VlReadMem::setData(void* valuep, const std::string& rhs) { QData shift = m_hex ? 4ULL : 1ULL; bool innum = false; // Shift value in for (std::string::const_iterator it = rhs.begin(); it != rhs.end(); ++it) { char c = tolower(*it); int value = (c >= 'a' ? (c == 'x' ? VL_RAND_RESET_I(4) : (c - 'a' + 10)) : (c - '0')); if (m_bits <= 8) { CData* datap = reinterpret_cast(valuep); if (!innum) { *datap = 0; } *datap = ((*datap << shift) + value) & VL_MASK_I(m_bits); } else if (m_bits <= 16) { SData* datap = reinterpret_cast(valuep); if (!innum) { *datap = 0; } *datap = ((*datap << shift) + value) & VL_MASK_I(m_bits); } else if (m_bits <= VL_IDATASIZE) { IData* datap = reinterpret_cast(valuep); if (!innum) { *datap = 0; } *datap = ((*datap << shift) + value) & VL_MASK_I(m_bits); } else if (m_bits <= VL_QUADSIZE) { QData* datap = reinterpret_cast(valuep); if (!innum) { *datap = 0; } *datap = ((*datap << static_cast(shift)) + static_cast(value)) & VL_MASK_Q(m_bits); } else { WDataOutP datap = reinterpret_cast(valuep); if (!innum) VL_ZERO_RESET_W(m_bits, datap); _VL_SHIFTL_INPLACE_W(m_bits, datap, static_cast(shift)); datap[0] |= value; } innum = true; } } VlWriteMem::VlWriteMem(bool hex, int bits, const std::string& filename, QData start, QData end) : m_hex(hex) , m_bits(bits) , m_addr(0) { if (VL_UNLIKELY(start > end)) { VL_FATAL_MT(filename.c_str(), 0, "", "$writemem invalid address range"); return; } m_fp = fopen(filename.c_str(), "w"); if (VL_UNLIKELY(!m_fp)) { VL_FATAL_MT(filename.c_str(), 0, "", "$writemem file not found"); // cppcheck-suppress resourceLeak // m_fp is NULL - bug in cppcheck return; } } VlWriteMem::~VlWriteMem() { if (m_fp) { fclose(m_fp); m_fp = NULL; } } void VlWriteMem::print(QData addr, bool addrstamp, const void* valuep) { if (VL_UNLIKELY(!m_fp)) return; if (addr != m_addr && addrstamp) { // Only assoc has time stamps fprintf(m_fp, "@%" VL_PRI64 "x\n", addr); } m_addr = addr + 1; if (m_bits <= 8) { const CData* datap = reinterpret_cast(valuep); if (m_hex) { fprintf(m_fp, memhFormat(m_bits), VL_MASK_I(m_bits) & *datap); fprintf(m_fp, "\n"); } else { fprintf(m_fp, "%s\n", formatBinary(m_bits, *datap)); } } else if (m_bits <= 16) { const SData* datap = reinterpret_cast(valuep); if (m_hex) { fprintf(m_fp, memhFormat(m_bits), VL_MASK_I(m_bits) & *datap); fprintf(m_fp, "\n"); } else { fprintf(m_fp, "%s\n", formatBinary(m_bits, *datap)); } } else if (m_bits <= 32) { const IData* datap = reinterpret_cast(valuep); if (m_hex) { fprintf(m_fp, memhFormat(m_bits), VL_MASK_I(m_bits) & *datap); fprintf(m_fp, "\n"); } else { fprintf(m_fp, "%s\n", formatBinary(m_bits, *datap)); } } else if (m_bits <= 64) { const QData* datap = reinterpret_cast(valuep); vluint64_t value = VL_MASK_Q(m_bits) & *datap; vluint32_t lo = value & 0xffffffff; vluint32_t hi = value >> 32; if (m_hex) { fprintf(m_fp, memhFormat(m_bits - 32), hi); fprintf(m_fp, "%08x\n", lo); } else { fprintf(m_fp, "%s", formatBinary(m_bits - 32, hi)); fprintf(m_fp, "%s\n", formatBinary(32, lo)); } } else { WDataInP datap = reinterpret_cast(valuep); // output as a sequence of VL_EDATASIZE'd words // from MSB to LSB. Mask off the MSB word which could // contain junk above the top of valid data. int word_idx = ((m_bits - 1) / VL_EDATASIZE); bool first = true; while (word_idx >= 0) { EData data = datap[word_idx]; if (first) { data &= VL_MASK_E(m_bits); int top_word_nbits = VL_BITBIT_E(m_bits - 1) + 1; if (m_hex) { fprintf(m_fp, memhFormat(top_word_nbits), data); } else { fprintf(m_fp, "%s", formatBinary(top_word_nbits, data)); } } else { if (m_hex) { fprintf(m_fp, "%08x", data); } else { fprintf(m_fp, "%s", formatBinary(32, data)); } } word_idx--; first = false; } fprintf(m_fp, "\n"); } } void VL_READMEM_N(bool hex, // Hex format, else binary int bits, // M_Bits of each array row QData depth, // Number of rows int array_lsb, // Index of first row. Valid row addresses // // range from array_lsb up to (array_lsb + depth - 1) const std::string& filename, // Input file name void* memp, // Array state QData start, // First array row address to read QData end // Last row address to read ) VL_MT_SAFE { if (start < static_cast(array_lsb)) start = array_lsb; VlReadMem rmem(hex, bits, filename, start, end); if (VL_UNLIKELY(!rmem.isOpen())) return; while (true) { QData addr = 0; std::string value; if (rmem.get(addr /*ref*/, value /*ref*/)) { if (VL_UNLIKELY(addr < static_cast(array_lsb) || addr >= static_cast(array_lsb + depth))) { VL_FATAL_MT(filename.c_str(), rmem.linenum(), "", "$readmem file address beyond bounds of array"); } else { QData entry = addr - array_lsb; if (bits <= 8) { CData* datap = &(reinterpret_cast(memp))[entry]; rmem.setData(datap, value); } else if (bits <= 16) { SData* datap = &(reinterpret_cast(memp))[entry]; rmem.setData(datap, value); } else if (bits <= VL_IDATASIZE) { IData* datap = &(reinterpret_cast(memp))[entry]; rmem.setData(datap, value); } else if (bits <= VL_QUADSIZE) { QData* datap = &(reinterpret_cast(memp))[entry]; rmem.setData(datap, value); } else { WDataOutP datap = &(reinterpret_cast(memp))[entry * VL_WORDS_I(bits)]; rmem.setData(datap, value); } } } else { break; } } } void VL_WRITEMEM_N(bool hex, // Hex format, else binary int bits, // Width of each array row QData depth, // Number of rows int array_lsb, // Index of first row. Valid row addresses // // range from array_lsb up to (array_lsb + depth - 1) const std::string& filename, // Output file name const void* memp, // Array state QData start, // First array row address to write QData end // Last address to write, or ~0 when not specified ) VL_MT_SAFE { QData addr_max = array_lsb + depth - 1; if (start < static_cast(array_lsb)) start = array_lsb; if (end > addr_max) end = addr_max; VlWriteMem wmem(hex, bits, filename, start, end); if (VL_UNLIKELY(!wmem.isOpen())) return; for (QData addr = start; addr <= end; ++addr) { QData row_offset = addr - array_lsb; if (bits <= 8) { const CData* datap = &(reinterpret_cast(memp))[row_offset]; wmem.print(addr, false, datap); } else if (bits <= 16) { const SData* datap = &(reinterpret_cast(memp))[row_offset]; wmem.print(addr, false, datap); } else if (bits <= 32) { const IData* datap = &(reinterpret_cast(memp))[row_offset]; wmem.print(addr, false, datap); } else if (bits <= 64) { const QData* datap = &(reinterpret_cast(memp))[row_offset]; wmem.print(addr, false, datap); } else { WDataInP memDatap = reinterpret_cast(memp); WDataInP datap = &memDatap[row_offset * VL_WORDS_I(bits)]; wmem.print(addr, false, datap); } } } //=========================================================================== // Timescale conversion // Helper function for conversion of timescale strings // Converts (1|10|100)(s|ms|us|ns|ps|fs) to power of then int VL_TIME_STR_CONVERT(const char* strp) { int scale = 0; if (!strp) return 0; if (*strp++ != '1') return 0; while (*strp == '0') { scale++; strp++; } switch (*strp++) { case 's': break; case 'm': scale -= 3; break; case 'u': scale -= 6; break; case 'n': scale -= 9; break; case 'p': scale -= 12; break; case 'f': scale -= 15; break; default: return 0; } if ((scale < 0) && (*strp++ != 's')) return 0; if (*strp) return 0; return scale; } static const char* vl_time_str(int scale) { static const char* const names[] = {"100s", "10s", "1s", "100ms", "10ms", "1ms", "100us", "10us", "1us", "100ns", "10ns", "1ns", "100ps", "10ps", "1ps", "100fs", "10fs", "1fs"}; if (VL_UNLIKELY(scale > 2 || scale < -15)) scale = 0; return names[2 - scale]; } double vl_time_multiplier(int scale) { // Return timescale multipler -18 to +18 // For speed, this does not check for illegal values if (scale < 0) { static const double neg10[] = {1.0, 0.1, 0.01, 0.001, 0.0001, 0.00001, 0.000001, 0.0000001, 0.00000001, 0.000000001, 0.0000000001, 0.00000000001, 0.000000000001, 0.0000000000001, 0.00000000000001, 0.000000000000001, 0.0000000000000001, 0.00000000000000001, 0.000000000000000001}; return neg10[-scale]; } else { static const double pow10[] = {1.0, 10.0, 100.0, 1000.0, 10000.0, 100000.0, 1000000.0, 10000000.0, 100000000.0, 1000000000.0, 10000000000.0, 100000000000.0, 1000000000000.0, 10000000000000.0, 100000000000000.0, 1000000000000000.0, 10000000000000000.0, 100000000000000000.0, 1000000000000000000.0}; return pow10[scale]; } } const char* Verilated::timeunitString() VL_MT_SAFE { return vl_time_str(timeunit()); } const char* Verilated::timeprecisionString() VL_MT_SAFE { return vl_time_str(timeprecision()); } void VL_PRINTTIMESCALE(const char* namep, const char* timeunitp) VL_MT_SAFE { VL_PRINTF_MT("Time scale of %s is %s / %s\n", namep, timeunitp, Verilated::timeprecisionString()); } void VL_TIMEFORMAT_IINI(int units, int precision, const std::string& suffix, int width) VL_MT_SAFE { VerilatedImp::timeFormatUnits(units); VerilatedImp::timeFormatPrecision(precision); VerilatedImp::timeFormatSuffix(suffix); VerilatedImp::timeFormatWidth(width); } //=========================================================================== // Verilated:: Methods Verilated::ThreadLocal::ThreadLocal() : #ifdef VL_THREADED t_mtaskId(0) , t_endOfEvalReqd(0) , #endif t_dpiScopep(NULL) , t_dpiFilename(0) , t_dpiLineno(0) { } Verilated::ThreadLocal::~ThreadLocal() {} void Verilated::debug(int level) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_s.s_debug = level; if (level) { #ifdef VL_DEBUG VL_DEBUG_IF(VL_DBG_MSGF("- Verilated::debug is on." " Message prefix indicates {,}.\n");); #else VL_PRINTF_MT("- Verilated::debug attempted," " but compiled without VL_DEBUG, so messages suppressed.\n" "- Suggest remake using 'make ... CPPFLAGS=-DVL_DEBUG'\n"); #endif } } void Verilated::randReset(int val) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_s.s_randReset = val; } void Verilated::randSeed(int val) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_s.s_randSeed = val; } void Verilated::calcUnusedSigs(bool flag) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_s.s_calcUnusedSigs = flag; } void Verilated::errorCount(int val) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_s.s_errorCount = val; } void Verilated::errorCountInc() VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); ++s_s.s_errorCount; } void Verilated::errorLimit(int val) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_s.s_errorLimit = val; } void Verilated::gotFinish(bool flag) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_s.s_gotFinish = flag; } void Verilated::assertOn(bool flag) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_s.s_assertOn = flag; } void Verilated::fatalOnVpiError(bool flag) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_s.s_fatalOnVpiError = flag; } void Verilated::timeunit(int value) VL_MT_SAFE { if (value < 0) value = -value; // Stored as 0..15 const VerilatedLockGuard lock(m_mutex); s_s.s_timeunit = value; } void Verilated::timeprecision(int value) VL_MT_SAFE { if (value < 0) value = -value; // Stored as 0..15 const VerilatedLockGuard lock(m_mutex); s_s.s_timeprecision = value; #ifdef SYSTEMC_VERSION sc_time sc_res = sc_get_time_resolution(); int sc_prec = 99; if (sc_res == sc_time(1, SC_SEC)) { sc_prec = 0; } else if (sc_res == sc_time(1, SC_MS)) { sc_prec = 3; } else if (sc_res == sc_time(1, SC_US)) { sc_prec = 6; } else if (sc_res == sc_time(1, SC_NS)) { sc_prec = 9; } else if (sc_res == sc_time(1, SC_PS)) { sc_prec = 12; } else if (sc_res == sc_time(1, SC_FS)) { sc_prec = 15; } if (value != sc_prec) { std::ostringstream msg; msg << "SystemC's sc_set_time_resolution is 10^-" << sc_prec << ", which does not match Verilog timeprecision 10^-" << value << ". Suggest use 'sc_set_time_resolution(" << vl_time_str(value) << ")', or Verilator '--timescale-override " << vl_time_str(sc_prec) << "/" << vl_time_str(sc_prec) << "'"; std::string msgs = msg.str(); VL_FATAL_MT("", 0, "", msgs.c_str()); } #endif } void Verilated::profThreadsStart(vluint64_t flag) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_ns.s_profThreadsStart = flag; } void Verilated::profThreadsWindow(vluint64_t flag) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); s_ns.s_profThreadsWindow = flag; } void Verilated::profThreadsFilenamep(const char* flagp) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); if (s_ns.s_profThreadsFilenamep) free(const_cast(s_ns.s_profThreadsFilenamep)); s_ns.s_profThreadsFilenamep = strdup(flagp); } const char* Verilated::catName(const char* n1, const char* n2, const char* delimiter) VL_MT_SAFE { // Returns new'ed data // Used by symbol table creation to make module names static VL_THREAD_LOCAL char* strp = NULL; static VL_THREAD_LOCAL size_t len = 0; size_t newlen = strlen(n1) + strlen(n2) + strlen(delimiter) + 1; if (!strp || newlen > len) { if (strp) delete[] strp; strp = new char[newlen]; len = newlen; } strcpy(strp, n1); if (*n1) strcat(strp, delimiter); strcat(strp, n2); return strp; } //========================================================================= // Flush and exit callbacks // Keeping these out of class Verilated to avoid having to include // in verilated.h (for compilation speed) typedef std::list > VoidPCbList; static VoidPCbList g_flushCbs; static VoidPCbList g_exitCbs; static void addCb(Verilated::VoidPCb cb, void* datap, VoidPCbList& cbs) { std::pair pair(cb, datap); cbs.remove(pair); // Just in case it's a duplicate cbs.push_back(pair); } static void removeCb(Verilated::VoidPCb cb, void* datap, VoidPCbList& cbs) { std::pair pair(cb, datap); cbs.remove(pair); } static void runCallbacks(VoidPCbList& cbs) VL_MT_SAFE { for (VoidPCbList::iterator it = cbs.begin(); it != cbs.end(); ++it) { it->first(it->second); } } void Verilated::addFlushCb(VoidPCb cb, void* datap) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); addCb(cb, datap, g_flushCbs); } void Verilated::removeFlushCb(VoidPCb cb, void* datap) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); removeCb(cb, datap, g_flushCbs); } void Verilated::runFlushCallbacks() VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); runCallbacks(g_flushCbs); fflush(stderr); fflush(stdout); // When running internal code coverage (gcc --coverage, as opposed to // verilator --coverage), dump coverage data to properly cover failing // tests. VL_GCOV_FLUSH(); } void Verilated::addExitCb(VoidPCb cb, void* datap) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); addCb(cb, datap, g_exitCbs); } void Verilated::removeExitCb(VoidPCb cb, void* datap) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); removeCb(cb, datap, g_exitCbs); } void Verilated::runExitCallbacks() VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); runCallbacks(g_exitCbs); } const char* Verilated::productName() VL_PURE { return VERILATOR_PRODUCT; } const char* Verilated::productVersion() VL_PURE { return VERILATOR_VERSION; } void Verilated::commandArgs(int argc, const char** argv) VL_MT_SAFE { const VerilatedLockGuard lock(s_args.m_argMutex); s_args.argc = argc; s_args.argv = argv; VerilatedImp::commandArgs(argc, argv); } const char* Verilated::commandArgsPlusMatch(const char* prefixp) VL_MT_SAFE { const std::string& match = VerilatedImp::argPlusMatch(prefixp); static VL_THREAD_LOCAL char outstr[VL_VALUE_STRING_MAX_WIDTH]; if (match.empty()) return ""; outstr[0] = '\0'; strncat(outstr, match.c_str(), VL_VALUE_STRING_MAX_WIDTH - 1); return outstr; } void Verilated::nullPointerError(const char* filename, int linenum) VL_MT_SAFE { // Slowpath - Called only on error VL_FATAL_MT(filename, linenum, "", "Null pointer dereferenced"); VL_UNREACHABLE } void Verilated::overWidthError(const char* signame) VL_MT_SAFE { // Slowpath - Called only when signal sets too high of a bit std::string msg = (std::string("Testbench C set input '") + signame + "' to value that overflows what the signal's width can fit"); VL_FATAL_MT("unknown", 0, "", msg.c_str()); VL_UNREACHABLE } void Verilated::mkdir(const char* dirname) VL_MT_UNSAFE { #if defined(_WIN32) || defined(__MINGW32__) ::mkdir(dirname); #else ::mkdir(dirname, 0777); #endif } void Verilated::quiesce() VL_MT_SAFE { #ifdef VL_THREADED // Wait until all threads under this evaluation are quiet // THREADED-TODO #endif } void Verilated::internalsDump() VL_MT_SAFE { VerilatedImp::internalsDump(); } void Verilated::scopesDump() VL_MT_SAFE { VerilatedImp::scopesDump(); } const VerilatedScope* Verilated::scopeFind(const char* namep) VL_MT_SAFE { return VerilatedImp::scopeFind(namep); } int Verilated::exportFuncNum(const char* namep) VL_MT_SAFE { return VerilatedImp::exportFind(namep); } const VerilatedScopeNameMap* Verilated::scopeNameMap() VL_MT_SAFE { return VerilatedImp::scopeNameMap(); } #ifdef VL_THREADED void Verilated::endOfThreadMTaskGuts(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE { VL_DEBUG_IF(VL_DBG_MSGF("End of thread mtask\n");); VerilatedThreadMsgQueue::flush(evalMsgQp); } void Verilated::endOfEvalGuts(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE { VL_DEBUG_IF(VL_DBG_MSGF("End-of-eval cleanup\n");); evalMsgQp->process(); } #endif //=========================================================================== // VerilatedImp:: Methods std::string VerilatedImp::timeFormatSuffix() VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_sergMutex); return s_s.m_serg.m_timeFormatSuffix; } void VerilatedImp::timeFormatSuffix(const std::string& value) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_sergMutex); s_s.m_serg.m_timeFormatSuffix = value; } void VerilatedImp::timeFormatUnits(int value) VL_MT_SAFE { s_s.m_ser.m_timeFormatUnits = value; } void VerilatedImp::timeFormatPrecision(int value) VL_MT_SAFE { s_s.m_ser.m_timeFormatPrecision = value; } void VerilatedImp::timeFormatWidth(int value) VL_MT_SAFE { s_s.m_ser.m_timeFormatWidth = value; } void VerilatedImp::internalsDump() VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_argMutex); VL_PRINTF_MT("internalsDump:\n"); versionDump(); VL_PRINTF_MT(" Argv:"); for (ArgVec::const_iterator it = s_s.m_argVec.begin(); it != s_s.m_argVec.end(); ++it) { VL_PRINTF_MT(" %s", it->c_str()); } VL_PRINTF_MT("\n"); scopesDump(); exportsDump(); userDump(); } void VerilatedImp::versionDump() VL_MT_SAFE { VL_PRINTF_MT(" Version: %s %s\n", Verilated::productName(), Verilated::productVersion()); } void VerilatedImp::commandArgs(int argc, const char** argv) VL_EXCLUDES(s_s.m_argMutex) { const VerilatedLockGuard lock(s_s.m_argMutex); s_s.m_argVec.clear(); // Always clear commandArgsAddGuts(argc, argv); } void VerilatedImp::commandArgsAdd(int argc, const char** argv) VL_EXCLUDES(s_s.m_argMutex) { const VerilatedLockGuard lock(s_s.m_argMutex); commandArgsAddGuts(argc, argv); } void VerilatedImp::commandArgsAddGuts(int argc, const char** argv) VL_REQUIRES(s_s.m_argMutex) { if (!s_s.m_argVecLoaded) s_s.m_argVec.clear(); for (int i = 0; i < argc; ++i) { s_s.m_argVec.push_back(argv[i]); commandArgVl(argv[i]); } s_s.m_argVecLoaded = true; // Can't just test later for empty vector, no arguments is ok } void VerilatedImp::commandArgVl(const std::string& arg) { if (0 == strncmp(arg.c_str(), "+verilator+", strlen("+verilator+"))) { std::string value; if (arg == "+verilator+debug") { Verilated::debug(4); } else if (commandArgVlValue(arg, "+verilator+debugi+", value /*ref*/)) { Verilated::debug(atoi(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+error+limit+", value /*ref*/)) { Verilated::errorLimit(atoi(value.c_str())); } else if (arg == "+verilator+help") { versionDump(); VL_PRINTF_MT("For help, please see 'verilator --help'\n"); VL_FATAL_MT("COMMAND_LINE", 0, "", "Exiting due to command line argument (not an error)"); } else if (commandArgVlValue(arg, "+verilator+prof+threads+start+", value /*ref*/)) { Verilated::profThreadsStart(atoll(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+prof+threads+window+", value /*ref*/)) { Verilated::profThreadsWindow(atol(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+prof+threads+file+", value /*ref*/)) { Verilated::profThreadsFilenamep(value.c_str()); } else if (commandArgVlValue(arg, "+verilator+rand+reset+", value /*ref*/)) { Verilated::randReset(atoi(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+seed+", value /*ref*/)) { Verilated::randSeed(atoi(value.c_str())); } else if (arg == "+verilator+noassert") { Verilated::assertOn(false); } else if (arg == "+verilator+V") { versionDump(); // Someday more info too VL_FATAL_MT("COMMAND_LINE", 0, "", "Exiting due to command line argument (not an error)"); } else if (arg == "+verilator+version") { versionDump(); VL_FATAL_MT("COMMAND_LINE", 0, "", "Exiting due to command line argument (not an error)"); } else { VL_PRINTF_MT("%%Warning: Unknown +verilator runtime argument: '%s'\n", arg.c_str()); } } } bool VerilatedImp::commandArgVlValue(const std::string& arg, const std::string& prefix, std::string& valuer) { size_t len = prefix.length(); if (0 == strncmp(prefix.c_str(), arg.c_str(), len)) { valuer = arg.substr(len); return true; } else { return false; } } //====================================================================== // VerilatedSyms:: Methods VerilatedSyms::VerilatedSyms() { #ifdef VL_THREADED __Vm_evalMsgQp = new VerilatedEvalMsgQueue; #endif } VerilatedSyms::~VerilatedSyms() { #ifdef VL_THREADED delete __Vm_evalMsgQp; #endif } //=========================================================================== // VerilatedModule:: Methods VerilatedModule::VerilatedModule(const char* namep) : m_namep(strdup(namep)) {} VerilatedModule::~VerilatedModule() { // Memory cleanup - not called during normal operation // NOLINTNEXTLINE(google-readability-casting) if (m_namep) VL_DO_CLEAR(free((void*)(m_namep)), m_namep = NULL); } //====================================================================== // VerilatedVar:: Methods // cppcheck-suppress unusedFunction // Used by applications vluint32_t VerilatedVarProps::entSize() const { vluint32_t size = 1; switch (vltype()) { case VLVT_PTR: size = sizeof(void*); break; case VLVT_UINT8: size = sizeof(CData); break; case VLVT_UINT16: size = sizeof(SData); break; case VLVT_UINT32: size = sizeof(IData); break; case VLVT_UINT64: size = sizeof(QData); break; case VLVT_WDATA: size = VL_WORDS_I(packed().elements()) * sizeof(IData); break; default: size = 0; break; } return size; } size_t VerilatedVarProps::totalSize() const { size_t size = entSize(); for (int udim = 0; udim <= udims(); ++udim) size *= m_unpacked[udim].elements(); return size; } void* VerilatedVarProps::datapAdjustIndex(void* datap, int dim, int indx) const { if (VL_UNLIKELY(dim <= 0 || dim > udims())) return NULL; if (VL_UNLIKELY(indx < low(dim) || indx > high(dim))) return NULL; int indxAdj = indx - low(dim); vluint8_t* bytep = reinterpret_cast(datap); // If on index 1 of a 2 index array, then each index 1 is index2sz*entsz size_t slicesz = entSize(); for (int d = dim + 1; d <= m_udims; ++d) slicesz *= elements(d); bytep += indxAdj * slicesz; return bytep; } //====================================================================== // VerilatedScope:: Methods VerilatedScope::VerilatedScope() { m_callbacksp = NULL; m_namep = NULL; m_identifierp = NULL; m_funcnumMax = 0; m_symsp = NULL; m_varsp = NULL; m_timeunit = 0; m_type = SCOPE_OTHER; } VerilatedScope::~VerilatedScope() { // Memory cleanup - not called during normal operation VerilatedImp::scopeErase(this); if (m_namep) VL_DO_CLEAR(delete[] m_namep, m_namep = NULL); if (m_callbacksp) VL_DO_CLEAR(delete[] m_callbacksp, m_callbacksp = NULL); if (m_varsp) VL_DO_CLEAR(delete m_varsp, m_varsp = NULL); m_funcnumMax = 0; // Force callback table to empty } void VerilatedScope::configure(VerilatedSyms* symsp, const char* prefixp, const char* suffixp, const char* identifier, vlsint8_t timeunit, const Type& type) VL_MT_UNSAFE { // Slowpath - called once/scope at construction // We don't want the space and reference-count access overhead of strings. m_symsp = symsp; m_type = type; m_timeunit = timeunit; char* namep = new char[strlen(prefixp) + strlen(suffixp) + 2]; strcpy(namep, prefixp); if (*prefixp && *suffixp) strcat(namep, "."); strcat(namep, suffixp); m_namep = namep; m_identifierp = identifier; VerilatedImp::scopeInsert(this); } void VerilatedScope::exportInsert(int finalize, const char* namep, void* cb) VL_MT_UNSAFE { // Slowpath - called once/scope*export at construction // Insert a exported function into scope table int funcnum = VerilatedImp::exportInsert(namep); if (!finalize) { // Need two passes so we know array size to create // Alternative is to dynamically stretch the array, which is more code, and slower. if (funcnum >= m_funcnumMax) { m_funcnumMax = funcnum + 1; } } else { if (VL_UNCOVERABLE(funcnum >= m_funcnumMax)) { VL_FATAL_MT(__FILE__, __LINE__, "", // LCOV_EXCL_LINE "Internal: Bad funcnum vs. pre-finalize maximum"); } if (VL_UNLIKELY(!m_callbacksp)) { // First allocation m_callbacksp = new void*[m_funcnumMax]; memset(m_callbacksp, 0, m_funcnumMax * sizeof(void*)); } m_callbacksp[funcnum] = cb; } } void VerilatedScope::varInsert(int finalize, const char* namep, void* datap, bool isParam, VerilatedVarType vltype, int vlflags, int dims, ...) VL_MT_UNSAFE { // Grab dimensions // In the future we may just create a large table at emit time and // statically construct from that. if (!finalize) return; if (!m_varsp) m_varsp = new VerilatedVarNameMap(); VerilatedVar var(namep, datap, vltype, static_cast(vlflags), dims, isParam); va_list ap; va_start(ap, dims); for (int i = 0; i < dims; ++i) { int msb = va_arg(ap, int); int lsb = va_arg(ap, int); if (i == 0) { var.m_packed.m_left = msb; var.m_packed.m_right = lsb; } else if (i >= 1 && i <= var.udims()) { var.m_unpacked[i - 1].m_left = msb; var.m_unpacked[i - 1].m_right = lsb; } else { // We could have a linked list of ranges, but really this whole thing needs // to be generalized to support structs and unions, etc. VL_FATAL_MT( __FILE__, __LINE__, "", (std::string("Unsupported multi-dimensional public varInsert: ") + namep).c_str()); } } va_end(ap); m_varsp->insert(std::make_pair(namep, var)); } // cppcheck-suppress unusedFunction // Used by applications VerilatedVar* VerilatedScope::varFind(const char* namep) const VL_MT_SAFE_POSTINIT { if (VL_LIKELY(m_varsp)) { VerilatedVarNameMap::iterator it = m_varsp->find(namep); if (VL_LIKELY(it != m_varsp->end())) return &(it->second); } return NULL; } void* VerilatedScope::exportFindNullError(int funcnum) VL_MT_SAFE { // Slowpath - Called only when find has failed std::string msg = (std::string("Testbench C called '") + VerilatedImp::exportName(funcnum) + "' but scope wasn't set, perhaps due to dpi import call without " + "'context', or missing svSetScope. See IEEE 1800-2017 35.5.3."); VL_FATAL_MT("unknown", 0, "", msg.c_str()); return NULL; } void* VerilatedScope::exportFindError(int funcnum) const { // Slowpath - Called only when find has failed std::string msg = (std::string("Testbench C called '") + VerilatedImp::exportName(funcnum) + "' but this DPI export function exists only in other scopes, not scope '" + name() + "'"); VL_FATAL_MT("unknown", 0, "", msg.c_str()); return NULL; } void VerilatedScope::scopeDump() const { VL_PRINTF_MT(" SCOPE %p: %s\n", this, name()); for (int i = 0; i < m_funcnumMax; ++i) { if (m_callbacksp && m_callbacksp[i]) { VL_PRINTF_MT(" DPI-EXPORT %p: %s\n", m_callbacksp[i], VerilatedImp::exportName(i)); } } if (VerilatedVarNameMap* varsp = this->varsp()) { for (VerilatedVarNameMap::const_iterator it = varsp->begin(); it != varsp->end(); ++it) { VL_PRINTF_MT(" VAR %p: %s\n", &(it->second), it->first); } } } void VerilatedHierarchy::add(VerilatedScope* fromp, VerilatedScope* top) { VerilatedImp::hierarchyAdd(fromp, top); } //=========================================================================== // VerilatedOneThreaded:: Methods #if defined(VL_THREADED) && defined(VL_DEBUG) void VerilatedAssertOneThread::fatal_different() VL_MT_SAFE { VL_FATAL_MT(__FILE__, __LINE__, "", "Routine called that is single threaded, but called from" " a different thread then the expected constructing thread"); } #endif //=========================================================================== verilator-4.038/include/verilated_imp.h0000664000177100017500000005623213702133367020151 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// /// \file /// \brief Verilator: Implementation Header, only for verilated.cpp internals. /// /// Code available from: https://verilator.org /// //========================================================================= #ifndef _VERILATED_IMP_H_ #define _VERILATED_IMP_H_ 1 ///< Header Guard // clang-format off #if !defined(_VERILATED_CPP_) && !defined(_VERILATED_DPI_CPP_) && !defined(_VERILATED_VPI_CPP_) # error "verilated_imp.h only to be included by verilated*.cpp internals" #endif #include "verilatedos.h" #include "verilated.h" #include "verilated_heavy.h" #include "verilated_syms.h" #include #include #include #include #ifdef VL_THREADED # include # include #endif // clang-format on class VerilatedScope; //====================================================================== // Threaded message passing #ifdef VL_THREADED /// Message, enqueued on an mtask, and consumed on the main eval thread class VerilatedMsg { public: // TYPES struct Cmp { bool operator()(const VerilatedMsg& a, const VerilatedMsg& b) const { return a.mtaskId() < b.mtaskId(); } }; private: // MEMBERS vluint32_t m_mtaskId; ///< MTask that did enqueue std::function m_cb; ///< Lambda to execute when message received public: // CONSTRUCTORS VerilatedMsg(const std::function& cb) : m_mtaskId(Verilated::mtaskId()) , m_cb(cb) {} ~VerilatedMsg() {} // METHODS vluint32_t mtaskId() const { return m_mtaskId; } /// Execute the lambda function void run() const { m_cb(); } }; /// Each thread has a queue it pushes to /// This assumes no thread starts pushing the next tick until the previous has drained. /// If more aggressiveness is needed, a double-buffered scheme might work well. class VerilatedEvalMsgQueue { typedef std::multiset VerilatedThreadQueue; std::atomic m_depth; ///< Current depth of queue (see comments below) VerilatedMutex m_mutex; ///< Mutex protecting queue VerilatedThreadQueue m_queue VL_GUARDED_BY(m_mutex); ///< Message queue public: // CONSTRUCTORS VerilatedEvalMsgQueue() : m_depth(0) { assert(atomic_is_lock_free(&m_depth)); } ~VerilatedEvalMsgQueue() {} private: VL_UNCOPYABLE(VerilatedEvalMsgQueue); public: // METHODS //// Add message to queue (called by producer) void post(const VerilatedMsg& msg) VL_EXCLUDES(m_mutex) { const VerilatedLockGuard lock(m_mutex); m_queue.insert(msg); // Pass by value to copy the message into queue ++m_depth; } /// Service queue until completion (called by consumer) void process() VL_EXCLUDES(m_mutex) { // Tracking m_depth is redundant to e.g. getting the mutex and looking at queue size, // but on the reader side it's 4x faster to test an atomic then getting a mutex while (m_depth) { // Wait for a message to be added to the queue // We don't use unique_lock as want to unlock with the message copy still in scope m_mutex.lock(); assert(!m_queue.empty()); // Otherwise m_depth is wrong // Unfortunately to release the lock we need to copy the message // (Or have the message be a pointer, but then new/delete cost on each message) // We assume messages are small, so copy auto it = m_queue.begin(); const VerilatedMsg msg = *(it); m_queue.erase(it); m_mutex.unlock(); m_depth--; // Ok if outside critical section as only this code checks the value { VL_DEBUG_IF(VL_DBG_MSGF("Executing callback from mtaskId=%d\n", msg.mtaskId());); msg.run(); } } } }; /// Each thread has a local queue to build up messages until the end of the eval() call class VerilatedThreadMsgQueue { std::queue m_queue; public: // CONSTRUCTORS VerilatedThreadMsgQueue() {} ~VerilatedThreadMsgQueue() { // The only call of this with a non-empty queue is a fatal error. // So this does not flush the queue, as the destination queue is not known to this class. } private: VL_UNCOPYABLE(VerilatedThreadMsgQueue); // METHODS static VerilatedThreadMsgQueue& threadton() { static VL_THREAD_LOCAL VerilatedThreadMsgQueue t_s; return t_s; } public: /// Add message to queue, called by producer static void post(const VerilatedMsg& msg) VL_MT_SAFE { // Handle calls to threaded routines outside // of any mtask -- if an initial block calls $finish, say. if (Verilated::mtaskId() == 0) { // No queueing, just do the action immediately msg.run(); } else { Verilated::endOfEvalReqdInc(); threadton().m_queue.push(msg); // Pass by value to copy the message into queue } } /// Push all messages to the eval's queue static void flush(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE { while (!threadton().m_queue.empty()) { evalMsgQp->post(threadton().m_queue.front()); threadton().m_queue.pop(); Verilated::endOfEvalReqdDec(); } } }; #endif // VL_THREADED // FILE* list constructed from a file-descriptor class VerilatedFpList { FILE* m_fp[31]; std::size_t m_sz; public: typedef FILE* const* const_iterator; explicit VerilatedFpList() : m_sz(0) {} const_iterator begin() const { return m_fp; } const_iterator end() const { return m_fp + m_sz; } std::size_t size() const { return m_sz; } std::size_t capacity() const { return 31; } void push_back(FILE* fd) { if (VL_LIKELY(size() < capacity())) m_fp[m_sz++] = fd; } }; //====================================================================== // VerilatedImp class VerilatedImp { // Whole class is internal use only - Global information shared between verilated*.cpp files. protected: friend class Verilated; // TYPES typedef std::vector ArgVec; typedef std::map, void*> UserMap; typedef std::map ExportNameMap; // MEMBERS static VerilatedImp s_s; ///< Static Singleton; One and only static this struct Serialized { // All these members serialized/deserialized int m_timeFormatUnits; // $timeformat units int m_timeFormatPrecision; // $timeformat number of decimal places int m_timeFormatWidth; // $timeformat character width enum { UNITS_NONE = 99 }; // Default based on precision Serialized() : m_timeFormatUnits(UNITS_NONE) , m_timeFormatPrecision(0) , m_timeFormatWidth(20) {} ~Serialized() {} } m_ser; VerilatedMutex m_sergMutex; ///< Protect m_ser struct SerializedG { // All these members serialized/deserialized and guarded std::string m_timeFormatSuffix; // $timeformat printf format } m_serg VL_GUARDED_BY(m_sergMutex); // Nothing below here is save-restored; users expected to re-register appropriately VerilatedMutex m_argMutex; ///< Protect m_argVec, m_argVecLoaded /// Argument list (NOT save-restored, may want different results) ArgVec m_argVec VL_GUARDED_BY(m_argMutex); bool m_argVecLoaded VL_GUARDED_BY(m_argMutex); ///< Ever loaded argument list VerilatedMutex m_userMapMutex; ///< Protect m_userMap UserMap m_userMap VL_GUARDED_BY(m_userMapMutex); ///< Map of <(scope,userkey), userData> VerilatedMutex m_nameMutex; ///< Protect m_nameMap /// Map of VerilatedScopeNameMap m_nameMap VL_GUARDED_BY(m_nameMutex); VerilatedMutex m_hierMapMutex; ///< Protect m_hierMap /// Map the represents scope hierarchy VerilatedHierarchyMap m_hierMap VL_GUARDED_BY(m_hierMapMutex); // Slow - somewhat static: VerilatedMutex m_exportMutex; ///< Protect m_nameMap /// Map of ExportNameMap m_exportMap VL_GUARDED_BY(m_exportMutex); int m_exportNext VL_GUARDED_BY(m_exportMutex); ///< Next export funcnum // File I/O VerilatedMutex m_fdMutex; ///< Protect m_fdps, m_fdFree std::vector m_fdps VL_GUARDED_BY(m_fdMutex); ///< File descriptors /// List of free descriptors (SLOW - FOPEN/CLOSE only) std::vector m_fdFree VL_GUARDED_BY(m_fdMutex); // List of free descriptors in the MCT region [4, 32) std::vector m_fdFreeMct VL_GUARDED_BY(m_fdMutex); public: // But only for verilated*.cpp // CONSTRUCTORS VerilatedImp() : m_argVecLoaded(false) , m_exportNext(0) { s_s.m_fdps.resize(31); std::fill(s_s.m_fdps.begin(), s_s.m_fdps.end(), (FILE*)0); s_s.m_fdFreeMct.resize(30); for (std::size_t i = 0, id = 1; i < s_s.m_fdFreeMct.size(); ++i, ++id) { s_s.m_fdFreeMct[i] = id; } } ~VerilatedImp() {} private: VL_UNCOPYABLE(VerilatedImp); public: // METHODS - debug static void internalsDump() VL_MT_SAFE; static void versionDump() VL_MT_SAFE; // METHODS - arguments public: static void commandArgs(int argc, const char** argv) VL_EXCLUDES(s_s.m_argMutex); static void commandArgsAdd(int argc, const char** argv) VL_EXCLUDES(s_s.m_argMutex); static std::string argPlusMatch(const char* prefixp) VL_EXCLUDES(s_s.m_argMutex) { const VerilatedLockGuard lock(s_s.m_argMutex); // Note prefixp does not include the leading "+" size_t len = strlen(prefixp); if (VL_UNLIKELY(!s_s.m_argVecLoaded)) { s_s.m_argVecLoaded = true; // Complain only once VL_FATAL_MT("unknown", 0, "", "%Error: Verilog called $test$plusargs or $value$plusargs without" " testbench C first calling Verilated::commandArgs(argc,argv)."); } for (ArgVec::const_iterator it = s_s.m_argVec.begin(); it != s_s.m_argVec.end(); ++it) { if ((*it)[0] == '+') { if (0 == strncmp(prefixp, it->c_str() + 1, len)) return *it; } } return ""; } private: static void commandArgsAddGuts(int argc, const char** argv) VL_REQUIRES(s_s.m_argMutex); static void commandArgVl(const std::string& arg); static bool commandArgVlValue(const std::string& arg, const std::string& prefix, std::string& valuer); public: // METHODS - user scope tracking // We implement this as a single large map instead of one map per scope // There's often many more scopes than userdata's and thus having a ~48byte // per map overhead * N scopes would take much more space and cache thrashing. static inline void userInsert(const void* scopep, void* userKey, void* userData) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_userMapMutex); UserMap::iterator it = s_s.m_userMap.find(std::make_pair(scopep, userKey)); if (it != s_s.m_userMap.end()) { it->second = userData; } else { s_s.m_userMap.insert(it, std::make_pair(std::make_pair(scopep, userKey), userData)); } } static inline void* userFind(const void* scopep, void* userKey) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_userMapMutex); UserMap::const_iterator it = s_s.m_userMap.find(std::make_pair(scopep, userKey)); if (VL_UNLIKELY(it == s_s.m_userMap.end())) return NULL; return it->second; } private: /// Symbol table destruction cleans up the entries for each scope. static void userEraseScope(const VerilatedScope* scopep) VL_MT_SAFE { // Slow ok - called once/scope on destruction, so we simply iterate. const VerilatedLockGuard lock(s_s.m_userMapMutex); for (UserMap::iterator it = s_s.m_userMap.begin(); it != s_s.m_userMap.end();) { if (it->first.first == scopep) { s_s.m_userMap.erase(it++); } else { ++it; } } } static void userDump() VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_userMapMutex); // Avoid it changing in middle of dump bool first = true; for (UserMap::const_iterator it = s_s.m_userMap.begin(); it != s_s.m_userMap.end(); ++it) { if (first) { VL_PRINTF_MT(" userDump:\n"); first = false; } VL_PRINTF_MT(" DPI_USER_DATA scope %p key %p: %p\n", it->first.first, it->first.second, it->second); } } public: // But only for verilated*.cpp // METHODS - scope name static void scopeInsert(const VerilatedScope* scopep) VL_MT_SAFE { // Slow ok - called once/scope at construction const VerilatedLockGuard lock(s_s.m_nameMutex); VerilatedScopeNameMap::iterator it = s_s.m_nameMap.find(scopep->name()); if (it == s_s.m_nameMap.end()) { s_s.m_nameMap.insert(it, std::make_pair(scopep->name(), scopep)); } } static inline const VerilatedScope* scopeFind(const char* namep) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_nameMutex); // If too slow, can assume this is only VL_MT_SAFE_POSINIT VerilatedScopeNameMap::const_iterator it = s_s.m_nameMap.find(namep); if (VL_UNLIKELY(it == s_s.m_nameMap.end())) return NULL; return it->second; } static void scopeErase(const VerilatedScope* scopep) VL_MT_SAFE { // Slow ok - called once/scope at destruction const VerilatedLockGuard lock(s_s.m_nameMutex); userEraseScope(scopep); VerilatedScopeNameMap::iterator it = s_s.m_nameMap.find(scopep->name()); if (it != s_s.m_nameMap.end()) s_s.m_nameMap.erase(it); } static void scopesDump() VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_nameMutex); VL_PRINTF_MT(" scopesDump:\n"); for (VerilatedScopeNameMap::const_iterator it = s_s.m_nameMap.begin(); it != s_s.m_nameMap.end(); ++it) { const VerilatedScope* scopep = it->second; scopep->scopeDump(); } VL_PRINTF_MT("\n"); } static const VerilatedScopeNameMap* scopeNameMap() VL_MT_SAFE_POSTINIT { // Thread save only assuming this is called only after model construction completed return &s_s.m_nameMap; } public: // But only for verilated*.cpp // METHODS - hierarchy static void hierarchyAdd(const VerilatedScope* fromp, const VerilatedScope* top) VL_MT_SAFE { // Slow ok - called at construction for VPI accessible elements const VerilatedLockGuard lock(s_s.m_hierMapMutex); s_s.m_hierMap[fromp].push_back(top); } static const VerilatedHierarchyMap* hierarchyMap() VL_MT_SAFE_POSTINIT { // Thread save only assuming this is called only after model construction completed return &s_s.m_hierMap; } public: // But only for verilated*.cpp // METHODS - export names // Each function prototype is converted to a function number which we // then use to index a 2D table also indexed by scope number, because we // can't know at Verilation time what scopes will exist in other modules // in the design that also happen to have our same callback function. // Rather than a 2D map, the integer scheme saves 500ish ns on a likely // miss at the cost of a multiply, and all lookups move to slowpath. static int exportInsert(const char* namep) VL_MT_SAFE { // Slow ok - called once/function at creation const VerilatedLockGuard lock(s_s.m_exportMutex); ExportNameMap::iterator it = s_s.m_exportMap.find(namep); if (it == s_s.m_exportMap.end()) { s_s.m_exportMap.insert(it, std::make_pair(namep, s_s.m_exportNext++)); return s_s.m_exportNext++; } else { return it->second; } } static int exportFind(const char* namep) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_exportMutex); ExportNameMap::const_iterator it = s_s.m_exportMap.find(namep); if (VL_LIKELY(it != s_s.m_exportMap.end())) return it->second; std::string msg = (std::string("%Error: Testbench C called ") + namep + " but no such DPI export function name exists in ANY model"); VL_FATAL_MT("unknown", 0, "", msg.c_str()); return -1; } static const char* exportName(int funcnum) VL_MT_SAFE { // Slowpath; find name for given export; errors only so no map to reverse-map it const VerilatedLockGuard lock(s_s.m_exportMutex); for (ExportNameMap::const_iterator it = s_s.m_exportMap.begin(); it != s_s.m_exportMap.end(); ++it) { if (it->second == funcnum) return it->first; } return "*UNKNOWN*"; } static void exportsDump() VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_exportMutex); bool first = true; for (ExportNameMap::const_iterator it = s_s.m_exportMap.begin(); it != s_s.m_exportMap.end(); ++it) { if (first) { VL_PRINTF_MT(" exportDump:\n"); first = false; } VL_PRINTF_MT(" DPI_EXPORT_NAME %05d: %s\n", it->second, it->first); } } // We don't free up m_exportMap until the end, because we can't be sure // what other models are using the assigned funcnum's. public: // But only for verilated*.cpp // METHODS - timeformat static std::string timeFormatSuffix() VL_MT_SAFE; static void timeFormatSuffix(const std::string& value) VL_MT_SAFE; static int timeFormatUnits() VL_MT_SAFE { if (s_s.m_ser.m_timeFormatUnits == Serialized::UNITS_NONE) { return Verilated::timeprecision(); } return s_s.m_ser.m_timeFormatUnits; } static int timeFormatPrecision() VL_MT_SAFE { return s_s.m_ser.m_timeFormatPrecision; } static int timeFormatWidth() VL_MT_SAFE { return s_s.m_ser.m_timeFormatWidth; } static void timeFormatUnits(int value) VL_MT_SAFE; static void timeFormatPrecision(int value) VL_MT_SAFE; static void timeFormatWidth(int value) VL_MT_SAFE; public: // But only for verilated*.cpp // METHODS - file IO static IData fdNewMcd(const char* filenamep) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_fdMutex); if (s_s.m_fdFreeMct.empty()) return 0; IData idx = s_s.m_fdFreeMct.back(); s_s.m_fdFreeMct.pop_back(); s_s.m_fdps[idx] = fopen(filenamep, "w"); if (VL_UNLIKELY(!s_s.m_fdps[idx])) return 0; return (1 << idx); } static IData fdNew(const char* filenamep, const char* modep) VL_MT_SAFE { FILE* fp = fopen(filenamep, modep); if (VL_UNLIKELY(!fp)) return 0; // Bit 31 indicates it's a descriptor not a MCD const VerilatedLockGuard lock(s_s.m_fdMutex); if (s_s.m_fdFree.empty()) { // Need to create more space in m_fdps and m_fdFree const std::size_t start = std::max(31UL + 1UL + 3UL, s_s.m_fdps.size()); const std::size_t excess = 10; s_s.m_fdps.resize(start + excess); std::fill(s_s.m_fdps.begin() + start, s_s.m_fdps.end(), (FILE*)0); s_s.m_fdFree.resize(excess); for (std::size_t i = 0, id = start; i < s_s.m_fdFree.size(); ++i, ++id) { s_s.m_fdFree[i] = id; } } IData idx = s_s.m_fdFree.back(); s_s.m_fdFree.pop_back(); s_s.m_fdps[idx] = fp; return (idx | (1UL << 31)); // bit 31 indicates not MCD } static void fdFlush(IData fdi) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_fdMutex); const VerilatedFpList fdlist = fdToFpList(fdi); for (VerilatedFpList::const_iterator it = fdlist.begin(); it != fdlist.end(); ++it) { fflush(*it); } } static IData fdSeek(IData fdi, IData offset, IData origin) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_fdMutex); const VerilatedFpList fdlist = fdToFpList(fdi); if (VL_UNLIKELY(fdlist.size() != 1)) return 0; return static_cast( fseek(*fdlist.begin(), static_cast(offset), static_cast(origin))); } static IData fdTell(IData fdi) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_fdMutex); const VerilatedFpList fdlist = fdToFpList(fdi); if (VL_UNLIKELY(fdlist.size() != 1)) return 0; return static_cast(ftell(*fdlist.begin())); } static void fdWrite(IData fdi, const std::string& output) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_fdMutex); const VerilatedFpList fdlist = fdToFpList(fdi); for (VerilatedFpList::const_iterator it = fdlist.begin(); it != fdlist.end(); ++it) { if (VL_UNLIKELY(!*it)) continue; fwrite(output.c_str(), 1, output.size(), *it); } } static void fdClose(IData fdi) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_fdMutex); if ((fdi & (1 << 31)) != 0) { // Non-MCD case IData idx = VL_MASK_I(31) & fdi; if (VL_UNLIKELY(idx >= s_s.m_fdps.size())) return; if (VL_UNLIKELY(!s_s.m_fdps[idx])) return; // Already free fclose(s_s.m_fdps[idx]); s_s.m_fdps[idx] = (FILE*)0; s_s.m_fdFree.push_back(idx); } else { // MCD case for (int i = 0; (fdi != 0) && (i < 31); i++, fdi >>= 1) { if (fdi & VL_MASK_I(1)) { fclose(s_s.m_fdps[i]); s_s.m_fdps[i] = NULL; s_s.m_fdFreeMct.push_back(i); } } } } static inline FILE* fdToFp(IData fdi) VL_MT_SAFE { const VerilatedLockGuard lock(s_s.m_fdMutex); const VerilatedFpList fdlist = fdToFpList(fdi); if (VL_UNLIKELY(fdlist.size() != 1)) return NULL; return *fdlist.begin(); } private: static inline VerilatedFpList fdToFpList(IData fdi) VL_REQUIRES(s_s.m_fdMutex) { VerilatedFpList fp; if ((fdi & (1 << 31)) != 0) { // Non-MCD case const IData idx = fdi & VL_MASK_I(31); switch (idx) { case 0: fp.push_back(stdin); break; case 1: fp.push_back(stdout); break; case 2: fp.push_back(stderr); break; default: if (VL_LIKELY(idx < s_s.m_fdps.size())) fp.push_back(s_s.m_fdps[idx]); break; } } else { // MCD Case for (int i = 0; (fdi != 0) && (i < fp.capacity()); ++i, fdi >>= 1) { if (fdi & VL_MASK_I(1)) fp.push_back(s_s.m_fdps[i]); } } return fp; } }; //====================================================================== #endif // Guard verilator-4.038/include/.gitignore0000664000177100017500000000004013657601702017130 0ustar wsnyderwsnyderverilated.mk verilated_config.h verilator-4.038/include/verilated_config.h0000664000177100017500000000161013702334662020620 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: Auto version information include for all Verilated C files /// /// Code available from: https://verilator.org /// //************************************************************************* ///**** Product and Version name // Autoconf substitutes this with the strings from AC_INIT. #define VERILATOR_PRODUCT "Verilator" #define VERILATOR_VERSION "4.038 2020-07-11" verilator-4.038/include/verilated_cov.cpp0000664000177100017500000004600213702216165020476 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Verilator coverage analysis /// //============================================================================= #include "verilatedos.h" #include "verilated.h" #include "verilated_cov.h" #include "verilated_cov_key.h" #include #include #include //============================================================================= // VerilatedCovImpBase /// Implementation base class for constants struct VerilatedCovImpBase { // TYPES enum { MAX_KEYS = 33 }; /// Maximum user arguments + filename+lineno enum { KEY_UNDEF = 0 }; /// Magic key # for unspecified values }; //============================================================================= // VerilatedCovImpItem /// Implementation class for a VerilatedCov item class VerilatedCovImpItem : VerilatedCovImpBase { public: // But only local to this file // MEMBERS int m_keys[MAX_KEYS]; ///< Key int m_vals[MAX_KEYS]; ///< Value for specified key // CONSTRUCTORS // Derived classes should call zero() in their constructor VerilatedCovImpItem() { for (int i = 0; i < MAX_KEYS; ++i) { m_keys[i] = KEY_UNDEF; m_vals[i] = 0; } } virtual ~VerilatedCovImpItem() {} virtual vluint64_t count() const = 0; virtual void zero() const = 0; }; //============================================================================= /// VerilatedCoverItem templated for a specific class /// Creates a new coverage item for the specified type. /// This isn't in the header file for auto-magic conversion because it /// inlines to too much code and makes compilation too slow. template class VerilatedCoverItemSpec : public VerilatedCovImpItem { private: // MEMBERS T* m_countp; ///< Count value public: // METHODS // cppcheck-suppress truncLongCastReturn virtual vluint64_t count() const VL_OVERRIDE { return *m_countp; } virtual void zero() const VL_OVERRIDE { *m_countp = 0; } // CONSTRUCTORS // cppcheck-suppress noExplicitConstructor explicit VerilatedCoverItemSpec(T* countp) : m_countp(countp) { *m_countp = 0; } virtual ~VerilatedCoverItemSpec() VL_OVERRIDE {} }; //============================================================================= // VerilatedCovImp /// Implementation class for VerilatedCov. See that class for public method information. /// All value and keys are indexed into a unique number. Thus we can greatly reduce /// the storage requirements for otherwise identical keys. class VerilatedCovImp : VerilatedCovImpBase { private: // TYPES typedef std::map ValueIndexMap; typedef std::map IndexValueMap; typedef std::deque ItemList; // MEMBERS VerilatedMutex m_mutex; ///< Protects all members ValueIndexMap m_valueIndexes VL_GUARDED_BY(m_mutex); ///< Unique arbitrary value for values IndexValueMap m_indexValues VL_GUARDED_BY(m_mutex); ///< Unique arbitrary value for keys ItemList m_items VL_GUARDED_BY(m_mutex); ///< List of all items VerilatedCovImpItem* m_insertp VL_GUARDED_BY(m_mutex); ///< Item about to insert const char* m_insertFilenamep VL_GUARDED_BY(m_mutex); ///< Filename about to insert int m_insertLineno VL_GUARDED_BY(m_mutex); ///< Line number about to insert // CONSTRUCTORS VerilatedCovImp() { m_insertp = NULL; m_insertFilenamep = NULL; m_insertLineno = 0; } VL_UNCOPYABLE(VerilatedCovImp); public: ~VerilatedCovImp() { clearGuts(); } static VerilatedCovImp& imp() VL_MT_SAFE { static VerilatedCovImp s_singleton; return s_singleton; } private: // PRIVATE METHODS int valueIndex(const std::string& value) VL_REQUIRES(m_mutex) { static int nextIndex = KEY_UNDEF + 1; ValueIndexMap::iterator iter = m_valueIndexes.find(value); if (iter != m_valueIndexes.end()) return iter->second; nextIndex++; assert(nextIndex > 0); // Didn't rollover m_valueIndexes.insert(std::make_pair(value, nextIndex)); m_indexValues.insert(std::make_pair(nextIndex, value)); return nextIndex; } static std::string dequote(const std::string& text) VL_PURE { // Quote any special characters std::string rtn; for (const char* pos = text.c_str(); *pos; ++pos) { if (!isprint(*pos) || *pos == '%' || *pos == '"') { char hex[10]; sprintf(hex, "%%%02X", pos[0]); rtn += hex; } else { rtn += *pos; } } return rtn; } static bool legalKey(const std::string& key) VL_PURE { // Because we compress long keys to a single letter, and // don't want applications to either get confused if they use // a letter differently, nor want them to rely on our compression... // (Considered using numeric keys, but will remain back compatible.) if (key.length() < 2) return false; if (key.length() == 2 && isdigit(key[1])) return false; return true; } static std::string keyValueFormatter(const std::string& key, const std::string& value) VL_PURE { std::string name; if (key.length() == 1 && isalpha(key[0])) { name += std::string("\001") + key; } else { name += std::string("\001") + dequote(key); } name += std::string("\002") + dequote(value); return name; } static std::string combineHier(const std::string& old, const std::string& add) VL_PURE { // (foo.a.x, foo.b.x) => foo.*.x // (foo.a.x, foo.b.y) => foo.* // (foo.a.x, foo.b) => foo.* if (old == add) return add; if (old.empty()) return add; if (add.empty()) return old; const char* a = old.c_str(); const char* b = add.c_str(); // Scan forward to first mismatch const char* apre = a; const char* bpre = b; while (*apre == *bpre) { apre++; bpre++; } // We used to backup and split on only .'s but it seems better to be verbose // and not assume . is the separator std::string prefix = std::string(a, apre - a); // Scan backward to last mismatch const char* apost = a + strlen(a) - 1; const char* bpost = b + strlen(b) - 1; while (*apost == *bpost && apost > apre && bpost > bpre) { apost--; bpost--; } // Forward to . so we have a whole word std::string suffix = *bpost ? std::string(bpost + 1) : ""; std::string out = prefix + "*" + suffix; // cout << "\nch pre="<zero(); } } // We assume there's always call to i/f/p in that order void inserti(VerilatedCovImpItem* itemp) VL_EXCLUDES(m_mutex) { const VerilatedLockGuard lock(m_mutex); assert(!m_insertp); m_insertp = itemp; } void insertf(const char* filenamep, int lineno) VL_EXCLUDES(m_mutex) { const VerilatedLockGuard lock(m_mutex); m_insertFilenamep = filenamep; m_insertLineno = lineno; } void insertp(const char* ckeyps[MAX_KEYS], const char* valps[MAX_KEYS]) VL_EXCLUDES(m_mutex) { const VerilatedLockGuard lock(m_mutex); assert(m_insertp); // First two key/vals are filename ckeyps[0] = "filename"; valps[0] = m_insertFilenamep; std::string linestr = vlCovCvtToStr(m_insertLineno); ckeyps[1] = "lineno"; valps[1] = linestr.c_str(); // Default page if not specified const char* fnstartp = m_insertFilenamep; while (const char* foundp = strchr(fnstartp, '/')) fnstartp = foundp + 1; const char* fnendp = fnstartp; for (; *fnendp && *fnendp != '.'; fnendp++) {} std::string page_default = "sp_user/" + std::string(fnstartp, fnendp - fnstartp); ckeyps[2] = "page"; valps[2] = page_default.c_str(); // Keys -> strings std::string keys[MAX_KEYS]; for (int i = 0; i < MAX_KEYS; ++i) { if (ckeyps[i] && ckeyps[i][0]) { keys[i] = ckeyps[i]; } } // Ignore empty keys for (int i = 0; i < MAX_KEYS; ++i) { if (!keys[i].empty()) { for (int j = i + 1; j < MAX_KEYS; ++j) { if (keys[i] == keys[j]) { // Duplicate key. Keep the last one keys[i] = ""; break; } } } } // Insert the values int addKeynum = 0; for (int i = 0; i < MAX_KEYS; ++i) { const std::string key = keys[i]; if (!keys[i].empty()) { const std::string val = valps[i]; // cout<<" "<<__FUNCTION__<<" "<m_keys[addKeynum] = valueIndex(key); m_insertp->m_vals[addKeynum] = valueIndex(val); addKeynum++; if (VL_UNCOVERABLE(!legalKey(key))) { std::string msg = ("%Error: Coverage keys of one character, or letter+digit are illegal: " + key); // LCOV_EXCL_LINE VL_FATAL_MT("", 0, "", msg.c_str()); } } } m_items.push_back(m_insertp); // Prepare for next m_insertp = NULL; } void write(const char* filename) VL_EXCLUDES(m_mutex) { Verilated::quiesce(); const VerilatedLockGuard lock(m_mutex); #ifndef VM_COVERAGE VL_FATAL_MT("", 0, "", "%Error: Called VerilatedCov::write when VM_COVERAGE disabled\n"); #endif selftest(); std::ofstream os(filename); if (os.fail()) { std::string msg = std::string("%Error: Can't write '") + filename + "'"; VL_FATAL_MT("", 0, "", msg.c_str()); return; } os << "# SystemC::Coverage-3\n"; // Build list of events; totalize if collapsing hierarchy typedef std::map > EventMap; EventMap eventCounts; for (ItemList::iterator it = m_items.begin(); it != m_items.end(); ++it) { VerilatedCovImpItem* itemp = *(it); std::string name; std::string hier; bool per_instance = false; for (int i = 0; i < MAX_KEYS; ++i) { if (itemp->m_keys[i] != KEY_UNDEF) { std::string key = VerilatedCovKey::shortKey(m_indexValues[itemp->m_keys[i]]); std::string val = m_indexValues[itemp->m_vals[i]]; if (key == VL_CIK_PER_INSTANCE) { if (val != "0") per_instance = true; } if (key == VL_CIK_HIER) { hier = val; } else { // Print it name += keyValueFormatter(key, val); } } } if (per_instance) { // Not collapsing hierarchies name += keyValueFormatter(VL_CIK_HIER, hier); hier = ""; } // Group versus point labels don't matter here, downstream // deals with it. Seems bad for sizing though and doesn't // allow easy addition of new group codes (would be // inefficient) // Find or insert the named event EventMap::iterator cit = eventCounts.find(name); if (cit != eventCounts.end()) { const std::string& oldhier = cit->second.first; cit->second.second += itemp->count(); cit->second.first = combineHier(oldhier, hier); } else { eventCounts.insert(std::make_pair(name, make_pair(hier, itemp->count()))); } } // Output body for (EventMap::const_iterator it = eventCounts.begin(); it != eventCounts.end(); ++it) { os << "C '" << std::dec; os << it->first; if (!it->second.first.empty()) os << keyValueFormatter(VL_CIK_HIER, it->second.first); os << "' " << it->second.second; os << std::endl; } } }; //============================================================================= // VerilatedCov void VerilatedCov::clear() VL_MT_SAFE { VerilatedCovImp::imp().clear(); } void VerilatedCov::clearNonMatch(const char* matchp) VL_MT_SAFE { VerilatedCovImp::imp().clearNonMatch(matchp); } void VerilatedCov::zero() VL_MT_SAFE { VerilatedCovImp::imp().zero(); } void VerilatedCov::write(const char* filenamep) VL_MT_SAFE { VerilatedCovImp::imp().write(filenamep); } void VerilatedCov::_inserti(vluint32_t* itemp) VL_MT_SAFE { VerilatedCovImp::imp().inserti(new VerilatedCoverItemSpec(itemp)); } void VerilatedCov::_inserti(vluint64_t* itemp) VL_MT_SAFE { VerilatedCovImp::imp().inserti(new VerilatedCoverItemSpec(itemp)); } void VerilatedCov::_insertf(const char* filename, int lineno) VL_MT_SAFE { VerilatedCovImp::imp().insertf(filename, lineno); } #define K(n) const char* key##n #define A(n) const char *key##n, const char *valp##n // Argument list #define C(n) key##n, valp##n // Calling argument list #define N(n) "", "" // Null argument list void VerilatedCov::_insertp(A(0), A(1), A(2), A(3), A(4), A(5), A(6), A(7), A(8), A(9), A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19), A(20), A(21), A(22), A(23), A(24), A(25), A(26), A(27), A(28), A(29)) VL_MT_SAFE { const char* keyps[VerilatedCovImpBase::MAX_KEYS] = {NULL, NULL, NULL, // filename,lineno,page key0, key1, key2, key3, key4, key5, key6, key7, key8, key9, key10, key11, key12, key13, key14, key15, key16, key17, key18, key19, key20, key21, key22, key23, key24, key25, key26, key27, key28, key29}; const char* valps[VerilatedCovImpBase::MAX_KEYS] = {NULL, NULL, NULL, // filename,lineno,page valp0, valp1, valp2, valp3, valp4, valp5, valp6, valp7, valp8, valp9, valp10, valp11, valp12, valp13, valp14, valp15, valp16, valp17, valp18, valp19, valp20, valp21, valp22, valp23, valp24, valp25, valp26, valp27, valp28, valp29}; VerilatedCovImp::imp().insertp(keyps, valps); } // And versions with fewer arguments (oh for a language with named parameters!) void VerilatedCov::_insertp(A(0), A(1), A(2), A(3), A(4), A(5), A(6), A(7), A(8), A(9)) VL_MT_SAFE { _insertp(C(0), C(1), C(2), C(3), C(4), C(5), C(6), C(7), C(8), C(9), N(10), N(11), N(12), N(13), N(14), N(15), N(16), N(17), N(18), N(19), N(20), N(21), N(22), N(23), N(24), N(25), N(26), N(27), N(28), N(29)); } void VerilatedCov::_insertp(A(0), A(1), A(2), A(3), A(4), A(5), A(6), A(7), A(8), A(9), A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19)) VL_MT_SAFE { _insertp(C(0), C(1), C(2), C(3), C(4), C(5), C(6), C(7), C(8), C(9), C(10), C(11), C(12), C(13), C(14), C(15), C(16), C(17), C(18), C(19), N(20), N(21), N(22), N(23), N(24), N(25), N(26), N(27), N(28), N(29)); } // Backward compatibility for Verilator void VerilatedCov::_insertp(A(0), A(1), K(2), int val2, K(3), int val3, K(4), const std::string& val4, A(5), A(6), A(7)) VL_MT_SAFE { std::string val2str = vlCovCvtToStr(val2); std::string val3str = vlCovCvtToStr(val3); _insertp(C(0), C(1), key2, val2str.c_str(), key3, val3str.c_str(), key4, val4.c_str(), C(5), C(6), C(7), N(8), N(9), N(10), N(11), N(12), N(13), N(14), N(15), N(16), N(17), N(18), N(19), N(20), N(21), N(22), N(23), N(24), N(25), N(26), N(27), N(28), N(29)); } #undef A #undef C #undef N #undef K verilator-4.038/include/verilated.h0000664000177100017500000032673013702326166017310 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: Common include for all Verilated C files /// /// This file is included automatically by Verilator at the top of /// all C++ files it generates. It contains standard macros and /// classes required by the Verilated code. /// /// Code available from: https://verilator.org /// //************************************************************************* #ifndef _VERILATED_H_ #define _VERILATED_H_ 1 ///< Header Guard // clang-format off #include "verilatedos.h" #if VM_SC # include "verilated_sc.h" // Get SYSTEMC_VERSION and time declarations #endif #include #include #include #include #include #include // avoided to reduce compile time // avoided and instead in verilated_heavy.h to reduce compile time // avoided and instead in verilated_heavy.h to reduce compile time #ifdef VL_THREADED # include # include # include #endif // Allow user to specify their own include file #ifdef VL_VERILATED_INCLUDE // cppcheck-suppress preprocessorErrorDirective # include VL_VERILATED_INCLUDE #endif // clang-format on //============================================================================= // Switches // clang-format off #if VM_TRACE // Verilator tracing requested # define WAVES 1 // Set backward compatibility flag #endif // Version check #if defined(SYSTEMC_VERSION) && (SYSTEMC_VERSION < 20111121) # warning "Verilator soon requires SystemC 2.3.*; see manual for deprecated other versions." #endif // clang-format on //========================================================================= // Basic types // clang-format off // P // Packed data of bit type (C/S/I/Q/W) typedef vluint8_t CData; ///< Verilated pack data, 1-8 bits typedef vluint16_t SData; ///< Verilated pack data, 9-16 bits typedef vluint32_t IData; ///< Verilated pack data, 17-32 bits typedef vluint64_t QData; ///< Verilated pack data, 33-64 bits typedef vluint32_t EData; ///< Verilated pack element of WData array typedef EData WData; ///< Verilated pack data, >64 bits, as an array // float F // No typedef needed; Verilator uses float // double D // No typedef needed; Verilator uses double // string N // No typedef needed; Verilator uses string // clang-format on typedef const WData* WDataInP; ///< Array input to a function typedef WData* WDataOutP; ///< Array output from a function class VerilatedEvalMsgQueue; class VerilatedScopeNameMap; class VerilatedVar; class VerilatedVarNameMap; class VerilatedVcd; class VerilatedVcdC; class VerilatedVcdSc; class VerilatedFst; class VerilatedFstC; enum VerilatedVarType { VLVT_UNKNOWN = 0, VLVT_PTR, // Pointer to something VLVT_UINT8, // AKA CData VLVT_UINT16, // AKA SData VLVT_UINT32, // AKA IData VLVT_UINT64, // AKA QData VLVT_WDATA, // AKA WData VLVT_STRING // C++ string }; enum VerilatedVarFlags { VLVD_0 = 0, // None VLVD_IN = 1, // == vpiInput VLVD_OUT = 2, // == vpiOutput VLVD_INOUT = 3, // == vpiInOut VLVD_NODIR = 5, // == vpiNoDirection VLVF_MASK_DIR = 7, // Bit mask for above directions // Flags VLVF_PUB_RD = (1 << 8), // Public readable VLVF_PUB_RW = (1 << 9), // Public writable VLVF_DPI_CLAY = (1 << 10) // DPI compatible C standard layout }; //========================================================================= /// Mutex and threading support /// Return current thread ID (or 0), not super fast, cache if needed extern vluint32_t VL_THREAD_ID() VL_MT_SAFE; #if VL_THREADED #define VL_LOCK_SPINS 50000 /// Number of times to spin for a mutex before relaxing /// Mutex, wrapped to allow -fthread_safety checks class VL_CAPABILITY("mutex") VerilatedMutex { private: std::mutex m_mutex; // Mutex public: VerilatedMutex() {} ~VerilatedMutex() {} const VerilatedMutex& operator!() const { return *this; } // For -fthread_safety /// Acquire/lock mutex void lock() VL_ACQUIRE() { // Try to acquire the lock by spinning. If the wait is short, // avoids a trap to the OS plus OS scheduler overhead. if (VL_LIKELY(try_lock())) return; // Short circuit loop for (int i = 0; i < VL_LOCK_SPINS; ++i) { if (VL_LIKELY(try_lock())) return; VL_CPU_RELAX(); } // Spinning hasn't worked, pay the cost of blocking. m_mutex.lock(); } /// Release/unlock mutex void unlock() VL_RELEASE() { m_mutex.unlock(); } /// Try to acquire mutex. Returns true on success, and false on failure. bool try_lock() VL_TRY_ACQUIRE(true) { return m_mutex.try_lock(); } }; /// Lock guard for mutex (ala std::unique_lock), wrapped to allow -fthread_safety checks class VL_SCOPED_CAPABILITY VerilatedLockGuard { VL_UNCOPYABLE(VerilatedLockGuard); private: VerilatedMutex& m_mutexr; public: explicit VerilatedLockGuard(VerilatedMutex& mutexr) VL_ACQUIRE(mutexr) : m_mutexr(mutexr) { m_mutexr.lock(); } ~VerilatedLockGuard() VL_RELEASE() { m_mutexr.unlock(); } void lock() VL_ACQUIRE() { m_mutexr.lock(); } void unlock() VL_RELEASE() { m_mutexr.unlock(); } }; #else // !VL_THREADED /// Empty non-threaded mutex to avoid #ifdefs in consuming code class VerilatedMutex { public: void lock() {} void unlock() {} }; /// Empty non-threaded lock guard to avoid #ifdefs in consuming code class VerilatedLockGuard { VL_UNCOPYABLE(VerilatedLockGuard); public: explicit VerilatedLockGuard(VerilatedMutex&) {} ~VerilatedLockGuard() {} void lock() {} void unlock() {} }; #endif // VL_THREADED /// Remember the calling thread at construction time, and make sure later calls use same thread class VerilatedAssertOneThread { // MEMBERS #if defined(VL_THREADED) && defined(VL_DEBUG) vluint32_t m_threadid; /// Thread that is legal public: // CONSTRUCTORS /// The constructor establishes the thread id for all later calls. /// If necessary, a different class could be made that inits it otherwise. VerilatedAssertOneThread() : m_threadid(VL_THREAD_ID()) {} ~VerilatedAssertOneThread() { check(); } // METHODS /// Check that the current thread ID is the same as the construction thread ID void check() VL_MT_UNSAFE_ONE { if (VL_UNCOVERABLE(m_threadid != VL_THREAD_ID())) { if (m_threadid == 0) { m_threadid = VL_THREAD_ID(); } else { fatal_different(); // LCOV_EXCL_LINE } } } void changeThread() { m_threadid = 0; } // Allow intentional change-of-thread static void fatal_different() VL_MT_SAFE; #else // !VL_THREADED || !VL_DEBUG public: void check() {} void changeThread() {} #endif }; //========================================================================= /// Base class for all Verilated module classes class VerilatedScope; class VerilatedModule { VL_UNCOPYABLE(VerilatedModule); private: const char* m_namep; ///< Module name public: explicit VerilatedModule(const char* namep); ///< Create module with given hierarchy name ~VerilatedModule(); const char* name() const { return m_namep; } ///< Return name of module }; //========================================================================= // Declare nets #define VL_SIG8(name, msb, lsb) CData name ///< Declare signal, 1-8 bits #define VL_SIG16(name, msb, lsb) SData name ///< Declare signal, 9-16 bits #define VL_SIG64(name, msb, lsb) QData name ///< Declare signal, 33-64 bits #define VL_SIG(name, msb, lsb) IData name ///< Declare signal, 17-32 bits #define VL_SIGW(name, msb, lsb, words) WData name[words] ///< Declare signal, 65+ bits #define VL_IN8(name, msb, lsb) CData name ///< Declare input signal, 1-8 bits #define VL_IN16(name, msb, lsb) SData name ///< Declare input signal, 9-16 bits #define VL_IN64(name, msb, lsb) QData name ///< Declare input signal, 33-64 bits #define VL_IN(name, msb, lsb) IData name ///< Declare input signal, 17-32 bits #define VL_INW(name, msb, lsb, words) WData name[words] ///< Declare input signal, 65+ bits #define VL_INOUT8(name, msb, lsb) CData name ///< Declare bidir signal, 1-8 bits #define VL_INOUT16(name, msb, lsb) SData name ///< Declare bidir signal, 9-16 bits #define VL_INOUT64(name, msb, lsb) QData name ///< Declare bidir signal, 33-64 bits #define VL_INOUT(name, msb, lsb) IData name ///< Declare bidir signal, 17-32 bits #define VL_INOUTW(name, msb, lsb, words) WData name[words] ///< Declare bidir signal, 65+ bits #define VL_OUT8(name, msb, lsb) CData name ///< Declare output signal, 1-8 bits #define VL_OUT16(name, msb, lsb) SData name ///< Declare output signal, 9-16 bits #define VL_OUT64(name, msb, lsb) QData name ///< Declare output signal, 33-64bits #define VL_OUT(name, msb, lsb) IData name ///< Declare output signal, 17-32 bits #define VL_OUTW(name, msb, lsb, words) WData name[words] ///< Declare output signal, 65+ bits #define VL_PIN_NOP(instname, pin, port) ///< Connect a pin, ala SP_PIN #define VL_CELL(instname, type) ///< Declare a cell, ala SP_CELL /// Declare a module, ala SC_MODULE #define VL_MODULE(modname) class modname : public VerilatedModule /// Constructor, ala SC_CTOR #define VL_CTOR(modname) modname(const char* __VCname = "") /// Constructor declaration for C++, ala SP_CTOR_IMPL #define VL_CTOR_IMP(modname) \ modname::modname(const char* __VCname) \ : VerilatedModule(__VCname) /// Constructor declaration for SystemC, ala SP_CTOR_IMPL #define VL_SC_CTOR_IMP(modname) modname::modname(sc_module_name) //========================================================================= // Functions overridable by user defines // (Internals however must use VL_PRINTF_MT, which calls these.) // clang-format off #ifndef VL_PRINTF # define VL_PRINTF printf ///< Print ala printf, called from main thread; redefine if desired #endif #ifndef VL_VPRINTF # define VL_VPRINTF vprintf ///< Print ala vprintf, called from main thread; redefine if desired #endif // clang-format on //=========================================================================== /// Verilator symbol table base class class VerilatedSyms { public: // But for internal use only #ifdef VL_THREADED VerilatedEvalMsgQueue* __Vm_evalMsgQp; #endif VerilatedSyms(); ~VerilatedSyms(); }; //=========================================================================== /// Verilator global class information class /// This class is initialized by main thread only. Reading post-init is thread safe. class VerilatedScope { public: typedef enum { SCOPE_MODULE, SCOPE_OTHER } Type; // Type of a scope, currently module is only interesting private: // Fastpath: VerilatedSyms* m_symsp; ///< Symbol table void** m_callbacksp; ///< Callback table pointer (Fastpath) int m_funcnumMax; ///< Maxium function number stored (Fastpath) // 4 bytes padding (on -m64), for rent. VerilatedVarNameMap* m_varsp; ///< Variable map const char* m_namep; ///< Scope name (Slowpath) const char* m_identifierp; ///< Identifier of scope (with escapes removed) vlsint8_t m_timeunit; ///< Timeunit in negative power-of-10 Type m_type; ///< Type of the scope public: // But internals only - called from VerilatedModule's VerilatedScope(); ~VerilatedScope(); void configure(VerilatedSyms* symsp, const char* prefixp, const char* suffixp, const char* identifier, vlsint8_t timeunit, const Type& type) VL_MT_UNSAFE; void exportInsert(int finalize, const char* namep, void* cb) VL_MT_UNSAFE; void varInsert(int finalize, const char* namep, void* datap, bool isParam, VerilatedVarType vltype, int vlflags, int dims, ...) VL_MT_UNSAFE; // ACCESSORS const char* name() const { return m_namep; } const char* identifier() const { return m_identifierp; } vlsint8_t timeunit() const { return m_timeunit; } inline VerilatedSyms* symsp() const { return m_symsp; } VerilatedVar* varFind(const char* namep) const VL_MT_SAFE_POSTINIT; VerilatedVarNameMap* varsp() const VL_MT_SAFE_POSTINIT { return m_varsp; } void scopeDump() const; void* exportFindError(int funcnum) const; static void* exportFindNullError(int funcnum) VL_MT_SAFE; static inline void* exportFind(const VerilatedScope* scopep, int funcnum) VL_MT_SAFE { if (VL_UNLIKELY(!scopep)) return exportFindNullError(funcnum); if (VL_LIKELY(funcnum < scopep->m_funcnumMax)) { // m_callbacksp must be declared, as Max'es are > 0 return scopep->m_callbacksp[funcnum]; } else { // LCOV_EXCL_LINE return scopep->exportFindError(funcnum); // LCOV_EXCL_LINE } } Type type() const { return m_type; } }; class VerilatedHierarchy { public: static void add(VerilatedScope* fromp, VerilatedScope* top); }; //=========================================================================== /// Verilator global static information class class Verilated { // MEMBERS // Slow path variables static VerilatedMutex m_mutex; ///< Mutex for s_s/s_ns members, when VL_THREADED static struct Serialized { // All these members serialized/deserialized // Fast path int s_debug; ///< See accessors... only when VL_DEBUG set bool s_calcUnusedSigs; ///< Waves file on, need all signals calculated bool s_gotFinish; ///< A $finish statement executed bool s_assertOn; ///< Assertions are enabled bool s_fatalOnVpiError; ///< Stop on vpi error/unsupported // Slow path vlsint8_t s_timeunit; ///< Time unit as 0..15 vlsint8_t s_timeprecision; ///< Time precision as 0..15 int s_errorCount; ///< Number of errors int s_errorLimit; ///< Stop on error number int s_randReset; ///< Random reset: 0=all 0s, 1=all 1s, 2=random int s_randSeed; ///< Random seed: 0=random Serialized(); ~Serialized() {} } s_s; static struct NonSerialized { // Non-serialized information // These are reloaded from on command-line settings, so do not need to persist // Fast path vluint64_t s_profThreadsStart; ///< +prof+threads starting time vluint32_t s_profThreadsWindow; ///< +prof+threads window size // Slow path const char* s_profThreadsFilenamep; ///< +prof+threads filename NonSerialized(); ~NonSerialized(); } s_ns; // no need to be save-restored (serialized) the // assumption is that the restore is allowed to pass different arguments static struct CommandArgValues { VerilatedMutex m_argMutex; ///< Mutex for s_args members, when VL_THREADED int argc; const char** argv; CommandArgValues() : argc(0) , argv(NULL) {} ~CommandArgValues() {} } s_args; // Not covered by mutex, as per-thread static VL_THREAD_LOCAL struct ThreadLocal { #ifdef VL_THREADED vluint32_t t_mtaskId; ///< Current mtask# executing on this thread vluint32_t t_endOfEvalReqd; ///< Messages may be pending, thread needs endOf-eval calls #endif const VerilatedScope* t_dpiScopep; ///< DPI context scope const char* t_dpiFilename; ///< DPI context filename int t_dpiLineno; ///< DPI context line number ThreadLocal(); ~ThreadLocal(); } t_s; private: // CONSTRUCTORS VL_UNCOPYABLE(Verilated); public: // METHODS - User called /// Select initial value of otherwise uninitialized signals. //// /// 0 = Set to zeros /// 1 = Set all bits to one /// 2 = Randomize all bits static void randReset(int val) VL_MT_SAFE; static int randReset() VL_MT_SAFE { return s_s.s_randReset; } ///< Return randReset value static void randSeed(int val) VL_MT_SAFE; static int randSeed() VL_MT_SAFE { return s_s.s_randSeed; } ///< Return randSeed value /// Enable debug of internal verilated code static void debug(int level) VL_MT_SAFE; #ifdef VL_DEBUG /// Return debug level /// When multithreaded this may not immediately react to another thread /// changing the level (no mutex) static inline int debug() VL_MT_SAFE { return s_s.s_debug; } #else /// Return constant 0 debug level, so C++'s optimizer rips up static inline int debug() VL_PURE { return 0; } #endif /// Enable calculation of unused signals static void calcUnusedSigs(bool flag) VL_MT_SAFE; static bool calcUnusedSigs() VL_MT_SAFE { ///< Return calcUnusedSigs value return s_s.s_calcUnusedSigs; } /// Current number of errors/assertions static void errorCount(int val) VL_MT_SAFE; static void errorCountInc() VL_MT_SAFE; static int errorCount() VL_MT_SAFE { return s_s.s_errorCount; } /// Set number of errors/assertions before stop static void errorLimit(int val) VL_MT_SAFE; static int errorLimit() VL_MT_SAFE { return s_s.s_errorLimit; } /// Did the simulation $finish? static void gotFinish(bool flag) VL_MT_SAFE; static bool gotFinish() VL_MT_SAFE { return s_s.s_gotFinish; } ///< Return if got a $finish /// Allow traces to at some point be enabled (disables some optimizations) static void traceEverOn(bool flag) VL_MT_SAFE { if (flag) { calcUnusedSigs(flag); } } /// Enable/disable assertions static void assertOn(bool flag) VL_MT_SAFE; static bool assertOn() VL_MT_SAFE { return s_s.s_assertOn; } /// Enable/disable vpi fatal static void fatalOnVpiError(bool flag) VL_MT_SAFE; static bool fatalOnVpiError() VL_MT_SAFE { return s_s.s_fatalOnVpiError; } /// Time handling static int timeunit() VL_MT_SAFE { return -s_s.s_timeunit; } static const char* timeunitString() VL_MT_SAFE; static void timeunit(int value) VL_MT_SAFE; static int timeprecision() VL_MT_SAFE { return -s_s.s_timeprecision; } static const char* timeprecisionString() VL_MT_SAFE; static void timeprecision(int value) VL_MT_SAFE; /// --prof-threads related settings static void profThreadsStart(vluint64_t flag) VL_MT_SAFE; static vluint64_t profThreadsStart() VL_MT_SAFE { return s_ns.s_profThreadsStart; } static void profThreadsWindow(vluint64_t flag) VL_MT_SAFE; static vluint32_t profThreadsWindow() VL_MT_SAFE { return s_ns.s_profThreadsWindow; } static void profThreadsFilenamep(const char* flagp) VL_MT_SAFE; static const char* profThreadsFilenamep() VL_MT_SAFE { return s_ns.s_profThreadsFilenamep; } typedef void (*VoidPCb)(void*); // Callback type for below /// Callbacks to run on global flush static void addFlushCb(VoidPCb cb, void* datap) VL_MT_SAFE; static void removeFlushCb(VoidPCb cb, void* datap) VL_MT_SAFE; static void runFlushCallbacks() VL_MT_SAFE; /// Callbacks to run prior to termination static void addExitCb(VoidPCb cb, void* datap) VL_MT_SAFE; static void removeExitCb(VoidPCb cb, void* datap) VL_MT_SAFE; static void runExitCallbacks() VL_MT_SAFE; /// Record command line arguments, for retrieval by $test$plusargs/$value$plusargs, /// and for parsing +verilator+ run-time arguments. /// This should be called before the first model is created. static void commandArgs(int argc, const char** argv) VL_MT_SAFE; static void commandArgs(int argc, char** argv) VL_MT_SAFE { commandArgs(argc, const_cast(argv)); } static void commandArgsAdd(int argc, const char** argv); static CommandArgValues* getCommandArgs() VL_MT_SAFE { return &s_args; } /// Match plusargs with a given prefix. Returns static char* valid only for a single call static const char* commandArgsPlusMatch(const char* prefixp) VL_MT_SAFE; /// Produce name & version for (at least) VPI static const char* productName() VL_PURE; static const char* productVersion() VL_PURE; /// Convenience OS utilities static void mkdir(const char* dirname) VL_MT_UNSAFE; /// When multithreaded, quiesce the model to prepare for trace/saves/coverage /// This may only be called when no locks are held. static void quiesce() VL_MT_SAFE; /// For debugging, print much of the Verilator internal state. /// The output of this function may change in future /// releases - contact the authors before production use. static void internalsDump() VL_MT_SAFE; /// For debugging, print text list of all scope names with /// dpiImport/Export context. This function may change in future /// releases - contact the authors before production use. static void scopesDump() VL_MT_SAFE; public: // METHODS - INTERNAL USE ONLY (but public due to what uses it) // Internal: Create a new module name by concatenating two strings static const char* catName(const char* n1, const char* n2, const char* delimiter = "."); // Returns static data // Internal: Throw signal assertion static void nullPointerError(const char* filename, int linenum) VL_ATTR_NORETURN VL_MT_SAFE; static void overWidthError(const char* signame) VL_ATTR_NORETURN VL_MT_SAFE; // Internal: Find scope static const VerilatedScope* scopeFind(const char* namep) VL_MT_SAFE; static const VerilatedScopeNameMap* scopeNameMap() VL_MT_SAFE; // Internal: Get and set DPI context static const VerilatedScope* dpiScope() VL_MT_SAFE { return t_s.t_dpiScopep; } static void dpiScope(const VerilatedScope* scopep) VL_MT_SAFE { t_s.t_dpiScopep = scopep; } static void dpiContext(const VerilatedScope* scopep, const char* filenamep, int lineno) VL_MT_SAFE { t_s.t_dpiScopep = scopep; t_s.t_dpiFilename = filenamep; t_s.t_dpiLineno = lineno; } static void dpiClearContext() VL_MT_SAFE { t_s.t_dpiScopep = NULL; } static bool dpiInContext() VL_MT_SAFE { return t_s.t_dpiScopep != NULL; } static const char* dpiFilenamep() VL_MT_SAFE { return t_s.t_dpiFilename; } static int dpiLineno() VL_MT_SAFE { return t_s.t_dpiLineno; } static int exportFuncNum(const char* namep) VL_MT_SAFE; static size_t serialized1Size() VL_PURE { return sizeof(s_s); } static void* serialized1Ptr() VL_MT_UNSAFE { return &s_s; } // Unsafe, for Serialize only static size_t serialized2Size() VL_PURE; static void* serialized2Ptr() VL_MT_UNSAFE; #ifdef VL_THREADED /// Set the mtaskId, called when an mtask starts static void mtaskId(vluint32_t id) VL_MT_SAFE { t_s.t_mtaskId = id; } static vluint32_t mtaskId() VL_MT_SAFE { return t_s.t_mtaskId; } static void endOfEvalReqdInc() VL_MT_SAFE { ++t_s.t_endOfEvalReqd; } static void endOfEvalReqdDec() VL_MT_SAFE { --t_s.t_endOfEvalReqd; } /// Called at end of each thread mtask, before finishing eval static void endOfThreadMTask(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE { if (VL_UNLIKELY(t_s.t_endOfEvalReqd)) { endOfThreadMTaskGuts(evalMsgQp); } } /// Called at end of eval loop static void endOfEval(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE { // It doesn't work to set endOfEvalReqd on the threadpool thread // and then check it on the eval thread since it's thread local. // It should be ok to call into endOfEvalGuts, it returns immediately // if there are no transactions. endOfEvalGuts(evalMsgQp); } #endif private: #ifdef VL_THREADED static void endOfThreadMTaskGuts(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE; static void endOfEvalGuts(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE; #endif }; //========================================================================= // Extern functions -- User may override -- See verilated.cpp /// Routine to call for $finish /// User code may wish to replace this function, to do so, define VL_USER_FINISH. /// This code does not have to be thread safe. /// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this. extern void vl_finish(const char* filename, int linenum, const char* hier); /// Routine to call for $stop /// User code may wish to replace this function, to do so, define VL_USER_STOP. /// This code does not have to be thread safe. /// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this. extern void vl_stop(const char* filename, int linenum, const char* hier); /// Routine to call for a couple of fatal messages /// User code may wish to replace this function, to do so, define VL_USER_FATAL. /// This code does not have to be thread safe. /// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this. extern void vl_fatal(const char* filename, int linenum, const char* hier, const char* msg); //========================================================================= // Extern functions -- Slow path /// Multithread safe wrapper for calls to $finish extern void VL_FINISH_MT(const char* filename, int linenum, const char* hier) VL_MT_SAFE; /// Multithread safe wrapper for calls to $stop extern void VL_STOP_MT(const char* filename, int linenum, const char* hier, bool maybe = true) VL_MT_SAFE; /// Multithread safe wrapper to call for a couple of fatal messages extern void VL_FATAL_MT(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_SAFE; // clang-format off /// Print a string, multithread safe. Eventually VL_PRINTF will get called. #ifdef VL_THREADED extern void VL_PRINTF_MT(const char* formatp, ...) VL_ATTR_PRINTF(1) VL_MT_SAFE; #else # define VL_PRINTF_MT VL_PRINTF // The following parens will take care of themselves #endif // clang-format on /// Print a debug message from internals with standard prefix, with printf style format extern void VL_DBG_MSGF(const char* formatp, ...) VL_ATTR_PRINTF(1) VL_MT_SAFE; extern IData VL_RANDOM_I(int obits); ///< Randomize a signal extern QData VL_RANDOM_Q(int obits); ///< Randomize a signal extern WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp); ///< Randomize a signal /// Init time only, so slow is fine extern IData VL_RAND_RESET_I(int obits); ///< Random reset a signal extern QData VL_RAND_RESET_Q(int obits); ///< Random reset a signal extern WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp); ///< Random reset a signal /// Zero reset a signal (slow - else use VL_ZERO_W) extern WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp); #if VL_THREADED /// Return high-precision counter for profiling, or 0x0 if not available inline QData VL_RDTSC_Q() { vluint64_t val; VL_RDTSC(val); return val; } #endif extern void VL_PRINTTIMESCALE(const char* namep, const char* timeunitp) VL_MT_SAFE; /// Math extern WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, bool is_modulus); /// File I/O extern IData VL_FGETS_IXI(int obits, void* destp, IData fpi); extern void VL_FFLUSH_I(IData fdi); extern IData VL_FSEEK_I(IData fdi, IData offset, IData origin); extern IData VL_FTELL_I(IData fdi); extern void VL_FCLOSE_I(IData fdi); extern IData VL_FREAD_I(int width, int array_lsb, int array_size, void* memp, IData fpi, IData start, IData count); extern void VL_WRITEF(const char* formatp, ...); extern void VL_FWRITEF(IData fpi, const char* formatp, ...); extern IData VL_FSCANF_IX(IData fpi, const char* formatp, ...); extern IData VL_SSCANF_IIX(int lbits, IData ld, const char* formatp, ...); extern IData VL_SSCANF_IQX(int lbits, QData ld, const char* formatp, ...); extern IData VL_SSCANF_IWX(int lbits, WDataInP lwp, const char* formatp, ...); extern void VL_SFORMAT_X(int obits, CData& destr, const char* formatp, ...); extern void VL_SFORMAT_X(int obits, SData& destr, const char* formatp, ...); extern void VL_SFORMAT_X(int obits, IData& destr, const char* formatp, ...); extern void VL_SFORMAT_X(int obits, QData& destr, const char* formatp, ...); extern void VL_SFORMAT_X(int obits, void* destp, const char* formatp, ...); extern IData VL_SYSTEM_IW(int lhswords, WDataInP lhsp); extern IData VL_SYSTEM_IQ(QData lhs); inline IData VL_SYSTEM_II(IData lhs) VL_MT_SAFE { return VL_SYSTEM_IQ(lhs); } extern IData VL_TESTPLUSARGS_I(const char* formatp); extern const char* vl_mc_scan_plusargs(const char* prefixp); // PLIish //========================================================================= // Base macros /// Return true if data[bit] set; not 0/1 return, but 0/non-zero return. #define VL_BITISSET_I(data, bit) ((data) & (VL_UL(1) << VL_BITBIT_I(bit))) #define VL_BITISSET_Q(data, bit) ((data) & (1ULL << VL_BITBIT_Q(bit))) #define VL_BITISSET_E(data, bit) ((data) & (VL_EUL(1) << VL_BITBIT_E(bit))) #define VL_BITISSET_W(data, bit) ((data)[VL_BITWORD_E(bit)] & (VL_EUL(1) << VL_BITBIT_E(bit))) #define VL_BITISSETLIMIT_W(data, width, bit) (((bit) < (width)) && VL_BITISSET_W(data, bit)) /// Shift appropriate word by bit. Does not account for wrapping between two words #define VL_BITRSHIFT_W(data, bit) ((data)[VL_BITWORD_E(bit)] >> VL_BITBIT_E(bit)) /// Create two 32-bit words from quadword /// WData is always at least 2 words; does not clean upper bits #define VL_SET_WQ(owp, data) \ do { \ (owp)[0] = static_cast(data); \ (owp)[1] = static_cast((data) >> VL_EDATASIZE); \ } while (false) #define VL_SET_WI(owp, data) \ do { \ (owp)[0] = static_cast(data); \ (owp)[1] = 0; \ } while (false) #define VL_SET_QW(lwp) \ ((static_cast((lwp)[0])) \ | (static_cast((lwp)[1]) << (static_cast(VL_EDATASIZE)))) #define _VL_SET_QII(ld, rd) ((static_cast(ld) << 32ULL) | static_cast(rd)) /// Return FILE* from IData extern FILE* VL_CVT_I_FP(IData lhs) VL_MT_SAFE; // clang-format off // Use a union to avoid cast-to-different-size warnings /// Return void* from QData static inline void* VL_CVT_Q_VP(QData lhs) VL_PURE { union { void* fp; QData q; } u; u.q = lhs; return u.fp; } /// Return QData from void* static inline QData VL_CVT_VP_Q(void* fp) VL_PURE { union { void* fp; QData q; } u; u.q = 0; u.fp = fp; return u.q; } /// Return double from QData (bits, not numerically) static inline double VL_CVT_D_Q(QData lhs) VL_PURE { union { double d; QData q; } u; u.q = lhs; return u.d; } /// Return QData from double (bits, not numerically) static inline QData VL_CVT_Q_D(double lhs) VL_PURE { union { double d; QData q; } u; u.d = lhs; return u.q; } // clang-format on /// Return double from QData (numeric) static inline double VL_ITOR_D_I(IData lhs) VL_PURE { return static_cast(static_cast(lhs)); } /// Return QData from double (numeric) static inline IData VL_RTOI_I_D(double lhs) VL_PURE { return static_cast(VL_TRUNC(lhs)); } // Sign extend such that if MSB set, we get ffff_ffff, else 0s // (Requires clean input) #define VL_SIGN_I(nbits, lhs) ((lhs) >> VL_BITBIT_I((nbits)-VL_UL(1))) #define VL_SIGN_Q(nbits, lhs) ((lhs) >> VL_BITBIT_Q((nbits)-1ULL)) #define VL_SIGN_E(nbits, lhs) ((lhs) >> VL_BITBIT_E((nbits)-VL_EUL(1))) #define VL_SIGN_W(nbits, rwp) \ ((rwp)[VL_BITWORD_E((nbits)-VL_EUL(1))] >> VL_BITBIT_E((nbits)-VL_EUL(1))) #define VL_SIGNONES_E(nbits, lhs) (-(VL_SIGN_E(nbits, lhs))) // Sign bit extended up to MSB, doesn't include unsigned portion // Optimization bug in GCC 3.3 returns different bitmasks to later states for static inline IData VL_EXTENDSIGN_I(int lbits, IData lhs) VL_PURE { return (-((lhs) & (VL_UL(1) << (lbits - 1)))); } static inline QData VL_EXTENDSIGN_Q(int lbits, QData lhs) VL_PURE { return (-((lhs) & (1ULL << (lbits - 1)))); } // Debugging prints extern void _VL_DEBUG_PRINT_W(int lbits, WDataInP iwp); //========================================================================= // Pli macros extern int VL_TIME_STR_CONVERT(const char* strp) VL_PURE; // These are deprecated and used only to establish the default precision/units. // Use Verilator timescale-override for better control. // clang-format off #ifndef VL_TIME_PRECISION # ifdef VL_TIME_PRECISION_STR # define VL_TIME_PRECISION VL_TIME_STR_CONVERT(VL_STRINGIFY(VL_TIME_PRECISION_STR)) # else # define VL_TIME_PRECISION (-12) ///< Timescale default units if not in Verilog - picoseconds # endif #endif #ifndef VL_TIME_UNIT # ifdef VL_TIME_UNIT_STR # define VL_TIME_UNIT VL_TIME_STR_CONVERT(VL_STRINGIFY(VL_TIME_PRECISION_STR)) # else # define VL_TIME_UNIT (-12) ///< Timescale default units if not in Verilog - picoseconds # endif #endif /// Return current simulation time #if defined(SYSTEMC_VERSION) # if SYSTEMC_VERSION > 20011000 // Already defined: extern sc_time sc_time_stamp(); inline vluint64_t vl_time_stamp64() { return sc_time_stamp().value(); } # else // Before SystemC changed to integral time representation // Already defined: extern double sc_time_stamp(); inline vluint64_t vl_time_stamp64() { return static_cast(sc_time_stamp()); } # endif #else // Non-SystemC # ifdef VL_TIME_STAMP64 extern vluint64_t vl_time_stamp64(); # else extern double sc_time_stamp(); // Verilator 4.032 and newer inline vluint64_t vl_time_stamp64() { return static_cast(sc_time_stamp()); } # endif #endif #define VL_TIME_I() (static_cast(vl_time_stamp64())) #define VL_TIME_Q() (static_cast(vl_time_stamp64())) #define VL_TIME_D() (static_cast(vl_time_stamp64())) /// Time scaled from 1-per-precision into a module's time units ("Unit"-ed, not "United") // Optimized assuming scale is always constant. // Can't use multiply in Q flavor, as might lose precision #define VL_TIME_UNITED_Q(scale) (VL_TIME_Q() / static_cast(scale)) #define VL_TIME_UNITED_D(scale) (VL_TIME_D() / static_cast(scale)) /// Time imported from units to time precision double vl_time_multiplier(int scale); /// Evaluate expression if debug enabled #ifdef VL_DEBUG # define VL_DEBUG_IF(text) \ do { \ if (VL_UNLIKELY(Verilated::debug())) {text} \ } while (false) #else // We intentionally do not compile the text to improve compile speed # define VL_DEBUG_IF(text) do {} while (false) #endif /// Collect coverage analysis for this line #ifndef SP_AUTO_COVER3 # define SP_AUTO_COVER3(what,file,line) #endif // clang-format on //========================================================================= // Functional macros/routines // These all take the form // VL_func_IW(bits, bits, op, op) // VL_func_WW(bits, bits, out, op, op) // The I/W indicates if it's a integer or wide for the output and each operand. // The bits indicate the bit width of the output and each operand. // If wide output, a temporary storage location is specified. //=================================================================== // SETTING OPERATORS // Output clean // EMIT_RULE: VL_CLEAN: oclean=clean; obits=lbits; #define VL_CLEAN_II(obits, lbits, lhs) ((lhs)&VL_MASK_I(obits)) #define VL_CLEAN_QQ(obits, lbits, lhs) ((lhs)&VL_MASK_Q(obits)) // EMIT_RULE: VL_ASSIGNCLEAN: oclean=clean; obits==lbits; #define VL_ASSIGNCLEAN_W(obits, owp, lwp) VL_CLEAN_WW((obits), (obits), (owp), (lwp)) static inline WDataOutP _VL_CLEAN_INPLACE_W(int obits, WDataOutP owp) VL_MT_SAFE { int words = VL_WORDS_I(obits); owp[words - 1] &= VL_MASK_E(obits); return owp; } static inline WDataOutP VL_CLEAN_WW(int obits, int, WDataOutP owp, WDataInP lwp) VL_MT_SAFE { int words = VL_WORDS_I(obits); for (int i = 0; (i < (words - 1)); ++i) owp[i] = lwp[i]; owp[words - 1] = lwp[words - 1] & VL_MASK_E(obits); return owp; } static inline WDataOutP VL_ZERO_W(int obits, WDataOutP owp) VL_MT_SAFE { int words = VL_WORDS_I(obits); for (int i = 0; i < words; ++i) owp[i] = 0; return owp; } static inline WDataOutP VL_ALLONES_W(int obits, WDataOutP owp) VL_MT_SAFE { int words = VL_WORDS_I(obits); for (int i = 0; i < (words - 1); ++i) owp[i] = ~VL_EUL(0); owp[words - 1] = VL_MASK_E(obits); return owp; } // EMIT_RULE: VL_ASSIGN: oclean=rclean; obits==lbits; // For now, we always have a clean rhs. // Note: If a ASSIGN isn't clean, use VL_ASSIGNCLEAN instead to do the same thing. static inline WDataOutP VL_ASSIGN_W(int obits, WDataOutP owp, WDataInP lwp) VL_MT_SAFE { int words = VL_WORDS_I(obits); for (int i = 0; i < words; ++i) owp[i] = lwp[i]; return owp; } // EMIT_RULE: VL_ASSIGNBIT: rclean=clean; static inline void VL_ASSIGNBIT_II(int, int bit, CData& lhsr, IData rhs) VL_PURE { lhsr = ((lhsr & ~(VL_UL(1) << VL_BITBIT_I(bit))) | (rhs << VL_BITBIT_I(bit))); } static inline void VL_ASSIGNBIT_II(int, int bit, SData& lhsr, IData rhs) VL_PURE { lhsr = ((lhsr & ~(VL_UL(1) << VL_BITBIT_I(bit))) | (rhs << VL_BITBIT_I(bit))); } static inline void VL_ASSIGNBIT_II(int, int bit, IData& lhsr, IData rhs) VL_PURE { lhsr = ((lhsr & ~(VL_UL(1) << VL_BITBIT_I(bit))) | (rhs << VL_BITBIT_I(bit))); } static inline void VL_ASSIGNBIT_QI(int, int bit, QData& lhsr, QData rhs) VL_PURE { lhsr = ((lhsr & ~(1ULL << VL_BITBIT_Q(bit))) | (static_cast(rhs) << VL_BITBIT_Q(bit))); } static inline void VL_ASSIGNBIT_WI(int, int bit, WDataOutP owp, IData rhs) VL_MT_SAFE { EData orig = owp[VL_BITWORD_E(bit)]; owp[VL_BITWORD_E(bit)] = ((orig & ~(VL_EUL(1) << VL_BITBIT_E(bit))) | (static_cast(rhs) << VL_BITBIT_E(bit))); } // Alternative form that is an instruction faster when rhs is constant one. static inline void VL_ASSIGNBIT_IO(int, int bit, CData& lhsr, IData) VL_PURE { lhsr = (lhsr | (VL_UL(1) << VL_BITBIT_I(bit))); } static inline void VL_ASSIGNBIT_IO(int, int bit, SData& lhsr, IData) VL_PURE { lhsr = (lhsr | (VL_UL(1) << VL_BITBIT_I(bit))); } static inline void VL_ASSIGNBIT_IO(int, int bit, IData& lhsr, IData) VL_PURE { lhsr = (lhsr | (VL_UL(1) << VL_BITBIT_I(bit))); } static inline void VL_ASSIGNBIT_QO(int, int bit, QData& lhsr, IData) VL_PURE { lhsr = (lhsr | (1ULL << VL_BITBIT_Q(bit))); } static inline void VL_ASSIGNBIT_WO(int, int bit, WDataOutP owp, IData) VL_MT_SAFE { EData orig = owp[VL_BITWORD_E(bit)]; owp[VL_BITWORD_E(bit)] = (orig | (VL_EUL(1) << VL_BITBIT_E(bit))); } //=================================================================== // SYSTEMC OPERATORS // Copying verilog format to systemc integers and bit vectors. // Get a SystemC variable #define VL_ASSIGN_ISI(obits, vvar, svar) \ { (vvar) = VL_CLEAN_II((obits), (obits), (svar).read()); } #define VL_ASSIGN_QSQ(obits, vvar, svar) \ { (vvar) = VL_CLEAN_QQ((obits), (obits), (svar).read()); } #define VL_ASSIGN_ISW(obits, od, svar) \ { (od) = ((svar).read().get_word(0)) & VL_MASK_I(obits); } #define VL_ASSIGN_QSW(obits, od, svar) \ { \ (od) = ((static_cast((svar).read().get_word(1))) << VL_IDATASIZE \ | (svar).read().get_word(0)) \ & VL_MASK_Q(obits); \ } #define VL_ASSIGN_WSW(obits, owp, svar) \ { \ int words = VL_WORDS_I(obits); \ for (int i = 0; i < words; ++i) (owp)[i] = (svar).read().get_word(i); \ (owp)[words - 1] &= VL_MASK_E(obits); \ } #define VL_ASSIGN_ISU(obits, vvar, svar) \ { (vvar) = VL_CLEAN_II((obits), (obits), (svar).read().to_uint()); } #define VL_ASSIGN_QSU(obits, vvar, svar) \ { (vvar) = VL_CLEAN_QQ((obits), (obits), (svar).read().to_uint64()); } #define VL_ASSIGN_WSB(obits, owp, svar) \ { \ int words = VL_WORDS_I(obits); \ sc_biguint<(obits)> _butemp = (svar).read(); \ for (int i = 0; i < words; ++i) { \ int msb = ((i + 1) * VL_IDATASIZE) - 1; \ msb = (msb >= (obits)) ? ((obits)-1) : msb; \ (owp)[i] = _butemp.range(msb, i * VL_IDATASIZE).to_uint(); \ } \ (owp)[words - 1] &= VL_MASK_E(obits); \ } // Copying verilog format from systemc integers and bit vectors. // Set a SystemC variable #define VL_ASSIGN_SII(obits, svar, vvar) \ { (svar).write(vvar); } #define VL_ASSIGN_SQQ(obits, svar, vvar) \ { (svar).write(vvar); } #define VL_ASSIGN_SWI(obits, svar, rd) \ { \ sc_bv<(obits)> _bvtemp; \ _bvtemp.set_word(0, (rd)); \ (svar).write(_bvtemp); \ } #define VL_ASSIGN_SWQ(obits, svar, rd) \ { \ sc_bv<(obits)> _bvtemp; \ _bvtemp.set_word(0, static_cast(rd)); \ _bvtemp.set_word(1, static_cast((rd) >> VL_IDATASIZE)); \ (svar).write(_bvtemp); \ } #define VL_ASSIGN_SWW(obits, svar, rwp) \ { \ sc_bv<(obits)> _bvtemp; \ for (int i = 0; i < VL_WORDS_I(obits); ++i) _bvtemp.set_word(i, (rwp)[i]); \ (svar).write(_bvtemp); \ } #define VL_ASSIGN_SUI(obits, svar, rd) \ { (svar).write(rd); } #define VL_ASSIGN_SUQ(obits, svar, rd) \ { (svar).write(rd); } #define VL_ASSIGN_SBI(obits, svar, rd) \ { (svar).write(rd); } #define VL_ASSIGN_SBQ(obits, svar, rd) \ { (svar).write(rd); } #define VL_ASSIGN_SBW(obits, svar, rwp) \ { \ sc_biguint<(obits)> _butemp; \ for (int i = 0; i < VL_WORDS_I(obits); ++i) { \ int msb = ((i + 1) * VL_IDATASIZE) - 1; \ msb = (msb >= (obits)) ? ((obits)-1) : msb; \ _butemp.range(msb, i* VL_IDATASIZE) = (rwp)[i]; \ } \ (svar).write(_butemp); \ } //=================================================================== // Extending sizes // CAREFUL, we're width changing, so obits!=lbits // Right must be clean because otherwise size increase would pick up bad bits // EMIT_RULE: VL_EXTEND: oclean=clean; rclean==clean; #define VL_EXTEND_II(obits, lbits, lhs) ((lhs)) #define VL_EXTEND_QI(obits, lbits, lhs) (static_cast(lhs)) #define VL_EXTEND_QQ(obits, lbits, lhs) ((lhs)) static inline WDataOutP VL_EXTEND_WI(int obits, int, WDataOutP owp, IData ld) VL_MT_SAFE { // Note for extracts that obits != lbits owp[0] = ld; for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = 0; return owp; } static inline WDataOutP VL_EXTEND_WQ(int obits, int, WDataOutP owp, QData ld) VL_MT_SAFE { VL_SET_WQ(owp, ld); for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = 0; return owp; } static inline WDataOutP VL_EXTEND_WW(int obits, int lbits, WDataOutP owp, WDataInP lwp) VL_MT_SAFE { for (int i = 0; i < VL_WORDS_I(lbits); ++i) owp[i] = lwp[i]; for (int i = VL_WORDS_I(lbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0; return owp; } // EMIT_RULE: VL_EXTENDS: oclean=*dirty*; obits=lbits; // Sign extension; output dirty static inline IData VL_EXTENDS_II(int, int lbits, IData lhs) VL_PURE { return VL_EXTENDSIGN_I(lbits, lhs) | lhs; } static inline QData VL_EXTENDS_QI(int, int lbits, QData lhs /*Q_as_need_extended*/) VL_PURE { return VL_EXTENDSIGN_Q(lbits, lhs) | lhs; } static inline QData VL_EXTENDS_QQ(int, int lbits, QData lhs) VL_PURE { return VL_EXTENDSIGN_Q(lbits, lhs) | lhs; } static inline WDataOutP VL_EXTENDS_WI(int obits, int lbits, WDataOutP owp, IData ld) VL_MT_SAFE { EData sign = VL_SIGNONES_E(lbits, static_cast(ld)); owp[0] = ld | (sign & ~VL_MASK_E(lbits)); for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = sign; return owp; } static inline WDataOutP VL_EXTENDS_WQ(int obits, int lbits, WDataOutP owp, QData ld) VL_MT_SAFE { VL_SET_WQ(owp, ld); EData sign = VL_SIGNONES_E(lbits, owp[1]); owp[1] |= sign & ~VL_MASK_E(lbits); for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = sign; return owp; } static inline WDataOutP VL_EXTENDS_WW(int obits, int lbits, WDataOutP owp, WDataInP lwp) VL_MT_SAFE { for (int i = 0; i < VL_WORDS_I(lbits) - 1; ++i) owp[i] = lwp[i]; int lmsw = VL_WORDS_I(lbits) - 1; EData sign = VL_SIGNONES_E(lbits, lwp[lmsw]); owp[lmsw] = lwp[lmsw] | (sign & ~VL_MASK_E(lbits)); for (int i = VL_WORDS_I(lbits); i < VL_WORDS_I(obits); ++i) owp[i] = sign; return owp; } //=================================================================== // REDUCTION OPERATORS // EMIT_RULE: VL_REDAND: oclean=clean; lclean==clean; obits=1; #define VL_REDAND_II(obits, lbits, lhs) ((lhs) == VL_MASK_I(lbits)) #define VL_REDAND_IQ(obits, lbits, lhs) ((lhs) == VL_MASK_Q(lbits)) static inline IData VL_REDAND_IW(int, int lbits, WDataInP lwp) VL_MT_SAFE { int words = VL_WORDS_I(lbits); EData combine = lwp[0]; for (int i = 1; i < words - 1; ++i) combine &= lwp[i]; combine &= ~VL_MASK_E(lbits) | lwp[words - 1]; return ((~combine) == 0); } // EMIT_RULE: VL_REDOR: oclean=clean; lclean==clean; obits=1; #define VL_REDOR_I(lhs) ((lhs) != 0) #define VL_REDOR_Q(lhs) ((lhs) != 0) static inline IData VL_REDOR_W(int words, WDataInP lwp) VL_MT_SAFE { EData equal = 0; for (int i = 0; i < words; ++i) equal |= lwp[i]; return (equal != 0); } // EMIT_RULE: VL_REDXOR: oclean=dirty; obits=1; static inline IData VL_REDXOR_2(IData r) VL_PURE { // Experiments show VL_REDXOR_2 is faster than __builtin_parityl r = (r ^ (r >> 1)); return r; } static inline IData VL_REDXOR_4(IData r) VL_PURE { #if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS) return __builtin_parityl(r); #else r = (r ^ (r >> 1)); r = (r ^ (r >> 2)); return r; #endif } static inline IData VL_REDXOR_8(IData r) VL_PURE { #if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS) return __builtin_parityl(r); #else r = (r ^ (r >> 1)); r = (r ^ (r >> 2)); r = (r ^ (r >> 4)); return r; #endif } static inline IData VL_REDXOR_16(IData r) VL_PURE { #if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS) return __builtin_parityl(r); #else r = (r ^ (r >> 1)); r = (r ^ (r >> 2)); r = (r ^ (r >> 4)); r = (r ^ (r >> 8)); return r; #endif } static inline IData VL_REDXOR_32(IData r) VL_PURE { #if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS) return __builtin_parityl(r); #else r = (r ^ (r >> 1)); r = (r ^ (r >> 2)); r = (r ^ (r >> 4)); r = (r ^ (r >> 8)); r = (r ^ (r >> 16)); return r; #endif } static inline IData VL_REDXOR_64(QData r) VL_PURE { #if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS) return __builtin_parityll(r); #else r = (r ^ (r >> 1)); r = (r ^ (r >> 2)); r = (r ^ (r >> 4)); r = (r ^ (r >> 8)); r = (r ^ (r >> 16)); r = (r ^ (r >> 32)); return static_cast(r); #endif } static inline IData VL_REDXOR_W(int words, WDataInP lwp) VL_MT_SAFE { EData r = lwp[0]; for (int i = 1; i < words; ++i) r ^= lwp[i]; return VL_REDXOR_32(r); } // EMIT_RULE: VL_COUNTONES_II: oclean = false; lhs clean static inline IData VL_COUNTONES_I(IData lhs) VL_PURE { // This is faster than __builtin_popcountl IData r = lhs - ((lhs >> 1) & 033333333333) - ((lhs >> 2) & 011111111111); r = (r + (r >> 3)) & 030707070707; r = (r + (r >> 6)); r = (r + (r >> 12) + (r >> 24)) & 077; return r; } static inline IData VL_COUNTONES_Q(QData lhs) VL_PURE { return VL_COUNTONES_I(static_cast(lhs)) + VL_COUNTONES_I(static_cast(lhs >> 32)); } #define VL_COUNTONES_E VL_COUNTONES_I static inline IData VL_COUNTONES_W(int words, WDataInP lwp) VL_MT_SAFE { EData r = 0; for (int i = 0; i < words; ++i) r += VL_COUNTONES_E(lwp[i]); return r; } // EMIT_RULE: VL_COUNTBITS_II: oclean = false; lhs clean static inline IData VL_COUNTBITS_I(int lbits, IData lhs, IData ctrl0, IData ctrl1, IData ctrl2) VL_PURE { int ctrlSum = (ctrl0 & 0x1) + (ctrl1 & 0x1) + (ctrl2 & 0x1); if (ctrlSum == 3) { return VL_COUNTONES_I(lhs); } else if (ctrlSum == 0) { IData mask = (lbits == 32) ? -1 : ((1 << lbits) - 1); return VL_COUNTONES_I(~lhs & mask); } else { return (lbits == 32) ? 32 : lbits; } } static inline IData VL_COUNTBITS_Q(int lbits, QData lhs, IData ctrl0, IData ctrl1, IData ctrl2) VL_PURE { return VL_COUNTBITS_I(32, static_cast(lhs), ctrl0, ctrl1, ctrl2) + VL_COUNTBITS_I(lbits - 32, static_cast(lhs >> 32), ctrl0, ctrl1, ctrl2); } #define VL_COUNTBITS_E VL_COUNTBITS_I static inline IData VL_COUNTBITS_W(int lbits, int words, WDataInP lwp, IData ctrl0, IData ctrl1, IData ctrl2) VL_MT_SAFE { EData r = 0; IData wordLbits = 32; for (int i = 0; i < words; ++i) { if (i == words - 1) { wordLbits = lbits % 32; } r += VL_COUNTBITS_E(wordLbits, lwp[i], ctrl0, ctrl1, ctrl2); } return r; } static inline IData VL_ONEHOT_I(IData lhs) VL_PURE { return (((lhs & (lhs - 1)) == 0) & (lhs != 0)); } static inline IData VL_ONEHOT_Q(QData lhs) VL_PURE { return (((lhs & (lhs - 1)) == 0) & (lhs != 0)); } static inline IData VL_ONEHOT_W(int words, WDataInP lwp) VL_MT_SAFE { EData one = 0; for (int i = 0; (i < words); ++i) { if (lwp[i]) { if (one) return 0; one = 1; if (lwp[i] & (lwp[i] - 1)) return 0; } } return one; } static inline IData VL_ONEHOT0_I(IData lhs) VL_PURE { return ((lhs & (lhs - 1)) == 0); } static inline IData VL_ONEHOT0_Q(QData lhs) VL_PURE { return ((lhs & (lhs - 1)) == 0); } static inline IData VL_ONEHOT0_W(int words, WDataInP lwp) VL_MT_SAFE { bool one = false; for (int i = 0; (i < words); ++i) { if (lwp[i]) { if (one) return 0; one = true; if (lwp[i] & (lwp[i] - 1)) return 0; } } return 1; } static inline IData VL_CLOG2_I(IData lhs) VL_PURE { // There are faster algorithms, or fls GCC4 builtins, but rarely used if (VL_UNLIKELY(!lhs)) return 0; lhs--; int shifts = 0; for (; lhs != 0; ++shifts) lhs = lhs >> 1; return shifts; } static inline IData VL_CLOG2_Q(QData lhs) VL_PURE { if (VL_UNLIKELY(!lhs)) return 0; lhs--; int shifts = 0; for (; lhs != 0; ++shifts) lhs = lhs >> 1ULL; return shifts; } static inline IData VL_CLOG2_W(int words, WDataInP lwp) VL_MT_SAFE { EData adjust = (VL_COUNTONES_W(words, lwp) == 1) ? 0 : 1; for (int i = words - 1; i >= 0; --i) { if (VL_UNLIKELY(lwp[i])) { // Shorter worst case if predict not taken for (int bit = VL_EDATASIZE - 1; bit >= 0; --bit) { if (VL_UNLIKELY(VL_BITISSET_E(lwp[i], bit))) { return i * VL_EDATASIZE + bit + adjust; } } // Can't get here - one bit must be set } } return 0; } static inline IData VL_MOSTSETBITP1_W(int words, WDataInP lwp) VL_MT_SAFE { // MSB set bit plus one; similar to FLS. 0=value is zero for (int i = words - 1; i >= 0; --i) { if (VL_UNLIKELY(lwp[i])) { // Shorter worst case if predict not taken for (int bit = VL_EDATASIZE - 1; bit >= 0; --bit) { if (VL_UNLIKELY(VL_BITISSET_E(lwp[i], bit))) { return i * VL_EDATASIZE + bit + 1; } } // Can't get here - one bit must be set } } return 0; } //=================================================================== // SIMPLE LOGICAL OPERATORS // EMIT_RULE: VL_AND: oclean=lclean||rclean; obits=lbits; lbits==rbits; static inline WDataOutP VL_AND_W(int words, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { for (int i = 0; (i < words); ++i) owp[i] = (lwp[i] & rwp[i]); return owp; } // EMIT_RULE: VL_OR: oclean=lclean&&rclean; obits=lbits; lbits==rbits; static inline WDataOutP VL_OR_W(int words, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { for (int i = 0; (i < words); ++i) owp[i] = (lwp[i] | rwp[i]); return owp; } // EMIT_RULE: VL_CHANGEXOR: oclean=1; obits=32; lbits==rbits; static inline IData VL_CHANGEXOR_W(int words, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { IData od = 0; for (int i = 0; (i < words); ++i) od |= (lwp[i] ^ rwp[i]); return od; } // EMIT_RULE: VL_XOR: oclean=lclean&&rclean; obits=lbits; lbits==rbits; static inline WDataOutP VL_XOR_W(int words, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { for (int i = 0; (i < words); ++i) owp[i] = (lwp[i] ^ rwp[i]); return owp; } // EMIT_RULE: VL_XNOR: oclean=dirty; obits=lbits; lbits==rbits; static inline WDataOutP VL_XNOR_W(int words, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { for (int i = 0; (i < words); ++i) owp[i] = (lwp[i] ^ ~rwp[i]); return owp; } // EMIT_RULE: VL_NOT: oclean=dirty; obits=lbits; static inline WDataOutP VL_NOT_W(int words, WDataOutP owp, WDataInP lwp) VL_MT_SAFE { for (int i = 0; i < words; ++i) owp[i] = ~(lwp[i]); return owp; } //========================================================================= // Logical comparisons // EMIT_RULE: VL_EQ: oclean=clean; lclean==clean; rclean==clean; obits=1; lbits==rbits; // EMIT_RULE: VL_NEQ: oclean=clean; lclean==clean; rclean==clean; obits=1; lbits==rbits; // EMIT_RULE: VL_LT: oclean=clean; lclean==clean; rclean==clean; obits=1; lbits==rbits; // EMIT_RULE: VL_GT: oclean=clean; lclean==clean; rclean==clean; obits=1; lbits==rbits; // EMIT_RULE: VL_GTE: oclean=clean; lclean==clean; rclean==clean; obits=1; lbits==rbits; // EMIT_RULE: VL_LTE: oclean=clean; lclean==clean; rclean==clean; obits=1; lbits==rbits; #define VL_NEQ_W(words, lwp, rwp) (!VL_EQ_W(words, lwp, rwp)) #define VL_LT_W(words, lwp, rwp) (_VL_CMP_W(words, lwp, rwp) < 0) #define VL_LTE_W(words, lwp, rwp) (_VL_CMP_W(words, lwp, rwp) <= 0) #define VL_GT_W(words, lwp, rwp) (_VL_CMP_W(words, lwp, rwp) > 0) #define VL_GTE_W(words, lwp, rwp) (_VL_CMP_W(words, lwp, rwp) >= 0) // Output clean, AND MUST BE CLEAN static inline IData VL_EQ_W(int words, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { EData nequal = 0; for (int i = 0; (i < words); ++i) nequal |= (lwp[i] ^ rwp[i]); return (nequal == 0); } // Internal usage static inline int _VL_CMP_W(int words, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { for (int i = words - 1; i >= 0; --i) { if (lwp[i] > rwp[i]) return 1; if (lwp[i] < rwp[i]) return -1; } return 0; // == } #define VL_LTS_IWW(obits, lbits, rbbits, lwp, rwp) (_VL_CMPS_W(lbits, lwp, rwp) < 0) #define VL_LTES_IWW(obits, lbits, rbits, lwp, rwp) (_VL_CMPS_W(lbits, lwp, rwp) <= 0) #define VL_GTS_IWW(obits, lbits, rbits, lwp, rwp) (_VL_CMPS_W(lbits, lwp, rwp) > 0) #define VL_GTES_IWW(obits, lbits, rbits, lwp, rwp) (_VL_CMPS_W(lbits, lwp, rwp) >= 0) static inline IData VL_GTS_III(int, int lbits, int, IData lhs, IData rhs) VL_PURE { // For lbits==32, this becomes just a single instruction, otherwise ~5. // GCC 3.3.4 sign extension bugs on AMD64 architecture force us to use quad logic vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc return lhs_signed > rhs_signed; } static inline IData VL_GTS_IQQ(int, int lbits, int, QData lhs, QData rhs) VL_PURE { vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed > rhs_signed; } static inline IData VL_GTES_III(int, int lbits, int, IData lhs, IData rhs) VL_PURE { vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc return lhs_signed >= rhs_signed; } static inline IData VL_GTES_IQQ(int, int lbits, int, QData lhs, QData rhs) VL_PURE { vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed >= rhs_signed; } static inline IData VL_LTS_III(int, int lbits, int, IData lhs, IData rhs) VL_PURE { vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc return lhs_signed < rhs_signed; } static inline IData VL_LTS_IQQ(int, int lbits, int, QData lhs, QData rhs) VL_PURE { vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed < rhs_signed; } static inline IData VL_LTES_III(int, int lbits, int, IData lhs, IData rhs) VL_PURE { vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc return lhs_signed <= rhs_signed; } static inline IData VL_LTES_IQQ(int, int lbits, int, QData lhs, QData rhs) VL_PURE { vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed <= rhs_signed; } static inline int _VL_CMPS_W(int lbits, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { int words = VL_WORDS_I(lbits); int i = words - 1; // We need to flip sense if negative comparison EData lsign = VL_SIGN_E(lbits, lwp[i]); EData rsign = VL_SIGN_E(lbits, rwp[i]); if (!lsign && rsign) return 1; // + > - if (lsign && !rsign) return -1; // - < + for (; i >= 0; --i) { if (lwp[i] > rwp[i]) return 1; if (lwp[i] < rwp[i]) return -1; } return 0; // == } //========================================================================= // Math static inline WDataOutP VL_NEGATE_W(int words, WDataOutP owp, WDataInP lwp) VL_MT_SAFE { EData carry = 1; for (int i = 0; i < words; ++i) { owp[i] = ~lwp[i] + carry; carry = (owp[i] < ~lwp[i]); } return owp; } static void VL_NEGATE_INPLACE_W(int words, WDataOutP owp_lwp) VL_MT_SAFE { EData carry = 1; for (int i = 0; i < words; ++i) { EData word = ~owp_lwp[i] + carry; carry = (word < ~owp_lwp[i]); owp_lwp[i] = word; } } // EMIT_RULE: VL_MUL: oclean=dirty; lclean==clean; rclean==clean; // EMIT_RULE: VL_DIV: oclean=dirty; lclean==clean; rclean==clean; // EMIT_RULE: VL_MODDIV: oclean=dirty; lclean==clean; rclean==clean; #define VL_DIV_III(lbits, lhs, rhs) (((rhs) == 0) ? 0 : (lhs) / (rhs)) #define VL_DIV_QQQ(lbits, lhs, rhs) (((rhs) == 0) ? 0 : (lhs) / (rhs)) #define VL_DIV_WWW(lbits, owp, lwp, rwp) (_vl_moddiv_w(lbits, owp, lwp, rwp, 0)) #define VL_MODDIV_III(lbits, lhs, rhs) (((rhs) == 0) ? 0 : (lhs) % (rhs)) #define VL_MODDIV_QQQ(lbits, lhs, rhs) (((rhs) == 0) ? 0 : (lhs) % (rhs)) #define VL_MODDIV_WWW(lbits, owp, lwp, rwp) (_vl_moddiv_w(lbits, owp, lwp, rwp, 1)) static inline WDataOutP VL_ADD_W(int words, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { QData carry = 0; for (int i = 0; i < words; ++i) { carry = carry + static_cast(lwp[i]) + static_cast(rwp[i]); owp[i] = (carry & 0xffffffffULL); carry = (carry >> 32ULL) & 0xffffffffULL; } // Last output word is dirty return owp; } static inline WDataOutP VL_SUB_W(int words, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { QData carry = 0; for (int i = 0; i < words; ++i) { carry = (carry + static_cast(lwp[i]) + static_cast(static_cast(~rwp[i]))); if (i == 0) ++carry; // Negation of rwp owp[i] = (carry & 0xffffffffULL); carry = (carry >> 32ULL) & 0xffffffffULL; } // Last output word is dirty return owp; } static inline WDataOutP VL_MUL_W(int words, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { for (int i = 0; i < words; ++i) owp[i] = 0; for (int lword = 0; lword < words; ++lword) { for (int rword = 0; rword < words; ++rword) { QData mul = static_cast(lwp[lword]) * static_cast(rwp[rword]); for (int qword = lword + rword; qword < words; ++qword) { mul += static_cast(owp[qword]); owp[qword] = (mul & 0xffffffffULL); mul = (mul >> 32ULL) & 0xffffffffULL; } } } // Last output word is dirty return owp; } static inline IData VL_MULS_III(int, int lbits, int, IData lhs, IData rhs) VL_PURE { vlsint32_t lhs_signed = VL_EXTENDS_II(32, lbits, lhs); vlsint32_t rhs_signed = VL_EXTENDS_II(32, lbits, rhs); return lhs_signed * rhs_signed; } static inline QData VL_MULS_QQQ(int, int lbits, int, QData lhs, QData rhs) VL_PURE { vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed * rhs_signed; } static inline WDataOutP VL_MULS_WWW(int, int lbits, int, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { int words = VL_WORDS_I(lbits); // cppcheck-suppress variableScope WData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here // cppcheck-suppress variableScope WData rwstore[VL_MULS_MAX_WORDS]; WDataInP lwusp = lwp; WDataInP rwusp = rwp; EData lneg = VL_SIGN_E(lbits, lwp[words - 1]); if (lneg) { // Negate lhs lwusp = lwstore; VL_NEGATE_W(words, lwstore, lwp); lwstore[words - 1] &= VL_MASK_E(lbits); // Clean it } EData rneg = VL_SIGN_E(lbits, rwp[words - 1]); if (rneg) { // Negate rhs rwusp = rwstore; VL_NEGATE_W(words, rwstore, rwp); rwstore[words - 1] &= VL_MASK_E(lbits); // Clean it } VL_MUL_W(words, owp, lwusp, rwusp); owp[words - 1] &= VL_MASK_E( lbits); // Clean. Note it's ok for the multiply to overflow into the sign bit if ((lneg ^ rneg) & 1) { // Negate output (not using NEGATE, as owp==lwp) QData carry = 0; for (int i = 0; i < words; ++i) { carry = carry + static_cast(static_cast(~owp[i])); if (i == 0) ++carry; // Negation of temp2 owp[i] = (carry & 0xffffffffULL); carry = (carry >> 32ULL) & 0xffffffffULL; } // Not needed: owp[words-1] |= 1< 0) power = power * power; if (rhs & (1ULL << i)) out *= power; } return out; } static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) VL_PURE { if (VL_UNLIKELY(rhs == 0)) return 1; if (VL_UNLIKELY(lhs == 0)) return 0; QData power = lhs; QData out = 1ULL; for (int i = 0; i < rbits; ++i) { if (i > 0) power = power * power; if (rhs & (1ULL << i)) out *= power; } return out; } WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp); WDataOutP VL_POW_WWQ(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, QData rhs); QData VL_POW_QQW(int obits, int, int rbits, QData lhs, WDataInP rwp); #define VL_POWSS_IIQ(obits, lbits, rbits, lhs, rhs, lsign, rsign) \ VL_POWSS_QQQ(obits, lbits, rbits, lhs, rhs, lsign, rsign) #define VL_POWSS_IIQ(obits, lbits, rbits, lhs, rhs, lsign, rsign) \ VL_POWSS_QQQ(obits, lbits, rbits, lhs, rhs, lsign, rsign) #define VL_POWSS_IIW(obits, lbits, rbits, lhs, rwp, lsign, rsign) \ VL_POWSS_QQW(obits, lbits, rbits, lhs, rwp, lsign, rsign) #define VL_POWSS_QQI(obits, lbits, rbits, lhs, rhs, lsign, rsign) \ VL_POWSS_QQQ(obits, lbits, rbits, lhs, rhs, lsign, rsign) #define VL_POWSS_WWI(obits, lbits, rbits, owp, lwp, rhs, lsign, rsign) \ VL_POWSS_WWQ(obits, lbits, rbits, owp, lwp, rhs, lsign, rsign) static inline IData VL_POWSS_III(int obits, int, int rbits, IData lhs, IData rhs, bool lsign, bool rsign) VL_MT_SAFE { if (VL_UNLIKELY(rhs == 0)) return 1; if (rsign && VL_SIGN_I(rbits, rhs)) { if (lhs == 0) { return 0; // "X" } else if (lhs == 1) { return 1; } else if (lsign && lhs == VL_MASK_I(obits)) { // -1 if (rhs & 1) { return VL_MASK_I(obits); // -1^odd=-1 } else { return 1; // -1^even=1 } } return 0; } return VL_POW_III(obits, rbits, rbits, lhs, rhs); } static inline QData VL_POWSS_QQQ(int obits, int, int rbits, QData lhs, QData rhs, bool lsign, bool rsign) VL_MT_SAFE { if (VL_UNLIKELY(rhs == 0)) return 1; if (rsign && VL_SIGN_Q(rbits, rhs)) { if (lhs == 0) { return 0; // "X" } else if (lhs == 1) { return 1; } else if (lsign && lhs == VL_MASK_Q(obits)) { // -1 if (rhs & 1) { return VL_MASK_Q(obits); // -1^odd=-1 } else { return 1; // -1^even=1 } } return 0; } return VL_POW_QQQ(obits, rbits, rbits, lhs, rhs); } WDataOutP VL_POWSS_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, bool lsign, bool rsign); WDataOutP VL_POWSS_WWQ(int obits, int, int rbits, WDataOutP owp, WDataInP lwp, QData rhs, bool lsign, bool rsign); QData VL_POWSS_QQW(int obits, int, int rbits, QData lhs, WDataInP rwp, bool lsign, bool rsign); //=================================================================== // Concat/replication // INTERNAL: Stuff LHS bit 0++ into OUTPUT at specified offset // ld may be "dirty", output is clean static inline void _VL_INSERT_II(int, CData& lhsr, IData ld, int hbit, int lbit) VL_PURE { IData insmask = (VL_MASK_I(hbit - lbit + 1)) << lbit; lhsr = (lhsr & ~insmask) | ((ld << lbit) & insmask); } static inline void _VL_INSERT_II(int, SData& lhsr, IData ld, int hbit, int lbit) VL_PURE { IData insmask = (VL_MASK_I(hbit - lbit + 1)) << lbit; lhsr = (lhsr & ~insmask) | ((ld << lbit) & insmask); } static inline void _VL_INSERT_II(int, IData& lhsr, IData ld, int hbit, int lbit) VL_PURE { IData insmask = (VL_MASK_I(hbit - lbit + 1)) << lbit; lhsr = (lhsr & ~insmask) | ((ld << lbit) & insmask); } static inline void _VL_INSERT_QQ(int, QData& lhsr, QData ld, int hbit, int lbit) VL_PURE { QData insmask = (VL_MASK_Q(hbit - lbit + 1)) << lbit; lhsr = (lhsr & ~insmask) | ((ld << lbit) & insmask); } static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbit) VL_MT_SAFE { int hoffset = VL_BITBIT_E(hbit); int loffset = VL_BITBIT_E(lbit); if (hoffset == VL_SIZEBITS_E && loffset == 0) { // Fast and common case, word based insertion owp[VL_BITWORD_E(lbit)] = ld; } else { int hword = VL_BITWORD_E(hbit); int lword = VL_BITWORD_E(lbit); EData lde = static_cast(ld); if (hword == lword) { // know < EData bits because above checks it EData insmask = (VL_MASK_E(hoffset - loffset + 1)) << loffset; owp[lword] = (owp[lword] & ~insmask) | ((lde << loffset) & insmask); } else { EData hinsmask = (VL_MASK_E(hoffset - 0 + 1)) << 0; EData linsmask = (VL_MASK_E((VL_EDATASIZE - 1) - loffset + 1)) << loffset; int nbitsonright = VL_EDATASIZE - loffset; // bits that end up in lword owp[lword] = (owp[lword] & ~linsmask) | ((lde << loffset) & linsmask); owp[hword] = (owp[hword] & ~hinsmask) | ((lde >> nbitsonright) & hinsmask); } } } // INTERNAL: Stuff large LHS bit 0++ into OUTPUT at specified offset // lwp may be "dirty" static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int lbit) VL_MT_SAFE { int hoffset = hbit & VL_SIZEBITS_E; int loffset = lbit & VL_SIZEBITS_E; int lword = VL_BITWORD_E(lbit); int words = VL_WORDS_I(hbit - lbit + 1); if (hoffset == VL_SIZEBITS_E && loffset == 0) { // Fast and common case, word based insertion for (int i = 0; i < words; ++i) owp[lword + i] = lwp[i]; } else if (loffset == 0) { // Non-32bit, but nicely aligned, so stuff all but the last word for (int i = 0; i < (words - 1); ++i) owp[lword + i] = lwp[i]; // Know it's not a full word as above fast case handled it EData hinsmask = (VL_MASK_E(hoffset - 0 + 1)); owp[lword + words - 1] = (owp[words + lword - 1] & ~hinsmask) | (lwp[words - 1] & hinsmask); } else { EData hinsmask = (VL_MASK_E(hoffset - 0 + 1)) << 0; EData linsmask = (VL_MASK_E((VL_EDATASIZE - 1) - loffset + 1)) << loffset; int nbitsonright = VL_EDATASIZE - loffset; // bits that end up in lword (know loffset!=0) // Middle words int hword = VL_BITWORD_E(hbit); for (int i = 0; i < words; ++i) { { // Lower word int oword = lword + i; EData d = lwp[i] << loffset; EData od = (owp[oword] & ~linsmask) | (d & linsmask); if (oword == hword) { owp[oword] = (owp[oword] & ~hinsmask) | (od & hinsmask); } else { owp[oword] = od; } } { // Upper word int oword = lword + i + 1; if (oword <= hword) { EData d = lwp[i] >> nbitsonright; EData od = (d & ~linsmask) | (owp[oword] & linsmask); if (oword == hword) { owp[oword] = (owp[oword] & ~hinsmask) | (od & hinsmask); } else { owp[oword] = od; } } } } } } static inline void _VL_INSERT_WQ(int obits, WDataOutP owp, QData ld, int hbit, int lbit) VL_MT_SAFE { WData lwp[VL_WQ_WORDS_E]; VL_SET_WQ(lwp, ld); _VL_INSERT_WW(obits, owp, lwp, hbit, lbit); } // EMIT_RULE: VL_REPLICATE: oclean=clean>width32, dirty<=width32; lclean=clean; rclean==clean; // RHS MUST BE CLEAN CONSTANT. #define VL_REPLICATE_IOI(obits, lbits, rbits, ld, rep) (-(ld)) // Iff lbits==1 #define VL_REPLICATE_QOI(obits, lbits, rbits, ld, rep) (-(static_cast(ld))) // Iff lbits==1 static inline IData VL_REPLICATE_III(int, int lbits, int, IData ld, IData rep) VL_PURE { IData returndata = ld; for (unsigned i = 1; i < rep; ++i) { returndata = returndata << lbits; returndata |= ld; } return returndata; } static inline QData VL_REPLICATE_QII(int, int lbits, int, IData ld, IData rep) VL_PURE { QData returndata = ld; for (unsigned i = 1; i < rep; ++i) { returndata = returndata << lbits; returndata |= static_cast(ld); } return returndata; } static inline WDataOutP VL_REPLICATE_WII(int obits, int lbits, int, WDataOutP owp, IData ld, IData rep) VL_MT_SAFE { owp[0] = ld; for (unsigned i = 1; i < rep; ++i) { _VL_INSERT_WI(obits, owp, ld, i * lbits + lbits - 1, i * lbits); } return owp; } static inline WDataOutP VL_REPLICATE_WQI(int obits, int lbits, int, WDataOutP owp, QData ld, IData rep) VL_MT_SAFE { VL_SET_WQ(owp, ld); for (unsigned i = 1; i < rep; ++i) { _VL_INSERT_WQ(obits, owp, ld, i * lbits + lbits - 1, i * lbits); } return owp; } static inline WDataOutP VL_REPLICATE_WWI(int obits, int lbits, int, WDataOutP owp, WDataInP lwp, IData rep) VL_MT_SAFE { for (int i = 0; i < VL_WORDS_I(lbits); ++i) owp[i] = lwp[i]; for (unsigned i = 1; i < rep; ++i) { _VL_INSERT_WW(obits, owp, lwp, i * lbits + lbits - 1, i * lbits); } return owp; } // Left stream operator. Output will always be clean. LHS and RHS must be clean. // Special "fast" versions for slice sizes that are a power of 2. These use // shifts and masks to execute faster than the slower for-loop approach where a // subset of bits is copied in during each iteration. static inline IData VL_STREAML_FAST_III(int, int lbits, int, IData ld, IData rd_log2) VL_PURE { // Pre-shift bits in most-significant slice: // // If lbits is not a multiple of the slice size (i.e., lbits % rd != 0), // then we end up with a "gap" in our reversed result. For example, if we // have a 5-bit Verlilog signal (lbits=5) in an 8-bit C data type: // // ld = ---43210 // // (where numbers are the Verilog signal bit numbers and '-' is an unused bit). // Executing the switch statement below with a slice size of two (rd=2, // rd_log2=1) produces: // // ret = 1032-400 // // Pre-shifting the bits in the most-significant slice allows us to avoid // this gap in the shuffled data: // // ld_adjusted = --4-3210 // ret = 10324--- IData ret = ld; if (rd_log2) { vluint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2); // max multiple of rd <= lbits vluint32_t lbitsRem = lbits - lbitsFloor; // number of bits in most-sig slice (MSS) IData msbMask = VL_MASK_I(lbitsRem) << lbitsFloor; // mask to sel only bits in MSS ret = (ret & ~msbMask) | ((ret & msbMask) << ((VL_UL(1) << rd_log2) - lbitsRem)); } switch (rd_log2) { case 0: ret = ((ret >> 1) & VL_UL(0x55555555)) | ((ret & VL_UL(0x55555555)) << 1); // FALLTHRU case 1: ret = ((ret >> 2) & VL_UL(0x33333333)) | ((ret & VL_UL(0x33333333)) << 2); // FALLTHRU case 2: ret = ((ret >> 4) & VL_UL(0x0f0f0f0f)) | ((ret & VL_UL(0x0f0f0f0f)) << 4); // FALLTHRU case 3: ret = ((ret >> 8) & VL_UL(0x00ff00ff)) | ((ret & VL_UL(0x00ff00ff)) << 8); // FALLTHRU case 4: ret = ((ret >> 16) | (ret << 16)); // FALLTHRU default:; } return ret >> (VL_IDATASIZE - lbits); } static inline QData VL_STREAML_FAST_QQI(int, int lbits, int, QData ld, IData rd_log2) VL_PURE { // Pre-shift bits in most-significant slice (see comment in VL_STREAML_FAST_III) QData ret = ld; if (rd_log2) { vluint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2); vluint32_t lbitsRem = lbits - lbitsFloor; QData msbMask = VL_MASK_Q(lbitsRem) << lbitsFloor; ret = (ret & ~msbMask) | ((ret & msbMask) << ((1ULL << rd_log2) - lbitsRem)); } switch (rd_log2) { case 0: ret = (((ret >> 1) & 0x5555555555555555ULL) | ((ret & 0x5555555555555555ULL) << 1)); // FALLTHRU case 1: ret = (((ret >> 2) & 0x3333333333333333ULL) | ((ret & 0x3333333333333333ULL) << 2)); // FALLTHRU case 2: ret = (((ret >> 4) & 0x0f0f0f0f0f0f0f0fULL) | ((ret & 0x0f0f0f0f0f0f0f0fULL) << 4)); // FALLTHRU case 3: ret = (((ret >> 8) & 0x00ff00ff00ff00ffULL) | ((ret & 0x00ff00ff00ff00ffULL) << 8)); // FALLTHRU case 4: ret = (((ret >> 16) & 0x0000ffff0000ffffULL) | ((ret & 0x0000ffff0000ffffULL) << 16)); // FALLTHRU case 5: ret = ((ret >> 32) | (ret << 32)); // FALLTHRU default:; } return ret >> (VL_QUADSIZE - lbits); } // Regular "slow" streaming operators static inline IData VL_STREAML_III(int, int lbits, int, IData ld, IData rd) VL_PURE { IData ret = 0; // Slice size should never exceed the lhs width IData mask = VL_MASK_I(rd); for (int istart = 0; istart < lbits; istart += rd) { int ostart = lbits - rd - istart; ostart = ostart > 0 ? ostart : 0; ret |= ((ld >> istart) & mask) << ostart; } return ret; } static inline QData VL_STREAML_QQI(int, int lbits, int, QData ld, IData rd) VL_PURE { QData ret = 0; // Slice size should never exceed the lhs width QData mask = VL_MASK_Q(rd); for (int istart = 0; istart < lbits; istart += rd) { int ostart = lbits - rd - istart; ostart = ostart > 0 ? ostart : 0; ret |= ((ld >> istart) & mask) << ostart; } return ret; } static inline WDataOutP VL_STREAML_WWI(int, int lbits, int, WDataOutP owp, WDataInP lwp, IData rd) VL_MT_SAFE { VL_ZERO_W(lbits, owp); // Slice size should never exceed the lhs width int ssize = (rd < static_cast(lbits)) ? rd : (static_cast(lbits)); for (int istart = 0; istart < lbits; istart += rd) { int ostart = lbits - rd - istart; ostart = ostart > 0 ? ostart : 0; for (int sbit = 0; sbit < ssize && sbit < lbits - istart; ++sbit) { // Extract a single bit from lwp and shift it to the correct // location for owp. EData bit = (VL_BITRSHIFT_W(lwp, (istart + sbit)) & 1) << VL_BITBIT_E(ostart + sbit); owp[VL_BITWORD_E(ostart + sbit)] |= bit; } } return owp; } // Because concats are common and wide, it's valuable to always have a clean output. // Thus we specify inputs must be clean, so we don't need to clean the output. // Note the bit shifts are always constants, so the adds in these constify out. // Casts required, as args may be 8 bit entities, and need to shift to appropriate output size #define VL_CONCAT_III(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) #define VL_CONCAT_QII(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) #define VL_CONCAT_QIQ(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) #define VL_CONCAT_QQI(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) #define VL_CONCAT_QQQ(obits, lbits, rbits, ld, rd) \ (static_cast(ld) << (rbits) | static_cast(rd)) static inline WDataOutP VL_CONCAT_WII(int obits, int lbits, int rbits, WDataOutP owp, IData ld, IData rd) VL_MT_SAFE { owp[0] = rd; for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WI(obits, owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WWI(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, IData rd) VL_MT_SAFE { owp[0] = rd; for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WW(obits, owp, lwp, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WIW(int obits, int lbits, int rbits, WDataOutP owp, IData ld, WDataInP rwp) VL_MT_SAFE { for (int i = 0; i < VL_WORDS_I(rbits); ++i) owp[i] = rwp[i]; for (int i = VL_WORDS_I(rbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WI(obits, owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WIQ(int obits, int lbits, int rbits, WDataOutP owp, IData ld, QData rd) VL_MT_SAFE { VL_SET_WQ(owp, rd); for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WI(obits, owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WQI(int obits, int lbits, int rbits, WDataOutP owp, QData ld, IData rd) VL_MT_SAFE { owp[0] = rd; for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WQ(obits, owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WQQ(int obits, int lbits, int rbits, WDataOutP owp, QData ld, QData rd) VL_MT_SAFE { VL_SET_WQ(owp, rd); for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WQ(obits, owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WWQ(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, QData rd) VL_MT_SAFE { VL_SET_WQ(owp, rd); for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WW(obits, owp, lwp, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WQW(int obits, int lbits, int rbits, WDataOutP owp, QData ld, WDataInP rwp) VL_MT_SAFE { for (int i = 0; i < VL_WORDS_I(rbits); ++i) owp[i] = rwp[i]; for (int i = VL_WORDS_I(rbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WQ(obits, owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WWW(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { for (int i = 0; i < VL_WORDS_I(rbits); ++i) owp[i] = rwp[i]; for (int i = VL_WORDS_I(rbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WW(obits, owp, lwp, rbits + lbits - 1, rbits); return owp; } //=================================================================== // Shifts // Static shift, used by internal functions // The output is the same as the input - it overlaps! static inline void _VL_SHIFTL_INPLACE_W(int obits, WDataOutP iowp, IData rd /*1 or 4*/) VL_MT_SAFE { int words = VL_WORDS_I(obits); EData linsmask = VL_MASK_E(rd); for (int i = words - 1; i >= 1; --i) { iowp[i] = ((iowp[i] << rd) & ~linsmask) | ((iowp[i - 1] >> (VL_EDATASIZE - rd)) & linsmask); } iowp[0] = ((iowp[0] << rd) & ~linsmask); iowp[VL_WORDS_I(obits) - 1] &= VL_MASK_E(obits); } // EMIT_RULE: VL_SHIFTL: oclean=lclean; rclean==clean; // Important: Unlike most other funcs, the shift might well be a computed // expression. Thus consider this when optimizing. (And perhaps have 2 funcs?) static inline WDataOutP VL_SHIFTL_WWI(int obits, int, int, WDataOutP owp, WDataInP lwp, IData rd) VL_MT_SAFE { int word_shift = VL_BITWORD_E(rd); int bit_shift = VL_BITBIT_E(rd); if (rd >= static_cast(obits)) { // rd may be huge with MSB set for (int i = 0; i < VL_WORDS_I(obits); ++i) owp[i] = 0; } else if (bit_shift == 0) { // Aligned word shift (<<0,<<32,<<64 etc) for (int i = 0; i < word_shift; ++i) owp[i] = 0; for (int i = word_shift; i < VL_WORDS_I(obits); ++i) owp[i] = lwp[i - word_shift]; } else { for (int i = 0; i < VL_WORDS_I(obits); ++i) owp[i] = 0; _VL_INSERT_WW(obits, owp, lwp, obits - 1, rd); } return owp; } static inline WDataOutP VL_SHIFTL_WWW(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { for (int i = 1; i < VL_WORDS_I(rbits); ++i) { if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more return VL_ZERO_W(obits, owp); } } return VL_SHIFTL_WWI(obits, lbits, 32, owp, lwp, rwp[0]); } static inline IData VL_SHIFTL_IIW(int obits, int, int rbits, IData lhs, WDataInP rwp) VL_MT_SAFE { for (int i = 1; i < VL_WORDS_I(rbits); ++i) { if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more return 0; } } return VL_CLEAN_II(obits, obits, lhs << rwp[0]); } static inline QData VL_SHIFTL_QQW(int obits, int, int rbits, QData lhs, WDataInP rwp) VL_MT_SAFE { for (int i = 1; i < VL_WORDS_I(rbits); ++i) { if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more return 0; } } // Above checks rwp[1]==0 so not needed in below shift return VL_CLEAN_QQ(obits, obits, lhs << (static_cast(rwp[0]))); } // EMIT_RULE: VL_SHIFTR: oclean=lclean; rclean==clean; // Important: Unlike most other funcs, the shift might well be a computed // expression. Thus consider this when optimizing. (And perhaps have 2 funcs?) static inline WDataOutP VL_SHIFTR_WWI(int obits, int, int, WDataOutP owp, WDataInP lwp, IData rd) VL_MT_SAFE { int word_shift = VL_BITWORD_E(rd); // Maybe 0 int bit_shift = VL_BITBIT_E(rd); if (rd >= static_cast(obits)) { // rd may be huge with MSB set for (int i = 0; i < VL_WORDS_I(obits); ++i) owp[i] = 0; } else if (bit_shift == 0) { // Aligned word shift (>>0,>>32,>>64 etc) int copy_words = (VL_WORDS_I(obits) - word_shift); for (int i = 0; i < copy_words; ++i) owp[i] = lwp[i + word_shift]; for (int i = copy_words; i < VL_WORDS_I(obits); ++i) owp[i] = 0; } else { int loffset = rd & VL_SIZEBITS_E; int nbitsonright = VL_EDATASIZE - loffset; // bits that end up in lword (know loffset!=0) // Middle words int words = VL_WORDS_I(obits - rd); for (int i = 0; i < words; ++i) { owp[i] = lwp[i + word_shift] >> loffset; int upperword = i + word_shift + 1; if (upperword < VL_WORDS_I(obits)) owp[i] |= lwp[upperword] << nbitsonright; } for (int i = words; i < VL_WORDS_I(obits); ++i) owp[i] = 0; } return owp; } static inline WDataOutP VL_SHIFTR_WWW(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { for (int i = 1; i < VL_WORDS_I(rbits); ++i) { if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more return VL_ZERO_W(obits, owp); } } return VL_SHIFTR_WWI(obits, lbits, 32, owp, lwp, rwp[0]); } static inline WDataOutP VL_SHIFTR_WWQ(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, QData rd) VL_MT_SAFE { WData rwp[VL_WQ_WORDS_E]; VL_SET_WQ(rwp, rd); return VL_SHIFTR_WWW(obits, lbits, rbits, owp, lwp, rwp); } static inline IData VL_SHIFTR_IIW(int obits, int, int rbits, IData lhs, WDataInP rwp) VL_MT_SAFE { for (int i = 1; i < VL_WORDS_I(rbits); ++i) { if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more return 0; } } return VL_CLEAN_II(obits, obits, lhs >> rwp[0]); } static inline QData VL_SHIFTR_QQW(int obits, int, int rbits, QData lhs, WDataInP rwp) VL_MT_SAFE { for (int i = 1; i < VL_WORDS_I(rbits); ++i) { if (VL_UNLIKELY(rwp[i])) { // Huge shift 1>>32 or more return 0; } } // Above checks rwp[1]==0 so not needed in below shift return VL_CLEAN_QQ(obits, obits, lhs >> (static_cast(rwp[0]))); } // EMIT_RULE: VL_SHIFTRS: oclean=false; lclean=clean, rclean==clean; static inline IData VL_SHIFTRS_III(int obits, int lbits, int, IData lhs, IData rhs) VL_PURE { // Note the C standard does not specify the >> operator as a arithmetic shift! // IEEE says signed if output signed, but bit position from lbits; // must use lbits for sign; lbits might != obits, // an EXTEND(SHIFTRS(...)) can became a SHIFTRS(...) within same 32/64 bit word length IData sign = -(lhs >> (lbits - 1)); // ffff_ffff if negative IData signext = ~(VL_MASK_I(lbits) >> rhs); // One with bits where we've shifted "past" return (lhs >> rhs) | (sign & VL_CLEAN_II(obits, obits, signext)); } static inline QData VL_SHIFTRS_QQI(int obits, int lbits, int, QData lhs, IData rhs) VL_PURE { QData sign = -(lhs >> (lbits - 1)); QData signext = ~(VL_MASK_Q(lbits) >> rhs); return (lhs >> rhs) | (sign & VL_CLEAN_QQ(obits, obits, signext)); } static inline IData VL_SHIFTRS_IQI(int obits, int lbits, int rbits, QData lhs, IData rhs) VL_PURE { return static_cast(VL_SHIFTRS_QQI(obits, lbits, rbits, lhs, rhs)); } static inline WDataOutP VL_SHIFTRS_WWI(int obits, int lbits, int, WDataOutP owp, WDataInP lwp, IData rd) VL_MT_SAFE { int word_shift = VL_BITWORD_E(rd); int bit_shift = VL_BITBIT_E(rd); int lmsw = VL_WORDS_I(obits) - 1; EData sign = VL_SIGNONES_E(lbits, lwp[lmsw]); if (rd >= static_cast(obits)) { // Shifting past end, sign in all of lbits for (int i = 0; i <= lmsw; ++i) owp[i] = sign; owp[lmsw] &= VL_MASK_E(lbits); } else if (bit_shift == 0) { // Aligned word shift (>>0,>>32,>>64 etc) int copy_words = (VL_WORDS_I(obits) - word_shift); for (int i = 0; i < copy_words; ++i) owp[i] = lwp[i + word_shift]; if (copy_words >= 0) owp[copy_words - 1] |= ~VL_MASK_E(obits) & sign; for (int i = copy_words; i < VL_WORDS_I(obits); ++i) owp[i] = sign; owp[lmsw] &= VL_MASK_E(lbits); } else { int loffset = rd & VL_SIZEBITS_E; int nbitsonright = VL_EDATASIZE - loffset; // bits that end up in lword (know loffset!=0) // Middle words int words = VL_WORDS_I(obits - rd); for (int i = 0; i < words; ++i) { owp[i] = lwp[i + word_shift] >> loffset; int upperword = i + word_shift + 1; if (upperword < VL_WORDS_I(obits)) owp[i] |= lwp[upperword] << nbitsonright; } if (words) owp[words - 1] |= sign & ~VL_MASK_E(obits - loffset); for (int i = words; i < VL_WORDS_I(obits); ++i) owp[i] = sign; owp[lmsw] &= VL_MASK_E(lbits); } return owp; } static inline WDataOutP VL_SHIFTRS_WWW(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, WDataInP rwp) VL_MT_SAFE { EData overshift = 0; // Huge shift 1>>32 or more for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; if (VL_UNLIKELY(overshift)) { int lmsw = VL_WORDS_I(obits) - 1; EData sign = VL_SIGNONES_E(lbits, lwp[lmsw]); for (int j = 0; j <= lmsw; ++j) owp[j] = sign; owp[lmsw] &= VL_MASK_E(lbits); return owp; } return VL_SHIFTRS_WWI(obits, lbits, 32, owp, lwp, rwp[0]); } static inline WDataOutP VL_SHIFTRS_WWQ(int obits, int lbits, int rbits, WDataOutP owp, WDataInP lwp, QData rd) VL_MT_SAFE { WData rwp[VL_WQ_WORDS_E]; VL_SET_WQ(rwp, rd); return VL_SHIFTRS_WWW(obits, lbits, rbits, owp, lwp, rwp); } static inline IData VL_SHIFTRS_IIW(int obits, int lbits, int rbits, IData lhs, WDataInP rwp) VL_MT_SAFE { EData overshift = 0; // Huge shift 1>>32 or more for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; if (VL_UNLIKELY(overshift)) { IData sign = -(lhs >> (lbits - 1)); // ffff_ffff if negative return VL_CLEAN_II(obits, obits, sign); } return VL_SHIFTRS_III(obits, lbits, 32, lhs, rwp[0]); } static inline QData VL_SHIFTRS_QQW(int obits, int lbits, int rbits, QData lhs, WDataInP rwp) VL_MT_SAFE { EData overshift = 0; // Huge shift 1>>32 or more for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; if (VL_UNLIKELY(overshift)) { QData sign = -(lhs >> (lbits - 1)); // ffff_ffff if negative return VL_CLEAN_QQ(obits, obits, sign); } return VL_SHIFTRS_QQI(obits, lbits, 32, lhs, rwp[0]); } static inline IData VL_SHIFTRS_IIQ(int obits, int lbits, int rbits, IData lhs, QData rhs) VL_PURE { WData rwp[VL_WQ_WORDS_E]; VL_SET_WQ(rwp, rhs); return VL_SHIFTRS_IIW(obits, lbits, rbits, lhs, rwp); } static inline QData VL_SHIFTRS_QQQ(int obits, int lbits, int rbits, QData lhs, QData rhs) VL_PURE { WData rwp[VL_WQ_WORDS_E]; VL_SET_WQ(rwp, rhs); return VL_SHIFTRS_QQW(obits, lbits, rbits, lhs, rwp); } //=================================================================== // Bit selection // EMIT_RULE: VL_BITSEL: oclean=dirty; rclean==clean; #define VL_BITSEL_IIII(obits, lbits, rbits, zbits, lhs, rhs) ((lhs) >> (rhs)) #define VL_BITSEL_QIII(obits, lbits, rbits, zbits, lhs, rhs) ((lhs) >> (rhs)) #define VL_BITSEL_QQII(obits, lbits, rbits, zbits, lhs, rhs) ((lhs) >> (rhs)) #define VL_BITSEL_IQII(obits, lbits, rbits, zbits, lhs, rhs) (static_cast((lhs) >> (rhs))) static inline IData VL_BITSEL_IWII(int, int lbits, int, int, WDataInP lwp, IData rd) VL_MT_SAFE { int word = VL_BITWORD_E(rd); if (VL_UNLIKELY(rd > static_cast(lbits))) { return ~0; // Spec says you can go outside the range of a array. Don't coredump if so. // We return all 1's as that's more likely to find bugs (?) than 0's. } else { return (lwp[word] >> VL_BITBIT_E(rd)); } } // EMIT_RULE: VL_RANGE: oclean=lclean; out=dirty // & MUST BE CLEAN (currently constant) #define VL_SEL_IIII(obits, lbits, rbits, tbits, lhs, lsb, width) ((lhs) >> (lsb)) #define VL_SEL_QQII(obits, lbits, rbits, tbits, lhs, lsb, width) ((lhs) >> (lsb)) #define VL_SEL_IQII(obits, lbits, rbits, tbits, lhs, lsb, width) \ (static_cast((lhs) >> (lsb))) static inline IData VL_SEL_IWII(int, int lbits, int, int, WDataInP lwp, IData lsb, IData width) VL_MT_SAFE { int msb = lsb + width - 1; if (VL_UNLIKELY(msb > lbits)) { return ~0; // Spec says you can go outside the range of a array. Don't coredump if so. } else if (VL_BITWORD_E(msb) == VL_BITWORD_E(static_cast(lsb))) { return VL_BITRSHIFT_W(lwp, lsb); } else { // 32 bit extraction may span two words int nbitsfromlow = VL_EDATASIZE - VL_BITBIT_E(lsb); // bits that come from low word return ((lwp[VL_BITWORD_E(msb)] << nbitsfromlow) | VL_BITRSHIFT_W(lwp, lsb)); } } static inline QData VL_SEL_QWII(int, int lbits, int, int, WDataInP lwp, IData lsb, IData width) VL_MT_SAFE { int msb = lsb + width - 1; if (VL_UNLIKELY(msb > lbits)) { return ~0; // Spec says you can go outside the range of a array. Don't coredump if so. } else if (VL_BITWORD_E(msb) == VL_BITWORD_E(static_cast(lsb))) { return VL_BITRSHIFT_W(lwp, lsb); } else if (VL_BITWORD_E(msb) == 1 + VL_BITWORD_E(static_cast(lsb))) { int nbitsfromlow = VL_EDATASIZE - VL_BITBIT_E(lsb); QData hi = (lwp[VL_BITWORD_E(msb)]); QData lo = VL_BITRSHIFT_W(lwp, lsb); return (hi << nbitsfromlow) | lo; } else { // 64 bit extraction may span three words int nbitsfromlow = VL_EDATASIZE - VL_BITBIT_E(lsb); QData hi = (lwp[VL_BITWORD_E(msb)]); QData mid = (lwp[VL_BITWORD_E(lsb) + 1]); QData lo = VL_BITRSHIFT_W(lwp, lsb); return (hi << (nbitsfromlow + VL_EDATASIZE)) | (mid << nbitsfromlow) | lo; } } static inline WDataOutP VL_SEL_WWII(int obits, int lbits, int, int, WDataOutP owp, WDataInP lwp, IData lsb, IData width) VL_MT_SAFE { int msb = lsb + width - 1; int word_shift = VL_BITWORD_E(lsb); if (VL_UNLIKELY(msb > lbits)) { // Outside bounds, for (int i = 0; i < VL_WORDS_I(obits) - 1; ++i) owp[i] = ~0; owp[VL_WORDS_I(obits) - 1] = VL_MASK_E(obits); } else if (VL_BITBIT_E(lsb) == 0) { // Just a word extract for (int i = 0; i < VL_WORDS_I(obits); ++i) owp[i] = lwp[i + word_shift]; } else { // Not a _VL_INSERT because the bits come from any bit number and goto bit 0 int loffset = lsb & VL_SIZEBITS_E; int nbitsfromlow = VL_EDATASIZE - loffset; // bits that end up in lword (know loffset!=0) // Middle words int words = VL_WORDS_I(msb - lsb + 1); for (int i = 0; i < words; ++i) { owp[i] = lwp[i + word_shift] >> loffset; int upperword = i + word_shift + 1; if (upperword <= static_cast(VL_BITWORD_E(msb))) { owp[i] |= lwp[upperword] << nbitsfromlow; } } for (int i = words; i < VL_WORDS_I(obits); ++i) owp[i] = 0; } return owp; } //====================================================================== // Math needing insert/select /// Return QData from double (numeric) // EMIT_RULE: VL_RTOIROUND_Q_D: oclean=dirty; lclean==clean/real static inline QData VL_RTOIROUND_Q_D(int, double lhs) VL_PURE { // IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa // This does not need to support subnormals as they are sub-integral lhs = VL_ROUND(lhs); if (lhs == 0.0) return 0; QData q = VL_CVT_Q_D(lhs); int lsb = static_cast((q >> 52ULL) & VL_MASK_Q(11)) - 1023 - 52; vluint64_t mantissa = (q & VL_MASK_Q(52)) | (1ULL << 52); vluint64_t out = 0; if (lsb < 0) { out = mantissa >> -lsb; } else if (lsb < 64) { out = mantissa << lsb; } if (lhs < 0) out = -out; return out; } static inline IData VL_RTOIROUND_I_D(int bits, double lhs) VL_PURE { return static_cast(VL_RTOIROUND_Q_D(bits, lhs)); } static inline WDataOutP VL_RTOIROUND_W_D(int obits, WDataOutP owp, double lhs) VL_PURE { // IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa // This does not need to support subnormals as they are sub-integral lhs = VL_ROUND(lhs); VL_ZERO_W(obits, owp); if (lhs == 0.0) return owp; QData q = VL_CVT_Q_D(lhs); int lsb = static_cast((q >> 52ULL) & VL_MASK_Q(11)) - 1023 - 52; vluint64_t mantissa = (q & VL_MASK_Q(52)) | (1ULL << 52); if (lsb < 0) { VL_SET_WQ(owp, mantissa >> -lsb); } else if (lsb < obits) { _VL_INSERT_WQ(obits, owp, mantissa, lsb + 52, lsb); } if (lhs < 0) VL_NEGATE_INPLACE_W(VL_WORDS_I(obits), owp); return owp; } //====================================================================== // Range assignments // EMIT_RULE: VL_ASSIGNRANGE: rclean=dirty; static inline void VL_ASSIGNSEL_IIII(int obits, int lsb, CData& lhsr, IData rhs) VL_PURE { _VL_INSERT_II(obits, lhsr, rhs, lsb + obits - 1, lsb); } static inline void VL_ASSIGNSEL_IIII(int obits, int lsb, SData& lhsr, IData rhs) VL_PURE { _VL_INSERT_II(obits, lhsr, rhs, lsb + obits - 1, lsb); } static inline void VL_ASSIGNSEL_IIII(int obits, int lsb, IData& lhsr, IData rhs) VL_PURE { _VL_INSERT_II(obits, lhsr, rhs, lsb + obits - 1, lsb); } static inline void VL_ASSIGNSEL_QIII(int obits, int lsb, QData& lhsr, IData rhs) VL_PURE { _VL_INSERT_QQ(obits, lhsr, rhs, lsb + obits - 1, lsb); } static inline void VL_ASSIGNSEL_QQII(int obits, int lsb, QData& lhsr, QData rhs) VL_PURE { _VL_INSERT_QQ(obits, lhsr, rhs, lsb + obits - 1, lsb); } static inline void VL_ASSIGNSEL_QIIQ(int obits, int lsb, QData& lhsr, QData rhs) VL_PURE { _VL_INSERT_QQ(obits, lhsr, rhs, lsb + obits - 1, lsb); } // static inline void VL_ASSIGNSEL_IIIW(int obits, int lsb, IData& lhsr, WDataInP rwp) VL_MT_SAFE { // Illegal, as lhs width >= rhs width static inline void VL_ASSIGNSEL_WIII(int obits, int lsb, WDataOutP owp, IData rhs) VL_MT_SAFE { _VL_INSERT_WI(obits, owp, rhs, lsb + obits - 1, lsb); } static inline void VL_ASSIGNSEL_WIIQ(int obits, int lsb, WDataOutP owp, QData rhs) VL_MT_SAFE { _VL_INSERT_WQ(obits, owp, rhs, lsb + obits - 1, lsb); } static inline void VL_ASSIGNSEL_WIIW(int obits, int lsb, WDataOutP owp, WDataInP rwp) VL_MT_SAFE { _VL_INSERT_WW(obits, owp, rwp, lsb + obits - 1, lsb); } //====================================================================== // Triops static inline WDataOutP VL_COND_WIWW(int obits, int, int, int, WDataOutP owp, int cond, WDataInP w1p, WDataInP w2p) VL_MT_SAFE { int words = VL_WORDS_I(obits); for (int i = 0; i < words; ++i) owp[i] = cond ? w1p[i] : w2p[i]; return owp; } //====================================================================== // Constification // VL_CONST_W_#X(int obits, WDataOutP owp, IData data0, .... IData data(#-1)) // Sets wide vector words to specified constant words. // These macros are used when o might represent more words then are given as constants, // hence all upper words must be zeroed. // If changing the number of functions here, also change EMITCINLINES_NUM_CONSTW #define _END(obits, wordsSet) \ for (int i = (wordsSet); i < VL_WORDS_I(obits); ++i) o[i] = 0; \ return o // clang-format off static inline WDataOutP VL_CONST_W_1X(int obits, WDataOutP o, EData d0) VL_MT_SAFE { o[0] = d0; _END(obits, 1); } static inline WDataOutP VL_CONST_W_2X(int obits, WDataOutP o, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; _END(obits, 2); } static inline WDataOutP VL_CONST_W_3X(int obits, WDataOutP o, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; _END(obits,3); } static inline WDataOutP VL_CONST_W_4X(int obits, WDataOutP o, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; _END(obits,4); } static inline WDataOutP VL_CONST_W_5X(int obits, WDataOutP o, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; _END(obits,5); } static inline WDataOutP VL_CONST_W_6X(int obits, WDataOutP o, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; _END(obits,6); } static inline WDataOutP VL_CONST_W_7X(int obits, WDataOutP o, EData d6, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; o[6] = d6; _END(obits,7); } static inline WDataOutP VL_CONST_W_8X(int obits, WDataOutP o, EData d7, EData d6, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; o[6] = d6; o[7] = d7; _END(obits,8); } // static inline WDataOutP VL_CONSTHI_W_1X(int obits, int lsb, WDataOutP obase, EData d0) VL_MT_SAFE { WDataOutP o = obase + VL_WORDS_I(lsb); o[0] = d0; _END(obits,1); } static inline WDataOutP VL_CONSTHI_W_2X(int obits, int lsb, WDataOutP obase, EData d1, EData d0) VL_MT_SAFE { WDataOutP o = obase + VL_WORDS_I(lsb); o[0] = d0; o[1] = d1; _END(obits,2); } static inline WDataOutP VL_CONSTHI_W_3X(int obits, int lsb, WDataOutP obase, EData d2, EData d1, EData d0) VL_MT_SAFE { WDataOutP o = obase + VL_WORDS_I(lsb); o[0] = d0; o[1] = d1; o[2] = d2; _END(obits,3); } static inline WDataOutP VL_CONSTHI_W_4X(int obits, int lsb, WDataOutP obase, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { WDataOutP o = obase + VL_WORDS_I(lsb); o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; _END(obits,4); } static inline WDataOutP VL_CONSTHI_W_5X(int obits, int lsb, WDataOutP obase, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { WDataOutP o = obase + VL_WORDS_I(lsb); o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; _END(obits,5); } static inline WDataOutP VL_CONSTHI_W_6X(int obits, int lsb, WDataOutP obase, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { WDataOutP o = obase + VL_WORDS_I(lsb); o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; _END(obits,6); } static inline WDataOutP VL_CONSTHI_W_7X(int obits, int lsb, WDataOutP obase, EData d6, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { WDataOutP o = obase + VL_WORDS_I(lsb); o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; o[6] = d6; _END(obits,7); } static inline WDataOutP VL_CONSTHI_W_8X(int obits, int lsb, WDataOutP obase, EData d7, EData d6, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { WDataOutP o = obase + VL_WORDS_I(lsb); o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; o[6] = d6; o[7] = d7; _END(obits,8); } #undef _END // Partial constant, lower words of vector wider than 8*32, starting at bit number lsb static inline void VL_CONSTLO_W_8X(int lsb, WDataOutP obase, EData d7, EData d6, EData d5, EData d4, EData d3, EData d2, EData d1, EData d0) VL_MT_SAFE { WDataOutP o = obase + VL_WORDS_I(lsb); o[0] = d0; o[1] = d1; o[2] = d2; o[3] = d3; o[4] = d4; o[5] = d5; o[6] = d6; o[7] = d7; } // clang-format on //====================================================================== #endif // Guard verilator-4.038/include/verilated_vcd_c.cpp0000664000177100017500000007450713702133367021002 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief C++ Tracing in VCD Format /// //============================================================================= // SPDIFF_OFF // clang-format off #include "verilatedos.h" #include "verilated.h" #include "verilated_vcd_c.h" #include #include #include #include #if defined(_WIN32) && !defined(__MINGW32__) && !defined(__CYGWIN__) # include #else # include #endif // SPDIFF_ON #ifndef O_LARGEFILE // For example on WIN32 # define O_LARGEFILE 0 #endif #ifndef O_NONBLOCK # define O_NONBLOCK 0 #endif #ifndef O_CLOEXEC # define O_CLOEXEC 0 #endif // clang-format on // This size comes form VCD allowing use of printable ASCII characters between // '!' and '~' inclusive, which are a total of 94 different values. Encoding a // 32 bit code hence needs a maximum of ceil(log94(2**32-1)) == 5 bytes. #define VL_TRACE_MAX_VCD_CODE_SIZE 5 ///< Maximum length of a VCD string code // We use 8 bytes per code in a suffix buffer array. // 1 byte optional separator + VL_TRACE_MAX_VCD_CODE_SIZE bytes for code // + 1 byte '\n' + 1 byte suffix size. This luckily comes out to a power of 2, // meaning the array can be aligned such that entries never straddle multiple // cache-lines. #define VL_TRACE_SUFFIX_ENTRY_SIZE 8 ///< Size of a suffix entry //============================================================================= // Specialization of the generics for this trace format #define VL_DERIVED_T VerilatedVcd #include "verilated_trace_imp.cpp" #undef VL_DERIVED_T //============================================================================= //============================================================================= //============================================================================= // VerilatedVcdFile bool VerilatedVcdFile::open(const std::string& name) VL_MT_UNSAFE { m_fd = ::open(name.c_str(), O_CREAT | O_WRONLY | O_TRUNC | O_LARGEFILE | O_NONBLOCK | O_CLOEXEC, 0666); return m_fd >= 0; } void VerilatedVcdFile::close() VL_MT_UNSAFE { ::close(m_fd); } ssize_t VerilatedVcdFile::write(const char* bufp, ssize_t len) VL_MT_UNSAFE { return ::write(m_fd, bufp, len); } //============================================================================= //============================================================================= //============================================================================= // Opening/Closing VerilatedVcd::VerilatedVcd(VerilatedVcdFile* filep) : m_isOpen(false) , m_rolloverMB(0) , m_modDepth(0) { // Not in header to avoid link issue if header is included without this .cpp file m_fileNewed = (filep == NULL); m_filep = m_fileNewed ? new VerilatedVcdFile : filep; m_namemapp = NULL; m_evcd = false; m_wrChunkSize = 8 * 1024; m_wrBufp = new char[m_wrChunkSize * 8]; m_wrFlushp = m_wrBufp + m_wrChunkSize * 6; m_writep = m_wrBufp; m_wroteBytes = 0; m_suffixesp = NULL; } void VerilatedVcd::open(const char* filename) { m_assertOne.check(); if (isOpen()) return; // Set member variables m_filename = filename; // "" is ok, as someone may overload open openNext(m_rolloverMB != 0); if (!isOpen()) return; dumpHeader(); // Get the direct access pointer to the code strings m_suffixesp = &m_suffixes[0]; // Note: C++11 m_suffixes.data(); // When using rollover, the first chunk contains the header only. if (m_rolloverMB) openNext(true); } void VerilatedVcd::openNext(bool incFilename) { // Open next filename in concat sequence, mangle filename if // incFilename is true. m_assertOne.check(); closePrev(); // Close existing if (incFilename) { // Find _0000.{ext} in filename std::string name = m_filename; size_t pos = name.rfind('.'); if (pos > 8 && 0 == strncmp("_cat", name.c_str() + pos - 8, 4) && isdigit(name.c_str()[pos - 4]) && isdigit(name.c_str()[pos - 3]) && isdigit(name.c_str()[pos - 2]) && isdigit(name.c_str()[pos - 1])) { // Increment code. if ((++(name[pos - 1])) > '9') { name[pos - 1] = '0'; if ((++(name[pos - 2])) > '9') { name[pos - 2] = '0'; if ((++(name[pos - 3])) > '9') { name[pos - 3] = '0'; if ((++(name[pos - 4])) > '9') { name[pos - 4] = '0'; } } } } } else { // Append _cat0000 name.insert(pos, "_cat0000"); } m_filename = name; } if (VL_UNCOVERABLE(m_filename[0] == '|')) { assert(0); // LCOV_EXCL_LINE // Not supported yet. } else { // cppcheck-suppress duplicateExpression if (!m_filep->open(m_filename)) { // User code can check isOpen() m_isOpen = false; return; } } m_isOpen = true; fullDump(true); // First dump must be full m_wroteBytes = 0; } bool VerilatedVcd::preChangeDump() { if (VL_UNLIKELY(m_rolloverMB && m_wroteBytes > m_rolloverMB)) { openNext(true); } return isOpen(); } void VerilatedVcd::emitTimeChange(vluint64_t timeui) { printStr("#"); printQuad(timeui); printStr("\n"); } void VerilatedVcd::makeNameMap() { // Take signal information from each module and build m_namemapp deleteNameMap(); m_namemapp = new NameMap; VerilatedTrace::traceInit(); // Though not speced, it's illegal to generate a vcd with signals // not under any module - it crashes at least two viewers. // If no scope was specified, prefix everything with a "top" // This comes from user instantiations with no name - IE Vtop(""). bool nullScope = false; for (NameMap::const_iterator it = m_namemapp->begin(); it != m_namemapp->end(); ++it) { const std::string& hiername = it->first; if (!hiername.empty() && hiername[0] == '\t') nullScope = true; } if (nullScope) { NameMap* newmapp = new NameMap; for (NameMap::const_iterator it = m_namemapp->begin(); it != m_namemapp->end(); ++it) { const std::string& hiername = it->first; const std::string& decl = it->second; std::string newname = std::string("top"); if (hiername[0] != '\t') newname += ' '; newname += hiername; newmapp->insert(std::make_pair(newname, decl)); } deleteNameMap(); m_namemapp = newmapp; } } void VerilatedVcd::deleteNameMap() { if (m_namemapp) VL_DO_CLEAR(delete m_namemapp, m_namemapp = NULL); } VerilatedVcd::~VerilatedVcd() { close(); if (m_wrBufp) VL_DO_CLEAR(delete[] m_wrBufp, m_wrBufp = NULL); deleteNameMap(); if (m_filep && m_fileNewed) VL_DO_CLEAR(delete m_filep, m_filep = NULL); } void VerilatedVcd::closePrev() { // This function is on the flush() call path if (!isOpen()) return; VerilatedTrace::flush(); bufferFlush(); m_isOpen = false; m_filep->close(); } void VerilatedVcd::closeErr() { // This function is on the flush() call path // Close due to an error. We might abort before even getting here, // depending on the definition of vl_fatal. if (!isOpen()) return; // No buffer flush, just fclose m_isOpen = false; m_filep->close(); // May get error, just ignore it } void VerilatedVcd::close() { // This function is on the flush() call path m_assertOne.check(); if (!isOpen()) return; if (m_evcd) { printStr("$vcdclose "); printQuad(timeLastDump()); printStr(" $end\n"); } closePrev(); // closePrev() called VerilatedTrace::flush(), so we just // need to shut down the tracing thread here. VerilatedTrace::close(); } void VerilatedVcd::flush() { VerilatedTrace::flush(); bufferFlush(); } void VerilatedVcd::printStr(const char* str) { // Not fast... while (*str) { *m_writep++ = *str++; bufferCheck(); } } void VerilatedVcd::printQuad(vluint64_t n) { char buf[100]; sprintf(buf, "%" VL_PRI64 "u", n); printStr(buf); } void VerilatedVcd::bufferResize(vluint64_t minsize) { // minsize is size of largest write. We buffer at least 8 times as much data, // writing when we are 3/4 full (with thus 2*minsize remaining free) if (VL_UNLIKELY(minsize > m_wrChunkSize)) { char* oldbufp = m_wrBufp; m_wrChunkSize = minsize * 2; m_wrBufp = new char[m_wrChunkSize * 8]; memcpy(m_wrBufp, oldbufp, m_writep - oldbufp); m_writep = m_wrBufp + (m_writep - oldbufp); m_wrFlushp = m_wrBufp + m_wrChunkSize * 6; VL_DO_CLEAR(delete[] oldbufp, oldbufp = NULL); } } void VerilatedVcd::bufferFlush() VL_MT_UNSAFE_ONE { // This function can be called from the trace thread // This function is on the flush() call path // We add output data to m_writep. // When it gets nearly full we dump it using this routine which calls write() // This is much faster than using buffered I/O m_assertOne.check(); if (VL_UNLIKELY(!isOpen())) return; char* wp = m_wrBufp; while (true) { ssize_t remaining = (m_writep - wp); if (remaining == 0) break; errno = 0; ssize_t got = m_filep->write(wp, remaining); if (got > 0) { wp += got; m_wroteBytes += got; } else if (VL_UNCOVERABLE(got < 0)) { if (VL_UNCOVERABLE(errno != EAGAIN && errno != EINTR)) { // LCOV_EXCL_START // write failed, presume error (perhaps out of disk space) std::string msg = std::string("VerilatedVcd::bufferFlush: ") + strerror(errno); VL_FATAL_MT("", 0, "", msg.c_str()); closeErr(); break; // LCOV_EXCL_STOP } } } // Reset buffer m_writep = m_wrBufp; } //============================================================================= // VCD string code char* VerilatedVcd::writeCode(char* writep, vluint32_t code) { *writep++ = static_cast('!' + code % 94); code /= 94; while (code) { code--; *writep++ = static_cast('!' + code % 94); code /= 94; } return writep; } //============================================================================= // Definitions void VerilatedVcd::printIndent(int level_change) { if (level_change < 0) m_modDepth += level_change; assert(m_modDepth >= 0); for (int i = 0; i < m_modDepth; i++) printStr(" "); if (level_change > 0) m_modDepth += level_change; } void VerilatedVcd::dumpHeader() { printStr("$version Generated by VerilatedVcd $end\n"); time_t time_str = time(NULL); printStr("$date "); printStr(ctime(&time_str)); printStr(" $end\n"); printStr("$timescale "); printStr(timeResStr().c_str()); // lintok-begin-on-ref printStr(" $end\n"); makeNameMap(); // Signal header assert(m_modDepth == 0); printIndent(1); printStr("\n"); // We detect the spaces in module names to determine hierarchy. This // allows signals to be declared without fixed ordering, which is // required as Verilog signals might be separately declared from // SC module signals. // Print the signal names const char* lastName = ""; for (NameMap::const_iterator it = m_namemapp->begin(); it != m_namemapp->end(); ++it) { const std::string& hiernamestr = it->first; const std::string& decl = it->second; // Determine difference between the old and new names const char* hiername = hiernamestr.c_str(); const char* lp = lastName; const char* np = hiername; lastName = hiername; // Skip common prefix, it must break at a space or tab for (; *np && (*np == *lp); np++, lp++) {} while (np != hiername && *np && *np != ' ' && *np != '\t') { np--; lp--; } // printf("hier %s\n lp=%s\n np=%s\n",hiername,lp,np); // Any extra spaces in last name are scope ups we need to do bool first = true; for (; *lp; lp++) { if (*lp == ' ' || (first && *lp != '\t')) { printIndent(-1); printStr("$upscope $end\n"); } first = false; } // Any new spaces are scope downs we need to do while (*np) { if (*np == ' ') np++; if (*np == '\t') break; // tab means signal name starts printIndent(1); printStr("$scope module "); for (; *np && *np != ' ' && *np != '\t'; np++) { if (*np == '[') { printStr("("); } else if (*np == ']') { printStr(")"); } else { *m_writep++ = *np; } } printStr(" $end\n"); } printIndent(0); printStr(decl.c_str()); } while (m_modDepth > 1) { printIndent(-1); printStr("$upscope $end\n"); } printIndent(-1); printStr("$enddefinitions $end\n\n\n"); assert(m_modDepth == 0); // Reclaim storage deleteNameMap(); } void VerilatedVcd::declare(vluint32_t code, const char* name, const char* wirep, bool array, int arraynum, bool tri, bool bussed, int msb, int lsb) { const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1; VerilatedTrace::declCode(code, bits, tri); if (m_suffixes.size() <= nextCode() * VL_TRACE_SUFFIX_ENTRY_SIZE) { m_suffixes.resize(nextCode() * VL_TRACE_SUFFIX_ENTRY_SIZE * 2, 0); } // Make sure write buffer is large enough (one character per bit), plus header bufferResize(bits + 1024); // Split name into basename // Spaces and tabs aren't legal in VCD signal names, so: // Space separates each level of scope // Tab separates final scope from signal name // Tab sorts before spaces, so signals nicely will print before scopes // Note the hiername may be nothing, if so we'll add "\t{name}" std::string nameasstr = name; if (!moduleName().empty()) { nameasstr = moduleName() + scopeEscape() + nameasstr; // Optional ->module prefix } std::string hiername; std::string basename; for (const char* cp = nameasstr.c_str(); *cp; cp++) { if (isScopeEscape(*cp)) { // Ahh, we've just read a scope, not a basename if (!hiername.empty()) hiername += " "; hiername += basename; basename = ""; } else { basename += *cp; } } hiername += "\t" + basename; // Print reference std::string decl = "$var "; if (m_evcd) { decl += "port"; } else { decl += wirep; // usually "wire" } char buf[1000]; sprintf(buf, " %2d ", bits); decl += buf; if (m_evcd) { sprintf(buf, "<%u", code); decl += buf; } else { // Add string code to decl char* const endp = writeCode(buf, code); *endp = '\0'; decl += buf; // Build suffix array entry char* const entryp = &m_suffixes[code * VL_TRACE_SUFFIX_ENTRY_SIZE]; const size_t length = endp - buf; assert(length <= VL_TRACE_MAX_VCD_CODE_SIZE); // 1 bit values don't have a ' ' separator between value and string code const bool isBit = bits == 1; entryp[0] = ' '; // Separator std::strcpy(entryp + !isBit, buf); // Code (overwrite separator if isBit) entryp[length + !isBit] = '\n'; // Replace '\0' with line termination '\n' // Set length of suffix (used to increment write pointer) entryp[VL_TRACE_SUFFIX_ENTRY_SIZE - 1] = !isBit + length + 1; } decl += " "; decl += basename; if (array) { sprintf(buf, "(%d)", arraynum); decl += buf; hiername += buf; } if (bussed) { sprintf(buf, " [%d:%d]", msb, lsb); decl += buf; } decl += " $end\n"; m_namemapp->insert(std::make_pair(hiername, decl)); } void VerilatedVcd::declBit(vluint32_t code, const char* name, bool array, int arraynum) { declare(code, name, "wire", array, arraynum, false, false, 0, 0); } void VerilatedVcd::declBus(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, false, true, msb, lsb); } void VerilatedVcd::declQuad(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, false, true, msb, lsb); } void VerilatedVcd::declArray(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, false, true, msb, lsb); } void VerilatedVcd::declDouble(vluint32_t code, const char* name, bool array, int arraynum) { declare(code, name, "real", array, arraynum, false, false, 63, 0); } #ifdef VL_TRACE_VCD_OLD_API void VerilatedVcd::declTriBit(vluint32_t code, const char* name, bool array, int arraynum) { declare(code, name, "wire", array, arraynum, true, false, 0, 0); } void VerilatedVcd::declTriBus(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, true, true, msb, lsb); } void VerilatedVcd::declTriQuad(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, true, true, msb, lsb); } void VerilatedVcd::declTriArray(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, true, true, msb, lsb); } #endif // VL_TRACE_VCD_OLD_API //============================================================================= // Trace rendering prinitives void VerilatedVcd::finishLine(vluint32_t code, char* writep) { const char* const suffixp = m_suffixesp + code * VL_TRACE_SUFFIX_ENTRY_SIZE; // Copy the whole suffix (this avoid having hard to predict branches which // helps a lot). Note: The maximum length of the suffix is // VL_TRACE_MAX_VCD_CODE_SIZE + 2 == 7, but we unroll this here for speed. #ifdef VL_X86_64 // Copy the whole 8 bytes in one go, this works on little-endian machines // supporting unaligned stores. *reinterpret_cast(writep) = *reinterpret_cast(suffixp); #else // Portable variant writep[0] = suffixp[0]; writep[1] = suffixp[1]; writep[2] = suffixp[2]; writep[3] = suffixp[3]; writep[4] = suffixp[4]; writep[5] = suffixp[5]; writep[6] = '\n'; // The 6th index is always '\n' if it's relevant, no need to fetch it. #endif // Now write back the write pointer incremented by the actual size of the // suffix, which was stored in the last byte of the suffix buffer entry. m_writep = writep + suffixp[VL_TRACE_SUFFIX_ENTRY_SIZE - 1]; bufferCheck(); } //============================================================================= // emit* trace routines // Note: emit* are only ever called from one place (full* in // verilated_trace_imp.cpp, which is included in this file at the top), // so always inline them. VL_ATTR_ALWINLINE void VerilatedVcd::emitBit(vluint32_t code, CData newval) { // Don't prefetch suffix as it's a bit too late; char* wp = m_writep; *wp++ = '0' | static_cast(newval); finishLine(code, wp); } VL_ATTR_ALWINLINE void VerilatedVcd::emitCData(vluint32_t code, CData newval, int bits) { char* wp = m_writep; *wp++ = 'b'; cvtCDataToStr(wp, newval << (VL_BYTESIZE - bits)); finishLine(code, wp + bits); } VL_ATTR_ALWINLINE void VerilatedVcd::emitSData(vluint32_t code, SData newval, int bits) { char* wp = m_writep; *wp++ = 'b'; cvtSDataToStr(wp, newval << (VL_SHORTSIZE - bits)); finishLine(code, wp + bits); } VL_ATTR_ALWINLINE void VerilatedVcd::emitIData(vluint32_t code, IData newval, int bits) { char* wp = m_writep; *wp++ = 'b'; cvtIDataToStr(wp, newval << (VL_IDATASIZE - bits)); finishLine(code, wp + bits); } VL_ATTR_ALWINLINE void VerilatedVcd::emitQData(vluint32_t code, QData newval, int bits) { char* wp = m_writep; *wp++ = 'b'; cvtQDataToStr(wp, newval << (VL_QUADSIZE - bits)); finishLine(code, wp + bits); } VL_ATTR_ALWINLINE void VerilatedVcd::emitWData(vluint32_t code, const WData* newvalp, int bits) { int words = VL_WORDS_I(bits); char* wp = m_writep; *wp++ = 'b'; // Handle the most significant word const int bitsInMSW = VL_BITBIT_E(bits) ? VL_BITBIT_E(bits) : VL_EDATASIZE; cvtEDataToStr(wp, newvalp[--words] << (VL_EDATASIZE - bitsInMSW)); wp += bitsInMSW; // Handle the remaining words while (words > 0) { cvtEDataToStr(wp, newvalp[--words]); wp += VL_EDATASIZE; } finishLine(code, wp); } VL_ATTR_ALWINLINE void VerilatedVcd::emitDouble(vluint32_t code, double newval) { char* wp = m_writep; // Buffer can't overflow before sprintf; we sized during declaration sprintf(wp, "r%.16g", newval); wp += strlen(wp); finishLine(code, wp); } #ifdef VL_TRACE_VCD_OLD_API void VerilatedVcd::fullBit(vluint32_t code, const vluint32_t newval) { // Note the &1, so we don't require clean input -- makes more common no change case faster *oldp(code) = newval; *m_writep++ = ('0' + static_cast(newval & 1)); m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } void VerilatedVcd::fullBus(vluint32_t code, const vluint32_t newval, int bits) { *oldp(code) = newval; *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { *m_writep++ = ((newval & (1L << bit)) ? '1' : '0'); } *m_writep++ = ' '; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } void VerilatedVcd::fullQuad(vluint32_t code, const vluint64_t newval, int bits) { (*(reinterpret_cast(oldp(code)))) = newval; *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { *m_writep++ = ((newval & (1ULL << bit)) ? '1' : '0'); } *m_writep++ = ' '; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } void VerilatedVcd::fullArray(vluint32_t code, const vluint32_t* newval, int bits) { for (int word = 0; word < (((bits - 1) / 32) + 1); ++word) { oldp(code)[word] = newval[word]; } *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { *m_writep++ = ((newval[(bit / 32)] & (1L << (bit & 0x1f))) ? '1' : '0'); } *m_writep++ = ' '; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } void VerilatedVcd::fullArray(vluint32_t code, const vluint64_t* newval, int bits) { for (int word = 0; word < (((bits - 1) / 64) + 1); ++word) { oldp(code)[word] = newval[word]; } *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { *m_writep++ = ((newval[(bit / 64)] & (1ULL << (bit & 0x3f))) ? '1' : '0'); } *m_writep++ = ' '; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } void VerilatedVcd::fullTriBit(vluint32_t code, const vluint32_t newval, const vluint32_t newtri) { oldp(code)[0] = newval; oldp(code)[1] = newtri; *m_writep++ = "01zz"[newval | (newtri << 1)]; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } void VerilatedVcd::fullTriBus(vluint32_t code, const vluint32_t newval, const vluint32_t newtri, int bits) { oldp(code)[0] = newval; oldp(code)[1] = newtri; *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { *m_writep++ = "01zz"[((newval >> bit) & 1) | (((newtri >> bit) & 1) << 1)]; } *m_writep++ = ' '; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } void VerilatedVcd::fullTriQuad(vluint32_t code, const vluint64_t newval, const vluint64_t newtri, int bits) { (*(reinterpret_cast(oldp(code)))) = newval; (*(reinterpret_cast(oldp(code + 1)))) = newtri; *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { *m_writep++ = "01zz"[((newval >> bit) & 1ULL) | (((newtri >> bit) & 1ULL) << 1ULL)]; } *m_writep++ = ' '; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } void VerilatedVcd::fullTriArray(vluint32_t code, const vluint32_t* newvalp, const vluint32_t* newtrip, int bits) { for (int word = 0; word < (((bits - 1) / 32) + 1); ++word) { oldp(code)[word * 2] = newvalp[word]; oldp(code)[word * 2 + 1] = newtrip[word]; } *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { vluint32_t valbit = (newvalp[(bit / 32)] >> (bit & 0x1f)) & 1; vluint32_t tribit = (newtrip[(bit / 32)] >> (bit & 0x1f)) & 1; *m_writep++ = "01zz"[valbit | (tribit << 1)]; } *m_writep++ = ' '; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } void VerilatedVcd::fullDouble(vluint32_t code, const double newval) { // cppcheck-suppress invalidPointerCast (*(reinterpret_cast(oldp(code)))) = newval; // Buffer can't overflow before sprintf; we sized during declaration sprintf(m_writep, "r%.16g", newval); m_writep += strlen(m_writep); *m_writep++ = ' '; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; bufferCheck(); } #endif // VL_TRACE_VCD_OLD_API //====================================================================== //====================================================================== //====================================================================== #ifdef VERILATED_VCD_TEST #include vluint32_t v1, v2, s1, s2[3]; vluint32_t tri96[3]; vluint32_t tri96__tri[3]; vluint64_t quad96[2]; vluint64_t tquad; vluint64_t tquad__tri; vluint8_t ch; vluint64_t timestamp = 1; double doub = 0.0; float flo = 0.0f; void vcdInit(void*, VerilatedVcd* vcdp, vluint32_t) { vcdp->scopeEscape('.'); vcdp->module("top"); /**/ vcdp->declBus(0x2, "v1", -1, 0, 5, 1); /**/ vcdp->declBus(0x3, "v2", -1, 0, 6, 1); /**/ vcdp->module("top.sub1"); /***/ vcdp->declBit(0x4, "s1", -1, 0); /***/ vcdp->declBit(0x5, "ch", -1, 0); /**/ vcdp->module("top.sub2"); /***/ vcdp->declArray(0x6, "s2", -1, 0, 40, 3); // Note need to add 3 for next code. vcdp->module("top2"); /**/ vcdp->declBus(0x2, "t2v1", -1, 0, 4, 1); /**/ vcdp->declTriBit(0x10, "io1", -1, 0); /**/ vcdp->declTriBus(0x12, "io5", -1, 0, 4, 0); /**/ vcdp->declTriArray(0x16, "io96", -1, 0, 95, 0); /**/ // Note need to add 6 for next code. /**/ vcdp->declDouble(0x1c, "doub", -1, 0); /**/ // Note need to add 2 for next code. /**/ vcdp->declArray(0x20, "q2", -1, 0, 95, 0); /**/ // Note need to add 4 for next code. /**/ vcdp->declTriQuad(0x24, "tq", -1, 0, 63, 0); /**/ // Note need to add 4 for next code. } void vcdFull(void*, VerilatedVcd* vcdp) { vcdp->fullBus(0x2, v1, 5); vcdp->fullBus(0x3, v2, 7); vcdp->fullBit(0x4, s1); vcdp->fullBus(0x5, ch, 2); vcdp->fullArray(0x6, &s2[0], 38); vcdp->fullTriBit(0x10, tri96[0] & 1, tri96__tri[0] & 1); vcdp->fullTriBus(0x12, tri96[0] & 0x1f, tri96__tri[0] & 0x1f, 5); vcdp->fullTriArray(0x16, tri96, tri96__tri, 96); vcdp->fullDouble(0x1c, doub); vcdp->fullArray(0x20, &quad96[0], 96); vcdp->fullTriQuad(0x24, tquad, tquad__tri, 64); } void vcdChange(void*, VerilatedVcd* vcdp) { vcdp->chgBus(0x2, v1, 5); vcdp->chgBus(0x3, v2, 7); vcdp->chgBit(0x4, s1); vcdp->chgBus(0x5, ch, 2); vcdp->chgArray(0x6, &s2[0], 38); vcdp->chgTriBit(0x10, tri96[0] & 1, tri96__tri[0] & 1); vcdp->chgTriBus(0x12, tri96[0] & 0x1f, tri96__tri[0] & 0x1f, 5); vcdp->chgTriArray(0x16, tri96, tri96__tri, 96); vcdp->chgDouble(0x1c, doub); vcdp->chgArray(0x20, &quad96[0], 96); vcdp->chgTriQuad(0x24, tquad, tquad__tri, 64); } // clang-format off void vcdTestMain(const char* filenamep) { v1 = v2 = s1 = 0; s2[0] = s2[1] = s2[2] = 0; tri96[2] = tri96[1] = tri96[0] = 0; tri96__tri[2] = tri96__tri[1] = tri96__tri[0] = ~0; quad96[1] = quad96[0] = 0; ch = 0; doub = 0; tquad = tquad__tri = 0; { VerilatedVcdC* vcdp = new VerilatedVcdC; vcdp->evcd(true); vcdp->spTrace()->addInitCb(&vcdInit, 0); vcdp->spTrace()->addFullCb(&vcdFull, 0); vcdp->spTrace()->addChgCb(&vcdChange, 0); vcdp->open(filenamep); // Dumping vcdp->dump(++timestamp); v1 = 0xfff; tri96[2] = 4; tri96[1] = 2; tri96[0] = 1; tri96__tri[2] = tri96__tri[1] = tri96__tri[0] = ~0; // Still tri quad96[1] = 0xffffffff; quad96[0] = 0; doub = 1.5; flo = 1.4f; vcdp->dump(++timestamp); v2 = 0x1; s2[1] = 2; tri96__tri[2] = tri96__tri[1] = tri96__tri[0] = 0; // enable w/o data change quad96[1] = 0; quad96[0] = ~0; doub = -1.66e13; flo = 0.123f; tquad = 0x00ff00ff00ff00ffULL; tquad__tri = 0x0000fffff0000ffffULL; vcdp->dump(++timestamp); ch = 2; tri96[2] = ~4; tri96[1] = ~2; tri96[0] = ~1; doub = -3.33e-13; vcdp->dump(++timestamp); vcdp->dump(++timestamp); # ifdef VERILATED_VCD_TEST_64BIT vluint64_t bytesPerDump = 15ULL; for (vluint64_t i = 0; i < ((1ULL << 32) / bytesPerDump); i++) { v1 = i; vcdp->dump(++timestamp); } # endif vcdp->close(); } } #endif // clang-format on //******************************************************************** // ;compile-command: "v4make test_regress/t/t_trace_c_api.pl" // // Local Variables: // End: verilator-4.038/include/verilated.v0000664000177100017500000000167213702133367017320 0ustar wsnyderwsnyder//************************************************************************* // // Code available from: https://verilator.org // //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= // // DESCRIPTION: Verilator: Include in verilog files to hide verilator defines `ifdef _VERILATED_V_ `else `define _VERILATED_V_ 1 // Hide verilator pragmas from other tools `ifdef VERILATOR `else `define coverage_block_off `endif // Hide file descriptor difference - deprecated - for older versions `define verilator_file_descriptor integer `endif // guard verilator-4.038/include/verilated_cov.h0000664000177100017500000001304713702133367020150 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Coverage analysis support /// //============================================================================= #ifndef _VERILATED_COV_H_ #define _VERILATED_COV_H_ 1 #include "verilatedos.h" #include #include #include //============================================================================= /// Conditionally compile coverage code // clang-format off #ifdef VM_COVERAGE # define VL_IF_COVER(stmts) \ do { stmts; } while (false) #else # define VL_IF_COVER(stmts) \ do { \ if (false) { stmts; } \ } while (false) #endif // clang-format on //============================================================================= /// Insert a item for coverage analysis. /// The first argument is a pointer to the count to be dumped. /// The remaining arguments occur in pairs: A string key, and a value. /// The value may be a string, or another type which will be auto-converted to a string. /// /// Some typical keys: /// filename File the recording occurs in. Defaults to __FILE__ /// lineno Line number the recording occurs in. Defaults to __LINE__ /// column Column number (or occurrence# for dup file/lines). Defaults to undef. /// hier Hierarchical name. Defaults to name() /// type Type of coverage. Defaults to "user" /// Other types are 'block', 'fsm', 'toggle'. /// comment Description of the coverage event. Should be set by the user. /// Comments for type==block: 'if', 'else', 'elsif', 'case' /// thresh Threshold to consider fully covered. /// If unspecified, downstream tools will determine it. /// /// Examples: /// /// vluint32_t m_cases[10]; /// constructor { /// for (int i=0; i<10; ++i) { m_cases[i]=0; } /// } /// for (int i=0; i<10; ++i) { /// VL_COVER_INSERT(&m_cases[i], "comment", "Coverage Case", "i", cvtToNumStr(i)); /// } #define VL_COVER_INSERT(countp, ...) \ VL_IF_COVER(VerilatedCov::_inserti(countp); VerilatedCov::_insertf(__FILE__, __LINE__); \ VerilatedCov::_insertp("hier", name(), __VA_ARGS__)) //============================================================================= /// Convert VL_COVER_INSERT value arguments to strings template std::string vlCovCvtToStr(const T& t) VL_PURE { std::ostringstream os; os << t; return os.str(); } //============================================================================= // VerilatedCov /// Verilator coverage global class //// /// Global class with methods affecting all coverage data. /// All public methods in this class are thread safe. class VerilatedCov { VL_UNCOPYABLE(VerilatedCov); public: // GLOBAL METHODS /// Return default filename static const char* defaultFilename() VL_PURE { return "coverage.dat"; } /// Write all coverage data to a file static void write(const char* filenamep = defaultFilename()) VL_MT_SAFE; /// Insert a coverage item /// We accept from 1-30 key/value pairs, all as strings. /// Call _insert1, followed by _insert2 and _insert3 /// Do not call directly; use VL_COVER_INSERT or higher level macros instead // _insert1: Remember item pointer with count. (Not const, as may add zeroing function) static void _inserti(vluint32_t* itemp) VL_MT_SAFE; static void _inserti(vluint64_t* itemp) VL_MT_SAFE; // _insert2: Set default filename and line number static void _insertf(const char* filename, int lineno) VL_MT_SAFE; // _insert3: Set parameters // We could have just the maximum argument version, but this compiles // much slower (nearly 2x) than having smaller versions also. However // there's not much more gain in having a version for each number of args. #define K(n) const char* key##n #define A(n) const char *key##n, const char *valp##n // Argument list #define D(n) const char *key##n = NULL, const char *valp##n = NULL // Argument list static void _insertp(D(0), D(1), D(2), D(3), D(4), D(5), D(6), D(7), D(8), D(9)); static void _insertp(A(0), A(1), A(2), A(3), A(4), A(5), A(6), A(7), A(8), A(9), A(10), D(11), D(12), D(13), D(14), D(15), D(16), D(17), D(18), D(19)); static void _insertp(A(0), A(1), A(2), A(3), A(4), A(5), A(6), A(7), A(8), A(9), A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19), A(20), D(21), D(22), D(23), D(24), D(25), D(26), D(27), D(28), D(29)); // Backward compatibility for Verilator static void _insertp(A(0), A(1), K(2), int val2, K(3), int val3, K(4), const std::string& val4, A(5), A(6), A(7)); #undef K #undef A #undef D /// Clear coverage points (and call delete on all items) static void clear() VL_MT_SAFE; /// Clear items not matching the provided string static void clearNonMatch(const char* matchp) VL_MT_SAFE; /// Zero coverage points static void zero() VL_MT_SAFE; }; #endif // Guard verilator-4.038/include/verilated_trace_imp.cpp0000664000177100017500000005661713702133367021671 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Implementation of tracing functionality common to all trace formats /// //============================================================================= // SPDIFF_OFF // clang-format off #ifndef VL_DERIVED_T # error "This file should be included in trace format implementations" #endif #include "verilated_intrinsics.h" #include "verilated_trace.h" #if 0 # include # define VL_TRACE_THREAD_DEBUG(msg) std::cout << "TRACE THREAD: " << msg << std::endl #else # define VL_TRACE_THREAD_DEBUG(msg) #endif // clang-format on //============================================================================= // Static utility functions static double timescaleToDouble(const char* unitp) { char* endp = NULL; double value = strtod(unitp, &endp); // On error so we allow just "ns" to return 1e-9. if (value == 0.0 && endp == unitp) value = 1; unitp = endp; for (; *unitp && isspace(*unitp); unitp++) {} switch (*unitp) { case 's': value *= 1e1; break; case 'm': value *= 1e-3; break; case 'u': value *= 1e-6; break; case 'n': value *= 1e-9; break; case 'p': value *= 1e-12; break; case 'f': value *= 1e-15; break; case 'a': value *= 1e-18; break; } return value; } static std::string doubleToTimescale(double value) { const char* suffixp = "s"; // clang-format off if (value >= 1e0) { suffixp = "s"; value *= 1e0; } else if (value >= 1e-3 ) { suffixp = "ms"; value *= 1e3; } else if (value >= 1e-6 ) { suffixp = "us"; value *= 1e6; } else if (value >= 1e-9 ) { suffixp = "ns"; value *= 1e9; } else if (value >= 1e-12) { suffixp = "ps"; value *= 1e12; } else if (value >= 1e-15) { suffixp = "fs"; value *= 1e15; } else if (value >= 1e-18) { suffixp = "as"; value *= 1e18; } // clang-format on char valuestr[100]; sprintf(valuestr, "%3.0f%s", value, suffixp); return valuestr; // Gets converted to string, so no ref to stack } #ifdef VL_TRACE_THREADED //========================================================================= // Buffer management template <> vluint32_t* VerilatedTrace::getTraceBuffer() { vluint32_t* bufferp; // Some jitter is expected, so some number of alternative trace buffers are // required, but don't allocate more than 8 buffers. if (m_numTraceBuffers < 8) { // Allocate a new buffer if none is available if (!m_buffersFromWorker.tryGet(bufferp)) { ++m_numTraceBuffers; // Note: over allocate a bit so pointer comparison is well defined // if we overflow only by a small amount bufferp = new vluint32_t[m_traceBufferSize + 16]; } } else { // Block until a buffer becomes available bufferp = m_buffersFromWorker.get(); } return bufferp; } template <> void VerilatedTrace::waitForBuffer(const vluint32_t* buffp) { // Slow path code only called on flush/shutdown, so use a simple algorithm. // Collect buffers from worker and stash them until we get the one we want. std::deque stash; do { stash.push_back(m_buffersFromWorker.get()); } while (stash.back() != buffp); // Now put them back in the queue, in the original order. while (!stash.empty()) { m_buffersFromWorker.put_front(stash.back()); stash.pop_back(); } } //========================================================================= // Worker thread template <> void VerilatedTrace::workerThreadMain() { bool shutdown = false; do { vluint32_t* const bufferp = m_buffersToWorker.get(); VL_TRACE_THREAD_DEBUG(""); VL_TRACE_THREAD_DEBUG("Got buffer: " << bufferp); const vluint32_t* readp = bufferp; while (true) { const vluint32_t cmd = readp[0]; const vluint32_t top = cmd >> 4; // Always set this up, as it is almost always needed vluint32_t* const oldp = m_sigs_oldvalp + readp[1]; // Note this increment needs to be undone on commands which do not // actually contain a code, but those are the rare cases. readp += 2; switch (cmd & 0xF) { //=== // CHG_* commands case VerilatedTraceCommand::CHG_BIT_0: VL_TRACE_THREAD_DEBUG("Command CHG_BIT_0 " << top); chgBitImpl(oldp, 0); continue; case VerilatedTraceCommand::CHG_BIT_1: VL_TRACE_THREAD_DEBUG("Command CHG_BIT_1 " << top); chgBitImpl(oldp, 1); continue; case VerilatedTraceCommand::CHG_CDATA: VL_TRACE_THREAD_DEBUG("Command CHG_CDATA " << top); // Bits stored in bottom byte of command chgCDataImpl(oldp, *readp, top); readp += 1; continue; case VerilatedTraceCommand::CHG_SDATA: VL_TRACE_THREAD_DEBUG("Command CHG_SDATA " << top); // Bits stored in bottom byte of command chgSDataImpl(oldp, *readp, top); readp += 1; continue; case VerilatedTraceCommand::CHG_IDATA: VL_TRACE_THREAD_DEBUG("Command CHG_IDATA " << top); // Bits stored in bottom byte of command chgIDataImpl(oldp, *readp, top); readp += 1; continue; case VerilatedTraceCommand::CHG_QDATA: VL_TRACE_THREAD_DEBUG("Command CHG_QDATA " << top); // Bits stored in bottom byte of command chgQDataImpl(oldp, *reinterpret_cast(readp), top); readp += 2; continue; case VerilatedTraceCommand::CHG_WDATA: VL_TRACE_THREAD_DEBUG("Command CHG_WDATA " << top); chgWDataImpl(oldp, readp, top); readp += VL_WORDS_I(top); continue; case VerilatedTraceCommand::CHG_DOUBLE: VL_TRACE_THREAD_DEBUG("Command CHG_DOUBLE " << top); chgDoubleImpl(oldp, *reinterpret_cast(readp)); readp += 2; continue; //=== // Rare commands case VerilatedTraceCommand::TIME_CHANGE: VL_TRACE_THREAD_DEBUG("Command TIME_CHANGE " << top); readp -= 1; // No code in this command, undo increment emitTimeChange(*reinterpret_cast(readp)); readp += 2; continue; //=== // Commands ending this buffer case VerilatedTraceCommand::END: VL_TRACE_THREAD_DEBUG("Command END"); break; case VerilatedTraceCommand::SHUTDOWN: VL_TRACE_THREAD_DEBUG("Command SHUTDOWN"); shutdown = true; break; //=== // Unknown command default: { // LCOV_EXCL_START VL_TRACE_THREAD_DEBUG("Command UNKNOWN"); VL_PRINTF_MT("Trace command: 0x%08x\n", cmd); VL_FATAL_MT(__FILE__, __LINE__, "", "Unknown trace command"); break; } // LCOV_EXCL_STOP } // The above switch will execute 'continue' when necessary, // so if we ever reach here, we are done with the buffer. break; } VL_TRACE_THREAD_DEBUG("Returning buffer"); // Return buffer m_buffersFromWorker.put(bufferp); } while (VL_LIKELY(!shutdown)); } template <> void VerilatedTrace::shutdownWorker() { // If the worker thread is not running, done.. if (!m_workerThread) return; // Hand an buffer with a shutdown command to the worker thread vluint32_t* const bufferp = getTraceBuffer(); bufferp[0] = VerilatedTraceCommand::SHUTDOWN; m_buffersToWorker.put(bufferp); // Wait for it to return waitForBuffer(bufferp); // Join the thread and delete it m_workerThread->join(); m_workerThread.reset(nullptr); } #endif //============================================================================= // Life cycle template <> void VerilatedTrace::close() { #ifdef VL_TRACE_THREADED shutdownWorker(); while (m_numTraceBuffers) { delete[] m_buffersFromWorker.get(); m_numTraceBuffers--; } #endif } template <> void VerilatedTrace::flush() { #ifdef VL_TRACE_THREADED // Hand an empty buffer to the worker thread vluint32_t* const bufferp = getTraceBuffer(); *bufferp = VerilatedTraceCommand::END; m_buffersToWorker.put(bufferp); // Wait for it to be returned. As the processing is in-order, // this ensures all previous buffers have been processed. waitForBuffer(bufferp); #endif } //============================================================================= // Callbacks to run on global events template <> void VerilatedTrace::onFlush(void* selfp) { // Note this calls 'flush' on the derived class reinterpret_cast(selfp)->flush(); } template <> void VerilatedTrace::onExit(void* selfp) { // Note this calls 'close' on the derived class reinterpret_cast(selfp)->close(); } //============================================================================= // VerilatedTrace template <> VerilatedTrace::VerilatedTrace() : m_sigs_oldvalp(NULL) , m_timeLastDump(0) , m_fullDump(true) , m_nextCode(0) , m_numSignals(0) , m_maxBits(0) , m_scopeEscape('.') , m_timeRes(1e-9) , m_timeUnit(1e-9) #ifdef VL_TRACE_THREADED , m_numTraceBuffers(0) #endif { set_time_unit(Verilated::timeunitString()); set_time_resolution(Verilated::timeprecisionString()); } template <> VerilatedTrace::~VerilatedTrace() { if (m_sigs_oldvalp) VL_DO_CLEAR(delete[] m_sigs_oldvalp, m_sigs_oldvalp = NULL); Verilated::removeFlushCb(VerilatedTrace::onFlush, this); Verilated::removeExitCb(VerilatedTrace::onExit, this); #ifdef VL_TRACE_THREADED close(); #endif } //========================================================================= // Internals available to format specific implementations template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { m_assertOne.check(); // Note: It is possible to re-open a trace file (VCD in particular), // so we must reset the next code here, but it must have the same number // of codes on re-open const vluint32_t expectedCodes = nextCode(); m_nextCode = 1; m_numSignals = 0; m_maxBits = 0; // Call all initialize callbacks, which will: // - Call decl* for each signal // - Store the base code for (vluint32_t i = 0; i < m_initCbs.size(); ++i) { const CallbackRecord& cbr = m_initCbs[i]; cbr.m_initCb(cbr.m_userp, self(), nextCode()); } if (expectedCodes && nextCode() != expectedCodes) { VL_FATAL_MT(__FILE__, __LINE__, "", "Reopening trace file with different number of signals"); } // Now that we know the number of codes, allocate space for the buffer // holding previous signal values. if (!m_sigs_oldvalp) m_sigs_oldvalp = new vluint32_t[nextCode()]; // Set callback so flush/abort will flush this file Verilated::addFlushCb(VerilatedTrace::onFlush, this); Verilated::addExitCb(VerilatedTrace::onExit, this); #ifdef VL_TRACE_THREADED // Compute trace buffer size. we need to be able to store a new value for // each signal, which is 'nextCode()' entries after the init callbacks // above have been run, plus up to 2 more words of metadata per signal, // plus fixed overhead of 1 for a termination flag and 3 for a time stamp // update. m_traceBufferSize = nextCode() + numSignals() * 2 + 4; // Start the worker thread m_workerThread.reset(new std::thread(&VerilatedTrace::workerThreadMain, this)); #endif } template <> void VerilatedTrace::declCode(vluint32_t code, vluint32_t bits, bool tri) { if (!code) { VL_FATAL_MT(__FILE__, __LINE__, "", "Internal: internal trace problem, code 0 is illegal"); } // Note: The tri-state flag is not used by Verilator, but is here for // compatibility with some foreign code. int codesNeeded = VL_WORDS_I(bits); if (tri) codesNeeded *= 2; m_nextCode = std::max(m_nextCode, code + codesNeeded); ++m_numSignals; m_maxBits = std::max(m_maxBits, bits); } //========================================================================= // Internals available to format specific implementations template <> std::string VerilatedTrace::timeResStr() const { return doubleToTimescale(m_timeRes); } template <> std::string VerilatedTrace::timeUnitStr() const { return doubleToTimescale(m_timeUnit); } //========================================================================= // External interface to client code template <> void VerilatedTrace::set_time_unit(const char* unitp) { m_timeUnit = timescaleToDouble(unitp); } template <> void VerilatedTrace::set_time_unit(const std::string& unit) { set_time_unit(unit.c_str()); } template <> void VerilatedTrace::set_time_resolution(const char* unitp) { m_timeRes = timescaleToDouble(unitp); } template <> void VerilatedTrace::set_time_resolution(const std::string& unit) { set_time_resolution(unit.c_str()); } template <> void VerilatedTrace::dump(vluint64_t timeui) { m_assertOne.check(); if (VL_UNCOVERABLE(m_timeLastDump && timeui <= m_timeLastDump)) { // LCOV_EXCL_START VL_PRINTF_MT("%%Warning: previous dump at t=%" VL_PRI64 "u, requesting t=%" VL_PRI64 "u, dump call ignored\n", m_timeLastDump, timeui); return; } // LCOV_EXCL_STOP m_timeLastDump = timeui; Verilated::quiesce(); // Call hook for format specific behaviour if (VL_UNLIKELY(m_fullDump)) { if (!preFullDump()) return; } else { if (!preChangeDump()) return; } #ifdef VL_TRACE_THREADED // Currently only incremental dumps run on the worker thread vluint32_t* bufferp = nullptr; if (VL_LIKELY(!m_fullDump)) { // Get the trace buffer we are about to fill bufferp = getTraceBuffer(); m_traceBufferWritep = bufferp; m_traceBufferEndp = bufferp + m_traceBufferSize; // Tell worker to update time point m_traceBufferWritep[0] = VerilatedTraceCommand::TIME_CHANGE; *reinterpret_cast(m_traceBufferWritep + 1) = timeui; m_traceBufferWritep += 3; } else { // Update time point flush(); emitTimeChange(timeui); } #else // Update time point emitTimeChange(timeui); #endif // Run the callbacks if (VL_UNLIKELY(m_fullDump)) { m_fullDump = false; // No more need for next dump to be full for (vluint32_t i = 0; i < m_fullCbs.size(); ++i) { const CallbackRecord& cbr = m_fullCbs[i]; cbr.m_dumpCb(cbr.m_userp, self()); } } else { for (vluint32_t i = 0; i < m_chgCbs.size(); ++i) { const CallbackRecord& cbr = m_chgCbs[i]; cbr.m_dumpCb(cbr.m_userp, self()); } } for (vluint32_t i = 0; i < m_cleanupCbs.size(); ++i) { const CallbackRecord& cbr = m_cleanupCbs[i]; cbr.m_dumpCb(cbr.m_userp, self()); } #ifdef VL_TRACE_THREADED if (VL_LIKELY(bufferp)) { // Mark end of the trace buffer we just filled *m_traceBufferWritep++ = VerilatedTraceCommand::END; // Assert no buffer overflow assert(m_traceBufferWritep - bufferp <= m_traceBufferSize); // Pass it to the worker thread m_buffersToWorker.put(bufferp); } #endif } //============================================================================= // Non-hot path internal interface to Verilator generated code template <> void VerilatedTrace::addCallbackRecord(std::vector& cbVec, CallbackRecord& cbRec) { m_assertOne.check(); if (VL_UNCOVERABLE(timeLastDump() != 0)) { // LCOV_EXCL_START std::string msg = (std::string("Internal: ") + __FILE__ + "::" + __FUNCTION__ + " called with already open file"); VL_FATAL_MT(__FILE__, __LINE__, "", msg.c_str()); } // LCOV_EXCL_STOP cbVec.push_back(cbRec); } template <> void VerilatedTrace::addInitCb(initCb_t cb, void* userp) { CallbackRecord cbr(cb, userp); addCallbackRecord(m_initCbs, cbr); } template <> void VerilatedTrace::addFullCb(dumpCb_t cb, void* userp) { CallbackRecord cbr(cb, userp); addCallbackRecord(m_fullCbs, cbr); } template <> void VerilatedTrace::addChgCb(dumpCb_t cb, void* userp) { CallbackRecord cbr(cb, userp); addCallbackRecord(m_chgCbs, cbr); } template <> void VerilatedTrace::addCleanupCb(dumpCb_t cb, void* userp) { CallbackRecord cbr(cb, userp); addCallbackRecord(m_cleanupCbs, cbr); } //========================================================================= // Hot path internal interface to Verilator generated code // These functions must write the new value back into the old value store, // and subsequently call the format specific emit* implementations. Note // that this file must be included in the format specific implementation, so // the emit* functions can be inlined for performance. template <> void VerilatedTrace::fullBit(vluint32_t* oldp, CData newval) { *oldp = newval; self()->emitBit(oldp - m_sigs_oldvalp, newval); } template <> void VerilatedTrace::fullCData(vluint32_t* oldp, CData newval, int bits) { *oldp = newval; self()->emitCData(oldp - m_sigs_oldvalp, newval, bits); } template <> void VerilatedTrace::fullSData(vluint32_t* oldp, SData newval, int bits) { *oldp = newval; self()->emitSData(oldp - m_sigs_oldvalp, newval, bits); } template <> void VerilatedTrace::fullIData(vluint32_t* oldp, IData newval, int bits) { *oldp = newval; self()->emitIData(oldp - m_sigs_oldvalp, newval, bits); } template <> void VerilatedTrace::fullQData(vluint32_t* oldp, QData newval, int bits) { *reinterpret_cast(oldp) = newval; self()->emitQData(oldp - m_sigs_oldvalp, newval, bits); } template <> void VerilatedTrace::fullWData(vluint32_t* oldp, const WData* newvalp, int bits) { for (int i = 0; i < VL_WORDS_I(bits); ++i) oldp[i] = newvalp[i]; self()->emitWData(oldp - m_sigs_oldvalp, newvalp, bits); } template <> void VerilatedTrace::fullDouble(vluint32_t* oldp, double newval) { // cppcheck-suppress invalidPointerCast *reinterpret_cast(oldp) = newval; self()->emitDouble(oldp - m_sigs_oldvalp, newval); } //========================================================================= // Primitives converting binary values to strings... // All of these take a destination pointer where the string will be emitted, // and a value to convert. There are a couple of variants for efficiency. inline static void cvtCDataToStr(char* dstp, CData value) { #ifdef VL_HAVE_SSE2 // Similar to cvtSDataToStr but only the bottom 8 byte lanes are used const __m128i a = _mm_cvtsi32_si128(value); const __m128i b = _mm_unpacklo_epi8(a, a); const __m128i c = _mm_shufflelo_epi16(b, 0); const __m128i m = _mm_set1_epi64x(0x0102040810204080); const __m128i d = _mm_cmpeq_epi8(_mm_and_si128(c, m), m); const __m128i result = _mm_sub_epi8(_mm_set1_epi8('0'), d); _mm_storel_epi64(reinterpret_cast<__m128i*>(dstp), result); #else dstp[0] = '0' | static_cast((value >> 7) & 1); dstp[1] = '0' | static_cast((value >> 6) & 1); dstp[2] = '0' | static_cast((value >> 5) & 1); dstp[3] = '0' | static_cast((value >> 4) & 1); dstp[4] = '0' | static_cast((value >> 3) & 1); dstp[5] = '0' | static_cast((value >> 2) & 1); dstp[6] = '0' | static_cast((value >> 1) & 1); dstp[7] = '0' | static_cast(value & 1); #endif } inline static void cvtSDataToStr(char* dstp, SData value) { #ifdef VL_HAVE_SSE2 // We want each bit in the 16-bit input value to end up in a byte lane // within the 128-bit XMM register. Note that x86 is little-endian and we // want the MSB of the input at the low address, so we will bit-reverse // at the same time. // Put value in bottom of 128-bit register a[15:0] = value const __m128i a = _mm_cvtsi32_si128(value); // Interleave bytes with themselves // b[15: 0] = {2{a[ 7:0]}} == {2{value[ 7:0]}} // b[31:16] = {2{a[15:8]}} == {2{value[15:8]}} const __m128i b = _mm_unpacklo_epi8(a, a); // Shuffle bottom 64 bits, note swapping high bytes with low bytes // c[31: 0] = {2{b[31:16]}} == {4{value[15:8}} // c[63:32] = {2{b[15: 0]}} == {4{value[ 7:0}} const __m128i c = _mm_shufflelo_epi16(b, 0x05); // Shuffle whole register // d[ 63: 0] = {2{c[31: 0]}} == {8{value[15:8}} // d[126:54] = {2{c[63:32]}} == {8{value[ 7:0}} const __m128i d = _mm_shuffle_epi32(c, 0x50); // Test each bit within the bytes, this sets each byte lane to 0 // if the bit for that lane is 0 and to 0xff if the bit is 1. const __m128i m = _mm_set1_epi64x(0x0102040810204080); const __m128i e = _mm_cmpeq_epi8(_mm_and_si128(d, m), m); // Convert to ASCII by subtracting the masks from ASCII '0': // '0' - 0 is '0', '0' - -1 is '1' const __m128i result = _mm_sub_epi8(_mm_set1_epi8('0'), e); // Store the 16 characters to the un-aligned buffer _mm_storeu_si128(reinterpret_cast<__m128i*>(dstp), result); #else cvtCDataToStr(dstp, value >> 8); cvtCDataToStr(dstp + 8, value); #endif } inline static void cvtIDataToStr(char* dstp, IData value) { #ifdef VL_HAVE_AVX2 // Similar to cvtSDataToStr but the bottom 16-bits are processed in the // top half of the YMM registerss const __m256i a = _mm256_insert_epi32(_mm256_undefined_si256(), value, 0); const __m256i b = _mm256_permute4x64_epi64(a, 0); const __m256i s = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3); const __m256i c = _mm256_shuffle_epi8(b, s); const __m256i m = _mm256_set1_epi64x(0x0102040810204080); const __m256i d = _mm256_cmpeq_epi8(_mm256_and_si256(c, m), m); const __m256i result = _mm256_sub_epi8(_mm256_set1_epi8('0'), d); _mm256_storeu_si256(reinterpret_cast<__m256i*>(dstp), result); #else cvtSDataToStr(dstp, value >> 16); cvtSDataToStr(dstp + 16, value); #endif } inline static void cvtQDataToStr(char* dstp, QData value) { cvtIDataToStr(dstp, value >> 32); cvtIDataToStr(dstp + 32, value); } #define cvtEDataToStr cvtIDataToStr verilator-4.038/include/verilated.mk.in0000664000177100017500000001726213702133367020071 0ustar wsnyderwsnyder# -*- Makefile -*- ###################################################################### # DESCRIPTION: Makefile commands for all verilated target files # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### PERL = @PERL@ CXX = @CXX@ LINK = @CXX@ AR = ar RANLIB = ranlib OBJCACHE ?= @OBJCACHE@ CFG_WITH_CCWARN = @CFG_WITH_CCWARN@ CFG_WITH_LONGTESTS = @CFG_WITH_LONGTESTS@ # Select newest language CFG_CXXFLAGS_STD_NEWEST = @CFG_CXXFLAGS_STD_NEWEST@ # Select oldest language (for Verilator internal testing only) CFG_CXXFLAGS_STD_OLDEST = @CFG_CXXFLAGS_STD_OLDEST@ # Compiler flags to use to turn off unused and generated code warnings, such as -Wno-div-by-zero CFG_CXXFLAGS_NO_UNUSED = @CFG_CXXFLAGS_NO_UNUSED@ # Compiler flags that turn on extra warnings CFG_CXXFLAGS_WEXTRA = @CFG_CXXFLAGS_WEXTRA@ # Linker libraries for multithreading CFG_LDLIBS_THREADS = @CFG_LDLIBS_THREADS@ ###################################################################### # Programs VERILATOR_COVERAGE = $(PERL) $(VERILATOR_ROOT)/bin/verilator_coverage VERILATOR_INCLUDER = $(PERL) $(VERILATOR_ROOT)/bin/verilator_includer ###################################################################### # Make checks ifneq ($(words $(CURDIR)),1) $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)') endif ###################################################################### # C Preprocessor flags # Add -MMD -MP if you're using a recent version of GCC. VK_CPPFLAGS_ALWAYS += \ -MMD \ -I$(VERILATOR_ROOT)/include \ -I$(VERILATOR_ROOT)/include/vltstd \ -DVM_COVERAGE=$(VM_COVERAGE) \ -DVM_SC=$(VM_SC) \ -DVM_TRACE=$(VM_TRACE) \ $(CFG_CXXFLAGS_NO_UNUSED) \ ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users VK_CPPFLAGS_WALL += -Wall $(CFG_CXXFLAGS_WEXTRA) -Werror endif CPPFLAGS += -I. $(VK_CPPFLAGS_WALL) $(VK_CPPFLAGS_ALWAYS) VPATH += .. VPATH += $(VERILATOR_ROOT)/include VPATH += $(VERILATOR_ROOT)/include/vltstd #OPT = -ggdb -DPRINTINITSTR -DDETECTCHANGE #OPT = -ggdb -DPRINTINITSTR CPPFLAGS += $(OPT) CPPFLAGS += $(M32) LDFLAGS += $(M32) # Allow upper level user makefiles to specify flags they want. # These aren't ever set by Verilator, so users are free to override them. CPPFLAGS += $(USER_CPPFLAGS) LDFLAGS += $(USER_LDFLAGS) LDLIBS += $(USER_LDLIBS) # Add flags from -CFLAGS and -LDFLAGS on Verilator command line CPPFLAGS += $(VM_USER_CFLAGS) LDFLAGS += $(VM_USER_LDFLAGS) LDLIBS += $(VM_USER_LDLIBS) ###################################################################### # Optimization control. # See also the BENCHMARKING & OPTIMIZATION section of the manual. # Optimization flags for non performance-critical/rarely executed code. # No optimization by default, which improves compilation speed. OPT_SLOW = # Optimization for performance critical/hot code. Most time is spent in these # routines. Optimizing by default for improved execution speed. OPT_FAST = -Os # Optimization applied to the common run-time library used by verilated models. # For compatibility this is called OPT_GLOBAL even though it only applies to # files in the run-time library. Normally there should be no need for the user # to change this as the library is small, but can have significant speed impact. OPT_GLOBAL = -Os ####################################################################### ##### SystemC builds ifeq ($(VM_SC),1) CPPFLAGS += $(SYSTEMC_CXX_FLAGS) $(addprefix -I, $(SYSTEMC_INCLUDE)) LDFLAGS += $(SYSTEMC_CXX_FLAGS) $(addprefix -L, $(SYSTEMC_LIBDIR)) SC_LIBS = -lsystemc ifneq ($(wildcard $(SYSTEMC_LIBDIR)/*numeric_bit*),) # Systemc 1.2.1beta SC_LIBS += -lnumeric_bit -lqt endif endif ####################################################################### ##### Threaded builds ifneq ($(VM_C11),0) ifneq ($(VM_C11),) VK_C11=1 endif endif ifneq ($(VM_THREADS),0) ifneq ($(VM_THREADS),) CPPFLAGS += -DVL_THREADED VK_C11=1 VK_LIBS_THREADED=1 endif endif ifneq ($(VM_TRACE_THREADS),0) ifneq ($(VM_TRACE_THREADS),) ifeq ($(findstring -DVL_THREADED,$(CPPFLAGS)),) $(error VM_TRACE_THREADS requires VM_THREADS) endif CPPFLAGS += -DVL_TRACE_THREADED VK_C11=1 VK_LIBS_THREADED=1 endif endif ifneq ($(VM_TRACE_FST_WRITER_THREAD),0) ifneq ($(VM_TRACE_FST_WRITER_THREAD),) CPPFLAGS += -DVL_TRACE_FST_WRITER_THREAD VK_C11=1 VK_LIBS_THREADED=1 endif endif ifneq ($(VK_C11),0) ifneq ($(VK_C11),) # Need C++11 at least, so always default to newest CPPFLAGS += $(CFG_CXXFLAGS_STD_NEWEST) endif endif ifneq ($(VK_LIBS_THREADED),0) ifneq ($(VK_LIBS_THREADED),) LDLIBS += $(CFG_LDLIBS_THREADS) endif endif ####################################################################### ### Aggregates VM_FAST += $(VM_CLASSES_FAST) $(VM_SUPPORT_FAST) VM_SLOW += $(VM_CLASSES_SLOW) $(VM_SUPPORT_SLOW) ####################################################################### ### Overall Objects Linking VK_FAST_OBJS = $(addsuffix .o, $(VM_FAST)) VK_SLOW_OBJS = $(addsuffix .o, $(VM_SLOW)) VK_USER_OBJS = $(addsuffix .o, $(VM_USER_CLASSES)) # Note VM_GLOBAL_FAST and VM_GLOBAL_SLOW holds the files required from the # run-time library. In practice everything is actually in VM_GLOBAL_FAST, # but keeping the distinction for compatibility for now. VK_GLOBAL_OBJS = $(addsuffix .o, $(VM_GLOBAL_FAST) $(VM_GLOBAL_SLOW)) ifneq ($(VM_PARALLEL_BUILDS),1) # Fast build for small designs: All .cpp files in one fell swoop. This # saves total compute, but can be slower if only a little changes. It is # also a lot slower for medium to large designs when the speed of the C # compiler dominates, which in this mode is not parallelizable. VK_OBJS += $(VM_PREFIX)__ALL.o $(VM_PREFIX)__ALL.cpp: $(addsuffix .cpp, $(VM_FAST) $(VM_SLOW)) $(VERILATOR_INCLUDER) -DVL_INCLUDE_OPT=include $^ > $@ all_cpp: $(VM_PREFIX)__ALL.cpp else # Parallel build: Each .cpp file by itself. This can be somewhat slower for # very small designs and examples, but is a lot faster for large designs. VK_OBJS += $(VK_FAST_OBJS) $(VK_SLOW_OBJS) endif $(VM_PREFIX)__ALL.a: $(VK_OBJS) $(AR) -cr $@ $^ $(RANLIB) $@ ###################################################################### ### Compile rules ifneq ($(VM_DEFAULT_RULES),0) # Anything not in $(VK_SLOW_OBJS) or $(VK_GLOBAL_OBJS), including verilated.o # and user files passed on the Verilator command line use this rule. %.o: %.cpp $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< $(VK_SLOW_OBJS): %.o: %.cpp $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< $(VK_GLOBAL_OBJS): %.o: %.cpp $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_GLOBAL) -c -o $@ $< endif #Default rule embedded in make: #.cpp.o: # $(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $@ $< ###################################################################### ### Debugging debug-make:: @echo @echo CXXFLAGS: $(CXXFLAGS) @echo CPPFLAGS: $(CPPFLAGS) @echo OPT_FAST: $(OPT_FAST) @echo OPT_SLOW: $(OPT_SLOW) @echo VM_PREFIX: $(VM_PREFIX) @echo VM_PARALLEL_BUILDS: $(VM_PARALLEL_BUILDS) @echo VM_CLASSES_FAST: $(VM_CLASSES_FAST) @echo VM_CLASSES_SLOW: $(VM_CLASSES_SLOW) @echo VM_SUPPORT_FAST: $(VM_SUPPORT_FAST) @echo VM_SUPPORT_SLOW: $(VM_SUPPORT_SLOW) @echo VM_GLOBAL_FAST: $(VM_GLOBAL_FAST) @echo VM_GLOBAL_SLOW: $(VM_GLOBAL_SLOW) @echo VK_OBJS: $(VK_OBJS) @echo ###################################################################### ### Detect out of date files and rebuild. DEPS := $(wildcard *.d) ifneq ($(DEPS),) include $(DEPS) endif verilator-4.038/include/verilated_config.h.in0000664000177100017500000000161613702133367021232 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: Auto version information include for all Verilated C files /// /// Code available from: https://verilator.org /// //************************************************************************* ///**** Product and Version name // Autoconf substitutes this with the strings from AC_INIT. #define VERILATOR_PRODUCT "@PACKAGE_NAME@" #define VERILATOR_VERSION "@PACKAGE_VERSION@" verilator-4.038/include/verilated_vpi.cpp0000664000177100017500000023232113702216165020506 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// /// \file /// \brief Verilator: VPI implementation code /// /// This file must be compiled and linked against all objects /// created from Verilator or called by Verilator that use the VPI. /// /// Use "verilator --vpi" to add this to the Makefile for the linker. /// /// Code available from: https://verilator.org /// //========================================================================= #define _VERILATED_VPI_CPP_ #include "verilated.h" #include "verilated_vpi.h" #include "verilated_imp.h" #include #include #include //====================================================================== // Internal constants #define VL_DEBUG_IF_PLI VL_DEBUG_IF #define VL_VPI_LINE_SIZE 8192 //====================================================================== // Internal macros #define _VL_VPI_INTERNAL VerilatedVpiImp::error_info()->setMessage(vpiInternal)->setMessage #define _VL_VPI_SYSTEM VerilatedVpiImp::error_info()->setMessage(vpiSystem)->setMessage #define _VL_VPI_ERROR VerilatedVpiImp::error_info()->setMessage(vpiError)->setMessage #define _VL_VPI_WARNING VerilatedVpiImp::error_info()->setMessage(vpiWarning)->setMessage #define _VL_VPI_NOTICE VerilatedVpiImp::error_info()->setMessage(vpiNotice)->setMessage #define _VL_VPI_ERROR_RESET VerilatedVpiImp::error_info()->resetError // Not supported yet #define _VL_VPI_UNIMP() \ (_VL_VPI_ERROR(__FILE__, __LINE__, Verilated::catName("Unsupported VPI function: ", VL_FUNC))) //====================================================================== // Implementation // Base VPI handled object class VerilatedVpio { // MEM MANGLEMENT static VL_THREAD_LOCAL vluint8_t* t_freeHead; public: // CONSTRUCTORS VerilatedVpio() {} virtual ~VerilatedVpio() {} inline static void* operator new(size_t size) VL_MT_SAFE { // We new and delete tons of vpi structures, so keep them around // To simplify our free list, we use a size large enough for all derived types // We reserve word zero for the next pointer, as that's safer in case a // dangling reference to the original remains around. static const size_t chunk = 96; if (VL_UNCOVERABLE(size > chunk)) VL_FATAL_MT(__FILE__, __LINE__, "", "increase chunk"); if (VL_LIKELY(t_freeHead)) { vluint8_t* newp = t_freeHead; t_freeHead = *(reinterpret_cast(newp)); return newp + 8; } // +8: 8 bytes for next vluint8_t* newp = reinterpret_cast(::operator new(chunk + 8)); return newp + 8; } inline static void operator delete(void* obj, size_t /*size*/)VL_MT_SAFE { vluint8_t* oldp = (static_cast(obj)) - 8; *(reinterpret_cast(oldp)) = t_freeHead; t_freeHead = oldp; } // MEMBERS static inline VerilatedVpio* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } inline vpiHandle castVpiHandle() { return reinterpret_cast(this); } // ACCESSORS virtual const char* name() const { return ""; } virtual const char* fullname() const { return ""; } virtual const char* defname() const { return ""; } virtual vluint32_t type() const { return 0; } virtual vluint32_t size() const { return 0; } virtual const VerilatedRange* rangep() const { return NULL; } virtual vpiHandle dovpi_scan() { return 0; } }; typedef PLI_INT32 (*VerilatedPliCb)(struct t_cb_data*); class VerilatedVpioCb : public VerilatedVpio { t_cb_data m_cbData; s_vpi_value m_value; QData m_time; public: // cppcheck-suppress uninitVar // m_value VerilatedVpioCb(const t_cb_data* cbDatap, QData time) : m_cbData(*cbDatap) , m_time(time) { m_value.format = cbDatap->value ? cbDatap->value->format : vpiSuppressVal; m_cbData.value = &m_value; } virtual ~VerilatedVpioCb() {} static inline VerilatedVpioCb* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiCallback; } vluint32_t reason() const { return m_cbData.reason; } VerilatedPliCb cb_rtnp() const { return m_cbData.cb_rtn; } t_cb_data* cb_datap() { return &(m_cbData); } QData time() const { return m_time; } }; class VerilatedVpioConst : public VerilatedVpio { vlsint32_t m_num; public: explicit VerilatedVpioConst(vlsint32_t num) : m_num(num) {} virtual ~VerilatedVpioConst() {} static inline VerilatedVpioConst* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiConstant; } vlsint32_t num() const { return m_num; } }; class VerilatedVpioParam : public VerilatedVpio { const VerilatedVar* m_varp; const VerilatedScope* m_scopep; public: VerilatedVpioParam(const VerilatedVar* varp, const VerilatedScope* scopep) : m_varp(varp) , m_scopep(scopep) {} virtual ~VerilatedVpioParam() {} static inline VerilatedVpioParam* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiParameter; } const VerilatedVar* varp() const { return m_varp; } void* varDatap() const { return m_varp->datap(); } const VerilatedScope* scopep() const { return m_scopep; } virtual const char* name() const { return m_varp->name(); } virtual const char* fullname() const { static VL_THREAD_LOCAL std::string out; out = std::string(m_scopep->name()) + "." + name(); return out.c_str(); } }; class VerilatedVpioRange : public VerilatedVpio { const VerilatedRange* m_range; vlsint32_t m_iteration; public: explicit VerilatedVpioRange(const VerilatedRange* range) : m_range(range) , m_iteration(0) {} virtual ~VerilatedVpioRange() {} static inline VerilatedVpioRange* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiRange; } virtual vluint32_t size() const { return m_range->elements(); } virtual const VerilatedRange* rangep() const { return m_range; } int iteration() const { return m_iteration; } void iterationInc() { ++m_iteration; } virtual vpiHandle dovpi_scan() { if (!iteration()) { VerilatedVpioRange* nextp = new VerilatedVpioRange(*this); nextp->iterationInc(); return ((nextp)->castVpiHandle()); } return 0; // End of list - only one deep } }; class VerilatedVpioScope : public VerilatedVpio { protected: const VerilatedScope* m_scopep; public: explicit VerilatedVpioScope(const VerilatedScope* scopep) : m_scopep(scopep) {} virtual ~VerilatedVpioScope() {} static inline VerilatedVpioScope* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiScope; } const VerilatedScope* scopep() const { return m_scopep; } virtual const char* name() const { return m_scopep->name(); } virtual const char* fullname() const { return m_scopep->name(); } }; class VerilatedVpioVar : public VerilatedVpio { const VerilatedVar* m_varp; const VerilatedScope* m_scopep; vluint8_t* m_prevDatap; // Previous value of data, for cbValueChange union { vluint8_t u8[4]; vluint32_t u32; } m_mask; // memoized variable mask vluint32_t m_entSize; // memoized variable size protected: void* m_varDatap; // varp()->datap() adjusted for array entries vlsint32_t m_index; const VerilatedRange& get_range() const { // Determine number of dimensions and return outermost return (m_varp->dims() > 1) ? m_varp->unpacked() : m_varp->packed(); } public: VerilatedVpioVar(const VerilatedVar* varp, const VerilatedScope* scopep) : m_varp(varp) , m_scopep(scopep) , m_index(0) { m_prevDatap = NULL; m_mask.u32 = VL_MASK_I(varp->packed().elements()); m_entSize = varp->entSize(); m_varDatap = varp->datap(); } virtual ~VerilatedVpioVar() { if (m_prevDatap) VL_DO_CLEAR(delete[] m_prevDatap, m_prevDatap = NULL); } static inline VerilatedVpioVar* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } const VerilatedVar* varp() const { return m_varp; } const VerilatedScope* scopep() const { return m_scopep; } vluint32_t mask() const { return m_mask.u32; } vluint8_t mask_byte(int idx) { return m_mask.u8[idx & 3]; } vluint32_t entSize() const { return m_entSize; } vluint32_t index() { return m_index; } virtual vluint32_t type() const { return (varp()->dims() > 1) ? vpiMemory : vpiReg; // but might be wire, logic } virtual vluint32_t size() const { return get_range().elements(); } virtual const VerilatedRange* rangep() const { return &get_range(); } virtual const char* name() const { return m_varp->name(); } virtual const char* fullname() const { static VL_THREAD_LOCAL std::string out; out = std::string(m_scopep->name()) + "." + name(); return out.c_str(); } void* prevDatap() const { return m_prevDatap; } void* varDatap() const { return m_varDatap; } void createPrevDatap() { if (VL_UNLIKELY(!m_prevDatap)) { m_prevDatap = new vluint8_t[entSize()]; memcpy(prevDatap(), varp()->datap(), entSize()); } } }; class VerilatedVpioMemoryWord : public VerilatedVpioVar { public: VerilatedVpioMemoryWord(const VerilatedVar* varp, const VerilatedScope* scopep, vlsint32_t index, int offset) : VerilatedVpioVar(varp, scopep) { m_index = index; m_varDatap = (static_cast(varp->datap())) + entSize() * offset; } virtual ~VerilatedVpioMemoryWord() {} static inline VerilatedVpioMemoryWord* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiMemoryWord; } virtual vluint32_t size() const { return varp()->packed().elements(); } virtual const VerilatedRange* rangep() const { return &(varp()->packed()); } virtual const char* fullname() const { static VL_THREAD_LOCAL std::string out; char num[20]; sprintf(num, "%d", m_index); out = std::string(scopep()->name()) + "." + name() + "[" + num + "]"; return out.c_str(); } }; class VerilatedVpioVarIter : public VerilatedVpio { const VerilatedScope* m_scopep; VerilatedVarNameMap::const_iterator m_it; bool m_started; public: explicit VerilatedVpioVarIter(const VerilatedScope* scopep) : m_scopep(scopep) , m_started(false) {} virtual ~VerilatedVpioVarIter() {} static inline VerilatedVpioVarIter* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiIterator; } virtual vpiHandle dovpi_scan() { if (VL_LIKELY(m_scopep->varsp())) { VerilatedVarNameMap* varsp = m_scopep->varsp(); if (VL_UNLIKELY(!m_started)) { m_it = varsp->begin(); m_started = true; } else if (VL_UNLIKELY(m_it == varsp->end())) { return 0; } else { ++m_it; } if (m_it == varsp->end()) return 0; return ((new VerilatedVpioVar(&(m_it->second), m_scopep))->castVpiHandle()); } return 0; // End of list - only one deep } }; class VerilatedVpioMemoryWordIter : public VerilatedVpio { const vpiHandle m_handle; const VerilatedVar* m_varp; vlsint32_t m_iteration; vlsint32_t m_direction; bool m_done; public: VerilatedVpioMemoryWordIter(const vpiHandle handle, const VerilatedVar* varp) : m_handle(handle) , m_varp(varp) , m_iteration(varp->unpacked().right()) , m_direction(VL_LIKELY(varp->unpacked().left() > varp->unpacked().right()) ? 1 : -1) , m_done(false) {} virtual ~VerilatedVpioMemoryWordIter() {} static inline VerilatedVpioMemoryWordIter* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiIterator; } void iterationInc() { if (!(m_done = (m_iteration == m_varp->unpacked().left()))) m_iteration += m_direction; } virtual vpiHandle dovpi_scan() { vpiHandle result; if (m_done) return 0; result = vpi_handle_by_index(m_handle, m_iteration); iterationInc(); return result; } }; class VerilatedVpioModule : public VerilatedVpioScope { const char* m_name; const char* m_fullname; public: explicit VerilatedVpioModule(const VerilatedScope* modulep) : VerilatedVpioScope(modulep) { m_fullname = m_scopep->name(); if (strncmp(m_fullname, "TOP.", 4) == 0) m_fullname += 4; m_name = m_scopep->identifier(); } static inline VerilatedVpioModule* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiModule; } virtual const char* name() const { return m_name; } virtual const char* fullname() const { return m_fullname; } }; class VerilatedVpioModuleIter : public VerilatedVpio { const std::vector* m_vec; std::vector::const_iterator m_it; public: explicit VerilatedVpioModuleIter(const std::vector& vec) : m_vec(&vec) { m_it = m_vec->begin(); } virtual ~VerilatedVpioModuleIter() {} static inline VerilatedVpioModuleIter* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } virtual vluint32_t type() const { return vpiIterator; } virtual vpiHandle dovpi_scan() { if (m_it == m_vec->end()) return 0; const VerilatedScope* modp = *m_it++; return (new VerilatedVpioModule(modp))->castVpiHandle(); } }; //====================================================================== struct VerilatedVpiTimedCbsCmp { /// Ordering sets keyed by time, then callback descriptor bool operator()(const std::pair& a, const std::pair& b) const { if (a.first < b.first) return true; if (a.first > b.first) return false; return a.second < b.second; } }; class VerilatedVpiError; class VerilatedVpiImp { enum { CB_ENUM_MAX_VALUE = cbAtEndOfSimTime + 1 }; // Maxium callback reason typedef std::list VpioCbList; typedef std::set, VerilatedVpiTimedCbsCmp> VpioTimedCbs; struct product_info { PLI_BYTE8* product; }; VpioCbList m_cbObjLists[CB_ENUM_MAX_VALUE]; // Callbacks for each supported reason VpioTimedCbs m_timedCbs; // Time based callbacks VerilatedVpiError* m_errorInfop; // Container for vpi error info VerilatedAssertOneThread m_assertOne; ///< Assert only called from single thread static VerilatedVpiImp s_s; // Singleton public: VerilatedVpiImp() { m_errorInfop = NULL; } ~VerilatedVpiImp() {} static void assertOneCheck() { s_s.m_assertOne.check(); } static void cbReasonAdd(VerilatedVpioCb* vop) { if (vop->reason() == cbValueChange) { if (VerilatedVpioVar* varop = VerilatedVpioVar::castp(vop->cb_datap()->obj)) { varop->createPrevDatap(); } } if (VL_UNCOVERABLE(vop->reason() >= CB_ENUM_MAX_VALUE)) { VL_FATAL_MT(__FILE__, __LINE__, "", "vpi bb reason too large"); } s_s.m_cbObjLists[vop->reason()].push_back(vop); } static void cbTimedAdd(VerilatedVpioCb* vop) { s_s.m_timedCbs.insert(std::make_pair(vop->time(), vop)); } static void cbReasonRemove(VerilatedVpioCb* cbp) { VpioCbList& cbObjList = s_s.m_cbObjLists[cbp->reason()]; // We do not remove it now as we may be iterating the list, // instead set to NULL and will cleanup later for (VpioCbList::iterator it = cbObjList.begin(); it != cbObjList.end(); ++it) { if (*it == cbp) *it = NULL; } } static void cbTimedRemove(VerilatedVpioCb* cbp) { VpioTimedCbs::iterator it = s_s.m_timedCbs.find(std::make_pair(cbp->time(), cbp)); if (VL_LIKELY(it != s_s.m_timedCbs.end())) { s_s.m_timedCbs.erase(it); } } static void callTimedCbs() VL_MT_UNSAFE_ONE { assertOneCheck(); QData time = VL_TIME_Q(); for (VpioTimedCbs::iterator it = s_s.m_timedCbs.begin(); it != s_s.m_timedCbs.end();) { if (VL_UNLIKELY(it->first <= time)) { VerilatedVpioCb* vop = it->second; VpioTimedCbs::iterator last_it = it; ++it; // Timed callbacks are one-shot s_s.m_timedCbs.erase(last_it); VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: timed_callback %p\n", vop);); (vop->cb_rtnp())(vop->cb_datap()); } else { ++it; } } } static QData cbNextDeadline() { VpioTimedCbs::const_iterator it = s_s.m_timedCbs.begin(); if (VL_LIKELY(it != s_s.m_timedCbs.end())) return it->first; return ~0ULL; // maxquad } static bool callCbs(vluint32_t reason) VL_MT_UNSAFE_ONE { VpioCbList& cbObjList = s_s.m_cbObjLists[reason]; bool called = false; for (VpioCbList::iterator it = cbObjList.begin(); it != cbObjList.end();) { if (VL_UNLIKELY(!*it)) { // Deleted earlier, cleanup it = cbObjList.erase(it); continue; } VerilatedVpioCb* vop = *it++; VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: reason_callback %d %p\n", reason, vop);); (vop->cb_rtnp())(vop->cb_datap()); called = true; } return called; } static void callValueCbs() VL_MT_UNSAFE_ONE { assertOneCheck(); VpioCbList& cbObjList = s_s.m_cbObjLists[cbValueChange]; typedef std::set VpioVarSet; VpioVarSet update; // set of objects to update after callbacks for (VpioCbList::iterator it = cbObjList.begin(); it != cbObjList.end();) { if (VL_UNLIKELY(!*it)) { // Deleted earlier, cleanup it = cbObjList.erase(it); continue; } VerilatedVpioCb* vop = *it++; if (VerilatedVpioVar* varop = VerilatedVpioVar::castp(vop->cb_datap()->obj)) { void* newDatap = varop->varDatap(); void* prevDatap = varop->prevDatap(); // Was malloced when we added the callback VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_test %s v[0]=%d/%d %p %p\n", varop->fullname(), *((CData*)newDatap), *((CData*)prevDatap), newDatap, prevDatap);); if (memcmp(prevDatap, newDatap, varop->entSize()) != 0) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_callback %p %s v[0]=%d\n", vop, varop->fullname(), *((CData*)newDatap));); update.insert(varop); vpi_get_value(vop->cb_datap()->obj, vop->cb_datap()->value); (vop->cb_rtnp())(vop->cb_datap()); } } } for (VpioVarSet::const_iterator it = update.begin(); it != update.end(); ++it) { memcpy((*it)->prevDatap(), (*it)->varDatap(), (*it)->entSize()); } } static VerilatedVpiError* error_info() VL_MT_UNSAFE_ONE; // getter for vpi error info }; class VerilatedVpiError { //// Container for vpi error info t_vpi_error_info m_errorInfo; bool m_flag; char m_buff[VL_VPI_LINE_SIZE]; void setError(PLI_BYTE8* message, PLI_BYTE8* code, PLI_BYTE8* file, PLI_INT32 line) { m_errorInfo.message = message; m_errorInfo.file = file; m_errorInfo.line = line; m_errorInfo.code = code; do_callbacks(); } void do_callbacks() { if (getError()->level >= vpiError && Verilated::fatalOnVpiError()) { // Stop on vpi error/unsupported vpi_unsupported(); } // We need to run above code first because in the case that the // callback executes further vpi functions we will loose the error // as it will be overwritten. VerilatedVpiImp::callCbs(cbPLIError); } public: VerilatedVpiError() : m_flag(false) { m_buff[0] = '\0'; m_errorInfo.product = const_cast(Verilated::productName()); } ~VerilatedVpiError() {} static void selfTest() VL_MT_UNSAFE_ONE; VerilatedVpiError* setMessage(PLI_INT32 level) { m_flag = true; m_errorInfo.level = level; return this; } void setMessage(const std::string& file, PLI_INT32 line, const char* message, ...) { // message cannot be a const string& as va_start cannot use a reference static VL_THREAD_LOCAL std::string filehold; va_list args; va_start(args, message); VL_VSNPRINTF(m_buff, sizeof(m_buff), message, args); va_end(args); m_errorInfo.state = vpiPLI; filehold = file; setError((PLI_BYTE8*)m_buff, NULL, const_cast(filehold.c_str()), line); } p_vpi_error_info getError() { if (m_flag) return &m_errorInfo; return NULL; } void resetError() { m_flag = false; } static void vpi_unsupported() { // Not supported yet p_vpi_error_info error_info_p = VerilatedVpiImp::error_info()->getError(); if (error_info_p) { VL_FATAL_MT(error_info_p->file, error_info_p->line, "", error_info_p->message); return; } VL_FATAL_MT(__FILE__, __LINE__, "", "vpi_unsupported called without error info set"); } static const char* strFromVpiVal(PLI_INT32 vpiVal) VL_MT_SAFE; static const char* strFromVpiObjType(PLI_INT32 vpiVal) VL_MT_SAFE; static const char* strFromVpiMethod(PLI_INT32 vpiVal) VL_MT_SAFE; static const char* strFromVpiCallbackReason(PLI_INT32 vpiVal) VL_MT_SAFE; static const char* strFromVpiProp(PLI_INT32 vpiVal) VL_MT_SAFE; }; //====================================================================== VerilatedVpiImp VerilatedVpiImp::s_s; // Singleton VL_THREAD_LOCAL vluint8_t* VerilatedVpio::t_freeHead = NULL; //====================================================================== // VerilatedVpi implementation void VerilatedVpi::callTimedCbs() VL_MT_UNSAFE_ONE { VerilatedVpiImp::callTimedCbs(); } void VerilatedVpi::callValueCbs() VL_MT_UNSAFE_ONE { VerilatedVpiImp::callValueCbs(); } bool VerilatedVpi::callCbs(vluint32_t reason) VL_MT_UNSAFE_ONE { return VerilatedVpiImp::callCbs(reason); } QData VerilatedVpi::cbNextDeadline() VL_MT_UNSAFE_ONE { return VerilatedVpiImp::cbNextDeadline(); } //====================================================================== // VerilatedVpiImp implementation VerilatedVpiError* VerilatedVpiImp::error_info() VL_MT_UNSAFE_ONE { VerilatedVpiImp::assertOneCheck(); if (VL_UNLIKELY(!s_s.m_errorInfop)) { s_s.m_errorInfop = new VerilatedVpiError(); } return s_s.m_errorInfop; } //====================================================================== // VerilatedVpiError Methods const char* VerilatedVpiError::strFromVpiVal(PLI_INT32 vpiVal) VL_MT_SAFE { // clang-format off static const char* const names[] = { "*undefined*", "vpiBinStrVal", "vpiOctStrVal", "vpiDecStrVal", "vpiHexStrVal", "vpiScalarVal", "vpiIntVal", "vpiRealVal", "vpiStringVal", "vpiVectorVal", "vpiStrengthVal", "vpiTimeVal", "vpiObjTypeVal", "vpiSuppressVal", "vpiShortIntVal", "vpiLongIntVal", "vpiShortRealVal", "vpiRawTwoStateVal", "vpiRawFourStateVal", }; // clang-format on if (VL_UNCOVERABLE(vpiVal < 0)) return names[0]; return names[(vpiVal <= vpiRawFourStateVal) ? vpiVal : 0]; } const char* VerilatedVpiError::strFromVpiObjType(PLI_INT32 vpiVal) VL_MT_SAFE { // clang-format off static const char* const names[] = { "*undefined*", "vpiAlways", "vpiAssignStmt", "vpiAssignment", "vpiBegin", "vpiCase", "vpiCaseItem", "vpiConstant", "vpiContAssign", "vpiDeassign", "vpiDefParam", "vpiDelayControl", "vpiDisable", "vpiEventControl", "vpiEventStmt", "vpiFor", "vpiForce", "vpiForever", "vpiFork", "vpiFuncCall", "vpiFunction", "vpiGate", "vpiIf", "vpiIfElse", "vpiInitial", "vpiIntegerVar", "vpiInterModPath", "vpiIterator", "vpiIODecl", "vpiMemory", "vpiMemoryWord", "vpiModPath", "vpiModule", "vpiNamedBegin", "vpiNamedEvent", "vpiNamedFork", "vpiNet", "vpiNetBit", "vpiNullStmt", "vpiOperation", "vpiParamAssign", "vpiParameter", "vpiPartSelect", "vpiPathTerm", "vpiPort", "vpiPortBit", "vpiPrimTerm", "vpiRealVar", "vpiReg", "vpiRegBit", "vpiRelease", "vpiRepeat", "vpiRepeatControl", "vpiSchedEvent", "vpiSpecParam", "vpiSwitch", "vpiSysFuncCall", "vpiSysTaskCall", "vpiTableEntry", "vpiTask", "vpiTaskCall", "vpiTchk", "vpiTchkTerm", "vpiTimeVar", "vpiTimeQueue", "vpiUdp", "vpiUdpDefn", "vpiUserSystf", "vpiVarSelect", "vpiWait", "vpiWhile", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "vpiAttribute", "vpiBitSelect", "vpiCallback", "vpiDelayTerm", "vpiDelayDevice", "vpiFrame", "vpiGateArray", "vpiModuleArray", "vpiPrimitiveArray", "vpiNetArray", "vpiRange", "vpiRegArray", "vpiSwitchArray", "vpiUdpArray", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "*undefined*", "vpiContAssignBit", "vpiNamedEventArray", "vpiIndexedPartSelect", "*undefined*", "*undefined*", "vpiGenScopeArray", "vpiGenScope", "vpiGenVar" }; // clang-format on if (VL_UNCOVERABLE(vpiVal < 0)) return names[0]; return names[(vpiVal <= vpiGenVar) ? vpiVal : 0]; } const char* VerilatedVpiError::strFromVpiMethod(PLI_INT32 vpiVal) VL_MT_SAFE { // clang-format off static const char* const names[] = { "vpiCondition", "vpiDelay", "vpiElseStmt", "vpiForIncStmt", "vpiForInitStmt", "vpiHighConn", "vpiLhs", "vpiIndex", "vpiLeftRange", "vpiLowConn", "vpiParent", "vpiRhs", "vpiRightRange", "vpiScope", "vpiSysTfCall", "vpiTchkDataTerm", "vpiTchkNotifier", "vpiTchkRefTerm", "vpiArgument", "vpiBit", "vpiDriver", "vpiInternalScope", "vpiLoad", "vpiModDataPathIn", "vpiModPathIn", "vpiModPathOut", "vpiOperand", "vpiPortInst", "vpiProcess", "vpiVariables", "vpiUse", "vpiExpr", "vpiPrimitive", "vpiStmt" }; // clang-format on if (vpiVal > vpiStmt || vpiVal < vpiCondition) return "*undefined*"; return names[vpiVal - vpiCondition]; } const char* VerilatedVpiError::strFromVpiCallbackReason(PLI_INT32 vpiVal) VL_MT_SAFE { // clang-format off static const char* const names[] = { "*undefined*", "cbValueChange", "cbStmt", "cbForce", "cbRelease", "cbAtStartOfSimTime", "cbReadWriteSynch", "cbReadOnlySynch", "cbNextSimTime", "cbAfterDelay", "cbEndOfCompile", "cbStartOfSimulation", "cbEndOfSimulation", "cbError", "cbTchkViolation", "cbStartOfSave", "cbEndOfSave", "cbStartOfRestart", "cbEndOfRestart", "cbStartOfReset", "cbEndOfReset", "cbEnterInteractive", "cbExitInteractive", "cbInteractiveScopeChange", "cbUnresolvedSystf", "cbAssign", "cbDeassign", "cbDisable", "cbPLIError", "cbSignal", "cbNBASynch", "cbAtEndOfSimTime" }; // clang-format on if (VL_UNCOVERABLE(vpiVal < 0)) return names[0]; return names[(vpiVal <= cbAtEndOfSimTime) ? vpiVal : 0]; } const char* VerilatedVpiError::strFromVpiProp(PLI_INT32 vpiVal) VL_MT_SAFE { // clang-format off static const char* const names[] = { "*undefined or other*", "vpiType", "vpiName", "vpiFullName", "vpiSize", "vpiFile", "vpiLineNo", "vpiTopModule", "vpiCellInstance", "vpiDefName", "vpiProtected", "vpiTimeUnit", "vpiTimePrecision", "vpiDefNetType", "vpiUnconnDrive", "vpiDefFile", "vpiDefLineNo", "vpiScalar", "vpiVector", "vpiExplicitName", "vpiDirection", "vpiConnByName", "vpiNetType", "vpiExplicitScalared", "vpiExplicitVectored", "vpiExpanded", "vpiImplicitDecl", "vpiChargeStrength", "vpiArray", "vpiPortIndex", "vpiTermIndex", "vpiStrength0", "vpiStrength1", "vpiPrimType", "vpiPolarity", "vpiDataPolarity", "vpiEdge", "vpiPathType", "vpiTchkType", "vpiOpType", "vpiConstType", "vpiBlocking", "vpiCaseType", "vpiFuncType", "vpiNetDeclAssign", "vpiUserDefn", "vpiScheduled", "*undefined*", "*undefined*", "vpiActive", "vpiAutomatic", "vpiCell", "vpiConfig", "vpiConstantSelect", "vpiDecompile", "vpiDefAttribute", "vpiDelayType", "vpiIteratorType", "vpiLibrary", "*undefined*", "vpiOffset", "vpiResolvedNetType", "vpiSaveRestartID", "vpiSaveRestartLocation", "vpiValid", "vpiSigned", "vpiStop", "vpiFinish", "vpiReset", "vpiSetInteractiveScope", "vpiLocalParam", "vpiModPathHasIfNone", "vpiIndexedPartSelectType", "vpiIsMemory", "vpiIsProtected" }; // clang-format on if (vpiVal == vpiUndefined) return "vpiUndefined"; return names[(vpiVal <= vpiIsProtected) ? vpiVal : 0]; } #define SELF_CHECK_RESULT_CSTR(got, exp) \ if (0 != strcmp((got), (exp))) { \ std::string msg \ = std::string("%Error: ") + "GOT = '" + got + "'" + " EXP = '" + exp + "'"; \ VL_FATAL_MT(__FILE__, __LINE__, "", msg.c_str()); \ } #define SELF_CHECK_ENUM_STR(fn, enum) \ do { \ const char* strVal = VerilatedVpiError::fn(enum); \ SELF_CHECK_RESULT_CSTR(strVal, #enum); \ } while (0) void VerilatedVpi::selfTest() VL_MT_UNSAFE_ONE { VerilatedVpiError::selfTest(); } void VerilatedVpiError::selfTest() VL_MT_UNSAFE_ONE { VerilatedVpiImp::assertOneCheck(); SELF_CHECK_ENUM_STR(strFromVpiVal, vpiBinStrVal); SELF_CHECK_ENUM_STR(strFromVpiVal, vpiRawFourStateVal); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAlways); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiWhile); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAttribute); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUdpArray); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiContAssignBit); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGenVar); SELF_CHECK_ENUM_STR(strFromVpiMethod, vpiCondition); SELF_CHECK_ENUM_STR(strFromVpiMethod, vpiStmt); SELF_CHECK_ENUM_STR(strFromVpiCallbackReason, cbValueChange); SELF_CHECK_ENUM_STR(strFromVpiCallbackReason, cbAtEndOfSimTime); SELF_CHECK_ENUM_STR(strFromVpiProp, vpiType); SELF_CHECK_ENUM_STR(strFromVpiProp, vpiProtected); SELF_CHECK_ENUM_STR(strFromVpiProp, vpiDirection); SELF_CHECK_ENUM_STR(strFromVpiProp, vpiTermIndex); SELF_CHECK_ENUM_STR(strFromVpiProp, vpiConstType); SELF_CHECK_ENUM_STR(strFromVpiProp, vpiAutomatic); SELF_CHECK_ENUM_STR(strFromVpiProp, vpiOffset); SELF_CHECK_ENUM_STR(strFromVpiProp, vpiStop); SELF_CHECK_ENUM_STR(strFromVpiProp, vpiIsProtected); } #undef SELF_CHECK_ENUM_STR #undef SELF_CHECK_RESULT_CSTR //====================================================================== // callback related vpiHandle vpi_register_cb(p_cb_data cb_data_p) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); // cppcheck-suppress nullPointer if (VL_UNLIKELY(!cb_data_p)) { _VL_VPI_WARNING(__FILE__, __LINE__, "%s : callback data pointer is null", VL_FUNC); return NULL; } switch (cb_data_p->reason) { case cbAfterDelay: { QData time = 0; if (cb_data_p->time) time = _VL_SET_QII(cb_data_p->time->high, cb_data_p->time->low); VerilatedVpioCb* vop = new VerilatedVpioCb(cb_data_p, VL_TIME_Q() + time); VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb %d %p delay=%" VL_PRI64 "u\n", cb_data_p->reason, vop, time);); VerilatedVpiImp::cbTimedAdd(vop); return vop->castVpiHandle(); } case cbReadWriteSynch: // FALLTHRU // Supported via vlt_main.cpp case cbReadOnlySynch: // FALLTHRU // Supported via vlt_main.cpp case cbNextSimTime: // FALLTHRU // Supported via vlt_main.cpp case cbStartOfSimulation: // FALLTHRU // Supported via vlt_main.cpp case cbEndOfSimulation: // FALLTHRU // Supported via vlt_main.cpp case cbValueChange: // FALLTHRU // Supported via vlt_main.cpp case cbPLIError: // FALLTHRU // NOP, but need to return handle, so make object case cbEnterInteractive: // FALLTHRU // NOP, but need to return handle, so make object case cbExitInteractive: // FALLTHRU // NOP, but need to return handle, so make object case cbInteractiveScopeChange: { // FALLTHRU // NOP, but need to return handle, so make object VerilatedVpioCb* vop = new VerilatedVpioCb(cb_data_p, 0); VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb %d %p\n", cb_data_p->reason, vop);); VerilatedVpiImp::cbReasonAdd(vop); return vop->castVpiHandle(); } default: _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Unsupported callback type %s", VL_FUNC, VerilatedVpiError::strFromVpiCallbackReason(cb_data_p->reason)); return NULL; } } PLI_INT32 vpi_remove_cb(vpiHandle object) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_remove_cb %p\n", object);); VerilatedVpiImp::assertOneCheck(); VerilatedVpioCb* vop = VerilatedVpioCb::castp(object); _VL_VPI_ERROR_RESET(); if (VL_UNLIKELY(!vop)) return 0; if (vop->cb_datap()->reason == cbAfterDelay) { VerilatedVpiImp::cbTimedRemove(vop); } else { VerilatedVpiImp::cbReasonRemove(vop); } return 1; } void vpi_get_cb_info(vpiHandle /*object*/, p_cb_data /*cb_data_p*/) { _VL_VPI_UNIMP(); } vpiHandle vpi_register_systf(p_vpi_systf_data /*systf_data_p*/) { _VL_VPI_UNIMP(); return 0; } void vpi_get_systf_info(vpiHandle /*object*/, p_vpi_systf_data /*systf_data_p*/) { _VL_VPI_UNIMP(); } // for obtaining handles vpiHandle vpi_handle_by_name(PLI_BYTE8* namep, vpiHandle scope) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); if (VL_UNLIKELY(!namep)) return NULL; VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_handle_by_name %s %p\n", namep, scope);); const VerilatedVar* varp = NULL; const VerilatedScope* scopep; VerilatedVpioScope* voScopep = VerilatedVpioScope::castp(scope); std::string scopeAndName = namep; if (voScopep) { scopeAndName = std::string(voScopep->fullname()) + "." + namep; namep = const_cast(scopeAndName.c_str()); } { // This doesn't yet follow the hierarchy in the proper way scopep = Verilated::scopeFind(namep); if (scopep) { // Whole thing found as a scope if (scopep->type() == VerilatedScope::SCOPE_MODULE) { return (new VerilatedVpioModule(scopep))->castVpiHandle(); } else { return (new VerilatedVpioScope(scopep))->castVpiHandle(); } } const char* baseNamep = scopeAndName.c_str(); std::string scopename; const char* dotp = strrchr(namep, '.'); if (VL_LIKELY(dotp)) { baseNamep = dotp + 1; scopename = std::string(namep, dotp - namep); } if (scopename.find('.') == std::string::npos) { // This is a toplevel, hence search in our TOP ports first. scopep = Verilated::scopeFind("TOP"); if (scopep) { varp = scopep->varFind(baseNamep); } } if (!varp) { scopep = Verilated::scopeFind(scopename.c_str()); if (!scopep) return NULL; varp = scopep->varFind(baseNamep); } } if (!varp) return NULL; if (varp->isParam()) { return (new VerilatedVpioParam(varp, scopep))->castVpiHandle(); } else { return (new VerilatedVpioVar(varp, scopep))->castVpiHandle(); } } vpiHandle vpi_handle_by_index(vpiHandle object, PLI_INT32 indx) { // Used to get array entries VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_handle_by_index %p %d\n", object, indx);); VerilatedVpiImp::assertOneCheck(); VerilatedVpioVar* varop = VerilatedVpioVar::castp(object); _VL_VPI_ERROR_RESET(); if (VL_LIKELY(varop)) { if (varop->varp()->dims() < 2) return 0; if (VL_LIKELY(varop->varp()->unpacked().left() >= varop->varp()->unpacked().right())) { if (VL_UNLIKELY(indx > varop->varp()->unpacked().left() || indx < varop->varp()->unpacked().right())) return 0; return (new VerilatedVpioMemoryWord(varop->varp(), varop->scopep(), indx, indx - varop->varp()->unpacked().right())) ->castVpiHandle(); } if (VL_UNLIKELY(indx < varop->varp()->unpacked().left() || indx > varop->varp()->unpacked().right())) return 0; return (new VerilatedVpioMemoryWord(varop->varp(), varop->scopep(), indx, indx - varop->varp()->unpacked().left())) ->castVpiHandle(); } _VL_VPI_INTERNAL(__FILE__, __LINE__, "%s : can't resolve handle", VL_FUNC); return 0; } // for traversing relationships vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_handle %d %p\n", type, object);); VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); switch (type) { case vpiLeftRange: { if (VerilatedVpioVar* vop = VerilatedVpioVar::castp(object)) { if (VL_UNLIKELY(!vop->rangep())) return 0; return (new VerilatedVpioConst(vop->rangep()->left()))->castVpiHandle(); } else if (VerilatedVpioRange* vop = VerilatedVpioRange::castp(object)) { if (VL_UNLIKELY(!vop->rangep())) return 0; return (new VerilatedVpioConst(vop->rangep()->left()))->castVpiHandle(); } _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p) for type %s, nothing will be returned", VL_FUNC, object, VerilatedVpiError::strFromVpiMethod(type)); return 0; } case vpiRightRange: { if (VerilatedVpioVar* vop = VerilatedVpioVar::castp(object)) { if (VL_UNLIKELY(!vop->rangep())) return 0; return (new VerilatedVpioConst(vop->rangep()->right()))->castVpiHandle(); } else if (VerilatedVpioRange* vop = VerilatedVpioRange::castp(object)) { if (VL_UNLIKELY(!vop->rangep())) return 0; return (new VerilatedVpioConst(vop->rangep()->right()))->castVpiHandle(); } _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p) for type %s, nothing will be returned", VL_FUNC, object, VerilatedVpiError::strFromVpiMethod(type)); return 0; } case vpiIndex: { VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); if (VL_UNLIKELY(!vop)) return 0; return (new VerilatedVpioConst(vop->index()))->castVpiHandle(); } case vpiScope: { VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); if (VL_UNLIKELY(!vop)) return 0; return (new VerilatedVpioScope(vop->scopep()))->castVpiHandle(); } case vpiParent: { VerilatedVpioMemoryWord* vop = VerilatedVpioMemoryWord::castp(object); if (VL_UNLIKELY(!vop)) return 0; return (new VerilatedVpioVar(vop->varp(), vop->scopep()))->castVpiHandle(); } default: _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", VL_FUNC, VerilatedVpiError::strFromVpiMethod(type)); return 0; } } vpiHandle vpi_handle_multi(PLI_INT32 /*type*/, vpiHandle /*refHandle1*/, vpiHandle /*refHandle2*/, ...) { _VL_VPI_UNIMP(); return 0; } vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_iterate %d %p\n", type, object);); VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); switch (type) { case vpiMemoryWord: { VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); if (VL_UNLIKELY(!vop)) return 0; if (vop->varp()->dims() < 2) return 0; if (vop->varp()->dims() > 2) { _VL_VPI_WARNING(__FILE__, __LINE__, "%s: %s, object %s has unsupported number of indices (%d)", VL_FUNC, VerilatedVpiError::strFromVpiMethod(type), vop->fullname(), vop->varp()->dims()); } return (new VerilatedVpioMemoryWordIter(object, vop->varp()))->castVpiHandle(); } case vpiRange: { VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); if (VL_UNLIKELY(!vop)) return 0; if (vop->varp()->dims() < 2) return 0; // Unsupported is multidim list if (vop->varp()->dims() > 2) { _VL_VPI_WARNING(__FILE__, __LINE__, "%s: %s, object %s has unsupported number of indices (%d)", VL_FUNC, VerilatedVpiError::strFromVpiMethod(type), vop->fullname(), vop->varp()->dims()); } return ((new VerilatedVpioRange(vop->rangep()))->castVpiHandle()); } case vpiReg: { VerilatedVpioScope* vop = VerilatedVpioScope::castp(object); if (VL_UNLIKELY(!vop)) return 0; return ((new VerilatedVpioVarIter(vop->scopep()))->castVpiHandle()); } case vpiModule: { VerilatedVpioModule* vop = VerilatedVpioModule::castp(object); const VerilatedHierarchyMap* map = VerilatedImp::hierarchyMap(); const VerilatedScope* mod = vop ? vop->scopep() : NULL; VerilatedHierarchyMap::const_iterator it = map->find(const_cast(mod)); if (it == map->end()) return 0; return ((new VerilatedVpioModuleIter(it->second))->castVpiHandle()); } default: _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", VL_FUNC, VerilatedVpiError::strFromVpiObjType(type)); return 0; } } vpiHandle vpi_scan(vpiHandle object) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_scan %p\n", object);); VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); VerilatedVpio* vop = VerilatedVpio::castp(object); if (VL_UNLIKELY(!vop)) return NULL; return vop->dovpi_scan(); } // for processing properties PLI_INT32 vpi_get(PLI_INT32 property, vpiHandle object) { // Leave this in the header file - in many cases the compiler can constant propagate "object" VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_get %d %p\n", property, object);); VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); switch (property) { case vpiTimePrecision: { return Verilated::timeprecision(); } case vpiTimeUnit: { VerilatedVpioScope* vop = VerilatedVpioScope::castp(object); if (!vop) return Verilated::timeunit(); // Null asks for global, not unlikely return vop->scopep()->timeunit(); } case vpiType: { VerilatedVpio* vop = VerilatedVpio::castp(object); if (VL_UNLIKELY(!vop)) return 0; return vop->type(); } case vpiDirection: { // By forthought, the directions already are vpi enumerated VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); if (VL_UNLIKELY(!vop)) return 0; return vop->varp()->vldir(); } case vpiScalar: // FALLTHRU case vpiVector: { VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); if (VL_UNLIKELY(!vop)) return 0; return (property == vpiVector) ^ (vop->varp()->dims() == 0); } case vpiSize: { VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); if (VL_UNLIKELY(!vop)) return 0; return vop->size(); } default: _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", VL_FUNC, VerilatedVpiError::strFromVpiProp(property)); return 0; } } PLI_INT64 vpi_get64(PLI_INT32 /*property*/, vpiHandle /*object*/) { _VL_VPI_UNIMP(); return 0; } PLI_BYTE8* vpi_get_str(PLI_INT32 property, vpiHandle object) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_get_str %d %p\n", property, object);); VerilatedVpiImp::assertOneCheck(); VerilatedVpio* vop = VerilatedVpio::castp(object); _VL_VPI_ERROR_RESET(); if (VL_UNLIKELY(!vop)) return NULL; switch (property) { case vpiName: { return const_cast(vop->name()); } case vpiFullName: { return const_cast(vop->fullname()); } case vpiDefName: { return const_cast(vop->defname()); } case vpiType: { return const_cast(VerilatedVpiError::strFromVpiObjType(vop->type())); } default: _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", VL_FUNC, VerilatedVpiError::strFromVpiProp(property)); return 0; } } // delay processing void vpi_get_delays(vpiHandle /*object*/, p_vpi_delay /*delay_p*/) { _VL_VPI_UNIMP(); } void vpi_put_delays(vpiHandle /*object*/, p_vpi_delay /*delay_p*/) { _VL_VPI_UNIMP(); } // value processing bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const char* fullname, bool isGetValue) { bool status = true; if ((valuep->format == vpiVectorVal) || (valuep->format == vpiBinStrVal) || (valuep->format == vpiOctStrVal) || (valuep->format == vpiHexStrVal)) { switch (varp->vltype()) { case VLVT_UINT8: case VLVT_UINT16: case VLVT_UINT32: case VLVT_UINT64: case VLVT_WDATA: return status; default: status = false; } } else if (valuep->format == vpiDecStrVal) { switch (varp->vltype()) { case VLVT_UINT8: case VLVT_UINT16: case VLVT_UINT32: case VLVT_UINT64: return status; default: status = false; } } else if (valuep->format == vpiStringVal) { switch (varp->vltype()) { case VLVT_UINT8: case VLVT_UINT16: case VLVT_UINT32: case VLVT_UINT64: case VLVT_WDATA: return status; case VLVT_STRING: if (isGetValue) { return status; } else { status = false; break; } default: status = false; } } else if (valuep->format == vpiIntVal) { switch (varp->vltype()) { case VLVT_UINT8: case VLVT_UINT16: case VLVT_UINT32: return status; default: status = false; } } else if (valuep->format == vpiSuppressVal) { return status; } else { status = false; } _VL_VPI_ERROR(__FILE__, __LINE__, "%s: Unsupported format (%s) for %s", VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname); return status; } void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep, const char* fullname) { if (!vl_check_format(varp, valuep, fullname, true)) return; // Maximum required size is for binary string, one byte per bit plus null termination static VL_THREAD_LOCAL char outStr[1 + VL_MULS_MAX_WORDS * 32]; // cppcheck-suppress variableScope static VL_THREAD_LOCAL int outStrSz = sizeof(outStr) - 1; // We used to presume vpiValue.format = vpiIntVal or if single bit vpiScalarVal // This may cause backward compatibility issues with older code. if (valuep->format == vpiVectorVal) { // Vector pointer must come from our memory pool // It only needs to persist until the next vpi_get_value static VL_THREAD_LOCAL t_vpi_vecval out[VL_MULS_MAX_WORDS * 2]; valuep->value.vector = out; if (varp->vltype() == VLVT_UINT8) { out[0].aval = *(reinterpret_cast(varDatap)); out[0].bval = 0; return; } else if (varp->vltype() == VLVT_UINT16) { out[0].aval = *(reinterpret_cast(varDatap)); out[0].bval = 0; return; } else if (varp->vltype() == VLVT_UINT32) { out[0].aval = *(reinterpret_cast(varDatap)); out[0].bval = 0; return; } else if (varp->vltype() == VLVT_UINT64) { QData data = *(reinterpret_cast(varDatap)); out[1].aval = static_cast(data >> 32ULL); out[1].bval = 0; out[0].aval = static_cast(data); out[0].bval = 0; return; } else if (varp->vltype() == VLVT_WDATA) { int words = VL_WORDS_I(varp->packed().elements()); if (VL_UNCOVERABLE(words >= VL_MULS_MAX_WORDS)) { VL_FATAL_MT( __FILE__, __LINE__, "", "vpi_get_value with more than VL_MULS_MAX_WORDS; increase and recompile"); } WDataInP datap = (reinterpret_cast(varDatap)); for (int i = 0; i < words; ++i) { out[i].aval = datap[i]; out[i].bval = 0; } return; } } else if (valuep->format == vpiBinStrVal) { valuep->value.str = outStr; int bits = varp->packed().elements(); CData* datap = (reinterpret_cast(varDatap)); int i; if (bits > outStrSz) { // limit maximum size of output to size of buffer to prevent overrun. bits = outStrSz; _VL_VPI_WARNING( __FILE__, __LINE__, "%s: Truncating string value of %s for %s" " as buffer size (%d, VL_MULS_MAX_WORDS=%d) is less than required (%d)", VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, outStrSz, VL_MULS_MAX_WORDS, bits); } for (i = 0; i < bits; ++i) { char val = (datap[i >> 3] >> (i & 7)) & 1; outStr[bits - i - 1] = val ? '1' : '0'; } outStr[i] = '\0'; return; } else if (valuep->format == vpiOctStrVal) { valuep->value.str = outStr; int chars = (varp->packed().elements() + 2) / 3; int bytes = VL_BYTES_I(varp->packed().elements()); CData* datap = (reinterpret_cast(varDatap)); int i; if (chars > outStrSz) { // limit maximum size of output to size of buffer to prevent overrun. _VL_VPI_WARNING( __FILE__, __LINE__, "%s: Truncating string value of %s for %s" " as buffer size (%d, VL_MULS_MAX_WORDS=%d) is less than required (%d)", VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, outStrSz, VL_MULS_MAX_WORDS, chars); chars = outStrSz; } for (i = 0; i < chars; ++i) { div_t idx = div(i * 3, 8); int val = datap[idx.quot]; if ((idx.quot + 1) < bytes) { // if the next byte is valid or that in // for when the required 3 bits straddle adjacent bytes val |= datap[idx.quot + 1] << 8; } // align so least significant 3 bits represent octal char val >>= idx.rem; if (i == (chars - 1)) { // most signifcant char, mask off non existant bits when vector // size is not a multiple of 3 unsigned int rem = varp->packed().elements() % 3; if (rem) { // generate bit mask & zero non existant bits val &= (1 << rem) - 1; } } outStr[chars - i - 1] = '0' + (val & 7); } outStr[i] = '\0'; return; } else if (valuep->format == vpiDecStrVal) { valuep->value.str = outStr; // outStrSz does not include NULL termination so add one if (varp->vltype() == VLVT_UINT8) { VL_SNPRINTF(outStr, outStrSz + 1, "%hhu", static_cast(*(reinterpret_cast(varDatap)))); return; } else if (varp->vltype() == VLVT_UINT16) { VL_SNPRINTF(outStr, outStrSz + 1, "%hu", static_cast(*(reinterpret_cast(varDatap)))); return; } else if (varp->vltype() == VLVT_UINT32) { VL_SNPRINTF(outStr, outStrSz + 1, "%u", static_cast(*(reinterpret_cast(varDatap)))); return; } else if (varp->vltype() == VLVT_UINT64) { VL_SNPRINTF(outStr, outStrSz + 1, "%llu", static_cast(*(reinterpret_cast(varDatap)))); return; } } else if (valuep->format == vpiHexStrVal) { valuep->value.str = outStr; int chars = (varp->packed().elements() + 3) >> 2; CData* datap = (reinterpret_cast(varDatap)); int i; if (chars > outStrSz) { // limit maximum size of output to size of buffer to prevent overrun. _VL_VPI_WARNING( __FILE__, __LINE__, "%s: Truncating string value of %s for %s" " as buffer size (%d, VL_MULS_MAX_WORDS=%d) is less than required (%d)", VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, outStrSz, VL_MULS_MAX_WORDS, chars); chars = outStrSz; } for (i = 0; i < chars; ++i) { char val = (datap[i >> 1] >> ((i & 1) << 2)) & 15; if (i == (chars - 1)) { // most signifcant char, mask off non existant bits when vector // size is not a multiple of 4 unsigned int rem = varp->packed().elements() & 3; if (rem) { // generate bit mask & zero non existant bits val &= (1 << rem) - 1; } } outStr[chars - i - 1] = "0123456789abcdef"[static_cast(val)]; } outStr[i] = '\0'; return; } else if (valuep->format == vpiStringVal) { if (varp->vltype() == VLVT_STRING) { valuep->value.str = reinterpret_cast(varDatap); return; } else { valuep->value.str = outStr; int bytes = VL_BYTES_I(varp->packed().elements()); CData* datap = (reinterpret_cast(varDatap)); int i; if (bytes > outStrSz) { // limit maximum size of output to size of buffer to prevent overrun. _VL_VPI_WARNING( __FILE__, __LINE__, "%s: Truncating string value of %s for %s" " as buffer size (%d, VL_MULS_MAX_WORDS=%d) is less than required (%d)", VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, outStrSz, VL_MULS_MAX_WORDS, bytes); bytes = outStrSz; } for (i = 0; i < bytes; ++i) { char val = datap[bytes - i - 1]; // other simulators replace [leading?] zero chars with spaces, replicate here. outStr[i] = val ? val : ' '; } outStr[i] = '\0'; return; } } else if (valuep->format == vpiIntVal) { if (varp->vltype() == VLVT_UINT8) { valuep->value.integer = *(reinterpret_cast(varDatap)); return; } else if (varp->vltype() == VLVT_UINT16) { valuep->value.integer = *(reinterpret_cast(varDatap)); return; } else if (varp->vltype() == VLVT_UINT32) { valuep->value.integer = *(reinterpret_cast(varDatap)); return; } } else if (valuep->format == vpiSuppressVal) { return; } _VL_VPI_ERROR(__FILE__, __LINE__, "%s: Unsupported format (%s) as requested for %s", VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname); return; } void vpi_get_value(vpiHandle object, p_vpi_value valuep) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_get_value %p\n", object);); VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); if (VL_UNLIKELY(!valuep)) return; if (VerilatedVpioVar* vop = VerilatedVpioVar::castp(object)) { vl_get_value(vop->varp(), vop->varDatap(), valuep, vop->fullname()); return; } else if (VerilatedVpioParam* vop = VerilatedVpioParam::castp(object)) { vl_get_value(vop->varp(), vop->varDatap(), valuep, vop->fullname()); return; } else if (VerilatedVpioConst* vop = VerilatedVpioConst::castp(object)) { if (valuep->format == vpiIntVal) { valuep->value.integer = vop->num(); return; } _VL_VPI_ERROR(__FILE__, __LINE__, "%s: Unsupported format (%s) for %s", VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); return; } _VL_VPI_ERROR(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p)", VL_FUNC, object); } vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_p*/, PLI_INT32 /*flags*/) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_put_value %p %p\n", object, valuep);); VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); if (VL_UNLIKELY(!valuep)) { _VL_VPI_WARNING(__FILE__, __LINE__, "Ignoring vpi_put_value with NULL value pointer"); return 0; } if (VerilatedVpioVar* vop = VerilatedVpioVar::castp(object)) { VL_DEBUG_IF_PLI( VL_DBG_MSGF("- vpi: vpi_put_value name=%s fmt=%d vali=%d\n", vop->fullname(), valuep->format, valuep->value.integer); VL_DBG_MSGF("- vpi: varp=%p putatp=%p\n", vop->varp()->datap(), vop->varDatap());); if (VL_UNLIKELY(!vop->varp()->isPublicRW())) { _VL_VPI_WARNING(__FILE__, __LINE__, "Ignoring vpi_put_value to signal marked read-only," " use public_flat_rw instead: %s", vop->fullname()); return 0; } if (!vl_check_format(vop->varp(), valuep, vop->fullname(), false)) return 0; if (valuep->format == vpiVectorVal) { if (VL_UNLIKELY(!valuep->value.vector)) return NULL; if (vop->varp()->vltype() == VLVT_UINT8) { *(reinterpret_cast(vop->varDatap())) = valuep->value.vector[0].aval & vop->mask(); return object; } else if (vop->varp()->vltype() == VLVT_UINT16) { *(reinterpret_cast(vop->varDatap())) = valuep->value.vector[0].aval & vop->mask(); return object; } else if (vop->varp()->vltype() == VLVT_UINT32) { *(reinterpret_cast(vop->varDatap())) = valuep->value.vector[0].aval & vop->mask(); return object; } else if (vop->varp()->vltype() == VLVT_UINT64) { *(reinterpret_cast(vop->varDatap())) = _VL_SET_QII( valuep->value.vector[1].aval & vop->mask(), valuep->value.vector[0].aval); return object; } else if (vop->varp()->vltype() == VLVT_WDATA) { int words = VL_WORDS_I(vop->varp()->packed().elements()); WDataOutP datap = (reinterpret_cast(vop->varDatap())); for (int i = 0; i < words; ++i) { datap[i] = valuep->value.vector[i].aval; if (i == (words - 1)) datap[i] &= vop->mask(); } return object; } } else if (valuep->format == vpiBinStrVal) { int bits = vop->varp()->packed().elements(); int len = strlen(valuep->value.str); CData* datap = (reinterpret_cast(vop->varDatap())); for (int i = 0; i < bits; ++i) { char set = (i < len) ? (valuep->value.str[len - i - 1] == '1') : 0; // zero bits 7:1 of byte when assigning to bit 0, else // or in 1 if bit set if (i & 7) { datap[i >> 3] |= set << (i & 7); } else { datap[i >> 3] = set; } } return object; } else if (valuep->format == vpiOctStrVal) { int chars = (vop->varp()->packed().elements() + 2) / 3; int bytes = VL_BYTES_I(vop->varp()->packed().elements()); int len = strlen(valuep->value.str); CData* datap = (reinterpret_cast(vop->varDatap())); div_t idx; datap[0] = 0; // reset zero'th byte for (int i = 0; i < chars; ++i) { union { char byte[2]; short half; } val; idx = div(i * 3, 8); if (i < len) { // ignore illegal chars char digit = valuep->value.str[len - i - 1]; if (digit >= '0' && digit <= '7') { val.half = digit - '0'; } else { _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Non octal character '%c' in '%s' as value %s for %s", VL_FUNC, digit, valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); val.half = 0; } } else { val.half = 0; } // align octal character to position within vector, note that // the three bits may straddle a byte boundary so two byte wide // assignments are made to adjacent bytes - but not if the least // significant byte of the aligned value is the most significant // byte of the destination. val.half <<= idx.rem; datap[idx.quot] |= val.byte[0]; // or in value if ((idx.quot + 1) < bytes) { datap[idx.quot + 1] = val.byte[1]; // this also resets // all bits to 0 prior to or'ing above } } // mask off non-existent bits in the most significant byte if (idx.quot == (bytes - 1)) { datap[idx.quot] &= vop->mask_byte(idx.quot); } else if (idx.quot + 1 == (bytes - 1)) { datap[idx.quot + 1] &= vop->mask_byte(idx.quot + 1); } // zero off remaining top bytes for (int i = idx.quot + 2; i < bytes; ++i) datap[i] = 0; return object; } else if (valuep->format == vpiDecStrVal) { char remainder[16]; unsigned long long val; int success = sscanf(valuep->value.str, "%30llu%15s", &val, remainder); if (success < 1) { _VL_VPI_ERROR(__FILE__, __LINE__, "%s: Parsing failed for '%s' as value %s for %s", VL_FUNC, valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); return 0; } if (success > 1) { _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Trailing garbage '%s' in '%s' as value %s for %s", VL_FUNC, remainder, valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); } if (vop->varp()->vltype() == VLVT_UINT8) { *(reinterpret_cast(vop->varDatap())) = val & vop->mask(); return object; } else if (vop->varp()->vltype() == VLVT_UINT16) { *(reinterpret_cast(vop->varDatap())) = val & vop->mask(); return object; } else if (vop->varp()->vltype() == VLVT_UINT32) { *(reinterpret_cast(vop->varDatap())) = val & vop->mask(); return object; } else if (vop->varp()->vltype() == VLVT_UINT64) { *(reinterpret_cast(vop->varDatap())) = val; (reinterpret_cast(vop->varDatap()))[1] &= vop->mask(); return object; } } else if (valuep->format == vpiHexStrVal) { int chars = (vop->varp()->packed().elements() + 3) >> 2; CData* datap = (reinterpret_cast(vop->varDatap())); char* val = valuep->value.str; // skip hex ident if one is detected at the start of the string if (val[0] == '0' && (val[1] == 'x' || val[1] == 'X')) val += 2; int len = strlen(val); for (int i = 0; i < chars; ++i) { char hex; // compute hex digit value if (i < len) { char digit = val[len - i - 1]; if (digit >= '0' && digit <= '9') { hex = digit - '0'; } else if (digit >= 'a' && digit <= 'f') { hex = digit - 'a' + 10; } else if (digit >= 'A' && digit <= 'F') { hex = digit - 'A' + 10; } else { _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Non hex character '%c' in '%s' as value %s for %s", VL_FUNC, digit, valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); hex = 0; } } else { hex = 0; } // assign hex digit value to destination if (i & 1) { datap[i >> 1] |= hex << 4; } else { datap[i >> 1] = hex; // this also resets all // bits to 0 prior to or'ing above of the msb } } // apply bit mask to most significant byte datap[(chars - 1) >> 1] &= vop->mask_byte((chars - 1) >> 1); return object; } else if (valuep->format == vpiStringVal) { int bytes = VL_BYTES_I(vop->varp()->packed().elements()); int len = strlen(valuep->value.str); CData* datap = (reinterpret_cast(vop->varDatap())); for (int i = 0; i < bytes; ++i) { // prepend with 0 values before placing string the least significant bytes datap[i] = (i < len) ? valuep->value.str[len - i - 1] : 0; } return object; } else if (valuep->format == vpiIntVal) { if (vop->varp()->vltype() == VLVT_UINT8) { *(reinterpret_cast(vop->varDatap())) = vop->mask() & valuep->value.integer; return object; } else if (vop->varp()->vltype() == VLVT_UINT16) { *(reinterpret_cast(vop->varDatap())) = vop->mask() & valuep->value.integer; return object; } else if (vop->varp()->vltype() == VLVT_UINT32) { *(reinterpret_cast(vop->varDatap())) = vop->mask() & valuep->value.integer; return object; } } _VL_VPI_ERROR(__FILE__, __LINE__, "%s: Unsupported format (%s) as requested for %s", VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); return NULL; } else if (VerilatedVpioParam* vop = VerilatedVpioParam::castp(object)) { _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Ignoring vpi_put_value to vpiParameter: %s", VL_FUNC, vop->fullname()); return 0; } else if (VerilatedVpioConst* vop = VerilatedVpioConst::castp(object)) { _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Ignoring vpi_put_value to vpiConstant: %s", VL_FUNC, vop->fullname()); return 0; } _VL_VPI_ERROR(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p)", VL_FUNC, object); return NULL; } void vpi_get_value_array(vpiHandle /*object*/, p_vpi_arrayvalue /*arrayvalue_p*/, PLI_INT32* /*index_p*/, PLI_UINT32 /*num*/) { _VL_VPI_UNIMP(); } void vpi_put_value_array(vpiHandle /*object*/, p_vpi_arrayvalue /*arrayvalue_p*/, PLI_INT32* /*index_p*/, PLI_UINT32 /*num*/) { _VL_VPI_UNIMP(); } // time processing void vpi_get_time(vpiHandle object, p_vpi_time time_p) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); // cppcheck-suppress nullPointer if (VL_UNLIKELY(!time_p)) { _VL_VPI_WARNING(__FILE__, __LINE__, "Ignoring vpi_get_time with NULL value pointer"); return; } if (time_p->type == vpiSimTime) { QData qtime = VL_TIME_Q(); WData itime[2]; VL_SET_WQ(itime, qtime); time_p->low = itime[0]; time_p->high = itime[1]; return; } else if (time_p->type == vpiScaledRealTime) { double dtime = VL_TIME_D(); if (VerilatedVpioScope* vop = VerilatedVpioScope::castp(object)) { int scalePow10 = Verilated::timeprecision() - vop->scopep()->timeunit(); double scale = vl_time_multiplier(scalePow10); // e.g. 0.0001 dtime *= scale; } time_p->real = dtime; return; } _VL_VPI_ERROR(__FILE__, __LINE__, "%s: Unsupported type (%d)", VL_FUNC, time_p->type); } // I/O routines PLI_UINT32 vpi_mcd_open(PLI_BYTE8* filenamep) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); return VL_FOPEN_NN(filenamep, "wb"); } PLI_UINT32 vpi_mcd_close(PLI_UINT32 mcd) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); VL_FCLOSE_I(mcd); return 0; } PLI_BYTE8* vpi_mcd_name(PLI_UINT32 /*mcd*/) { _VL_VPI_UNIMP(); return 0; } PLI_INT32 vpi_mcd_printf(PLI_UINT32 mcd, PLI_BYTE8* formatp, ...) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); va_list ap; va_start(ap, formatp); int chars = vpi_mcd_vprintf(mcd, formatp, ap); va_end(ap); return chars; } PLI_INT32 vpi_printf(PLI_BYTE8* formatp, ...) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); va_list ap; va_start(ap, formatp); int chars = vpi_vprintf(formatp, ap); va_end(ap); return chars; } PLI_INT32 vpi_vprintf(PLI_BYTE8* formatp, va_list ap) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); return VL_VPRINTF(formatp, ap); } PLI_INT32 vpi_mcd_vprintf(PLI_UINT32 mcd, PLI_BYTE8* format, va_list ap) { VerilatedVpiImp::assertOneCheck(); FILE* fp = VL_CVT_I_FP(mcd); _VL_VPI_ERROR_RESET(); // cppcheck-suppress nullPointer if (VL_UNLIKELY(!fp)) return 0; int chars = vfprintf(fp, format, ap); return chars; } PLI_INT32 vpi_flush(void) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); Verilated::runFlushCallbacks(); return 0; } PLI_INT32 vpi_mcd_flush(PLI_UINT32 mcd) { VerilatedVpiImp::assertOneCheck(); FILE* fp = VL_CVT_I_FP(mcd); _VL_VPI_ERROR_RESET(); if (VL_UNLIKELY(!fp)) return 1; fflush(fp); return 0; } // utility routines PLI_INT32 vpi_compare_objects(vpiHandle /*object1*/, vpiHandle /*object2*/) { _VL_VPI_UNIMP(); return 0; } PLI_INT32 vpi_chk_error(p_vpi_error_info error_info_p) { // executing vpi_chk_error does not reset error // error_info_p can be NULL, so only return level in that case VerilatedVpiImp::assertOneCheck(); p_vpi_error_info _error_info_p = VerilatedVpiImp::error_info()->getError(); if (error_info_p && _error_info_p) *error_info_p = *_error_info_p; if (!_error_info_p) return 0; // no error occured return _error_info_p->level; // return error severity level } PLI_INT32 vpi_free_object(vpiHandle object) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); return vpi_release_handle(object); // Deprecated } PLI_INT32 vpi_release_handle(vpiHandle object) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_release_handle %p\n", object);); VerilatedVpiImp::assertOneCheck(); VerilatedVpio* vop = VerilatedVpio::castp(object); _VL_VPI_ERROR_RESET(); if (VL_UNLIKELY(!vop)) return 0; vpi_remove_cb(object); // May not be a callback, but that's ok VL_DO_DANGLING(delete vop, vop); return 1; } PLI_INT32 vpi_get_vlog_info(p_vpi_vlog_info vlog_info_p) VL_MT_SAFE { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); vlog_info_p->argc = Verilated::getCommandArgs()->argc; vlog_info_p->argv = const_cast(Verilated::getCommandArgs()->argv); vlog_info_p->product = const_cast(Verilated::productName()); vlog_info_p->version = const_cast(Verilated::productVersion()); return 1; } // routines added with 1364-2001 PLI_INT32 vpi_get_data(PLI_INT32 /*id*/, PLI_BYTE8* /*dataLoc*/, PLI_INT32 /*numOfBytes*/) { _VL_VPI_UNIMP(); return 0; } PLI_INT32 vpi_put_data(PLI_INT32 /*id*/, PLI_BYTE8* /*dataLoc*/, PLI_INT32 /*numOfBytes*/) { _VL_VPI_UNIMP(); return 0; } void* vpi_get_userdata(vpiHandle /*obj*/) { _VL_VPI_UNIMP(); return 0; } PLI_INT32 vpi_put_userdata(vpiHandle /*obj*/, void* /*userdata*/) { _VL_VPI_UNIMP(); return 0; } PLI_INT32 vpi_control(PLI_INT32 operation, ...) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_control %d\n", operation);); VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); switch (operation) { case vpiFinish: { VL_FINISH_MT("", 0, "*VPI*"); return 1; } case vpiStop: { VL_STOP_MT("", 0, "*VPI*"); return 1; // LCOV_EXCL_LINE } default: { _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Unsupported type %s, ignoring", VL_FUNC, VerilatedVpiError::strFromVpiProp(operation)); return 0; } } } vpiHandle vpi_handle_by_multi_index(vpiHandle /*obj*/, PLI_INT32 /*num_index*/, PLI_INT32* /*index_array*/) { _VL_VPI_UNIMP(); return 0; } verilator-4.038/include/verilated_sc.h0000664000177100017500000000346513702133367017771 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: Common include for all Verilated SystemC files /// /// This file is included automatically by Verilator at the top of /// all SystemC files it generates. /// /// Code available from: https://verilator.org /// //************************************************************************* #ifndef _VERILATED_SC_H_ #define _VERILATED_SC_H_ 1 ///< Header Guard #include "verilatedos.h" #include "systemc.h" //============================================================================= // VL_SC_BV_DATAP // We want to get a pointer to m_data in the sc_bv_base class, // but it is protected. So make an exposing class, then use // cast magic to get at it. Saves patching get_datap in SystemC. // This class is thread safe (though most of SystemC is not). #define VL_SC_BV_DATAP(bv) (VlScBvExposer::sp_datap(bv)) class VlScBvExposer : public sc_bv_base { public: static const vluint32_t* sp_datap(const sc_bv_base& base) VL_MT_SAFE { return static_cast(&base)->sp_datatp(); } const vluint32_t* sp_datatp() const { return reinterpret_cast(m_data); } // Above reads this protected element in sc_bv_base: // sc_digit* m_data; // data array }; //========================================================================= #endif // Guard verilator-4.038/include/verilated_vcd_c.h0000664000177100017500000004161613702133367020442 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief C++ Tracing in VCD Format /// //============================================================================= // SPDIFF_OFF #ifndef _VERILATED_VCD_C_H_ #define _VERILATED_VCD_C_H_ 1 #include "verilated.h" #include "verilated_trace.h" #include #include #include class VerilatedVcd; // SPDIFF_ON //============================================================================= // VerilatedFile /// File handling routines, which can be overrode for e.g. socket I/O class VerilatedVcdFile { private: int m_fd; ///< File descriptor we're writing to public: // METHODS VerilatedVcdFile() : m_fd(0) {} virtual ~VerilatedVcdFile() {} virtual bool open(const std::string& name) VL_MT_UNSAFE; virtual void close() VL_MT_UNSAFE; virtual ssize_t write(const char* bufp, ssize_t len) VL_MT_UNSAFE; }; //============================================================================= // VerilatedVcd /// Base class to create a Verilator VCD dump /// This is an internally used class - see VerilatedVcdC for what to call from applications class VerilatedVcd : public VerilatedTrace { private: // Give the superclass access to private bits (to avoid virtual functions) friend class VerilatedTrace; //========================================================================= // VCD specific internals VerilatedVcdFile* m_filep; ///< File we're writing to bool m_fileNewed; ///< m_filep needs destruction bool m_isOpen; ///< True indicates open file bool m_evcd; ///< True for evcd format std::string m_filename; ///< Filename we're writing to (if open) vluint64_t m_rolloverMB; ///< MB of file size to rollover at int m_modDepth; ///< Depth of module hierarchy char* m_wrBufp; ///< Output buffer char* m_wrFlushp; ///< Output buffer flush trigger location char* m_writep; ///< Write pointer into output buffer vluint64_t m_wrChunkSize; ///< Output buffer size vluint64_t m_wroteBytes; ///< Number of bytes written to this file std::vector m_suffixes; ///< VCD line end string codes + metadata const char* m_suffixesp; ///< Pointer to first element of above typedef std::map NameMap; NameMap* m_namemapp; ///< List of names for the header void bufferResize(vluint64_t minsize); void bufferFlush() VL_MT_UNSAFE_ONE; inline void bufferCheck() { // Flush the write buffer if there's not enough space left for new information // We only call this once per vector, so we need enough slop for a very wide "b###" line if (VL_UNLIKELY(m_writep > m_wrFlushp)) { bufferFlush(); } } void closePrev(); void closeErr(); void openNext(); void makeNameMap(); void deleteNameMap(); void printIndent(int level_change); void printStr(const char* str); void printQuad(vluint64_t n); void printTime(vluint64_t timeui); void declare(vluint32_t code, const char* name, const char* wirep, bool array, int arraynum, bool tri, bool bussed, int msb, int lsb); void dumpHeader(); char* writeCode(char* writep, vluint32_t code); void finishLine(vluint32_t code, char* writep); // CONSTRUCTORS VL_UNCOPYABLE(VerilatedVcd); protected: //========================================================================= // Implementation of VerilatedTrace interface // Implementations of protected virtual methods for VerilatedTrace void emitTimeChange(vluint64_t timeui) VL_OVERRIDE; // Hooks called from VerilatedTrace bool preFullDump() VL_OVERRIDE { return isOpen(); } bool preChangeDump() VL_OVERRIDE; // Implementations of duck-typed methods for VerilatedTrace. These are // called from only one place (namely full*) so always inline them. inline void emitBit(vluint32_t code, CData newval); inline void emitCData(vluint32_t code, CData newval, int bits); inline void emitSData(vluint32_t code, SData newval, int bits); inline void emitIData(vluint32_t code, IData newval, int bits); inline void emitQData(vluint32_t code, QData newval, int bits); inline void emitWData(vluint32_t code, const WData* newvalp, int bits); inline void emitDouble(vluint32_t code, double newval); public: //========================================================================= // External interface to client code explicit VerilatedVcd(VerilatedVcdFile* filep = NULL); ~VerilatedVcd(); // ACCESSORS /// Set size in megabytes after which new file should be created void rolloverMB(vluint64_t rolloverMB) { m_rolloverMB = rolloverMB; } // METHODS /// Open the file; call isOpen() to see if errors void open(const char* filename) VL_MT_UNSAFE_ONE; /// Open next data-only file void openNext(bool incFilename) VL_MT_UNSAFE_ONE; /// Close the file void close() VL_MT_UNSAFE_ONE; /// Flush any remaining data to this file void flush() VL_MT_UNSAFE_ONE; /// Is file open? bool isOpen() const { return m_isOpen; } //========================================================================= // Internal interface to Verilator generated code void declBit(vluint32_t code, const char* name, bool array, int arraynum); void declBus(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); void declQuad(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); void declArray(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); void declDouble(vluint32_t code, const char* name, bool array, int arraynum); #ifdef VL_TRACE_VCD_OLD_API //========================================================================= // Note: These are only for testing for backward compatibility with foreign // code and is not used by Verilator. Do not use these as there is no // guarantee of functionality. void declTriBit(vluint32_t code, const char* name, bool array, int arraynum); void declTriBus(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); void declTriQuad(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); void declTriArray(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); void fullBit(vluint32_t* oldp, CData newval) { fullBit(oldp - this->oldp(0), newval); } void fullCData(vluint32_t* oldp, CData newval, int bits) { fullBus(oldp - this->oldp(0), newval, bits); } void fullSData(vluint32_t* oldp, SData newval, int bits) { fullBus(oldp - this->oldp(0), newval, bits); } void fullIData(vluint32_t* oldp, IData newval, int bits) { fullBus(oldp - this->oldp(0), newval, bits); } void fullQData(vluint32_t* oldp, QData newval, int bits) { fullQuad(oldp - this->oldp(0), newval, bits); } void fullWData(vluint32_t* oldp, const WData* newvalp, int bits) { fullArray(oldp - this->oldp(0), newvalp, bits); } void fullDouble(vluint32_t* oldp, double newval) { fullDouble(oldp - this->oldp(0), newval); } inline void chgBit(vluint32_t* oldp, CData newval) { chgBit(oldp - this->oldp(0), newval); } inline void chgCData(vluint32_t* oldp, CData newval, int bits) { chgBus(oldp - this->oldp(0), newval, bits); } inline void chgSData(vluint32_t* oldp, SData newval, int bits) { chgBus(oldp - this->oldp(0), newval, bits); } inline void chgIData(vluint32_t* oldp, IData newval, int bits) { chgBus(oldp - this->oldp(0), newval, bits); } inline void chgQData(vluint32_t* oldp, QData newval, int bits) { chgQuad(oldp - this->oldp(0), newval, bits); } inline void chgWData(vluint32_t* oldp, const WData* newvalp, int bits) { chgArray(oldp - this->oldp(0), newvalp, bits); } inline void chgDouble(vluint32_t* oldp, double newval) { chgDouble(oldp - this->oldp(0), newval); } /// Inside dumping routines, dump one signal, faster when not inlined /// due to code size reduction. void fullBit(vluint32_t code, const vluint32_t newval); void fullBus(vluint32_t code, const vluint32_t newval, int bits); void fullQuad(vluint32_t code, const vluint64_t newval, int bits); void fullArray(vluint32_t code, const vluint32_t* newvalp, int bits); void fullArray(vluint32_t code, const vluint64_t* newvalp, int bits); void fullTriBit(vluint32_t code, const vluint32_t newval, const vluint32_t newtri); void fullTriBus(vluint32_t code, const vluint32_t newval, const vluint32_t newtri, int bits); void fullTriQuad(vluint32_t code, const vluint64_t newval, const vluint64_t newtri, int bits); void fullTriArray(vluint32_t code, const vluint32_t* newvalp, const vluint32_t* newtrip, int bits); void fullDouble(vluint32_t code, const double newval); /// Inside dumping routines, dump one signal if it has changed. /// We do want to inline these to avoid calls when the value did not change. inline void chgBit(vluint32_t code, const vluint32_t newval) { vluint32_t diff = oldp(code)[0] ^ newval; if (VL_UNLIKELY(diff)) fullBit(code, newval); } inline void chgBus(vluint32_t code, const vluint32_t newval, int bits) { vluint32_t diff = oldp(code)[0] ^ newval; if (VL_UNLIKELY(diff)) { if (VL_UNLIKELY(bits == 32 || (diff & ((1U << bits) - 1)))) { fullBus(code, newval, bits); } } } inline void chgQuad(vluint32_t code, const vluint64_t newval, int bits) { vluint64_t diff = (*(reinterpret_cast(oldp(code)))) ^ newval; if (VL_UNLIKELY(diff)) { if (VL_UNLIKELY(bits == 64 || (diff & ((1ULL << bits) - 1)))) { fullQuad(code, newval, bits); } } } inline void chgArray(vluint32_t code, const vluint32_t* newvalp, int bits) { for (int word = 0; word < (((bits - 1) / 32) + 1); ++word) { if (VL_UNLIKELY(oldp(code)[word] ^ newvalp[word])) { fullArray(code, newvalp, bits); return; } } } inline void chgArray(vluint32_t code, const vluint64_t* newvalp, int bits) { for (int word = 0; word < (((bits - 1) / 64) + 1); ++word) { if (VL_UNLIKELY(*(reinterpret_cast(oldp(code + 2 * word))) ^ newvalp[word])) { fullArray(code, newvalp, bits); return; } } } inline void chgTriBit(vluint32_t code, const vluint32_t newval, const vluint32_t newtri) { vluint32_t diff = ((oldp(code)[0] ^ newval) | (oldp(code)[1] ^ newtri)); if (VL_UNLIKELY(diff)) { // Verilator 3.510 and newer provide clean input, so the below // is only for back compatibility if (VL_UNLIKELY(diff & 1)) { // Change after clean? fullTriBit(code, newval, newtri); } } } inline void chgTriBus(vluint32_t code, const vluint32_t newval, const vluint32_t newtri, int bits) { vluint32_t diff = ((oldp(code)[0] ^ newval) | (oldp(code)[1] ^ newtri)); if (VL_UNLIKELY(diff)) { if (VL_UNLIKELY(bits == 32 || (diff & ((1U << bits) - 1)))) { fullTriBus(code, newval, newtri, bits); } } } inline void chgTriQuad(vluint32_t code, const vluint64_t newval, const vluint64_t newtri, int bits) { vluint64_t diff = (((*(reinterpret_cast(oldp(code)))) ^ newval) | ((*(reinterpret_cast(oldp(code + 1)))) ^ newtri)); if (VL_UNLIKELY(diff)) { if (VL_UNLIKELY(bits == 64 || (diff & ((1ULL << bits) - 1)))) { fullTriQuad(code, newval, newtri, bits); } } } inline void chgTriArray(vluint32_t code, const vluint32_t* newvalp, const vluint32_t* newtrip, int bits) { for (int word = 0; word < (((bits - 1) / 32) + 1); ++word) { if (VL_UNLIKELY((oldp(code)[word * 2] ^ newvalp[word]) | (oldp(code)[word * 2 + 1] ^ newtrip[word]))) { fullTriArray(code, newvalp, newtrip, bits); return; } } } inline void chgDouble(vluint32_t code, const double newval) { // cppcheck-suppress invalidPointerCast if (VL_UNLIKELY((*(reinterpret_cast(oldp(code)))) != newval)) { fullDouble(code, newval); } } // METHODS // Old/standalone API only void evcd(bool flag) { m_evcd = flag; } #endif // VL_TRACE_VCD_OLD_API }; // Declare specializations here they are used in VerilatedVcdC just below template <> void VerilatedTrace::dump(vluint64_t timeui); template <> void VerilatedTrace::set_time_unit(const char* unitp); template <> void VerilatedTrace::set_time_unit(const std::string& unit); template <> void VerilatedTrace::set_time_resolution(const char* unitp); template <> void VerilatedTrace::set_time_resolution(const std::string& unit); //============================================================================= // VerilatedVcdC /// Create a VCD dump file in C standalone (no SystemC) simulations. /// Also derived for use in SystemC simulations. /// Thread safety: Unless otherwise indicated, every function is VL_MT_UNSAFE_ONE class VerilatedVcdC { VerilatedVcd m_sptrace; ///< Trace file being created // CONSTRUCTORS VL_UNCOPYABLE(VerilatedVcdC); public: explicit VerilatedVcdC(VerilatedVcdFile* filep = NULL) : m_sptrace(filep) {} ~VerilatedVcdC() { close(); } /// Routines can only be called from one thread; allow next call from different thread void changeThread() { spTrace()->changeThread(); } public: // ACCESSORS /// Is file open? bool isOpen() const { return m_sptrace.isOpen(); } // METHODS /// Open a new VCD file /// This includes a complete header dump each time it is called, /// just as if this object was deleted and reconstructed. void open(const char* filename) VL_MT_UNSAFE_ONE { m_sptrace.open(filename); } /// Continue a VCD dump by rotating to a new file name /// The header is only in the first file created, this allows /// "cat" to be used to combine the header plus any number of data files. void openNext(bool incFilename = true) VL_MT_UNSAFE_ONE { m_sptrace.openNext(incFilename); } /// Set size in megabytes after which new file should be created void rolloverMB(size_t rolloverMB) { m_sptrace.rolloverMB(rolloverMB); } /// Close dump void close() VL_MT_UNSAFE_ONE { m_sptrace.close(); } /// Flush dump void flush() VL_MT_UNSAFE_ONE { m_sptrace.flush(); } /// Write one cycle of dump data void dump(vluint64_t timeui) { m_sptrace.dump(timeui); } /// Write one cycle of dump data - backward compatible and to reduce /// conversion warnings. It's better to use a vluint64_t time instead. void dump(double timestamp) { dump(static_cast(timestamp)); } void dump(vluint32_t timestamp) { dump(static_cast(timestamp)); } void dump(int timestamp) { dump(static_cast(timestamp)); } /// Set time units (s/ms, defaults to ns) /// For Verilated models, these propage from the Verilated default --timeunit void set_time_unit(const char* unit) { m_sptrace.set_time_unit(unit); } void set_time_unit(const std::string& unit) { m_sptrace.set_time_unit(unit); } /// Set time resolution (s/ms, defaults to ns) /// For Verilated models, these propage from the Verilated default --timeunit void set_time_resolution(const char* unit) { m_sptrace.set_time_resolution(unit); } void set_time_resolution(const std::string& unit) { m_sptrace.set_time_resolution(unit); } /// Internal class access inline VerilatedVcd* spTrace() { return &m_sptrace; } #ifdef VL_TRACE_VCD_OLD_API //========================================================================= // Note: These are only for testing for backward compatibility with foreign // code and is not used by Verilator. Do not use these as there is no // guarantee of functionality. /// Use evcd format void evcd(bool flag) VL_MT_UNSAFE_ONE { m_sptrace.evcd(flag); } #endif }; #endif // guard verilator-4.038/include/verilated_save.h0000664000177100017500000002460013702133367020314 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2000-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Save-restore serialization of verilated modules /// //============================================================================= #ifndef _VERILATED_SAVE_C_H_ #define _VERILATED_SAVE_C_H_ 1 #include "verilatedos.h" #include "verilated_heavy.h" #include //============================================================================= // VerilatedSerialize - convert structures to a stream representation // This class is not thread safe, it must be called by a single thread class VerilatedSerialize { protected: // MEMBERS // For speed, keep m_cp as the first member of this structure vluint8_t* m_cp; ///< Current pointer into m_bufp buffer vluint8_t* m_bufp; ///< Output buffer bool m_isOpen; ///< True indicates open file/stream std::string m_filename; ///< Filename, for error messages VerilatedAssertOneThread m_assertOne; ///< Assert only called from single thread inline static size_t bufferSize() { return 256 * 1024; } // See below for slack calculation inline static size_t bufferInsertSize() { return 16 * 1024; } void header() VL_MT_UNSAFE_ONE; void trailer() VL_MT_UNSAFE_ONE; // CONSTRUCTORS VL_UNCOPYABLE(VerilatedSerialize); public: VerilatedSerialize() { m_isOpen = false; m_bufp = new vluint8_t[bufferSize()]; m_cp = m_bufp; } virtual ~VerilatedSerialize() { close(); if (m_bufp) VL_DO_CLEAR(delete m_bufp, m_bufp = NULL); } // METHODS bool isOpen() const { return m_isOpen; } std::string filename() const { return m_filename; } virtual void close() VL_MT_UNSAFE_ONE { flush(); } virtual void flush() VL_MT_UNSAFE_ONE {} inline VerilatedSerialize& write(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { const vluint8_t* __restrict dp = (const vluint8_t* __restrict)datap; while (size) { bufferCheck(); size_t blk = size; if (blk > bufferInsertSize()) blk = bufferInsertSize(); const vluint8_t* __restrict maxp = dp + blk; for (; dp < maxp; *m_cp++ = *dp++) {} size -= blk; } return *this; // For function chaining } private: VerilatedSerialize& bufferCheck() VL_MT_UNSAFE_ONE { // Flush the write buffer if there's not enough space left for new information // We only call this once per vector, so we need enough slop for a very wide "b###" line if (VL_UNLIKELY(m_cp > (m_bufp + (bufferSize() - bufferInsertSize())))) flush(); return *this; // For function chaining } }; //============================================================================= // VerilatedDeserial - load structures from a stream representation // This class is not thread safe, it must be called by a single thread class VerilatedDeserialize { protected: // MEMBERS // For speed, keep m_cp as the first member of this structure vluint8_t* m_cp; ///< Current pointer into m_bufp buffer vluint8_t* m_bufp; ///< Output buffer vluint8_t* m_endp; ///< Last valid byte in m_bufp buffer bool m_isOpen; ///< True indicates open file/stream std::string m_filename; ///< Filename, for error messages VerilatedAssertOneThread m_assertOne; ///< Assert only called from single thread inline static size_t bufferSize() { return 256 * 1024; } // See below for slack calculation inline static size_t bufferInsertSize() { return 16 * 1024; } virtual void fill() = 0; void header() VL_MT_UNSAFE_ONE; void trailer() VL_MT_UNSAFE_ONE; // CONSTRUCTORS VL_UNCOPYABLE(VerilatedDeserialize); public: VerilatedDeserialize() { m_isOpen = false; m_bufp = new vluint8_t[bufferSize()]; m_cp = m_bufp; m_endp = NULL; } virtual ~VerilatedDeserialize() { close(); if (m_bufp) VL_DO_CLEAR(delete m_bufp, m_bufp = NULL); } // METHODS bool isOpen() const { return m_isOpen; } std::string filename() const { return m_filename; } virtual void close() VL_MT_UNSAFE_ONE { flush(); } virtual void flush() VL_MT_UNSAFE_ONE {} inline VerilatedDeserialize& read(void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { vluint8_t* __restrict dp = static_cast(datap); while (size) { bufferCheck(); size_t blk = size; if (blk > bufferInsertSize()) blk = bufferInsertSize(); const vluint8_t* __restrict maxp = dp + blk; for (; dp < maxp; *dp++ = *m_cp++) {} size -= blk; } return *this; // For function chaining } // Read a datum and compare with expected value VerilatedDeserialize& readAssert(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE; VerilatedDeserialize& readAssert(vluint64_t data) VL_MT_UNSAFE_ONE { return readAssert(&data, sizeof(data)); } private: bool readDiffers(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE; VerilatedDeserialize& bufferCheck() VL_MT_UNSAFE_ONE { // Flush the write buffer if there's not enough space left for new information // We only call this once per vector, so we need enough slop for a very wide "b###" line if (VL_UNLIKELY((m_cp + bufferInsertSize()) > m_endp)) fill(); return *this; // For function chaining } }; //============================================================================= // VerilatedSave - serialize to a file // This class is not thread safe, it must be called by a single thread class VerilatedSave : public VerilatedSerialize { private: int m_fd; ///< File descriptor we're writing to public: // CONSTRUCTORS VerilatedSave() : m_fd(-1) {} virtual ~VerilatedSave() VL_OVERRIDE { close(); } // METHODS /// Open the file; call isOpen() to see if errors void open(const char* filenamep) VL_MT_UNSAFE_ONE; void open(const std::string& filename) VL_MT_UNSAFE_ONE { open(filename.c_str()); } virtual void close() VL_OVERRIDE VL_MT_UNSAFE_ONE; virtual void flush() VL_OVERRIDE VL_MT_UNSAFE_ONE; }; //============================================================================= // VerilatedRestore - deserialize from a file // This class is not thread safe, it must be called by a single thread class VerilatedRestore : public VerilatedDeserialize { private: int m_fd; ///< File descriptor we're writing to public: // CONSTRUCTORS VerilatedRestore() : m_fd(-1) {} virtual ~VerilatedRestore() VL_OVERRIDE { close(); } // METHODS /// Open the file; call isOpen() to see if errors void open(const char* filenamep) VL_MT_UNSAFE_ONE; void open(const std::string& filename) VL_MT_UNSAFE_ONE { open(filename.c_str()); } virtual void close() VL_OVERRIDE VL_MT_UNSAFE_ONE; virtual void flush() VL_OVERRIDE VL_MT_UNSAFE_ONE {} virtual void fill() VL_OVERRIDE VL_MT_UNSAFE_ONE; }; //============================================================================= inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint64_t& rhs) { return os.write(&rhs, sizeof(rhs)); } inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint64_t& rhs) { return os.read(&rhs, sizeof(rhs)); } inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint32_t& rhs) { return os.write(&rhs, sizeof(rhs)); } inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint32_t& rhs) { return os.read(&rhs, sizeof(rhs)); } inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint16_t& rhs) { return os.write(&rhs, sizeof(rhs)); } inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint16_t& rhs) { return os.read(&rhs, sizeof(rhs)); } inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint8_t& rhs) { return os.write(&rhs, sizeof(rhs)); } inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint8_t& rhs) { return os.read(&rhs, sizeof(rhs)); } inline VerilatedSerialize& operator<<(VerilatedSerialize& os, bool& rhs) { return os.write(&rhs, sizeof(rhs)); } inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, bool& rhs) { return os.read(&rhs, sizeof(rhs)); } inline VerilatedSerialize& operator<<(VerilatedSerialize& os, double& rhs) { return os.write(&rhs, sizeof(rhs)); } inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, double& rhs) { return os.read(&rhs, sizeof(rhs)); } inline VerilatedSerialize& operator<<(VerilatedSerialize& os, float& rhs) { return os.write(&rhs, sizeof(rhs)); } inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, float& rhs) { return os.read(&rhs, sizeof(rhs)); } inline VerilatedSerialize& operator<<(VerilatedSerialize& os, std::string& rhs) { vluint32_t len = rhs.length(); os << len; return os.write(rhs.data(), len); } inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, std::string& rhs) { vluint32_t len = 0; os >> len; rhs.resize(len); return os.read((void*)rhs.data(), len); } template VerilatedSerialize& operator<<(VerilatedSerialize& os, VlAssocArray& rhs) { os << rhs.atDefault(); vluint32_t len = rhs.size(); os << len; for (typename VlAssocArray::const_iterator it = rhs.begin(); it != rhs.end(); ++it) { T_Key index = it->first; // Copy to get around const_iterator T_Value value = it->second; os << index << value; } return os; } template VerilatedDeserialize& operator>>(VerilatedDeserialize& os, VlAssocArray& rhs) { os >> rhs.atDefault(); vluint32_t len = 0; os >> len; rhs.clear(); for (vluint32_t i = 0; i < len; ++i) { T_Key index; T_Value value; os >> index; os >> value; rhs.at(index) = value; } return os; } #endif // Guard verilator-4.038/include/verilated_threads.h0000664000177100017500000002366513702133367021022 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2012-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Thread pool and profiling for Verilated modules /// //============================================================================= #ifndef _VERILATED_THREADS_H_ #define _VERILATED_THREADS_H_ #include "verilatedos.h" #include "verilated.h" // for VerilatedMutex and clang annotations #include #include #include // clang-format off #if defined(__linux) # include // For sched_getcpu() #endif #if defined(__APPLE__) # include // For __cpuid_count() #endif // clang-format on // VlMTaskVertex and VlThreadpool will work with multiple symbol table types. // Since the type is opaque to VlMTaskVertex and VlThreadPool, represent it // as a void* here. typedef void* VlThrSymTab; typedef void (*VlExecFnp)(bool, VlThrSymTab); /// Track dependencies for a single MTask. class VlMTaskVertex { // MEMBERS static std::atomic s_yields; // Statistics // On even cycles, _upstreamDepsDone increases as upstream // dependencies complete. When it reaches _upstreamDepCount, // this MTaskVertex is ready. // // On odd cycles, _upstreamDepsDone decreases as upstream // dependencies complete, and when it reaches zero this MTaskVertex // is ready. // // An atomic is smaller than a mutex, and lock-free. // // (Why does the size of this class matter? If an mtask has many // downstream mtasks to notify, we hope these will pack into a // small number of cache lines to reduce the cost of pointer chasing // during done-notification. Nobody's quantified that cost though. // If we were really serious about shrinking this class, we could // use 16-bit types here...) std::atomic m_upstreamDepsDone; const vluint32_t m_upstreamDepCount; public: // CONSTRUCTORS // 'upstreamDepCount' is the number of upstream MTaskVertex's // that must notify this MTaskVertex before it will become ready // to run. explicit VlMTaskVertex(vluint32_t upstreamDepCount); ~VlMTaskVertex() {} static vluint64_t yields() { return s_yields; } static void yieldThread() { ++s_yields; // Statistics std::this_thread::yield(); } // Upstream mtasks must call this when they complete. // Returns true when the current MTaskVertex becomes ready to execute, // false while it's still waiting on more dependencies. inline bool signalUpstreamDone(bool evenCycle) { if (evenCycle) { vluint32_t upstreamDepsDone = 1 + m_upstreamDepsDone.fetch_add(1, std::memory_order_release); assert(upstreamDepsDone <= m_upstreamDepCount); return (upstreamDepsDone == m_upstreamDepCount); } else { vluint32_t upstreamDepsDone_prev = m_upstreamDepsDone.fetch_sub(1, std::memory_order_release); assert(upstreamDepsDone_prev > 0); return (upstreamDepsDone_prev == 1); } } inline bool areUpstreamDepsDone(bool evenCycle) const { vluint32_t target = evenCycle ? m_upstreamDepCount : 0; return m_upstreamDepsDone.load(std::memory_order_acquire) == target; } inline void waitUntilUpstreamDone(bool evenCycle) const { unsigned ct = 0; while (VL_UNLIKELY(!areUpstreamDepsDone(evenCycle))) { VL_CPU_RELAX(); ++ct; if (VL_UNLIKELY(ct > VL_LOCK_SPINS)) { ct = 0; yieldThread(); } } } }; // Profiling support class VlProfileRec { protected: friend class VlThreadPool; enum VlProfileE { TYPE_MTASK_RUN, TYPE_BARRIER }; VlProfileE m_type; // Record type vluint32_t m_mtaskId; // Mtask we're logging vluint32_t m_predictTime; // How long scheduler predicted would take vluint64_t m_startTime; // Tick at start of execution vluint64_t m_endTime; // Tick at end of execution unsigned m_cpu; // Execution CPU number (at start anyways) public: class Barrier {}; VlProfileRec() {} explicit VlProfileRec(Barrier) { m_type = TYPE_BARRIER; m_mtaskId = 0; m_predictTime = 0; m_startTime = 0; m_endTime = 0; m_cpu = getcpu(); } void startRecord(vluint64_t time, uint32_t mtask, uint32_t predict) { m_type = VlProfileRec::TYPE_MTASK_RUN; m_mtaskId = mtask; m_predictTime = predict; m_startTime = time; m_cpu = getcpu(); } void endRecord(vluint64_t time) { m_endTime = time; } static int getcpu() { // Return current executing CPU #if defined(__linux) return sched_getcpu(); #elif defined(__APPLE__) vluint32_t info[4]; __cpuid_count(1, 0, info[0], info[1], info[2], info[3]); // info[1] is EBX, bits 24-31 are APIC ID if ((info[3] & (1 << 9)) == 0) { return -1; // no APIC on chip } else { return (unsigned)info[1] >> 24; } #elif defined(_WIN32) return GetCurrentProcessorNumber(); #else return 0; #endif } }; class VlThreadPool; class VlWorkerThread { private: // TYPES struct ExecRec { VlExecFnp m_fnp; // Function to execute VlThrSymTab m_sym; // Symbol table to execute bool m_evenCycle; // Even/odd for flag alternation ExecRec() : m_fnp(NULL) , m_sym(NULL) , m_evenCycle(false) {} ExecRec(VlExecFnp fnp, bool evenCycle, VlThrSymTab sym) : m_fnp(fnp) , m_sym(sym) , m_evenCycle(evenCycle) {} }; // MEMBERS VerilatedMutex m_mutex; std::condition_variable_any m_cv; // Only notify the condition_variable if the worker is waiting bool m_waiting VL_GUARDED_BY(m_mutex); // Why a vector? We expect the pending list to be very short, typically // 0 or 1 or 2, so popping from the front shouldn't be // expensive. Revisit if we ever have longer queues... std::vector m_ready VL_GUARDED_BY(m_mutex); // Store the size atomically, so we can spin wait std::atomic m_ready_size; VlThreadPool* m_poolp; // Our associated thread pool bool m_profiling; // Is profiling enabled? std::atomic m_exiting; // Worker thread should exit std::thread m_cthread; // Underlying C++ thread record VL_UNCOPYABLE(VlWorkerThread); public: // CONSTRUCTORS explicit VlWorkerThread(VlThreadPool* poolp, bool profiling); ~VlWorkerThread(); // METHODS inline void dequeWork(ExecRec* workp) { // Spin for a while, waiting for new data for (int i = 0; i < VL_LOCK_SPINS; ++i) { if (VL_LIKELY(m_ready_size.load(std::memory_order_relaxed))) { // break; } VL_CPU_RELAX(); } VerilatedLockGuard lk(m_mutex); while (m_ready.empty()) { m_waiting = true; m_cv.wait(lk); } m_waiting = false; // As noted above this is inefficient if our ready list is ever // long (but it shouldn't be) *workp = m_ready.front(); m_ready.erase(m_ready.begin()); m_ready_size.fetch_sub(1, std::memory_order_relaxed); } inline void wakeUp() { addTask(nullptr, false, nullptr); } inline void addTask(VlExecFnp fnp, bool evenCycle, VlThrSymTab sym) { bool notify; { const VerilatedLockGuard lk(m_mutex); m_ready.emplace_back(fnp, evenCycle, sym); m_ready_size.fetch_add(1, std::memory_order_relaxed); notify = m_waiting; } if (notify) m_cv.notify_one(); } void workerLoop(); static void startWorker(VlWorkerThread* workerp); }; class VlThreadPool { // TYPES typedef std::vector ProfileTrace; typedef std::set ProfileSet; // MEMBERS std::vector m_workers; // our workers bool m_profiling; // is profiling enabled? // Support profiling -- we can append records of profiling events // to this vector with very low overhead, and then dump them out // later. This prevents the overhead of printf/malloc/IO from // corrupting the profiling data. It's super cheap to append // a VlProfileRec struct on the end of a pre-allocated vector; // this is the only cost we pay in real-time during a profiling cycle. static VL_THREAD_LOCAL ProfileTrace* t_profilep; ProfileSet m_allProfiles VL_GUARDED_BY(m_mutex); VerilatedMutex m_mutex; public: // CONSTRUCTORS // Construct a thread pool with 'nThreads' dedicated threads. The thread // pool will create these threads and make them available to execute tasks // via this->workerp(index)->addTask(...) VlThreadPool(int nThreads, bool profiling); ~VlThreadPool(); // METHODS inline int numThreads() const { return m_workers.size(); } inline VlWorkerThread* workerp(int index) { assert(index >= 0); assert(index < m_workers.size()); return m_workers[index]; } inline VlProfileRec* profileAppend() { t_profilep->emplace_back(); return &(t_profilep->back()); } void profileAppendAll(const VlProfileRec& rec); void profileDump(const char* filenamep, vluint64_t ticksElapsed); // In profiling mode, each executing thread must call // this once to setup profiling state: void setupProfilingClientThread(); void tearDownProfilingClientThread(); private: VL_UNCOPYABLE(VlThreadPool); }; #endif verilator-4.038/include/verilated_intrinsics.h0000664000177100017500000000271613702133367021547 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: Common include for target specific intrinsics. /// /// Code using machine specific intrinsics for optimization should /// include this header rather than directly including he target /// specific headers. We provide macros to check for availability /// of instruction sets, and a common mechanism to disable them. /// //************************************************************************* #ifndef _VERILATED_INTRINSICS_H_ #define _VERILATED_INTRINSICS_H_ 1 ///< Header Guard // clang-format off // Use VL_DISABLE_INTRINSICS to disable all intrinsics based optimization #if !defined(VL_DISABLE_INTRINSICS) && !defined(VL_PORTABLE_ONLY) # if defined(__SSE2__) && !defined(VL_DISABLE_SSE2) # define VL_HAVE_SSE2 1 # include # endif # if defined(__AVX2__) && defined(VL_HAVE_SSE2) && !defined(VL_DISABLE_AVX2) # define VL_HAVE_AVX2 1 # include # endif #endif // clang-format on #endif // Guard verilator-4.038/include/verilated_sym_props.h0000664000177100017500000002251013702133367021407 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// /// \file /// \brief Verilator: Include to provide information about symbol inspection /// /// This file is for inclusion by internal files that need to inspect /// specific symbols. /// /// User routines wanting to inspect the symbol table should use /// verilated_syms.h instead. /// /// These classes are thread safe, and read only. /// /// Code available from: https://verilator.org /// //************************************************************************* #ifndef _VERILATED_SYM_PROPS_H_ #define _VERILATED_SYM_PROPS_H_ 1 ///< Header Guard #include "verilatedos.h" #include //=========================================================================== /// Verilator range /// Thread safety: Assume is constructed only with model, then any number of readers // See also V3Ast::VNumRange class VerilatedRange { int m_left; int m_right; protected: friend class VerilatedVarProps; friend class VerilatedScope; VerilatedRange() : m_left(0) , m_right(0) {} VerilatedRange(int left, int right) : m_left(left) , m_right(right) {} void init(int left, int right) { m_left = left; m_right = right; } public: ~VerilatedRange() {} int left() const { return m_left; } int right() const { return m_right; } int low() const { return (m_left < m_right) ? m_left : m_right; } int high() const { return (m_left > m_right) ? m_left : m_right; } int elements() const { return (VL_LIKELY(m_left >= m_right) ? (m_left - m_right + 1) : (m_right - m_left + 1)); } int increment() const { return (m_left >= m_right) ? 1 : -1; } }; //=========================================================================== /// Verilator variable /// Thread safety: Assume is constructed only with model, then any number of readers class VerilatedVarProps { // TYPES enum { MAGIC = 0xddc4f829 }; // MEMBERS const vluint32_t m_magic; // Magic number const VerilatedVarType m_vltype; // Data type const VerilatedVarFlags m_vlflags; // Direction const int m_pdims; // Packed dimensions const int m_udims; // Unpacked dimensions VerilatedRange m_packed; // Packed array range std::vector m_unpacked; // Unpacked array ranges void initUnpacked(const int* ulims) { for (int i = 0; i < m_udims; ++i) { const int left = ulims ? ulims[2 * i + 0] : 0; const int right = ulims ? ulims[2 * i + 1] : 0; m_unpacked.push_back(VerilatedRange(left, right)); } } // CONSTRUCTORS protected: friend class VerilatedScope; VerilatedVarProps(VerilatedVarType vltype, VerilatedVarFlags vlflags, int pdims, int udims) : m_magic(MAGIC) , m_vltype(vltype) , m_vlflags(vlflags) , m_pdims(pdims) , m_udims(udims) { initUnpacked(NULL); } public: class Unpacked {}; // Without packed VerilatedVarProps(VerilatedVarType vltype, int vlflags) : m_magic(MAGIC) , m_vltype(vltype) , m_vlflags(VerilatedVarFlags(vlflags)) , m_pdims(0) , m_udims(0) {} VerilatedVarProps(VerilatedVarType vltype, int vlflags, Unpacked, int udims, const int* ulims) : m_magic(MAGIC) , m_vltype(vltype) , m_vlflags(VerilatedVarFlags(vlflags)) , m_pdims(0) , m_udims(udims) { initUnpacked(ulims); } // With packed class Packed {}; VerilatedVarProps(VerilatedVarType vltype, int vlflags, Packed, int pl, int pr) : m_magic(MAGIC) , m_vltype(vltype) , m_vlflags(VerilatedVarFlags(vlflags)) , m_pdims(1) , m_udims(0) , m_packed(pl, pr) {} VerilatedVarProps(VerilatedVarType vltype, int vlflags, Packed, int pl, int pr, Unpacked, int udims, const int* ulims) : m_magic(MAGIC) , m_vltype(vltype) , m_vlflags(VerilatedVarFlags(vlflags)) , m_pdims(1) , m_udims(udims) , m_packed(pl, pr) { initUnpacked(ulims); } public: ~VerilatedVarProps() {} // METHODS bool magicOk() const { return m_magic == MAGIC; } VerilatedVarType vltype() const { return m_vltype; } VerilatedVarFlags vldir() const { return static_cast(static_cast(m_vlflags) & VLVF_MASK_DIR); } vluint32_t entSize() const; bool isPublicRW() const { return ((m_vlflags & VLVF_PUB_RW) != 0); } /// DPI compatible C standard layout bool isDpiCLayout() const { return ((m_vlflags & VLVF_DPI_CLAY) != 0); } int udims() const { return m_udims; } int dims() const { return m_pdims + m_udims; } const VerilatedRange& packed() const { return m_packed; } const VerilatedRange& unpacked() const { return m_unpacked[0]; } // DPI accessors int left(int dim) const { return dim == 0 ? m_packed.left() : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].left() : 0; } int right(int dim) const { return dim == 0 ? m_packed.right() : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].right() : 0; } int low(int dim) const { return dim == 0 ? m_packed.low() : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].low() : 0; } int high(int dim) const { return dim == 0 ? m_packed.high() : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].high() : 0; } int increment(int dim) const { return dim == 0 ? m_packed.increment() : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].increment() : 0; } int elements(int dim) const { return dim == 0 ? m_packed.elements() : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].elements() : 0; } /// Total size in bytes (note DPI limited to 4GB) size_t totalSize() const; /// Adjust a data pointer to access a given array element, NuLL if something goes bad void* datapAdjustIndex(void* datap, int dim, int indx) const; }; //=========================================================================== /// Verilator DPI open array variable class VerilatedDpiOpenVar { // MEMBERS const VerilatedVarProps* m_propsp; // Variable properties void* m_datap; // Location of data (local to thread always, so safe) public: // CONSTRUCTORS VerilatedDpiOpenVar(const VerilatedVarProps* propsp, void* datap) : m_propsp(propsp) , m_datap(datap) {} VerilatedDpiOpenVar(const VerilatedVarProps* propsp, const void* datap) : m_propsp(propsp) , m_datap(const_cast(datap)) {} ~VerilatedDpiOpenVar() {} // METHODS void* datap() const { return m_datap; } // METHODS - from VerilatedVarProps bool magicOk() const { return m_propsp->magicOk(); } VerilatedVarType vltype() const { return m_propsp->vltype(); } bool isDpiStdLayout() const { return m_propsp->isDpiCLayout(); } const VerilatedRange& packed() const { return m_propsp->packed(); } const VerilatedRange& unpacked() const { return m_propsp->unpacked(); } int udims() const { return m_propsp->udims(); } int left(int dim) const { return m_propsp->left(dim); } int right(int dim) const { return m_propsp->right(dim); } int low(int dim) const { return m_propsp->low(dim); } int high(int dim) const { return m_propsp->high(dim); } int increment(int dim) const { return m_propsp->increment(dim); } int elements(int dim) const { return m_propsp->elements(dim); } size_t totalSize() const { return m_propsp->totalSize(); } void* datapAdjustIndex(void* datap, int dim, int indx) const { return m_propsp->datapAdjustIndex(datap, dim, indx); } }; //=========================================================================== /// Verilator variable /// Thread safety: Assume is constructed only with model, then any number of readers class VerilatedVar : public VerilatedVarProps { // MEMBERS void* m_datap; // Location of data const char* m_namep; // Name - slowpath protected: bool m_isParam; friend class VerilatedScope; // CONSTRUCTORS VerilatedVar(const char* namep, void* datap, VerilatedVarType vltype, VerilatedVarFlags vlflags, int dims, bool isParam) : VerilatedVarProps(vltype, vlflags, (dims > 0 ? 1 : 0), ((dims > 1) ? dims - 1 : 0)) , m_datap(datap) , m_namep(namep) , m_isParam(isParam) {} public: ~VerilatedVar() {} // ACCESSORS void* datap() const { return m_datap; } const VerilatedRange& range() const { return packed(); } // Deprecated const VerilatedRange& array() const { return unpacked(); } // Deprecated const char* name() const { return m_namep; } bool isParam() const { return m_isParam; } }; #endif // Guard verilator-4.038/include/verilated_vpi.h0000664000177100017500000000356213702133367020160 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// /// \file /// \brief Verilator: VPI implementation code /// /// This file must be compiled and linked against all objects /// created from Verilator or called by Verilator that use the VPI. /// /// Code available from: https://verilator.org /// //========================================================================= #ifndef _VERILATED_VPI_H_ #define _VERILATED_VPI_H_ 1 ///< Header Guard #include "verilatedos.h" #include "verilated.h" #include "verilated_syms.h" //====================================================================== // From IEEE 1800-2009 annex K #include "vltstd/vpi_user.h" //====================================================================== class VerilatedVpi { public: /// Call timed callbacks /// Users should call this from their main loops static void callTimedCbs() VL_MT_UNSAFE_ONE; /// Call value based callbacks /// Users should call this from their main loops static void callValueCbs() VL_MT_UNSAFE_ONE; /// Call callbacks of arbitrary types /// Users can call this from their application code static bool callCbs(vluint32_t reason) VL_MT_UNSAFE_ONE; /// Returns time of the next registered VPI callback, or /// ~(0) if none are registered static QData cbNextDeadline() VL_MT_UNSAFE_ONE; /// Self test, for internal use only static void selfTest() VL_MT_UNSAFE_ONE; }; #endif // Guard verilator-4.038/include/verilated_save.cpp0000664000177100017500000002126613702216165020652 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // THIS MODULE IS PUBLICLY LICENSED // // Copyright 2001-2020 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief C++ Tracing in VCD Format /// //============================================================================= #include "verilatedos.h" #include "verilated.h" #include "verilated_save.h" #include #include // clang-format off #if defined(_WIN32) && !defined(__MINGW32__) && !defined(__CYGWIN__) # include #else # include #endif #ifndef O_LARGEFILE // For example on WIN32 # define O_LARGEFILE 0 #endif #ifndef O_NONBLOCK # define O_NONBLOCK 0 #endif #ifndef O_CLOEXEC # define O_CLOEXEC 0 #endif // clang-format on // CONSTANTS static const char* const VLTSAVE_HEADER_STR = "verilatorsave01\n"; ///< Value of first bytes of each file static const char* const VLTSAVE_TRAILER_STR = "vltsaved"; ///< Value of last bytes of each file //============================================================================= //============================================================================= //============================================================================= // Searalization bool VerilatedDeserialize::readDiffers(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { bufferCheck(); const vluint8_t* __restrict dp = static_cast(datap); vluint8_t miss = 0; while (size--) miss |= (*dp++ ^ *m_cp++); return (miss != 0); } VerilatedDeserialize& VerilatedDeserialize::readAssert(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { if (VL_UNLIKELY(readDiffers(datap, size))) { std::string fn = filename(); std::string msg = "Can't deserialize save-restore file as was made from different model:" + filename(); VL_FATAL_MT(fn.c_str(), 0, "", msg.c_str()); close(); } return *this; // For function chaining } void VerilatedSerialize::header() VL_MT_UNSAFE_ONE { VerilatedSerialize& os = *this; // So can cut and paste standard << code below assert((strlen(VLTSAVE_HEADER_STR) & 7) == 0); // Keep aligned os.write(VLTSAVE_HEADER_STR, strlen(VLTSAVE_HEADER_STR)); // Verilated doesn't do it itself, as if we're not using save/restore // it doesn't need to compile this stuff in os.write(Verilated::serialized1Ptr(), Verilated::serialized1Size()); os.write(Verilated::serialized2Ptr(), Verilated::serialized2Size()); } void VerilatedDeserialize::header() VL_MT_UNSAFE_ONE { VerilatedDeserialize& os = *this; // So can cut and paste standard >> code below if (VL_UNLIKELY(os.readDiffers(VLTSAVE_HEADER_STR, strlen(VLTSAVE_HEADER_STR)))) { std::string fn = filename(); std::string msg = std::string("Can't deserialize; file has wrong header signature: ") + filename(); VL_FATAL_MT(fn.c_str(), 0, "", msg.c_str()); close(); } os.read(Verilated::serialized1Ptr(), Verilated::serialized1Size()); os.read(Verilated::serialized2Ptr(), Verilated::serialized2Size()); } void VerilatedSerialize::trailer() VL_MT_UNSAFE_ONE { VerilatedSerialize& os = *this; // So can cut and paste standard << code below assert((strlen(VLTSAVE_TRAILER_STR) & 7) == 0); // Keep aligned os.write(VLTSAVE_TRAILER_STR, strlen(VLTSAVE_TRAILER_STR)); } void VerilatedDeserialize::trailer() VL_MT_UNSAFE_ONE { VerilatedDeserialize& os = *this; // So can cut and paste standard >> code below if (VL_UNLIKELY(os.readDiffers(VLTSAVE_TRAILER_STR, strlen(VLTSAVE_TRAILER_STR)))) { std::string fn = filename(); std::string msg = std::string("Can't deserialize; file has wrong end-of-file signature: ") + filename(); VL_FATAL_MT(fn.c_str(), 0, "", msg.c_str()); close(); } } //============================================================================= //============================================================================= //============================================================================= // Opening/Closing void VerilatedSave::open(const char* filenamep) VL_MT_UNSAFE_ONE { m_assertOne.check(); if (isOpen()) return; VL_DEBUG_IF(VL_DBG_MSGF("- save: opening save file %s\n", filenamep);); if (VL_UNCOVERABLE(filenamep[0] == '|')) { assert(0); // LCOV_EXCL_LINE // Not supported yet. } else { // cppcheck-suppress duplicateExpression m_fd = ::open(filenamep, O_CREAT | O_WRONLY | O_TRUNC | O_LARGEFILE | O_NONBLOCK | O_CLOEXEC, 0666); if (VL_UNLIKELY(m_fd < 0)) { // User code can check isOpen() m_isOpen = false; return; } } m_isOpen = true; m_filename = filenamep; m_cp = m_bufp; header(); } void VerilatedRestore::open(const char* filenamep) VL_MT_UNSAFE_ONE { m_assertOne.check(); if (isOpen()) return; VL_DEBUG_IF(VL_DBG_MSGF("- restore: opening restore file %s\n", filenamep);); if (VL_UNCOVERABLE(filenamep[0] == '|')) { assert(0); // LCOV_EXCL_LINE // Not supported yet. } else { // cppcheck-suppress duplicateExpression m_fd = ::open(filenamep, O_CREAT | O_RDONLY | O_LARGEFILE | O_CLOEXEC, 0666); if (VL_UNLIKELY(m_fd < 0)) { // User code can check isOpen() m_isOpen = false; return; } } m_isOpen = true; m_filename = filenamep; m_cp = m_bufp; m_endp = m_bufp; header(); } void VerilatedSave::close() VL_MT_UNSAFE_ONE { if (!isOpen()) return; trailer(); flush(); m_isOpen = false; ::close(m_fd); // May get error, just ignore it } void VerilatedRestore::close() VL_MT_UNSAFE_ONE { if (!isOpen()) return; trailer(); flush(); m_isOpen = false; ::close(m_fd); // May get error, just ignore it } //============================================================================= // Buffer management void VerilatedSave::flush() VL_MT_UNSAFE_ONE { m_assertOne.check(); if (VL_UNLIKELY(!isOpen())) return; vluint8_t* wp = m_bufp; while (true) { ssize_t remaining = (m_cp - wp); if (remaining == 0) break; errno = 0; ssize_t got = ::write(m_fd, wp, remaining); if (got > 0) { wp += got; } else if (VL_UNCOVERABLE(got < 0)) { if (VL_UNCOVERABLE(errno != EAGAIN && errno != EINTR)) { // LCOV_EXCL_START // write failed, presume error (perhaps out of disk space) std::string msg = std::string(__FUNCTION__) + ": " + strerror(errno); VL_FATAL_MT("", 0, "", msg.c_str()); close(); break; // LCOV_EXCL_STOP } } } m_cp = m_bufp; // Reset buffer } void VerilatedRestore::fill() VL_MT_UNSAFE_ONE { m_assertOne.check(); if (VL_UNLIKELY(!isOpen())) return; // Move remaining characters down to start of buffer. (No memcpy, overlaps allowed) vluint8_t* rp = m_bufp; for (vluint8_t* sp = m_cp; sp < m_endp; *rp++ = *sp++) {} // Overlaps m_endp = m_bufp + (m_endp - m_cp); m_cp = m_bufp; // Reset buffer // Read into buffer starting at m_endp while (true) { ssize_t remaining = (m_bufp + bufferSize() - m_endp); if (remaining == 0) break; errno = 0; ssize_t got = ::read(m_fd, m_endp, remaining); if (got > 0) { m_endp += got; } else if (VL_UNCOVERABLE(got < 0)) { if (VL_UNCOVERABLE(errno != EAGAIN && errno != EINTR)) { // LCOV_EXCL_START // write failed, presume error (perhaps out of disk space) std::string msg = std::string(__FUNCTION__) + ": " + strerror(errno); VL_FATAL_MT("", 0, "", msg.c_str()); close(); break; // LCOV_EXCL_STOP } } else { // got==0, EOF // Fill buffer from here to end with NULLs so reader's don't // need to check eof each character. while (m_endp < m_bufp + bufferSize()) *m_endp++ = '\0'; break; } } } //============================================================================= // Serialization of types verilator-4.038/include/vltstd/0000775000177100017500000000000013702335701016460 5ustar wsnyderwsnyderverilator-4.038/include/vltstd/vpi_user.h0000664000177100017500000013075613657601702020507 0ustar wsnyderwsnyder/******************************************************************************* * vpi_user.h * * IEEE Std 1800-2017 Programming Language Interface (PLI) * * This file contains the constant definitions, structure definitions, and * routine declarations used by the SystemVerilog Verification Procedural * Interface (VPI) access routines. * ******************************************************************************/ /******************************************************************************* * NOTE: the constant values 1 through 299 are reserved for use in this * vpi_user.h file. ******************************************************************************/ #ifndef VPI_USER_H #define VPI_USER_H #include #ifdef __cplusplus extern "C" { #endif /*----------------------------------------------------------------------------*/ /*----------------------------- Portability Help -----------------------------*/ /*----------------------------------------------------------------------------*/ /* Define size-critical types on all OS platforms. */ #if defined (_MSC_VER) typedef unsigned __int64 uint64_t; typedef unsigned __int32 uint32_t; typedef unsigned __int8 uint8_t; typedef signed __int64 int64_t; typedef signed __int32 int32_t; typedef signed __int8 int8_t; #elif defined(__MINGW32__) #include #elif defined(__linux) || (defined(__APPLE__) && defined(__MACH__)) #include #else #include #endif /* Sized variables */ #ifndef SVPI_TYPES #define SVPI_TYPES typedef int64_t PLI_INT64; typedef uint64_t PLI_UINT64; #endif #ifndef PLI_TYPES #define PLI_TYPES typedef int PLI_INT32; typedef unsigned int PLI_UINT32; typedef short PLI_INT16; typedef unsigned short PLI_UINT16; typedef char PLI_BYTE8; typedef unsigned char PLI_UBYTE8; #endif /* Use to import a symbol */ #if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__)) #ifndef PLI_DLLISPEC #define PLI_DLLISPEC __declspec(dllimport) #define VPI_USER_DEFINED_DLLISPEC 1 #endif #else #ifndef PLI_DLLISPEC #define PLI_DLLISPEC #endif #endif /* Use to export a symbol */ #if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__)) #ifndef PLI_DLLESPEC #define PLI_DLLESPEC __declspec(dllexport) #define VPI_USER_DEFINED_DLLESPEC 1 #endif #else #ifndef PLI_DLLESPEC #define PLI_DLLESPEC #endif #endif /* Use to mark a function as external */ #ifndef PLI_EXTERN #define PLI_EXTERN #endif /* Use to mark a variable as external */ #ifndef PLI_VEXTERN #define PLI_VEXTERN extern #endif #ifndef PLI_PROTOTYPES #define PLI_PROTOTYPES #define PROTO_PARAMS(params) params /* object is defined imported by the application */ #undef XXTERN #define XXTERN PLI_EXTERN PLI_DLLISPEC /* object is exported by the application */ #undef EETERN #define EETERN PLI_EXTERN PLI_DLLESPEC #endif /********************************** TYPEDEFS **********************************/ typedef PLI_UINT32 *vpiHandle; /******************************** OBJECT TYPES ********************************/ #define vpiAlways 1 /* always procedure */ #define vpiAssignStmt 2 /* quasi-continuous assignment */ #define vpiAssignment 3 /* procedural assignment */ #define vpiBegin 4 /* block statement */ #define vpiCase 5 /* case statement */ #define vpiCaseItem 6 /* case statement item */ #define vpiConstant 7 /* numerical constant or string literal */ #define vpiContAssign 8 /* continuous assignment */ #define vpiDeassign 9 /* deassignment statement */ #define vpiDefParam 10 /* defparam */ #define vpiDelayControl 11 /* delay statement (e.g., #10) */ #define vpiDisable 12 /* named block disable statement */ #define vpiEventControl 13 /* wait on event, e.g., @e */ #define vpiEventStmt 14 /* event trigger, e.g., ->e */ #define vpiFor 15 /* for statement */ #define vpiForce 16 /* force statement */ #define vpiForever 17 /* forever statement */ #define vpiFork 18 /* fork-join block */ #define vpiFuncCall 19 /* function call */ #define vpiFunction 20 /* function */ #define vpiGate 21 /* primitive gate */ #define vpiIf 22 /* if statement */ #define vpiIfElse 23 /* if-else statement */ #define vpiInitial 24 /* initial procedure */ #define vpiIntegerVar 25 /* integer variable */ #define vpiInterModPath 26 /* intermodule wire delay */ #define vpiIterator 27 /* iterator */ #define vpiIODecl 28 /* input/output declaration */ #define vpiMemory 29 /* behavioral memory */ #define vpiMemoryWord 30 /* single word of memory */ #define vpiModPath 31 /* module path for path delays */ #define vpiModule 32 /* module instance */ #define vpiNamedBegin 33 /* named block statement */ #define vpiNamedEvent 34 /* event variable */ #define vpiNamedFork 35 /* named fork-join block */ #define vpiNet 36 /* scalar or vector net */ #define vpiNetBit 37 /* bit of vector net */ #define vpiNullStmt 38 /* a semicolon. Ie. #10 ; */ #define vpiOperation 39 /* behavioral operation */ #define vpiParamAssign 40 /* module parameter assignment */ #define vpiParameter 41 /* module parameter */ #define vpiPartSelect 42 /* part-select */ #define vpiPathTerm 43 /* terminal of module path */ #define vpiPort 44 /* module port */ #define vpiPortBit 45 /* bit of vector module port */ #define vpiPrimTerm 46 /* primitive terminal */ #define vpiRealVar 47 /* real variable */ #define vpiReg 48 /* scalar or vector reg */ #define vpiRegBit 49 /* bit of vector reg */ #define vpiRelease 50 /* release statement */ #define vpiRepeat 51 /* repeat statement */ #define vpiRepeatControl 52 /* repeat control in an assign stmt */ #define vpiSchedEvent 53 /* vpi_put_value() event */ #define vpiSpecParam 54 /* specparam */ #define vpiSwitch 55 /* transistor switch */ #define vpiSysFuncCall 56 /* system function call */ #define vpiSysTaskCall 57 /* system task call */ #define vpiTableEntry 58 /* UDP state table entry */ #define vpiTask 59 /* task */ #define vpiTaskCall 60 /* task call */ #define vpiTchk 61 /* timing check */ #define vpiTchkTerm 62 /* terminal of timing check */ #define vpiTimeVar 63 /* time variable */ #define vpiTimeQueue 64 /* simulation event queue */ #define vpiUdp 65 /* user-defined primitive */ #define vpiUdpDefn 66 /* UDP definition */ #define vpiUserSystf 67 /* user-defined system task/function */ #define vpiVarSelect 68 /* variable array selection */ #define vpiWait 69 /* wait statement */ #define vpiWhile 70 /* while statement */ /********************** object types added with 1364-2001 *********************/ #define vpiAttribute 105 /* attribute of an object */ #define vpiBitSelect 106 /* Bit-select of parameter, var select */ #define vpiCallback 107 /* callback object */ #define vpiDelayTerm 108 /* Delay term which is a load or driver */ #define vpiDelayDevice 109 /* Delay object within a net */ #define vpiFrame 110 /* reentrant task/func frame */ #define vpiGateArray 111 /* gate instance array */ #define vpiModuleArray 112 /* module instance array */ #define vpiPrimitiveArray 113 /* vpiprimitiveArray type */ #define vpiNetArray 114 /* multidimensional net */ #define vpiRange 115 /* range declaration */ #define vpiRegArray 116 /* multidimensional reg */ #define vpiSwitchArray 117 /* switch instance array */ #define vpiUdpArray 118 /* UDP instance array */ #define vpiContAssignBit 128 /* Bit of a vector continuous assignment */ #define vpiNamedEventArray 129 /* multidimensional named event */ /********************** object types added with 1364-2005 *********************/ #define vpiIndexedPartSelect 130 /* Indexed part-select object */ #define vpiGenScopeArray 133 /* array of generated scopes */ #define vpiGenScope 134 /* A generated scope */ #define vpiGenVar 135 /* Object used to instantiate gen scopes */ /*********************************** METHODS **********************************/ /**************** methods used to traverse 1 to 1 relationships ***************/ #define vpiCondition 71 /* condition expression */ #define vpiDelay 72 /* net or gate delay */ #define vpiElseStmt 73 /* else statement */ #define vpiForIncStmt 74 /* increment statement in for loop */ #define vpiForInitStmt 75 /* initialization statement in for loop */ #define vpiHighConn 76 /* higher connection to port */ #define vpiLhs 77 /* left-hand side of assignment */ #define vpiIndex 78 /* index of var select, bit-select, etc. */ #define vpiLeftRange 79 /* left range of vector or part-select */ #define vpiLowConn 80 /* lower connection to port */ #define vpiParent 81 /* parent object */ #define vpiRhs 82 /* right-hand side of assignment */ #define vpiRightRange 83 /* right range of vector or part-select */ #define vpiScope 84 /* containing scope object */ #define vpiSysTfCall 85 /* task function call */ #define vpiTchkDataTerm 86 /* timing check data term */ #define vpiTchkNotifier 87 /* timing check notifier */ #define vpiTchkRefTerm 88 /* timing check reference term */ /************* methods used to traverse 1 to many relationships ***************/ #define vpiArgument 89 /* argument to (system) task/function */ #define vpiBit 90 /* bit of vector net or port */ #define vpiDriver 91 /* driver for a net */ #define vpiInternalScope 92 /* internal scope in module */ #define vpiLoad 93 /* load on net or reg */ #define vpiModDataPathIn 94 /* data terminal of a module path */ #define vpiModPathIn 95 /* Input terminal of a module path */ #define vpiModPathOut 96 /* output terminal of a module path */ #define vpiOperand 97 /* operand of expression */ #define vpiPortInst 98 /* connected port instance */ #define vpiProcess 99 /* process in module, program or interface */ #define vpiVariables 100 /* variables in module */ #define vpiUse 101 /* usage */ /******** methods which can traverse 1 to 1, or 1 to many relationships *******/ #define vpiExpr 102 /* connected expression */ #define vpiPrimitive 103 /* primitive (gate, switch, UDP) */ #define vpiStmt 104 /* statement in process or task */ /************************ methods added with 1364-2001 ************************/ #define vpiActiveTimeFormat 119 /* active $timeformat() system task */ #define vpiInTerm 120 /* To get to a delay device's drivers. */ #define vpiInstanceArray 121 /* vpiInstance arrays */ #define vpiLocalDriver 122 /* local drivers (within a module */ #define vpiLocalLoad 123 /* local loads (within a module */ #define vpiOutTerm 124 /* To get to a delay device's loads. */ #define vpiPorts 125 /* Module port */ #define vpiSimNet 126 /* simulated net after collapsing */ #define vpiTaskFunc 127 /* task/function */ /************************ methods added with 1364-2005 ************************/ #define vpiBaseExpr 131 /* Indexed part-select's base expression */ #define vpiWidthExpr 132 /* Indexed part-select's width expression */ /************************ methods added with 1800-2009 ************************/ #define vpiAutomatics 136 /* Automatic variables of a frame */ /********************************* PROPERTIES *********************************/ /************************** generic object properties *************************/ #define vpiUndefined -1 /* undefined property */ #define vpiType 1 /* type of object */ #define vpiName 2 /* local name of object */ #define vpiFullName 3 /* full hierarchical name */ #define vpiSize 4 /* size of gate, net, port, etc. */ #define vpiFile 5 /* File name in which the object is used*/ #define vpiLineNo 6 /* line number where the object is used */ /***************************** module properties ******************************/ #define vpiTopModule 7 /* top-level module (Boolean) */ #define vpiCellInstance 8 /* cell (Boolean) */ #define vpiDefName 9 /* module definition name */ #define vpiProtected 10 /* source protected module (Boolean) */ #define vpiTimeUnit 11 /* module time unit */ #define vpiTimePrecision 12 /* module time precision */ #define vpiDefNetType 13 /* default net type */ #define vpiUnconnDrive 14 /* unconnected port drive strength */ #define vpiHighZ 1 /* No default drive given */ #define vpiPull1 2 /* default pull1 drive */ #define vpiPull0 3 /* default pull0 drive */ #define vpiDefFile 15 /* File name where the module is defined*/ #define vpiDefLineNo 16 /* line number for module definition */ #define vpiDefDelayMode 47 /* Default delay mode for a module */ #define vpiDelayModeNone 1 /* no delay mode specified */ #define vpiDelayModePath 2 /* path delay mode */ #define vpiDelayModeDistrib 3 /* distributed delay mode */ #define vpiDelayModeUnit 4 /* unit delay mode */ #define vpiDelayModeZero 5 /* zero delay mode */ #define vpiDelayModeMTM 6 /* min:typ:max delay mode */ #define vpiDefDecayTime 48 /* Default decay time for a module */ /*************************** port and net properties **************************/ #define vpiScalar 17 /* scalar (Boolean) */ #define vpiVector 18 /* vector (Boolean) */ #define vpiExplicitName 19 /* port is explicitly named */ #define vpiDirection 20 /* direction of port: */ #define vpiInput 1 /* input */ #define vpiOutput 2 /* output */ #define vpiInout 3 /* inout */ #define vpiMixedIO 4 /* mixed input-output */ #define vpiNoDirection 5 /* no direction */ #define vpiConnByName 21 /* connected by name (Boolean) */ #define vpiNetType 22 /* net subtypes: */ #define vpiWire 1 /* wire net */ #define vpiWand 2 /* wire-and net */ #define vpiWor 3 /* wire-or net */ #define vpiTri 4 /* tri net */ #define vpiTri0 5 /* pull-down net */ #define vpiTri1 6 /* pull-up net */ #define vpiTriReg 7 /* three-state reg net */ #define vpiTriAnd 8 /* three-state wire-and net */ #define vpiTriOr 9 /* three-state wire-or net */ #define vpiSupply1 10 /* supply-1 net */ #define vpiSupply0 11 /* supply-0 net */ #define vpiNone 12 /* no default net type (1364-2001) */ #define vpiUwire 13 /* unresolved wire net (1364-2005) */ #define vpiExplicitScalared 23 /* explicitly scalared (Boolean) */ #define vpiExplicitVectored 24 /* explicitly vectored (Boolean) */ #define vpiExpanded 25 /* expanded vector net (Boolean) */ #define vpiImplicitDecl 26 /* implicitly declared net (Boolean) */ #define vpiChargeStrength 27 /* charge decay strength of net */ /* Defined as part of strengths section. #define vpiLargeCharge 0x10 #define vpiMediumCharge 0x04 #define vpiSmallCharge 0x02 */ #define vpiArray 28 /* variable array (Boolean) */ #define vpiPortIndex 29 /* Port index */ /************************ gate and terminal properties ************************/ #define vpiTermIndex 30 /* Index of a primitive terminal */ #define vpiStrength0 31 /* 0-strength of net or gate */ #define vpiStrength1 32 /* 1-strength of net or gate */ #define vpiPrimType 33 /* primitive subtypes: */ #define vpiAndPrim 1 /* and gate */ #define vpiNandPrim 2 /* nand gate */ #define vpiNorPrim 3 /* nor gate */ #define vpiOrPrim 4 /* or gate */ #define vpiXorPrim 5 /* xor gate */ #define vpiXnorPrim 6 /* xnor gate */ #define vpiBufPrim 7 /* buffer */ #define vpiNotPrim 8 /* not gate */ #define vpiBufif0Prim 9 /* zero-enabled buffer */ #define vpiBufif1Prim 10 /* one-enabled buffer */ #define vpiNotif0Prim 11 /* zero-enabled not gate */ #define vpiNotif1Prim 12 /* one-enabled not gate */ #define vpiNmosPrim 13 /* nmos switch */ #define vpiPmosPrim 14 /* pmos switch */ #define vpiCmosPrim 15 /* cmos switch */ #define vpiRnmosPrim 16 /* resistive nmos switch */ #define vpiRpmosPrim 17 /* resistive pmos switch */ #define vpiRcmosPrim 18 /* resistive cmos switch */ #define vpiRtranPrim 19 /* resistive bidirectional */ #define vpiRtranif0Prim 20 /* zero-enable resistive bidirectional */ #define vpiRtranif1Prim 21 /* one-enable resistive bidirectional */ #define vpiTranPrim 22 /* bidirectional */ #define vpiTranif0Prim 23 /* zero-enabled bidirectional */ #define vpiTranif1Prim 24 /* one-enabled bidirectional */ #define vpiPullupPrim 25 /* pullup */ #define vpiPulldownPrim 26 /* pulldown */ #define vpiSeqPrim 27 /* sequential UDP */ #define vpiCombPrim 28 /* combinational UDP */ /**************** path, path terminal, timing check properties ****************/ #define vpiPolarity 34 /* polarity of module path... */ #define vpiDataPolarity 35 /* ...or data path: */ #define vpiPositive 1 /* positive */ #define vpiNegative 2 /* negative */ #define vpiUnknown 3 /* unknown (unspecified) */ #define vpiEdge 36 /* edge type of module path: */ #define vpiNoEdge 0x00 /* no edge */ #define vpiEdge01 0x01 /* 0 -> 1 */ #define vpiEdge10 0x02 /* 1 -> 0 */ #define vpiEdge0x 0x04 /* 0 -> x */ #define vpiEdgex1 0x08 /* x -> 1 */ #define vpiEdge1x 0x10 /* 1 -> x */ #define vpiEdgex0 0x20 /* x -> 0 */ #define vpiPosedge (vpiEdgex1 | vpiEdge01 | vpiEdge0x) #define vpiNegedge (vpiEdgex0 | vpiEdge10 | vpiEdge1x) #define vpiAnyEdge (vpiPosedge | vpiNegedge) #define vpiPathType 37 /* path delay connection subtypes: */ #define vpiPathFull 1 /* ( a *> b ) */ #define vpiPathParallel 2 /* ( a => b ) */ #define vpiTchkType 38 /* timing check subtypes: */ #define vpiSetup 1 /* $setup */ #define vpiHold 2 /* $hold */ #define vpiPeriod 3 /* $period */ #define vpiWidth 4 /* $width */ #define vpiSkew 5 /* $skew */ #define vpiRecovery 6 /* $recovery */ #define vpiNoChange 7 /* $nochange */ #define vpiSetupHold 8 /* $setuphold */ #define vpiFullskew 9 /* $fullskew -- added for 1364-2001 */ #define vpiRecrem 10 /* $recrem -- added for 1364-2001 */ #define vpiRemoval 11 /* $removal -- added for 1364-2001 */ #define vpiTimeskew 12 /* $timeskew -- added for 1364-2001 */ /**************************** expression properties ***************************/ #define vpiOpType 39 /* operation subtypes: */ #define vpiMinusOp 1 /* unary minus */ #define vpiPlusOp 2 /* unary plus */ #define vpiNotOp 3 /* unary not */ #define vpiBitNegOp 4 /* bitwise negation */ #define vpiUnaryAndOp 5 /* bitwise reduction AND */ #define vpiUnaryNandOp 6 /* bitwise reduction NAND */ #define vpiUnaryOrOp 7 /* bitwise reduction OR */ #define vpiUnaryNorOp 8 /* bitwise reduction NOR */ #define vpiUnaryXorOp 9 /* bitwise reduction XOR */ #define vpiUnaryXNorOp 10 /* bitwise reduction XNOR */ #define vpiSubOp 11 /* binary subtraction */ #define vpiDivOp 12 /* binary division */ #define vpiModOp 13 /* binary modulus */ #define vpiEqOp 14 /* binary equality */ #define vpiNeqOp 15 /* binary inequality */ #define vpiCaseEqOp 16 /* case (x and z) equality */ #define vpiCaseNeqOp 17 /* case inequality */ #define vpiGtOp 18 /* binary greater than */ #define vpiGeOp 19 /* binary greater than or equal */ #define vpiLtOp 20 /* binary less than */ #define vpiLeOp 21 /* binary less than or equal */ #define vpiLShiftOp 22 /* binary left shift */ #define vpiRShiftOp 23 /* binary right shift */ #define vpiAddOp 24 /* binary addition */ #define vpiMultOp 25 /* binary multiplication */ #define vpiLogAndOp 26 /* binary logical AND */ #define vpiLogOrOp 27 /* binary logical OR */ #define vpiBitAndOp 28 /* binary bitwise AND */ #define vpiBitOrOp 29 /* binary bitwise OR */ #define vpiBitXorOp 30 /* binary bitwise XOR */ #define vpiBitXNorOp 31 /* binary bitwise XNOR */ #define vpiBitXnorOp vpiBitXNorOp /* added with 1364-2001 */ #define vpiConditionOp 32 /* ternary conditional */ #define vpiConcatOp 33 /* n-ary concatenation */ #define vpiMultiConcatOp 34 /* repeated concatenation */ #define vpiEventOrOp 35 /* event OR */ #define vpiNullOp 36 /* null operation */ #define vpiListOp 37 /* list of expressions */ #define vpiMinTypMaxOp 38 /* min:typ:max: delay expression */ #define vpiPosedgeOp 39 /* posedge */ #define vpiNegedgeOp 40 /* negedge */ #define vpiArithLShiftOp 41 /* arithmetic left shift (1364-2001) */ #define vpiArithRShiftOp 42 /* arithmetic right shift (1364-2001) */ #define vpiPowerOp 43 /* arithmetic power op (1364-2001) */ #define vpiConstType 40 /* constant subtypes: */ #define vpiDecConst 1 /* decimal integer */ #define vpiRealConst 2 /* real */ #define vpiBinaryConst 3 /* binary integer */ #define vpiOctConst 4 /* octal integer */ #define vpiHexConst 5 /* hexadecimal integer */ #define vpiStringConst 6 /* string literal */ #define vpiIntConst 7 /* integer constant (1364-2001) */ #define vpiTimeConst 8 /* time constant */ #define vpiBlocking 41 /* blocking assignment (Boolean) */ #define vpiCaseType 42 /* case statement subtypes: */ #define vpiCaseExact 1 /* exact match */ #define vpiCaseX 2 /* ignore X's */ #define vpiCaseZ 3 /* ignore Z's */ #define vpiNetDeclAssign 43 /* assign part of decl (Boolean) */ /************************** task/function properties **************************/ #define vpiFuncType 44 /* function & system function type */ #define vpiIntFunc 1 /* returns integer */ #define vpiRealFunc 2 /* returns real */ #define vpiTimeFunc 3 /* returns time */ #define vpiSizedFunc 4 /* returns an arbitrary size */ #define vpiSizedSignedFunc 5 /* returns sized signed value */ /** alias 1364-1995 system function subtypes to 1364-2001 function subtypes ***/ #define vpiSysFuncType vpiFuncType #define vpiSysFuncInt vpiIntFunc #define vpiSysFuncReal vpiRealFunc #define vpiSysFuncTime vpiTimeFunc #define vpiSysFuncSized vpiSizedFunc #define vpiUserDefn 45 /*user-defined system task/func(Boolean)*/ #define vpiScheduled 46 /* object still scheduled (Boolean) */ /*********************** properties added with 1364-2001 **********************/ #define vpiActive 49 /* reentrant task/func frame is active */ #define vpiAutomatic 50 /* task/func obj is automatic */ #define vpiCell 51 /* configuration cell */ #define vpiConfig 52 /* configuration config file */ #define vpiConstantSelect 53 /* (Boolean) bit-select or part-select indices are constant expressions */ #define vpiDecompile 54 /* decompile the object */ #define vpiDefAttribute 55 /* Attribute defined for the obj */ #define vpiDelayType 56 /* delay subtype */ #define vpiModPathDelay 1 /* module path delay */ #define vpiInterModPathDelay 2 /* intermodule path delay */ #define vpiMIPDelay 3 /* module input port delay */ #define vpiIteratorType 57 /* object type of an iterator */ #define vpiLibrary 58 /* configuration library */ #define vpiOffset 60 /* offset from LSB */ #define vpiResolvedNetType 61 /* net subtype after resolution, returns same subtypes as vpiNetType */ #define vpiSaveRestartID 62 /* unique ID for save/restart data */ #define vpiSaveRestartLocation 63 /* name of save/restart data file */ /* vpiValid,vpiValidTrue,vpiValidFalse were deprecated in 1800-2009 */ #define vpiValid 64 /* reentrant task/func frame or automatic variable is valid */ #define vpiValidFalse 0 #define vpiValidTrue 1 #define vpiSigned 65 /* TRUE for vpiIODecl and any object in the expression class if the object has the signed attribute */ #define vpiLocalParam 70 /* TRUE when a param is declared as a localparam */ #define vpiModPathHasIfNone 71 /* Mod path has an ifnone statement */ /*********************** properties added with 1364-2005 **********************/ #define vpiIndexedPartSelectType 72 /* Indexed part-select type */ #define vpiPosIndexed 1 /* +: */ #define vpiNegIndexed 2 /* -: */ #define vpiIsMemory 73 /* TRUE for a one-dimensional reg array */ #define vpiIsProtected 74 /* TRUE for protected design information */ /*************** vpi_control() constants (added with 1364-2001) ***************/ #define vpiStop 66 /* execute simulator's $stop */ #define vpiFinish 67 /* execute simulator's $finish */ #define vpiReset 68 /* execute simulator's $reset */ #define vpiSetInteractiveScope 69 /* set simulator's interactive scope */ /**************************** I/O related defines *****************************/ #define VPI_MCD_STDOUT 0x00000001 /*************************** STRUCTURE DEFINITIONS ****************************/ /******************************* time structure *******************************/ typedef struct t_vpi_time { PLI_INT32 type; /* [vpiScaledRealTime, vpiSimTime, vpiSuppressTime] */ PLI_UINT32 high, low; /* for vpiSimTime */ double real; /* for vpiScaledRealTime */ } s_vpi_time, *p_vpi_time; /* time types */ #define vpiScaledRealTime 1 #define vpiSimTime 2 #define vpiSuppressTime 3 /****************************** delay structures ******************************/ typedef struct t_vpi_delay { struct t_vpi_time *da; /* pointer to application-allocated array of delay values */ PLI_INT32 no_of_delays; /* number of delays */ PLI_INT32 time_type; /* [vpiScaledRealTime, vpiSimTime, vpiSuppressTime] */ PLI_INT32 mtm_flag; /* true for mtm values */ PLI_INT32 append_flag; /* true for append */ PLI_INT32 pulsere_flag; /* true for pulsere values */ } s_vpi_delay, *p_vpi_delay; /***************************** value structures *******************************/ /* vector value */ #ifndef VPI_VECVAL /* added in 1364-2005 */ #define VPI_VECVAL typedef struct t_vpi_vecval { /* following fields are repeated enough times to contain vector */ PLI_UINT32 aval, bval; /* bit encoding: ab: 00=0, 10=1, 11=X, 01=Z */ } s_vpi_vecval, *p_vpi_vecval; #endif /* strength (scalar) value */ typedef struct t_vpi_strengthval { PLI_INT32 logic; /* vpi[0,1,X,Z] */ PLI_INT32 s0, s1; /* refer to strength coding below */ } s_vpi_strengthval, *p_vpi_strengthval; /* strength values */ #define vpiSupplyDrive 0x80 #define vpiStrongDrive 0x40 #define vpiPullDrive 0x20 #define vpiWeakDrive 0x08 #define vpiLargeCharge 0x10 #define vpiMediumCharge 0x04 #define vpiSmallCharge 0x02 #define vpiHiZ 0x01 /* generic value */ typedef struct t_vpi_value { PLI_INT32 format; /* vpi[[Bin,Oct,Dec,Hex]Str,Scalar,Int,Real,String, Vector,Strength,Suppress,Time,ObjType]Val */ union { PLI_BYTE8 *str; /* string value */ PLI_INT32 scalar; /* vpi[0,1,X,Z] */ PLI_INT32 integer; /* integer value */ double real; /* real value */ struct t_vpi_time *time; /* time value */ struct t_vpi_vecval *vector; /* vector value */ struct t_vpi_strengthval *strength; /* strength value */ PLI_BYTE8 *misc; /* ...other */ } value; } s_vpi_value, *p_vpi_value; typedef struct t_vpi_arrayvalue { PLI_UINT32 format; /* vpi[Int,Real,Time,ShortInt,LongInt,ShortReal, RawTwoState,RawFourState]Val */ PLI_UINT32 flags; /* array bit flags- vpiUserAllocFlag */ union { PLI_INT32 *integers; /* integer values */ PLI_INT16 *shortints; /* short integer values */ PLI_INT64 *longints; /* long integer values */ PLI_BYTE8 *rawvals; /* 2/4-state vector elements */ struct t_vpi_vecval *vectors; /* 4-state vector elements */ struct t_vpi_time *times; /* time values */ double *reals; /* real values */ float *shortreals; /* short real values */ } value; } s_vpi_arrayvalue, *p_vpi_arrayvalue; /* value formats */ #define vpiBinStrVal 1 #define vpiOctStrVal 2 #define vpiDecStrVal 3 #define vpiHexStrVal 4 #define vpiScalarVal 5 #define vpiIntVal 6 #define vpiRealVal 7 #define vpiStringVal 8 #define vpiVectorVal 9 #define vpiStrengthVal 10 #define vpiTimeVal 11 #define vpiObjTypeVal 12 #define vpiSuppressVal 13 #define vpiShortIntVal 14 #define vpiLongIntVal 15 #define vpiShortRealVal 16 #define vpiRawTwoStateVal 17 #define vpiRawFourStateVal 18 /* delay modes */ #define vpiNoDelay 1 #define vpiInertialDelay 2 #define vpiTransportDelay 3 #define vpiPureTransportDelay 4 /* force and release flags */ #define vpiForceFlag 5 #define vpiReleaseFlag 6 /* scheduled event cancel flag */ #define vpiCancelEvent 7 /* bit mask for the flags argument to vpi_put_value() */ #define vpiReturnEvent 0x1000 /* bit flags for vpi_get_value_array flags field */ #define vpiUserAllocFlag 0x2000 /* bit flags for vpi_put_value_array flags field */ #define vpiOneValue 0x4000 #define vpiPropagateOff 0x8000 /* scalar values */ #define vpi0 0 #define vpi1 1 #define vpiZ 2 #define vpiX 3 #define vpiH 4 #define vpiL 5 #define vpiDontCare 6 /* #define vpiNoChange 7 Defined under vpiTchkType, but can be used here. */ /*********************** system task/function structure ***********************/ typedef struct t_vpi_systf_data { PLI_INT32 type; /* vpiSysTask, vpiSysFunc */ PLI_INT32 sysfunctype; /* vpiSysTask, vpi[Int,Real,Time,Sized, SizedSigned]Func */ PLI_BYTE8 *tfname; /* first character must be '$' */ PLI_INT32 (*calltf)(PLI_BYTE8 *); PLI_INT32 (*compiletf)(PLI_BYTE8 *); PLI_INT32 (*sizetf)(PLI_BYTE8 *); /* for sized function callbacks only */ PLI_BYTE8 *user_data; } s_vpi_systf_data, *p_vpi_systf_data; #define vpiSysTask 1 #define vpiSysFunc 2 /* the subtypes are defined under the vpiFuncType property */ /**************** SystemVerilog execution information structure ***************/ typedef struct t_vpi_vlog_info { PLI_INT32 argc; PLI_BYTE8 **argv; PLI_BYTE8 *product; PLI_BYTE8 *version; } s_vpi_vlog_info, *p_vpi_vlog_info; /*********************** PLI error information structure **********************/ typedef struct t_vpi_error_info { PLI_INT32 state; /* vpi[Compile,PLI,Run] */ PLI_INT32 level; /* vpi[Notice,Warning,Error,System,Internal] */ PLI_BYTE8 *message; PLI_BYTE8 *product; PLI_BYTE8 *code; PLI_BYTE8 *file; PLI_INT32 line; } s_vpi_error_info, *p_vpi_error_info; /* state when error occurred */ #define vpiCompile 1 #define vpiPLI 2 #define vpiRun 3 /* error severity levels */ #define vpiNotice 1 #define vpiWarning 2 #define vpiError 3 #define vpiSystem 4 #define vpiInternal 5 /**************************** callback structures *****************************/ /* normal callback structure */ typedef struct t_cb_data { PLI_INT32 reason; /* callback reason */ PLI_INT32 (*cb_rtn)(struct t_cb_data *); /* call routine */ vpiHandle obj; /* trigger object */ p_vpi_time time; /* callback time */ p_vpi_value value; /* trigger object value */ PLI_INT32 index; /* index of the memory word or var select that changed */ PLI_BYTE8 *user_data; } s_cb_data, *p_cb_data; /****************************** CALLBACK REASONS ******************************/ /***************************** Simulation related *****************************/ #define cbValueChange 1 #define cbStmt 2 #define cbForce 3 #define cbRelease 4 /******************************** Time related ********************************/ #define cbAtStartOfSimTime 5 #define cbReadWriteSynch 6 #define cbReadOnlySynch 7 #define cbNextSimTime 8 #define cbAfterDelay 9 /******************************* Action related *******************************/ #define cbEndOfCompile 10 #define cbStartOfSimulation 11 #define cbEndOfSimulation 12 #define cbError 13 #define cbTchkViolation 14 #define cbStartOfSave 15 #define cbEndOfSave 16 #define cbStartOfRestart 17 #define cbEndOfRestart 18 #define cbStartOfReset 19 #define cbEndOfReset 20 #define cbEnterInteractive 21 #define cbExitInteractive 22 #define cbInteractiveScopeChange 23 #define cbUnresolvedSystf 24 /**************************** Added with 1364-2001 ****************************/ #define cbAssign 25 #define cbDeassign 26 #define cbDisable 27 #define cbPLIError 28 #define cbSignal 29 /**************************** Added with 1364-2005 ****************************/ #define cbNBASynch 30 #define cbAtEndOfSimTime 31 /**************************** FUNCTION DECLARATIONS ***************************/ /* Include compatibility mode macro definitions. */ //#include "vpi_compatibility.h" /* callback related */ XXTERN vpiHandle vpi_register_cb PROTO_PARAMS((p_cb_data cb_data_p)); XXTERN PLI_INT32 vpi_remove_cb PROTO_PARAMS((vpiHandle cb_obj)); XXTERN void vpi_get_cb_info PROTO_PARAMS((vpiHandle object, p_cb_data cb_data_p)); XXTERN vpiHandle vpi_register_systf PROTO_PARAMS((p_vpi_systf_data systf_data_p)); XXTERN void vpi_get_systf_info PROTO_PARAMS((vpiHandle object, p_vpi_systf_data systf_data_p)); /* for obtaining handles */ XXTERN vpiHandle vpi_handle_by_name PROTO_PARAMS((PLI_BYTE8 *name, vpiHandle scope)); XXTERN vpiHandle vpi_handle_by_index PROTO_PARAMS((vpiHandle object, PLI_INT32 indx)); /* for traversing relationships */ XXTERN vpiHandle vpi_handle PROTO_PARAMS((PLI_INT32 type, vpiHandle refHandle)); XXTERN vpiHandle vpi_handle_multi PROTO_PARAMS((PLI_INT32 type, vpiHandle refHandle1, vpiHandle refHandle2, ... )); XXTERN vpiHandle vpi_iterate PROTO_PARAMS((PLI_INT32 type, vpiHandle refHandle)); XXTERN vpiHandle vpi_scan PROTO_PARAMS((vpiHandle iterator)); /* for processing properties */ XXTERN PLI_INT32 vpi_get PROTO_PARAMS((PLI_INT32 property, vpiHandle object)); XXTERN PLI_INT64 vpi_get64 PROTO_PARAMS((PLI_INT32 property, vpiHandle object)); XXTERN PLI_BYTE8 *vpi_get_str PROTO_PARAMS((PLI_INT32 property, vpiHandle object)); /* delay processing */ XXTERN void vpi_get_delays PROTO_PARAMS((vpiHandle object, p_vpi_delay delay_p)); XXTERN void vpi_put_delays PROTO_PARAMS((vpiHandle object, p_vpi_delay delay_p)); /* value processing */ XXTERN void vpi_get_value PROTO_PARAMS((vpiHandle expr, p_vpi_value value_p)); XXTERN vpiHandle vpi_put_value PROTO_PARAMS((vpiHandle object, p_vpi_value value_p, p_vpi_time time_p, PLI_INT32 flags)); XXTERN void vpi_get_value_array PROTO_PARAMS((vpiHandle object, p_vpi_arrayvalue arrayvalue_p, PLI_INT32 *index_p, PLI_UINT32 num)); XXTERN void vpi_put_value_array PROTO_PARAMS((vpiHandle object, p_vpi_arrayvalue arrayvalue_p, PLI_INT32 *index_p, PLI_UINT32 num)); /* time processing */ XXTERN void vpi_get_time PROTO_PARAMS((vpiHandle object, p_vpi_time time_p)); /* I/O routines */ XXTERN PLI_UINT32 vpi_mcd_open PROTO_PARAMS((PLI_BYTE8 *fileName)); XXTERN PLI_UINT32 vpi_mcd_close PROTO_PARAMS((PLI_UINT32 mcd)); XXTERN PLI_BYTE8 *vpi_mcd_name PROTO_PARAMS((PLI_UINT32 cd)); XXTERN PLI_INT32 vpi_mcd_printf PROTO_PARAMS((PLI_UINT32 mcd, PLI_BYTE8 *format, ...)); XXTERN PLI_INT32 vpi_printf PROTO_PARAMS((PLI_BYTE8 *format, ...)); /* utility routines */ XXTERN PLI_INT32 vpi_compare_objects PROTO_PARAMS((vpiHandle object1, vpiHandle object2)); XXTERN PLI_INT32 vpi_chk_error PROTO_PARAMS((p_vpi_error_info error_info_p)); /* vpi_free_object() was deprecated in 1800-2009 */ XXTERN PLI_INT32 vpi_free_object PROTO_PARAMS((vpiHandle object)); XXTERN PLI_INT32 vpi_release_handle PROTO_PARAMS((vpiHandle object)); XXTERN PLI_INT32 vpi_get_vlog_info PROTO_PARAMS((p_vpi_vlog_info vlog_info_p)); /* routines added with 1364-2001 */ XXTERN PLI_INT32 vpi_get_data PROTO_PARAMS((PLI_INT32 id, PLI_BYTE8 *dataLoc, PLI_INT32 numOfBytes)); XXTERN PLI_INT32 vpi_put_data PROTO_PARAMS((PLI_INT32 id, PLI_BYTE8 *dataLoc, PLI_INT32 numOfBytes)); XXTERN void *vpi_get_userdata PROTO_PARAMS((vpiHandle obj)); XXTERN PLI_INT32 vpi_put_userdata PROTO_PARAMS((vpiHandle obj, void *userdata)); XXTERN PLI_INT32 vpi_vprintf PROTO_PARAMS((PLI_BYTE8 *format, va_list ap)); XXTERN PLI_INT32 vpi_mcd_vprintf PROTO_PARAMS((PLI_UINT32 mcd, PLI_BYTE8 *format, va_list ap)); XXTERN PLI_INT32 vpi_flush PROTO_PARAMS((void)); XXTERN PLI_INT32 vpi_mcd_flush PROTO_PARAMS((PLI_UINT32 mcd)); XXTERN PLI_INT32 vpi_control PROTO_PARAMS((PLI_INT32 operation, ...)); XXTERN vpiHandle vpi_handle_by_multi_index PROTO_PARAMS((vpiHandle obj, PLI_INT32 num_index, PLI_INT32 *index_array)); /****************************** GLOBAL VARIABLES ******************************/ PLI_VEXTERN PLI_DLLESPEC void (*vlog_startup_routines[])( void ); /* array of function pointers, last pointer should be null */ #undef PLI_EXTERN #undef PLI_VEXTERN #ifdef VPI_USER_DEFINED_DLLISPEC # undef VPI_USER_DEFINED_DLLISPEC # undef PLI_DLLISPEC #endif #ifdef VPI_USER_DEFINED_DLLESPEC # undef VPI_USER_DEFINED_DLLESPEC # undef PLI_DLLESPEC #endif #ifdef PLI_PROTOTYPES # undef PLI_PROTOTYPES # undef PROTO_PARAMS # undef XXTERN # undef EETERN #endif #ifdef __cplusplus } #endif #endif /* VPI_USER_H */ verilator-4.038/include/vltstd/svdpi.h0000664000177100017500000004416313660317316017773 0ustar wsnyderwsnyder/* -*- C -*- * * svdpi.h * * SystemVerilog Direct Programming Interface (DPI). * * This file contains the constant definitions, structure definitions, * and routine declarations used by SystemVerilog DPI. * * This file is from the SystemVerilog IEEE 1800-2017 Annex I. */ #ifndef INCLUDED_SVDPI #define INCLUDED_SVDPI #ifdef __cplusplus extern "C" { #endif /* Define size-critical types on all OS platforms. */ #if defined (_MSC_VER) typedef unsigned __int64 uint64_t; typedef unsigned __int32 uint32_t; typedef unsigned __int8 uint8_t; typedef signed __int64 int64_t; typedef signed __int32 int32_t; typedef signed __int8 int8_t; #elif defined(__MINGW32__) #include #elif defined(__APPLE__) #include #elif defined(__linux) || (defined(__APPLE__) && defined(__MACH__)) #include #else #include #endif /* Use to import a symbol into dll */ #ifndef DPI_DLLISPEC #if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__)) #define DPI_DLLISPEC __declspec(dllimport) #else #define DPI_DLLISPEC #endif #endif /* Use to export a symbol from dll */ #ifndef DPI_DLLESPEC #if (defined(_MSC_VER) || defined(__MINGW32__) || defined(__CYGWIN__)) #define DPI_DLLESPEC __declspec(dllexport) #else #define DPI_DLLESPEC #endif #endif /* Use to mark a function as external */ #ifndef DPI_EXTERN #define DPI_EXTERN #endif #ifndef DPI_PROTOTYPES #define DPI_PROTOTYPES /* object is defined imported by the application */ #define XXTERN DPI_EXTERN DPI_DLLISPEC /* object is exported by the application */ #define EETERN DPI_EXTERN DPI_DLLESPEC #endif /* canonical representation */ #define sv_0 0 #define sv_1 1 #define sv_z 2 #define sv_x 3 /* common type for 'bit' and 'logic' scalars. */ typedef uint8_t svScalar; typedef svScalar svBit; /* scalar */ typedef svScalar svLogic; /* scalar */ /* * DPI representation of packed arrays. * 2-state and 4-state vectors, exactly the same as PLI's avalue/bvalue. */ #ifndef VPI_VECVAL #define VPI_VECVAL typedef struct t_vpi_vecval { uint32_t aval; uint32_t bval; } s_vpi_vecval, *p_vpi_vecval; #endif /* (a chunk of) packed logic array */ typedef s_vpi_vecval svLogicVecVal; /* (a chunk of) packed bit array */ typedef uint32_t svBitVecVal; /* Number of chunks required to represent the given width packed array */ #define SV_PACKED_DATA_NELEMS(WIDTH) (((WIDTH) + 31) >> 5) /* * Because the contents of the unused bits is undetermined, * the following macros can be handy. */ #define SV_MASK(N) (~(-1 << (N))) #define SV_GET_UNSIGNED_BITS(VALUE, N) \ ((N) == 32 ? (VALUE) : ((VALUE) & SV_MASK(N))) #define SV_GET_SIGNED_BITS(VALUE, N) \ ((N) == 32 ? (VALUE) : \ (((VALUE) & (1 << (N))) ? ((VALUE) | ~SV_MASK(N)) : ((VALUE) & SV_MASK(N)))) /* * Implementation-dependent representation. */ /* * Return implementation version information string ("1800-2005" or "SV3.1a"). */ XXTERN const char* svDpiVersion( void ); /* a handle to a scope (an instance of a module or interface) */ XXTERN typedef void* svScope; /* a handle to a generic object (actually, unsized array) */ XXTERN typedef void* svOpenArrayHandle; /* * Bit-select utility functions. * * Packed arrays are assumed to be indexed n-1:0, * where 0 is the index of LSB */ /* s=source, i=bit-index */ XXTERN svBit svGetBitselBit(const svBitVecVal* s, int i); XXTERN svLogic svGetBitselLogic(const svLogicVecVal* s, int i); /* d=destination, i=bit-index, s=scalar */ XXTERN void svPutBitselBit(svBitVecVal* d, int i, svBit s); XXTERN void svPutBitselLogic(svLogicVecVal* d, int i, svLogic s); /* * Part-select utility functions. * * A narrow (<=32 bits) part-select is extracted from the * source representation and written into the destination word. * * Normalized ranges and indexing [n-1:0] are used for both arrays. * * s=source, d=destination, i=starting bit index, w=width * like for variable part-selects; limitations: w <= 32 */ XXTERN void svGetPartselBit(svBitVecVal* d, const svBitVecVal* s, int i, int w); XXTERN void svGetPartselLogic(svLogicVecVal* d, const svLogicVecVal* s, int i, int w); XXTERN void svPutPartselBit(svBitVecVal* d, const svBitVecVal s, int i, int w); XXTERN void svPutPartselLogic(svLogicVecVal* d, const svLogicVecVal s, int i, int w); /* * Open array querying functions * These functions are modeled upon the SystemVerilog array * querying functions and use the same semantics. * * If the dimension is 0, then the query refers to the * packed part of an array (which is one-dimensional). * Dimensions > 0 refer to the unpacked part of an array. */ /* h= handle to open array, d=dimension */ XXTERN int svLeft(const svOpenArrayHandle h, int d); XXTERN int svRight(const svOpenArrayHandle h, int d); XXTERN int svLow(const svOpenArrayHandle h, int d); XXTERN int svHigh(const svOpenArrayHandle h, int d); XXTERN int svIncrement(const svOpenArrayHandle h, int d); XXTERN int svSize(const svOpenArrayHandle h, int d); XXTERN int svDimensions(const svOpenArrayHandle h); /* * Pointer to the actual representation of the whole array of any type * NULL if not in C layout */ XXTERN void *svGetArrayPtr(const svOpenArrayHandle); /* total size in bytes or 0 if not in C layout */ XXTERN int svSizeOfArray(const svOpenArrayHandle); /* * Return a pointer to an element of the array * or NULL if index outside the range or null pointer */ XXTERN void *svGetArrElemPtr(const svOpenArrayHandle, int indx1, ...); /* specialized versions for 1-, 2- and 3-dimensional arrays: */ XXTERN void *svGetArrElemPtr1(const svOpenArrayHandle, int indx1); XXTERN void *svGetArrElemPtr2(const svOpenArrayHandle, int indx1, int indx2); XXTERN void *svGetArrElemPtr3(const svOpenArrayHandle, int indx1, int indx2, int indx3); /* * Functions for copying between simulator storage and user space. * These functions copy the whole packed array in either direction. * The user is responsible for allocating an array to hold the * canonical representation. */ /* s=source, d=destination */ /* From user space into simulator storage */ XXTERN void svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1, ...); XXTERN void svPutBitArrElem1VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1); XXTERN void svPutBitArrElem2VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1, int indx2); XXTERN void svPutBitArrElem3VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1, int indx2, int indx3); XXTERN void svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1, ...); XXTERN void svPutLogicArrElem1VecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1); XXTERN void svPutLogicArrElem2VecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1, int indx2); XXTERN void svPutLogicArrElem3VecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1, int indx2, int indx3); /* From simulator storage into user space */ XXTERN void svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1, ...); XXTERN void svGetBitArrElem1VecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1); XXTERN void svGetBitArrElem2VecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1, int indx2); XXTERN void svGetBitArrElem3VecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1, int indx2, int indx3); XXTERN void svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, ...); XXTERN void svGetLogicArrElem1VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1); XXTERN void svGetLogicArrElem2VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, int indx2); XXTERN void svGetLogicArrElem3VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, int indx2, int indx3); XXTERN svBit svGetBitArrElem(const svOpenArrayHandle s, int indx1, ...); XXTERN svBit svGetBitArrElem1(const svOpenArrayHandle s, int indx1); XXTERN svBit svGetBitArrElem2(const svOpenArrayHandle s, int indx1, int indx2); XXTERN svBit svGetBitArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int indx3); XXTERN svLogic svGetLogicArrElem(const svOpenArrayHandle s, int indx1, ...); XXTERN svLogic svGetLogicArrElem1(const svOpenArrayHandle s, int indx1); XXTERN svLogic svGetLogicArrElem2(const svOpenArrayHandle s, int indx1, int indx2); XXTERN svLogic svGetLogicArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int indx3); XXTERN void svPutLogicArrElem(const svOpenArrayHandle d, svLogic value, int indx1, ...); XXTERN void svPutLogicArrElem1(const svOpenArrayHandle d, svLogic value, int indx1); XXTERN void svPutLogicArrElem2(const svOpenArrayHandle d, svLogic value, int indx1, int indx2); XXTERN void svPutLogicArrElem3(const svOpenArrayHandle d, svLogic value, int indx1, int indx2, int indx3); XXTERN void svPutBitArrElem(const svOpenArrayHandle d, svBit value, int indx1, ...); XXTERN void svPutBitArrElem1(const svOpenArrayHandle d, svBit value, int indx1); XXTERN void svPutBitArrElem2(const svOpenArrayHandle d, svBit value, int indx1, int indx2); XXTERN void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1, int indx2, int indx3); /* Functions for working with DPI context */ /* * Retrieve the active instance scope currently associated with the executing * imported function. Unless a prior call to svSetScope has occurred, this * is the scope of the function's declaration site, not call site. * Returns NULL if called from C code that is *not* an imported function. */ XXTERN svScope svGetScope( void ); /* * Set context for subsequent export function execution. * This function must be called before calling an export function, unless * the export function is called while executing an import function. In that * case the export function shall inherit the scope of the surrounding import * function. This is known as the "default scope". * The return is the previous active scope (per svGetScope) */ XXTERN svScope svSetScope(const svScope scope); /* Gets the fully qualified name of a scope handle */ XXTERN const char* svGetNameFromScope(const svScope); /* * Retrieve svScope to instance scope of an arbitrary function declaration. * (can be either module, program, interface, or generate scope) * The return value shall be NULL for unrecognized scope names. */ XXTERN svScope svGetScopeFromName(const char* scopeName); /* * Store an arbitrary user data pointer for later retrieval by svGetUserData() * The userKey is generated by the user. It must be guaranteed by the user to * be unique from all other userKey's for all unique data storage requirements * It is recommended that the address of static functions or variables in the * user's C code be used as the userKey. * It is illegal to pass in NULL values for either the scope or userData * arguments. It is also an error to call svPutUserData() with an invalid * svScope. This function returns -1 for all error cases, 0 upon success. It is * suggested that userData values of 0 (NULL) not be used as otherwise it can * be impossible to discern error status returns when calling svGetUserData() */ XXTERN int svPutUserData(const svScope scope, void *userKey, void* userData); /* * Retrieve an arbitrary user data pointer that was previously * stored by a call to svPutUserData(). See the comment above * svPutUserData() for an explanation of userKey, as well as * restrictions on NULL and illegal svScope and userKey values. * This function returns NULL for all error cases, 0 upon success. * This function also returns NULL in the event that a prior call * to svPutUserData() was never made. */ XXTERN void* svGetUserData(const svScope scope, void* userKey); /* * Returns the file and line number in the SV code from which the import call * was made. If this information available, returns TRUE and updates fileName * and lineNumber to the appropriate values. Behavior is unpredictable if * fileName or lineNumber are not appropriate pointers. If this information is * not available return FALSE and contents of fileName and lineNumber not * modified. Whether this information is available or not is implementation- * specific. Note that the string provided (if any) is owned by the SV * implementation and is valid only until the next call to any SV function. * Applications must not modify this string or free it */ XXTERN int svGetCallerInfo(const char** fileName, int *lineNumber); /* * Returns 1 if the current execution thread is in the disabled state. * Disable protocol must be adhered to if in the disabled state. */ XXTERN int svIsDisabledState( void ); /* * Imported functions call this API function during disable processing to * acknowledge that they are correctly participating in the DPI disable protocol. * This function must be called before returning from an imported function that is * in the disabled state. */ XXTERN void svAckDisabledState( void ); /* ********************************************************** * DEPRECATED PORTION OF FILE STARTS FROM HERE. * IEEE-1800-compliant tools may not provide * support for the following functionality. ********************************************************** */ /* * Canonical representation of packed arrays * 2-state and 4-state vectors, modeled upon PLI's avalue/bvalue */ #define SV_CANONICAL_SIZE(WIDTH) (((WIDTH)+31)>>5) typedef unsigned int svBitVec32;/* (a chunk of) packed bit array */ typedef struct { unsigned int c; unsigned int d;} svLogicVec32; /* (a chunk of) packed logic array */ /* reference to a standalone packed array */ typedef void* svBitPackedArrRef; typedef void* svLogicPackedArrRef; /* * total size in bytes of the simulator's representation of a packed array * width in bits */ XXTERN int svSizeOfBitPackedArr(int width); XXTERN int svSizeOfLogicPackedArr(int width); /* Translation between the actual representation and the canonical representation */ /* s=source, d=destination, w=width */ /* actual <-- canonical */ XXTERN void svPutBitVec32(svBitPackedArrRef d, const svBitVec32* s, int w); XXTERN void svPutLogicVec32(svLogicPackedArrRef d, const svLogicVec32* s, int w); /* canonical <-- actual */ XXTERN void svGetBitVec32(svBitVec32* d, const svBitPackedArrRef s, int w); XXTERN void svGetLogicVec32(svLogicVec32* d, const svLogicPackedArrRef s, int w); /* * Bit-select functions * Packed arrays are assumed to be indexed n-1:0, * where 0 is the index of LSB */ /* s=source, i=bit-index */ XXTERN svBit svGetSelectBit(const svBitPackedArrRef s, int i); XXTERN svLogic svGetSelectLogic(const svLogicPackedArrRef s, int i); /* d=destination, i=bit-index, s=scalar */ XXTERN void svPutSelectBit(svBitPackedArrRef d, int i, svBit s); XXTERN void svPutSelectLogic(svLogicPackedArrRef d, int i, svLogic s); /* * functions for part-select * * a narrow (<=32 bits) part-select is copied between * the implementation representation and a single chunk of * canonical representation * Normalized ranges and indexing [n-1:0] are used for both arrays: * the array in the implementation representation and the canonical array. * * s=source, d=destination, i=starting bit index, w=width * like for variable part-selects; limitations: w <= 32 */ /* canonical <-- actual */ XXTERN void svGetPartSelectBit(svBitVec32* d, const svBitPackedArrRef s, int i, int w); XXTERN svBitVec32 svGetBits(const svBitPackedArrRef s, int i, int w); XXTERN svBitVec32 svGet32Bits(const svBitPackedArrRef s, int i); /* 32-bits */ XXTERN uint64_t svGet64Bits(const svBitPackedArrRef s, int i); /* 64-bits */ XXTERN void svGetPartSelectLogic(svLogicVec32* d, const svLogicPackedArrRef s, int i, int w); /* actual <-- canonical */ XXTERN void svPutPartSelectBit(svBitPackedArrRef d, const svBitVec32 s, int i, int w); XXTERN void svPutPartSelectLogic(svLogicPackedArrRef d, const svLogicVec32* s, int i, int w); /* * Functions for open array translation between simulator and canonical * representations. These functions copy the whole packed array in either * direction. The user is responsible for allocating an array in the * canonical representation. */ /* s=source, d=destination */ /* actual <-- canonical */ XXTERN void svPutBitArrElemVec32(const svOpenArrayHandle d, const svBitVec32* s, int indx1, ...); XXTERN void svPutBitArrElem1Vec32(const svOpenArrayHandle d, const svBitVec32* s, int indx1); XXTERN void svPutBitArrElem2Vec32(const svOpenArrayHandle d, const svBitVec32* s, int indx1, int indx2); XXTERN void svPutBitArrElem3Vec32(const svOpenArrayHandle d, const svBitVec32* s, int indx1, int indx2, int indx3); XXTERN void svPutLogicArrElemVec32(const svOpenArrayHandle d, const svLogicVec32* s, int indx1, ...); XXTERN void svPutLogicArrElem1Vec32(const svOpenArrayHandle d, const svLogicVec32* s, int indx1); XXTERN void svPutLogicArrElem2Vec32(const svOpenArrayHandle d, const svLogicVec32* s, int indx1, int indx2); XXTERN void svPutLogicArrElem3Vec32(const svOpenArrayHandle d, const svLogicVec32* s, int indx1, int indx2, int indx3); /* canonical <-- actual */ XXTERN void svGetBitArrElemVec32(svBitVec32* d, const svOpenArrayHandle s, int indx1, ...); XXTERN void svGetBitArrElem1Vec32(svBitVec32* d, const svOpenArrayHandle s, int indx1); XXTERN void svGetBitArrElem2Vec32(svBitVec32* d, const svOpenArrayHandle s, int indx1, int indx2); XXTERN void svGetBitArrElem3Vec32(svBitVec32* d, const svOpenArrayHandle s, int indx1, int indx2, int indx3); XXTERN void svGetLogicArrElemVec32(svLogicVec32* d, const svOpenArrayHandle s, int indx1, ...); XXTERN void svGetLogicArrElem1Vec32(svLogicVec32* d, const svOpenArrayHandle s, int indx1); XXTERN void svGetLogicArrElem2Vec32(svLogicVec32* d, const svOpenArrayHandle s, int indx1, int indx2); XXTERN void svGetLogicArrElem3Vec32(svLogicVec32* d, const svOpenArrayHandle s, int indx1, int indx2, int indx3); /* ********************************************************** * DEPRECATED PORTION OF FILE ENDS HERE. ********************************************************** */ #undef DPI_EXTERN #ifdef DPI_PROTOTYPES #undef DPI_PROTOTYPES #undef XXTERN #undef EETERN #endif #ifdef __cplusplus } #endif #endif verilator-4.038/include/verilated_threads.cpp0000664000177100017500000001477713702133367021361 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // // Copyright 2012-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// /// \file /// \brief Thread pool for verilated modules /// //============================================================================= #include "verilatedos.h" #include "verilated_threads.h" #include std::atomic VlMTaskVertex::s_yields; VL_THREAD_LOCAL VlThreadPool::ProfileTrace* VlThreadPool::t_profilep = NULL; //============================================================================= // VlMTaskVertex VlMTaskVertex::VlMTaskVertex(vluint32_t upstreamDepCount) : m_upstreamDepsDone(0) , m_upstreamDepCount(upstreamDepCount) { assert(atomic_is_lock_free(&m_upstreamDepsDone)); } //============================================================================= // VlWorkerThread VlWorkerThread::VlWorkerThread(VlThreadPool* poolp, bool profiling) : m_waiting(false) , m_ready_size(0) , m_poolp(poolp) , m_profiling(profiling) , m_exiting(false) // Must init this last -- after setting up fields that it might read: , m_cthread(startWorker, this) {} VlWorkerThread::~VlWorkerThread() { m_exiting.store(true, std::memory_order_release); wakeUp(); // The thread should exit; join it. m_cthread.join(); } void VlWorkerThread::workerLoop() { if (VL_UNLIKELY(m_profiling)) m_poolp->setupProfilingClientThread(); ExecRec work; work.m_fnp = NULL; while (true) { if (VL_LIKELY(!work.m_fnp)) dequeWork(&work); // Do this here, not above, to avoid a race with the destructor. if (VL_UNLIKELY(m_exiting.load(std::memory_order_acquire))) break; if (VL_LIKELY(work.m_fnp)) { work.m_fnp(work.m_evenCycle, work.m_sym); work.m_fnp = NULL; } } if (VL_UNLIKELY(m_profiling)) m_poolp->tearDownProfilingClientThread(); } void VlWorkerThread::startWorker(VlWorkerThread* workerp) { workerp->workerLoop(); } //============================================================================= // VlThreadPool VlThreadPool::VlThreadPool(int nThreads, bool profiling) : m_profiling(profiling) { // --threads N passes nThreads=N-1, as the "main" threads counts as 1 unsigned cpus = std::thread::hardware_concurrency(); if (cpus < nThreads + 1) { static int warnedOnce = 0; if (!warnedOnce++) { VL_PRINTF_MT("%%Warning: System has %u CPUs but model Verilated with" " --threads %d; may run slow.\n", cpus, nThreads + 1); } } // Create'em for (int i = 0; i < nThreads; ++i) { m_workers.push_back(new VlWorkerThread(this, profiling)); } // Set up a profile buffer for the current thread too -- on the // assumption that it's the same thread that calls eval and may be // donated to run mtasks during the eval. if (VL_UNLIKELY(m_profiling)) setupProfilingClientThread(); } VlThreadPool::~VlThreadPool() { for (int i = 0; i < m_workers.size(); ++i) { // Each ~WorkerThread will wait for its thread to exit. delete m_workers[i]; } if (VL_UNLIKELY(m_profiling)) tearDownProfilingClientThread(); } void VlThreadPool::tearDownProfilingClientThread() { assert(t_profilep); delete t_profilep; t_profilep = NULL; } void VlThreadPool::setupProfilingClientThread() { assert(!t_profilep); t_profilep = new ProfileTrace; // Reserve some space in the thread-local profiling buffer; // try not to malloc while collecting profiling. t_profilep->reserve(4096); { const VerilatedLockGuard lk(m_mutex); m_allProfiles.insert(t_profilep); } } void VlThreadPool::profileAppendAll(const VlProfileRec& rec) { const VerilatedLockGuard lk(m_mutex); for (ProfileSet::iterator it = m_allProfiles.begin(); it != m_allProfiles.end(); ++it) { // Every thread's profile trace gets a copy of rec. (*it)->emplace_back(rec); } } void VlThreadPool::profileDump(const char* filenamep, vluint64_t ticksElapsed) { const VerilatedLockGuard lk(m_mutex); VL_DEBUG_IF(VL_DBG_MSGF("+prof+threads writing to '%s'\n", filenamep);); FILE* fp = fopen(filenamep, "w"); if (VL_UNLIKELY(!fp)) { VL_FATAL_MT(filenamep, 0, "", "+prof+threads+file file not writable"); // cppcheck-suppress resourceLeak // bug, doesn't realize fp is nullptr return; } // TODO Perhaps merge with verilated_coverage output format, so can // have a common merging and reporting tool, etc. fprintf(fp, "VLPROFTHREAD 1.0 # Verilator thread profile dump version 1.0\n"); fprintf(fp, "VLPROF arg --threads %" VL_PRI64 "u\n", vluint64_t(m_workers.size() + 1)); fprintf(fp, "VLPROF arg +verilator+prof+threads+start+%" VL_PRI64 "u\n", Verilated::profThreadsStart()); fprintf(fp, "VLPROF arg +verilator+prof+threads+window+%u\n", Verilated::profThreadsWindow()); fprintf(fp, "VLPROF stat yields %" VL_PRI64 "u\n", VlMTaskVertex::yields()); vluint32_t thread_id = 0; for (ProfileSet::const_iterator pit = m_allProfiles.begin(); pit != m_allProfiles.end(); ++pit) { ++thread_id; bool printing = false; // False while in warmup phase for (ProfileTrace::const_iterator eit = (*pit)->begin(); eit != (*pit)->end(); ++eit) { switch (eit->m_type) { case VlProfileRec::TYPE_BARRIER: // printing = true; break; case VlProfileRec::TYPE_MTASK_RUN: if (!printing) break; fprintf(fp, "VLPROF mtask %d" " start %" VL_PRI64 "u end %" VL_PRI64 "u elapsed %" VL_PRI64 "u" " predict_time %u cpu %u on thread %u\n", eit->m_mtaskId, eit->m_startTime, eit->m_endTime, (eit->m_endTime - eit->m_startTime), eit->m_predictTime, eit->m_cpu, thread_id); break; default: assert(false); break; // LCOV_EXCL_LINE } } } fprintf(fp, "VLPROF stat ticks %" VL_PRI64 "u\n", ticksElapsed); fclose(fp); } verilator-4.038/verilator-config.cmake.in0000664000177100017500000003507013702133370020401 0ustar wsnyderwsnyder###################################################################### # # DESCRIPTION: CMake configuration file for Verilator # # Include it in your CMakeLists.txt using: # # find_package(verilate) # # This script adds a verilate function. # # add_executable(simulator ) # verilate(simulator SOURCES ) # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### cmake_minimum_required(VERSION 3.8) # Prefer VERILATOR_ROOT from environment if (DEFINED ENV{VERILATOR_ROOT}) set(VERILATOR_ROOT "$ENV{VERILATOR_ROOT}" CACHE PATH "VERILATOR_ROOT") endif() set(VERILATOR_ROOT "${CMAKE_CURRENT_LIST_DIR}" CACHE PATH "VERILATOR_ROOT") find_program(VERILATOR_BIN NAMES verilator_bin verilator_bin.exe HINTS ${VERILATOR_ROOT}/bin ENV VERILATOR_ROOT NO_CMAKE_PATH NO_CMAKE_ENVIRONMENT_PATH NO_CMAKE_SYSTEM_PATH) if (NOT VERILATOR_ROOT) message(FATAL_ERROR "VERILATOR_ROOT cannot be detected. Set it to the appropriate directory (e.g. /usr/share/verilator) as an environment variable or CMake define.") endif() if (NOT VERILATOR_BIN) message(FATAL_ERROR "Cannot find verilator_bin excecutable.") endif() set(verilator_FOUND 1) include(CheckCXXSourceCompiles) function(_verilator_check_cxx_libraries LIBRARIES RESVAR) # Check whether a particular link option creates a valid executable set(_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC "int main() {return 0;}\n") set(CMAKE_REQUIRED_FLAGS) set(CMAKE_REQUIRED_DEFINITIONS) set(CMAKE_REQUIRED_INCLUDES) set(CMAKE_REQUIRED_LINK_OPTIONS) set(CMAKE_REQUIRED_LIBRARIES ${LIBRARIES}) set(CMAKE_REQUIRED_QUIET) check_cxx_source_compiles("${_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC}" "${RESVAR}") set("${RESVAR}" "${${RESVAR}}" PARENT_SCOPE) endfunction() # Check compiler flag support. Skip on MSVC, these are all GCC flags. if (NOT CMAKE_CXX_COMPILER_ID MATCHES MSVC) if (NOT DEFINED VERILATOR_CFLAGS OR NOT DEFINED VERILATOR_MT_CFLAGS) include(CheckCXXCompilerFlag) foreach (FLAG @CFG_CXX_FLAGS_CMAKE@) string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) check_cxx_compiler_flag(${FLAG} ${FLAGNAME}) if (${FLAGNAME}) list(APPEND VERILATOR_CFLAGS ${FLAG}) endif() endforeach() foreach (FLAG @CFG_LDFLAGS_THREADS_CMAKE@) string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) _verilator_check_cxx_libraries("${FLAG}" ${FLAGNAME}) if (${FLAGNAME}) list(APPEND VERILATOR_MT_CFLAGS ${FLAG}) endif() endforeach() endif() endif() define_property(TARGET PROPERTY VERILATOR_THREADED BRIEF_DOCS "Verilator multithreading enabled" FULL_DOCS "Verilator multithreading enabled" ) define_property(TARGET PROPERTY VERILATOR_COVERAGE BRIEF_DOCS "Verilator coverage enabled" FULL_DOCS "Verilator coverage enabled" ) define_property(TARGET PROPERTY VERILATOR_TRACE BRIEF_DOCS "Verilator trace enabled" FULL_DOCS "Verilator trace enabled" ) define_property(TARGET PROPERTY VERILATOR_TRACE_VCD BRIEF_DOCS "Verilator VCD trace enabled" FULL_DOCS "Verilator VCD trace enabled" ) define_property(TARGET PROPERTY VERILATOR_TRACE_FST BRIEF_DOCS "Verilator FST trace enabled" FULL_DOCS "Verilator FST trace enabled" ) define_property(TARGET PROPERTY VERILATOR_SYSTEMC BRIEF_DOCS "Verilator SystemC enabled" FULL_DOCS "Verilator SystemC enabled" ) function(verilate TARGET) cmake_parse_arguments(VERILATE "COVERAGE;TRACE;TRACE_FST;SYSTEMC" "PREFIX;TOP_MODULE;THREADS;DIRECTORY" "SOURCES;VERILATOR_ARGS;INCLUDE_DIRS;OPT_SLOW;OPT_FAST;OPT_GLOBAL" ${ARGN}) if (NOT VERILATE_SOURCES) message(FATAL_ERROR "Need at least one source") endif() if (NOT VERILATE_PREFIX) list(GET VERILATE_SOURCES 0 TOPSRC) get_filename_component(_SRC_NAME ${TOPSRC} NAME_WE) set(VERILATE_PREFIX V${_SRC_NAME}) endif() if (VERILATE_TOP_MODULE) list(APPEND VERILATOR_ARGS --top-module ${VERILATE_TOP_MODULE}) endif() if (VERILATE_THREADS) list(APPEND VERILATOR_ARGS --threads ${VERILATE_THREADS}) endif() if (VERILATE_COVERAGE) list(APPEND VERILATOR_ARGS --coverage) endif() if (VERILATE_TRACE AND VERILATE_TRACE_FST) message(FATAL_ERROR "Cannot have both TRACE and TRACE_FST") endif() if (VERILATE_TRACE) list(APPEND VERILATOR_ARGS --trace) endif() if (VERILATE_TRACE_FST) list(APPEND VERILATOR_ARGS --trace-fst) endif() if (VERILATE_SYSTEMC) list(APPEND VERILATOR_ARGS --sc) else() list(APPEND VERILATOR_ARGS --cc) endif() foreach(INC ${VERILATE_INCLUDE_DIRS}) list(APPEND VERILATOR_ARGS -y "${INC}") endforeach() string(TOLOWER ${CMAKE_CXX_COMPILER_ID} COMPILER) if (COMPILER STREQUAL "appleclang") set(COMPILER clang) elseif (NOT COMPILER MATCHES "^msvc$|^clang$") set(COMPILER gcc) endif() get_target_property(BINARY_DIR "${TARGET}" BINARY_DIR) get_target_property(TARGET_NAME "${TARGET}" NAME) set(VDIR "${BINARY_DIR}/CMakeFiles/${TARGET_NAME}.dir/${VERILATE_PREFIX}.dir") if (VERILATE_DIRECTORY) set(VDIR "${VERILATE_DIRECTORY}") endif() file(MAKE_DIRECTORY ${VDIR}) set(VERILATOR_COMMAND "${VERILATOR_BIN}" --compiler ${COMPILER} --prefix ${VERILATE_PREFIX} --Mdir ${VDIR} --make cmake ${VERILATOR_ARGS} ${VERILATE_VERILATOR_ARGS} ${VERILATE_SOURCES}) set(VARGS_FILE "${VDIR}/verilator_args.txt") set(VCMAKE "${VDIR}/${VERILATE_PREFIX}.cmake") set(VCMAKE_COPY "${VDIR}/${VERILATE_PREFIX}_copy.cmake") if (NOT EXISTS "${VARGS_FILE}" OR NOT EXISTS "${VCMAKE_COPY}") set(VERILATOR_OUTDATED ON) else() file(READ "${VARGS_FILE}" PREVIOUS_VERILATOR_COMMAND) if(NOT VERILATOR_COMMAND STREQUAL PREVIOUS_VERILATOR_COMMAND) set(VERILATOR_OUTDATED ON) endif() endif() if (VERILATOR_OUTDATED) message(STATUS "Executing Verilator...") execute_process( COMMAND ${VERILATOR_COMMAND} WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" RESULT_VARIABLE _VERILATOR_RC OUTPUT_VARIABLE _VERILATOR_OUTPUT ERROR_VARIABLE _VERILATOR_OUTPUT) if (_VERILATOR_RC) string(REPLACE ";" " " VERILATOR_COMMAND_READABLE "${VERILATOR_COMMAND}") message("Verilator command: \"${VERILATOR_COMMAND_READABLE}\"") message("Output:\n${_VERILATOR_OUTPUT}") message(FATAL_ERROR "Verilator command failed (return code=${_VERILATOR_RC})") endif() execute_process(COMMAND "${CMAKE_COMMAND}" -E copy "${VCMAKE}" "${VCMAKE_COPY}") endif() file(WRITE "${VARGS_FILE}" "${VERILATOR_COMMAND}") include("${VCMAKE_COPY}") set(GENERATED_C_SOURCES ${${VERILATE_PREFIX}_CLASSES_FAST} ${${VERILATE_PREFIX}_CLASSES_SLOW} ${${VERILATE_PREFIX}_SUPPORT_FAST} ${${VERILATE_PREFIX}_SUPPORT_SLOW}) foreach(GENERATED_C_SOURCE ${GENERATED_C_SOURCES}) get_filename_component(C_OUTPUT_NAME_WE "${GENERATED_C_SOURCE}" NAME_WE) if(C_OUTPUT_NAME_WE MATCHES ".*Trace.*") continue() endif() list(APPEND GENERATED_H_SOURCES "${VDIR}/${C_OUTPUT_NAME_WE}.h") endforeach() set(GENERATED_SOURCES ${GENERATED_C_SOURCES} ${GENERATED_H_SOURCES}) add_custom_command(OUTPUT ${GENERATED_SOURCES} "${VCMAKE}" COMMAND ${VERILATOR_COMMAND} WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" DEPENDS "${VERILATOR_BIN}" ${${VERILATE_PREFIX}_DEPS} VERBATIM) # Reconfigure if file list has changed # (check contents rather than modified time to avoid unnecessary reconfiguration) add_custom_command(OUTPUT "${VCMAKE_COPY}" COMMAND "${CMAKE_COMMAND}" -E copy_if_different "${VCMAKE}" "${VCMAKE_COPY}" DEPENDS "${VCMAKE}" VERBATIM) if (${VERILATE_PREFIX}_THREADS) # If any verilate() call specifies THREADS, define VL_THREADED in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_THREADED ON) endif() if (${VERILATE_PREFIX}_COVERAGE) # If any verilate() call specifies COVERAGE, define VM_COVERAGE in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_COVERAGE ON) endif() if (${VERILATE_PREFIX}_TRACE_VCD) # If any verilate() call specifies TRACE, define VM_TRACE in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_VCD ON) endif() if (${VERILATE_PREFIX}_TRACE_FST) # If any verilate() call specifies TRACE_FST, define VM_TRACE_FST in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_FST ON) endif() if (${VERILATE_PREFIX}_SC) # If any verilate() call specifies SYSTEMC, define VM_SC in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_SYSTEMC ON) endif() # Add the compile flags only on Verilated sources target_include_directories(${TARGET} PUBLIC ${VDIR}) target_sources(${TARGET} PRIVATE ${GENERATED_SOURCES} "${VCMAKE_COPY}" ${${VERILATE_PREFIX}_GLOBAL} ${${VERILATE_PREFIX}_USER_CLASSES}) foreach(_VSOURCE ${VERILATE_SOURCES} ${${VERILATE_PREFIX}_DEPS}) get_filename_component(_VSOURCE "${_VSOURCE}" ABSOLUTE BASE_DIR) list(APPEND VHD_SOURCES "${_VSOURCE}") endforeach() target_sources(${TARGET} PRIVATE ${VHD_SOURCES}) # Add the compile flags only on Verilated sources foreach(VSLOW ${${VERILATE_PREFIX}_CLASSES_SLOW} ${${VERILATE_PREFIX}_SUPPORT_SLOW}) foreach(OPT_SLOW ${VERILATE_OPT_SLOW} ${${VERILATE_PREFIX}_USER_CFLAGS}) set_property(SOURCE "${VSLOW}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_SLOW}") endforeach() endforeach() foreach(VFAST ${${VERILATE_PREFIX}_CLASSES_FAST} ${${VERILATE_PREFIX}_SUPPORT_FAST}) foreach(OPT_FAST ${VERILATE_OPT_FAST} ${${VERILATE_PREFIX}_USER_CFLAGS}) set_property(SOURCE "${VFAST}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_FAST}") endforeach() endforeach() foreach(VGLOBAL ${${VERILATE_PREFIX}_GLOBAL}) foreach(OPT_GLOBAL ${VERILATE_OPT_GLOBAL} ${${VERILATE_PREFIX}_USER_CFLAGS}) set_property(SOURCE "${VGLOBAL}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_GLOBAL}") endforeach() endforeach() target_include_directories(${TARGET} PUBLIC "${VERILATOR_ROOT}/include" "${VERILATOR_ROOT}/include/vltstd") target_compile_definitions(${TARGET} PRIVATE VM_COVERAGE=$> VM_SC=$> $<$>:VL_THREADED> VM_TRACE=$> VM_TRACE_VCD=$> VM_TRACE_FST=$> ) target_link_libraries(${TARGET} PUBLIC ${${VERILATE_PREFIX}_USER_LDLIBS} "$<$>:${VERILATOR_MT_CFLAGS}>" ) # SystemC requires the C++ version to match the library version, avoid setting anything here set(GEN_THREADED $>) set(GEN_SYSTEMC $>) target_compile_features(${TARGET} PRIVATE $<$>:cxx_std_11> ) endfunction() function(_verilator_find_systemc) if (NOT TARGET Verilator::systemc) # Find SystemC include file "systemc.h" in the following order: # 1. SYSTEMC_INCLUDE (environment) variable # 2. SYSTEMC_ROOT (environment) variable # 3. SYSTEMC (environment) variable # 4. Use CMake module provided by SystemC installation # (eventually requires CMAKE_PREFIX_PATH set) find_path(SYSTEMC_INCLUDEDIR NAMES systemc.h HINTS "${SYSTEMC_INCLUDE} " ENV SYSTEMC_INCLUDE) find_path(SYSTEMC_INCLUDEDIR NAMES systemc.h HINTS "${SYSTEMC_ROOT}" ENV SYSTEMC_ROOT PATH_SUFFIXES include) find_path(SYSTEMC_INCLUDEDIR NAMES systemc.h HINTS "${SYSTEMC}" ENV SYSTEMC PATH_SUFFIXES include) # Find SystemC library in the following order: # 1. SYSTEMC_LIBDIR (environment) variable # 2. SYSTEMC_ROOT (environment) variable # 3. SYSTEMC (environment) variable # 4. Use CMake module provided by SystemC installation # (eventually requires CMAKE_PREFIX_PATH set) # Find SystemC using include and library paths find_library(SYSTEMC_LIBRARY NAMES systemc HINTS "${SYSTEMC_LIBDIR}" ENV SYSTEMC_LIBDIR) find_library(SYSTEMC_LIBRARY NAMES systemc HINTS "${SYSTEMC_ROOT}" ENV SYSTEMC_ROOT PATH_SUFFIXES lib) find_library(SYSTEMC_LIBRARY NAMES systemc HINTS "${SYSTEMC}" ENV SYSTEMC PATH_SUFFIXES lib) if (SYSTEMC_INCLUDEDIR AND SYSTEMC_LIBRARY) add_library(Verilator::systemc INTERFACE IMPORTED) set_target_properties(Verilator::systemc PROPERTIES INTERFACE_INCLUDE_DIRECTORIES "${SYSTEMC_INCLUDEDIR}" INTERFACE_LINK_LIBRARIES "${SYSTEMC_LIBRARY}") return() endif() find_package(SystemCLanguage QUIET) if (SystemCLanguage_FOUND) add_library(Verilator::systemc INTERFACE IMPORTED) set_target_properties(Verilator::systemc PROPERTIES INTERFACE_LINK_LIBRARIES "SystemC::systemc") return() endif() message("SystemC not found. This can be fixed by doing either of the following steps:") message("- set the SYSTEMC_INCLUDE and SYSTEMC_LIBDIR (environment) variables; or") message("- set SYSTEMC_ROOT (environment) variable; or") message("- set SYSTEMC (environment) variable; or") message("- use the CMake module of your SystemC installation (may require CMAKE_PREFIX_PATH)") message(FATAL_ERROR "SystemC not found") endif() endfunction() function(verilator_link_systemc TARGET) _verilator_find_systemc() target_link_libraries("${TARGET}" PUBLIC Verilator::systemc) target_compile_options(${TARGET} PRIVATE $ENV{SYSTEMC_CXX_FLAGS} ${SYSTEMC_CXX_FLAGS}) endfunction() function(verilator_generate_key OUTPUT_VARIABLE) execute_process(COMMAND ${VERILATOR_BIN} --generate-key OUTPUT_VARIABLE KEY_VAL RESULT_VARIABLE KEY_RET) if (KEY_RET) message(FATAL_ERROR "verilator --generate-key failed") endif() string(STRIP ${KEY_VAL} KEY_VAL) set(${OUTPUT_VARIABLE} ${KEY_VAL} PARENT_SCOPE) endfunction() verilator-4.038/README.adoc0000664000177100017500000001565313702133367015320 0ustar wsnyderwsnyder// Github doesn't render images unless absolute URL :!toc: ifdef::env-github[] image:https://img.shields.io/badge/License-LGPL%20v3-blue.svg[license LGPLv3,link=https://www.gnu.org/licenses/lgpl-3.0] image:https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg[license Artistic-2.0,link=https://opensource.org/licenses/Artistic-2.0] image:https://api.codacy.com/project/badge/Grade/fa78caa433c84a4ab9049c43e9debc6f[Code Quality,link=https://www.codacy.com/gh/verilator/verilator] image:https://codecov.io/gh/verilator/verilator/branch/master/graph/badge.svg[Coverage,link=https://codecov.io/gh/verilator/verilator] image:https://travis-ci.com/verilator/verilator.svg?branch=master[Build Status (Travis CI),link=https://travis-ci.com/verilator/verilator] endif::[] ifdef::env-github[] :link_verilator_contributing: link:docs/CONTRIBUTING.adoc :link_verilator_install: link:docs/install.adoc endif::[] ifndef::env-github[] :link_verilator_contributing: https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.adoc :link_verilator_install: https://verilator.org/install endif::[] :link_verilator_commercial_support: https://verilator.org/verilator_commercial_support == Welcome to Verilator [cols="a,a",indent=0,frame="none",grid="rows"] |=== ^.^| *Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.* +++
+++ • Accepts synthesizable Verilog or SystemVerilog +++
+++ • Performs lint code-quality checks +++
+++ • Compiles into multithreaded {cpp}, or SystemC +++
+++ • Creates XML to front-end your own tools <.^|image:https://www.veripool.org/img/verilator_256_200_min.png[Logo,256,200] >.^|image:https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png[,388,178] ^.^| *Fast* +++
+++ • Outperforms many commercial simulators +++
+++ • Single- and multi-threaded output models ^.^| *Widely Used* +++
+++ • Wide industry and academic deployment +++
+++ • Out-of-the-box support from Arm, and RISC-V vendor IP <.^|image:https://www.veripool.org/img/verilator_usage_400x200-min.png[,400,200] >.^|image:https://www.veripool.org/img/verilator_community_400x125-min.png[,400,125] ^.^| *Community Driven & Openly Licensed* +++
+++ • Guided by the https://chipsalliance.org/[CHIPS Alliance] and https://www.linuxfoundation.org/[Linux Foundation] +++
+++ • Open, and free as in both speech and beer +++
+++ • More simulation for your verification budget ^.^| *Commercial Support Available* +++
+++ • Commercial support contracts +++
+++ • Design support contracts +++
+++ • Enhancement contracts <.^|image:https://www.veripool.org/img/verilator_support_400x125-min.png[,400,125] |=== == What Verilator Does Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files, the "Verilated" code. The user writes a little {cpp}/SystemC wrapper file, which instantiates the "Verilated" model of the user's top level module. These {cpp}/SystemC files are then compiled by a {cpp} compiler (gcc/clang/MSVC++). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators. Verilator may not be the best choice if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator, or if you are looking for a behavioral Verilog simulator e.g. for a quick class project (we recommend http://iverilog.icarus.com[Icarus Verilog] for this.) However, if you are looking for a path to migrate SystemVerilog to {cpp} or SystemC, or your team is comfortable writing just a touch of {cpp} code, Verilator is the tool for you. == Performance Verilator does not simply convert Verilog HDL to {cpp} or SystemC. Rather, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a {cpp}/SystemC module. The results are a compiled Verilog model that executes even on a single-thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as http://iverilog.icarus.com[Icarus Verilog]. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators). Verilator has typically similar or better performance versus the closed-source Verilog simulators (Carbon Design Systems Carbonator, Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus Verilator gives you the best cycles/dollar. For more information on how Verilator stacks up to some of the other closed-sourced and open-sourced Verilog simulators, see the https://www.veripool.org/verilog_sim_benchmarks.html[Verilog Simulator Benchmarks]. (If you benchmark Verilator, please see the notes in the https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)], and also if possible post on the forums the results; there may be additional tweaks possible.) == Installation & Documentation For more information: * {link_verilator_install}[Verilator installation and package directory structure] * https://verilator.org/verilator_doc.html[Verilator manual (HTML)], or https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)] * https://github.com/verilator/verilator-announce[Subscribe to verilator announcements] * https://verilator.org/forum[Verilator forum] * https://verilator.org/issues[Verilator issues] == Support Verilator is a community project, guided by the https://chipsalliance.org/[CHIPS Alliance] under the https://www.linuxfoundation.org/[Linux Foundation]. We appreciate and welcome your contributions in whatever form; please see {link_verilator_contributing}[Contributing to Verilator]. Thanks to our https://verilator.org/verilator_doc.html#CONTRIBUTORS[Contributors and Sponsors]. Verilator also supports and encourages commercial support models and organizations; please see {link_verilator_commercial_support}[Verilator Commercial Support]. == Related Projects * http://gtkwave.sourceforge.net/[GTKwave] - Waveform viewer for Verilator traces. * http://iverilog.icarus.com[Icarus Verilog] - Icarus is a full featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may. == Open License Verilator is Copyright 2003-2020 by Wilson Snyder. (Report bugs to https://verilator.org/issues[Verilator Issues].) Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See the documentation for more details. verilator-4.038/verilator.pc.in0000664000177100017500000000045213702133370016454 0ustar wsnyderwsnyderprefix=@prefix@ exec_prefix=@exec_prefix@ libdir=@libdir@ datarootdir=@datarootdir@ includedir=@pkgdatadir@/include Name: verilator Description: fast free Verilog simulator URL: https://verilator.org Version: @PACKAGE_VERSION_NUMBER@ Requires: Libs: Cflags: -I${includedir} -I${includedir}/vltstd verilator-4.038/test_regress/0000775000177100017500000000000013702335701016226 5ustar wsnyderwsnyderverilator-4.038/test_regress/Makefile_obj0000664000177100017500000000275313702133367020533 0ustar wsnyderwsnyder# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside object directory # # This is executed in the object directory, and called by ../Makefile # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #***************************************************************************** default: $(VM_PREFIX) include $(VM_PREFIX).mk # So t/t_foobar.cpp is found (due to test_regress using -Mdir) VPATH += ../.. ####################################################################### # Needed by DPI tests CPPFLAGS += -DVERILATOR=1 # Debugging CPPFLAGS += -DVL_DEBUG=1 # Assertions disabled as SystemC libraries are not clean #CPPFLAGS += -D_GLIBCXX_DEBUG # Needed by tracing routines CPPFLAGS += -DTEST_OBJ_DIR=$(TEST_OBJ_DIR) CPPFLAGS += -DVM_PREFIX=$(VM_PREFIX) CPPFLAGS += -DVM_PREFIX_INCLUDE="<$(VM_PREFIX).h>" CPPFLAGS += $(CPPFLAGS_DRIVER) CPPFLAGS += $(CPPFLAGS_DRIVER2) CPPFLAGS += $(CPPFLAGS_ADD) ifeq ($(CFG_WITH_LONGTESTS),yes) ifeq ($(DRIVER_STD),newest) CPPFLAGS += $(CFG_CXXFLAGS_STD_NEWEST) else ifeq ($(DRIVER_STD),oldest) CPPFLAGS += $(CFG_CXXFLAGS_STD_OLDEST) endif endif ####################################################################### verilator-4.038/test_regress/input.vc0000664000177100017500000000007413702133367017724 0ustar wsnyderwsnyder +librescan +libext+.v -y t +incdir+t +incdir+../include verilator-4.038/test_regress/Makefile0000664000177100017500000000510013702133367017666 0ustar wsnyderwsnyder#***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside source directory # # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ default: test # This must point to the root of the VERILATOR kit VERILATOR_ROOT := $(shell pwd)/.. export VERILATOR_ROOT # Pick up PERL and other variable settings include $(VERILATOR_ROOT)/include/verilated.mk ###################################################################### ifneq ($(VCS_HOME),) #Default to off, even with vcs; not all tests are ensured to be working #PRODUCTS += --vcs endif ifneq ($(NC_ROOT),) #Default to off, even with vcs; not all tests are ensured to be working #PRODUCTS += --nc endif # Run tests in parallel. Requires Parallel::Forker to be installed. ifeq ($(CFG_WITH_LONGTESTS),yes) DRIVER_FLAGS ?= -j 0 --quiet --rerun endif .SUFFIXES: ###################################################################### SCENARIOS ?= --vlt --vltmt --dist DRIVER_HASHSET ?= .PHONY: test test: $(PERL) driver.pl $(DRIVER_FLAGS) $(SCENARIOS) $(DRIVER_HASHSET) ###################################################################### vcs: $(PERL) driver.pl $(DRIVER_FLAGS) --vcs --stop ###################################################################### nc: $(PERL) driver.pl $(DRIVER_FLAGS) --nc --stop ###################################################################### vlt: $(PERL) driver.pl $(DRIVER_FLAGS) --vlt --stop vltmt: $(PERL) driver.pl $(DRIVER_FLAGS) --vltmt --stop ###################################################################### random: $(PERL) driver.pl $(DRIVER_FLAGS) --optimize : --stop random_forever: while ( VERILATOR_NO_DEBUG=1 CPPFLAGS_ADD=-Wno-error $(MAKE) random ) ; do \ echo ; \ done ####################################################################### # Informational - used by some tests print-cxx-version: $(CXX) --version ###################################################################### maintainer-copy:: clean mostlyclean distclean maintainer-clean:: -rm -rf obj_* simv* simx* csrc cov_work INCA_libs *.log *.key logs vc_hdrs.h -rm -rf t/obj_* verilator-4.038/test_regress/driver.pl0000775000177100017500000027241313702133367020076 0ustar wsnyderwsnyder#!/usr/bin/env perl # See copyright, etc in below POD section. ###################################################################### require 5.006_001; use warnings; use Cwd; BEGIN { if (!$ENV{VERILATOR_ROOT} && -x "../bin/verilator") { $ENV{VERILATOR_ROOT} = Cwd::getcwd()."/.."; } $ENV{MAKE} ||= "make"; $ENV{CXX} ||= "c++"; } use Getopt::Long; use IO::File; use Pod::Usage; use Data::Dumper; $Data::Dumper::Sortkeys=1; use FindBin qw($RealBin); use strict; use vars qw($Debug %Vars $Driver $Fork); use version; use POSIX qw(strftime); use lib "."; use Time::HiRes qw(usleep); use Digest::MD5 qw(md5); $::Driver = 1; $::Have_Forker = 0; eval "use Parallel::Forker; \$Fork=Parallel::Forker->new(use_sig_child=>1, poll_interval=>10*1000); \$::Have_Forker=1;"; $Fork = Forker->new(use_sig_child=>1) if !$Fork; my $forker_Min_Version = 1.258; if ($::Have_Forker && $Parallel::Forker::VERSION < $forker_Min_Version) { print STDERR "driver.pl: Parallel::Forker is older than $forker_Min_Version, suggest 'cpan install Parallel::Forker'\n"; $::Have_Forker = 0; } $SIG{CHLD} = sub { $Fork->sig_child() if $Fork; }; $SIG{TERM} = sub { $Fork->kill_tree_all('TERM') if $Fork; die "Quitting...\n"; }; #====================================================================== # Map of all scenarios, with the names used to enable them our %All_Scenarios = (dist => [ "dist"], atsim => [ "simulator", "simulator_st", "atsim"], ghdl => ["linter", "simulator", "simulator_st", "ghdl"], iv => [ "simulator", "simulator_st", "iv"], ms => ["linter", "simulator", "simulator_st", "ms"], nc => ["linter", "simulator", "simulator_st", "nc"], vcs => ["linter", "simulator", "simulator_st", "vcs"], xsim => ["linter", "simulator", "simulator_st", "xsim"], vlt => ["linter", "simulator", "simulator_st", "vlt_all", "vlt"], vltmt => [ "simulator", "vlt_all", "vltmt"], ); #====================================================================== # main autoflush STDOUT 1; autoflush STDERR 1; our @Orig_ARGV = @ARGV; our @Orig_ARGV_Sw; foreach (@Orig_ARGV) { push @Orig_ARGV_Sw, $_ if /^-/ && !/^-j/; } our $Start = time(); our $Vltmt_threads = 3; $Debug = 0; my $opt_benchmark; my @opt_tests; my $opt_dist; my $opt_gdb; my $opt_rr; my $opt_gdbbt; my $opt_gdbsim; my $opt_hashset; my $opt_jobs = 1; my $opt_optimize; my $opt_quiet; my $opt_rerun; my $opt_rrsim; my %opt_scenarios; my $opt_site; my $opt_stop; my $opt_trace; my $opt_verbose; my $Opt_Verilated_Debug; our $Opt_Unsupported; our $Opt_Verilation = 1; our @Opt_Driver_Verilator_Flags; Getopt::Long::config("pass_through"); if (! GetOptions( "benchmark:i" => sub { $opt_benchmark = $_[1] ? $_[1] : 1; }, "debug" => \&debug, #debugi see parameter() "gdb!" => \$opt_gdb, "gdbbt!" => \$opt_gdbbt, "gdbsim!" => \$opt_gdbsim, "golden!" => sub { $ENV{HARNESS_UPDATE_GOLDEN} = 1; }, "hashset=s" => \$opt_hashset, "help" => \&usage, "j=i" => \$opt_jobs, "optimize:s" => \$opt_optimize, "quiet!" => \$opt_quiet, "rerun!" => \$opt_rerun, "rr!" => \$opt_rr, "rrsim!" => \$opt_rrsim, "site!" => \$opt_site, "stop!" => \$opt_stop, "trace!" => \$opt_trace, "unsupported!"=> \$Opt_Unsupported, "verbose!" => \$opt_verbose, "verilation!" => \$Opt_Verilation, # Undocumented debugging "verilated-debug!" => \$Opt_Verilated_Debug, #W see parameter() # Scenarios "atsim|athdl!"=> sub { $opt_scenarios{atsim} = $_[1]; }, "dist!" => sub { $opt_scenarios{dist} = $_[1]; }, "ghdl!" => sub { $opt_scenarios{ghdl} = $_[1]; }, "iv!" => sub { $opt_scenarios{iv} = $_[1]; }, "ms!" => sub { $opt_scenarios{ms} = $_[1]; }, "nc!" => sub { $opt_scenarios{nc} = $_[1]; }, "vlt!" => sub { $opt_scenarios{vlt} = $_[1]; }, "vltmt!" => sub { $opt_scenarios{vltmt} = $_[1]; }, "vcs!" => sub { $opt_scenarios{vcs} = $_[1]; }, "xsim!" => sub { $opt_scenarios{xsim} = $_[1]; }, "<>" => \¶meter, )) { die "%Error: Bad usage, try '$0 --help'\n"; } $opt_jobs = calc_jobs() if defined $opt_jobs && $opt_jobs==0; $Fork->max_proc($opt_jobs); if ((scalar keys %opt_scenarios) < 1) { $opt_scenarios{dist} = 1; $opt_scenarios{vlt} = 1; } our @Test_Dirs = "t"; push @Test_Dirs, split(/:/,$ENV{VERILATOR_TESTS_SITE}) if (($#opt_tests<0 ? $opt_site : 1) && $ENV{VERILATOR_TESTS_SITE}); if ($#opt_tests<0) { # Run everything my %uniq; foreach my $dir (@Test_Dirs) { my @stats = stat($dir); # Uniquify by inode, so different paths to same place get combined next if !$stats[1] || $uniq{$stats[1]}++; push @opt_tests, sort(glob("${dir}/t_*.pl")); } } @opt_tests = _calc_hashset(@opt_tests) if $opt_hashset; if ($#opt_tests>=2 && $opt_jobs>=2) { # Without this tests such as t_debug_sigsegv_bt_bad.pl will occasionally # block on input and cause a SIGSTOP, then a "fg" was needed to resume testing. if (!$::Have_Forker) { print STDERR "driver.pl: NO_FORKER: For faster testing 'sudo cpan install Parallel::Forker'\n"; } print STDERR "== Many jobs; redirecting STDIN\n"; open(STDIN, "+>/dev/null"); } mkdir "obj_dist"; my $timestart = strftime("%Y%m%d_%H%M%S", localtime); my $runner; { $runner = Runner->new( driver_log_filename => "obj_dist/driver_${timestart}.log", quiet => $opt_quiet); foreach my $testpl (@opt_tests) { foreach my $scenario (sort keys %opt_scenarios) { next if !$opt_scenarios{$scenario}; $runner->one_test(pl_filename => $testpl, $scenario => 1); } } $runner->wait_and_report; } if ($opt_rerun && $runner->fail_count) { print("="x70,"\n"); print("="x70,"\n"); print("RERUN ==\n\n"); # Avoid parallel run to ensure that isn't causing problems # If > 10 failures something more wrong and get results quickly $Fork->max_proc(1) unless $runner->fail_count > 10; my $orig_runner = $runner; $runner = Runner->new( driver_log_filename => "obj_dist/driver_${timestart}_rerun.log", quiet => 0, fail1_cnt => $orig_runner->fail_count, ok_cnt => $orig_runner->{ok_cnt}, skip_cnt => $orig_runner->{skip_cnt}, unsup_cnt => $orig_runner->{unsup_cnt}); foreach my $test (@{$orig_runner->{fail_tests}}) { $test->clean; # Reschedule test $runner->one_test(pl_filename => $test->{pl_filename}, $test->{scenario} => 1); } $runner->wait_and_report; } exit(10) if $runner->fail_count; #---------------------------------------------------------------------- sub usage { pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT); exit(1); # Unreachable } sub debug { $Debug = 1; push @Opt_Driver_Verilator_Flags, "--debug --no-skip-identical"; } our $_Parameter_Next_Level; sub parameter { my $param = shift; if ($_Parameter_Next_Level) { ($param =~ /^(\d+)$/) or die "%Error: Expected number following $_Parameter_Next_Level: $param\n"; push @Opt_Driver_Verilator_Flags, $param; $_Parameter_Next_Level = undef; } elsif ($param =~ /\.pl/) { push @opt_tests, $param; } elsif ($param =~ /^-?(-debugi|-dump-treei)/) { push @Opt_Driver_Verilator_Flags, $param; $_Parameter_Next_Level = $param; } elsif ($param =~ /^-?(-W||-debug-check)/) { push @Opt_Driver_Verilator_Flags, $param; } else { die "%Error: Unknown parameter: $param\n"; } } sub max_procs { my $ok = eval " use Unix::Processors; return Unix::Processors->new->max_online; "; return $ok; } sub calc_threads { my $default = shift; my $ok = max_procs(); $ok && !$@ or return $default; return ($ok < $default) ? $ok : $default; } sub calc_jobs { my $ok = max_procs(); $ok && !$@ or die "%Error: Can't use -j: $@\n"; print "driver.pl: Found $ok cores, using -j ",$ok+1,"\n"; return $ok + 1; } sub _calc_hashset { my @in = @_; return @in if !$opt_hashset; $opt_hashset =~ m!^(\d+)/(\d+)$! or die "%Error: Need number/number format for --hashset: $opt_hashset\n"; my ($set, $nsets) = ($1, $2); my @new; foreach my $t (@opt_tests) { my $checksum = unpack('L', substr(md5($t), 0, 4)); if (($set % $nsets) == ($checksum % $nsets)) { push @new, $t; } } return @new; } ####################################################################### ####################################################################### ####################################################################### ####################################################################### # Runner class package Runner; use strict; sub new { my $class = shift; my $self = { # Parameters driver_log_filename => undef, quiet => 0, # Counts all_cnt => 0, left_cnt => 0, ok_cnt => 0, fail1_cnt => 0, fail_cnt => 0, skip_cnt => 0, unsup_cnt => 0, skip_msgs => [], fail_msgs => [], fail_tests => [], # Per-task identifiers running_ids => {}, @_}; bless $self, $class; return $self; } sub fail_count { return $_[0]->{fail_cnt}; } sub one_test { my $self = shift; my @params = @_; my %params = (@params); $self->{all_cnt}++; $self->{left_cnt}++; $::Fork->schedule ( test_pl_filename => $params{pl_filename}, run_pre_start => sub { my $process = shift; # Running in context of parent, before run_on_start # Make an identifier that is unique across all current running jobs my $i = 1; while (exists $self->{running_ids}{$i}) { ++$i; } $process->{running_id} = $i; $self->{running_ids}{$process->{running_id}} = 1; }, run_on_start => sub { my $process = shift; # Running in context of child, so can't pass data to parent directly if ($self->{quiet}) { open(STDOUT, ">/dev/null"); open(STDERR, ">&STDOUT"); } print("="x70,"\n"); my $test = VTest->new(@params, running_id => $process->{running_id}); $test->oprint("="x50,"\n"); unlink $test->{status_filename}; $test->_prep; $test->_read; # Don't put anything other than _exit after _read, # as may call _exit via another path $test->_exit; }, run_on_finish => sub { # Running in context of parent my $process = shift; my $test = VTest->new(@params, running_id => $process->{running_id}); $test->_read_status; if ($test->ok) { $self->{ok_cnt}++; } elsif ($test->scenario_off && !$test->errors) { } elsif ($test->skips && !$test->errors) { push @{$self->{skip_msgs}}, ("\t#".$test->soprint("-Skip: $test->{skips}\n")); $self->{skip_cnt}++; } elsif ($test->unsupporteds && !$test->errors) { $self->{unsup_cnt}++; } else { $test->oprint("FAILED: $test->{errors}\n"); my $j = ($opt_jobs>1?" -j":""); my $makecmd = $ENV{VERILATOR_MAKE} || "$ENV{MAKE}$j &&"; my $upperdir = (Cwd::getcwd() =~ /test_regress/ ? 'test_regress/' : ''); push @{$self->{fail_msgs}}, ("\t#".$test->soprint("%Error: $test->{errors}\n") ."\t\t$makecmd " .$upperdir.$test->{pl_filename} ." ".join(' ', _manual_args()) ." --".$test->{scenario}."\n"); push @{$self->{fail_tests}}, $test; $self->{fail_cnt}++; $self->report($self->{driver_log_filename}); my $other = ""; foreach my $proc ($::Fork->running) { $other .= " ".$proc->{test_pl_filename}; } $test->oprint("Simultaneous running tests:",$other,"\n") if $other && !$opt_quiet; if ($opt_stop) { die "%Error: --stop and errors found\n"; } } $self->{left_cnt}--; $self->print_summary; delete $self->{running_ids}{$process->{running_id}} if $process->{running_id}; }, )->ready(); } sub wait_and_report { my $self = shift; $self->print_summary(force=>1); # Wait for all children to finish while ($::Fork->is_any_left) { $::Fork->poll; if ((time() - ($self->{_last_summary_time} || 0) >= 30) && (!$opt_gdb && !$opt_gdbsim)) { # Don't show for interactive gdb etc $self->print_summary(force=>1, show_running=>1); } Time::HiRes::usleep 100*1000; } $runner->report(undef); $runner->report($self->{driver_log_filename}); } sub report { my $self = shift; my $filename = shift; my $fh = \*STDOUT; if ($filename) { $fh = IO::File->new(">$filename") or die "%Error: $! writing $filename,"; } $fh->print("\n"); $fh->print("="x70,"\n"); foreach my $f (sort @{$self->{fail_msgs}}) { chomp $f; $fh->print("$f\n"); } foreach my $f (sort @{$self->{skip_msgs}}) { chomp $f; $fh->print("$f\n"); } my $sum = ($self->{fail_cnt} && "FAILED" || $self->{skip_cnt} && "PASSED w/SKIPS" || "PASSED"); $fh->print("TESTS DONE, $sum: ".$self->sprint_summary."\n"); } sub print_summary { my $self = shift; my %params = (force => 0, # Force printing show_running => 0, # Show running processes @_); if (!$self->{quiet} || $params{force} || ($self->{left_cnt} < 5) || (time() - ($self->{_last_summary_time} || 0) >= 15)) { # Don't show for interactive gdb etc $self->{_last_summary_time} = time(); print STDERR ("==SUMMARY: ".$self->sprint_summary."\n"); if ($params{show_running}) { my $other; foreach my $proc ($::Fork->running) { $other .= " ".$proc->{test_pl_filename}; } print STDERR ("==STILL RUNNING: ".$other."\n"); } } } sub sprint_summary { my $self = shift; my $delta = time() - $::Start; my $leftmsg = $::Have_Forker ? $self->{left_cnt} : "NO-FORKER"; my $pct = int(100*($self->{left_cnt} / ($self->{all_cnt} + 0.001)) + 0.999); my $eta = ($self->{all_cnt} * ($delta / (($self->{all_cnt} - $self->{left_cnt})+0.001))) - $delta; $eta = 0 if $delta < 10; my $out = ""; $out .= "Left $leftmsg " if $self->{left_cnt}; $out .= "Passed $self->{ok_cnt}"; # Ordered below most severe to least severe $out .= " Failed $self->{fail_cnt}"; $out .= " Failed-First $self->{fail1_cnt}" if $self->{fail1_cnt}; $out .= " Skipped $self->{skip_cnt}" if $self->{skip_cnt}; $out .= " Unsup $self->{unsup_cnt}"; $out .= sprintf(" Eta %d:%02d", int($eta/60), $eta%60) if $self->{left_cnt} > 10 && $eta > 10; $out .= sprintf(" Time %d:%02d", int($delta/60), $delta%60); return $out; } sub _manual_args { # Return command line with scenarios stripped my @out; arg: foreach my $arg (@Orig_ARGV_Sw) { foreach my $allsc (keys %All_Scenarios) { foreach my $allscarg (@{$All_Scenarios{$allsc}}) { next arg if ("--$allscarg" eq $arg); } } # Also strip certain flags that per-test debugging won't want next arg if $arg eq '--rerun'; next arg if $arg eq '--quiet'; push @out, $arg; } return @out; } ####################################################################### ####################################################################### ####################################################################### ####################################################################### # Test class package VTest; use Carp; use Cwd; use Data::Dumper; use File::Spec; use File::Path qw(mkpath); use vars qw($Self $Self); use strict; sub defineOpt { my $xsim = shift; return $xsim ? "--define " : "+define+"; } sub new { my $class = shift; my $self = {@_}; $self->{name} ||= $2 if $self->{pl_filename} =~ m!^(.*/)?([^/]*)\.pl$!; $self->{scenario} = ""; $self->{scenario} ||= "dist" if $self->{dist}; $self->{scenario} ||= "atsim" if $self->{atsim}; $self->{scenario} ||= "ghdl" if $self->{ghdl}; $self->{scenario} ||= "vcs" if $self->{vcs}; $self->{scenario} ||= "vlt" if $self->{vlt}; $self->{scenario} ||= "vltmt" if $self->{vltmt}; $self->{scenario} ||= "nc" if $self->{nc}; $self->{scenario} ||= "ms" if $self->{ms}; $self->{scenario} ||= "iv" if $self->{iv}; $self->{scenario} ||= "xsim" if $self->{xsim}; foreach my $dir (@::Test_Dirs) { # t_dir used both absolutely and under obj_dir if (-e "$dir/$self->{name}.pl") { # Note most tests require error messages of the form t/x.v # Therefore pl_filename must be t/ for local tests $self->{pl_filename} = File::Spec->abs2rel("$dir/$self->{name}.pl"); # t_dir must be absolute - used under t or under obj_dir $self->{t_dir} ||= File::Spec->rel2abs($dir); last; } } $self->{t_dir} or die "%Error: Can't locate dir for $self->{name},"; if (!$self->{obj_dir}) { my $scen_dir = File::Spec->abs2rel("$self->{t_dir}/../obj_$self->{scenario}"); $scen_dir =~ s!^t/\.\./!!; # Simplify filenames on local runs mkdir $scen_dir; # Not a mkpath so find out if trying to build somewhere odd $self->{obj_dir} ="$scen_dir/$self->{name}"; } my $define_opt = defineOpt($self->{xsim}); $self = { name => undef, # Set below, name of this test pl_filename => undef, # Name of .pl file to get setup from make_top_shell => 1, # Make a default __top.v file make_main => 1, # Make __main.cpp make_pli => 0, # need to compile pli sc_time_resolution => "SC_PS", # Keep - PS is SystemC default sim_time => 1100, benchmark => $opt_benchmark, verbose => $opt_verbose, run_env => '', # All compilers v_flags => [split(/\s+/, (($self->{xsim} ? " -f input.xsim.vc " : (-r 'input.vc' ? " -f input.vc " : "")) .($self->{t_dir} !~ m!/test_regress! # Don't include standard dir, only site's ? " +incdir+$self->{t_dir} -y $self->{t_dir}" : "") . " ".$define_opt."TEST_OBJ_DIR=$self->{obj_dir}" .($opt_verbose ? " ".$define_opt."TEST_VERBOSE=1":"") .($opt_benchmark ? " ".$define_opt."TEST_BENCHMARK=$opt_benchmark":"") .($opt_trace ? " ".$define_opt."WAVES=1":"") ))], v_flags2 => [], # Overridden in some sim files v_other_filenames => [], # After the filename so we can spec multiple files all_run_flags => [], pli_flags => ["-I$ENV{VERILATOR_ROOT}/include/vltstd -fPIC -shared" .(($^O eq "darwin" ) ? " -Wl,-undefined,dynamic_lookup" : " -export-dynamic") ." -o $self->{obj_dir}/libvpi.so"], # ATSIM atsim => 0, atsim_flags => [split(/\s+/,"-c +sv +define+ATSIM"), "+sv_dir+$self->{obj_dir}/.athdl_compile"], atsim_flags2 => [], # Overridden in some sim files atsim_run_flags => [], # GHDL ghdl => 0, ghdl_work_dir => "$self->{obj_dir}/ghdl_compile", ghdl_flags => [($::Debug?"-v":""), "--workdir=$self->{obj_dir}/ghdl_compile", ], ghdl_flags2 => [], # Overridden in some sim files ghdl_run_flags => [], # IV iv => 0, iv_flags => [split(/\s+/,"+define+IVERILOG -g2012 -o $self->{obj_dir}/simiv")], iv_flags2 => [], # Overridden in some sim files iv_pli => 0, # need to use pli iv_run_flags => [], # VCS vcs => 0, vcs_flags => [split(/\s+/,"+vcs+lic+wait +cli -debug_access +define+VCS+1 -q -sverilog -CFLAGS '-DVCS' ")], vcs_flags2 => [], # Overridden in some sim files vcs_run_flags => [split(/\s+/,"+vcs+lic_wait")], # NC nc => 0, nc_flags => [split(/\s+/,("+licqueue +nowarn+LIBNOU +define+NC=1 -q +assert +sv -c " .($opt_trace ? " +access+r":"")))], nc_flags2 => [], # Overridden in some sim files nc_run_flags => [split(/\s+/,"+licqueue -q +assert +sv -R")], # ModelSim ms => 0, ms_flags => [split(/\s+/, ("-sv -work $self->{obj_dir}/work +define+MS=1 -ccflags \"-DMS=1\""))], ms_flags2 => [], # Overridden in some sim files ms_pli => 1, # need to use pli ms_run_flags => [split(/\s+/,"-lib $self->{obj_dir}/work -c -do 'run -all;quit' ")], # XSim xsim => 0, xsim_flags => [split(/\s+/,("--nolog --sv --define XSIM --work $self->{name}=$self->{obj_dir}/xsim"))], xsim_flags2 => [], # Overridden in some sim files xsim_run_flags => [split(/\s+/,("--nolog --runall --lib $self->{name}=$self->{obj_dir}/xsim" .($opt_trace ? " --debug all":"")))], xsim_run_flags2 => [], # Overridden in some sim files # Verilator vlt => 0, vltmt => 0, verilator_flags => ["-cc", "-Mdir $self->{obj_dir}", "-OD", # As currently disabled unless -O3 "--debug-check", "--comp-limit-members 10", ], verilator_flags2 => [], verilator_flags3 => ["--clk clk"], verilator_make_gmake => 1, verilator_make_cmake => 0, verilated_debug => $Opt_Verilated_Debug, stdout_filename => undef, # Redirect stdout %$self}; bless $self, $class; $self->{vlt_all} = $self->{vlt} || $self->{vltmt}; # Any Verilator scenario $self->{VM_PREFIX} ||= "V".$self->{name}; $self->{stats} ||= "$self->{obj_dir}/V".$self->{name}."__stats.txt"; $self->{status_filename} ||= "$self->{obj_dir}/V".$self->{name}.".status"; $self->{run_log_filename} ||= "$self->{obj_dir}/vlt_sim.log"; $self->{coverage_filename} ||= "$self->{obj_dir}/coverage.dat"; $self->{main_filename} ||= "$self->{obj_dir}/$self->{VM_PREFIX}__main.cpp"; ($self->{top_filename} ||= $self->{pl_filename}) =~ s/\.pl$//; ($self->{golden_filename} ||= $self->{pl_filename}) =~ s/\.pl$/.out/; if (-e ($self->{top_filename}.".vhd")) { # If VHDL file exists $self->{vhdl} = 1; $self->{top_filename} .= ".vhd"; } else { $self->{top_filename} .= ".v"; } if (!$self->{make_top_shell}) { $self->{top_shell_filename} = $self->{top_filename}; } else { $self->{top_shell_filename} = "$self->{obj_dir}/$self->{VM_PREFIX}__top.v"; } $self->{pli_filename} ||= $self->{name}.".cpp"; return $self; } sub soprint { my $self = (ref $_[0] ? shift : $Self); my $str = "$self->{scenario}/$self->{name}: ".join('',@_); $str =~ s/\n\n+$/\n/s; return $str; } sub oprint { my $self = (ref $_[0] ? shift : $Self); print $self->soprint(@_); } sub error { my $self = (ref $_[0] ? shift : $Self); my $msg = join('',@_); # Called from tests as: error("Reason message"[, ...]); warn "%Warning: $self->{scenario}/$self->{name}: ".$msg."\n"; $self->{errors} ||= $msg; } sub skip { my $self = (ref $_[0] ? shift : $Self); my $msg = join('',@_); # Called from tests as: skip("Reason message"[, ...]); warn "-Skip: $self->{scenario}/$self->{name}: ".$msg."\n"; $self->{skips} ||= "Skip: ".$msg; } sub unsupported { my $self = (ref $_[0] ? shift : $Self); my $msg = join('',@_); # Called from tests as: unsupported("Reason message"[, ...]); warn "-Unsupported: $self->{scenario}/$self->{name}: ".$msg."\n"; if (!$::Opt_Unsupported) { $self->{unsupporteds} ||= "Unsupported: ".$msg; } } sub scenarios { my $self = (ref $_[0] ? shift : $Self); my %params = (@_); # Called from tests as: scenarios(...); # to specify which scenarios this test runs under. # Where ... is one cases listed in All_Scenarios if ((scalar keys %params) < 1) { $params{simulators} = 1; } my %enabled_scenarios; foreach my $scenario (keys %params) { my $value = $params{$scenario}; my $hit = 0; foreach my $allsc (keys %All_Scenarios) { foreach my $allscarg (@{$All_Scenarios{$allsc}}) { if ($scenario eq $allscarg) { $hit = 1; $enabled_scenarios{$allsc} = 1; } } } if (!$hit) { $self->error("scenarios('$scenario' => ...) has unknown scenario '$scenario',"); } } if (!$enabled_scenarios{$self->{scenario}}) { $self->skip("scenario '$self->{scenario}' not enabled for test"); $self->{scenario_off} ||= 1; $self->_exit(); } } sub _prep { my $self = shift; mkdir $self->{obj_dir}; # Ok if already exists } sub _read { my $self = shift; # Read the control file (-r $self->{pl_filename}) or return $self->error("Can't open $self->{pl_filename}\n"); $Self = $self; delete $INC{$self->{pl_filename}}; require $self->{pl_filename}; } sub _exit { my $self = shift; if ($self->ok) { $self->oprint("Self PASSED\n"); } elsif ($self->skips && !$self->errors) { $self->oprint("%Skip: $self->{skips}\n"); } elsif ($self->unsupporteds && !$self->errors) { $self->oprint("%Unsupported: $self->{unsupporteds}\n"); } else { $self->error("Missing ok\n") if !$self->errors; $self->oprint("%Error: $self->{errors}\n"); } $self->_write_status; exit(0); } sub _write_status { my $self = shift; my $filename = $self->{status_filename}; my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,"; $Data::Dumper::Indent = 1; $Data::Dumper::Sortkeys = 1; print $fh Dumper($self); print $fh "1;"; $fh->close(); } sub _read_status { my $self = shift; my $filename = $self->{status_filename}; use vars qw($VAR1); local $VAR1; if (!-r $filename) { $self->error("driver.pl _read_status file missing: $filename"); return; } { local %INC = (); require $filename or die "%Error: $! $filename,"; } if ($VAR1) { %{$self} = %{$VAR1}; } else { $self->error("driver.pl _read_status file empty: $filename"); return; } } #---------------------------------------------------------------------- # Methods invoked by tests sub clean { my $self = (ref $_[0] ? shift : $Self); # Called on a rerun to cleanup files if ($self->{clean_command}) { system($self->{clean_command}); } if (1) { # Prevents false-failures when switching compilers # Remove old results to force hard rebuild system("rm", "-rf", "$self->{obj_dir}__fail1"); system("mv", "$self->{obj_dir}", "$self->{obj_dir}__fail1"); } } sub clean_objs { my $self = (ref $_[0] ? shift : $Self); system("rm", "-rf", glob("$self->{obj_dir}/*")); } sub compile_vlt_cmd { my $self = (ref $_[0]? shift : $Self); my %param = (%{$self}, @_); # Default arguments are from $self return 1 if $self->errors || $self->skips || $self->unsupporteds; my @vlt_cmd = ( "perl", "$ENV{VERILATOR_ROOT}/bin/verilator", $self->compile_vlt_flags(%param), $param{top_filename}, @{$param{v_other_filenames}}, $param{stdout_filename}?"> ".$param{stdout_filename}:"" ); return @vlt_cmd; } sub compile_vlt_flags { my $self = (ref $_[0]? shift : $Self); my %param = (%{$self}, @_); # Default arguments are from $self return 1 if $self->errors || $self->skips || $self->unsupporteds; my $checkflags = join(' ',@{$param{v_flags}}, @{$param{v_flags2}}, @{$param{verilator_flags}}, @{$param{verilator_flags2}}, @{$param{verilator_flags3}}); $self->{sc} = 1 if ($checkflags =~ /-sc\b/); $self->{trace} = ($opt_trace || $checkflags =~ /-trace\b/ || $checkflags =~ /-trace-fst\b/); $self->{trace_format} = (($checkflags =~ /-trace-fst/ && 'fst-c') || ($self->{sc} && 'vcd-sc') || (!$self->{sc} && 'vcd-c')); $self->{savable} = 1 if ($checkflags =~ /-savable\b/); $self->{coverage} = 1 if ($checkflags =~ /-coverage\b/); my @verilator_flags = @{$param{verilator_flags}}; unshift @verilator_flags, "--gdb" if $opt_gdb; unshift @verilator_flags, "--gdbbt" if $opt_gdbbt; unshift @verilator_flags, "--rr" if $opt_rr; unshift @verilator_flags, "--x-assign unique"; # More likely to be buggy unshift @verilator_flags, "--trace" if $opt_trace; my $threads = ::calc_threads($Vltmt_threads); unshift @verilator_flags, "--threads $threads" if $param{vltmt} && $checkflags !~ /-threads /; unshift @verilator_flags, "--trace-threads 1" if $param{vltmt} && $checkflags =~ /-trace /; unshift @verilator_flags, "--trace-threads 2" if $param{vltmt} && $checkflags =~ /-trace-fst /; unshift @verilator_flags, "--debug-partition" if $param{vltmt}; unshift @verilator_flags, "--make gmake" if $param{verilator_make_gmake}; unshift @verilator_flags, "--make cmake" if $param{verilator_make_cmake}; unshift @verilator_flags, "--exe" if $param{make_main} && $param{verilator_make_gmake}; unshift @verilator_flags, "../".$self->{main_filename} if $param{make_main} && $param{verilator_make_gmake}; if (defined $opt_optimize) { my $letters = ""; if ($opt_optimize =~ /[a-zA-Z]/) { $letters = $opt_optimize; } else { # Randomly turn on/off different optimizations foreach my $l ('a'..'z') { $letters .= ((rand() > 0.5) ? $l : uc $l); } unshift @verilator_flags, "--trace" if rand() > 0.5; unshift @verilator_flags, "--coverage" if rand() > 0.5; } unshift @verilator_flags, "--O".$letters; } my @cmdargs = ( "--prefix ".$param{VM_PREFIX}, @verilator_flags, @{$param{verilator_flags2}}, @{$param{verilator_flags3}}, @{$param{v_flags}}, @{$param{v_flags2}}, # Flags from driver cmdline override default flags and # flags from the test itself driver_verilator_flags(), ); return @cmdargs; } sub driver_verilator_flags { #my $self = (ref $_[0] ? shift : $Self); return @Opt_Driver_Verilator_Flags } sub lint { my $self = (ref $_[0] ? shift : $Self); my %param = (# %{$self}, # Default arguments are from $self # Lint specific default overrides make_main => 0, make_top_shell => 0, verilator_flags2 => ["--lint-only"], verilator_make_gmake => 0, @_); $self->compile(%param); } sub compile { my $self = (ref $_[0]? shift : $Self); my %param = (tee => 1, %{$self}, @_); # Default arguments are from $self return 1 if $self->errors || $self->skips || $self->unsupporteds; $self->oprint("Compile\n") if $self->{verbose}; compile_vlt_cmd(%param); if (!$self->{make_top_shell}) { $param{top_shell_filename} = $self->{top_shell_filename} = $self->{top_filename}; } else { $param{top_shell_filename} = $self->{top_shell_filename} = "$self->{obj_dir}/$self->{VM_PREFIX}__top.".$self->v_suffix; } if ($param{atsim}) { $self->_make_top(); $self->_run(logfile=>"$self->{obj_dir}/atsim_compile.log", fails=>$param{fails}, cmd=>[($ENV{VERILATOR_ATSIM}||"atsim"), @{$param{atsim_flags}}, @{$param{atsim_flags2}}, @{$param{v_flags}}, @{$param{v_flags2}}, $param{top_filename}, $param{top_shell_filename}, @{$param{v_other_filenames}}, ]); } elsif ($param{ghdl}) { mkdir $self->{ghdl_work_dir}; $self->_make_top(); $self->_run(logfile=>"$self->{obj_dir}/ghdl_compile.log", fails=>$param{fails}, cmd=>[($ENV{VERILATOR_GHDL}||"ghdl"), # Add -c here, as having -c twice freaks it out ((($ENV{VERILATOR_GHDL}||' ') =~ / -c\b/) ? "" : "-c"), @{$param{ghdl_flags}}, @{$param{ghdl_flags2}}, #@{$param{v_flags}}, # Not supported #@{$param{v_flags2}}, # Not supported $param{top_filename}, $param{top_shell_filename}, @{$param{v_other_filenames}}, "-e t", ]); } elsif ($param{vcs}) { $self->_make_top(); $self->_run(logfile=>"$self->{obj_dir}/vcs_compile.log", fails=>$param{fails}, cmd=>[($ENV{VERILATOR_VCS}||"vcs"), @{$param{vcs_flags}}, @{$param{vcs_flags2}}, @{$param{v_flags}}, @{$param{v_flags2}}, $param{top_filename}, $param{top_shell_filename}, @{$param{v_other_filenames}}, ]); } elsif ($param{nc}) { $self->_make_top(); my @more_args; if ($self->vhdl) { ((my $ts = $param{top_shell_filename}) =~ s!\.v!!); $ts =~ s!.*/!!;; push @more_args, "-vhdltop", $ts; } $self->_run(logfile=>"$self->{obj_dir}/nc_compile.log", fails=>$param{fails}, cmd=>[($ENV{VERILATOR_NCVERILOG}||"ncverilog"), @{$param{nc_flags}}, @{$param{nc_flags2}}, @{$param{v_flags}}, @{$param{v_flags2}}, $param{top_filename}, $param{top_shell_filename}, @{$param{v_other_filenames}}, @more_args ]); } elsif ($param{ms}) { $self->_make_top(); $self->_run(logfile=>"$self->{obj_dir}/ms_compile.log", fails=>$param{fails}, cmd=>[("vlib $self->{obj_dir}/work && "), ($ENV{VERILATOR_MODELSIM}||"vlog"), @{$param{ms_flags}}, @{$param{ms_flags2}}, @{$param{v_flags}}, @{$param{v_flags2}}, $param{top_filename}, $param{top_shell_filename}, @{$param{v_other_filenames}} ]); } elsif ($param{iv}) { $self->_make_top(); my @cmd = (($ENV{VERILATOR_IVERILOG}||"iverilog"), @{$param{iv_flags}}, @{$param{iv_flags2}}, @{$param{v_flags}}, @{$param{v_flags2}}, $param{top_filename}, $param{top_shell_filename}, @{$param{v_other_filenames}}); @cmd = grep { s/\+define\+/-D /g; $_; } @cmd; $self->_run(logfile=>"$self->{obj_dir}/iv_compile.log", fails=>$param{fails}, cmd=>\@cmd); } elsif ($param{xsim}) { $self->_make_top(); $self->_run(logfile=>"$self->{obj_dir}/xsim_compile.log", fails=>$param{fails}, cmd=>[($ENV{VERILATOR_XVLOG}||"xvlog"), @{$param{xsim_flags}}, @{$param{xsim_flags2}}, @{$param{v_flags}}, @{$param{v_flags2}}, $param{top_filename}, $param{top_shell_filename}, @{$param{v_other_filenames}} ]); } elsif ($param{vlt_all}) { if ($self->sc && !$self->have_sc) { $self->skip("Test requires SystemC; ignore error since not installed\n"); return 1; } if ($self->{vltmt} && !$self->cfg_with_threaded) { $self->skip("Test requires Verilator configured with threads\n"); return 1; } if ($param{verilator_make_cmake} && !$self->have_cmake) { $self->skip("Test requires CMake; ignore error since not available or version too old\n"); return 1; } if (!$param{fails} && $param{make_main}) { $self->_make_main(); } if ($param{verilator_make_gmake} || (!$param{verilator_make_gmake} && !$param{verilator_make_cmake})) { my @vlt_cmd = $self->compile_vlt_cmd(%param); $self->oprint("Running Verilator (gmake)\n") if $self->{verbose}; $self->_run(logfile => "$self->{obj_dir}/vlt_compile.log", fails => $param{fails}, tee => $param{tee}, expect => $param{expect}, expect_filename => $param{expect_filename}, verilator_run => 1, cmd => \@vlt_cmd) if $::Opt_Verilation; return 1 if $self->errors || $self->skips || $self->unsupporteds; } if ($param{verilator_make_cmake}) { my @vlt_args = $self->compile_vlt_flags(%param); $self->oprint("Running cmake\n") if $self->{verbose}; mkdir $self->{obj_dir}; my @csources = (); unshift @csources, $self->{main_filename} if $param{make_main}; $self->_run(logfile => "$self->{obj_dir}/vlt_cmake.log", fails => $param{fails}, tee => $param{tee}, expect => $param{expect}, expect_filename => $param{expect_filename}, verilator_run => 1, cmd => ["cd \"".$self->{obj_dir}."\" && cmake", "\"".$self->{t_dir}."/..\"", "-DTEST_VERILATOR_ROOT=$ENV{VERILATOR_ROOT}", "-DTEST_NAME=$self->{name}", "-DTEST_CSOURCES=\"@csources\"", "-DTEST_VERILATOR_ARGS=\"@vlt_args\"", "-DTEST_VERILATOR_SOURCES=\"$param{top_filename} @{$param{v_other_filenames}}\"", "-DTEST_VERBOSE=\"".($self->{verbose} ? 1 : 0)."\"", "-DTEST_SYSTEMC=\"" .($self->sc ? 1 : 0). "\"", "-DCMAKE_PREFIX_PATH=\"".(($ENV{SYSTEMC_INCLUDE}||$ENV{SYSTEMC}||'')."/..\""), "-DTEST_OPT_FAST=\"" . ($param{benchmark} ? "-Os" : "-O0") . "\"", "-DTEST_OPT_GLOBAL=\"" . ($param{benchmark} ? "-Os" : "-O0") . "\"", "-DTEST_VERILATION=\"" . $::Opt_Verilation . "\"", ]); return 1 if $self->errors || $self->skips || $self->unsupporteds; } if (!$param{fails} && $param{verilator_make_gmake}) { $self->oprint("Running make (gmake)\n") if $self->{verbose}; $self->_run(logfile => "$self->{obj_dir}/vlt_gcc.log", entering => "$self->{obj_dir}", cmd => [$ENV{MAKE}, "-C ".$self->{obj_dir}, "-f ".$::RealBin."/Makefile_obj", ($self->{verbose} ? "" : "--no-print-directory"), "VM_PREFIX=$self->{VM_PREFIX}", "TEST_OBJ_DIR=$self->{obj_dir}", "CPPFLAGS_DRIVER=-D".uc($self->{name}), ($self->{verbose} ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1":""), ($param{benchmark} ? "" : "OPT_FAST=-O0"), ($param{benchmark} ? "" : "OPT_GLOBAL=-O0"), "$self->{VM_PREFIX}", # bypass default rule, as we don't need archive ($param{make_flags}||""), ]); } if (!$param{fails} && $param{verilator_make_cmake}) { $self->oprint("Running cmake --build\n") if $self->{verbose}; $self->_run(logfile => "$self->{obj_dir}/vlt_cmake_build.log", cmd => ["cmake", "--build", $self->{obj_dir}, ($self->{verbose}?"--verbose":""), ]); } } else { $self->error("No compile step defined for '$self->{scenario}' scenario"); } if ($param{make_pli}) { $self->oprint("Compile vpi\n") if $self->{verbose}; my @cmd = ($ENV{CXX}, @{$param{pli_flags}}, "-DIS_VPI", "$self->{t_dir}/$self->{pli_filename}"); $self->_run(logfile=>"$self->{obj_dir}/pli_compile.log", fails=>$param{fails}, cmd=>\@cmd); } return 1; } sub execute { my $self = (ref $_[0]? shift : $Self); return 1 if $self->errors || $self->skips || $self->unsupporteds; my %param = (%{$self}, @_); # Default arguments are from $self # params may be expect or {tool}_expect $self->oprint("Run\n") if $self->{verbose}; delete $ENV{SYSTEMC_DISABLE_COPYRIGHT_MESSAGE}; $ENV{SYSTEMC_DISABLE_COPYRIGHT_MESSAGE} = "DISABLE" if !$self->{verbose}; my $run_env = $param{run_env}; $run_env .= ' ' if $run_env; if ($param{atsim}) { $self->_run(logfile=>"$self->{obj_dir}/atsim_sim.log", fails=>$param{fails}, cmd=>["echo q | ".$run_env."$self->{obj_dir}/athdl_sv", @{$param{atsim_run_flags}}, @{$param{all_run_flags}}, ], %param, expect=>$param{atsim_run_expect}, # non-verilator expect isn't the same expect_filename=>$param{atsim_run_expect_filename}, ); } elsif ($param{ghdl}) { $self->_run(logfile=>"$self->{obj_dir}/ghdl_sim.log", fails=>$param{fails}, cmd=>[$run_env."$self->{obj_dir}/simghdl", @{$param{ghdl_run_flags}}, @{$param{all_run_flags}}, ], %param, expect=>$param{ghdl_run_expect}, # non-verilator expect isn't the same expect_filename=>$param{ghdl_run_expect_filename}, ); } elsif ($param{iv}) { my @cmd = ($run_env."$self->{obj_dir}/simiv", @{$param{iv_run_flags}}, @{$param{all_run_flags}}, ); if ($param{iv_pli}) { # don't enter command line on $stop, include vpi unshift @cmd, "vvp -n -m $self->{obj_dir}/libvpi.so"; } $self->_run(logfile=>"$self->{obj_dir}/iv_sim.log", fails=>$param{fails}, cmd=> \@cmd, %param, expect=>$param{iv_run_expect}, # non-verilator expect isn't the same expect_filename=>$param{iv_run_expect_filename}, ); } elsif ($param{ms}) { my @pli_opt=(); if ($param{ms_pli}) { unshift @pli_opt, "-pli $self->{obj_dir}/libvpi.so"; } $self->_run(logfile=>"$self->{obj_dir}/ms_sim.log", fails=>$param{fails}, cmd=>["echo q | ".$run_env.($ENV{VERILATOR_MODELSIM}||"vsim"), @{$param{ms_run_flags}}, @{$param{all_run_flags}}, @{pli_opt}, (" top") ], %param, expect=>$param{ms_run_expect}, # non-verilator expect isn't the same expect_filename=>$param{ms_expect_filename}, ); } elsif ($param{nc}) { $self->_run(logfile=>"$self->{obj_dir}/nc_sim.log", fails=>$param{fails}, cmd=>["echo q | ".$run_env.($ENV{VERILATOR_NCVERILOG}||"ncverilog"), @{$param{nc_run_flags}}, @{$param{all_run_flags}}, ], %param, expect=>$param{nc_run_expect}, # non-verilator expect isn't the same expect_filename=>$param{nc_run_expect_filename}, ); } elsif ($param{vcs}) { #my $fh = IO::File->new(">simv.key") or die "%Error: $! simv.key,"; #$fh->print("quit\n"); $fh->close; $self->_run(logfile=>"$self->{obj_dir}/vcs_sim.log", cmd=>["echo q | ".$run_env."./simv", @{$param{vcs_run_flags}}, @{$param{all_run_flags}}, ], %param, expect=>$param{vcs_run_expect}, # non-verilator expect isn't the same expect_filename=>$param{vcs_run_expect_filename}, ); } elsif ($param{xsim}) { $self->_run(logfile=>"$self->{obj_dir}/xsim_sim.log", fails=>$param{fails}, cmd=>[$run_env.($ENV{VERILATOR_XELAB}||"xelab"), @{$param{xsim_run_flags}}, @{$param{xsim_run_flags2}}, @{$param{all_run_flags}}, (" $self->{name}.top") ], %param, expect=>$param{xsim_run_expect}, # non-verilator expect isn't the same expect_filename=>$param{xsim_expect_filename}, ); } elsif ($param{vlt_all} #&& (!$param{needs_v4} || -r "$ENV{VERILATOR_ROOT}/src/V3Gate.cpp") ) { $param{executable} ||= "$self->{obj_dir}/$param{VM_PREFIX}"; my $debugger = ""; if ($opt_gdbsim) { $debugger = ($ENV{VERILATOR_GDB}||"gdb")." "; } elsif ($opt_rrsim) { $debugger = "rr record "; } $self->_run(logfile=>"$self->{obj_dir}/vlt_sim.log", cmd=>[($run_env .$debugger .$param{executable} .($opt_gdbsim ? " -ex 'run " : "")), @{$param{all_run_flags}}, ($opt_gdbsim ? "'" : ""), ], %param, expect=>$param{expect}, # backward compatible name expect_filename=>$param{expect_filename}, # backward compatible name ); } else { $self->error("No execute step for this simulator"); } } sub setenv { my $self = (ref $_[0]? shift : $Self); my $var = shift; my $val = shift; print "\texport $var='$val'\n"; $ENV{$var} = $val; } sub inline_checks { my $self = (ref $_[0]? shift : $Self); return 1 if $self->errors || $self->skips || $self->unsupporteds; return 1 if !$self->{vlt_all}; my %param = (%{$self}, @_); # Default arguments are from $self my $covfn = $Self->{coverage_filename}; my $contents = $self->file_contents($covfn); $self->oprint("Extract checks\n") if $self->{verbose}; my $fh = IO::File->new("<$self->{top_filename}"); while (defined(my $line = $fh->getline)) { if ($line =~ /CHECK/) { if ($line =~ /CHECK_COVER *\( *([---0-9]+) *, *"([^"]+)" *, *("([^"]+)" *,|) *(\d+) *\)/) { my $lineno = ($. + $1); my $hier=$2; my $comment=$4; my $count=$5; my $regexp = "\001l\002".$lineno; $regexp .= ".*\001o\002".quotemeta($comment) if $comment; $regexp .= ".*\001h\002".quotemeta($hier) if $hier; $regexp .= ".*' ".$count; if ($contents !~ /$regexp/) { $self->error("CHECK_COVER: $covfn: Regexp not found: $regexp\n". "From $self->{top_filename}:$.: $line"); } } elsif ($line =~ /CHECK_COVER_MISSING *\( *([---0-9]+) *\)/) { my $lineno = ($. + $1); my $regexp = "\001l\002".$lineno; if ($contents =~ /$regexp/) { $self->error("CHECK_COVER_MISSING: $covfn: Regexp found: $regexp\n". "From $self->{top_filename}:$.: $line"); } } else { $self->error("$self->{top_filename}:$.: Unknown CHECK request: $line"); } } } $fh->close; } #---------------------------------------------------------------------- # Accessors sub ok { my $self = (ref $_[0]? shift : $Self); $self->{ok} = $_[0] if defined $_[0]; $self->{ok} = 0 if $self->{errors} || $self->{skips} || $self->unsupporteds; return $self->{ok}; } sub continuing { my $self = (ref $_[0]? shift : $Self); return !($self->errors || $self->skips || $self->unsupporteds); } sub errors { my $self = (ref $_[0]? shift : $Self); return $self->{errors}; } sub scenario_off { my $self = (ref $_[0]? shift : $Self); return $self->{scenario_off}; } sub skips { my $self = (ref $_[0]? shift : $Self); return $self->{skips}; } sub unsupporteds { my $self = (ref $_[0]? shift : $Self); return $self->{unsupporteds}; } sub top_filename { my $self = (ref $_[0]? shift : $Self); $self->{top_filename} = shift if defined $_[0]; return $self->{top_filename}; } sub vhdl { my $self = (ref $_[0]? shift : $Self); $self->{vhdl} = shift if defined $_[0]; if ($self->{vhdl}) { $self->{top_filename} =~ s/\.v$/\.vhdl/; } return $self->{vhdl}; } sub v_suffix { my $self = (ref $_[0]? shift : $Self); # Suffix for file type, e.g. .vhdl or .v return $self->{vhdl} ? "vhdl" : "v"; } sub sc { my $self = (ref $_[0]? shift : $Self); return $self->{sc}; } sub have_sc { my $self = (ref $_[0]? shift : $Self); return 1 if (defined $ENV{SYSTEMC} || defined $ENV{SYSTEMC_INCLUDE} || $ENV{CFG_HAVE_SYSTEMC}); return 1 if $self->verilator_version =~ /systemc found *= *1/i; return 0; } sub make_version { my $ver = `$ENV{MAKE} --version`; if ($ver =~ /make ([0-9]+\.[0-9]+)/i) { return $1; } else { return -1; } } sub have_cmake { return cmake_version() >= version->declare("3.8"); } sub cmake_version { chomp(my $cmake_bin = `which cmake`); if (!$cmake_bin) { return undef; } my $cmake_version = `cmake --version`; if ($cmake_version !~ /cmake version (\d+)\.(\d+)/) { return undef; } $cmake_version = "$1.$2"; return version->declare($cmake_version); } sub trace_filename { my $self = shift; return "$self->{obj_dir}/simx.fst" if $self->{trace_format} =~ /^fst/; return "$self->{obj_dir}/simx.vcd"; } sub obj_dir { my $self = shift; return $self->{obj_dir}; } sub get_default_vltmt_threads { return $Vltmt_threads; } sub pli_filename { my $self = (ref $_[0]? shift : $Self); $self->{pli_filename} = shift if defined $_[0]; return $self->{pli_filename}; } sub too_few_cores { my $threads = ::calc_threads($Vltmt_threads); return $threads < $Vltmt_threads; } sub skip_if_too_few_cores { my $self = (ref $_[0]? shift : $Self); if (too_few_cores()) { $self->skip("Skipping due to too few cores\n"); } } sub wno_unopthreads_for_few_cores { if (too_few_cores()) { warn "Too few cores, using -Wno-UNOPTTHREADS\n"; return "-Wno-UNOPTTHREADS"; } return ""; } sub VM_PREFIX { my $self = (ref $_[0]? shift : $Self); $self->{VM_PREFIX} = shift if defined $_[0]; return $self->{VM_PREFIX}; } #---------------------------------------------------------------------- sub run { my $self = (ref $_[0]? shift : $Self); $self->_run(@_); } sub _run { my $self = (ref $_[0]? shift : $Self); my %param = (tee => 1, #entering => # Print entering directory information #verilator_run => # Move gcov data to parallel area @_); my $command = join(' ',@{$param{cmd}}); $command = "time $command" if $opt_benchmark && $command !~ /^cd /; print "\t$command"; print " > $param{logfile}" if $param{logfile}; print "\n"; if ($param{verilator_run}) { # Gcov fails when parallel jobs write same data file, # so we make sure output dir is unique across all running jobs. # We can't just put each one in obj_dir as it uses too much disk. $ENV{GCOV_PREFIX_STRIP} = 99; $ENV{GCOV_PREFIX} = "$self->{t_dir}/obj_dist/gcov_$self->{running_id}"; } else { delete $ENV{GCOV_PREFIX_STRIP}; delete $ENV{GCOV_PREFIX}; } # Execute command redirecting output, keeping order between stderr and stdout. # Must do low-level IO so GCC interaction works (can't be line-based) my $status; { pipe(PARENTRD, CHILDWR) or die "%Error: Can't Pipe, stopped"; autoflush PARENTRD 1; autoflush CHILDWR 1; my $logfh; if ($param{logfile}) { $logfh = IO::File->new(">$param{logfile}") or die "%Error: Can't open $param{logfile}"; } my $pid=fork(); if ($pid) { # Parent close CHILDWR; print "driver: Entering directory '", File::Spec->rel2abs($param{entering}), "'\n" if $param{entering}; while (1) { my $buf = ''; my $got = sysread PARENTRD,$buf,10000; last if defined $got && $got==0; print $buf if $param{tee}; print $logfh $buf if $logfh; } close PARENTRD; close $logfh if $logfh; print "driver: Leaving directory '", File::Spec->rel2abs($param{entering}), "'\n" if $param{entering}; } else { # Child close PARENTRD; close $logfh if $logfh; # Reset signals $SIG{ALRM} = 'DEFAULT'; $SIG{CHLD} = 'DEFAULT'; # Logging open(STDOUT, ">&CHILDWR") or croak "%Error: Can't redirect stdout, stopped"; open(STDERR, ">&STDOUT") or croak "%Error: Can't dup stdout, stopped"; autoflush STDOUT 1; autoflush STDERR 1; system "$command"; my $status = $?; if (($status & 127) == 4 # SIGILL || ($status & 127) == 8 # SIGFPA || ($status & 127) == 11) { # SIGSEGV $Self->error("Exec failed with core dump"); } exit($? ? 10 : 0); # $?>>8 misses coredumps } waitpid($pid,0); $status = $? || 0; } flush STDOUT; flush STDERR; if (!$param{fails} && $status) { my $firstline = ""; if (my $fh = IO::File->new("<$param{logfile}")) { $firstline = $fh->getline || ''; chomp $firstline; } $self->error("Exec of $param{cmd}[0] failed: $firstline\n"); } if ($param{fails} && $status) { print "(Exec expected to fail, and did.)\n"; } if ($param{fails} && !$status) { $self->error("Exec of $param{cmd}[0] ok, but expected to fail\n"); } return if $self->errors || $self->skips || $self->unsupporteds; # Read the log file a couple of times to allow for NFS delays if ($param{check_finished} || $param{expect}) { for (my $try = $self->tries - 1; $try >= 0; $try--) { sleep 1 if ($try != $self->tries - 1); my $moretry = $try != 0; my $fh = IO::File->new("<$param{logfile}"); next if !$fh && $moretry; local $/; undef $/; my $wholefile = <$fh>; $fh->close(); # Finished? if ($param{check_finished} && $wholefile !~ /\*\-\* All Finished \*\-\*/) { next if $moretry; $self->error("Missing All Finished\n"); } if ($param{expect}) { # Strip debugging comments # See also files_identical $wholefile =~ s/^- [^\n]+\n//mig; $wholefile =~ s/^- [a-z.0-9]+:\d+:[^\n]+\n//mig; $wholefile =~ s/^dot [^\n]+\n//mig; # Compare my $quoted = quotemeta($param{expect}); my $ok = ($wholefile eq $param{expect} || _try_regex($wholefile, $param{expect}) == 1 || $wholefile =~ /$quoted/ms); if (!$ok) { #print "**BAD $self->{name} $param{logfile} MT $moretry $try\n"; next if $moretry; $self->error("Mismatch in output from $param{cmd}[0]\n"); $self->error("Might be error in regexp format\n") if $ok<1; print "GOT:\n"; print $wholefile; print "ENDGOT\n"; print "EXPECT:\n"; print $param{expect}; print "ENDEXPECT\n"; } } last; } } if ($param{expect_filename}) { files_identical($param{logfile}, $param{expect_filename}, 'logfile'); } } ####################################################################### # Little utilities sub _try_regex { # Try to eval a regexp # Returns: # 1 if $text ~= /$regex/ms # 0 if no match # -1 if $regex is invalid, doesn't compile my ($text, $regex) = @_; my $result; { local $@; eval { $result = ($text =~ /$regex/ms); }; $result = -1 if $@; } return $result; } sub _make_main { my $self = shift; if ($self->vhdl) { $self->_read_inputs_vhdl(); } else { $self->_read_inputs_v(); } my $filename = $self->{main_filename}; my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,"; print $fh "// Test defines\n"; print $fh "#define MAIN_TIME_MULTIPLIER ".($self->{main_time_multiplier} || 1)."\n"; print $fh "// OS header\n"; print $fh "#include \"verilatedos.h\"\n"; print $fh "// Generated header\n"; my $VM_PREFIX = $self->{VM_PREFIX}; print $fh "#include \"$VM_PREFIX.h\"\n"; print $fh "// General headers\n"; print $fh "#include \"verilated.h\"\n"; print $fh "#include \"systemc.h\"\n" if $self->sc; print $fh "#include \"verilated_fst_c.h\"\n" if $self->{trace} && $self->{trace_format} eq 'fst-c'; print $fh "#include \"verilated_vcd_c.h\"\n" if $self->{trace} && $self->{trace_format} eq 'vcd-c'; print $fh "#include \"verilated_vcd_sc.h\"\n" if $self->{trace} && $self->{trace_format} eq 'vcd-sc'; print $fh "#include \"verilated_save.h\"\n" if $self->{savable}; print $fh "$VM_PREFIX* topp;\n"; if (!$self->sc) { if ($self->{vl_time_stamp64}) { print $fh "vluint64_t main_time = 0;\n"; print $fh "vluint64_t vl_time_stamp() { return main_time; }\n"; } else { print $fh "double main_time = 0;\n"; print $fh "double sc_time_stamp() { return main_time; }\n"; } } if ($self->{savable}) { $fh->print("\n"); $fh->print("void save_model(const char* filenamep) {\n"); $fh->print(" VL_PRINTF(\"Saving model to '%s'\\n\", filenamep);\n"); $fh->print(" VerilatedSave os;\n"); $fh->print(" os.open(filenamep);\n"); $fh->print(" os << main_time;\n"); $fh->print(" os << *topp;\n"); $fh->print(" os.close();\n"); $fh->print("}\n"); $fh->print("\n"); $fh->print("void restore_model(const char* filenamep) {\n"); $fh->print(" VL_PRINTF(\"Restoring model from '%s'\\n\", filenamep);\n"); $fh->print(" VerilatedRestore os;\n"); $fh->print(" os.open(filenamep);\n"); $fh->print(" os >> main_time;\n"); $fh->print(" os >> *topp;\n"); $fh->print(" os.close();\n"); $fh->print("}\n"); } #### Main if ($self->sc) { print $fh "extern int sc_main(int argc, char** argv);\n"; print $fh "int sc_main(int argc, char** argv) {\n"; print $fh " sc_signal fastclk;\n" if $self->{inputs}{fastclk}; print $fh " sc_signal clk;\n" if $self->{inputs}{clk}; print $fh " sc_set_time_resolution(1, $Self->{sc_time_resolution});\n"; print $fh " sc_time sim_time($self->{sim_time}, $Self->{sc_time_resolution});\n"; } else { print $fh "int main(int argc, char** argv, char** env) {\n"; print $fh " double sim_time = $self->{sim_time};\n"; } print $fh " Verilated::commandArgs(argc, argv);\n"; print $fh " Verilated::debug(".($self->{verilated_debug}?1:0).");\n"; print $fh " srand48(5);\n"; # Ensure determinism print $fh " Verilated::randReset(".$self->{verilated_randReset}.");\n" if defined $self->{verilated_randReset}; print $fh " topp = new $VM_PREFIX(\"top\");\n"; print $fh " Verilated::internalsDump()\n;" if $self->{verilated_debug}; my $set; if ($self->sc) { print $fh " topp->fastclk(fastclk);\n" if $self->{inputs}{fastclk}; print $fh " topp->clk(clk);\n" if $self->{inputs}{clk}; $set = ""; } else { print $fh " topp->eval();\n"; $set = "topp->"; } if ($self->{trace}) { $fh->print("\n"); $fh->print("#if VM_TRACE\n"); $fh->print(" Verilated::traceEverOn(true);\n"); $fh->print(" VerilatedFstC* tfp = new VerilatedFstC;\n") if $self->{trace_format} eq 'fst-c'; $fh->print(" VerilatedVcdC* tfp = new VerilatedVcdC;\n") if $self->{trace_format} eq 'vcd-c'; $fh->print(" VerilatedVcdSc* tfp = new VerilatedVcdSc;\n") if $self->{trace_format} eq 'vcd-sc'; $fh->print(" topp->trace(tfp, 99);\n"); $fh->print(" tfp->open(\"".$self->trace_filename."\");\n"); if ($self->{trace} && !$self->sc) { $fh->print(" if (tfp) tfp->dump(main_time);\n"); } $fh->print("#endif\n"); } if ($self->{savable}) { $fh->print(" const char* save_time_strp = Verilated::commandArgsPlusMatch(\"save_time=\");\n"); $fh->print(" unsigned int save_time = !save_time_strp[0] ? 0 : atoi(save_time_strp+strlen(\"+save_time=\"));\n"); $fh->print(" const char* save_restore_strp = Verilated::commandArgsPlusMatch(\"save_restore=\");\n"); $fh->print(" unsigned int save_restore = !save_restore_strp[0] ? 0 : 1;\n"); } if ($self->{savable}) { $fh->print(" if (save_restore) {\n"); $fh->print(" restore_model(\"$self->{obj_dir}/saved.vltsv\");\n"); $fh->print(" } else {\n"); } else { $fh->print(" {\n"); } print $fh " ${set}fastclk = false;\n" if $self->{inputs}{fastclk}; print $fh " ${set}clk = false;\n" if $self->{inputs}{clk}; _print_advance_time($self, $fh, 10); print $fh " }\n"; print $fh " while ((sc_time_stamp() < sim_time * MAIN_TIME_MULTIPLIER)\n"; print $fh " && !Verilated::gotFinish()) {\n"; for (my $i=0; $i<5; $i++) { my $action = 0; if ($self->{inputs}{fastclk}) { print $fh " ${set}fastclk = !${set}fastclk;\n"; $action = 1; } if ($i==0 && $self->{inputs}{clk}) { print $fh " ${set}clk = !${set}clk;\n"; $action = 1; } if ($self->{savable}) { $fh->print(" if (sc_time_stamp() == save_time && save_time) {\n"); $fh->print(" save_model(\"$self->{obj_dir}/saved.vltsv\");\n"); $fh->print(" printf(\"Exiting after save_model\\n\");\n"); $fh->print(" exit(0);\n"); $fh->print(" }\n"); } _print_advance_time($self, $fh, 1, $action); } print $fh " }\n"; print $fh " if (!Verilated::gotFinish()) {\n"; print $fh ' vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");',"\n"; print $fh " }\n"; print $fh " topp->final();\n"; if ($self->{coverage}) { $fh->print("#if VM_COVERAGE\n"); $fh->print(" VerilatedCov::write(\"",$self->{coverage_filename},"\");\n"); $fh->print("#endif // VM_COVERAGE\n"); } if ($self->{trace}) { $fh->print("#if VM_TRACE\n"); $fh->print(" if (tfp) tfp->close();\n"); $fh->print("#endif // VM_TRACE\n"); } $fh->print("\n"); print $fh " VL_DO_DANGLING(delete topp, topp);\n"; print $fh " exit(0L);\n"; print $fh "}\n"; $fh->close(); } sub _print_advance_time { my $self = shift; my $fh = shift; my $time = shift; my $action = shift; my $set; if ($self->sc) { $set = ""; } else { $set = "topp->"; } if ($self->sc) { print $fh "#if (SYSTEMC_VERSION>=20070314)\n"; print $fh " sc_start(${time}, $Self->{sc_time_resolution});\n"; print $fh "#else\n"; print $fh " sc_start(${time});\n"; print $fh "#endif\n"; } else { if ($action) { print $fh " ${set}eval();\n"; if ($self->{trace} && !$self->sc) { $fh->print("#if VM_TRACE\n"); $fh->print(" if (tfp) tfp->dump(main_time);\n"); $fh->print("#endif // VM_TRACE\n"); } } print $fh " main_time += ${time} * MAIN_TIME_MULTIPLIER;\n"; } } ####################################################################### sub _make_top { my $self = shift; if ($self->vhdl) { $self->_make_top_vhdl; } else { $self->_make_top_v; } } sub _make_top_v { my $self = shift; $self->_read_inputs_v(); my $fh = IO::File->new(">$self->{top_shell_filename}") or die "%Error: $! $self->{top_shell_filename},"; print $fh "module top;\n"; foreach my $inp (sort (keys %{$self->{inputs}})) { print $fh " reg ${inp};\n"; } # Inst print $fh " t t (\n"; my $comma=""; foreach my $inp (sort (keys %{$self->{inputs}})) { print $fh " ${comma}.${inp} (${inp})\n"; $comma=","; } print $fh " );\n"; # Waves print $fh "\n"; print $fh "`ifdef WAVES\n"; print $fh " initial begin\n"; print $fh " \$display(\"-Tracing Waves to Dumpfile: ".$self->trace_filename."\");\n"; print $fh " \$dumpfile(\"".$self->trace_filename."\");\n"; print $fh " \$dumpvars(0, top);\n"; print $fh " end\n"; print $fh "`endif\n"; # Test print $fh "\n"; print $fh " initial begin\n"; print $fh " fastclk = 0;\n" if $self->{inputs}{fastclk}; print $fh " clk = 0;\n" if $self->{inputs}{clk}; print $fh " #10;\n"; print $fh " fastclk = 1;\n" if $self->{inputs}{fastclk}; print $fh " clk = 1;\n" if $self->{inputs}{clk}; print $fh " while (\$time < $self->{sim_time}) begin\n"; for (my $i=0; $i<5; $i++) { print $fh " #1;\n"; print $fh " fastclk = !fastclk;\n" if $self->{inputs}{fastclk}; print $fh " clk = !clk;\n" if $i==4 && $self->{inputs}{clk}; } print $fh " end\n"; print $fh " end\n"; print $fh "endmodule\n"; $fh->close(); } sub _make_top_vhdl { my $self = shift; $self->_read_inputs_vhdl(); my $fh = IO::File->new(">$self->{top_shell_filename}") or die "%Error: $! $self->{top_shell_filename},"; print $fh "library ieee;\n"; my @ports = sort (keys %{$self->{inputs}}); print $fh "entity t_ent is\n"; if ($#ports >= 0) { print $fh " port(\n"; my $semi = ""; foreach my $inp (@ports) { print $fh " ${semi}${inp} : in std_logic\n"; $semi=";"; } print $fh " );\n"; } print $fh "end;\n"; print $fh "entity top is\n"; print $fh "end;\n"; # Inst print $fh "architecture t_beh of t_ent is\n"; if ($#ports >= 0) { foreach my $inp (@ports) { print $fh " signal ${inp} : std_logic := '0';\n"; } } print $fh " begin\n"; print $fh " t : t_ent\n"; if ($#ports >= 0) { print $fh " port map(\n"; my $comma=""; foreach my $inp (@ports) { print $fh "\t${comma}${inp} => ${inp}\n"; $comma=","; } print $fh " )\n"; } print $fh " ;\n"; print $fh " end;\n"; # Waves TBD # Test TBD print $fh "end;\n"; $fh->close(); } ####################################################################### sub _read_inputs_v { my $self = shift; my $filename = $self->top_filename; $filename = "$self->{t_dir}/$filename" if !-r $filename; my $fh = IO::File->new("<$filename") or die "%Error: $! $filename,"; my $get_sigs=1; my %inputs; while (defined(my $line = $fh->getline)) { if ($get_sigs) { if ($line =~ /^\s*input\s*(\S+)\s*(\/[^\/]+\/|)\s*;/) { $inputs{$1} = $1; } if ($line =~ /^\s*(function|task|endmodule)/) { $get_sigs = 0; } } if ($line =~ /^\s*module\s+t\b/) { # Ignore any earlier inputs; Module 't' has precedence %inputs = (); $get_sigs = 1; } } $self->{inputs}{$_} = $inputs{$_} foreach keys %inputs; $fh->close(); } ####################################################################### sub _read_inputs_vhdl { my $self = shift; my $filename = $self->top_filename; $filename = "$self->{t_dir}/$filename" if !-r $filename; my $fh = IO::File->new("<$filename") or die "%Error: $! $filename,"; while (defined(my $line = $fh->getline)) { # Only supports this form right now: # signal: in ... # signal: out ... if ($line =~ /^\s*(\S+)\s*:\s*(in)\b\s*/) { $self->{inputs}{$1} = $1; } if ($line =~ /^\s*(architecture)/) { last; } } $fh->close(); } ####################################################################### # Verilator utilities our $_Verilator_Version; sub verilator_version { # Returns verbose version, line 1 contains actual version if (!defined $_Verilator_Version) { my @args = ("perl", "$ENV{VERILATOR_ROOT}/bin/verilator", "-V"); my $args = join(' ',@args); $_Verilator_Version = `$args`; $_Verilator_Version or die "can't fork: $! ".join(' ',@args); chomp $_Verilator_Version; } return $_Verilator_Version if defined $_Verilator_Version; } ####################################################################### # File utilities sub files_identical { my $self = (ref $_[0]? shift : $Self); my $fn1 = shift; my $fn2 = shift; my $fn1_is_logfile = shift; return 1 if $self->errors || $self->skips || $self->unsupporteds; try: for (my $try = $self->tries - 1; $try >= 0; $try--) { sleep 1 if ($try != $self->tries - 1); my $moretry = $try != 0; my $f1 = IO::File->new("<$fn1"); my $f2 = IO::File->new("<$fn2"); if (!$f1) { next try if $moretry; $self->error("Files_identical file does not exist $fn1\n"); return 0; } if (!$f2 && !$ENV{HARNESS_UPDATE_GOLDEN}) { next try if $moretry; $self->error("Files_identical file does not exist $fn2\n"); return 0; } my @l1 = $f1 && $f1->getlines(); my @l2 = $f2 && $f2->getlines(); if ($fn1_is_logfile) { @l1 = grep { !/^- [^\n]+\n/ && !/^- [a-z.0-9]+:\d+:[^\n]+\n/ && !/^-node:/ && !/^dot [^\n]+\n/ && !/^In file: .*\/sc_.*:\d+/ } @l1; @l1 = map { s/(Internal Error: [^\n]+\.cpp):[0-9]+:/$1:#:/; s/^-V\{t[0-9]+,[0-9]+\}/-V{t#,#}/; # --vlt vs --vltmt run differences $_; } @l1; for (my $l=0; $l<=$#l1; ++$l) { # Don't put control chars into our source repository $l1[$l] =~ s/\r/<#013>/mig; $l1[$l] =~ s/Command Failed[^\n]+/Command Failed/mig; $l1[$l] =~ s/Version: Verilator[^\n]+/Version: Verilator ###/mig; $l1[$l] =~ s/CPU Time: +[0-9.]+ seconds[^\n]+/CPU Time: ###/mig; if ($l1[$l] =~ s/Exiting due to.*/Exiting due to/mig) { splice @l1, $l+1; # Trunc rest last; } } } my $nl = $#l1; $nl = $#l2 if ($#l2 > $nl); for (my $l=0; $l<=$nl; ++$l) { if (($l1[$l]||"") ne ($l2[$l]||"")) { next try if $moretry; $self->error("Line ".($l+1)." mismatches; $fn1 != $fn2"); warn("F1: ".($l1[$l]||"*EOF*\n") ."F2: ".($l2[$l]||"*EOF*\n")); if ($ENV{HARNESS_UPDATE_GOLDEN}) { # Update golden files with current warn "%Warning: HARNESS_UPDATE_GOLDEN set: cp $fn1 $fn2\n"; my $fhw = IO::File->new(">$fn2") or $self->error("Files_identical $! $fn2\n"); $fhw->print(join('',@l1)); } else { warn "To update reference: HARNESS_UPDATE_GOLDEN=1 {command} or --golden\n"; } return 0; } } return 1; } } sub files_identical_sorted { my $self = (ref $_[0]? shift : $Self); my $fn1 = shift; my $fn2 = shift; my $fn1_is_logfile = shift; return 1 if $self->errors || $self->skips || $self->unsupporteds; # Set LC_ALL as suggested in the sort manpage to avoid sort order # changes from the locale. setenv('LC_ALL', "C"); my $fn1sort = "$fn1.sort"; run(cmd => ["sort", "$fn1", "> $fn1sort"]); return $self->files_identical($fn1sort, $fn2, $fn1_is_logfile); } sub copy_if_golden { my $self = (ref $_[0]? shift : $Self); my $fn1 = shift; my $fn2 = shift; if ($ENV{HARNESS_UPDATE_GOLDEN}) { # Update golden files with current warn "%Warning: HARNESS_UPDATE_GOLDEN set: cp $fn1 $fn2\n"; eval "use File::Copy;"; File::Copy::copy($fn1, $fn2); } } sub vcd_identical { my $self = (ref $_[0]? shift : $Self); my $fn1 = shift; my $fn2 = shift; return 0 if $self->errors || $self->skips || $self->unsupporteds; if (!-r $fn1) { $self->error("Vcd_identical file does not exist $fn1\n"); return 0; } if (!-r $fn2) { $self->error("Vcd_identical file does not exist $fn2\n"); return 0; } { # vcddiff to check transitions, if installed my $cmd = qq{vcddiff --help}; print "\t$cmd\n" if $::Debug; my $out = `$cmd`; if (!$out || $out !~ /Usage:/) { $self->skip("No vcddiff installed\n"); return 1; } $cmd = qq{vcddiff "$fn1" "$fn2"}; print "\t$cmd\n" if $::Debug; $out = `$cmd`; if ($out ne '') { print $out; $self->error("VCD miscompare $fn1 $fn2\n"); $self->copy_if_golden($fn1, $fn2); return 0; } } { # vcddiff doesn't check module and variable scope, so check that # Also provides backup if vcddiff not installed my $h1 = $self->_vcd_read($fn1); my $h2 = $self->_vcd_read($fn2); $Data::Dumper::Sortkeys = 1; my $a = Dumper($h1); my $b = Dumper($h2); if ($a ne $b) { print "$a\n$b\n" if $::Debug; $self->error("VCD hier mismatch $fn1 $fn2\n"); $self->copy_if_golden($fn1, $fn2); return 0; } } return 1; } sub fst2vcd { my $self = (ref $_[0]? shift : $Self); my $fn1 = shift; my $fn2 = shift; if (!-r $fn1) { $self->error("File does not exist $fn1\n"); return 0; } my $cmd = qq{fst2vcd -h}; print "\t$cmd\n" if $::Debug; my $out = `$cmd`; if (!$out || $out !~ /Usage:/) { $self->skip("No fst2vcd installed\n"); return 1; } $cmd = qq{fst2vcd -e -f "$fn1" -o "$fn2"}; print "\t$cmd\n"; # Always print to help debug race cases $out = `$cmd`; return 1; } sub fst_identical { my $self = (ref $_[0]? shift : $Self); my $fn1 = shift; my $fn2 = shift; return 0 if $self->errors || $self->skips || $self->unsupporteds; my $tmp = $fn1.".vcd"; fst2vcd($fn1, $tmp); return vcd_identical($tmp, $fn2); } sub _vcd_read { my $self = (ref $_[0]? shift : $Self); my $filename = shift; my $data = {}; my $fh = IO::File->new("<$filename"); if (!$fh) { warn "%Error: $! $filename\n"; return $data; } my @hier = ($data); my $lasthier; while (defined(my $line = $fh->getline)) { if ($line =~ /\$scope module\s+(\S+)/) { $hier[$#hier]->{$1} ||= {}; push @hier, $hier[$#hier]->{$1}; $lasthier = $hier[$#hier]; } elsif ($line =~ /(\$var \S+\s+\d+\s+)\S+\s+(\S+)/) { $hier[$#hier]->{$1.$2} ||= {}; $lasthier = $hier[$#hier]; } elsif ($line =~ /(\$attrbegin .* \$end)/) { if ($lasthier) { $lasthier->{$1} ||= 1; } } elsif ($line =~ /\$enddefinitions/) { last; } while ($line =~ s/\$upscope//) { pop @hier; $lasthier = undef; } } return $data; } our $_Cxx_Version; sub cxx_version { $_Cxx_Version ||= `$ENV{MAKE} -C $ENV{VERILATOR_ROOT}/test_regress -f Makefile print-cxx-version`; return $_Cxx_Version; } our $_Cfg_With_Threaded; sub cfg_with_threaded { $_Cfg_With_Threaded ||= `$ENV{MAKE} -C $ENV{VERILATOR_ROOT} -f Makefile print-cfg-with-threaded`; return ($_Cfg_With_Threaded =~ /yes/i) ? 1:0; } sub tries { # Number of retries when reading logfiles, generally only need many # retries when system is busy running a lot of tests return 2 if !$::Fork->running; return 7 if (scalar($::Fork->running)) > 1; return 2; } sub file_grep_not { my $self = (ref $_[0]? shift : $Self); my $filename = shift; my $regexp = shift; my $expvalue = shift; return if $self->errors || $self->skips || $self->unsupporteds; !defined $expvalue or $self->error("file_grep_not: Unexpected 3rd argument: $expvalue"); my $contents = $self->file_contents($filename); return if ($contents eq "_Already_Errored_"); if ($contents =~ /$regexp/) { $self->error("File_grep_not: $filename: Regexp found: $regexp\n"); } } sub file_grep { my $self = (ref $_[0]? shift : $Self); my $filename = shift; my $regexp = shift; my $expvalue = shift; return if $self->errors || $self->skips || $self->unsupporteds; my $contents = $self->file_contents($filename); return if ($contents eq "_Already_Errored_"); if ($contents !~ /$regexp/) { $self->error("File_grep: $filename: Regexp not found: $regexp\n"); } elsif ($expvalue && $expvalue ne $1) { $self->error("File_grep: $filename: Got='$1' Expected='$expvalue' in regexp: $regexp\n"); } } my %_File_Contents_Cache; sub file_contents { my $self = (ref $_[0]? shift : $Self); my $filename = shift; if (!$_File_Contents_Cache{$filename}) { my $fh = IO::File->new("<$filename"); if (!$fh) { $_File_Contents_Cache{$filename} = "_Already_Errored_"; $self->error("File_grep file not found: ".$filename."\n"); return $_File_Contents_Cache{$filename}; } local $/; undef $/; my $wholefile = <$fh>; $fh->close(); $_File_Contents_Cache{$filename} = $wholefile; } return $_File_Contents_Cache{$filename}; } sub write_wholefile { my $self = (ref $_[0]? shift : $Self); my $filename = shift; my $contents = shift; my $fh = IO::File->new(">$filename") or die "%Error: $! writing $filename,"; print $fh $contents; $fh->close; } ####################################################################### ####################################################################### ####################################################################### ####################################################################### # Forker class package Forker; use strict; # This is a shell that matches Parallel::Forker. # If that package is not installed, this runs the tests in *series* sub new { my $class = shift; my $self = {@_}; bless $self, $class; return $self; } sub schedule { my $self = shift; my %params = (@_); $params{run_pre_start}->($self); if (my $pid = fork()) { # Parent waitpid($pid, 0); } else { # Child $params{run_on_start}->($self); exit(0); # Don't close anything } $params{run_on_finish}->($self); return $self; } sub max_proc {} sub sig_child {} sub kill_tree_all {} sub wait_all {} sub ready {} sub running {} sub is_any_left { return 0; } ####################################################################### 1; package main; __END__ =pod =head1 NAME driver.pl - Run regression tests =head1 SYNOPSIS driver.pl =head1 DESCRIPTION driver.pl invokes Verilator or another simulator on each test file. The driver reports the number of tests which pass, fail, skipped (some resource required by the test is not available, such as SystemC), or are unsupported (buggy or require a feature change before will pass.) There are hundreds of tests, and for faster completion you may want to run the regression tests with OBJCACHE enabled and in parallel on a machine with many cores. See the -j option and OBJCACHE environment variable. =head1 TEST CONFIGURATION The Perl script (e.g. C) controls how the test will run by driver.pl. In general it includes a call to the C subroutine to compile the test with Verilator (or an alternative simulator), followed by a call to the C subroutine to run the test. Compile-only tests omit the call to C. If those complete, the script calls C to increment the count of successful tests and then returns 1 as its result. Both C and C take an optional argument hash table to control their behavior. For example: compile( verilator_flags2 => ["--lint-only"], fails => 1, ); indicates that when compiling this test, the C<--lint-only> flag should be passed and that the test is expected to fail. The full list of arguments can be found by looking at the C source code. Some commonly used arguments are: =over 4 =item all_run_flags A list of flags to be passed when running the simulator (Verilated model or one of the other simulators). =item check_finished Set to 1 to indicate successful completion of the test is indicated by the string C<*-* All Finished *-*> being printed on standard output. This is the normal way for successful tests to finish. =item expect A quoted list of strings or regular expression to be matched in the output. See for more detail on how this argument should be used. =item fails Set to 1 to indicate this step (C or C or C) is expected to fail. Tests that are expected to fail generally have _bad in their filename. =item make_main Set to 0 to disable the automatic creation of a C++ test wrapper (for example when a hand-written test wrapper is provided using C<--exe>). =item make_top_shell Set to 0 to disable the automatic creation of a top level shell to run the executable (for example when a hand-written test wrapper is provided using C<--exe>). =item ms_flags =item ms_flags2 =item ms_run_flags The equivalent of C, C and C, but only for use with the ModelSim simulator. =item nc_flags =item nc_flags2 =item nc_run_flags The equivalent of C, C and C, but only for use with the Cadence NC simulator. =item iv_flags =item iv_flags2 =item iv_run_flags The equivalent of C, C and C, but only for use with the Icarus Verilog simulator. =item v_flags A list of standard Verilog simulator flags to be passed to the simulator compiler (Verilator or one of the other simulators). This list is create by the driver and rarely changed, use v_flags2 instead. =item v_flags2 A list of standard Verilog simulator flags to be passed to the simulator compiler (Verilator or one of the other simulators). Unlike v_flags, these options may be overridden in some simulation files. Similar sets of flags exist for atsim, GHDL, Cadence NC, Modelsim and Synopsys VCS. =item vcs_flags =item vcs_flags2 =item vcs_run_flags The equivalent of C, C and C, but only for use with the Synopsys VCS simulator. =item verilator_flags =item verilator_flags2 The equivalent of C and C, but only for use with Verilator. If a flag is a standard flag (+incdir for example) v_flags2 should be used instead. =item xsim_flags =item xsim_flags2 =item xsim_run_flags The equivalent of C, C and C, but only for use with the Xilinx XSim simulator. =back =head2 HINTS ON WRITING TESTS There is generally no need for the test to create its own main program or top level shell as the driver creates one automatically, however some tests require their own C++ or SystemC test harness. This is commonly given the same name as the test, but with .cpp as suffix (C). This can be specified as follows: compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); Tests should be self-checking, rather than producing lots of output. If a test succeeds it should print C<*-* All Finished *-*> to standard output and terminate (in Verilog C<$finish>), if not it should just stop (in Verilog C<$stop>) as that signals an error. If termination should be triggered from the C++ wrapper, the following code can be used: vl_fatal(__FILE__, __LINE__, "dut", ""); exit(1); This can be particularly useful if checking that the Verilator model has not unexpectedly terminated. if (Verilated::gotFinish()) { vl_fatal(__FILE__, __LINE__, "dut", ""); exit(1); } Where it might be useful for a test to produce output, it should qualify this with C. For example in Verilog: `ifdef TEST_VERBOSE $write("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif Or in a hand-written C++ wrapper: #ifdef TEST_VERBOSE cout << "Read a = " << a << endl; #endif The C specifies a filename that should be used to check the output results. This should not generally be used to decide if a test has succeeded. However, in the case of tests that are designed to fail at compile time, it is the only option. For example: compile( fails => 1, expect_filename => $Self->{golden_filename}, ); Note expect_filename strips some debugging information from the logfile when comparing. The C argument specifies a regular expression which must match the output. =head1 DRIVER ARGUMENTS =over 4 =item --benchmark [] Show execution times of each step. If an optional number is given, specifies the number of simulation cycles (for tests that support it). =item --debug Same as C: Use the debug version of Verilator which enables additional assertions, debugging messages, and structure dump files. =item --debugi(-) Same as C: Set Verilator internal debugging level globally to the specified debug level (1-10) or set the specified source file to the specified level. Higher levels produce more detailed messages (plain C<--debug> is equivalent to C<--debugi 4>). =item --dump-tree Same as C: Enable Verilator writing .tree debug files with dumping level 3, which dumps the standard critical stages. For details on the format see the Verilator Internals manual. =item --gdb Same as C: Run Verilator under the debugger. =item --gdbbt Same as C: Run Verilator under the debugger, only to print backtrace information. Requires --debug. =item --gdbsim Run Verilator generated executable under the debugger. =item --golden Update golden files, equivalent to setting HARNESS_UPDATE_GOLDEN=1. =item --hashset I/I Split tests based on a hash of the test names into I and run only tests in set number I (0..I-1). =item --help Displays this message and program version and exits. =item --j # Run number of parallel tests, or 0 to determine the count based on the number of cores installed. Requires Perl's Parallel::Forker package. =item --optimize Randomly turn on/off different optimizations. With specific flags, use those optimization settings =item --quiet Suppress all output except for failures and progress messages every 15 seconds. Intended for use only in automated regressions. See also C<--rerun>, and C<--verbose> which is not the opposite of C<--quiet>. =item --rerun Rerun all tests that failed in this run. Reruns force the flags C<--no-quiet --j 1>. =item --rr Same as C: Run Verilator and record with rr. =item --rrsim Run Verilator generated executable and record with rr. =item --site Run site specific tests also. =item --stop Stop on the first error. =item --trace Set the simulator specific flags to request waveform tracing. =item --unsupported Run tests even if marked as unsupported. =item --verbose Compile and run the test in verbose mode. This means C will be defined for the test (Verilog and any C++/SystemC wrapper). =back =head1 SCENARIO ARGUMENTS The following options control which simulator is used, and which tests are run. Multiple flags may be used to run multiple simulators/scenarios simultaneously. =over 4 =item --atsim Run ATSIM simulator tests. =item --dist Run simulator-agnostic distribution tests. =item --ghdl Run GHDL simulator tests. =item --iverilog Run Icarus Verilog simulator tests. =item --ms Run ModelSim simulator tests. =item --nc Run Cadence NC-Verilog simulator tests. =item --vcs Run Synopsys VCS simulator tests. =item --vlt Run Verilator tests in single-threaded mode. Default unless another scenario flag is provided. =item --vltmt Run Verilator tests in multithreaded mode. =item --xsim Run Xilinx XSim simulator tests. =back =head1 ENVIRONMENT =over 4 =item SYSTEMC Root directory name of SystemC kit. Only used if SYSTEMC_INCLUDE not set. =item SYSTEMC_INCLUDE Directory name with systemc.h in it. =item VERILATOR_GHDL Command to use to invoke GHDL. =item VERILATOR_IVERILOG Command to use to invoke Icarus Verilog. =item VERILATOR_MAKE Command to use to rebuild Verilator and run single test. Defaults to "make &&". =item VERILATOR_MODELSIM Command to use to invoke ModelSim. =item VERILATOR_NCVERILOG Command to use to invoke ncverilog. =item VERILATOR_TESTS_SITE Used with --site, a colon-separated list of directories with tests to be added to testlist. =item VERILATOR_VCS Command to use to invoke VCS. =item VERILATOR_XELAB Command to use to invoke XSim xelab =item VERILATOR_XVLOG Command to use to invoke XSim xvlog =back =head1 DISTRIBUTION The latest version is available from L. Copyright 2003-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS Wilson Snyder =head1 SEE ALSO L =cut ###################################################################### verilator-4.038/test_regress/vgen.pl0000775000177100017500000012201613702133370017525 0ustar wsnyderwsnyder#!/usr/bin/env perl # See copyright, etc in below POD section. ###################################################################### require 5.006_001; use warnings; use Getopt::Long; use IO::File; use Pod::Usage; use Data::Dumper; $Data::Dumper::Indent = 1; use Bit::Vector; use strict; use vars qw($Debug); our @Orig_ARGV = @ARGV; our $Rerun_Args = $0." ".join(' ',@Orig_ARGV); $Rerun_Args =~ s/\s+$//; use vars qw(@Blocks %Vars %VarAttrs %VarsBlock %Tree @Commit $Depth %IdWidth %Ops); #====================================================================== # width=> Number of bits the output size is, 0=you tell me. # func=> What to put in output file # signed=> 0=unsigned output, 1=signed output, '%1'=signed if op1 signed # lsb=> LSB for variable declarations # em=> How to calculate emulated return value # %w Width of this output op ($treeref->{width}) # %v Output value ($treeref->{val}) # %1r First operand ($treeref->{op1}) # %1v First operand value ($treeref->{op1}{val}) # %1w First operand width ($treeref->{op1}{width}) our $Raise_Weight_Max = 50; %Ops = ( 'VCONST'=> {weight=>1&&20, width=>0, sc=>1, terminal=>1, v=>'%v', }, 'VIDNEW'=> {weight=>1&&10, width=>0, sc=>1, terminal=>0, v=>'%i', }, 'VIDOLD'=> {weight=>1&&20, width=>0, sc=>1, terminal=>0, v=>'%i', }, 'VIDSAME'=> {weight=>1&&20, width=>0, sc=>1, terminal=>0, v=>'%i', }, 'VRANGE'=> {weight=>1&&30, width=>0, signed=>0,sc=>0, terminal=>0, v=>'%i[%2:%3]', }, 'VBITSEL'=> {weight=>1&&10, width=>1, signed=>0,sc=>0, terminal=>0, v=>'%i[%2]', }, 'VBITSELP'=> {weight=>1&&10, width=>0, signed=>0,sc=>0, terminal=>0, v=>'%i[%2+:%3]', }, 'VBITSELM'=> {weight=>1&&10, width=>0, signed=>0,sc=>0, terminal=>0, v=>'%i[%2-:%3]', }, # Unary 'VEXTEND'=> {weight=>1&&3, width=>-2, signed=>0,sc=>0, terminal=>0, v=>'{%xd\'h0,%1}', }, 'VLOGNOT'=> {weight=>1&&1, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(! %1)', }, 'VREDAND'=> {weight=>1&&1, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(& %1)', }, 'VREDOR'=> {weight=>1&&1, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(| %1)', }, 'VREDNAND'=> {weight=>1&&1, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(~& %1)', }, 'VREDNOR'=> {weight=>1&&1, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(~| %1)', }, 'VREDXNOR'=> {weight=>1&&1, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(^~ %1)', }, 'VREDXOR'=> {weight=>1&&1, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(^ %1)', }, 'VNOT'=> {weight=>1&&3, width=>0, sc=>1, terminal=>0, v=>'(~ %1)', }, 'VNEGATE'=> {weight=>1&&2, width=>0, sc=>1, terminal=>0, v=>'(- %1)', }, 'VCOUNTONES'=> {weight=>0&&2, width=>32, signed=>0, sc=>0, terminal=>0, v=>'\$countones(%1)', }, # No ncv support 'VONEHOT'=> {weight=>0&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'\$onehot(%1)', }, # No ncv support 'VONEHOT0'=> {weight=>0&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'\$onehot0(%1)', }, # No ncv support # Binary 'VAND'=> {weight=>1&&2, width=>0, sc=>1, terminal=>0, v=>'(%1 & %2)', }, 'VOR'=> {weight=>1&&2, width=>0, sc=>1, terminal=>0, v=>'(%1 | %2)', }, 'VNAND'=> {weight=>1&&0, width=>0, sc=>0, terminal=>0, v=>'(%1 ~& %2)', }, #FIX vcs bug! 'VNOR'=> {weight=>1&&0, width=>0, sc=>0, terminal=>0, v=>'(%1 ~| %2)', }, #FIX vcs bug! 'VXOR'=> {weight=>1&&2, width=>0, sc=>1, terminal=>0, v=>'(%1 ^ %2)', }, 'VXNOR'=> {weight=>1&&0, width=>0, sc=>0, terminal=>0, v=>'(%1 ^~ %2)', }, #FIX vcs bug! 'VEQ'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 == %2)', }, 'VNEQ'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 != %2)', }, 'VGT'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 > %2)', }, 'VGTE'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 >= %2)', }, 'VLT'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 < %2)', }, 'VLTE'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 <= %2)', }, 'VEQCASE'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 === %2)', }, # FIX just a = for now 'VNEQCASE'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 !== %2)', }, # FIX just a != for now 'VLOGOR'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 || %2)', }, 'VLOGAND'=> {weight=>1&&2, width=>1, signed=>0, sc=>0, terminal=>0, v=>'(%1 && %2)', }, 'VADD'=> {weight=>1&&10, width=>0, sc=>1, terminal=>0, v=>'(%1 + %2)', }, 'VSUB'=> {weight=>1&&10, width=>0, sc=>1, terminal=>0, v=>'(%1 - %2)', }, 'VMUL'=> {weight=>1&&15,width=>0, sc=>1, terminal=>0, v=>'(%1 * %2)', }, # High % as rarely applyable # Unspecified behavior with == (a-signed / b) -- see t_math_signed5.v test 'VDIV'=> {weight=>1&&8, width=>0, signed=>0, sc=>1, terminal=>0, v=>'((%2)==%xw\'h0 ? %xw\'%xsh0:(%1 / %2))', }, 'VMODDIV'=> {weight=>1&&8, width=>0, signed=>0, sc=>1, terminal=>0, v=>'((%2)==%xw\'h0 ? %xw\'%xsh0:(%1 %% %2))', }, #'VPOW'=> {weight=>2&&0,width=>-64, sc=>0, terminal=>0, v=>'(%1 ** %2)', }, 'VSHIFTL'=> {weight=>1&&8, width=>0, signed=>0, sc=>0, terminal=>0, v=>'(%1 << %2)', }, 'VSHIFTLS'=> {weight=>1&&8, width=>0, signed=>1, sc=>0, terminal=>0, v=>'(%1 <<< %2)', }, 'VSHIFTR'=> {weight=>1&&8, width=>0, signed=>0, sc=>0, terminal=>0, v=>'(%1 >> %2)', }, 'VSHIFTRS'=> {weight=>1&&15,width=>0, signed=>1, sc=>0, terminal=>0, v=>'(%1 >>> %2)', }, # ShiftR seems to sign extend differently for <=32 and >32 bits 'VCONCAT'=> {weight=>1&&4, width=>-2,signed=>0, sc=>0, terminal=>0, v=>'{%1,%2}', }, 'VREPLIC'=> {weight=>1&&2, width=>0, signed=>0, sc=>0, terminal=>0, v=>'{%1{%2}}', }, 'VREPLIC1W'=> {weight=>1&&2, width=>0, signed=>0, sc=>0, terminal=>0, v=>'{%1{%2}}', }, 'VSIGNED'=> {weight=>1&&2, width=>0, signed=>1, sc=>0, terminal=>0, v=>'\$signed(%1)', }, 'VUNSIGNED'=> {weight=>1&&2, width=>0, signed=>0, sc=>0, terminal=>0, v=>'\$unsigned(%1)', }, # Triops 'VCOND'=> {weight=>1&&4, width=>0, sc=>0, terminal=>0, v=>'(%1 ? %2 : %3)', }, # Control flow #VIF #VFOR #VCASE #VCASEX #VCASEZ ); my %ops2 = ( 'VCONST'=> {pl=>'', rnd=>'rnd_const(%tr);'}, 'VIDNEW'=> {pl=>'%tv=$Vars{%i}{val};', rnd=>'%i=next_id(%tw);' .' $Vars{%i}=gen_leaf(width=>%tw,trunc=>1,signed=>%tg);' .' $VarAttrs{%i}{lsb} = rnd_lsb();' .' id_commit(%tr,"%i");1;',}, 'VIDOLD'=> {pl=>'%tv=$Vars{%i}{val};', rnd=>'%i=id_old(%tr);', ok_id_width=>1,}, 'VIDSAME'=> {pl=>'%tv=$Vars{%i}{val};', rnd=>'%i=id_same(%tr);', ok_id_width=>1,}, # These create IDs they then extract from 'VRANGE'=> {pl=>'VRANGE(%tr,$Vars{%i}{val},%2v,%3v,$VarAttrs{%i}{lsb});', rnd=>'%i=next_id(%tw); $VarAttrs{%i}{lsb} = 0&&rnd_lsb();' .' my $lsb=rnd(128-%tw); my $msb=$lsb+%tw-1;' .' %2r=val_leaf($msb); %3r=val_leaf($lsb);' .' $Vars{%i}=gen_leaf(width=>($msb+1));'}, 'VBITSEL'=> {pl=>'VRANGE(%tr,$Vars{%i}{val},%2v,%2v,$VarAttrs{%i}{lsb});', rnd=>'%i=next_id(%tw); $VarAttrs{%i}{lsb} = 0&&rnd_lsb();' .' my $wid=min(128,rnd_width()|3);' .' %2r=gen_leaf(width=>(log2($wid)-1),signed=>0);' .' $Vars{%i}=gen_leaf(width=>$wid);'}, 'VBITSELP'=> {pl=>'VBITSELP(%tr,$Vars{%i}{val},%2v,%3v,$VarAttrs{%i}{lsb});', rnd=>'%i=next_id(%tw); $VarAttrs{%i}{lsb} = 0&&rnd_lsb();' .' my $wid=min(128,(%tw+rnd_width()|3)); %3r=val_leaf(%tw); my $maxval = $wid-%tw; %2r=(($maxval<4)?val_leaf($maxval):gen_leaf(width=>(log2($maxval)-1),signed=>0));' .' $Vars{%i}=gen_leaf(width=>$wid);'}, 'VBITSELM'=> {pl=>'VBITSELM(%tr,$Vars{%i}{val},%2v,%3v,$VarAttrs{%i}{lsb});', rnd=>'%i=next_id(%tw); $VarAttrs{%i}{lsb} = 0&&rnd_lsb();' .' my $wid=min(128,(%tw+rnd_width()|3)); %3r=val_leaf(%tw); my $maxval = $wid-1; my $minval=%tw-1; %2r=val_leaf(rnd($maxval-$minval)+$minval);' .' $Vars{%i}=gen_leaf(width=>$wid);'}, # No easy way to make expr with specified minimum # Unary 'VEXTEND'=> {pl=>'VRESIZE (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>rnd_width(%tw-1));'}, 'VLOGNOT'=> {pl=>'VLOGNOT (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, 'VREDAND'=> {pl=>'VREDAND (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, 'VREDOR'=> {pl=>'VREDOR (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, 'VREDNAND'=> {pl=>'VREDNAND (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, 'VREDNOR'=> {pl=>'VREDNOR (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, 'VREDXOR'=> {pl=>'VREDXOR (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, 'VREDXNOR'=> {pl=>'VREDXNOR (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, 'VNOT'=> {pl=>'VNOT (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg);'}, 'VNEGATE'=> {pl=>'VNEGATE (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg);'}, 'VCOUNTONES'=> {pl=>'VCOUNTONES(%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, 'VONEHOT'=> {pl=>'VONEHOT (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, 'VONEHOT0'=> {pl=>'VONEHOT0 (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'}, # Binary 'VAND'=> {pl=>'VAND (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'}, 'VOR'=> {pl=>'VOR (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'}, 'VNAND'=> {pl=>'VNAND (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'}, 'VNOR'=> {pl=>'VNOR (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'}, 'VXOR'=> {pl=>'VXOR (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'}, 'VXNOR'=> {pl=>'VXNOR (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'}, 'VEQ'=> {pl=>'VEQ (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'}, 'VNEQ'=> {pl=>'VNE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'}, 'VGT'=> {pl=>'VGT (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'}, 'VGTE'=> {pl=>'VGE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'}, 'VLT'=> {pl=>'VLT (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'}, 'VLTE'=> {pl=>'VLE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'}, 'VEQCASE'=> {pl=>'VEQ (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'}, 'VNEQCASE'=> {pl=>'VNE (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>%1w,signed=>%1g);'}, 'VLOGOR'=> {pl=>'VLOGOR (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>0);'}, 'VLOGAND'=> {pl=>'VLOGAND(%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>0); %2r=gen_leaf(width=>0);'}, 'VADD'=> {pl=>'VADD (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);', trunc=>1,}, 'VSUB'=> {pl=>'VSUB (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);', trunc=>1,}, 'VMUL'=> {pl=>'VMUL (%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);', trunc=>1,}, # Multiply generates larger width, so need truncate for safety 'VDIV'=> {pl=>'VDIV (%tr,%1r,%2r,0);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'}, 'VMODDIV'=> {pl=>'VDIV (%tr,%1r,%2r,1);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>%tw,signed=>%tg);'}, #'VPOW'=> {pl=>'VPOW (%tr,%1r,%2r);', rnd=>'%1r=gen_leaf(width=>min(%tw,6),signed=>%tg); %2r=gen_leaf(width=>min(%tw,8),signed=>%tg);', trunc=>1,}, # Generates larger width, so need truncate for safety 'VSHIFTL'=> {pl=>'VSHIFTL(%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>log2(%tw)+1,signed=>%tg);'}, 'VSHIFTLS'=> {pl=>'VSHIFTL(%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>log2(%tw)+1,signed=>%tg);'}, 'VSHIFTR'=> {pl=>'VSHIFTR(%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>log2(%tw)+1,signed=>%tg);'}, 'VSHIFTRS'=> {pl=>'VSHIFTRS(%tr,%1v,%2v);', rnd=>'%1r=gen_leaf(width=>%tw,signed=>%tg); %2r=gen_leaf(width=>log2(%tw)+1,signed=>%tg);'}, 'VCONCAT'=> {pl=>'VCONCAT(%tr,%1v,%2v);', rnd=>'my $d=(rnd(%tw-2)+1); %1r=gen_leaf(width=>$d,signed=>0); %2r=gen_leaf(width=>(%tw-$d),signed=>0);'}, 'VREPLIC'=> {pl=>'VREPLIC(%tr,%1v,%2v);', rnd=>'my $d=rnd_rep_width(%tw); %1r=val_leaf($d); %2r=gen_leaf(width=>(%tw/$d),signed=>0);'}, 'VREPLIC1W'=> {pl=>'VREPLIC(%tr,%1v,%2v);', rnd=>'%1r=val_leaf(%tw); %2r=gen_leaf(width=>1,signed=>0);'}, 'VSIGNED'=> {pl=>'VCLONE (%tr,%1v,0);', rnd=>'%1r=gen_leaf(width=>%tw);'}, 'VUNSIGNED'=> {pl=>'VCLONE (%tr,%1v,0);', rnd=>'%1r=gen_leaf(width=>%tw);'}, # Triops 'VCOND'=> {pl=>'VCOND(%tr,%1v,%2v,%3v);', rnd=>'%1r=gen_leaf(width=>1); %2r=gen_leaf(width=>%tw,signed=>%tg); %3r=gen_leaf(width=>%tw,signed=>%tg);'}, ); foreach my $op (keys %ops2) { while ((my $key,my $val) = each %{$ops2{$op}}) { $Ops{$op}{$key} = $val; } } #====================================================================== # main #Bit::Vector->Configuration("ops=arithmetic"); my $opt_seed=5; our $Opt_NumOps = 30; our $Opt_Depth = 4; our $Opt_Output; our $Opt_Signed = 1; our $Opt_Raise; our $Opt_BlockStmts = 2; our $Signed_Pct = 60; $Debug = 0; if (! GetOptions ( "help" => \&usage, "debug" => \&debug, "depth=i" => \$Opt_Depth, "blockstmts=i"=> \$Opt_BlockStmts, "numops=i" => \$Opt_NumOps, "o=s" => \$Opt_Output, "raise=i" => \$Opt_Raise, "seed=i" => \$opt_seed, "signed!" => \$Opt_Signed, "<>" => \¶meter, )) { usage(); } if ($opt_seed==0) { srand(); $opt_seed = rnd(1<<20)+1; $Rerun_Args =~ s/-seed[= ]+0/-seed=$opt_seed/; print " $Rerun_Args\n"; } srand($opt_seed); init(); selftest(); gentest(); $Opt_Output or die "%Error: Need -o option,"; write_output_v($Opt_Output); #---------------------------------------------------------------------- sub usage { pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT); exit(1); # Unreachable } sub debug { $Debug = 1; } sub parameter { my $param = shift; die "%Error: Unknown parameter: $param\n"; } ####################################################################### ####################################################################### ####################################################################### ####################################################################### # Global Functions sub init { for my $op (keys %Ops) { my $opref = $Ops{$op}; $opref->{name} = $op; gen_v($opref); gen_pl($opref); gen_rnd($opref); } raise(); } sub raise { for (my $i=0; $i<($Opt_Raise||0); $i++) { my @ops = (values %Ops); while (1) { my $rndop = $ops[rnd($#ops + 1)]; next if !$rndop->{weight}; # Don't turn on disabled ops $rndop->{weight} += rnd($Raise_Weight_Max); printf "\tWeight %-15s +%d\n",$rndop->{name},$rndop->{weight}; last; } } } sub gentest { for (my $opn=0; $opn<$Opt_NumOps/$Opt_BlockStmts; $opn++) { do_a_test(); } } ####################################################################### # Randomization sub _rnd_op_ok { my $opref = shift; my $paramref = shift; return (($opref->{width} == 0 || $opref->{width} == $paramref->{width} # Note -2 means >, while -32 means {width}==-31 && $paramref->{width}<=31) # -31... must be <31 bits || ($opref->{width}==-32 && $paramref->{width}<=32) # -32... must be <32 bits || ($opref->{width}==-63 && $paramref->{width}<=63) # -63... must be <63 bits || ($opref->{width}==-64 && $paramref->{width}<=64) # -64... must be <64 bits || ($opref->{width}==-2 && $paramref->{width}>=2) # -2... must be >2 bits ) && (!$opref->{ok_id_width} || $IdWidth{$paramref->{width}}{$paramref->{signed}||0}) && (!defined $opref->{signed} || ($opref->{signed} == ($paramref->{signed}||0))) && (!$opref->{trunc} || $paramref->{trunc}) && (!$opref->{opt_signed} || $Opt_Signed) && (($Depth < $Opt_Depth && !$paramref->{need_terminal}) || $opref->{terminal})); } sub rnd_op { my $paramref = shift; my $totweight = 0; foreach my $opref (values %Ops) { if (_rnd_op_ok($opref,$paramref)) { $totweight += $opref->{weight}; } } my $chooseweight = rnd($totweight); $totweight = 0; foreach my $opref (sort {$a->{name} cmp $b->{name}} values %Ops) { if (_rnd_op_ok($opref,$paramref)) { $totweight += $opref->{weight}; if ($chooseweight < $totweight) { return $opref; } } } die "%Error: No instructions match,"; } sub rnd_width { my $max = shift; my $v = rnd(100); my $n = (0 || (($v<20) && 1) || (($v<25) && 2) || (($v<30) && 31) || (($v<35) && 32) || (($v<40) && 63) || (($v<45) && 64) || (($v<50) && 95) || (($v<55) && 96) || (rnd(128)+1)); if ($max && $n>=$max) { $n = rnd($max-1)+1; } return $n; } sub rnd_rep_width { my $out = shift; return 1 if $out==1; # We'd like to pick any divisor that works. my @factors; for (my $div=1; $div<$out; $div++) { if (int($out/$div)==($out/$div)) { push @factors, $div; } } my $fac = $factors[rnd($#factors+1)]; #print "RND REP $out -> $fac (@factors)\n" if $Debug; return $fac; } sub rnd_const { my $treeref = shift; my $width = $treeref->{width} or die; my $v = rnd(100); my $val = Bit::Vector->new($width); if ($v<25) { # zero } elsif ($v<50) { # ones for (my $w=0; $w<$val->Word_Size; ++$w) { $val->Word_Store(0,~0); } } elsif ($v<60) { # one $val->Word_Store(0,1); } else { # random for (my $w=0; $w<$val->Word_Size; ++$w) { $val->Word_Store($w,rnd_int()); } } $treeref->{val} = $val; } sub rnd_int { my $v = rnd(100); return 0 if ($v<25); return ~0 if ($v<50); return 1 if ($v<60); return rnd32(); } sub rnd_lsb { return 0; #return rnd(8)-4; # Not working yet } sub rnd { return (int(rand($_[0]))) if ($_[0] < (1<<15)); return (rnd32() % $_[0]); } sub rnd32 { my $vp = int(rand(1<<16)); $vp ^= (int(rand(1<<8)))<<16; # Single 1<<16 doesn't work $vp ^= (int(rand(1<<8)))<<24; return ($vp); } ####################################################################### our $Next_Id = 0; sub next_id { # Note width hasn't been determined yet $Next_Id++; my $id = sprintf("W%04d",$Next_Id); return $id; } sub id_commit { my $treeref = shift; my $width = $treeref->{width}; my $signed = $treeref->{signed}; my $id = shift; push @Commit, sub { $IdWidth{$width}{$signed} = [] if !$IdWidth{$width}{$signed}; push @{$IdWidth{$width}{$signed}}, $id; $VarsBlock{$id}{set} = 1; 1; }; } sub id_old { my $treeref = shift; my $width = $treeref->{width}; my $signed = $treeref->{signed}; my $n = $#{$IdWidth{$width}{$signed}} + 1; my $idn = rnd($n); my $id = $IdWidth{$width}{$signed}[$idn]; $VarsBlock{$id}{used} = 1; return $id; } sub id_same { my $treeref = shift; my $width = $treeref->{width}; my $signed = $treeref->{signed}; my @possible; foreach my $id (keys %VarsBlock) { next if !$VarsBlock{$id}{used}; my $varref = $Vars{$id}; next if $varref->{signed} != $signed; next if $varref->{width} != $width; push @possible, $id; } my $n = $#possible + 1; if ($n<1) { # Nothing, grab another! return id_old($treeref,$width,$signed); } my $idn = rnd($n); my $id = $possible[$idn]; $VarsBlock{$id}{used} = 1; return $id; } sub write_output_v { my $filename = shift; my $fh = IO::File->new($filename, "w") or die("%Error: $! $filename,\n"); print $fh "// Created by: $Rerun_Args\n"; print $fh "module vgen (clk);\n"; print $fh " input clk;\n"; print $fh " reg check; initial check = '0;\n"; print $fh ' initial $write("\n*** Vgen.v starting, seed = ',$opt_seed,'\n");',"\n"; print $fh " // verilator lint_off UNSIGNED\n"; print $fh " // verilator lint_off CMPCONST\n"; print $fh " // verilator lint_off WIDTH\n"; print $fh "\n"; my $cycles = 2; foreach my $var (sort (keys %Vars)) { print $fh "",decl_text ($var),"\n"; } foreach my $block (@Blocks) { print $fh "\t//".('='x60)."\n"; my $style = rnd(100); if ($style < 15) { # This allows statements to get split up, and constants to propagate print $fh " always @(", join(" or ", ('check', @{$block->{inputs}})); print $fh ") begin : $block->{name}\n"; print $fh @{$block->{preass}}; print $fh " end\n"; print $fh " always @(posedge clk) begin : $block->{name}Check\n"; print $fh @{$block->{body}}; print $fh " end\n"; } elsif ($style < 40) { print $fh " always @(", join(" or ", ('check', @{$block->{inputs}})); print $fh ") begin : $block->{name}\n"; print $fh @{$block->{preass}}; print $fh @{$block->{body}}; print $fh " end\n"; } else { foreach my $stmt (@{$block->{preass}}) { $cycles++; print $fh " always @(posedge clk) begin\n"; $stmt =~ s/ = / <= /mg; print $fh $stmt; print $fh " end\n"; } print $fh " always @(posedge clk) begin\n"; print $fh @{$block->{body}}; print $fh " end\n"; } } print $fh "\n"; print $fh " parameter [31:0] CYCLES /*verilator public*/ = $cycles;\n"; print $fh "\n"; print $fh " integer cyc; initial cyc = 0;\n"; print $fh " always @(posedge clk) begin\n"; print $fh "`ifdef TEST_VERBOSE\n"; print $fh ' $write("[%0t] cyc=%0d check=%d\n", $time, cyc, check);',"\n"; print $fh "`endif\n"; print $fh " cyc <= cyc + 1;\n"; print $fh " if (cyc < CYCLES) begin\n"; print $fh " check <= 1'b0;\n"; print $fh " end\n"; print $fh " else if (cyc >= CYCLES) begin\n"; print $fh " check <= 1'b1;\n"; print $fh " if (cyc >= (CYCLES+10)) begin\n"; print $fh ' $write("*-* All Finished *-*\n");',"\n"; print $fh ' $finish;',"\n"; print $fh " end\n"; print $fh " end\n"; print $fh " end\n"; print $fh "endmodule\n"; $fh->close(); } ###################################################################### sub callers { for (my $i=0; ; $i++) { my @c = caller($i); last if !$c[0]; print "Caller $i: ",join(' ',@c[0..3]),"\n"; } } ####################################################################### ####################################################################### ####################################################################### ####################################################################### # Code generation/emitting Functions sub do_a_test { local $Depth = 0; @Commit = (); %VarsBlock = (); my $block = { name=>"Block".($#Blocks+2), body=>[], preass=>[], inputs=>[], outputs=>[], }; for (my $i=0; $i<$Opt_BlockStmts; $i++) { my $treeref = gen_leaf(width=>0); push @{$block->{body}}, "\tif ($treeref->{text} != ".$treeref->val_to_text().") if (check) ".stop_text().";\n"; } foreach my $var (keys %VarsBlock) { push @{$block->{inputs}}, $var if $VarsBlock{$var}{used} && !$VarsBlock{$var}{set}; } foreach my $var (reverse (sort (keys %Vars))) { my $varref = $Vars{$var}; next if $varref->{printedit}; $varref->{printedit} = 1; push @{$block->{outputs}}, $var; push @{$block->{preass}}, sprintf ("\t$var = %s;\n" ,$varref->{text}); } foreach my $com (@Commit) { &{$com} or die "%Error: Can't eval:\n$com\n $@ "; } push @Blocks, $block; } sub gen_leaf { my $inforef = {width=>0, # Anything need_terminal=>0, #trunc=>undef, # Allow multiply op @_}; $inforef->{width} ||= rnd_width(); $inforef->{signed} = ($Opt_Signed && $inforef->{width}>1 && (rnd(100)<$Signed_Pct))?1:0 if !defined $inforef->{signed}; print +((" "x$Depth)."Leaf of width $inforef->{width}\n") if $Debug; my $op = rnd_op($inforef); my $treeref = new Vg::Base; while ((my $key,my $val) = each %{$op}) { $treeref->{$key} = $val; } while ((my $key,my $val) = each %{$inforef}) { $treeref->{$key} = $val; } local $Depth = $Depth+1; print "RndSub $treeref->{rnd_sub_text}\n" if $Debug; $treeref->{rnd_sub}($treeref); $treeref->tree_dump() if $Debug; print "RndPl\n" if $Debug; $treeref->{pl_sub}($treeref); print "RndV\n" if $Debug; $treeref->{text} = $treeref->{v_sub}($treeref); print "Done\n" if $Debug; print " Value ",$treeref->{val}," = ",$treeref->val_to_text(),"\n" if $Debug; #$treeref->tree_dump() if $Debug; $treeref->{val_size} = $treeref->{val}->Size; # Debugging $treeref->{val_text} = $treeref->{val}->to_Hex; # Debugging ($treeref->{val}->Size == $treeref->{width}) or die "%Error: Size mismatch ",$treeref->{val}->Size,"!=",$treeref->{width},"\n",Dumper($treeref); return $treeref; } sub gen_v { my $opref = shift; my $fmt = $opref->{v}; $fmt =~ s/%1/%s/g; $fmt =~ s/%2/%s/g; $fmt =~ s/%3/%s/g; $fmt =~ s/%v/%s/g; $fmt =~ s/%i/%s/g; $fmt =~ s/%x[wds]/%s/g; my $argl = $opref->{v}; my @args; while ($argl =~ s/(%x.|%.)//) { my $arg = $1; push @args, '$treeref->{op1}{text}' if $arg =~ /%1/; push @args, '$treeref->{op2}{text}' if $arg =~ /%2/; push @args, '$treeref->{op3}{text}' if $arg =~ /%3/; push @args, '$treeref->val_to_text' if $arg =~ /%v/; push @args, '$treeref->{id}' if $arg =~ /%i/; push @args, '$treeref->{signed}?"s":""' if $arg =~ /%xs/; push @args, '$treeref->{width}' if $arg =~ /%xw/; push @args, '$treeref->{width}-$treeref->{op1}{width}' if $arg =~ /%xd/; } my $func = ("sub { " ." my \$treeref = shift;" ." sprintf(\"$fmt\",".join(',',@args).");" ."}"); my $set = ("\$opref->{v_sub} = $func; 1;"); $opref->{v_sub_text} = $func; # For seeing it in debugging dumps #print "Op V $opref->{name} $set\n"; eval($set) or die "%Error: Can't eval:\n$set\n $@ "; } sub escapes { my $str = shift; my $cmt = shift; $str =~ s/%tr/\$treeref/g; $str =~ s/%tg/\$treeref->{signed}/g; $str =~ s/%tv/\$treeref->{val}/g; $str =~ s/%tw/\$treeref->{width}/g; # $str =~ s/%1r/\$treeref->{op1}/g; $str =~ s/%1g/\$treeref->{op1}{signed}/g; $str =~ s/%1n/(\$treeref->{op1}{val}->Word_Read(0))/g; $str =~ s/%1v/\$treeref->{op1}{val}/g; $str =~ s/%1w/\$treeref->{op1}{width}/g; # $str =~ s/%2r/\$treeref->{op2}/g; $str =~ s/%2g/\$treeref->{op2}{signed}/g; $str =~ s/%2n/(\$treeref->{op2}{val}->Word_Read(0))/g; $str =~ s/%2v/\$treeref->{op2}{val}/g; $str =~ s/%2w/\$treeref->{op2}{width}/g; # $str =~ s/%3r/\$treeref->{op3}/g; $str =~ s/%3g/\$treeref->{op3}{signed}/g; $str =~ s/%3n/(\$treeref->{op3}{val}->Word_Read(0))/g; $str =~ s/%3v/\$treeref->{op3}{val}/g; $str =~ s/%3w/\$treeref->{op3}{width}/g; # $str =~ s/%i/\$treeref->{id}/g; ($str !~ /%/) or die "%Error: $cmt: Unknown %% escape in $str,"; return $str; } sub gen_pl { my $opref = shift; my $str = escapes($opref->{pl}, $opref->{name}); my $func = ("sub { " ." my \$treeref = shift;" ." $str;" ."}"); my $set = ("\$opref->{pl_sub} = $func; 1;"); $opref->{pl_sub_text} = $func; # For seeing it in debugging dumps #print "Op PL $opref->{name} $set\n"; eval($set) or die "%Error: Can't eval:\n$set\n $@ "; } sub gen_rnd { my $opref = shift; my $str = escapes($opref->{rnd}, $opref->{name}); my $func = ("sub { " ." my \$treeref = shift;" ." $str;" ."}"); my $set = ("\$opref->{rnd_sub} = $func; 1;"); $opref->{rnd_sub_text} = $func; # For seeing it in debugging dumps #print "Op RND $opref->{name} $set\n"; eval($set) or die "%Error: Can't eval:\n$set\n $@ "; } sub stop_text { return '$stop'; } sub decl_text { my $var = shift; my $decl_with = shift; my $varref = $Vars{$var}; return sprintf(" reg %s [%3d:%3d] %s %s; //=%d'h%s" , ($varref->{signed}?"signed":" ") , ($varref->{val}->Size)-1+$VarAttrs{$var}{lsb}, , $VarAttrs{$var}{lsb} , $var , (rnd(100)<30 ? "/*verilator public*/":(" "x length("/*verilator public*/"))) , $varref->{val}->Size , lc $varref->{val}->to_Hex); } ####################################################################### ####################################################################### ####################################################################### ####################################################################### # Math Functions sub selftest { my $o = {}; VDIV($o, {val=>Bit::Vector->new_Dec(8,0xff)}, {val=>Bit::Vector->new_Dec(8,0x13)}, 0); ($o->{val}->Word_Read(0) == 0x0d) or die; VDIV($o, {val=>Bit::Vector->new_Dec(8,0xff)}, {val=>Bit::Vector->new_Dec(8,0x13)}, 1); ($o->{val}->Word_Read(0) == 0x08) or die; VDIV($o, {val=>Bit::Vector->new_Dec(8,0xff), signed=>1}, {val=>Bit::Vector->new_Dec(8,0x13), signed=>1}, 0); ($o->{val}->Word_Read(0) == 0x00) or die; VDIV($o, {val=>Bit::Vector->new_Dec(8,0xff), signed=>1}, {val=>Bit::Vector->new_Dec(8,0x13), signed=>1}, 1); ($o->{val}->Word_Read(0) == 0xff) or die; VDIV($o, {val=>Bit::Vector->new_Dec(8,0xff), signed=>1}, {val=>Bit::Vector->new_Dec(8,0xdb), signed=>1}, 1); ($o->{val}->Word_Read(0) == 0xff) or die; VDIV($o, {val=>Bit::Vector->new_Dec(8,0x72), signed=>1}, {val=>Bit::Vector->new_Dec(8,0xdb), signed=>1}, 1); ($o->{val}->Word_Read(0) == 0x3) or die; } sub val_leaf { return {width=>32, signed=>0, val=>Bit::Vector->new_Dec(32,$_[0]), text=>$_[0],}; } sub makebool { return (Bit::Vector->new_Dec(1,$_[0])); } sub newsized { return (Bit::Vector->new($_[0]->Size)); } sub max { return $_[0]<$_[1] ? $_[1] : $_[0]; } sub min { return $_[0]>$_[1] ? $_[1] : $_[0]; } sub log2 { for (my $i=31; $i>=0; $i--) { return $i+1 if $_[0]>(1<<$i); } return 0; } sub countones { my $out = 0; for (my $bit=0; $bit < $_[0]->Size; $bit++) { $out ++ if $_[0]->bit_test($bit); } return $out; } sub VLOGNOT { $_[0]{val} = makebool(($_[1]->is_empty)?1:0); } sub VNEGATE { $_[0]{val} = my $o = newsized($_[1]); $o->Negate($_[1]); } sub VCOUNTONES { $_[0]{val} = Bit::Vector->new_Dec(32,countones($_[1])); } sub VONEHOT { $_[0]{val} = makebool((countones($_[1])==1)?1:0); } sub VONEHOT0 { $_[0]{val} = makebool((countones($_[1])<=1)?1:0); } sub VLOGAND { $_[0]{val} = makebool((!($_[1]->is_empty) && !($_[2]->is_empty))?1:0); } sub VLOGOR { $_[0]{val} = makebool((!($_[1]->is_empty) || !($_[2]->is_empty))?1:0); } sub VCOND { if (!($_[1]->is_empty)) { $_[0]{val}=$_[2]->Clone; } else { $_[0]{val}=$_[3]->Clone; } } sub VREDAND { $_[0]{val} = makebool(($_[1]->is_full)?1:0); } sub VREDOR { $_[0]{val} = makebool(($_[1]->is_empty)?0:1); } sub VREDNAND { $_[0]{val} = makebool(($_[1]->is_full)?0:1); } sub VREDNOR { $_[0]{val} = makebool(($_[1]->is_empty)?1:0); } sub VREDXOR { my $out = 0; for (my $bit=0; $bit < $_[1]->Size; $bit++) { $out ^= $_[1]->bit_test($bit); } $_[0]{val} = makebool($out); } sub VREDXNOR { my $out = 1; for (my $bit=0; $bit < $_[1]->Size; $bit++) { $out ^= $_[1]->bit_test($bit); } $_[0]{val} = makebool($out); } sub eithercompare { ($_[1]->{signed} && $_[2]->{signed}) ? $_[1]{val}->Compare($_[2]{val}) : $_[1]{val}->Lexicompare($_[2]{val}); } sub VEQ { $_[0]{val} = makebool( (eithercompare($_[0],$_[1],$_[2])==0) ?1:0); } sub VNE { $_[0]{val} = makebool( (eithercompare($_[0],$_[1],$_[2])!=0) ?1:0); } sub VLT { $_[0]{val} = makebool( (eithercompare($_[0],$_[1],$_[2])< 0) ?1:0); } sub VLE { $_[0]{val} = makebool( (eithercompare($_[0],$_[1],$_[2])<=0) ?1:0); } sub VGT { $_[0]{val} = makebool( (eithercompare($_[0],$_[1],$_[2])> 0) ?1:0); } sub VGE { $_[0]{val} = makebool( (eithercompare($_[0],$_[1],$_[2])>=0) ?1:0); } sub VSHIFTLxx { print "$Vars{vq}->ShiftL($_[0],$_[1]);\n"; print " ",$_[0]->to_Hex," ",$_[1]->to_Hex,";\n"; my $out = $_[0]->Clone; $out->Move_Left($_[1]->Word_Read(0)); print $out->to_Hex,"\n"; return $out; } sub VAND { $_[0]{val}=my $o=newsized($_[1]); $o->Intersection($_[1],$_[2]); } sub VOR { $_[0]{val}=my $o=newsized($_[1]); $o->Union($_[1],$_[2]); } sub VNAND { $_[0]{val}=my $o=newsized($_[1]); $o->Intersection($_[1],$_[2]); $o->Complement($o); } sub VNOR { $_[0]{val}=my $o=newsized($_[1]); $o->Union($_[1],$_[2]); $o->Complement($o); } sub VXOR { $_[0]{val}=my $o=newsized($_[1]); $o->ExclusiveOr($_[1],$_[2]); } sub VXNOR{ $_[0]{val}=my $o=newsized($_[1]); $o->ExclusiveOr($_[1],$_[2]); $o->Complement($o); } sub VNOT { $_[0]{val}=my $o=newsized($_[1]); $o->Complement($_[1]); } sub VSHIFTL{ $_[0]{val}=my $o=$_[1]->Clone; $o->Move_Left ($_[2]->Word_Read(0)); } sub VSHIFTR{ $_[0]{val}=my $o=$_[1]->Clone; $o->Move_Right($_[2]->Word_Read(0)); } sub VSHIFTRS{$_[0]{val}=my $o=$_[1]->Clone; $o->Move_Right($_[2]->Word_Read(0)); if ($_[1]->msb() && $_[2]->Word_Read(0)>0) {$o->Interval_Fill(max(0,$o->Size-1-$_[2]->Word_Read(0)), $o->Size-1); } #print (" SHI ",$_[0]{val}->to_Hex,' = ',$_[1]->to_Hex,' >>> ',$_[2]->Word_Read(0),"\n"); } sub VCLONE { $_[0]{val}=$_[1]->Clone; } sub VRESIZE { $_[0]{val}=$_[1]->Clone; $_[0]{val}->Resize($_[0]{width}); } sub VADD { $_[0]{val}=my $o=newsized($_[1]); $o->add($_[1],$_[2],0); } sub VSUB { $_[0]{val}=my $o=newsized($_[1]); $o->subtract($_[1],$_[2],0); } sub VMUL { # Multiply is signed, so need an additional sign bit my $a=$_[1]->Clone; $a->Resize($a->Size + 1); my $b=$_[2]->Clone; $b->Resize($b->Size + 1); my $mo=Bit::Vector->new($_[1]->Size + $_[2]->Size + 1); $mo->Multiply($a,$b); my $o=newsized($_[1]); $o->Interval_Copy($mo,0,0,$_[1]->Size); $_[0]{val}=$o; } sub VDIV { my $is_mod = $_[3]; if ($_[2]{val}->is_empty) { # Avoid divide by zero $_[0]{val}=newsized($_[1]{val}); return; } my $a=$_[1]{val}->Clone; if (!$_[1]->{signed}) { $a->Resize($a->Size + 1); } my $b=$_[2]{val}->Clone; if (!$_[2]->{signed}) { $b->Resize($b->Size + 1); } #print ("//DIVpp ",$_[1]->to_Hex,' ',$_[2]->to_Hex,' ',$_[1]->Size,'.',$_[2]->Size," \n"); #print ("//DIVpp ",$a->to_Hex,' ',$b->to_Hex,' ',$a->Size,'.',$b->Size," \n"); my $quo=newsized($a); my $rem=newsized($a); $quo->Divide($a,$b,$rem); # No division by zero - handled by if above my $o=newsized($_[1]{val}); $o->Interval_Copy($is_mod ? $rem : $quo,0,0,$_[1]{val}->Size); #print "//DIV",($_[1]->{signed}?"S":" "),' w',$a->Size,' ',$_[1]{val}->to_Hex,' ',$_[2]{val}->to_Hex,' =',$quo->to_Hex,'.',$rem->to_Hex," \n"; $_[0]{val}=$o; } sub VPOW { # Power is a signed operation my $a=$_[1]{val}->Clone; if (!$_[1]->{signed}) { $a->Resize($_[1]{val}->Size + 1); } my $b=$_[2]{val}->Clone; if (!$_[2]->{signed}) { $b->Resize($_[2]{val}->Size + 1); } print "VVpow = ",$_[1]{val}->to_Hex," ** ",$_[2]{val}->to_Hex,"\n"; my $mo=Bit::Vector->new($_[1]{val}->Size + 1); $mo->Power($a,$b); my $o=Bit::Vector->new($_[0]{width}); $o->Interval_Copy($mo,0,0,$_[1]{val}->Size); $_[0]{val}=$o; print "VV = $o\n"; } sub VRANGE { #print "RANGE ",$_[1]->to_Hex,' ',$_[2]->to_Hex,' ',$_[3]->to_Hex," \n"; return VRANGE_CONST($_[0], $_[1], $_[2]->Word_Read(0), $_[3]->Word_Read(0), $_[4]); } sub VBITSELP { return VRANGE_CONST($_[0], $_[1], $_[2]->Word_Read(0)+$_[3]->Word_Read(0)-1, $_[2]->Word_Read(0), $_[4]); } sub VBITSELM { return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0), $_[2]->Word_Read(0)-$_[3]->Word_Read(0)+1, $_[4]); } sub VRANGE_CONST { # to, from, msb, lsb, variable_lsb_to_subtract #print "RANGE ",$_[1]->to_Hex,' ',$_[2],' ',$_[3],' ',$_[4]," \n"; my $size = $_[2] - $_[3] + 1; my $o=Bit::Vector->new($size); if ($_[3] < $_[1]->Size) { $o->Interval_Copy($_[1],0,$_[3]-$_[4],$size); } $_[0]{val}=$o; } sub VCONCAT { my $o=Bit::Vector->new($_[1]->Size + $_[2]->Size); $o->Interval_Copy($_[1],$_[2]->Size,0,$_[1]->Size); $o->Interval_Copy($_[2],0,0,$_[2]->Size); $_[0]{val}=$o; } sub VREPLIC { my $o=Bit::Vector->new($_[1]->Word_Read(0) * $_[2]->Size); my $pos = 0; for (my $time=0; $time<($_[1]->Word_Read(0)); $time++) { $o->Interval_Copy($_[2],$pos,0,$_[2]->Size); $pos += $_[2]->Size; } $_[0]{val}=$o; } ####################################################################### ####################################################################### ####################################################################### package Vg::Base; use Data::Dumper; use strict; #------------------------------------------------------------ # CREATORS sub new { my $class = shift; my $self = { width=>0, # Width of expression, 0=Pick a width #signed=>0/1, # Undef = pick a sign @_}; bless $self, $class; return $self; } # ACCESSORS #------------------------------------------------------------ # OUTPUTTING sub val_to_text { my $treeref = shift; my $val = lc $treeref->{val}->to_Hex(); $val = "0" if $treeref->{val}->is_empty; return ($treeref->{width} .($treeref->{signed}?"'sh":"'h") .$val); } sub tree_dump { my $treeref = shift; print Dumper($treeref); } ####################################################################### __END__ =pod =head1 NAME vgen.pl - Generate random verilog code =head1 SYNOPSIS vgen.pl -o vgen.v =head1 DESCRIPTION vgen.pl generates automatic random verilog programs. =head1 ARGUMENTS =over 4 =item --help Displays this message and program version and exits. =item --blockstmts Number of statements per block. Defaults to 2. =item --depth Maximum depth of generated expressions. =item --initial Put all statements into an initial block. This will probably be optimized down to a NOP. =item --numops Number of operations to create. =item -o I Specify output filename. =item --raise Pick the specified number of random opcodes, and raise their frequency. =item --seed Seed for the random number generator. Defaults to 5, 0=randomize. =item --signed Include some signed arithmetic in the generated code. Experimental. =back =head1 DISTRIBUTION Copyright 2001-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS Wilson Snyder =head1 SEE ALSO =cut ###################################################################### ### Local Variables: ### compile-command: "./vgen.pl --depth=10 --blockstmts=10 -o obj_dir/vgen.v" ### compile-command: "v4make test_regress/t/t_vgen.pl " ### End: verilator-4.038/test_regress/.gitignore0000664000177100017500000000021113702133367020214 0ustar wsnyderwsnyder*.old obj_dir obj_* vcs.key csrc cov_work simv* simx* *.log *.key ncverilog.* INCA_libs logs .vcsmx_rebuild vc_hdrs.h xsim.*/ *.jou *.pb verilator-4.038/test_regress/CMakeLists.txt0000664000177100017500000000633313702133367020777 0ustar wsnyderwsnyder###################################################################### # # DESCRIPTION: CMake script for regression tests # # This CMake file is meant to be consumed by regression tests. # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### cmake_minimum_required(VERSION 3.8) set(TEST_REQUIRED_VARS NAME CSOURCES OPT_FAST OPT_GLOBAL VERILATOR_ROOT VERILATOR_ARGS VERILATOR_SOURCES SYSTEMC VERBOSE VERILATION) foreach(var ${TEST_REQUIRED_VARS}) if (NOT DEFINED TEST_${var}) message(FATAL_ERROR "TEST_${var} not defined. This CMakeLists.txt file is meant to be run by driver.pl.") endif() endforeach() project("${TEST_NAME}") if(TEST_VERBOSE) add_definitions(-DTEST_VERBOSE=1) endif() separate_arguments(TEST_VERILATOR_ARGS UNIX_COMMAND "${TEST_VERILATOR_ARGS}") # filter out empty arguments list(FILTER TEST_VERILATOR_ARGS EXCLUDE REGEX "$^") set(TEST_PREFIX ${TEST_NAME}) # If --ARG is present, set OUT = function(getarg LST ARG OUT) list(FIND ${LST} ${ARG} _INDEX) if(NOT _INDEX EQUAL -1) list(REMOVE_AT ${LST} ${_INDEX}) list(GET ${LST} ${_INDEX} VAL) set(${OUT} ${VAL} PARENT_SCOPE) endif() endfunction() # Normalise -- to - string(REGEX REPLACE "(^|;)--" "\\1-" TEST_VERILATOR_ARGS_NORM "${TEST_VERILATOR_ARGS}") getarg(TEST_VERILATOR_ARGS_NORM "-prefix" TEST_PREFIX) getarg(TEST_VERILATOR_ARGS_NORM "-threads" TEST_THREADS) # Strip unwanted args with 1 parameter string(REGEX REPLACE "(^|;)--?(Mdir|make|prefix|threads);[^;]*" "" TEST_VERILATOR_ARGS "${TEST_VERILATOR_ARGS}") # Strip unwanted args string(REGEX REPLACE "(^|;)--?(sc|cc)" "" TEST_VERILATOR_ARGS "${TEST_VERILATOR_ARGS}") separate_arguments(TEST_VERILATOR_SOURCES UNIX_COMMAND "${TEST_VERILATOR_SOURCES}") # filter out empty sources list(FILTER TEST_VERILATOR_SOURCES EXCLUDE REGEX "$^") find_package(verilator REQUIRED HINTS ${TEST_VERILATOR_ROOT}) set(verilate_ARGS MAIN) if(TEST_PREFIX) list(APPEND verilate_ARGS PREFIX ${TEST_PREFIX}) endif() if(TEST_OPT_FAST) list(APPEND verilate_ARGS OPT_FAST ${TEST_OPT_FAST}) endif() if(TEST_OPT_GLOBAL) list(APPEND verilate_ARGS OPT_GLOBAL ${TEST_OPT_GLOBAL}) endif() if(TEST_THREADS) list(APPEND verilate_ARGS THREADS ${TEST_THREADS}) endif() if(TEST_SYSTEMC) list(APPEND verilate_ARGS SYSTEMC) endif() set(TARGET_NAME "V${TEST_NAME}") add_executable(${TARGET_NAME} ${TEST_CSOURCES}) if(TEST_VERILATION) verilate(${TARGET_NAME} ${verilate_ARGS} VERILATOR_ARGS ${TEST_VERILATOR_ARGS} DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} SOURCES ${TEST_VERILATOR_SOURCES}) endif() if(TEST_SYSTEMC) verilator_link_systemc("${TARGET_NAME}") endif() string(TOUPPER "${TEST_NAME}" TEST_NAME_UC) target_compile_definitions(${TARGET_NAME} PRIVATE "TEST_OBJ_DIR=${CMAKE_CURRENT_BINARY_DIR}" "VM_PREFIX=${TEST_PREFIX}" "VM_PREFIX_INCLUDE=<${TEST_PREFIX}.h>" "${TEST_NAME_UC}" ) verilator-4.038/test_regress/t/0000775000177100017500000000000013702335707016477 5ustar wsnyderwsnyderverilator-4.038/test_regress/t/t_class_extends_this.pl0000775000177100017500000000117613702133367023253 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_output_type.cpp0000664000177100017500000006101513702133370023607 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_output_type__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; # else # error "Unknown simulator for DPI test" #endif //====================================================================== // Implementations of imported functions //====================================================================== void set_bvals(svLogicVecVal* v, unsigned n); void set_bvals(svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { v[i].bval = 0; } } // Basic types as per IEEE 1800-2017 35.5.6 void i_byte(char* o) { static int n = 0; *o = 10 - n++; } void i_byte_unsigned(unsigned char* o) { static int n = 0; *o = 20 - n++; } void i_shortint(short* o) { static int n = 0; *o = 30 - n++; } void i_shortint_unsigned(unsigned short* o) { static int n = 0; *o = 40 - n++; } void i_int(int* o) { static int n = 0; *o = 50 - n++; } void i_int_unsigned(unsigned* o) { static int n = 0; *o = 60 - n++; } void i_longint(sv_longint_t* o) { static int n = 0; *o = 70 - n++; } void i_longint_unsigned(sv_longint_unsigned_t* o) { static int n = 0; *o = 80 - n++; } #ifndef NO_TIME void i_time(svLogicVecVal* o) { static int n = 0; o[0].aval = 90 - n++; o[1].aval = 0; set_bvals(o, 2); } #endif #ifndef NO_INTEGER void i_integer(svLogicVecVal* o) { static int n = 0; o->aval = 100 - n++; set_bvals(o, 1); } #endif void i_real(double* o) { static int n = 0; *o = (-2.0 * n++ - 1.0) / 2.0; } #ifndef NO_SHORTREAL void i_shortreal(float* o) { static int n = 0; *o = (-4.0f * n++ - 1.0f) / 4.0f; } #endif void i_chandle(void** o) { static int n = 0; printf("i_chandle %d\n", n); *o = (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } void i_string(const char** o) { static int n = 0; printf("i_string %d\n", n); *o = (n++ % 2) ? "Hello" : "World"; } void i_bit(svBit* o) { static int n = 0; printf("i_bit %d\n", n); *o = !(n++ % 2); } void i_logic(svLogic* o) { static int n = 0; printf("i_logic %d\n", n); *o = n++ % 2; } // Basic types via typedefs void i_byte_t(char* o) { static int n = 0; const char r = 10 - n; n += 2; *o = r; } void i_byte_unsigned_t(unsigned char* o) { static int n = 0; const unsigned char r = 20 - n; n += 2; *o = r; } void i_shortint_t(short* o) { static int n = 0; const short r = 30 - n; n += 2; *o = r; } void i_shortint_unsigned_t(unsigned short* o) { static int n = 0; const unsigned short r = 40 - n; n += 2; *o = r; } void i_int_t(int* o) { static int n = 0; const int r = 50 - n; n += 2; *o = r; } void i_int_unsigned_t(unsigned* o) { static int n = 0; const unsigned r = 60 - n; n += 2; *o = r; } void i_longint_t(sv_longint_t* o) { static int n = 0; const long long r = 70 - n; n += 2; *o = r; } void i_longint_unsigned_t(sv_longint_unsigned_t* o) { static int n = 0; const unsigned long long r = 80 - n; n += 2; *o = r; } #ifndef NO_TIME void i_time_t(svLogicVecVal* o) { static int n = 0; o[0].aval = 90 - n; o[1].aval = 0; set_bvals(o, 2); n += 2; } #endif #ifndef NO_INTEGER void i_integer_t(svLogicVecVal* o) { static int n = 0; o->aval = 100 - n; set_bvals(o, 1); n += 2; } #endif void i_real_t(double* o) { static int n = 0; const double r = (-2.0 * n - 1.0) / 2.0; n += 2; *o = r; } #ifndef NO_SHORTREAL void i_shortreal_t(float* o) { static int n = 0; const float r = (-4.0f * n - 1.0f) / 4.0f; n += 2; *o = r; } #endif void i_chandle_t(void** o) { static int n = 0; printf("i_chandle_t %d\n", n); *o = (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } void i_string_t(const char** o) { static int n = 0; printf("i_string_t %d\n", n); *o = (n++ % 2) ? "Hello" : "World"; } void i_bit_t(svBit* o) { static int n = 0; printf("i_bit_t %d\n", n); *o = !(n++ % 2); } void i_logic_t(svLogic* o) { static int n = 0; printf("i_logic_t %d\n", n); *o = n++ % 2; } // 2-state packed arrays void i_array_2_state_1(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_1 %d\n", n); *o = !(n++ % 2); } void i_array_2_state_32(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_32 %d\n", n); *o = 0xffffffffU << n++; } void i_array_2_state_33(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_33 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = 1; } void i_array_2_state_64(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_64 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; } void i_array_2_state_65(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_65 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = 1; } void i_array_2_state_128(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_128 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = -1; o[3] = -1; } // 2-state packed structures void i_struct_2_state_1(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_1 %d\n", n); *o = !(n++ % 2); } void i_struct_2_state_32(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_32 %d\n", n); *o = 0xffffffffU << n++; } void i_struct_2_state_33(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_33 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = 1; } void i_struct_2_state_64(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_64 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; } void i_struct_2_state_65(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_65 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = 1; } void i_struct_2_state_128(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_128 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = -1; o[3] = -1; } // 2-state packed unions void i_union_2_state_1(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_1 %d\n", n); *o = !(n++ % 2); } void i_union_2_state_32(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_32 %d\n", n); *o = 0xffffffffU << n++; } void i_union_2_state_33(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_33 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = 1; } void i_union_2_state_64(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_64 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; } void i_union_2_state_65(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_65 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = 1; } void i_union_2_state_128(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_128 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = -1; o[3] = -1; } // 4-state packed arrays void i_array_4_state_1(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_1 %d\n", n); o->aval = !(n++ % 2); set_bvals(o, 1); } void i_array_4_state_32(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_32 %d\n", n); o->aval = 0xffffffffU << n++; set_bvals(o, 1); } void i_array_4_state_33(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_33 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = 1; set_bvals(o, 2); } void i_array_4_state_64(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_64 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; set_bvals(o, 2); } void i_array_4_state_65(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_65 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = 1; set_bvals(o, 3); } void i_array_4_state_128(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_128 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = -1; o[3].aval = -1; set_bvals(o, 4); } // 4-state packed structures void i_struct_4_state_1(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_1 %d\n", n); o->aval = !(n++ % 2); set_bvals(o, 1); } void i_struct_4_state_32(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_32 %d\n", n); o->aval = 0xffffffffU << n++; set_bvals(o, 1); } void i_struct_4_state_33(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_33 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = 1; set_bvals(o, 2); } void i_struct_4_state_64(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_64 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; set_bvals(o, 2); } void i_struct_4_state_65(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_65 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = 1; set_bvals(o, 3); } void i_struct_4_state_128(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_128 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = -1; o[3].aval = -1; set_bvals(o, 4); } // 4-state packed unions void i_union_4_state_1(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_1 %d\n", n); o->aval = !(n++ % 2); set_bvals(o, 1); } void i_union_4_state_32(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_32 %d\n", n); o->aval = 0xffffffffU << n++; set_bvals(o, 1); } void i_union_4_state_33(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_33 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = 1; set_bvals(o, 2); } void i_union_4_state_64(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_64 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; set_bvals(o, 2); } void i_union_4_state_65(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_65 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = 1; set_bvals(o, 3); } void i_union_4_state_128(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_128 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = -1; o[3].aval = -1; set_bvals(o, 4); } //====================================================================== // Check exported functions //====================================================================== #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void check_bvals(const svLogicVecVal* v, unsigned n); void check_bvals(const svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { if (v[i].bval != 0) { printf(__FILE__ ":%d Bad svLogicVecVal bval\n", __LINE__); abort(); } } } void check_exports() { static unsigned n = 0; char x_byte; unsigned char x_byte_unsigned; short x_shortint; unsigned short x_shortint_unsigned; int x_int; unsigned x_int_unsigned; sv_longint_t x_longint; sv_longint_unsigned_t x_longint_unsigned; #ifndef NO_TIME svLogicVecVal x_time[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer[1]; #endif double x_real; #ifndef NO_SHORTREAL float x_shortreal; #endif void* x_chandle; const char* x_string; svBit x_bit; svLogic x_logic; char x_byte_t; unsigned char x_byte_unsigned_t; short x_shortint_t; unsigned short x_shortint_unsigned_t; int x_int_t; unsigned x_int_unsigned_t; sv_longint_t x_longint_t; sv_longint_unsigned_t x_longint_unsigned_t; #ifndef NO_TIME svLogicVecVal x_time_t[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer_t[1]; #endif double x_real_t; #ifndef NO_SHORTREAL float x_shortreal_t; #endif void* x_chandle_t; const char* x_string_t; svBit x_bit_t; svLogic x_logic_t; svBitVecVal x_array_2_state_1[1]; svBitVecVal x_array_2_state_32[1]; svBitVecVal x_array_2_state_33[2]; svBitVecVal x_array_2_state_64[2]; svBitVecVal x_array_2_state_65[3]; svBitVecVal x_array_2_state_128[4]; svBitVecVal x_struct_2_state_1[1]; svBitVecVal x_struct_2_state_32[1]; svBitVecVal x_struct_2_state_33[2]; svBitVecVal x_struct_2_state_64[2]; svBitVecVal x_struct_2_state_65[3]; svBitVecVal x_struct_2_state_128[4]; svBitVecVal x_union_2_state_1[1]; svBitVecVal x_union_2_state_32[1]; svBitVecVal x_union_2_state_33[2]; svBitVecVal x_union_2_state_64[2]; svBitVecVal x_union_2_state_65[3]; svBitVecVal x_union_2_state_128[4]; svLogicVecVal x_array_4_state_1[1]; svLogicVecVal x_array_4_state_32[1]; svLogicVecVal x_array_4_state_33[2]; svLogicVecVal x_array_4_state_64[2]; svLogicVecVal x_array_4_state_65[3]; svLogicVecVal x_array_4_state_128[4]; svLogicVecVal x_struct_4_state_1[1]; svLogicVecVal x_struct_4_state_32[1]; svLogicVecVal x_struct_4_state_33[2]; svLogicVecVal x_struct_4_state_64[2]; svLogicVecVal x_struct_4_state_65[3]; svLogicVecVal x_struct_4_state_128[4]; svLogicVecVal x_union_4_state_1[1]; svLogicVecVal x_union_4_state_32[1]; svLogicVecVal x_union_4_state_33[2]; svLogicVecVal x_union_4_state_64[2]; svLogicVecVal x_union_4_state_65[3]; svLogicVecVal x_union_4_state_128[4]; // Basic types as per IEEE 1800-2017 35.5.6 e_byte(&x_byte); if (x_byte != 10 + n) stop(); e_byte_unsigned(&x_byte_unsigned); if (x_byte_unsigned != 20 + n) stop(); e_shortint(&x_shortint); if (x_shortint != 30 + n) stop(); e_shortint_unsigned(&x_shortint_unsigned); if (x_shortint_unsigned != 40 + n) stop(); e_int(&x_int); if (x_int != 50 + n) stop(); e_int_unsigned(&x_int_unsigned); if (x_int_unsigned != 60 + n) stop(); e_longint(&x_longint); if (x_longint != 70 + n) stop(); e_longint_unsigned(&x_longint_unsigned); if (x_longint_unsigned != 80 + n) stop(); #ifndef NO_TIME e_time(x_time); if (x_time[0].aval != 90 + n || x_time[1].aval != 0) stop(); check_bvals(x_time, 2); #endif #ifndef NO_INTEGER e_integer(x_integer); if (x_integer[0].aval != 100 + n) stop(); check_bvals(x_integer, 1); #endif e_real(&x_real); if (x_real != 1.0 * n + 0.5) stop(); #ifndef NO_SHORTREAL e_shortreal(&x_shortreal); if (x_shortreal != 1.0f * n + 0.25f) stop(); #endif e_chandle(&x_chandle); if (x_chandle != NULL) stop(); e_string(&x_string); if ((n % 2) == 0) { if (strcmp(x_string, "Hello") != 0) stop(); } else { if (strcmp(x_string, "World") != 0) stop(); } e_bit(&x_bit); if (x_bit != (n % 2)) stop(); e_logic(&x_logic); if (x_logic != !(n % 2)) stop(); // Basic types via tyepdef e_byte_t(&x_byte_t); if (x_byte_t != 10 + 2 * n) stop(); e_byte_unsigned_t(&x_byte_unsigned_t); if (x_byte_unsigned_t != 20 + 2 * n) stop(); e_shortint_t(&x_shortint_t); if (x_shortint_t != 30 + 2 * n) stop(); e_shortint_unsigned_t(&x_shortint_unsigned_t); if (x_shortint_unsigned_t != 40 + 2 * n) stop(); e_int_t(&x_int_t); if (x_int_t != 50 + 2 * n) stop(); e_int_unsigned_t(&x_int_unsigned_t); if (x_int_unsigned_t != 60 + 2 * n) stop(); e_longint_t(&x_longint_t); if (x_longint_t != 70 + 2 * n) stop(); e_longint_unsigned_t(&x_longint_unsigned_t); if (x_longint_unsigned_t != 80 + 2 * n) stop(); #ifndef NO_TIME e_time_t(x_time_t); if (x_time_t[0].aval != 90 + 2 * n || x_time_t[1].aval != 0) stop(); check_bvals(x_time_t, 2); #endif #ifndef NO_INTEGER e_integer_t(x_integer_t); if (x_integer_t[0].aval != 100 + 2 * n) stop(); check_bvals(x_integer_t, 1); #endif e_real_t(&x_real_t); if (x_real_t != 1.0 * (2 * n) + 0.5) stop(); #ifndef NO_SHORTREAL e_shortreal_t(&x_shortreal_t); if (x_shortreal_t != 1.0f * (2 * n) + 0.25f) stop(); #endif e_chandle_t(&x_chandle_t); if (x_chandle_t != NULL) stop(); e_string_t(&x_string_t); if ((n % 2) == 0) { if (strcmp(x_string_t, "Hello") != 0) stop(); } else { if (strcmp(x_string_t, "World") != 0) stop(); } e_bit_t(&x_bit_t); if (x_bit_t != (n % 2)) stop(); e_logic_t(&x_logic_t); if (x_logic_t != !(n % 2)) stop(); const int m = n == 0 ? 0 : n - 1; // 2-state packed arrays e_array_2_state_1(x_array_2_state_1); if (x_array_2_state_1[0] != (n % 2)) stop(); e_array_2_state_32(x_array_2_state_32); if (x_array_2_state_32[0] != 0xffffffff >> n) stop(); e_array_2_state_33(x_array_2_state_33); if (x_array_2_state_33[1] != 1 >> n) stop(); if (x_array_2_state_33[0] != 0xffffffff >> m) stop(); e_array_2_state_64(x_array_2_state_64); if (x_array_2_state_64[1] != 0xffffffff >> n) stop(); if (x_array_2_state_64[0] != 0xffffffff) stop(); e_array_2_state_65(x_array_2_state_65); if (x_array_2_state_65[2] != 1 >> n) stop(); if (x_array_2_state_65[1] != 0xffffffff >> m) stop(); if (x_array_2_state_65[0] != 0xffffffff) stop(); e_array_2_state_128(x_array_2_state_128); if (x_array_2_state_128[3] != 0xffffffff >> n) stop(); if (x_array_2_state_128[2] != 0xffffffff) stop(); if (x_array_2_state_128[1] != 0xffffffff) stop(); if (x_array_2_state_64[0] != 0xffffffff) stop(); // 2-state packed structures e_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1[0] != (n % 2)) stop(); e_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32[0] != 0xffffffff >> n) stop(); e_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33[1] != 1 >> n) stop(); if (x_struct_2_state_33[0] != 0xffffffff >> m) stop(); e_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64[1] != 0xffffffff >> n) stop(); if (x_struct_2_state_64[0] != 0xffffffff) stop(); e_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65[2] != 1 >> n) stop(); if (x_struct_2_state_65[1] != 0xffffffff >> m) stop(); if (x_struct_2_state_65[0] != 0xffffffff) stop(); e_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128[3] != 0xffffffff >> n) stop(); if (x_struct_2_state_128[2] != 0xffffffff) stop(); if (x_struct_2_state_128[1] != 0xffffffff) stop(); if (x_struct_2_state_64[0] != 0xffffffff) stop(); // 2-state packed unions e_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1[0] != (n % 2)) stop(); e_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32[0] != 0xffffffff >> n) stop(); e_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33[1] != 1 >> n) stop(); if (x_union_2_state_33[0] != 0xffffffff >> m) stop(); e_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64[1] != 0xffffffff >> n) stop(); if (x_union_2_state_64[0] != 0xffffffff) stop(); e_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65[2] != 1 >> n) stop(); if (x_union_2_state_65[1] != 0xffffffff >> m) stop(); if (x_union_2_state_65[0] != 0xffffffff) stop(); e_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128[3] != 0xffffffff >> n) stop(); if (x_union_2_state_128[2] != 0xffffffff) stop(); if (x_union_2_state_128[1] != 0xffffffff) stop(); if (x_union_2_state_64[0] != 0xffffffff) stop(); // 4-state packed arrays e_array_4_state_1(x_array_4_state_1); if (x_array_4_state_1[0].aval != (n % 2)) stop(); e_array_4_state_32(x_array_4_state_32); if (x_array_4_state_32[0].aval != 0xffffffff >> n) stop(); e_array_4_state_33(x_array_4_state_33); if (x_array_4_state_33[1].aval != 1 >> n) stop(); if (x_array_4_state_33[0].aval != 0xffffffff >> m) stop(); e_array_4_state_64(x_array_4_state_64); if (x_array_4_state_64[1].aval != 0xffffffff >> n) stop(); if (x_array_4_state_64[0].aval != 0xffffffff) stop(); e_array_4_state_65(x_array_4_state_65); if (x_array_4_state_65[2].aval != 1 >> n) stop(); if (x_array_4_state_65[1].aval != 0xffffffff >> m) stop(); if (x_array_4_state_65[0].aval != 0xffffffff) stop(); e_array_4_state_128(x_array_4_state_128); if (x_array_4_state_128[3].aval != 0xffffffff >> n) stop(); if (x_array_4_state_128[2].aval != 0xffffffff) stop(); if (x_array_4_state_128[1].aval != 0xffffffff) stop(); if (x_array_4_state_64[0].aval != 0xffffffff) stop(); check_bvals(x_array_4_state_1, 1); check_bvals(x_array_4_state_32, 1); check_bvals(x_array_4_state_33, 2); check_bvals(x_array_4_state_64, 2); check_bvals(x_array_4_state_65, 3); check_bvals(x_array_4_state_128, 4); // 4-state packed structures e_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1[0].aval != (n % 2)) stop(); e_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32[0].aval != 0xffffffff >> n) stop(); e_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33[1].aval != 1 >> n) stop(); if (x_struct_4_state_33[0].aval != 0xffffffff >> m) stop(); e_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64[1].aval != 0xffffffff >> n) stop(); if (x_struct_4_state_64[0].aval != 0xffffffff) stop(); e_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65[2].aval != 1 >> n) stop(); if (x_struct_4_state_65[1].aval != 0xffffffff >> m) stop(); if (x_struct_4_state_65[0].aval != 0xffffffff) stop(); e_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128[3].aval != 0xffffffff >> n) stop(); if (x_struct_4_state_128[2].aval != 0xffffffff) stop(); if (x_struct_4_state_128[1].aval != 0xffffffff) stop(); if (x_struct_4_state_64[0].aval != 0xffffffff) stop(); check_bvals(x_struct_4_state_1, 1); check_bvals(x_struct_4_state_32, 1); check_bvals(x_struct_4_state_33, 2); check_bvals(x_struct_4_state_64, 2); check_bvals(x_struct_4_state_65, 3); check_bvals(x_struct_4_state_128, 4); // 4-state packed unions e_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1[0].aval != (n % 2)) stop(); e_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32[0].aval != 0xffffffff >> n) stop(); e_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33[1].aval != 1 >> n) stop(); if (x_union_4_state_33[0].aval != 0xffffffff >> m) stop(); e_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64[1].aval != 0xffffffff >> n) stop(); if (x_union_4_state_64[0].aval != 0xffffffff) stop(); e_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65[2].aval != 1 >> n) stop(); if (x_union_4_state_65[1].aval != 0xffffffff >> m) stop(); if (x_union_4_state_65[0].aval != 0xffffffff) stop(); e_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128[3].aval != 0xffffffff >> n) stop(); if (x_union_4_state_128[2].aval != 0xffffffff) stop(); if (x_union_4_state_128[1].aval != 0xffffffff) stop(); if (x_union_4_state_64[0].aval != 0xffffffff) stop(); check_bvals(x_union_4_state_1, 1); check_bvals(x_union_4_state_32, 1); check_bvals(x_union_4_state_33, 2); check_bvals(x_union_4_state_64, 2); check_bvals(x_union_4_state_65, 3); check_bvals(x_union_4_state_128, 4); n++; } verilator-4.038/test_regress/t/t_detectarray_3.v0000664000177100017500000000145313702133370021735 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Simple test of unoptflat // // Trigger the DETECTARRAY error on packed structure. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; module t (/*AUTOARG*/ // Inputs clk, res ); input clk; output [8:0][8:0] res; logic a = 1'b1; logic [8:0] b [8:0]; // where the error is reported logic [8:0][8:0] c; // where the error is reported // following just to make c as circular assign c[0] = c[0] | a << 1; assign b[0] = b[0] | a << 2; assign res[0] = c[0]; assign res[1] = b[0]; always @(posedge clk or negedge clk) begin if (res != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_case_zx_bad.out0000664000177100017500000000047013702133367022014 0ustar wsnyderwsnyder%Warning-CASEWITHX: t/t_case_zx_bad.v:16:9: Use of x constant in casez statement, (perhaps intended ?/z in constant) 16 | 4'b1xxx: $stop; | ^~~~~~~ ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_flag_parameter.vc0000664000177100017500000000114413702133370022315 0ustar wsnyderwsnyder-Gstring1="\"New String\"" -pvalue+string2="\"New String\"" -Gstring11='"New String"' -pvalue+string12='"New String"' -Gstring21=\"New\ String\" -pvalue+string22=\"New\ String\" -Greal11=0.2 -pvalue+real12=0.2 -Greal21=4E2 -pvalue+real22=4e2 -Greal31=0.2e2 -pvalue+real32=0.2e2 -Greal41=0x123.4p1 -pvalue+real42=0X123.4P1 -Greal51=0x123p-1 -pvalue+real52=0X123P-1 -Gint11=0x10 -pvalue+int12=0x10 -Gint21=020 -pvalue+int22=020 -Gint31=123 -pvalue+int32=123 -Gint41=32'hdead_beef -pvalue+int42=32'hdead_beef -Gint51=32\'hdead_beef -pvalue+int52=32\'hdead_beef -Gint61="32'hdead_beef" -pvalue+int62="32'hdead_beef" verilator-4.038/test_regress/t/t_inst_dearray_slice.v0000664000177100017500000000320713702133370023046 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by engr248. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] in = 0; wire [31:0] out; Test test( .out(out[31:0]), .clk(clk), .in (in[31:0]) ); always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule interface Intf (); endinterface module Select #( parameter int NUM_MASTER = 1 ) ( Intf Upstream, Intf Downstream[NUM_MASTER] ); endmodule module Crossbar #( parameter int NUM_MASTER = 1, parameter int NUM_SLAVE = 1 ) ( Intf Masters[NUM_MASTER] ); Intf selectOut[(NUM_MASTER * (NUM_SLAVE+1))-1 : 0](); genvar i; for (i = 0; i < NUM_MASTER; i = i + 1) begin Select #( .NUM_MASTER(NUM_SLAVE+1) ) select_inst ( .Upstream(Masters[i]), // Following line triggered the dearrayAll segfault .Downstream(selectOut[(i+1)*(NUM_SLAVE+1) - 1 : i*(NUM_SLAVE+1)]) ); end endmodule module Test ( input clk, input [31:0] in, output reg [31:0] out ); always @(posedge clk) begin out <= in; end Intf MST[2](); //MST must have >1 array size to trigger dearrayAll segfault Crossbar #( .NUM_MASTER(2), .NUM_SLAVE(1) ) xbar_inst ( .Masters(MST) ); endmodule verilator-4.038/test_regress/t/t_math_reverse.pl0000775000177100017500000000105313702133370022035 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_real_abs.v0000664000177100017500000000230013702133370021757 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug591 module t (/*AUTOARG*/); function real ABS (real num); ABS = (num < 0) ? -num : num; endfunction function logic range_chk; input real last; input real period; input real cmp; range_chk = 0; if ( last >= 0 ) begin if ( ABS(last - period) > cmp ) begin range_chk = 1; end end endfunction function integer ceil; input num; real num; if (num > $rtoi(num)) ceil = $rtoi(num) + 1; else // verilator lint_off REALCVT ceil = num; // verilator lint_on REALCVT endfunction initial begin if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop; if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop; if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop; if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop; if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop; if (ceil(-2.1) != -2) $stop; if (ceil(2.1) != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_two_portfst_cc.out0000775000177100017500000000250213702133370023762 0ustar wsnyderwsnyder$date Sun Apr 19 04:13:00 2020 $end $version fstWriter $end $timescale 1ps $end $scope module topa $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $var integer 32 # c_trace_on $end $scope module sub $end $var integer 32 $ inside_sub_a $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars #10 b00000000000000000000000000000001 $ b00000000000000000000000000000000 # b00000000000000000000000000000001 " 1! #15 0! #20 1! b00000000000000000000000000000011 # b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " b00000000000000000000000000000100 # #35 0! #40 1! b00000000000000000000000000000101 # b00000000000000000000000000000100 " #45 0! #50 1! b00000000000000000000000000000101 " b00000000000000000000000000000110 # #55 0! #60 1! b00000000000000000000000000000111 # b00000000000000000000000000000110 " #65 0! #70 1! b00000000000000000000000000000111 " b00000000000000000000000000001000 # #75 0! #80 1! b00000000000000000000000000001001 # b00000000000000000000000000001000 " #85 0! #90 1! b00000000000000000000000000001001 " b00000000000000000000000000001010 # #95 0! #100 1! b00000000000000000000000000001011 # b00000000000000000000000000001010 " #105 0! #110 1! b00000000000000000000000000001100 # b00000000000000000000000000001011 " verilator-4.038/test_regress/t/t_interface_missing_bad.out0000664000177100017500000000072713702133370024050 0ustar wsnyderwsnyder%Error: t/t_interface_missing_bad.v:14:4: Cannot find file containing interface: 'foo_intf' 14 | foo_intf foo | ^~~~~~~~ %Error: t/t_interface_missing_bad.v:20:4: Cannot find file containing interface: 'foo_intf' 20 | foo_intf the_foo (); | ^~~~~~~~ %Error: t/t_interface_missing_bad.v:25:15: Found definition of 'the_foo' as a CELL but expected a variable 25 | .foo (the_foo) | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_order_comboclkloop.v0000664000177100017500000000330313702133370023056 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off BLKANDNBLK // verilator lint_off COMBDLY // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT // verilator lint_off MULTIDRIVEN reg [31:0] runnerm1, runner; initial runner = 0; reg [31:0] runcount; initial runcount = 0; reg [31:0] clkrun; initial clkrun = 0; reg [31:0] clkcount; initial clkcount = 0; always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end reg run0; always @ (/*AS*/runnerm1) begin if ((runner & 32'hf)!=0) begin runcount = runcount + 1; runner = runnerm1; $write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1); end run0 = (runner[8:4]!=0 && runner[3:0]==0); end always @ (posedge run0) begin // Do something that forces another combo run clkcount <= clkcount + 1; runner[8:4] <= runner[8:4] - 1; runner[3:0] <= 3; $write ("[%0t] posedge runner=%0x\n", $time, runner); end reg [7:0] cyc; initial cyc=0; always @ (posedge clk) begin $write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount); cyc <= cyc + 8'd1; case (cyc) 8'd00: begin runner <= 0; end 8'd01: begin runner <= 32'h35; end default: ; endcase case (cyc) 8'd02: begin if (runcount!=32'he) $stop; if (clkcount!=32'h3) $stop; end 8'd03: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase end endmodule verilator-4.038/test_regress/t/t_assoc_wildcard_unsup.out0000664000177100017500000000026613702133367023770 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_assoc_wildcard_unsup.v:25:19: Unsupported: [*] wildcard associative arrays 25 | string a [*]; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_tri_select_unsized.v0000664000177100017500000000146113702133370023101 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test of selection with unsized Z. // // Test selecting Z when size is not explicit. Issue 510. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [1:0] b; wire [1:0] c; wire [0:0] d; // Explicit width due to issue 508 wire [0:0] e; // This works if we use 1'bz, or 1'bx, but not with just 'bz or 'bx. It // does require the tri-state Z. Since we get the same effect if b is // dimensioned [0:0], this may be connected to issue 508. assign b[1:0] = clk ? 2'bx : 'bz; assign c[1:0] = clk ? 2'bz : 'bx; assign d = clk ? 1'bx : 'bz; assign e = clk ? 1'bz : 'bx; endmodule // t verilator-4.038/test_regress/t/t_inst_implicit.v0000664000177100017500000000210213702133370022043 0ustar wsnyderwsnyder// DESCRIPTION:tor:ilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] o; wire [31:0] oe; Test test (/*AUTOINST*/ // Outputs .o (o[31:0]), .oe (oe[31:0])); // Test loop always @ (posedge clk) begin if (o !== 32'h00000001) $stop; if (oe !== 32'h00000001) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module subimp(o,oe); output [31:0] o; assign o = 32'h12345679; output [31:0] oe; assign oe = 32'hab345679; endmodule module Test(o,oe); output [31:0] o; output [31:0] oe; wire [31:0] xe; assign xe[31:1] = 0; // verilator lint_off IMPLICIT // verilator lint_off WIDTH subimp subimp(x, // x is implicit and one bit xe[0]); // xe explicit one bit assign o = x; assign oe = xe; // verilator lint_on WIDTH // verilator lint_on IMPLICIT endmodule verilator-4.038/test_regress/t/t_pli_bad.out0000664000177100017500000000123513702133370021136 0ustar wsnyderwsnyder%Error: t/t_pli_bad.v:10:7: Unsupported or unknown PLI call: '$unknown_pli_task' 10 | $unknown_pli_task; | ^~~~~~~~~~~~~~~~~ %Error: t/t_pli_bad.v:11:7: Unsupported or unknown PLI call: '$unknown_pli_task' 11 | $unknown_pli_task("arg", i); | ^~~~~~~~~~~~~~~~~ %Error: t/t_pli_bad.v:12:11: Unsupported or unknown PLI call: '$unknown_pli_function' 12 | i = $unknown_pli_function; | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_pli_bad.v:13:11: Unsupported or unknown PLI call: '$unknown_pli_function' 13 | i = $unknown_pli_function("arg", i); | ^~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_tri_various.v0000664000177100017500000001111413702133370021545 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [31:0] state; initial state=0; wire A = state[0]; wire OE = state[1]; wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9; wire [3:0] Z10; wire Z11; Test1 test1(/*AUTOINST*/ // Inouts .Z1 (Z1), // Inputs .OE (OE), .A (A)); Test2 test2(/*AUTOINST*/ // Inouts .Z2 (Z2), // Inputs .OE (OE), .A (A)); Test3 test3(/*AUTOINST*/ // Inouts .Z3 (Z3), // Inputs .OE (OE), .A (A)); Test4 test4(/*AUTOINST*/ // Outputs .Z4 (Z4), // Inouts .Z5 (Z5)); Test5 test5(/*AUTOINST*/ // Inouts .Z6 (Z6), .Z7 (Z7), .Z8 (Z8), .Z9 (Z9), // Inputs .OE (OE)); Test6 test6(/*AUTOINST*/ // Inouts .Z10 (Z10[3:0]), // Inputs .OE (OE)); Test7 test7(/*AUTOINST*/ // Outputs .Z11 (Z11), // Inputs .state (state[2:0])); always @(posedge clk) begin state <= state + 1; `ifdef TEST_VERBOSE $write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n", $time, state, Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11); `endif if(state == 0) begin if(Z1 !== 1'b1) $stop; // tests pullups if(Z2 !== 1'b1) $stop; if(Z3 !== 1'b1) $stop; `ifndef VERILATOR if(Z4 !== 1'b1) $stop; `endif if(Z5 !== 1'b1) $stop; if(Z6 !== 1'b1) $stop; if(Z7 !== 1'b0) $stop; if(Z8 !== 1'b0) $stop; if(Z9 !== 1'b1) $stop; if(Z10 !== 4'b0001) $stop; if(Z11 !== 1'b0) $stop; end else if(state == 1) begin if(Z1 !== 1'b1) $stop; // tests pullup if(Z2 !== 1'b1) $stop; if(Z3 !== 1'b1) $stop; `ifndef VERILATOR if(Z4 !== 1'b1) $stop; `endif if(Z5 !== 1'b1) $stop; if(Z6 !== 1'b1) $stop; if(Z7 !== 1'b0) $stop; if(Z8 !== 1'b0) $stop; if(Z9 !== 1'b1) $stop; if(Z10 !== 4'b0001) $stop; if(Z11 !== 1'b1) $stop; end else if(state == 2) begin if(Z1 !== 1'b0) $stop; // tests output driver low if(Z2 !== 1'b0) $stop; if(Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts `ifndef VERILATOR if(Z4 !== 1'b1) $stop; `endif if(Z5 !== 1'b1) $stop; if(Z6 !== 1'b0) $stop; if(Z7 !== 1'b1) $stop; if(Z8 !== 1'b1) $stop; if(Z9 !== 1'b0) $stop; if(Z10 !== 4'b0010) $stop; //if(Z11 !== 1'bx) $stop; // Doesn't matter end else if(state == 3) begin if(Z1 !== 1'b1) $stop; // tests output driver high if(Z2 !== 1'b1) $stop; if(Z3 !== 1'b1) $stop; `ifndef VERILATOR if(Z4 !== 1'b1) $stop; `endif if(Z5 !== 1'b1) $stop; if(Z6 !== 1'b0) $stop; if(Z7 !== 1'b1) $stop; if(Z8 !== 1'b1) $stop; if(Z9 !== 1'b0) $stop; if(Z10 !== 4'b0010) $stop; if(Z11 !== 1'b1) $stop; end else if(state == 4) begin $write("*-* All Finished *-*\n"); $finish; end end pullup(Z1); pullup(Z2); pullup(Z3); pullup(Z4); pullup(Z5); pullup(Z6); pulldown(Z7); pullup(Z8); pulldown(Z9); pulldown pd10[3:0] (Z10); endmodule module Test1(input OE, input A, inout Z1); assign Z1 = (OE) ? A : 1'bz; endmodule module Test2(input OE, input A, inout Z2); assign Z2 = (OE) ? A : 1'bz; endmodule // mixed low-Z and tristate module Test3(input OE, input A, inout Z3); assign Z3 = (OE) ? A : 1'bz; assign Z3 = 1'b1; endmodule // floating output and inout `ifndef VERILATOR // Note verilator doesn't know to make Z4 a tristate unless marked an inout `endif module Test4(output Z4, inout Z5); endmodule // AND gate tristates module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9); assign Z6 = (OE) ? 1'b0 : 1'bz; assign Z7 = (OE) ? 1'b1 : 1'bz; assign Z8 = (OE) ? 1'bz : 1'b0; assign Z9 = (OE) ? 1'bz : 1'b1; endmodule // AND gate tristates module Test6(input OE, inout [3:0] Z10); wire [1:0] i; Test6a a (.OE(OE), .Z({Z10[0],Z10[1]})); Test6a b (.OE(~OE), .Z({Z10[2],Z10[0]})); endmodule module Test6a(input OE, inout [1:0] Z); assign Z = (OE) ? 2'b01 : 2'bzz; endmodule module Test7(input [2:0] state, output reg Z11); always @(*) begin casez (state) 3'b000: Z11 = 1'b0; 3'b0?1: Z11 = 1'b1; default: Z11 = 1'bx; endcase end endmodule // This is not implemented yet //module Test3(input OE, input A, inout Z3); // always @(*) begin // if(OE) begin // Z3 = A; // end else begin // Z3 = 1'bz; // end // end //endmodule verilator-4.038/test_regress/t/t_interface_param2.v0000664000177100017500000000217113702133370022404 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Adrian Wise. // SPDX-License-Identifier: CC0-1.0 //bug1104 module t (input clk); simple_bus sb_intf(clk); simple_bus #(.DWIDTH(16)) wide_intf(clk); mem mem(sb_intf.slave); cpu cpu(sb_intf.master); mem memW(wide_intf.slave); cpu cpuW(wide_intf.master); endmodule interface simple_bus #(AWIDTH = 8, DWIDTH = 8) (input logic clk); // Define the interface logic req, gnt; logic [AWIDTH-1:0] addr; logic [DWIDTH-1:0] data; modport slave( input req, addr, clk, output gnt, input data); modport master(input gnt, clk, output req, addr, output data); initial begin if (DWIDTH != 16) $stop; end endinterface: simple_bus module mem(interface a); logic avail; always @(posedge a.clk) a.gnt <= a.req & avail; initial begin if ($bits(a.data) != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module cpu(interface b); endmodule verilator-4.038/test_regress/t/t_mem_multi_io2.cpp0000664000177100017500000000373113702133370022263 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = NULL; bool pass = true; double sc_time_stamp() { return 0; } void check(const char* bus, int got, int exp) { if (got != exp) { VL_PRINTF("%%Error: Data mismatch on '%s', got=%x, exp=%x\n", bus, got, exp); pass = false; } } #ifdef SYSTEMC_VERSION int sc_main(int, char**) #else int main() #endif { Verilated::debug(0); tb = new VM_PREFIX("tb"); #ifdef SYSTEMC_VERSION sc_signal i3; sc_signal o3; sc_signal i34[4]; sc_signal o34[4]; sc_signal i345[4][5]; sc_signal o345[4][5]; tb->i3(i3); tb->o3(o3); for (int i = 0; i < 4; i++) { tb->i34[i](i34[i]); tb->o34[i](o34[i]); for (int j = 0; j < 5; j++) { tb->i345[i][j](i345[i][j]); tb->o345[i][j](o345[i][j]); } } #endif // loop through every possibility and check the result #ifdef SYSTEMC_VERSION sc_start(1, SC_NS); # define ASSIGN(s,v) s.write(v) # define READ(s) s.read() #else tb->eval(); # define ASSIGN(s,v) tb->s = (v) # define READ(s) tb->s #endif ASSIGN(i3, 13); for (int i = 0; i < 4; i++) { ASSIGN(i34[i], i); for (int j = 0; j < 5; j++) { ASSIGN(i345[i][j], i * 8 + j); } } #ifdef SYSTEMC_VERSION sc_start(1, SC_NS); #else tb->eval(); #endif check("o3", READ(o3), 13); for (int i = 0; i < 4; i++) { check("o34", READ(o34[i]), i); for (int j = 0; j < 5; j++) { check("o345", READ(o345[i][j]), i * 8 + j); } } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from test\n"); } return 0; } verilator-4.038/test_regress/t/t_flag_generate_key.pl0000775000177100017500000000120513702133370023003 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( v_flags2 => ["--generate-key"], expect => qr/VL-KEY/, verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_extends.v0000664000177100017500000000245113702133367022050 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Base0; // No members to check that to_string handles this endclass class Base1 extends Base0; int b1member; typedef int T; endclass class Base2 extends Base1; int b2member; endclass class Cls extends Base2; int imembera; int imemberb; T imemberc; endclass : Cls class uvm_object_wrapper; function int create (); endfunction endclass class uvm__registry #(type T=int) extends uvm_object_wrapper; // This override must be in the new symbol table, not // under the extend's symbol table function int create (); T obj; endfunction endclass module t (/*AUTOARG*/); initial begin Cls c; c = new; c.b1member = 10; c.b2member = 30; c.imembera = 100; c.imemberb = 110; c.imemberc = 120; $display("Display: set = \"%p\"", c); // '{all 4 members} if (c.b1member != 10) $stop; if (c.b2member != 30) $stop; if (c.imembera != 100) $stop; if (c.imemberb != 110) $stop; if (c.imemberc != 120) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_unconnected.pl0000775000177100017500000000105313702133370021656 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_array.pl0000775000177100017500000000125213702133370021646 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--cc --trace --trace-structs'], ); execute( check_finished => 1, ); file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); ok(1); 1; verilator-4.038/test_regress/t/t_case_x_bad.out0000664000177100017500000000067113702133367021625 0ustar wsnyderwsnyder%Warning-CASEX: t/t_case_x_bad.v:14:7: Suggest casez (with ?'s) in place of casex (with X's) 14 | casex (value) | ^~~~~ ... Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message. %Warning-CASEWITHX: t/t_case_x_bad.v:19:9: Use of x/? constant in case statement, (perhaps intended casex/casez) 19 | 4'b1xxx: $stop; | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_alias_unsup.v0000664000177100017500000000264013702133367021534 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Values to swap and locations for the swapped values. wire [31:0] x_fwd = 32'hdeadbeef; wire [31:0] y_fwd; wire [31:0] x_bwd; wire [31:0] y_bwd = 32'hfeedface; swap swap_fwd_i (.a (x_fwd), .b (y_fwd)); swap swap_bwd_i (.a (x_bwd), .b (y_bwd)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write ("x_fwd = %x, y_fwd = %x\n", x_fwd, y_fwd); $write ("x_bwd = %x, y_bwd = %x\n", x_bwd, y_bwd); `endif if (y_fwd != 32'hefbeadde) $stop; if (x_bwd == 32'hcefaedfe) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule // Swap the byte order of two args. module swap ( inout wire [31:0] a, inout wire [31:0] b ); alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b; // Equivalent to // wire [31:0] a_prime; // wire [31:0] b_prime; // assign b_prime = {a[7:0],a[15:8],a[23:16],a[31:24]}; // assign {a_prime[7:0],a_prime[15:8],a_prime[23:16],a_prime[31:24]} = b; // assign b = b_prime; // assign a = a_prime; endmodule verilator-4.038/test_regress/t/t_flag_topmod2_bad.pl0000775000177100017500000000113613702133370022536 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( v_flags2 => ["--top-module a "], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_in_assign_bad.out0000664000177100017500000000053213702133370023173 0ustar wsnyderwsnyder%Error-ASSIGNIN: t/t_var_in_assign_bad.v:12:16: Assigning to input/const variable: 'value' 12 | assign value = 4'h0; | ^~~~~ %Error-ASSIGNIN: t/t_var_in_assign_bad.v:21:16: Assigning to input/const variable: 'valueSub' 21 | assign valueSub = 4'h0; | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_begin2.pl0000775000177100017500000000106413702133370021534 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only --inline-mult 1"], ); ok(1); 1; verilator-4.038/test_regress/t/t_rnd.v0000664000177100017500000000177213702133370017773 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; reg [2:0] a; reg [33:0] wide; reg unused_r; initial _ranit = 0; always @ (posedge clk) begin : blockName begin // Verify begin/begin is legal unused_r <= 1'b1; end begin end // Verify empty is legal end wire one = 1'b1; wire [7:0] rand_bits = 8'b01xx_xx10; always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; // a = 3'b1xx; wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000; if (one !== 1'b1) $stop; if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop; // $write("*-* All Finished *-*\n"); $finish; end end // verilator lint_off UNUSED wire _unused_ok = |{1'b1, wide}; // verilator lint_on UNUSED endmodule verilator-4.038/test_regress/t/t_param_real.v0000664000177100017500000000117013702133370021303 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork // SPDX-License-Identifier: CC0-1.0 module mod #( parameter real HZ = 0 ); //verilator no_inline_module initial begin if ((HZ-$floor(HZ)) - 0.45 > 0.01) $stop; if ((HZ-$floor(HZ)) - 0.45 < -0.01) $stop; end endmodule module t(); mod #(.HZ(123.45)) mod1(); mod #(.HZ(24.45)) mod2(); initial begin if (mod1.HZ != 123.45) $stop; if (mod2.HZ != 24.45) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_pp_defkwd_bad.out0000664000177100017500000000020413702133370022310 0ustar wsnyderwsnyder%Error: t/t_pp_defkwd_bad.v:8:18: Attempting to define built-in directive: '`define' (IEEE 1800-2017 22.5.1) %Error: Exiting due to verilator-4.038/test_regress/t/t_class_class.out0000664000177100017500000000021513702133367022041 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_class.v:12:4: Unsupported: class within class 12 | class SubCls; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_sys_readmem_bad_notfound.pl0000775000177100017500000000114213702133370024402 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_const.v0000664000177100017500000000122613702133367020336 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); initial begin // verilator lint_off WIDTH if (32'hxxxxxxxx !== 'hx) $stop; if (32'hzzzzzzzz !== 'hz) $stop; if (32'h???????? !== 'h?) $stop; if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; if (68'h?_????????_???????? !== 'd?) $stop; // verilator lint_on WIDTH $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_iff.pl0000775000177100017500000000126313702133370020120 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( expect_filename => $Self->{golden_filename}, fails => $Self->{vlt_all}, # Verilator unsupported, bug1482, iff not supported ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_var_const_bad.pl0000775000177100017500000000107413702133370022160 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2005 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_down_inlbc.pl0000775000177100017500000000125513702133370023513 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_B +define+INLINE_C'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_emit_memb_limit.pl0000775000177100017500000000362413702133370022513 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; # Very slow on vltmt, and doesn't test much of value there, so disabled scenarios(vlt => 1); sub gen { my $filename = shift; my $n = shift; my $fh = IO::File->new(">$filename"); $fh->print("// Generated by t_emit_memb_limit.pl\n"); $fh->print("module t (i, clk, o);\n"); $fh->print(" input clk;\n"); $fh->print(" input i;\n"); $fh->print(" output logic o;\n"); for (my $i=0; $i<($n+1); ++$i) { $fh->print(" logic r$i;\n"); } $fh->print(" always @ (posedge clk) begin\n"); $fh->print(" r0 <= i;\n"); for (my $i=1; $i<$n; ++$i) { $fh->print(" r".($i+1)." <= r$i;\n"); } $fh->print(" o <= r$n;\n"); $fh->print(' $write("*-* All Finished *-*\n");',"\n"); $fh->print(' $finish;',"\n"); $fh->print(" end\n"); $fh->print("endmodule\n"); } top_filename("$Self->{obj_dir}/t_emit_memb_limit.v"); # Current limit is 50, so want to test at least 50*50 cases gen($Self->{top_filename}, 6000); compile( verilator_flags2=>["-x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS", # The slow V3Partition asserts are just too slow # in this test. They're disabled just for performance # reasons: "--no-debug-partition"], ); execute( check_finished => 1, ); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/struct \{/); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_var.v0000664000177100017500000000657113702133370020660 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function integer mon_check(); `endif module t (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; reg onebit /*verilator public_flat_rw @(posedge clk) */; reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */; reg [31:0] count /*verilator public_flat_rd */; reg [31:0] half_count /*verilator public_flat_rd */; reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */; reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */; reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */; reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */; reg [511:0] text /*verilator public_flat_rw @(posedge clk) */; integer status; sub sub(); // Test loop initial begin count = 0; onebit = 1'b0; fourthreetwoone[3] = 0; // stop icarus optimizing away text_byte = "B"; text_half = "Hf"; text_word = "Word"; text_long = "Long64b"; text = "Verilog Test module"; `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop; end $write("%%Info: Checking results\n"); if (onebit != 1'b1) $stop; if (quads[2] != 62'h12819213_abd31a1c) $stop; if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; if (text_byte != "A") $stop; if (text_half != "T2") $stop; if (text_word != "Tree") $stop; if (text_long != "44Four44") $stop; if (text != "lorem ipsum") $stop; end always @(posedge clk) begin count <= count + 2; if (count[1]) half_count <= half_count + 2; if (count == 1000) begin $write("*-* All Finished *-*\n"); $finish; end end genvar i; generate for (i=1; i<=128; i=i+1) begin : arr arr #(.LENGTH(i)) arr(); end endgenerate endmodule : t module sub; reg subsig1 /*verilator public_flat_rd*/; reg subsig2 /*verilator public_flat_rd*/; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = subsig1 | subsig2; `endif endmodule : sub module arr; parameter LENGTH = 1; reg [LENGTH-1:0] sig /*verilator public_flat_rw*/; reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/; reg check /*verilator public_flat_rw*/; reg verbose /*verilator public_flat_rw*/; initial begin sig = {LENGTH{1'b0}}; rfr = {LENGTH{1'b0}}; end always @(posedge check) begin if (verbose) $display("%m : %x %x", sig, rfr); if (check && sig != rfr) $stop; check <= 0; end endmodule : arr verilator-4.038/test_regress/t/t_dpi_accessors.v0000664000177100017500000000457613702133370022036 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test for using DPI as general accessors // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // // Contributed by Jeremy Bennett and Jie Xul // // This test exercises the use of DPI to access signals and registers in a // module hierarchy in a uniform fashion. See the discussion at // // https://www.veripool.org/boards/3/topics/show/752-Verilator-Command-line-specification-of-public-access-to-variables // // We need to test read and write access to: // - scalars // - vectors // - array elements // - slices of vectors or array elements // // We need to test that writing to non-writable elements generates an error. // // This Verilog would run forever. It will be stopped externally by the C++ // instantiating program. // Define the width of registers and size of memory we use `define REG_WIDTH 8 `define MEM_SIZE 256 // Top module defines the accessors and instantiates a sub-module with // substantive content. module t (/*AUTOARG*/ // Inputs clk ); input clk; `include "t_dpi_accessors_macros_inc.vh" `include "t_dpi_accessors_inc.vh" // Put the serious stuff in a sub-module, so we can check hierarchical // access works OK. test_sub i_test_sub (.clk (clk)); endmodule // t // A sub-module with all sorts of goodies we would like to access module test_sub (/*AUTOARG*/ // Inputs clk ); input clk; integer i; // General counter // Elements we would like to access from outside reg a; reg [`REG_WIDTH - 1:0] b; reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0]; wire c; wire [`REG_WIDTH - 1:0] d; reg [`REG_WIDTH - 1:0] e; reg [`REG_WIDTH - 1:0] f; // Drive our wires from our registers assign c = ~a; assign d = ~b; // Initial values for registers and array initial begin a = 0; b = `REG_WIDTH'h0; for (i = 0; i < `MEM_SIZE; i++) begin mem[i] = i [`REG_WIDTH - 1:0]; end e = 0; f = 0; end // Wipe out one memory cell in turn on the positive clock edge, restoring // the previous element. We toggle the wipeout value. always @(posedge clk) begin mem[b] <= {`REG_WIDTH {a}}; mem[b - 1] <= b - 1; a <= ~a; b <= b + 1; end endmodule // test_sub verilator-4.038/test_regress/t/t_param_type.v0000664000177100017500000000404513702133370021345 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // counters int cnt; int cnt_bit ; int cnt_byte; int cnt_int ; int cnt_ar1d; int cnt_ar2d; // sizes int siz_bit ; int siz_byte; int siz_int ; int siz_ar1d; int siz_ar2d; // add all counters assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d; // finish report always @ (posedge clk) if (cnt == 5) begin if (siz_bit != 1) $stop(); if (siz_byte != 8) $stop(); if (siz_int != 32) $stop(); if (siz_ar1d != 24) $stop(); if (siz_ar2d != 16) $stop(); end else if (cnt > 5) begin $write("*-* All Finished *-*\n"); $finish; end // instances with various types mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit ); mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte); mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int ); mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d); mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d); // double types mod_typ2 #(.WIDTH1(3), .WIDTH2(3), .TYP1(bit [2:0])) mod2_3_3(); mod_typ2 #(.WIDTH1(3), .WIDTH2(5), .TYP1(bit [2:0]), .TYP2(bit[4:0])) mod2_3_5(); endmodule : t module mod_typ #( parameter type TYP = byte )( input logic clk, output TYP cnt, output int siz ); initial cnt = 0; always @ (posedge clk) cnt <= cnt + 1; assign siz = $bits (cnt); endmodule module mod_typ2 #( parameter int WIDTH1 = 0, parameter int WIDTH2 = WIDTH1, parameter type TYP1 = byte, // Below we need to imply that TYP2 is a type TYP2 = TYP1 )(); TYP1 t1; TYP2 t2; initial begin if ($bits(t1) != WIDTH1) $stop; if ($bits(t2) != WIDTH2) $stop; end endmodule verilator-4.038/test_regress/t/t_trace_scstruct.v0000664000177100017500000000100113702133370022221 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNUSED // verilator lint_off UNDRIVEN //bug858 typedef struct packed { logic m_1; logic m_2; } struct_t; typedef struct packed { logic [94:0] m_1; logic m_2; } struct96_t; module t ( input struct_t test_input, input struct96_t t96 ); endmodule verilator-4.038/test_regress/t/t_interface1_modport.pl0000775000177100017500000000106013702133370023134 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_semaphore.out0000664000177100017500000000020213702133370021520 0ustar wsnyderwsnyder%Error: t/t_semaphore.v:17:4: Can't find typedef: 'semaphore' 17 | semaphore s; | ^~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_clk_latchgate.v0000664000177100017500000001137513702133367022003 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // -------------------------------------------------------- // Bug Description: // // Issue: The gated clock gclk_vld[0] toggles but dvld[0] // input to the flop does not propagate to the output // signal entry_vld[0] correctly. The value that propagates // is the new value of dvld[0] not the one just before the // posedge of gclk_vld[0]. // -------------------------------------------------------- // Define to see the bug with test failing with gated clock 'gclk_vld' // Comment out the define to see the test passing with ungated clock 'clk' `define GATED_CLK_TESTCASE 1 // A side effect of the problem is this warning, disabled by default //verilator lint_on IMPERFECTSCH // Test Bench module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; // Take CRC data and apply to testblock inputs wire [7:0] dvld = crc[7:0]; wire [7:0] ff_en_e1 = crc[15:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] entry_vld; // From test of Test.v wire [7:0] ff_en_vld; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .ff_en_vld (ff_en_vld[7:0]), .entry_vld (entry_vld[7:0]), // Inputs .clk (clk), .dvld (dvld[7:0]), .ff_en_e1 (ff_en_e1[7:0])); reg err_code; reg ffq_clk_active; reg [7:0] prv_dvld; initial begin err_code = 0; ffq_clk_active = 0; end always @ (posedge clk) begin prv_dvld = test.dvld; end always @ (negedge test.ff_entry_dvld_0.clk) begin ffq_clk_active = 1; if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1; end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc); $display(" en=%b fen=%b d=%b ev=%b", test.flop_en_vld[0], test.ff_en_vld[0], test.dvld[0], test.entry_vld[0]); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc<3) begin crc <= 64'h5aef0c8d_d70a4497; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc); if (ffq_clk_active == 0) begin $display ("----"); $display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs"); $display ("----"); $stop; end else if (err_code) begin $display ("----"); $display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs"); $display ("----"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module llq (clk, d, q); parameter WIDTH = 32; input clk; input [WIDTH-1:0] d; output [WIDTH-1:0] q; reg [WIDTH-1:0] qr; /* verilator lint_off COMBDLY */ always @(clk or d) if (clk == 1'b0) qr <= d; /* verilator lint_on COMBDLY */ assign q = qr; endmodule module ffq (clk, d, q); parameter WIDTH = 32; input clk; input [WIDTH-1:0] d; output [WIDTH-1:0] q; reg [WIDTH-1:0] qr; always @(posedge clk) qr <= d; assign q = qr; endmodule // DUT module module Test (/*AUTOARG*/ // Outputs ff_en_vld, entry_vld, // Inputs clk, dvld, ff_en_e1 ); input clk; input [7:0] dvld; input [7:0] ff_en_e1; output [7:0] ff_en_vld; output wire [7:0] entry_vld; wire [7:0] gclk_vld; wire [7:0] ff_en_vld /*verilator clock_enable*/; reg [7:0] flop_en_vld; always @(posedge clk) flop_en_vld <= ff_en_e1; // clock gating `ifdef GATED_CLK_TESTCASE assign gclk_vld = {8{clk}} & ff_en_vld; `else assign gclk_vld = {8{clk}}; `endif // latch for avoiding glitch on the clock gating control llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld)); // flops that use the gated clock signal ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0])); ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1])); ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2])); ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3])); ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4])); ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5])); ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6])); ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7])); endmodule verilator-4.038/test_regress/t/t_param_real2_collision.pl0000775000177100017500000000117413702133370023615 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_param_real2.v"); compile( verilator_flags2 => ["--debug-collision"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_writemem_b.gold4.mem0000664000177100017500000000602013702133370023550 0ustar wsnyderwsnyder000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 011101110101010101000000000001000011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 011101110101010101000000000010100011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010001 011101110101010101000000000010110011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010010 011101110101010101000000000011000011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010011 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 verilator-4.038/test_regress/t/t_class_package.pl0000775000177100017500000000105313702133367022137 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_genvar_for_bad.v0000664000177100017500000000107513702133370022142 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs ov, // Inputs clk, iv ); parameter N = 4; input clk; input [63:0] iv[N-1:0]; output logic [63:0] ov[N-1:0]; genvar i; generate always @(posedge clk) begin for (i=0; i 1); top_filename("t/t_split_var_0.v"); # Travis environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performace wise, but ok. compile( verilator_flags2 => ['--cc --trace --stats' . ($Self->{vltmt} ? ' --threads 6' : ''), '+define+TEST_ATTRIBUTES'], ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 12); file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 23); ok(1); 1; verilator-4.038/test_regress/t/t_trace_public_sig_vlt.pl0000775000177100017500000000231713702133370023540 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_trace_public.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( make_top_shell => 0, make_main => 0, v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_public_sig.cpp $Self->{t_dir}/t_trace_public_sig.vlt"], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", "t/t_trace_public.out"); # vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" file_grep("$Self->{obj_dir}/simx.vcd", qr/module glbl/i); ok(1); 1; verilator-4.038/test_regress/t/t_var_nonamebegin__log.out0000664000177100017500000000047713702133370023705 0ustar wsnyderwsnyderingen: {mod}.genblk1 top.t.genblk1 d3a: {mod}.d3nameda top.t.unnamedblk1.d3nameda b2: {mod} top.t.unnamedblk2 b3n: {mod}.b3named: top.t.unnamedblk2.b3named b3: {mod} top.t.unnamedblk2.unnamedblk3 b4: {mod} top.t.unnamedblk2.unnamedblk3.unnamedblk4 t1 {mod}.tsk top.t t2 {mod}.tsk top.t.unnamedblk7 *-* All Finished *-* verilator-4.038/test_regress/t/t_inst_prepost.v0000664000177100017500000000111113702133370021724 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub #(10,11,12,13) sub (); endmodule module sub (); parameter A = 0; parameter B = 1; ip ip(); parameter C = 2; parameter D = 3; initial begin if (A!=10) $stop; if (B!=11) $stop; if (C!=12) $stop; if (D!=13) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module ip; endmodule verilator-4.038/test_regress/t/t_sys_file_autoflush.pl0000775000177100017500000000131113702133370023255 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_sys_file_basic.v"); compile( v_flags2 => ['+incdir+../include', '+define+AUTOFLUSH'], verilator_flags2 => ['--autoflush'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_dup_bad.out0000664000177100017500000000040213702133367022524 0ustar wsnyderwsnyder%Error: t/t_assert_dup_bad.v:17:4: Duplicate declaration of block: 'covlabel' 17 | covlabel: | ^~~~~~~~ t/t_assert_dup_bad.v:15:4: ... Location of original declaration 15 | covlabel: | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_complex_structs.out0000664000177100017500000001221713702133370024162 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Tue Jan 21 18:55:13 2020 $end $timescale 1ps $end $scope module top $end $var wire 1 9# clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module t $end $var wire 1 9# clk $end $var wire 32 + cyc [31:0] $end $var wire 8 r# unpacked_array(-1) [7:0] $end $var wire 8 q# unpacked_array(-2) [7:0] $end $var wire 8 s# unpacked_array(0) [7:0] $end $var real 64 ?" v_arr_real(0) $end $var real 64 A" v_arr_real(1) $end $var wire 2 %! v_arrp [2:1] $end $var wire 2 -! v_arrp_arrp(3) [2:1] $end $var wire 2 5! v_arrp_arrp(4) [2:1] $end $var wire 1 A# v_arru(1) $end $var wire 1 B# v_arru(2) $end $var wire 2 ]! v_arru_arrp(3) [2:1] $end $var wire 2 ^! v_arru_arrp(4) [2:1] $end $var wire 1 Q# v_arru_arru(3)(1) $end $var wire 1 Y# v_arru_arru(3)(2) $end $var wire 1 a# v_arru_arru(4)(1) $end $var wire 1 i# v_arru_arru(4)(2) $end $var wire 3 o" v_enumb [2:0] $end $var wire 32 _" v_enumed [31:0] $end $var wire 32 g" v_enumed2 [31:0] $end $var real 64 /" v_real $end $scope module unnamedblk1 $end $var wire 32 )# b [31:0] $end $scope module unnamedblk2 $end $var wire 32 1# a [31:0] $end $upscope $end $upscope $end $scope module v_arrp_strp(3) $end $var wire 1 E! b0 $end $var wire 1 =! b1 $end $upscope $end $scope module v_arrp_strp(4) $end $var wire 1 U! b0 $end $var wire 1 M! b1 $end $upscope $end $scope module v_arru_strp(3) $end $var wire 1 u! b0 $end $var wire 1 m! b1 $end $upscope $end $scope module v_arru_strp(4) $end $var wire 1 '" b0 $end $var wire 1 }! b1 $end $upscope $end $scope module v_enumb2_str $end $var wire 3 w" a [2:0] $end $var wire 3 !# b [2:0] $end $upscope $end $scope module v_str32x2(0) $end $var wire 32 3 data [31:0] $end $upscope $end $scope module v_str32x2(1) $end $var wire 32 ; data [31:0] $end $upscope $end $scope module v_strp $end $var wire 1 K b0 $end $var wire 1 C b1 $end $upscope $end $scope module v_strp_strp $end $scope module x0 $end $var wire 1 k b0 $end $var wire 1 c b1 $end $upscope $end $scope module x1 $end $var wire 1 [ b0 $end $var wire 1 S b1 $end $upscope $end $upscope $end $scope module v_unip_strp $end $scope module x0 $end $var wire 1 { b0 $end $var wire 1 s b1 $end $upscope $end $scope module x1 $end $var wire 1 { b0 $end $var wire 1 s b1 $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 + b00000000000000000000000011111111 3 b00000000000000000000000000000000 ; 0C 0K 0S 0[ 0c 0k 0s 0{ b00 %! b00 -! b00 5! 0=! 0E! 0M! 0U! b00 ]! b00 ^! 0m! 0u! 0}! 0'" r0 /" r0 ?" r0 A" b00000000000000000000000000000000 _" b00000000000000000000000000000000 g" b000 o" b000 w" b000 !# b00000000000000000000000000000000 )# b00000000000000000000000000000000 1# 09# 0A# 0B# 0Q# 0Y# 0a# 0i# b00000000 q# b00000000 r# b00000000 s# #10 b00000000000000000000000000000001 + b00000000000000000000000011111110 3 b00000000000000000000000000000001 ; 1C 1K 1S 1[ 1c 1k 1s 1{ b11 %! b11 -! b11 5! 1=! 1E! 1M! 1U! b11 ]! b11 ^! 1m! 1u! 1}! 1'" r0.1 /" r0.2 ?" r0.3 A" b00000000000000000000000000000001 _" b00000000000000000000000000000010 g" b111 o" b00000000000000000000000000000101 )# b00000000000000000000000000000101 1# 19# #15 09# #20 b00000000000000000000000000000010 + b00000000000000000000000011111101 3 b00000000000000000000000000000010 ; 0C 0K 0S 0[ 0c 0k 0s 0{ b00 %! b00 -! b00 5! 0=! 0E! 0M! 0U! b00 ]! b00 ^! 0m! 0u! 0}! 0'" r0.2 /" r0.4 ?" r0.6 A" b00000000000000000000000000000010 _" b00000000000000000000000000000100 g" b110 o" b111 w" b111 !# 19# #25 09# #30 b00000000000000000000000000000011 + b00000000000000000000000011111100 3 b00000000000000000000000000000011 ; 1C 1K 1S 1[ 1c 1k 1s 1{ b11 %! b11 -! b11 5! 1=! 1E! 1M! 1U! b11 ]! b11 ^! 1m! 1u! 1}! 1'" r0.3 /" r0.6000000000000001 ?" r0.8999999999999999 A" b00000000000000000000000000000011 _" b00000000000000000000000000000110 g" b101 o" b110 w" b110 !# 19# #35 09# #40 b00000000000000000000000000000100 + b00000000000000000000000011111011 3 b00000000000000000000000000000100 ; 0C 0K 0S 0[ 0c 0k 0s 0{ b00 %! b00 -! b00 5! 0=! 0E! 0M! 0U! b00 ]! b00 ^! 0m! 0u! 0}! 0'" r0.4 /" r0.8 ?" r1.2 A" b00000000000000000000000000000100 _" b00000000000000000000000000001000 g" b100 o" b101 w" b101 !# 19# #45 09# #50 b00000000000000000000000000000101 + b00000000000000000000000011111010 3 b00000000000000000000000000000101 ; 1C 1K 1S 1[ 1c 1k 1s 1{ b11 %! b11 -! b11 5! 1=! 1E! 1M! 1U! b11 ]! b11 ^! 1m! 1u! 1}! 1'" r0.5 /" r1 ?" r1.5 A" b00000000000000000000000000000101 _" b00000000000000000000000000001010 g" b011 o" b100 w" b100 !# 19# #55 09# #60 b00000000000000000000000000000110 + b00000000000000000000000011111001 3 b00000000000000000000000000000110 ; 0C 0K 0S 0[ 0c 0k 0s 0{ b00 %! b00 -! b00 5! 0=! 0E! 0M! 0U! b00 ]! b00 ^! 0m! 0u! 0}! 0'" r0.6 /" r1.2 ?" r1.8 A" b00000000000000000000000000000110 _" b00000000000000000000000000001100 g" b010 o" b011 w" b011 !# 19# verilator-4.038/test_regress/t/t_fuzz_triand_bad.v0000664000177100017500000000037713702133370022355 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); tri g=g.and.g; endmodule verilator-4.038/test_regress/t/t_flag_debugi9.v0000664000177100017500000000073113702133370021523 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, // Inputs i ); // Need some logic to get mtask debug fully covered input i; output wire o; assign o = i; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_bind_public.v0000664000177100017500000000572013702133370023477 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Alex Solomatnikov. // SPDX-License-Identifier: CC0-1.0 interface hex2ram_if ( input bit trigger ); string instance_path = $sformatf("%m"); string testfile = ""; bit has_testfile = |($value$plusargs("testfile=%s", testfile)); bit armed = 1'b1; bit armed_trigger; initial begin $display("successfully bound hex2ram_if to %s", instance_path); armed = has_testfile && 1'b1; end assign armed_trigger = armed && trigger; always @(posedge armed_trigger) begin $display("%m(%0t): saw deassertion of reset", $time); end endinterface : hex2ram_if module t ( clk ); input clk /*verilator clocker*/; bit reset; wire success; SimpleTestHarness testHarness ( .clk(clk), .reset(reset), .io_success(success) ); integer cyc=0; always @ (posedge clk) begin cyc = cyc + 1; if (cyc<10) begin reset <= '0; end else if (cyc<20) begin reset <= '1; end else if (cyc<30) begin reset <= '0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule bind testharness_ext hex2ram_if i_hex2ram (.trigger(!t.reset)); module testharness_ext ( input W0_clk, input [24:0] W0_addr, input W0_en, input [127:0] W0_data, input [0:0] W0_mask, input R0_clk, input [24:0] R0_addr, input R0_en, output [127:0] R0_data ); reg [24:0] reg_R0_addr; wire [127:0] R0_rdata_mask; reg [127:0] ram [33554431:0]; wire [127:0] W0_wdata_mask; always @(posedge R0_clk) if (R0_en) reg_R0_addr <= R0_addr; always @(posedge W0_clk) if (W0_en) begin if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask; end assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask;; assign R0_rdata_mask = 0; assign W0_wdata_mask = 0; endmodule module SimpleTestHarness ( input clk, input reset, output io_success); wire [24:0] testharness_ext_R0_addr; wire testharness_ext_R0_en; wire testharness_ext_R0_clk; wire [127:0] testharness_ext_R0_data; wire [24:0] testharness_ext_W0_addr; wire testharness_ext_W0_en; wire testharness_ext_W0_clk; wire [127:0] testharness_ext_W0_data; wire [0:0] testharness_ext_W0_mask; testharness_ext testharness_ext ( .R0_addr(testharness_ext_R0_addr), .R0_en(testharness_ext_R0_en), .R0_clk(testharness_ext_R0_clk), .R0_data(testharness_ext_R0_data), .W0_addr(testharness_ext_W0_addr), .W0_en(testharness_ext_W0_en), .W0_clk(testharness_ext_W0_clk), .W0_data(testharness_ext_W0_data), .W0_mask(testharness_ext_W0_mask) ); endmodule verilator-4.038/test_regress/t/t_enum_func.v0000664000177100017500000000244013702133370021160 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum { EN_ZERO, EN_ONE } En_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; // Insure that we can declare a type with a function declaration function enum integer { EF_TRUE = 1, EF_FALSE = 0 } f_enum_inv ( input a); f_enum_inv = a ? EF_FALSE : EF_TRUE; endfunction initial begin if (f_enum_inv(1) != 0) $stop; if (f_enum_inv(0) != 1) $stop; end En_t a, z; sub sub (/*AUTOINST*/ // Outputs .z (z), // Inputs .a (a)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= EN_ZERO; end if (cyc==2) begin a <= EN_ONE; if (z != EN_ONE) $stop; end if (cyc==3) begin if (z != EN_ZERO) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module sub (input En_t a, output En_t z); always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE; endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-4.038/test_regress/t/t_class1.pl0000775000177100017500000000113413702133367020545 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_packed.pl0000775000177100017500000000105313702133370021436 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_order.v0000664000177100017500000000574413702133370020326 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // surefire lint_off ASWEBB // surefire lint_off ASWEMB // surefire lint_off STMINI // surefire lint_off CSEBEQ input clk; reg [7:0] a_to_clk_levm3; reg [7:0] b_to_clk_levm1; reg [7:0] c_com_levs10; reg [7:0] d_to_clk_levm2; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v wire [7:0] n_from_clk_lev2; // From a of t_order_a.v wire [7:0] o_from_com_levs11; // From a of t_order_a.v wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v // End of automatics reg [7:0] cyc; initial cyc=0; t_order_a a ( .one (8'h1), /*AUTOINST*/ // Outputs .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]), .n_from_clk_lev2 (n_from_clk_lev2[7:0]), .o_from_com_levs11 (o_from_com_levs11[7:0]), .o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]), // Inputs .clk (clk), .a_to_clk_levm3 (a_to_clk_levm3[7:0]), .b_to_clk_levm1 (b_to_clk_levm1[7:0]), .c_com_levs10 (c_com_levs10[7:0]), .d_to_clk_levm2 (d_to_clk_levm2[7:0])); t_order_b b ( /*AUTOINST*/ // Outputs .o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]), // Inputs .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0])); reg [7:0] o_from_com_levs12; reg [7:0] o_from_com_levs13; always @ (/*AS*/o_from_com_levs11) begin o_from_com_levs12 = o_from_com_levs11 + 8'h1; o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize o_from_com_levs13 = o_from_com_levs12; end reg sepassign_in; // verilator lint_off UNOPTFLAT wire [3:0] sepassign; // verilator lint_on UNOPTFLAT // verilator lint_off UNOPT assign #0.1 sepassign[0] = 0, sepassign[1] = sepassign[2], sepassign[2] = sepassign[3], sepassign[3] = sepassign_in; wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2; // verilator lint_on UNOPT always @ (posedge clk) begin cyc <= cyc+8'd1; sepassign_in <= 0; if (cyc == 8'd1) begin a_to_clk_levm3 <= 0; d_to_clk_levm2 <= 1; b_to_clk_levm1 <= 1; c_com_levs10 <= 2; sepassign_in <= 1; end if (cyc == 8'd2) begin if (sepassign !== 4'b1110) $stop; end if (cyc == 8'd3) begin $display("%d %d %d %d",m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12); if (m_from_clk_lev1_r !== 8'h2) $stop; if (o_subfrom_clk_lev3 !== 8'h2) $stop; if (n_from_clk_lev2 !== 8'h2) $stop; if (o_from_com_levs11 !== 8'h3) $stop; if (o_from_com_levs13 !== 8'h5) $stop; if (o_from_comandclk_levs12 !== 8'h5) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_interface1_modport_trace.pl0000775000177100017500000000120013702133370024306 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface1_modport.v"); compile( verilator_flags2 => ['--trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_fi.pl0000775000177100017500000000130313702133370020736 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["-FI $Self->{t_dir}/t_flag_fi_h.h", "--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_dump_cc.pl0000775000177100017500000000220613702133370023033 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); top_filename("t_trace_two_a.v"); compile( make_main => 0, verilator_make_gmake => 0, top_filename => 't_trace_two_b.v', VM_PREFIX => 'Vt_trace_two_b', verilator_flags2 => ['-trace'], ); compile( make_main => 0, top_filename => 't_trace_two_a.v', verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"], v_flags2 => ['+define+TEST_DUMP'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } ok(1); 1; verilator-4.038/test_regress/t/t_interface_array_nocolon_bad.pl0000775000177100017500000000111313702133370025041 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_local.v0000664000177100017500000000125213702133370021124 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; localparam N = 31; wire [31:0] vec; generate genvar g; // bug461 begin : topgen for (g=0; g 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_event_copy.pl0000775000177100017500000000117613702133370021532 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_multi_io3_cc.pl0000775000177100017500000000127513702133370022566 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_mem_multi_io3.v"); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io3.cpp -Oi"], verilator_flags3 => [], ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_dpulse.pl0000775000177100017500000000105313702133367021504 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_plog.v0000664000177100017500000000454613702133370021166 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; reg rst_n; // Take CRC data and apply to testblock inputs /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [2:0] pos1; // From test of Test.v wire [2:0] pos2; // From test of Test.v // End of automatics Test test ( // Outputs .pos1 (pos1[2:0]), .pos2 (pos2[2:0]), /*AUTOINST*/ // Inputs .clk (clk), .rst_n (rst_n)); // Aggregate outputs into a single result vector wire [63:0] result = {61'h0, pos1}; // What checksum will we end up with `define EXPECTED_SUM 64'h039ea4d039c2e70b // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; rst_n <= ~1'b0; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; rst_n <= ~1'b1; end else if (cyc<10) begin sum <= 64'h0; rst_n <= ~1'b1; end else if (cyc<90) begin if (pos1 !== pos2) $stop; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test #(parameter SAMPLE_WIDTH = 5 ) ( `ifdef verilator // Some simulators don't support clog2 output reg [$clog2(SAMPLE_WIDTH)-1:0] pos1, `else output reg [log2(SAMPLE_WIDTH-1)-1:0] pos1, `endif output reg [log2(SAMPLE_WIDTH-1)-1:0] pos2, // System input clk, input rst_n ); function integer log2(input integer arg); begin for(log2=0; arg>0; log2=log2+1) arg = (arg >> 1); end endfunction always @ (posedge clk or negedge rst_n) if (!rst_n) begin pos1 <= 0; pos2 <= 0; end else begin pos1 <= pos1 + 1; pos2 <= pos2 + 1; end endmodule verilator-4.038/test_regress/t/t_class_extern.v0000664000177100017500000000070313702133367021701 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; extern function void extfunc(); endclass function void Cls::extfunc(); $write("*-* All Finished *-*\n"); $finish; endfunction module t (/*AUTOARG*/); initial begin Cls c; c.extfunc(); end endmodule verilator-4.038/test_regress/t/t_langext_1_bad.pl0000775000177100017500000000115713702133370022046 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_langext_1.v"); # This is a lint only test. lint( v_flags2 => ["+verilog1995ext+v"], fails => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_uselib.v0000664000177100017500000000071513702133370021326 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); // // `uselib {dir= | file= | libext= | lib= `uselib libext=.v s s (); endmodule module s; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_size_bad.v0000664000177100017500000000074213702133370023004 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Demonstrate deferred linking error messages // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; endinterface module t (/*AUTOARG*/); localparam N = 4; foo_intf foo4 [N-1:0] (); foo_intf foo6 [5:0] (); baz baz4_inst (.foo(foo4)); baz baz6_inst (.foo(foo6)); endmodule module baz(foo_intf foo[4:0] ); endmodule verilator-4.038/test_regress/t/t_flag_lib.pl0000775000177100017500000000112213702133370021105 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( v_flags2 => ['-v', 't/t_flag_libinc.v'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_bad_notfound.v0000664000177100017500000000062013702133370024231 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; initial begin $readmemh("t/t_sys_readmem_bad_NOTFOUND.mem", hex); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_assoc.pl0000775000177100017500000000105313702133367020467 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_threads_counter_2.pl0000775000177100017500000000120213702133370022757 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); top_filename("t/t_threads_counter.v"); compile( verilator_flags2 => ['--cc --threads 2'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlcov_rank.pl0000775000177100017500000000155313702133370021522 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); run(cmd => ["../bin/verilator_coverage", "--rank", "t/t_vlcov_data_a.dat", "t/t_vlcov_data_b.dat", "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat", ], logfile => "$Self->{obj_dir}/vlcov.log", tee => 0, verilator_run => 1, ); files_identical("$Self->{obj_dir}/vlcov.log", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem.pl0000775000177100017500000000105313702133370021661 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_litendian.pl0000775000177100017500000000177113702133370022505 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Travis environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. compile( verilator_flags2 => ['--cc --trace --trace-params -Wno-LITENDIAN', ($Self->{vltmt} ? '--threads 6' : '')], ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_case_x_bad.pl0000775000177100017500000000110113702133367021421 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_threads_collide.pl0000775000177100017500000000162013702133370023332 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2018 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->skip_if_too_few_cores(); scenarios(vltmt => 1); top_filename("t/t_dpi_threads.v"); compile( v_flags2 => ["t/t_dpi_threads_c.cpp --threads-dpi all --no-threads-coarsen"], ); # Similar to t_dpi_threads, which confirms that Verilator can prevent a # race between DPI import calls, this test confirms that the race exists # and that the DPI C code can detect it under --threads-dpi all # mode. # execute( fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_default_bad.pl0000775000177100017500000000107413702133370022766 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_tri.pl0000775000177100017500000000105313702133370021160 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_lib_c.cpp0000664000177100017500000001057713702133370021434 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_lib__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern int dpii_failure(); extern void dpii_check(); } #endif //====================================================================== int failure = 0; int dpii_failure() { return failure; } #define CHECK_RESULT_HEX(got, exp) \ do { \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << std::hex \ << ": GOT=" << (got) << " EXP=" << (exp) << std::endl; \ failure = __LINE__; \ } \ } while (0) //====================================================================== void dpii_lib_bit_check() { svBitVecVal bv[3]; bv[0] = 0xa3a2a1a0; // 31..0 bv[1] = 0xa7a6a5a4; // 63..32 bv[2] = 0xabaaa9a8; // 95..64 CHECK_RESULT_HEX((int)svGetBitselBit(bv, 32), 0); CHECK_RESULT_HEX((int)svGetBitselBit(bv, 33), 0); CHECK_RESULT_HEX((int)svGetBitselBit(bv, 34), 1); CHECK_RESULT_HEX((int)svGetBitselBit(bv, 35), 0); CHECK_RESULT_HEX((int)svGetBitselBit(bv, 36), 0); CHECK_RESULT_HEX((int)svGetBitselBit(bv, 37), 1); CHECK_RESULT_HEX((int)svGetBitselBit(bv, 38), 0); CHECK_RESULT_HEX((int)svGetBitselBit(bv, 39), 1); svPutBitselBit(bv, 32, 1); svPutBitselBit(bv, 33, 0); svPutBitselBit(bv, 34, 1); svPutBitselBit(bv, 35, 1); CHECK_RESULT_HEX(bv[0], 0xa3a2a1a0); CHECK_RESULT_HEX(bv[1], 0xa7a6a5ad); CHECK_RESULT_HEX(bv[2], 0xabaaa9a8); svBitVecVal btmp[1]; svGetPartselBit(btmp, bv, 40, 8); CHECK_RESULT_HEX(btmp[0], 0xa5); svPutPartselBit(bv, btmp[0], 48, 8); CHECK_RESULT_HEX(bv[0], 0xa3a2a1a0); CHECK_RESULT_HEX(bv[1], 0xa7a5a5ad); CHECK_RESULT_HEX(bv[2], 0xabaaa9a8); } void dpii_lib_logic_check() { svLogicVecVal lv[3]; lv[0].aval = 0xb3b2b1b0; // 31..0 lv[1].aval = 0xb7b6b5b4; // 63..32 lv[2].aval = 0xbbbab9b8; // 95..64 lv[0].bval = 0xc3c2c1c0; // 31..0 lv[1].bval = 0xc7c6c5c4; // 63..32 lv[2].bval = 0xcbcac9c8; // 95..64 CHECK_RESULT_HEX((int)svGetBitselLogic(lv, 32), 0); CHECK_RESULT_HEX((int)svGetBitselLogic(lv, 33), 0); CHECK_RESULT_HEX((int)svGetBitselLogic(lv, 34), 3); CHECK_RESULT_HEX((int)svGetBitselLogic(lv, 35), 0); CHECK_RESULT_HEX((int)svGetBitselLogic(lv, 36), 1); CHECK_RESULT_HEX((int)svGetBitselLogic(lv, 37), 1); CHECK_RESULT_HEX((int)svGetBitselLogic(lv, 38), 2); CHECK_RESULT_HEX((int)svGetBitselLogic(lv, 39), 3); svPutBitselLogic(lv, 32, 1); svPutBitselLogic(lv, 33, 0); svPutBitselLogic(lv, 34, 1); svPutBitselLogic(lv, 35, 3); CHECK_RESULT_HEX(lv[0].aval, 0xb3b2b1b0); CHECK_RESULT_HEX(lv[1].aval, 0xb7b6b5bd); CHECK_RESULT_HEX(lv[2].aval, 0xbbbab9b8); CHECK_RESULT_HEX(lv[0].bval, 0xc3c2c1c0); CHECK_RESULT_HEX(lv[1].bval, 0xc7c6c5c8); CHECK_RESULT_HEX(lv[2].bval, 0xcbcac9c8); svLogicVecVal ltmp[1]; svGetPartselLogic(ltmp, lv, 40, 8); CHECK_RESULT_HEX(ltmp[0].aval, 0xb5); CHECK_RESULT_HEX(ltmp[0].bval, 0xc5); svPutPartselLogic(lv, ltmp[0], 48, 8); CHECK_RESULT_HEX(lv[0].aval, 0xb3b2b1b0); CHECK_RESULT_HEX(lv[1].aval, 0xb7b5b5bd); CHECK_RESULT_HEX(lv[2].aval, 0xbbbab9b8); CHECK_RESULT_HEX(lv[0].bval, 0xc3c2c1c0); CHECK_RESULT_HEX(lv[1].bval, 0xc7c5c5c8); CHECK_RESULT_HEX(lv[2].bval, 0xcbcac9c8); } //====================================================================== void dpii_check() { dpii_lib_bit_check(); dpii_lib_logic_check(); } verilator-4.038/test_regress/t/t_inst_notunsized.pl0000775000177100017500000000112413702133370022607 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2=>["-Wno-IMPLICIT"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_bad_sv.v0000664000177100017500000000041413702133370021306 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg do; mod mod (.do(bar)); endmodule verilator-4.038/test_regress/t/t_math_precedence.v0000664000177100017500000001067213702133370022315 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; wire [1:0] a = crc[1 +: 2]; wire [1:0] b = crc[3 +: 2]; wire [1:0] c = crc[5 +: 2]; wire [1:0] d = crc[7 +: 2]; wire [1:0] e = crc[9 +: 2]; wire [1:0] f = crc[11+: 2]; wire [1:0] g = crc[13+: 2]; // left () [] :: . // unary + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary) // left ** // left * / % // left + - (binary) // left << >> <<< >>> // left < <= > >= inside dist // left == != === !== ==? !=? // left & (binary) // left ^ ~^ ^~ (binary) // left | (binary) // left && // left || // left ? : // right -> // none = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <= // {} {{}} concatenation wire [1:0] bnz = (b==2'b0) ? 2'b11 : b; wire [1:0] cnz = (c==2'b0) ? 2'b11 : c; wire [1:0] dnz = (d==2'b0) ? 2'b11 : d; wire [1:0] enz = (e==2'b0) ? 2'b11 : e; // verilator lint_off WIDTH // Do a few in each group wire [1:0] o1 = ~ a; // Can't get more than one reduction to parse wire [1:0] o2 = ^ b; // Can't get more than one reduction to parse wire [1:0] o3 = a ** b ** c; // Some simulators botch this wire [1:0] o4 = a * b / cnz % dnz * enz; wire [1:0] o5 = a + b - c + d; wire [1:0] o6 = a << b >> c <<< d >>> e <<< f; wire [1:0] o7 = a < b <= c; wire [1:0] o8 = a == b != c === d == e; wire [1:0] o9 = a & b & c; wire [1:0] o10 = a ^ b ~^ c ^~ d ^ a; wire [1:0] o11 = a | b | c; wire [1:0] o12 = a && b && c; wire [1:0] o13 = a || b || c; wire [1:0] o14 = a ? b ? c : d : e; wire [1:0] o15 = a ? b : c ? d : e; // Now cross each pair of groups wire [1:0] x1 = ~ a ** ~ b ** ~c; // Some simulators botch this wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this wire [1:0] x3 = a + b * c + d; wire [1:0] x4 = a + b << c + d; wire [1:0] x5 = a == b << c == d; wire [1:0] x6 = a & b << c & d; wire [1:0] x7 = a ^ b & c ^ d; wire [1:0] x8 = a | b ^ c | d; wire [1:0] x9 = a && b | c && d; wire [1:0] x10 = a || b && c || d; wire [1:0] x11 = a ? b || c : d ? e : f; // verilator lint_on WIDTH function [1:0] pow (input [1:0] x, input [1:0] y); casez ({x,y}) 4'b00_??: pow = 2'b00; 4'b01_00: pow = 2'b01; 4'b01_01: pow = 2'b01; 4'b01_10: pow = 2'b01; 4'b01_11: pow = 2'b01; 4'b10_00: pow = 2'b01; 4'b10_01: pow = 2'b10; 4'b10_10: pow = 2'b00; 4'b10_11: pow = 2'b00; 4'b11_00: pow = 2'b01; 4'b11_01: pow = 2'b11; 4'b11_10: pow = 2'b01; 4'b11_11: pow = 2'b11; endcase endfunction // Aggregate outputs into a single result vector wire [63:0] result = {12'h0, x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1, o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x ",$time, cyc, crc, result); $write(" %b",o1); $write(" %b",o2); $write(" %b",o3); $write(" %b",o4); $write(" %b",o5); $write(" %b",o6); $write(" %b",o7); $write(" %b",o8); $write(" %b",o9); $write(" %b",o10); $write(" %b",o11); $write(" %b",o12); $write(" %b",o13); $write(" %b",o14); $write(" %b",o15); // Now cross each pair of groups $write(" %b",x1); $write(" %b",x2); $write(" %b",x3); $write(" %b",x4); $write(" %b",x5); $write(" %b",x6); $write(" %b",x7); $write(" %b",x8); $write(" %b",x9); $write(" %b",x10); $write(" %b",x11); $write("\n"); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h2756ea365ec7520e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_var_const.pl0000775000177100017500000000105313702133370021347 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_2in_vec.pl0000775000177100017500000000134513702133367021541 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_clk_2in.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["+define+T_CLK_2IN_VEC=1"], verilator_flags2 => ["--exe $Self->{t_dir}/t_clk_2in.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_uselib.pl0000775000177100017500000000100113702133370021464 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_func_bad.pl0000775000177100017500000000107413702133370021115 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_semaphore.pl0000775000177100017500000000117613702133370021342 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_gate_delref.v0000664000177100017500000000223413702133370021443 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug1475 module t (/*AUTOARG*/ // Outputs ID_45, IDa_f4c, // Inputs clk, ID_d9f, IDa_657, ID_477 ); input clk; output reg ID_45; input ID_d9f; input IDa_657; output reg IDa_f4c; reg ID_13; input ID_477; reg ID_489; reg ID_8d1; reg IDa_183; reg IDa_91c; reg IDa_a96; reg IDa_d6b; reg IDa_eb9; wire ID_fc8 = ID_d9f & ID_13; //<< wire ID_254 = ID_d9f & ID_13; wire ID_f40 = ID_fc8 ? ID_8d1 : 0; wire ID_f4c = ID_fc8 ? 0 : ID_477; wire ID_442 = IDa_91c; wire ID_825 = ID_489; always @(posedge clk) begin ID_13 <= ID_f40; ID_8d1 <= IDa_eb9; ID_489 <= ID_442; ID_45 <= ID_825; IDa_d6b <= IDa_a96; IDa_f4c <= ID_f4c; if (ID_254) begin IDa_91c <= IDa_d6b; IDa_183 <= IDa_657; IDa_a96 <= IDa_657; IDa_eb9 <= IDa_183; end end endmodule verilator-4.038/test_regress/t/t_interface_typo_bad.out0000664000177100017500000000070713702133370023370 0ustar wsnyderwsnyder%Error: t/t_interface_typo_bad.v:14:4: Parent cell's interface is not found: 'foo_intf' 14 | foo_intf foo | ^~~~~~~~ %Error: t/t_interface_typo_bad.v:22:4: Cannot find file containing interface: 'fo_intf' 22 | fo_intf the_foo; | ^~~~~~~ %Error: t/t_interface_typo_bad.v:27:15: Found definition of 'the_foo' as a CELL but expected a variable 27 | .foo (the_foo) | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_select_little.pl0000775000177100017500000000105313702133370022205 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_notfound_bad.out0000664000177100017500000000033313702133370023610 0ustar wsnyderwsnyder%Error: t/t_struct_notfound_bad.v:13:9: Member 'nfmember' not found in structure : ... In instance t 13 | s.nfmember = 0; | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_complex_threads_1.pl0000775000177100017500000000250313702133370024131 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_complex.v"); $Self->{golden_filename} = "t/t_trace_complex.out"; compile( verilator_flags2 => ['--cc --trace --trace-threads 1'] ); execute( check_finished => 1, ); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_arrp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arrp\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_strp\(/); vcd_identical ("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_import_c.cpp0000664000177100017500000001751713702133370022201 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_import__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif typedef struct { int a; int b; } substruct_t; #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern unsigned char dpii_f_bit (unsigned char i); extern svBitVecVal dpii_f_bit8 (const svBitVecVal* i); extern svBitVecVal dpii_f_bit9 (const svBitVecVal* i); extern svBitVecVal dpii_f_bit16 (const svBitVecVal* i); extern svBitVecVal dpii_f_bit17 (const svBitVecVal* i); extern svBitVecVal dpii_f_bit32 (const svBitVecVal* i); extern long long dpii_f_bit33 (const svBitVecVal* i); extern long long dpii_f_bit64 (const svBitVecVal* i); extern long long dpii_f_bit95 (const svBitVecVal* i, svBitVecVal* o); extern int dpii_f_int (int i); extern char dpii_f_byte (char i); extern short int dpii_f_shortint(short int i); extern long long dpii_f_longint (long long i); extern void* dpii_f_chandle (void* i); extern const char* dpii_f_string (const char* i); extern double dpii_f_real (double i); extern float dpii_f_shortreal(float i); extern void dpii_v_bit (unsigned char i, unsigned char* o); extern void dpii_v_int (int i, int *o); extern void dpii_v_uint (unsigned int i, unsigned int *o); extern void dpii_v_byte (char i, char *o); extern void dpii_v_shortint (short int i, short int *o); extern void dpii_v_ushort (unsigned short i, unsigned short *o); extern void dpii_v_longint (long long i, long long *o); extern void dpii_v_ulong (unsigned long long i, unsigned long long *o); extern void dpii_v_struct (const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_substruct (const svBitVecVal* i, int* o); extern void dpii_v_chandle (void* i, void* *o); extern void dpii_v_string (const char* i, const char** o); extern void dpii_v_real (double i, double* o); extern void dpii_v_shortreal(float i, float* o); extern void dpii_v_struct (const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_substruct (const svBitVecVal* i, int* o); extern void dpii_v_bit64(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_bit95(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_reg(unsigned char i, unsigned char* o); extern void dpii_v_reg15(const svLogicVecVal* i, svLogicVecVal* o); extern void dpii_v_reg95(const svLogicVecVal* i, svLogicVecVal* o); extern void dpii_v_integer(const svLogicVecVal* i, svLogicVecVal* o); extern void dpii_v_time(const svLogicVecVal* i, svLogicVecVal* o); extern int dpii_f_strlen(const char* i); extern void dpii_f_void(); extern int dpii_t_void(); extern int dpii_t_void_context(); extern int dpii_t_int(int i, int *o); extern int dpii_fa_bit(int i); } #endif //====================================================================== unsigned char dpii_f_bit (unsigned char i) { return 0x1 & ~i; } svBitVecVal dpii_f_bit8 (const svBitVecVal *i) { return 0xffUL & ~*i; } svBitVecVal dpii_f_bit9 (const svBitVecVal *i) { return 0x1ffUL & ~*i; } svBitVecVal dpii_f_bit16(const svBitVecVal *i) { return 0xffffUL & ~*i; } svBitVecVal dpii_f_bit17(const svBitVecVal *i) { return 0x1ffffUL & ~*i; } svBitVecVal dpii_f_bit32(const svBitVecVal *i) { return ~*i; } long long dpii_f_bit33(const svBitVecVal *i) { return ((1ULL<<33)-1) & ~((long long)(i[1])<<32ULL | i[0]); } long long dpii_f_bit64(const svBitVecVal *i) { return ~((long long)(i[1])<<32ULL | i[0]); } int dpii_f_int (int i) { return ~i; } char dpii_f_byte (char i) { return ~i; } short int dpii_f_shortint(short int i) { return ~i; } long long dpii_f_longint (long long i) { return ~i; } void* dpii_f_chandle (void* i) { return i; } const char* dpii_f_string (const char* i) { return i; } double dpii_f_real (double i) { return i+1.5; } float dpii_f_shortreal(float i) { return i+1.5f; } void dpii_v_bit(unsigned char i, unsigned char *o) { *o = 1 & ~i; } void dpii_v_int(int i, int *o) { *o = ~i; } void dpii_v_uint(unsigned int i, unsigned int *o) { *o = ~i; } void dpii_v_byte(char i, char *o) { *o = ~i; } void dpii_v_shortint(short int i, short int *o) { *o = ~i; } void dpii_v_ushort(unsigned short i, unsigned short *o) { *o = ~i; } void dpii_v_longint(long long i, long long *o) { *o = ~i; } void dpii_v_ulong(unsigned long long i, unsigned long long *o) { *o = ~i; } void dpii_v_chandle(void* i, void* *o) { *o = i; } void dpii_v_string(const char* i, const char** o) { *o = strdup(i); } // Leaks void dpii_v_real(double i, double* o) { *o = i + 1.5; } void dpii_v_shortreal(float i, float* o) { *o = i + 1.5f; } void dpii_v_reg(unsigned char i, unsigned char* o) { *o = (~i)&1; } void dpii_v_reg15(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval) & 0x7fffUL; o[0].bval = 0; } void dpii_v_reg95(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval); o[1].aval = (~i[1].aval); o[2].aval = (~i[2].aval) & 0x7fffffffUL; o[0].bval = 0; o[1].bval = 0; o[2].bval = 0; } void dpii_v_integer(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval); o[0].bval = 0; } void dpii_v_time(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval); o[1].aval = (~i[1].aval); o[0].bval = 0; o[1].bval = 0; } void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o) { o[0] = ~i[0]; o[1] = ~i[1]; o[2] = ~i[2]; } void dpii_v_substruct(const svBitVecVal* i, int* o) { // To be most like other tools, this should automagically take the substruct_t // as an argument, and not require this cast... substruct_t* issp = (substruct_t*)i; o[0] = issp->b - issp->a; } void dpii_v_bit64(const svBitVecVal* i, svBitVecVal* o) { o[0] = ~i[0]; o[1] = ~i[1]; } void dpii_v_bit95(const svBitVecVal* i, svBitVecVal* o) { o[0] = (~i[0]); o[1] = (~i[1]); o[2] = (~i[2]) & 0x7fffffffUL; } void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o) { o[0] = ~i[0]; o[1] = ~i[1]; o[2] = ~i[2]; } int dpii_f_strlen(const char* i) { return strlen(i); } //====================================================================== void dpii_f_void() {} #ifdef VCS void dpii_t_void() {} void dpii_t_void_context() {} void dpii_t_int(int i, int* o) { *o = i; } #else int dpii_t_void() { return svIsDisabledState(); } int dpii_t_void_context() { return svIsDisabledState(); } int dpii_t_int(int i, int* o) { *o = i; return svIsDisabledState(); // Tasks generally need this } #endif int dpii_fa_bit(int i) { return ~i; } verilator-4.038/test_regress/t/t_dpi_openfirst.pl0000775000177100017500000000121513702133370022216 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["t/t_dpi_openfirst_c.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_tree_inl0_pub1.vlt0000664000177100017500000000042213702133370023404 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config no_inline -module "l*" public -module "l*" -var "z*" verilator-4.038/test_regress/t/t_array_pattern_2d.pl0000775000177100017500000000105313702133367022617 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_dtree_inlab.pl0000775000177100017500000000125113702133370022656 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_A +define+INLINE_B'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_dup_bad.v0000664000177100017500000000047613702133370021445 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module a(); endmodule module test(); a a(); endmodule module a(); endmodule module b(); endmodule verilator-4.038/test_regress/t/t_mem_func.pl0000775000177100017500000000105313702133370021142 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_slice_cond.pl0000775000177100017500000000100113702133370021444 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_upscope.out0000664000177100017500000000061213650310376022056 0ustar wsnyderwsnydercreated tag with scope = top.t.b.gen[0].tag created tag with scope = top.t.b.gen[1].tag created tag with scope = top.t.tag mod a has scope = top.t mod a has tag = top.t.tag mod b has scope = top.t.b mod b has tag = top.t.tag mod c has scope = top.t.b.gen[0].c mod c has tag = top.t.b.gen[0].tag mod c has scope = top.t.b.gen[1].c mod c has tag = top.t.b.gen[1].tag *-* All Finished *-* verilator-4.038/test_regress/t/t_runflag_errorlimit.out0000664000177100017500000000070313702133370023451 0ustar wsnyderwsnyder[0] %Error: t_runflag_errorlimit.v:9: Assertion failed in top.t: One -Info: t/t_runflag_errorlimit.v:9: Verilog $stop, ignored due to +verilator+error+limit [0] %Error: t_runflag_errorlimit.v:10: Assertion failed in top.t: Two -Info: t/t_runflag_errorlimit.v:10: Verilog $stop, ignored due to +verilator+error+limit [0] %Error: t_runflag_errorlimit.v:11: Assertion failed in top.t: Three %Error: t/t_runflag_errorlimit.v:11: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_func_redef.pl0000775000177100017500000000100113702133370021442 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_array_partial.v0000664000177100017500000000426713702133370023101 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2011 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [19:10] bitout; wire [29:24] short_bitout; wire [7:0] allbits; wire [15:0] twobits; sub i_sub1 [7:4] (.allbits (allbits), .twobits (twobits[15:8]), .bitout (bitout[17:14])), i_sub2 [3:0] (.allbits (allbits), .twobits (twobits[7:0]), .bitout (bitout[13:10])); sub i_sub3 [7:4] (.allbits (allbits), .twobits (twobits[15:8]), .bitout (bitout[17:14])); sub i_sub4 [7:4] (.allbits (allbits), .twobits (twobits[15:8]), .bitout (short_bitout[27:24])); sub i_sub5 [7:0] (.allbits (allbits), .twobits (twobits), .bitout (bitout[17:10])); sub i_sub6 [7:4] (.allbits (allbits), .twobits (twobits[15:8]), .bitout ({bitout[18+:2],short_bitout[28+:2]})); integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Signals under test assign allbits = crc[7:0]; assign twobits = crc[15:0]; wire [63:0] result = {48'h0, short_bitout, bitout}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'ha1da9ff8082a4ff6 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule // t module sub ( input wire [7:0] allbits, input wire [1:0] twobits, output wire bitout); assign bitout = (^ twobits) ^ (^ allbits); endmodule // sub verilator-4.038/test_regress/t/t_typedef_param.v0000664000177100017500000000425713702133370022031 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef reg [2:0] threeansi_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = crc[2:0]; localparam type three_t = reg [2:0]; three_t outna; three_t outa; TestNonAnsi #( .p_t (reg [2:0]) ) test (// Outputs .out (outna), /*AUTOINST*/ // Inputs .clk (clk), .in (in[2:0])); TestAnsi #( .p_t (reg [2:0])) testa (// Outputs .out (outa), /*AUTOINST*/ // Inputs .clk (clk), .in (in[2:0])); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, outna, 1'b0, outa}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h018decfea0a8828a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module TestNonAnsi (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); parameter type p_t = shortint; input clk; input p_t in; output p_t out; always @(posedge clk) begin out <= ~in; end endmodule module TestAnsi #( parameter type p_t = shortint ) ( input clk, input p_t in, output p_t out ); always @(posedge clk) begin out <= ~in; end endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-4.038/test_regress/t/t_flag_fi_h.h0000664000177100017500000000101713702133370021060 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* extern void myfunction(); verilator-4.038/test_regress/t/t_time_sc_sec.pl0000775000177100017500000000141113702133370021624 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_time_sc.v"); $Self->{sc_time_resolution} = 'SC_SEC'; compile( verilator_flags2 => ['-sc', '-timescale 1s/1s', '+define+TEST_EXPECT=20s'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_interface_array0.v0000664000177100017500000000253413702133370023262 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 parameter N = 4; interface a_if #(parameter PARAM = 0) (); logic long_name; modport source (output long_name); modport sink (input long_name); endinterface module intf_source ( input logic [N-1:0] intf_input, a_if.source i_intf_source[N-1:0] ); generate for (genvar i=0; i < N;i++) begin assign i_intf_source[i].long_name = intf_input[i]; end endgenerate endmodule module intf_sink ( output [N-1:0] a_out, a_if.sink i_intf_sink[N-1:0] ); generate for (genvar i=0; i < N;i++) begin assign a_out[i] = i_intf_sink[i].long_name; end endgenerate endmodule module t ( clk ); input clk; logic [N-1:0] a_in; logic [N-1:0] a_out; logic [N-1:0] ack_out; a_if #(.PARAM(1)) tl_intf [N-1:0] (); intf_source source(a_in, tl_intf); intf_sink sink(a_out, tl_intf); initial a_in = '0; always @(posedge clk) begin a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; if (ack_out != a_out) begin $stop; end if (& a_in) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_sys_readmem_bad_end.out0000664000177100017500000000017013702133370023505 0ustar wsnyderwsnyder%Error: t/t_sys_readmem_bad_end.mem:12: $readmem file ended before specified final address (IEEE 2017 21.4) Aborting... verilator-4.038/test_regress/t/t_flag_lib.v0000664000177100017500000000041413702133370020737 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); liblib_a a (); endmodule verilator-4.038/test_regress/t/t_vlt_warn.pl0000775000177100017500000000107013702133370021204 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only t/t_vlt_warn.vlt -Wall"], ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_public_func.pl0000775000177100017500000000145713702133370023030 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_trace_public.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["-DATTRIBUTES -DPUB_FUNC --trace --exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", "t/t_trace_public.out"); ok(1); 1; verilator-4.038/test_regress/t/t_math_concat.pl0000775000177100017500000000105313702133370021631 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_port.pl0000775000177100017500000000105313702133370021741 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex.out0000664000177100017500000001017613702133370022375 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Tue Jan 21 18:15:27 2020 $end $timescale 1ps $end $scope module top $end $var wire 1 7" clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module t $end $var wire 1 7" clk $end $var wire 32 + cyc [31:0] $end $var wire 8 p" unpacked_array(-1) [7:0] $end $var wire 8 o" unpacked_array(-2) [7:0] $end $var wire 8 q" unpacked_array(0) [7:0] $end $var real 64 E! v_arr_real(0) $end $var real 64 G! v_arr_real(1) $end $var wire 2 [ v_arrp [2:1] $end $var wire 4 c v_arrp_arrp [3:0] $end $var wire 4 k v_arrp_strp [3:0] $end $var wire 1 ?" v_arru(1) $end $var wire 1 @" v_arru(2) $end $var wire 2 s v_arru_arrp(3) [2:1] $end $var wire 2 t v_arru_arrp(4) [2:1] $end $var wire 1 O" v_arru_arru(3)(1) $end $var wire 1 W" v_arru_arru(3)(2) $end $var wire 1 _" v_arru_arru(4)(1) $end $var wire 1 g" v_arru_arru(4)(2) $end $var wire 2 %! v_arru_strp(3) [1:0] $end $var wire 2 -! v_arru_strp(4) [1:0] $end $var wire 3 u! v_enumb [2:0] $end $var wire 6 }! v_enumb2_str [5:0] $end $var wire 32 e! v_enumed [31:0] $end $var wire 32 m! v_enumed2 [31:0] $end $var real 64 5! v_real $end $var wire 64 3 v_str32x2 [63:0] $end $var wire 2 C v_strp [1:0] $end $var wire 4 K v_strp_strp [3:0] $end $var wire 2 S v_unip_strp [1:0] $end $scope module p2 $end $var wire 32 )# PARAM [31:0] $end $upscope $end $scope module p3 $end $var wire 32 1# PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 '" b [31:0] $end $scope module unnamedblk2 $end $var wire 32 /" a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 + b0000000000000000000000000000000000000000000000000000000011111111 3 b00 C b0000 K b00 S b00 [ b0000 c b0000 k b00 s b00 t b00 %! b00 -! r0 5! r0 E! r0 G! b00000000000000000000000000000000 e! b00000000000000000000000000000000 m! b000 u! b000000 }! b00000000000000000000000000000000 '" b00000000000000000000000000000000 /" 07" 0?" 0@" 0O" 0W" 0_" 0g" b00000000 o" b00000000 p" b00000000 q" b00000000000000000000000000000010 )# b00000000000000000000000000000011 1# #10 b00000000000000000000000000000001 + b0000000000000000000000000000000100000000000000000000000011111110 3 b11 C b1111 K b11 S b11 [ b1111 c b1111 k b11 s b11 t b11 %! b11 -! r0.1 5! r0.2 E! r0.3 G! b00000000000000000000000000000001 e! b00000000000000000000000000000010 m! b111 u! b00000000000000000000000000000101 '" b00000000000000000000000000000101 /" 17" #15 07" #20 b00000000000000000000000000000010 + b0000000000000000000000000000001000000000000000000000000011111101 3 b00 C b0000 K b00 S b00 [ b0000 c b0000 k b00 s b00 t b00 %! b00 -! r0.2 5! r0.4 E! r0.6 G! b00000000000000000000000000000010 e! b00000000000000000000000000000100 m! b110 u! b111111 }! 17" #25 07" #30 b00000000000000000000000000000011 + b0000000000000000000000000000001100000000000000000000000011111100 3 b11 C b1111 K b11 S b11 [ b1111 c b1111 k b11 s b11 t b11 %! b11 -! r0.3 5! r0.6000000000000001 E! r0.8999999999999999 G! b00000000000000000000000000000011 e! b00000000000000000000000000000110 m! b101 u! b110110 }! 17" #35 07" #40 b00000000000000000000000000000100 + b0000000000000000000000000000010000000000000000000000000011111011 3 b00 C b0000 K b00 S b00 [ b0000 c b0000 k b00 s b00 t b00 %! b00 -! r0.4 5! r0.8 E! r1.2 G! b00000000000000000000000000000100 e! b00000000000000000000000000001000 m! b100 u! b101101 }! 17" #45 07" #50 b00000000000000000000000000000101 + b0000000000000000000000000000010100000000000000000000000011111010 3 b11 C b1111 K b11 S b11 [ b1111 c b1111 k b11 s b11 t b11 %! b11 -! r0.5 5! r1 E! r1.5 G! b00000000000000000000000000000101 e! b00000000000000000000000000001010 m! b011 u! b100100 }! 17" #55 07" #60 b00000000000000000000000000000110 + b0000000000000000000000000000011000000000000000000000000011111001 3 b00 C b0000 K b00 S b00 [ b0000 c b0000 k b00 s b00 t b00 %! b00 -! r0.6 5! r1.2 E! r1.8 G! b00000000000000000000000000000110 e! b00000000000000000000000000001100 m! b010 u! b011011 }! 17" verilator-4.038/test_regress/t/t_assert_synth_full_vlt.out0000664000177100017500000000023713702133367024210 0ustar wsnyderwsnyder[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: synthesis full_case, but non-match found %Error: t/t_assert_synth.v:40: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_past_unsup_bad.out0000664000177100017500000000027013702133370022551 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_past_unsup_bad.v:13:11: Unsupported: $past expr2 and clock arguments 13 | if ($past(d, 0, 0, 0)) $stop; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_time_vpi_100s10ms.pl0000775000177100017500000000151313702133370022432 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator_st => 1); top_filename("t/t_time_vpi.v"); $Self->{main_time_multiplier} = 100e0 / 10e-6; compile( v_flags2 => ['+define+time_scale_units=100s +define+time_scale_prec=10ms', 't/t_time_vpi_c.cpp'], verilator_flags2 => ['--vpi'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_ref_bad1.pl0000775000177100017500000000107113702133370021664 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_cover_line.v0000664000177100017500000001221013702133367021330 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; initial toggle=0; integer cyc; initial cyc=1; wire [7:0] cyc_copy = cyc[7:0]; alpha a1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); alpha a2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); beta b2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); tsk t1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; toggle <= '0; // Single and multiline if if (cyc==3) $write(""); if (cyc==3) begin $write(""); end // Single and multiline else if (cyc==3) ; else $write(""); if (cyc==3) ; else begin $write(""); end // Single and multiline if else if (cyc==3) $write(""); else $write(""); if (cyc==3) begin $write(""); end else begin $write(""); end // multiline elseif if (cyc==3) begin $write(""); end else if (cyc==4) begin $write(""); end else if (cyc==5) begin $write(""); end else begin $write(""); end // Single and multiline while while (0); while (0) begin $write(""); end do ; while (0); do begin $write(""); end while (0); //=== // Task and complicated if (cyc==3) begin toggle <= '1; end else if (cyc==5) begin `ifdef VERILATOR $c("call_task();"); `else call_task(); `endif end else if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end task call_task; /* verilator public */ t1.center_task(1'b1); endtask endmodule module alpha (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; always @ (posedge clk) begin if (toggle) begin // CHECK_COVER(0,"top.t.a*",2) $write(""); // t.a1 and t.a2 collapse to a count of 2 end if (toggle) begin $write(""); // CHECK_COVER_MISSING(0) // This doesn't even get added `ifdef ATTRIBUTE // verilator coverage_block_off `endif end end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ always @ (posedge clk) begin $write(""); // Always covered if (0) begin // CHECK_COVER(0,"top.t.b*",0) // Make sure that we don't optimize away zero buckets $write(""); end if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) // t.b1 and t.b2 collapse to a count of 2 $write(""); end if (toggle) begin : block // This doesn't `ifdef ATTRIBUTE // verilator coverage_block_off `endif begin end // Needed for .vlt to attach coverage_block_off if (1) begin end // CHECK_COVER_MISSING(0) $write(""); // CHECK_COVER_MISSING(0) end end endmodule module tsk (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ always @ (posedge clk) begin center_task(1'b0); end task center_task; input external; begin if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) $write(""); end if (external) begin // CHECK_COVER(0,"top.t.t1",1) $write("[%0t] Got external pulse\n", $time); end end endtask endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; // verilator coverage_off always @ (posedge clk) begin if (toggle) begin $write(""); // CHECK_COVER_MISSING(0) // because under coverage_module_off end end // verilator coverage_on always @ (posedge clk) begin if (toggle) begin // because under coverage_module_off $write(""); if (0) ; // CHECK_COVER(0,"top.t.o1",1) end end endmodule verilator-4.038/test_regress/t/t_mem_slot.v0000664000177100017500000000121013702133370021012 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define RegDel 1 module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal); input Clk; input [1:0] SlotIdx; input BitToChange; input BitVal; input [1:0] SlotToReturn; output reg [1:0] OutputVal; reg [1:0] Array[2:0]; always @(posedge Clk) begin Array[SlotIdx][BitToChange] <= #`RegDel BitVal; OutputVal = Array[SlotToReturn]; end endmodule verilator-4.038/test_regress/t/t_inst_overwide_bad.pl0000775000177100017500000000116113702133370023040 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_inst_overwide.v"); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_dpulse.v0000664000177100017500000000214013702133367021331 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off GENCLK reg [7:0] cyc; initial cyc=0; reg genclk; // verilator lint_off MULTIDRIVEN reg [7:0] set_both; // verilator lint_on MULTIDRIVEN wire genthiscyc = ( (cyc % 2) == 1 ); always @ (posedge clk) begin cyc <= cyc + 8'h1; genclk <= genthiscyc; set_both <= cyc; $write ("SB set_both %x <= cyc %x\n", set_both, cyc); if (genthiscyc) begin if (cyc>1 && set_both != (cyc - 8'h1)) $stop; end else begin if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end always @ (posedge genclk) begin set_both <= ~ set_both; $write ("SB set_both %x <= cyc %x\n", set_both, ~cyc); if (cyc>1 && set_both != (cyc - 8'h1)) $stop; end endmodule verilator-4.038/test_regress/t/t_func_range.v0000664000177100017500000000267113702133370021316 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; // verilator lint_off WIDTH `define INT_RANGE 31:0 `define INT_RANGE_MAX 31 `define VECTOR_RANGE 63:0 reg [`INT_RANGE] stashb, stasha, stashn, stashm; function [`VECTOR_RANGE] copy_range; input [`VECTOR_RANGE] y; input [`INT_RANGE] b; input [`INT_RANGE] a; input [`VECTOR_RANGE] x; input [`INT_RANGE] n; input [`INT_RANGE] m; begin copy_range = y; stashb = b; stasha = a; stashn = n; stashm = m; end endfunction parameter DATA_SIZE = 16; parameter NUM_OF_REGS = 32; reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; reg [DATA_SIZE-1:0] memread_rf_reg; always @(memread_rf) begin : memread_convert memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf, DATA_SIZE-'d1, DATA_SIZE-'d1); end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin memread_rf = 512'haa; end if (cyc==3) begin if (stashb != 'd15) $stop; if (stasha != 'd15) $stop; if (stashn != 'd15) $stop; if (stashm != 'd15) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_gen_missing.pl0000775000177100017500000000112613702133370021654 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ['+define+T_GEN_MISSING'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_bsspace_bad.v0000664000177100017500000000055413702133370022461 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Fake binary character here '', so is treated as binary and // don't get whitespace violation. `define FOO blak \ blak module t; endmodule verilator-4.038/test_regress/t/t_display_mcd.v0000664000177100017500000000066113702133370021474 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $fwrite(32'h8000_0001, "To stdout\n"); $fflush(32'h8000_0001); $fwrite(32'h8000_0002, "To stderr\n"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_dup2_bad.pl0000775000177100017500000000107413702133370021704 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_time.pl0000775000177100017500000000113413702133370022034 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_inside.v0000664000177100017500000000322113702133367021453 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; reg [63:0] sum; reg out1; reg [4:0] out2; sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n",$time, cyc, crc, sum, crc[3:0], out1,out2); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; if (cyc==0) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); `define EXPECTED_SUM 64'h10204fa5567c8a4b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, out2, // Inputs in ); input [23:0] in; output reg out1; output reg [4:0] out2; always @* begin case (in[3:0]) inside default: {out1,out2} = {1'b0,5'h0F}; // Note not last item 4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01}; 4'h4: {out1,out2} = {1'b1,5'h04}; [4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match 4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08}; [4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C}; endcase end endmodule verilator-4.038/test_regress/t/t_hierarchy_identifier_bad.pl0000775000177100017500000000107113702133370024337 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_missing_bad.v0000664000177100017500000000067513702133370022525 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); wire ok = 1'b0; sub sub (.ok(ok), , .nc()); endmodule module sub (input ok, input none, input nc, input missing); initial if (ok && none && nc && missing) begin end // No unused warning endmodule verilator-4.038/test_regress/t/t_func_tie_bad.pl0000775000177100017500000000107413702133370021756 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2011 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_genblk.out0000664000177100017500000000043213702133370021635 0ustar wsnyderwsnyder015: exp=top.t.show0 got=top.t.show0 019: exp=top.t.genblk1.show1 got=top.t.genblk1.show1 023: exp=top.t.genblk2.show2 got=top.t.genblk2.show2 028: exp=top.t.genblk3.genblk1.show3 got=top.t.genblk3.genblk1.show3 034: exp=top.t.x1.x3.show4 got=top.t.x1.x3.show4 *-* All Finished *-* verilator-4.038/test_regress/t/t_interface_down_noinl.pl0000775000177100017500000000116013702133370023536 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_sc_fs.pl0000775000177100017500000000141313702133370021464 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_time_sc.v"); $Self->{sc_time_resolution} = 'SC_FS'; compile( verilator_flags2 => ['-sc', '-timescale 1fs/1fs', '+define+TEST_EXPECT=20fs'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_output_type.out0000664000177100017500000001206113702133370023631 0ustar wsnyderwsnyderi_chandle 0 i_string 0 i_bit 0 i_logic 0 i_chandle_t 0 i_string_t 0 i_bit_t 0 i_logic_t 0 i_array_2_state_1 0 i_array_2_state_32 0 i_array_2_state_33 0 i_array_2_state_64 0 i_array_2_state_65 0 i_array_2_state_128 0 i_struct_2_state_1 0 i_struct_2_state_32 0 i_struct_2_state_33 0 i_struct_2_state_64 0 i_struct_2_state_65 0 i_struct_2_state_128 0 i_union_2_state_1 0 i_union_2_state_32 0 i_union_2_state_33 0 i_union_2_state_64 0 i_union_2_state_65 0 i_union_2_state_128 0 i_array_4_state_1 0 i_array_4_state_32 0 i_array_4_state_33 0 i_array_4_state_64 0 i_array_4_state_65 0 i_array_4_state_128 0 i_struct_4_state_1 0 i_struct_4_state_32 0 i_struct_4_state_33 0 i_struct_4_state_64 0 i_struct_4_state_65 0 i_struct_4_state_128 0 i_union_4_state_1 0 i_union_4_state_32 0 i_union_4_state_33 0 i_union_4_state_64 0 i_union_4_state_65 0 i_union_4_state_128 0 e_chandle 0 e_string 0 e_bit 0 e_logic 0 e_chandle_t 0 e_string_t 0 e_bit_t 0 e_logic_t 0 e_array_2_state_1 0 e_array_2_state_32 0 e_array_2_state_33 0 e_array_2_state_64 0 e_array_2_state_65 0 e_array_2_state_128 0 e_struct_2_state_1 0 e_struct_2_state_32 0 e_struct_2_state_33 0 e_struct_2_state_64 0 e_struct_2_state_65 0 e_struct_2_state_128 0 e_union_2_state_1 0 e_union_2_state_32 0 e_union_2_state_33 0 e_union_2_state_64 0 e_union_2_state_65 0 e_union_2_state_128 0 e_array_4_state_1 0 e_array_4_state_32 0 e_array_4_state_33 0 e_array_4_state_64 0 e_array_4_state_65 0 e_array_4_state_128 0 e_struct_4_state_1 0 e_struct_4_state_32 0 e_struct_4_state_33 0 e_struct_4_state_64 0 e_struct_4_state_65 0 e_struct_4_state_128 0 e_union_4_state_1 0 e_union_4_state_32 0 e_union_4_state_33 0 e_union_4_state_64 0 e_union_4_state_65 0 e_union_4_state_128 0 i_chandle 1 i_string 1 i_bit 1 i_logic 1 i_chandle_t 1 i_string_t 1 i_bit_t 1 i_logic_t 1 i_array_2_state_1 1 i_array_2_state_32 1 i_array_2_state_33 1 i_array_2_state_64 1 i_array_2_state_65 1 i_array_2_state_128 1 i_struct_2_state_1 1 i_struct_2_state_32 1 i_struct_2_state_33 1 i_struct_2_state_64 1 i_struct_2_state_65 1 i_struct_2_state_128 1 i_union_2_state_1 1 i_union_2_state_32 1 i_union_2_state_33 1 i_union_2_state_64 1 i_union_2_state_65 1 i_union_2_state_128 1 i_array_4_state_1 1 i_array_4_state_32 1 i_array_4_state_33 1 i_array_4_state_64 1 i_array_4_state_65 1 i_array_4_state_128 1 i_struct_4_state_1 1 i_struct_4_state_32 1 i_struct_4_state_33 1 i_struct_4_state_64 1 i_struct_4_state_65 1 i_struct_4_state_128 1 i_union_4_state_1 1 i_union_4_state_32 1 i_union_4_state_33 1 i_union_4_state_64 1 i_union_4_state_65 1 i_union_4_state_128 1 e_chandle 1 e_string 1 e_bit 1 e_logic 1 e_chandle_t 1 e_string_t 1 e_bit_t 1 e_logic_t 1 e_array_2_state_1 1 e_array_2_state_32 1 e_array_2_state_33 1 e_array_2_state_64 1 e_array_2_state_65 1 e_array_2_state_128 1 e_struct_2_state_1 1 e_struct_2_state_32 1 e_struct_2_state_33 1 e_struct_2_state_64 1 e_struct_2_state_65 1 e_struct_2_state_128 1 e_union_2_state_1 1 e_union_2_state_32 1 e_union_2_state_33 1 e_union_2_state_64 1 e_union_2_state_65 1 e_union_2_state_128 1 e_array_4_state_1 1 e_array_4_state_32 1 e_array_4_state_33 1 e_array_4_state_64 1 e_array_4_state_65 1 e_array_4_state_128 1 e_struct_4_state_1 1 e_struct_4_state_32 1 e_struct_4_state_33 1 e_struct_4_state_64 1 e_struct_4_state_65 1 e_struct_4_state_128 1 e_union_4_state_1 1 e_union_4_state_32 1 e_union_4_state_33 1 e_union_4_state_64 1 e_union_4_state_65 1 e_union_4_state_128 1 i_chandle 2 i_string 2 i_bit 2 i_logic 2 i_chandle_t 2 i_string_t 2 i_bit_t 2 i_logic_t 2 i_array_2_state_1 2 i_array_2_state_32 2 i_array_2_state_33 2 i_array_2_state_64 2 i_array_2_state_65 2 i_array_2_state_128 2 i_struct_2_state_1 2 i_struct_2_state_32 2 i_struct_2_state_33 2 i_struct_2_state_64 2 i_struct_2_state_65 2 i_struct_2_state_128 2 i_union_2_state_1 2 i_union_2_state_32 2 i_union_2_state_33 2 i_union_2_state_64 2 i_union_2_state_65 2 i_union_2_state_128 2 i_array_4_state_1 2 i_array_4_state_32 2 i_array_4_state_33 2 i_array_4_state_64 2 i_array_4_state_65 2 i_array_4_state_128 2 i_struct_4_state_1 2 i_struct_4_state_32 2 i_struct_4_state_33 2 i_struct_4_state_64 2 i_struct_4_state_65 2 i_struct_4_state_128 2 i_union_4_state_1 2 i_union_4_state_32 2 i_union_4_state_33 2 i_union_4_state_64 2 i_union_4_state_65 2 i_union_4_state_128 2 e_chandle 2 e_string 2 e_bit 2 e_logic 2 e_chandle_t 2 e_string_t 2 e_bit_t 2 e_logic_t 2 e_array_2_state_1 2 e_array_2_state_32 2 e_array_2_state_33 2 e_array_2_state_64 2 e_array_2_state_65 2 e_array_2_state_128 2 e_struct_2_state_1 2 e_struct_2_state_32 2 e_struct_2_state_33 2 e_struct_2_state_64 2 e_struct_2_state_65 2 e_struct_2_state_128 2 e_union_2_state_1 2 e_union_2_state_32 2 e_union_2_state_33 2 e_union_2_state_64 2 e_union_2_state_65 2 e_union_2_state_128 2 e_array_4_state_1 2 e_array_4_state_32 2 e_array_4_state_33 2 e_array_4_state_64 2 e_array_4_state_65 2 e_array_4_state_128 2 e_struct_4_state_1 2 e_struct_4_state_32 2 e_struct_4_state_33 2 e_struct_4_state_64 2 e_struct_4_state_65 2 e_struct_4_state_128 2 e_union_4_state_1 2 e_union_4_state_32 2 e_union_4_state_33 2 e_union_4_state_64 2 e_union_4_state_65 2 e_union_4_state_128 2 *-* All Finished *-* verilator-4.038/test_regress/t/t_display.pl0000775000177100017500000000113513702133370021017 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_output_type__Dpi.out0000664000177100017500000003344413702133370024574 0ustar wsnyderwsnyder// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS // DPI export at t/t_dpi_arg_output_type.v:521:18 extern void e_array_2_state_1(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:556:18 extern void e_array_2_state_128(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:528:18 extern void e_array_2_state_32(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:535:18 extern void e_array_2_state_33(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:542:18 extern void e_array_2_state_64(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:549:18 extern void e_array_2_state_65(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:650:18 extern void e_array_4_state_1(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:685:18 extern void e_array_4_state_128(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:657:18 extern void e_array_4_state_32(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:664:18 extern void e_array_4_state_33(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:671:18 extern void e_array_4_state_64(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:678:18 extern void e_array_4_state_65(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:399:18 extern void e_bit(svBit* o); // DPI export at t/t_dpi_arg_output_type.v:506:18 extern void e_bit_t(svBit* o); // DPI export at t/t_dpi_arg_output_type.v:307:18 extern void e_byte(char* o); // DPI export at t/t_dpi_arg_output_type.v:414:18 extern void e_byte_t(char* o); // DPI export at t/t_dpi_arg_output_type.v:313:18 extern void e_byte_unsigned(unsigned char* o); // DPI export at t/t_dpi_arg_output_type.v:420:18 extern void e_byte_unsigned_t(unsigned char* o); // DPI export at t/t_dpi_arg_output_type.v:385:18 extern void e_chandle(void** o); // DPI export at t/t_dpi_arg_output_type.v:492:18 extern void e_chandle_t(void** o); // DPI export at t/t_dpi_arg_output_type.v:331:18 extern void e_int(int* o); // DPI export at t/t_dpi_arg_output_type.v:438:18 extern void e_int_t(int* o); // DPI export at t/t_dpi_arg_output_type.v:337:18 extern void e_int_unsigned(unsigned int* o); // DPI export at t/t_dpi_arg_output_type.v:444:18 extern void e_int_unsigned_t(unsigned int* o); // DPI export at t/t_dpi_arg_output_type.v:364:18 extern void e_integer(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:471:18 extern void e_integer_t(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:406:18 extern void e_logic(svLogic* o); // DPI export at t/t_dpi_arg_output_type.v:513:18 extern void e_logic_t(svLogic* o); // DPI export at t/t_dpi_arg_output_type.v:343:18 extern void e_longint(long long* o); // DPI export at t/t_dpi_arg_output_type.v:450:18 extern void e_longint_t(long long* o); // DPI export at t/t_dpi_arg_output_type.v:349:18 extern void e_longint_unsigned(unsigned long long* o); // DPI export at t/t_dpi_arg_output_type.v:456:18 extern void e_longint_unsigned_t(unsigned long long* o); // DPI export at t/t_dpi_arg_output_type.v:371:18 extern void e_real(double* o); // DPI export at t/t_dpi_arg_output_type.v:478:18 extern void e_real_t(double* o); // DPI export at t/t_dpi_arg_output_type.v:319:18 extern void e_shortint(short* o); // DPI export at t/t_dpi_arg_output_type.v:426:18 extern void e_shortint_t(short* o); // DPI export at t/t_dpi_arg_output_type.v:325:18 extern void e_shortint_unsigned(unsigned short* o); // DPI export at t/t_dpi_arg_output_type.v:432:18 extern void e_shortint_unsigned_t(unsigned short* o); // DPI export at t/t_dpi_arg_output_type.v:392:18 extern void e_string(const char** o); // DPI export at t/t_dpi_arg_output_type.v:499:18 extern void e_string_t(const char** o); // DPI export at t/t_dpi_arg_output_type.v:564:18 extern void e_struct_2_state_1(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:599:18 extern void e_struct_2_state_128(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:571:18 extern void e_struct_2_state_32(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:578:18 extern void e_struct_2_state_33(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:585:18 extern void e_struct_2_state_64(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:592:18 extern void e_struct_2_state_65(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:693:18 extern void e_struct_4_state_1(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:728:18 extern void e_struct_4_state_128(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:700:18 extern void e_struct_4_state_32(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:707:18 extern void e_struct_4_state_33(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:714:18 extern void e_struct_4_state_64(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:721:18 extern void e_struct_4_state_65(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:356:18 extern void e_time(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:463:18 extern void e_time_t(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:607:18 extern void e_union_2_state_1(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:642:18 extern void e_union_2_state_128(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:614:18 extern void e_union_2_state_32(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:621:18 extern void e_union_2_state_33(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:628:18 extern void e_union_2_state_64(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:635:18 extern void e_union_2_state_65(svBitVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:736:18 extern void e_union_4_state_1(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:771:18 extern void e_union_4_state_128(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:743:18 extern void e_union_4_state_32(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:750:18 extern void e_union_4_state_33(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:757:18 extern void e_union_4_state_64(svLogicVecVal* o); // DPI export at t/t_dpi_arg_output_type.v:764:18 extern void e_union_4_state_65(svLogicVecVal* o); // DPI IMPORTS // DPI import at t/t_dpi_arg_output_type.v:781:41 extern void check_exports(); // DPI import at t/t_dpi_arg_output_type.v:154:33 extern void i_array_2_state_1(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:159:33 extern void i_array_2_state_128(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:155:33 extern void i_array_2_state_32(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:156:33 extern void i_array_2_state_33(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:157:33 extern void i_array_2_state_64(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:158:33 extern void i_array_2_state_65(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:178:33 extern void i_array_4_state_1(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:183:33 extern void i_array_4_state_128(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:179:33 extern void i_array_4_state_32(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:180:33 extern void i_array_4_state_33(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:181:33 extern void i_array_4_state_64(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:182:33 extern void i_array_4_state_65(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:126:33 extern void i_bit(svBit* o); // DPI import at t/t_dpi_arg_output_type.v:150:33 extern void i_bit_t(svBit* o); // DPI import at t/t_dpi_arg_output_type.v:106:33 extern void i_byte(char* o); // DPI import at t/t_dpi_arg_output_type.v:130:33 extern void i_byte_t(char* o); // DPI import at t/t_dpi_arg_output_type.v:107:33 extern void i_byte_unsigned(unsigned char* o); // DPI import at t/t_dpi_arg_output_type.v:131:33 extern void i_byte_unsigned_t(unsigned char* o); // DPI import at t/t_dpi_arg_output_type.v:124:33 extern void i_chandle(void** o); // DPI import at t/t_dpi_arg_output_type.v:148:33 extern void i_chandle_t(void** o); // DPI import at t/t_dpi_arg_output_type.v:110:33 extern void i_int(int* o); // DPI import at t/t_dpi_arg_output_type.v:134:33 extern void i_int_t(int* o); // DPI import at t/t_dpi_arg_output_type.v:111:33 extern void i_int_unsigned(unsigned int* o); // DPI import at t/t_dpi_arg_output_type.v:135:33 extern void i_int_unsigned_t(unsigned int* o); // DPI import at t/t_dpi_arg_output_type.v:118:33 extern void i_integer(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:142:33 extern void i_integer_t(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:127:33 extern void i_logic(svLogic* o); // DPI import at t/t_dpi_arg_output_type.v:151:33 extern void i_logic_t(svLogic* o); // DPI import at t/t_dpi_arg_output_type.v:112:33 extern void i_longint(long long* o); // DPI import at t/t_dpi_arg_output_type.v:136:33 extern void i_longint_t(long long* o); // DPI import at t/t_dpi_arg_output_type.v:113:33 extern void i_longint_unsigned(unsigned long long* o); // DPI import at t/t_dpi_arg_output_type.v:137:33 extern void i_longint_unsigned_t(unsigned long long* o); // DPI import at t/t_dpi_arg_output_type.v:120:33 extern void i_real(double* o); // DPI import at t/t_dpi_arg_output_type.v:144:33 extern void i_real_t(double* o); // DPI import at t/t_dpi_arg_output_type.v:108:33 extern void i_shortint(short* o); // DPI import at t/t_dpi_arg_output_type.v:132:33 extern void i_shortint_t(short* o); // DPI import at t/t_dpi_arg_output_type.v:109:33 extern void i_shortint_unsigned(unsigned short* o); // DPI import at t/t_dpi_arg_output_type.v:133:33 extern void i_shortint_unsigned_t(unsigned short* o); // DPI import at t/t_dpi_arg_output_type.v:125:33 extern void i_string(const char** o); // DPI import at t/t_dpi_arg_output_type.v:149:33 extern void i_string_t(const char** o); // DPI import at t/t_dpi_arg_output_type.v:162:33 extern void i_struct_2_state_1(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:167:33 extern void i_struct_2_state_128(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:163:33 extern void i_struct_2_state_32(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:164:33 extern void i_struct_2_state_33(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:165:33 extern void i_struct_2_state_64(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:166:33 extern void i_struct_2_state_65(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:186:33 extern void i_struct_4_state_1(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:191:33 extern void i_struct_4_state_128(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:187:33 extern void i_struct_4_state_32(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:188:33 extern void i_struct_4_state_33(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:189:33 extern void i_struct_4_state_64(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:190:33 extern void i_struct_4_state_65(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:115:33 extern void i_time(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:139:33 extern void i_time_t(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:170:33 extern void i_union_2_state_1(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:175:33 extern void i_union_2_state_128(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:171:33 extern void i_union_2_state_32(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:172:33 extern void i_union_2_state_33(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:173:33 extern void i_union_2_state_64(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:174:33 extern void i_union_2_state_65(svBitVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:194:33 extern void i_union_4_state_1(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:199:33 extern void i_union_4_state_128(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:195:33 extern void i_union_4_state_32(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:196:33 extern void i_union_4_state_33(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:197:33 extern void i_union_4_state_64(svLogicVecVal* o); // DPI import at t/t_dpi_arg_output_type.v:198:33 extern void i_union_4_state_65(svLogicVecVal* o); #ifdef __cplusplus } #endif verilator-4.038/test_regress/t/t_split_var_1_bad.v0000664000177100017500000000540013702133370022231 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 logic [7:0] should_show_warning_global0 /* verilator split_var */; logic [7:0] should_show_warning_global1 [1:0] /* verilator split_var */; interface ifs; logic [7:0] should_show_warning_ifs0 /* verilator split_var */; logic [7:0] should_show_warning_ifs1 [1:0] /* verilator split_var */; endinterface module t(); // The following variables can not be splitted. will see warnings. real should_show_warning0 /*verilator split_var*/; string should_show_warning1 /*verilator split_var*/; wire should_show_warning2 /*verilator split_var*/; logic [3:0] addr; logic [7:0] rd_data0, rd_data1, rd_data2; logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/; sub0 i_sub0(.addr(addr), .rd_data(rd_data0)); sub1 i_sub1(.addr(addr), .rd_data(rd_data2)); sub2 i_sub2; sub3 i_sub3; ifs i_ifs(); function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/, ref logic [7:0] ref_port /*verilator split_var*/); return 0; endfunction initial begin logic [7:0] loop_idx /*verilator split_var*/; addr = 0; addr = 1; i_sub0.cannot_split1[0] = 0; i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); for (loop_idx = 0; loop_idx < 8'd4; loop_idx = loop_idx + 2) begin addr += 1; end $finish; end endmodule module sub0(input [3:0]addr, output logic [7:0] rd_data); logic [7:0] cannot_split0[0:15] /*verilator split_var*/; logic [7:0] cannot_split1[0:15] /*verilator split_var*/; always_comb rd_data = cannot_split0[addr]; endmodule module sub1(input [3:0]addr, output logic [7:0] rd_data); genvar cannot_split_genvar /*verilator split_var*/; logic [15:0] [8:0] cannot_split /*verilator split_var*/; always_comb begin logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr]; rd_data = rd_tmp[{3'b0, addr[0]}+:8]; end endmodule module sub2; // from t_bitsel_wire_array_bad.v // a and b are arrays of length 1. wire a[0:0] /* verilator split_var */ ; // Array of nets wire b[0:0] /* verilator split_var */ ; assign a = 1'b0; // Only net assignment allowed assign b = a[0]; // Only net assignment allowed endmodule module sub3; // from t_select_bad_range3.v logic [7:0] inwires [12:10] /* verilator split_var */; wire [7:0] outwires [12:10] /* verilator split_var */; assign outwires[10] = inwires[11]; assign outwires[11] = inwires[12]; assign outwires[12] = inwires[13]; // must be an error here endmodule verilator-4.038/test_regress/t/t_interface_missing_bad.pl0000775000177100017500000000110213702133370023643 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_initial_dlyass_bad.pl0000775000177100017500000000114313702133370023167 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_initial_dlyass.v"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_xml_tag.out0000664000177100017500000001333313702133370021201 0ustar wsnyderwsnyder verilator-4.038/test_regress/t/t_vpi_stop_bad.out0000664000177100017500000000004213702133370022210 0ustar wsnyderwsnyder%Error: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_flag_help.pl0000775000177100017500000000170313702133370021274 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); foreach my $prog ( # See also t_flag_version.pl "../bin/verilator", "../bin/verilator_coverage", "../bin/verilator_difftree", "../bin/verilator_gantt", "../bin/verilator_profcfunc", ) { run(fails => 0, cmd => ["perl", $prog, "--help"], logfile => "$Self->{obj_dir}/t_help.log", tee => 0, verilator_run => 1, ); file_grep("$Self->{obj_dir}/t_help.log", qr/DISTRIBUTION/i); } ok(1); 1; verilator-4.038/test_regress/t/t_func_first.pl0000775000177100017500000000105313702133370021513 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_typedef.pl0000775000177100017500000000105313702133370021011 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_wait.out0000664000177100017500000000077413702133370020517 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_wait.v:12:7: Unsupported: wait statements 12 | wait (value == 1); | ^~~~ %Error-UNSUPPORTED: t/t_wait.v:14:7: Unsupported: wait statements 14 | wait (0); | ^~~~ %Error-UNSUPPORTED: t/t_wait.v:17:7: Unsupported: wait statements 17 | wait (value == 2); | ^~~~ %Error-UNSUPPORTED: t/t_wait.v:20:7: Unsupported: wait statements 20 | wait (value == 3) if (value != 3) $stop; | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_EXAMPLE.pl0000775000177100017500000000105313702133367020452 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_import_hdr_only.pl0000775000177100017500000000251013702133370023414 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use File::Temp; use File::Compare; scenarios(simulator => 1); top_filename("t/t_dpi_import.v"); my $tmp_dir = File::Temp->newdir(); compile( # Override default flags also verilator_flags => ["-Wall -Wno-DECLFILENAME -Mdir " . $tmp_dir . " --dpi-hdr-only"], verilator_make_gmake => 0, ); my @files = glob($tmp_dir . "/*"); error("Did not produce DPI header") if scalar(@files) == 0; error("Too many files created:".join(', ', @files)) if scalar(@files) > 1; my $tmp_header = $files[0]; print("============".$tmp_header."\n"); error("Unexpected file $tmp_header") unless $tmp_header =~ /__Dpi\.h$/; compile( verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], verilator_make_gmake => 0, ); @files = glob($Self->obj_dir . "/*__Dpi.h"); my $header = $files[0]; if (compare($tmp_header, $header) != 0) { error("DPI header files are not the same"); } ok(1); 1; verilator-4.038/test_regress/t/t_class_copy.pl0000775000177100017500000000105313702133367021516 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_bsspace_bad.pl0000775000177100017500000000107113702133370022625 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_missing_bad.pl0000775000177100017500000000121413702133370022460 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_gen_missing.v"); lint( v_flags2 => ['+define+T_GEN_MISSING_BAD'], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_delay_func_bad.pl0000775000177100017500000000107413702133370022273 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_overzero.v0000664000177100017500000000634413702133370021733 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dout, // Inputs clk, rstn, dval0, dval1 ); input clk; input rstn; output wire [7:0] dout; input [7:0] dval0; input [7:0] dval1; wire [7:0] dbgsel_w = '0; tsub tsub (/*AUTOINST*/ // Outputs .dout (dout[7:0]), // Inputs .clk (clk), .rstn (rstn), .dval0 (dval0[7:0]), .dval1 (dval1[7:0]), .dbgsel_w (dbgsel_w[7:0])); endmodule module tsub (/*AUTOARG*/ // Outputs dout, // Inputs clk, rstn, dval0, dval1, dbgsel_w ); input clk; input rstn; input [7:0] dval0; input [7:0] dval1; input [7:0] dbgsel_w; output [7:0] dout; wire [7:0] dout = dout0 | dout1; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] dout0; // From sub0 of sub0.v wire [7:0] dout1; // From sub1 of sub1.v // End of automatics initial begin $write("*-* All Finished *-*\n"); $finish; end reg [7:0] dbgsel_msk; always_comb begin reg [7:0] mask; mask = 8'hff; dbgsel_msk = (dbgsel_w & mask); end // TODO this should optimize away, but presently does not because // V3Gate constifies then doesn't see all other input edges have disappeared reg [7:0] dbgsel; always @(posedge clk) begin if ((rstn == 0)) begin dbgsel <= 0; end else begin dbgsel <= dbgsel_msk; end end sub0 sub0 (/*AUTOINST*/ // Outputs .dout0 (dout0[7:0]), // Inputs .rstn (rstn), .clk (clk), .dval0 (dval0[7:0]), .dbgsel (dbgsel[7:0])); sub1 sub1 (/*AUTOINST*/ // Outputs .dout1 (dout1[7:0]), // Inputs .rstn (rstn), .clk (clk), .dval1 (dval1[7:0]), .dbgsel (dbgsel[7:0])); endmodule module sub0 ( /*AUTOARG*/ // Outputs dout0, // Inputs rstn, clk, dval0, dbgsel ); input rstn; input clk; input [7:0] dval0; input [7:0] dbgsel; output reg [7:0] dout0; reg [7:0] dbgsel_d1r; always_comb begin // verilator lint_off WIDTH if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin // verilator lint_on WIDTH dout0 = dval0; end else begin dout0 = 0; end end always @(posedge clk) begin if ((rstn == 0)) begin dbgsel_d1r <= 0; end else begin dbgsel_d1r <= dbgsel; end end endmodule module sub1 ( /*AUTOARG*/ // Outputs dout1, // Inputs rstn, clk, dval1, dbgsel ); input rstn; input clk; input [7:0] dval1; input [7:0] dbgsel; output reg [7:0] dout1; reg [7:0] dbgsel_d1r; always_comb begin if (((dbgsel_d1r >= 84) && (dbgsel_d1r < 95))) begin dout1 = dval1; end else begin dout1 = 0; end end always @(posedge clk) begin if ((rstn == 0)) begin dbgsel_d1r <= 0; end else begin dbgsel_d1r <= dbgsel; end end endmodule verilator-4.038/test_regress/t/t_math_div0.pl0000775000177100017500000000107413702133370021227 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--x-assign 0'], ); execute( ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_type_methods_bad.pl0000775000177100017500000000107313702133370023711 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename} ); ok(1); 1; verilator-4.038/test_regress/t/t_func_task_bad.pl0000775000177100017500000000107413702133370022137 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2011 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_future.pl0000775000177100017500000000110513702133370021652 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => [qw(--lint-only -Wfuture-FUTURE1 -Wfuture-FUTURE2)], ); ok(1); 1; verilator-4.038/test_regress/t/t_concat_large.v0000664000177100017500000000075113702133367021633 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg [32767:0] a; initial begin // verilator lint_off WIDTHCONCAT a = {32768{1'b1}}; // verilator lint_on WIDTHCONCAT if (a[32000] != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_ref_bad3.v0000664000177100017500000000054213702133370021517 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH module t(ref int bad_primary_ref /*AUTOARG*/); endmodule verilator-4.038/test_regress/t/t_order.pl0000775000177100017500000000105313702133370020464 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_type_bad2.v0000664000177100017500000000046013702133370022232 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam t = logic; // Bad localparam t2 = realtime; // Bad endmodule verilator-4.038/test_regress/t/t_bitsel_const_bad.pl0000775000177100017500000000107413702133367022660 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_first.pl0000775000177100017500000000115413702133370021537 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => [$Self->wno_unopthreads_for_few_cores()] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_loop.pl0000775000177100017500000000105313702133370021661 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_sformat_noopt.pl0000775000177100017500000000155013702133370023143 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_sys_sformat.v"); compile( # Avoid inlining our simple example, to make sure verilated.h works right verilator_flags2 => ["-O0"], ); if ($Self->cxx_version =~ /clang/) { skip("Known clang bug"); #Here: if (VL_UNLIKELY(VL_NEQ_W(12, __Vtemp1, vlSymsp->TOP__t.__PVT__str))) } else{ execute( check_finished => 1, ); } ok(1); 1; verilator-4.038/test_regress/t/t_real_param.pl0000775000177100017500000000105213702133370021453 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dist_untracked.pl0000775000177100017500000000352213702133370022357 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); my $root = ".."; my $Debug; if (!-r "$root/.git") { skip("Not in a git repository"); } else { ### Must trim output before and after our file list my %warns; my $prefix; my $summary; { my $status = `cd $root && git ls-files -o --exclude-standard`; print "ST $status\n" if $Debug; foreach my $file (sort split /\n/, $status) { next if $file =~ /nodist/; if (_has_tabs("$root/$file")) { $warns{$file} = "File not in git or .gitignore (with tabs): $file"; $summary = "Files untracked in git or .gitignore (with tabs):" } else { $warns{$file} = "File not in git or .gitignore: $file"; $summary ||= "Files untracked in git or .gitignore:" } } } if (keys %warns) { # First warning lists everything as that's shown in the driver summary error($summary." ",join(' ',sort keys %warns)); foreach my $file (sort keys %warns) { error($warns{$file}); } } } sub _has_tabs { my $filename = shift; my $contents = file_contents($filename); if ($filename =~ /\.out$/) { # Ignore golden files } elsif ($contents =~ /[\001\002\003\004\005\006]/) { # Ignore binrary files } elsif ($contents =~ /\t/) { return 1; } return 0; } ok(1); 1; verilator-4.038/test_regress/t/t_var_pins_scui.pl0000775000177100017500000000410113702133370022212 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_var_pinsizes.v"); compile( verilator_flags2 => ["-sc -pins-uint8 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], make_main => 0, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16;/x); } execute(); ok(1); 1; verilator-4.038/test_regress/t/t_initial_dlyass_bad.out0000664000177100017500000000112113702133370023354 0ustar wsnyderwsnyder%Warning-INITIALDLY: t/t_initial_dlyass.v:18:9: Delayed assignments (<=) in initial or final block : ... Suggest blocking assignments (=) 18 | a <= 22; | ^~ ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. %Warning-INITIALDLY: t/t_initial_dlyass.v:19:9: Delayed assignments (<=) in initial or final block : ... Suggest blocking assignments (=) 19 | b <= 33; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_math_repl.v0000664000177100017500000000603313702133370021156 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [63:0] rf; reg [63:0] rf2; reg [63:0] biu; reg b; always @* begin rf[63:32] = biu[63:32] & {32{b}}; rf[31:0] = {32{b}}; rf2 = rf; rf2[31:0] = ~{32{b}}; end reg [31:0] src1, src0, sr, mask; wire [31:0] dualasr = ((| src1[31:4]) ? {{16{src0[31]}}, {16{src0[15]}}} : ( ( sr & {2{mask[31:16]}}) | ( {{16{src0[31]}}, {16{src0[15]}}} & {2{~mask[31:16]}}))); wire [31:0] sl_mask = (32'hffffffff << src1[4:0]); wire [31:0] sr_mask = {sl_mask[0], sl_mask[1], sl_mask[2], sl_mask[3], sl_mask[4], sl_mask[5], sl_mask[6], sl_mask[7], sl_mask[8], sl_mask[9], sl_mask[10], sl_mask[11], sl_mask[12], sl_mask[13], sl_mask[14], sl_mask[15], sl_mask[16], sl_mask[17], sl_mask[18], sl_mask[19], sl_mask[20], sl_mask[21], sl_mask[22], sl_mask[23], sl_mask[24], sl_mask[25], sl_mask[26], sl_mask[27], sl_mask[28], sl_mask[29], sl_mask[30], sl_mask[31]}; wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}}; wire [1:0] w = {2{b}}; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep); `endif if (cyc==1) begin biu <= 64'h12451282_abadee00; b <= 1'b0; src1 <= 32'h00000001; src0 <= 32'h9a4f1235; sr <= 32'h0f19f567; mask <= 32'h7af07ab4; end if (cyc==2) begin biu <= 64'h12453382_abad8801; b <= 1'b1; if (rf != 64'h0) $stop; if (rf2 != 64'h00000000ffffffff) $stop; src1 <= 32'h0010000f; src0 <= 32'h028aa336; sr <= 32'h42ad0377; mask <= 32'h1ab3b906; if (dualasr != 32'h8f1f7060) $stop; if (sl_mask != 32'hfffffffe) $stop; if (sr_mask != 32'h7fffffff) $stop; if (widerep != '0) $stop; end if (cyc==3) begin biu <= 64'h12422382_77ad8802; b <= 1'b1; if (rf != 64'h12453382ffffffff) $stop; if (rf2 != 64'h1245338200000000) $stop; src1 <= 32'h0000000f; src0 <= 32'h5c158f71; sr <= 32'h7076c40a; mask <= 32'h33eb3d44; if (dualasr != 32'h0000ffff) $stop; if (sl_mask != 32'hffff8000) $stop; if (sr_mask != 32'h0001ffff) $stop; if (widerep != '1) $stop; end if (cyc==4) begin if (rf != 64'h12422382ffffffff) $stop; if (rf2 != 64'h1242238200000000) $stop; if (dualasr != 32'h3062cc1e) $stop; if (sl_mask != 32'hffff8000) $stop; if (sr_mask != 32'h0001ffff) $stop; $write("*-* All Finished *-*\n"); if (widerep != '1) $stop; $finish; end end end endmodule verilator-4.038/test_regress/t/t_lint_comb_use.pl0000775000177100017500000000105413702133370022174 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only --bbox-sys"], ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_concat3.v0000664000177100017500000000332013702133367021370 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off LITENDIAN */ module some_module ( input wrclk ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (wrclk) some_other_state <= 0; end endmodule `define BROKEN module t1( input [-12:-9] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( `ifdef BROKEN .wrclk (i_clks[-12]) `else .wrclk (i_clk1) `endif ); endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [-12:-9] the_clks; logic data_q; assign the_clks[-12] = i_clk1; assign the_clks[-11] = i_clk2; assign the_clks[-10] = i_clk1; assign the_clks[-9] = i_clk0; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk1), .i_clk2 (clk2), .i_data (data_in) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_vcmarker_bad.v0000664000177100017500000000101213702133370022641 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); <<<<<<< HEAD // Intentional test: This conflict marker should be here initial $display("Hello"); ======= // Intentional test: This conflict marker should be here initial $display("Goodbye"); >>>>>>> MERGE // Intentional test: This conflict marker should be here endmodule verilator-4.038/test_regress/t/t_param_func.v0000664000177100017500000000147013702133370021316 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This test examines Verilator against paramter definition with functions. // Particularly the function takes in argument which is multi-dimentional. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Roland Kruse and Jie Xu. // SPDX-License-Identifier: CC0-1.0 module test#( parameter size = 4, parameter p = sum({32'h1,32'h2,32'h3,32'h4}, size)) (input clk, input logic sel, output [p:0] res); logic [p:0] cc = 'h45; assign res = sel ? cc : {(p+1){1'b1}}; function integer sum; input [3:0][31:0] values; input int size; sum = 0; begin for (int i = 0; i < size; i ++) sum += values[i]; end endfunction endmodule verilator-4.038/test_regress/t/t_param_noval_bad.out0000664000177100017500000000311113702133370022644 0ustar wsnyderwsnyder%Error: t/t_param_noval_bad.v:7:22: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'P' : ... In instance t 7 | module t #(parameter P); | ^ %Warning-WIDTH: t/t_param_noval_bad.v:10:7: Logical Operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. : ... In instance t 10 | for (j=0; P; j++) | ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: t/t_param_noval_bad.v:10:7: Non-genvar used in generate for: 'j' : ... In instance t 10 | for (j=0; P; j++) | ^~~ %Error: t/t_param_noval_bad.v:10:7: Loop unrolling failed. : ... In instance t 10 | for (j=0; P; j++) | ^~~ %Error-UNSUPPORTED: t/t_param_noval_bad.v:10:7: Unsupported: Can't unroll generate for; Unable to unroll loop : ... In instance t 10 | for (j=0; P; j++) | ^~~ %Error: t/t_param_noval_bad.v:10:7: For loop doesn't have genvar index, or is malformed : ... In instance t 10 | for (j=0; P; j++) | ^~~ %Error: Internal Error: t/t_param_noval_bad.v:10:7: ../V3Param.cpp:#: GENFOR should have been wrapped in BEGIN : ... In instance t 10 | for (j=0; P; j++) | ^~~ verilator-4.038/test_regress/t/t_sys_readmem_assoc_bad.pl0000775000177100017500000000111313702133370023654 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_pinsizes.v0000664000177100017500000000330013702133370021711 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Also check that SystemC is ordering properly // verilator lint_on IMPERFECTSCH module t (/*AUTOARG*/ // Outputs o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, obv1_vlt, obv16_vlt, // Inputs clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16, ibv1_vlt, ibv16_vlt ); input clk; input i1; input [7:0] i8; input [15:0] i16; input [31:0] i32; input [63:0] i64; input [64:0] i65; input [127:0] i128; input [512:0] i513; input i1a2 [1:0]; input [93:0] i94a3 [2:0]; output logic o1; output logic [7:0] o8; output logic [15:0] o16; output logic [31:0] o32; output logic [63:0] o64; output logic [64:0] o65; output logic [127:0] o128; output logic [512:0] o513; output logic o1a2 [1:0]; output logic [93:0] o94a3 [2:0]; input [0:0] ibv1 /*verilator sc_bv*/; input [15:0] ibv16 /*verilator sc_bv*/; input [0:0] ibv1_vlt; input [15:0] ibv16_vlt; output logic [0:0] obv1 /*verilator sc_bv*/; output logic [15:0] obv16 /*verilator sc_bv*/; output logic [0:0] obv1_vlt; output logic [15:0] obv16_vlt; always @ (posedge clk) begin o1 <= i1; o8 <= i8; o16 <= i16; o32 <= i32; o64 <= i64; o65 <= i65; o128 <= i128; o513 <= i513; obv1 <= ibv1; obv16 <= ibv16; obv1_vlt <= ibv1_vlt; obv16_vlt <= ibv16_vlt; o1a2 <= i1a2; o94a3 <= i94a3; end endmodule verilator-4.038/test_regress/t/t_sys_writemem_b.gold1.mem0000664000177100017500000000014213702133370023544 0ustar wsnyderwsnyder000010 000011 000100 000101 000110 000111 010000 000000 000000 000000 010100 010101 000000 000000 verilator-4.038/test_regress/t/t_inst_recurse2_bad.out0000664000177100017500000000047213702133370023143 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_inst_recurse2_bad.v:18:8: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped' : ... In instance t.looped.looped 18 | module looped ( ); | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_asvar_bad.pl0000775000177100017500000000110113702133370023305 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_if_swap.v0000664000177100017500000000062713702133370020636 0ustar wsnyderwsnydermodule t (/*AUTOARG*/ // Inputs clk ); input clk; integer f; always @(posedge clk) begin if (!$feof(f)) begin $display("Doing stuff with file."); end // Commenting out these two lines fixes the fault else begin end if (!$feof(f)) begin end else begin $display("Not doing stuff with file."); end end endmodule verilator-4.038/test_regress/t/t_lint_pindup_bad.v0000664000177100017500000000120613702133370022333 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output wire o, input wire i, input wire i2 ); sub #(, // Not found .NEXIST(1), // Not found .P(2), .P(3)) // Dup sub (.o(o), .i(i), .i(i2), // Dup .nexist(i2) // Not found ); endmodule module sub #(parameter P=1, parameter EXIST=9) ( output wire o, input wire i, input wire exists ); assign o = ~i; endmodule verilator-4.038/test_regress/t/t_interface_gen7.pl0000775000177100017500000000106013702133370022227 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_only.pl0000775000177100017500000000152413702133370021363 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint(); foreach my $file (glob("$Self->{obj_dir}/*")) { next if $file =~ /\.log/; # Made by driver.pl, not Verilator sources next if $file =~ /\.status/; # Made by driver.pl, not Verilator sources next if $file =~ /\.gcda/; # Made by gcov, not Verilator sources error("%Error: Created $file, but --lint-only shouldn't create files"); } ok(1); 1; verilator-4.038/test_regress/t/t_interface_modport_dir_bad.pl0000775000177100017500000000120113702133370024514 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, bug1622"); scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_bench_mux4k.v0000664000177100017500000001073313702133367021422 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 // // This implements a 4096:1 mux via two stages of 64:1 muxing. // change these two parameters to see the speed differences //`define DATA_WIDTH 12 //`define MUX2_SIZE 32 `define DATA_WIDTH 2 `define MUX2_SIZE 8 // if you change these, then the testbench will break `define ADDR_WIDTH 12 `define MUX1_SIZE 64 // Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64 module t (/*AUTOARG*/ // Inputs clk ); input clk; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v // End of automatics reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai; reg [`ADDR_WIDTH-1:0] addr; // Mux: takes in addr and datai and outputs datao mux4096 mux4096 (/*AUTOINST*/ // Outputs .datao (datao[`DATA_WIDTH-1:0]), // Inputs .datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), .addr (addr[`ADDR_WIDTH-1:0])); // calculate what the answer should be from datai. This is bit // tricky given the way datai gets sliced. datai is in bit // planes where all the LSBs are contiguous and then the next bit. reg [`DATA_WIDTH-1:0] datao_check; integer j; always @(datai or addr) begin for(j=0;j<`DATA_WIDTH;j=j+1) begin /* verilator lint_off WIDTH */ datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr); /* verilator lint_on WIDTH */ end end // Run the test loop. This just increments the address integer i, result; always @ (posedge clk) begin // initial the input data with random values if (addr == 0) begin result = 1; datai = 0; for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin /* verilator lint_off WIDTH */ datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); /* verilator lint_on WIDTH */ end end addr <= addr + 1; if (datao_check != datao) begin result = 0; $stop; end `ifdef TEST_VERBOSE $write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao); `endif // only run the first 10 addresses for now if (addr > 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module mux4096 (input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai, input [`ADDR_WIDTH-1:0] addr, output [`DATA_WIDTH-1:0] datao ); // DATA_WIDTH instantiations of mux4096_1bit mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] (.addr(addr), .datai(datai), .datao(datao) ); endmodule module mux4096_1bit (input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai, input [`ADDR_WIDTH-1:0] addr, output datao ); // address decoding wire [3:0] A = (4'b1) << addr[1:0]; wire [3:0] B = (4'b1) << addr[3:2]; wire [3:0] C = (4'b1) << addr[5:4]; wire [3:0] D = (4'b1) << addr[7:6]; wire [3:0] E = (4'b1) << addr[9:8]; wire [3:0] F = (4'b1) << addr[11:10]; wire [`MUX2_SIZE-1:0] data0; // DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64 // first stage of 64:1 muxing mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0] (.A(A), .B(B), .C(C), .datai(datai), .datao(data0)); // DATA_WIDTH*MUX2_SIZE instantiations of mux64 // second stage of 64:1 muxing mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2 (.A(D), .B(E), .C(F), .datai(data0), .datao(datao)); endmodule module mux64 #(parameter MUX_SIZE=64) (input [3:0] A, input [3:0] B, input [3:0] C, input [MUX_SIZE-1:0] datai, output datao ); wire [63:0] colSelA = { 16{ A[3:0] }}; wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}}; wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}}; wire [MUX_SIZE-1:0] data_bus; // Note each of these becomes a separate wire. //.colSelA(colSelA[MUX_SIZE-1:0]), //.colSelB(colSelB[MUX_SIZE-1:0]), //.colSelC(colSelC[MUX_SIZE-1:0]), drv drv[MUX_SIZE-1:0] (.colSelA(colSelA[MUX_SIZE-1:0]), .colSelB(colSelB[MUX_SIZE-1:0]), .colSelC(colSelC[MUX_SIZE-1:0]), .datai(datai), .datao(data_bus) ); assign datao = |data_bus; endmodule module drv (input colSelA, input colSelB, input colSelC, input datai, output datao ); assign datao = colSelC & colSelB & colSelA & datai; endmodule verilator-4.038/test_regress/t/t_interface_ref_trace.v0000664000177100017500000000436013702133370023156 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 // Test for trace file interface aliasing typedef struct packed { integer val100; integer val200; } struct_t; interface ifc (input logic clk, input integer cyc); integer value; struct_t the_struct; endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; ifc intf_1(.*); ifc intf_2(.*); always @(*) begin intf_1.value = cyc + 1; intf_2.value = cyc + 2; end sub_struct s1 (.intf_for_struct(intf_1)); sub_struct s2 (.intf_for_struct(intf_2)); sub_check c1 (.intf_for_check(intf_1)); sub_check c2 (.intf_for_check(intf_2)); sub_all a (.intf_one(intf_1), .intf_two(intf_2)); // Intentionally longer scope name sub_all abcdefghijklmnopqrstuvwxyz (.intf_one(intf_2), .intf_two(intf_1)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (intf_1.value != 21) $stop; if (intf_2.value != 22) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub_struct ( ifc intf_for_struct ); always @(*) begin intf_for_struct.the_struct.val100 = intf_for_struct.value + 100; intf_for_struct.the_struct.val200 = intf_for_struct.value + 200; end endmodule module sub_check ( ifc intf_for_check ); `ifdef NO_INLINE_A //verilator no_inline_module `endif always @(posedge intf_for_check.clk) begin if (intf_for_check.the_struct.val100 != intf_for_check.value + 100) $stop; if (intf_for_check.the_struct.val200 != intf_for_check.value + 200) $stop; end endmodule module sub_all ( ifc intf_one, ifc intf_two ); `ifdef NO_INLINE_B //verilator no_inline_module `endif ifc intf_in_sub_all ( .clk(intf_one.clk), .cyc(intf_one.cyc) ); assign intf_in_sub_all.value = intf_one.value + 1000; sub_check ac1 (.intf_for_check(intf_one)); sub_check ac2 (.intf_for_check(intf_two)); sub_struct as3 (.intf_for_struct(intf_in_sub_all)); sub_check ac3 (.intf_for_check(intf_in_sub_all)); endmodule verilator-4.038/test_regress/t/t_sys_file_basic_mcd.out0000664000177100017500000000006513702133370023345 0ustar wsnyderwsnyderSean Connery was the best Bond. *-* All Finished *-* verilator-4.038/test_regress/t/t_flag_main_sc_bad.pl0000775000177100017500000000130513702133370022561 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ['--exe --build --main --sc'], verilator_make_cmake => 0, verilator_make_gmake => 0, make_main => 0, fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen_noinl.pl0000775000177100017500000000115713702133370023346 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_cat_reopen.out0000664000177100017500000001745013702133370023047 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sat Feb 23 20:18:07 2013 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # 1$ #1 0$ #2 b00000000000000000000000000000010 # 1$ #3 0$ #4 b00000000000000000000000000000011 # 1$ #5 0$ #6 b00000000000000000000000000000100 # 1$ #7 0$ #8 b00000000000000000000000000000101 # 1$ #9 0$ #10 b00000000000000000000000000000110 # 1$ #11 0$ #12 b00000000000000000000000000000111 # 1$ #13 0$ #14 b00000000000000000000000000001000 # 1$ #15 0$ #16 b00000000000000000000000000001001 # 1$ #17 0$ #18 b00000000000000000000000000001010 # 1$ #19 0$ #20 b00000000000000000000000000001011 # 1$ #21 0$ #22 b00000000000000000000000000001100 # 1$ #23 0$ #24 b00000000000000000000000000001101 # 1$ #25 0$ #26 b00000000000000000000000000001110 # 1$ #27 0$ #28 b00000000000000000000000000001111 # 1$ #29 0$ #30 b00000000000000000000000000010000 # 1$ #31 0$ #32 b00000000000000000000000000010001 # 1$ #33 0$ #34 b00000000000000000000000000010010 # 1$ #35 0$ #36 b00000000000000000000000000010011 # 1$ #37 0$ #38 b00000000000000000000000000010100 # 1$ #39 0$ #40 b00000000000000000000000000010101 # 1$ #41 0$ #42 b00000000000000000000000000010110 # 1$ #43 0$ #44 b00000000000000000000000000010111 # 1$ #45 0$ #46 b00000000000000000000000000011000 # 1$ #47 0$ #48 b00000000000000000000000000011001 # 1$ #49 0$ #50 b00000000000000000000000000011010 # 1$ #51 0$ #52 b00000000000000000000000000011011 # 1$ #53 0$ #54 b00000000000000000000000000011100 # 1$ #55 0$ #56 b00000000000000000000000000011101 # 1$ #57 0$ #58 b00000000000000000000000000011110 # 1$ #59 0$ #60 b00000000000000000000000000011111 # 1$ #61 0$ #62 b00000000000000000000000000100000 # 1$ #63 0$ #64 b00000000000000000000000000100001 # 1$ #65 0$ #66 b00000000000000000000000000100010 # 1$ #67 0$ #68 b00000000000000000000000000100011 # 1$ #69 0$ #70 b00000000000000000000000000100100 # 1$ #71 0$ #72 b00000000000000000000000000100101 # 1$ #73 0$ #74 b00000000000000000000000000100110 # 1$ #75 0$ #76 b00000000000000000000000000100111 # 1$ #77 0$ #78 b00000000000000000000000000101000 # 1$ #79 0$ #80 b00000000000000000000000000101001 # 1$ #81 0$ #82 b00000000000000000000000000101010 # 1$ #83 0$ #84 b00000000000000000000000000101011 # 1$ #85 0$ #86 b00000000000000000000000000101100 # 1$ #87 0$ #88 b00000000000000000000000000101101 # 1$ #89 0$ #90 b00000000000000000000000000101110 # 1$ #91 0$ #92 b00000000000000000000000000101111 # 1$ #93 0$ #94 b00000000000000000000000000110000 # 1$ #95 0$ #96 b00000000000000000000000000110001 # 1$ #97 0$ #98 b00000000000000000000000000110010 # 1$ #99 0$ #100 b00000000000000000000000000110011 # 1$ #101 0$ #102 b00000000000000000000000000110100 # 1$ #103 0$ #104 b00000000000000000000000000110101 # 1$ #105 0$ #106 b00000000000000000000000000110110 # 1$ #107 0$ #108 b00000000000000000000000000110111 # 1$ #109 0$ #110 b00000000000000000000000000111000 # 1$ #111 0$ #112 b00000000000000000000000000111001 # 1$ #113 0$ #114 b00000000000000000000000000111010 # 1$ #115 0$ #116 b00000000000000000000000000111011 # 1$ #117 0$ #118 b00000000000000000000000000111100 # 1$ #119 0$ #120 b00000000000000000000000000111101 # 1$ #121 0$ #122 b00000000000000000000000000111110 # 1$ #123 0$ #124 b00000000000000000000000000111111 # 1$ #125 0$ #126 b00000000000000000000000001000000 # 1$ #127 0$ #128 b00000000000000000000000001000001 # 1$ #129 0$ #130 b00000000000000000000000001000010 # 1$ #131 0$ #132 b00000000000000000000000001000011 # 1$ #133 0$ #134 b00000000000000000000000001000100 # 1$ #135 0$ #136 b00000000000000000000000001000101 # 1$ #137 0$ #138 b00000000000000000000000001000110 # 1$ #139 0$ #140 b00000000000000000000000001000111 # 1$ #141 0$ #142 b00000000000000000000000001001000 # 1$ #143 0$ #144 b00000000000000000000000001001001 # 1$ #145 0$ #146 b00000000000000000000000001001010 # 1$ #147 0$ #148 b00000000000000000000000001001011 # 1$ #149 0$ #150 b00000000000000000000000001001100 # 1$ #151 0$ #152 b00000000000000000000000001001101 # 1$ #153 0$ #154 b00000000000000000000000001001110 # 1$ #155 0$ #156 b00000000000000000000000001001111 # 1$ #157 0$ #158 b00000000000000000000000001010000 # 1$ #159 0$ #160 b00000000000000000000000001010001 # 1$ #161 0$ #162 b00000000000000000000000001010010 # 1$ #163 0$ #164 b00000000000000000000000001010011 # 1$ #165 0$ #166 b00000000000000000000000001010100 # 1$ #167 0$ #168 b00000000000000000000000001010101 # 1$ #169 0$ #170 b00000000000000000000000001010110 # 1$ #171 0$ #172 b00000000000000000000000001010111 # 1$ #173 0$ #174 b00000000000000000000000001011000 # 1$ #175 0$ #176 b00000000000000000000000001011001 # 1$ #177 0$ #178 b00000000000000000000000001011010 # 1$ #179 0$ #180 b00000000000000000000000001011011 # 1$ #181 0$ #182 b00000000000000000000000001011100 # 1$ #183 0$ #184 b00000000000000000000000001011101 # 1$ #185 0$ #186 b00000000000000000000000001011110 # 1$ #187 0$ #188 b00000000000000000000000001011111 # 1$ #189 0$ #190 b00000000000000000000000001100000 # 1$ #191 0$ #192 b00000000000000000000000001100001 # 1$ #193 0$ #194 b00000000000000000000000001100010 # 1$ #195 0$ #196 b00000000000000000000000001100011 # 1$ #197 0$ #198 b00000000000000000000000001100100 # 1$ #199 0$ #200 b00000000000000000000000001100101 # 1$ #201 0$ #202 b00000000000000000000000001100110 # 1$ #203 0$ #204 b00000000000000000000000001100111 # 1$ #205 0$ #206 b00000000000000000000000001101000 # 1$ #207 0$ #208 b00000000000000000000000001101001 # 1$ #209 0$ #210 b00000000000000000000000001101010 # 1$ #211 0$ #212 b00000000000000000000000001101011 # 1$ #213 0$ #214 b00000000000000000000000001101100 # 1$ #215 0$ #216 b00000000000000000000000001101101 # 1$ #217 0$ #218 b00000000000000000000000001101110 # 1$ #219 0$ #220 b00000000000000000000000001101111 # 1$ #221 0$ #222 b00000000000000000000000001110000 # 1$ #223 0$ #224 b00000000000000000000000001110001 # 1$ #225 0$ #226 b00000000000000000000000001110010 # 1$ #227 0$ #228 b00000000000000000000000001110011 # 1$ #229 0$ #230 b00000000000000000000000001110100 # 1$ #231 0$ #232 b00000000000000000000000001110101 # 1$ #233 0$ #234 b00000000000000000000000001110110 # 1$ #235 0$ #236 b00000000000000000000000001110111 # 1$ #237 0$ #238 b00000000000000000000000001111000 # 1$ #239 0$ #240 b00000000000000000000000001111001 # 1$ #241 0$ #242 b00000000000000000000000001111010 # 1$ #243 0$ #244 b00000000000000000000000001111011 # 1$ #245 0$ #246 b00000000000000000000000001111100 # 1$ #247 0$ #248 b00000000000000000000000001111101 # 1$ #249 0$ #250 b00000000000000000000000001111110 # 1$ #251 0$ #252 b00000000000000000000000001111111 # 1$ #253 0$ #254 b00000000000000000000000010000000 # 1$ #255 0$ #256 b00000000000000000000000010000001 # 1$ #257 0$ #258 b00000000000000000000000010000010 # 1$ #259 0$ #260 b00000000000000000000000010000011 # 1$ #261 0$ #262 b00000000000000000000000010000100 # 1$ #263 0$ #264 b00000000000000000000000010000101 # 1$ #265 0$ #266 b00000000000000000000000010000110 # 1$ #267 0$ #268 b00000000000000000000000010000111 # 1$ #269 0$ #270 b00000000000000000000000010001000 # 1$ #271 0$ #272 b00000000000000000000000010001001 # 1$ #273 0$ #274 b00000000000000000000000010001010 # 1$ #275 0$ #276 b00000000000000000000000010001011 # 1$ #277 0$ #278 b00000000000000000000000010001100 # 1$ #279 0$ #280 b00000000000000000000000010001101 # 1$ #281 0$ #282 b00000000000000000000000010001110 # 1$ #283 0$ #284 b00000000000000000000000010001111 # 1$ #285 0$ #286 b00000000000000000000000010010000 # 1$ #287 0$ #288 b00000000000000000000000010010001 # 1$ #289 0$ #290 b00000000000000000000000010010010 # 1$ #291 0$ #292 b00000000000000000000000010010011 # 1$ #293 0$ #294 b00000000000000000000000010010100 # 1$ #295 0$ #296 b00000000000000000000000010010101 # 1$ #297 0$ #298 b00000000000000000000000010010110 # 1$ #299 0$ verilator-4.038/test_regress/t/t_bench_mux4k.pl0000775000177100017500000000120013702133367021560 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["--stats", $Self->wno_unopthreads_for_few_cores()] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_dupdef.v0000664000177100017500000000057013702133370021151 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define DUP fred `define DUP barney `define DUPP paramed(x) (x) `define DUPP paramed(x,z) (x*z) initial $stop; // Should have failed endmodule verilator-4.038/test_regress/t/t_unroll_complexcond.pl0000775000177100017500000000105313702133370023257 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_const_packed_struct_bad2.pl0000775000177100017500000000107313702133370025317 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2017 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_dupdef.pl0000775000177100017500000000105013702133370021314 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ["-Wno-REDEFMACRO"], ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_first_a.v0000664000177100017500000000150713702133370021670 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_inst_first_a (/*AUTOARG*/ // Outputs o_w5, o_w5_d1r, o_w40, o_w104, // Inputs clk, i_w5, i_w40, i_w104 ); input clk; input [4:0] i_w5; output [4:0] o_w5; output [4:0] o_w5_d1r; input [39:0] i_w40; output [39:0] o_w40; input [104:0] i_w104; output [104:0] o_w104; wire [4:0] o_w5 = i_w5; wire [39:0] o_w40 = i_w40; wire [104:0] o_w104 = i_w104; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [4:0] o_w5_d1r; // End of automatics always @ (posedge clk) begin o_w5_d1r <= i_w5; end endmodule verilator-4.038/test_regress/t/t_display_bad.pl0000775000177100017500000000107113702133370021624 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlcov_data_b.dat0000664000177100017500000000026713366724403022145 0ustar wsnyderwsnyder# SystemC::Coverage-3 C 'CoverPoint2ffile1.sphl159' 10 C 'CoverPoint3ffile1.sphl159' 0 C 'CoverPoint4ffile1.sphl159' 1 C 'CoverPoint5ffile1.sphl159' 9 verilator-4.038/test_regress/t/t_delay_func_bad.out0000664000177100017500000000063513702133370022466 0ustar wsnyderwsnyder%Error: t/t_delay_func_bad.v:10:8: Delays are not legal in functions. Suggest use a task (IEEE 1800-2017 13.4.4) : ... In instance t 10 | #1 $stop; | ^ %Error: t/t_delay_func_bad.v:23:8: Delays are not legal in final blocks (IEEE 1800-2017 9.2.3) : ... In instance t 23 | #1; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_top_bad.out0000664000177100017500000000047713702133370023203 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_interface_top_bad.v:17:19: Unsupported: Interfaced port on top level module 17 | ifc.counter_mp c_data | ^~~~~~ %Error: t/t_interface_top_bad.v:17:4: Parent cell's interface is not found: 'ifc' 17 | ifc.counter_mp c_data | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_input_eq_bad.out0000664000177100017500000000026513702133370023226 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_lint_input_eq_bad.v:10:15: Unsupported: Default value on module input: 'i2' 10 | input wire i2 = i | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_type.pl0000775000177100017500000000105313702133370020332 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_pullvec_bad.out0000664000177100017500000000131113702133370022675 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_tri_pullvec_bad.v:13:13: Unsupported: Conflicting pull directions. : ... In instance t 13 | pulldown p1 (w[1]); | ^~ t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p0 (w[0]); | ^~ %Error-UNSUPPORTED: t/t_tri_pullvec_bad.v:14:13: Unsupported: Conflicting pull directions. : ... In instance t 14 | pulldown p2 (w[2]); | ^~ t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p0 (w[0]); | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_delay_stmtdly_bad.out0000664000177100017500000000265113702133370023233 0ustar wsnyderwsnyder%Warning-ASSIGNDLY: t/t_delay.v:23:13: Unsupported: Ignoring delay on this assignment/primitive. 23 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1; | ^~~~~~~~~~~~~~~~~~ ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message. %Warning-ASSIGNDLY: t/t_delay.v:28:19: Unsupported: Ignoring delay on this assignment/primitive. 28 | dly0 <= #0 32'h11; | ^ %Warning-ASSIGNDLY: t/t_delay.v:31:19: Unsupported: Ignoring delay on this assignment/primitive. 31 | dly0 <= #0.12 dly0 + 32'h12; | ^~~~ %Warning-ASSIGNDLY: t/t_delay.v:39:25: Unsupported: Ignoring delay on this assignment/primitive. 39 | dly0 <= #(dly_s.dly) 32'h55; | ^ %Warning-STMTDLY: t/t_delay.v:44:11: Unsupported: Ignoring delay on this delayed statement. : ... In instance t 44 | #100 $finish; | ^~~ %Warning-UNUSED: t/t_delay.v:21:12: Signal is not used: 'dly_s' : ... In instance t 21 | dly_s_t dly_s; | ^~~~~ %Warning-BLKSEQ: t/t_delay.v:38:20: Blocking assignments (=) in sequential (flop or latch) block : ... Suggest delayed assignments (<=) 38 | dly_s.dly = 55; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_mod_dup_ign.v0000664000177100017500000000074213702133370021470 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub (); endmodule module sub; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule // verilator lint_off MODDUP module sub; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_overcmp.pl0000775000177100017500000000105313702133370021674 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_member_bad.out0000664000177100017500000000051713702133367023016 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_member_bad.v:11:20: Unsupported: class extends 11 | class Cls2 extends Base1; | ^~~~~ %Error: t/t_class_member_bad.v:11:20: Found definition of 'Base1' as a CLASS but expected a variable 11 | class Cls2 extends Base1; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_mem_multi_ref_bad.out0000664000177100017500000000440213702133370023175 0ustar wsnyderwsnyder%Error: t/t_mem_multi_ref_bad.v:15:11: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... In instance t 15 | dimn[1:0] = 0; | ^ %Error: t/t_mem_multi_ref_bad.v:15:11: Extracting 2 bits from only 1 bit number : ... In instance t 15 | dimn[1:0] = 0; | ^ %Error: t/t_mem_multi_ref_bad.v:16:14: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... In instance t 16 | dim0[1][1] = 0; | ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:16:14: Selection index out of range: 1:1 outside 0:0 : ... In instance t 16 | dim0[1][1] = 0; | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: t/t_mem_multi_ref_bad.v:17:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... In instance t 17 | dim1[1][1][1] = 0; | ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:17:17: Selection index out of range: 1:1 outside 0:0 : ... In instance t 17 | dim1[1][1][1] = 0; | ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:19:19: Selection index out of range: 1 outside 0:0 : ... In instance t 19 | dim2[0 +: 1][1] = 0; | ^ %Error: t/t_mem_multi_ref_bad.v:23:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... In instance t 23 | dim0nv[1][1] = 0; | ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:23:16: Selection index out of range: 1:1 outside 0:0 : ... In instance t 23 | dim0nv[1][1] = 0; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_unused.v0000664000177100017500000000254113702133370021534 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Outputs out, // Inputs in ); input in; // inputs don't get flagged as undriven output out; // outputs don't get flagged as unused sub sub (); // Check we don't warn about unused UDP signals udp_mux2 udpsub (out, in, in, in); // Check ignoreds mark as used reg sysused; initial $bboxed(sysused); // Check file IO. The fopen is the "driver" all else a usage. integer infile; integer outfile; initial begin outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w"); $fwrite(outfile, "1\n"); $fclose(outfile); infile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "r"); if ($fgetc(infile) != "1") begin end end wire _unused_ok; endmodule module sub; wire pub /*verilator public*/; // Ignore publics localparam THREE = 3; endmodule primitive udp_mux2 (q, a, b, s); output q; input a, b, s; table //a b s : out 1 ? 0 : 1 ; 0 ? 0 : 0 ; ? 1 1 : 1 ; ? 0 1 : 0 ; 0 0 x : 0 ; 1 1 x : 1 ; endtable endprimitive verilator-4.038/test_regress/t/t_sys_readmem_bad_addr.out0000664000177100017500000000014113702133370023647 0ustar wsnyderwsnyder%Error: t/t_sys_readmem_bad_addr.mem:9: $readmem file address beyond bounds of array Aborting... verilator-4.038/test_regress/t/t_vlcov_info.out0000664000177100017500000000007213702133370021706 0ustar wsnyderwsnyderTN:verilator_coverage SF:file1.sp DA:159,53 end_of_record verilator-4.038/test_regress/t/t_interface_gen6.v0000664000177100017500000000213113702133370022055 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug1001 interface intf #(parameter PARAM = 0) (); logic val; endinterface module t(); generate if (1) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '0; end endgenerate generate begin if (1) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '0; end end endgenerate generate begin begin if (1) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '0; end end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_unconnected_bad.v0000664000177100017500000000043013702133370022311 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `unconnected_drive `unconnected_drive pull2 module t; endmodule verilator-4.038/test_regress/t/t_assert_comp_bad.pl0000775000177100017500000000126113702133367022505 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], vcs_flags2 => ['-assert svaext'], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_detectarray_2.v0000664000177100017500000000157613702133370021742 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Simple test of unoptflat // // This should trigger the DETECTARRAY error like t_detectarray_1.v, but in // fact it casuses a broken link error. The only difference is that the struct // is defined using a constant rather than a localparam. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { logic [1:0] id; } context_t; context_t tsb; assign tsb.id = {tsb.id[0], clk}; initial begin tsb.id = 0; end always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("tsb.id = %x\n", tsb.id); `endif if (tsb.id[1] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_param_concat.pl0000775000177100017500000000113213702133370021776 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--Wno-WIDTHCONCAT"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen3_collision.pl0000775000177100017500000000120513702133370024277 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen3.v"); compile( verilator_flags2 => ["--debug-collision"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_cond_clean.v0000664000177100017500000000453113702133370022302 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] cnt = crc[3:0]; wire [6:0] decr = crc[14:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] next; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .next (next[3:0]), // Inputs .cnt (cnt[3:0]), .decr (decr[6:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, next}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h7cd85c944415d2ef if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs next, // Inputs cnt, decr ); input [3:0] cnt; input signed [6:0] decr; output reg [3:0] next; always_comb begin reg signed [6:0] tmp; tmp = 0; // verilator lint_off WIDTH tmp = ($signed({1'b0, cnt}) - decr); // verilator lint_on WIDTH if ((tmp > 15)) begin next = 15; end else if ((tmp < 0)) begin next = 0; end else begin next = tmp[3:0]; end end endmodule verilator-4.038/test_regress/t/t_assert_synth_full.pl0000775000177100017500000000144613702133367023135 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_synth.v"); compile( v_flags2 => ['+define+FAILING_FULL +define+ATTRIBUTES'], verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], ); execute( check_finished => 0, fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_rev.pl0000775000177100017500000000105313702133367021351 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_package_verb.v0000664000177100017500000000101213702133370021604 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug474 package verb_pkg; typedef enum int {VERB_I, VERB_W} Verb_t; Verb_t verb = VERB_I; string message = " "; endpackage module t; import verb_pkg::*; string message = "*x*"; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_udp_bad.out0000664000177100017500000000137213702133370021144 0ustar wsnyderwsnyder%Warning-PINMISSING: t/t_udp_bad.v:10:10: Cell has missing pin: 'c_bad' 10 | udp_x x (a, b); | ^ ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_udp_bad.v:14:18: Pin is not an in/out/inout/interface: 'a_bad' 14 | primitive udp_x (a_bad, b, c_bad); | ^~~~~ %Error: t/t_udp_bad.v:10:13: Pin not found: '__pinNumber1' 10 | udp_x x (a, b); | ^ %Error: t/t_udp_bad.v:15:9: Only inputs and outputs are allowed in udp modules 15 | tri a_bad; | ^~~~~ %Error: t/t_udp_bad.v:17:11: Multiple outputs not allowed in udp modules 17 | output c_bad; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_math_signed3.v0000664000177100017500000000616713702133370021560 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) module t (/*AUTOARG*/); // verilator lint_off WIDTH wire [1:0] bug729_au = ~0; wire signed [1:0] bug729_as = ~0; wire [2:0] bug729_b = ~0; // the $signed output is unsigned because the input is unsigned; the signedness does not change. wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0 wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0 wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1 wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1 wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0 wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0 wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1 wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1 wire [3:0] bug733_a = 4'b0010; wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111 wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111 wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111 // When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign wire [3:0] bug733_qu = 2'sb11; // 4'b1111 wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111 reg signed [32:0] bug349_s; reg signed [32:0] bug349_u; wire signed [1:0] sb11 = 2'sb11; wire [3:0] subout_u; sub sub (.a(2'sb11), .z(subout_u)); initial `checkh(subout_u, 4'b1111); wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111; initial `checkh(cond_a, 6'b111111); wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111; initial `checkh(cond_b, 6'b111111); initial begin // verilator lint_on WIDTH `checkh(bug729_yuu, 1'b0); `checkh(bug729_ysu, 1'b0); `checkh(bug729_yus, 1'b1); `checkh(bug729_yss, 1'b1); `checkh(bug729_zuu, 1'b0); `checkh(bug729_zsu, 1'b0); `checkh(bug729_zus, 1'b1); `checkh(bug729_zss, 1'b1); `checkh(bug733_yu, 4'b1111); `checkh(bug733_ys, 4'b1111); `checkh(bug733_zu, 4'b1111); `checkh(bug733_zs, 4'b1111); `checkh(bug733_qu, 4'b1111); `checkh(bug733_qs, 4'b1111); // verilator lint_off WIDTH bug349_s = 4'sb1111; `checkh(bug349_s, 33'h1ffffffff); bug349_u = 4'sb1111; `checkh(bug349_u, 33'h1ffffffff); bug349_s = 4'sb1111 - 1'b1; `checkh(bug349_s,33'he); bug349_s = 4'sb1111 - 5'b00001; `checkh(bug349_s,33'he); case (2'sb11) 4'b1111: ; default: $stop; endcase case (sb11) 4'b1111: ; default: $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (input [3:0] a, output [3:0] z); assign z = a; endmodule verilator-4.038/test_regress/t/t_case_dupitems.pl0000775000177100017500000000105313702133367022204 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_static_order.out0000664000177100017500000000123413702133367023420 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_static_order.v:23:16: Unsupported: 'static' class members : ... In instance t 23 | static ClsZ z = new; | ^ %Error-UNSUPPORTED: t/t_class_static_order.v:34:16: Unsupported: 'static' class members : ... In instance t 34 | static ClsA a = new; | ^ %Error-UNSUPPORTED: t/t_class_static_order.v:35:16: Unsupported: 'static' class members : ... In instance t 35 | static ClsB b = new; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_time_sc_fs.out0000664000177100017500000000013013702133370021650 0ustar wsnyderwsnyderTime scale of t is 1fs / 1fs [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-4.038/test_regress/t/t_param_scope_bad.v0000664000177100017500000000121713702133370022301 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [1:0] value; sub #(.CASEVAL(2'h0)) p0 (.value); sub #(.CASEVAL(2'h1)) p1 (.value); sub #(.CASEVAL(2'h2)) p2 (.value); sub #(.CASEVAL(2'h3)) p3 (.value); endmodule module sub ( input [1:0] value); parameter [1:0] CASEVAL = 2'h0; always_comb begin case (value) CASEVAL: ; 2'h2: $stop; default: ; endcase end endmodule verilator-4.038/test_regress/t/t_case_write2.v0000664000177100017500000000217413702133367021422 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "verilated.v" `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [63:0] crc; integer fd; integer fdtmp; t_case_write2_tasks tasks (); integer cyc; initial cyc=0; always @ (posedge clk) begin $fwrite(fd, "[%0d] crc=%x ", cyc, crc); tasks.big_case(fd, crc[31:0]); $fwrite(fd, "\n"); end always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc); cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==1) begin crc <= 64'h00000000_00000097; $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"}); fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w"); fd <= fdtmp; end if (cyc==90) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_mem_multi_io3_sc.pl0000775000177100017500000000130213702133370022575 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_mem_multi_io3.v"); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io3.cpp --sc -Oi"], verilator_flags3 => [], ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_width_bad.out0000664000177100017500000000602513702133370022521 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_lint_width_bad.v:17:25: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. : ... In instance t 17 | localparam [3:0] XS = 'hx; | ^~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_lint_width_bad.v:45:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. : ... In instance t.p4 45 | wire [4:0] out = in; | ^ %Warning-WIDTH: t/t_lint_width_bad.v:21:25: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits. : ... In instance t 21 | wire [4:0] d = (1'b1 << 2) + 5'b1; | ^~ %Warning-WIDTH: t/t_lint_width_bad.v:27:32: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits. : ... In instance t 27 | wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); | ^ %Warning-WIDTH: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits. : ... In instance t 32 | wire [2:0] cnt = (one + one + one + one); | ^ %Warning-WIDTH: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. : ... In instance t 32 | wire [2:0] cnt = (one + one + one + one); | ^ %Warning-WIDTH: t/t_lint_width_bad.v:32:43: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. : ... In instance t 32 | wire [2:0] cnt = (one + one + one + one); | ^ %Warning-WIDTH: t/t_lint_width_bad.v:32:49: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. : ... In instance t 32 | wire [2:0] cnt = (one + one + one + one); | ^ %Warning-WIDTH: t/t_lint_width_bad.v:37:26: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. : ... In instance t 37 | initial for (a = 0; a > THREE; ++a) $display(a); | ^ %Warning-WIDTH: t/t_lint_width_bad.v:38:26: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. : ... In instance t 38 | initial for (a = 0; a >= THREE; ++a) $display(a); | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_select_bound2.pl0000775000177100017500000000105313702133370022101 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_name3.pl0000775000177100017500000000105313702133370021400 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_arraysel_wide.pl0000775000177100017500000000100113702133367022202 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_display_bad.v0000664000177100017500000000077513702133370021465 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [40:0] disp; initial disp = 41'ha_bbbb_cccc; initial begin // Display formatting $display("%x"); // Too few $display("%x",disp,disp); // Too many $display("%q"); // Bad escape $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_flag_topmodule_bad.pl0000775000177100017500000000122613702133370023162 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_topmodule.v"); lint( fails => 1, nc => 0, # Need to get it not to give the prompt expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_modport_bad.pl0000775000177100017500000000107413702133370023666 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_intdot.pl0000775000177100017500000000105313702133370021503 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_shortcircuit2.v0000664000177100017500000000330613702133370022643 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_SHORTREAL `endif `ifdef NC `define NO_SHORTREAL `endif `ifdef VERILATOR // Unsupported `define NO_SHORTREAL `endif module t (/*AUTOARG*/); // Note these are NOT pure. import "DPI-C" function int dpii_clear (); import "DPI-C" function int dpii_count (input int ctr); import "DPI-C" function bit dpii_inc0 (input int ctr); import "DPI-C" function bit dpii_inc1 (input int ctr); import "DPI-C" function bit dpii_incx (input int ctr, input bit value); integer i; integer j; integer k; bit b; integer errors; task check1(integer line, bit got, bit ex); if (got != ex) begin $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); errors++; end endtask task check(integer line, int got, int ex); if (got != ex) begin $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); errors++; end endtask // Test loop initial begin // bug963 // verilator lint_off IGNOREDRETURN dpii_clear(); // verilator lint_on IGNOREDRETURN j = 0; for (i=0; i<64; i++) begin if (i[0]) j = 0; else j = {31'b0, dpii_inc1(0)}; k = k + j; end $write("%x\n",k); check (`__LINE__, dpii_count(0), 32); if (|errors) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_up_bad.pl0000775000177100017500000000107413702133370021766 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex_portable.pl0000775000177100017500000000253213702133370024071 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Same test as t_trace_complex, but exercising the old VCD tracing API scenarios(vlt => 1); top_filename("t/t_trace_complex.v"); compile( verilator_flags2 => ['--cc --trace -CFLAGS -DVL_PORTABLE_ONLY'], ); execute( check_finished => 1, ); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_arrp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arrp\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_strp\(/); vcd_identical ("$Self->{obj_dir}/simx.vcd", "t/t_trace_complex.out"); ok(1); 1; verilator-4.038/test_regress/t/t_unoptflat_simple_2_bad.out0000664000177100017500000000165313702133370024164 0ustar wsnyderwsnyder%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:15:15: Signal unoptimizable: Feedback to clock or circular logic: 't.x' 15 | wire [2:0] x; | ^ ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unoptflat_simple_2.v:15:15: Example path: t.x t/t_unoptflat_simple_2.v:17:18: Example path: ASSIGNW t/t_unoptflat_simple_2.v:15:15: Example path: t.x ... Widest candidate vars to split: t/t_unoptflat_simple_2.v:15:15: t.x, width 3, fanout 10, can split_var ... Most fanned out candidate vars to split: t/t_unoptflat_simple_2.v:15:15: t.x, width 3, fanout 10, can split_var ... Suggest add /*verilator split_var*/ to appropriate variables above. %Error: Exiting due to verilator-4.038/test_regress/t/t_mem_multi_ref_bad.pl0000775000177100017500000000120113702133370022776 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, nc => 0, # Need to get it not to give the prompt expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_concat6.v0000664000177100017500000000357113702133367021403 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input [3:0] i_clks ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; logic the_clk; assign the_clk = i_clks[3]; always @(posedge the_clk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (the_clk) some_other_state <= 0; $write("*-* All Finished *-*\n"); $finish; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( .i_clks (i_clks) ); endmodule module ident( input i_ident, output o_ident ); assign o_ident = i_ident; endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; logic ident_clk1; always @(posedge i_clk0) begin data_q <= i_data; end ident ident ( .i_ident (i_clk1), .o_ident (ident_clk1) ); t1 t1 ( .i_clks ({ident_clk1, i_clk2, ident_clk1, i_clk0}), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( /*AUTOARG*/ // Inputs clk /*verilator clocker*/ /*verilator public_flat*/, input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); input clk; logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk), .i_clk2 (clk2), .i_data (data_in) ); endmodule verilator-4.038/test_regress/t/t_case_auto1.v0000664000177100017500000000460513702133367021240 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam // synopsys enum En_State EP_State_IDLE = {3'b000,5'd00}, EP_State_CMDSHIFT0 = {3'b001,5'd00}, EP_State_CMDSHIFT13 = {3'b001,5'd13}, EP_State_CMDSHIFT14 = {3'b001,5'd14}, EP_State_CMDSHIFT15 = {3'b001,5'd15}, EP_State_CMDSHIFT16 = {3'b001,5'd16}, EP_State_DWAIT = {3'b010,5'd00}, EP_State_DSHIFT0 = {3'b100,5'd00}, EP_State_DSHIFT1 = {3'b100,5'd01}, EP_State_DSHIFT15 = {3'b100,5'd15}; reg [7:0] /* synopsys enum En_State */ m_state_xr; // Last command, for debugging /*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/ // Beginning of automatic ASCII enum decoding reg [79:0] m_stateAscii_xr; // Decode of m_state_xr always @(m_state_xr) begin case ({m_state_xr}) EP_State_IDLE: m_stateAscii_xr = "idle "; EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; EP_State_DWAIT: m_stateAscii_xr = "dwait "; EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; default: m_stateAscii_xr = "%Error "; endcase end // End of automatics integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); if (cyc==1) begin m_state_xr <= EP_State_IDLE; end if (cyc==2) begin if (m_stateAscii_xr != "idle ") $stop; m_state_xr <= EP_State_CMDSHIFT13; end if (cyc==3) begin if (m_stateAscii_xr != "cmdshift13") $stop; m_state_xr <= EP_State_CMDSHIFT16; end if (cyc==4) begin if (m_stateAscii_xr != "cmdshift16") $stop; m_state_xr <= EP_State_DWAIT; end if (cyc==9) begin if (m_stateAscii_xr != "dwait ") $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_var_escape.v0000664000177100017500000000331313702133370021311 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs \escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9backslash\done , // Inputs clk ); input clk; integer cyc; initial cyc=1; output \escaped_normal ; wire \escaped_normal = cyc[0]; output double__underscore ; wire double__underscore = cyc[0]; // C doesn't allow leading non-alpha, so must escape output \9num ; wire \9num = cyc[0]; output \bra[ket]slash/dash-colon:9backslash\done ; wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0]; wire \wire = cyc[0]; wire \check_alias = cyc[0]; wire \check:alias = cyc[0]; wire \check;alias = !cyc[0]; // These are *different entities*, bug83 wire [31:0] \a0.cyc = ~a0.cyc; wire [31:0] \other.cyc = ~a0.cyc; sub a0 (.cyc(cyc)); sub \mod.with_dot (.cyc(cyc)); always @ (posedge clk) begin cyc <= cyc + 1; if (escaped_normal != cyc[0]) $stop; if (\escaped_normal != cyc[0]) $stop; if (double__underscore != cyc[0]) $stop; if (\9num != cyc[0]) $stop; if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop; if (\wire != cyc[0]) $stop; if (\check_alias != cyc[0]) $stop; if (\check:alias != cyc[0]) $stop; if (\check;alias != !cyc[0]) $stop; if (\a0.cyc != ~cyc) $stop; if (\other.cyc != ~cyc) $stop; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub ( input [31:0] cyc ); endmodule verilator-4.038/test_regress/t/t_vpi_zero_time_cb.pl0000775000177100017500000000174013702133370022673 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1, iv => 1); compile( make_top_shell => 0, make_main => 0, make_pli => 1, sim_time => 2100, iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"], v_flags2 => ["+define+USE_VPI_NOT_DPI"], verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_zero_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"], ); execute( iv_pli => 1, ms_pli => 1, check_finished => 1, all_run_flags => ['+PLUS +INT=1234 +STRSTR'] ); ok(1); 1; verilator-4.038/test_regress/t/t_func_twocall.pl0000775000177100017500000000105313702133370022031 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_circ_subst_bad.out0000664000177100017500000000032413702133370023207 0ustar wsnyderwsnyder%Error: t/t_pp_circ_subst_bad.v:8:40002: Too many preprocessor tokens on a line (>20000); perhaps recursive `define %Error: t/t_pp_circ_subst_bad.v:8:1: syntax error, unexpected IDENTIFIER %Error: Exiting due to verilator-4.038/test_regress/t/t_package_dot.v0000664000177100017500000000110413702133370021436 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef struct packed { logic [3:0] msk; logic [3:0] dat; } STR_t; endpackage; package csr_pkg; typedef pkg::STR_t reg_t; localparam reg_t REG_RST = 8'h34; endpackage module t (/*AUTOARG*/); initial begin if (csr_pkg::REG_RST.msk != 4'h3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_order_clkinst.out0000664000177100017500000000312413702133370022405 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Fri Jun 22 19:27:45 2018 $end $timescale 1ps $end $scope module top $end $var wire 1 / clk $end $scope module t $end $var wire 32 % c1_count [31:0] $end $var wire 1 # c1_start $end $var wire 32 ( c3_count [31:0] $end $var wire 1 ' c3_start $end $var wire 1 / clk $end $var wire 8 $ cyc [7:0] $end $var wire 32 & s2_count [31:0] $end $var wire 1 # s2_start $end $scope module c1 $end $var wire 32 % count [31:0] $end $var wire 32 * runner [31:0] $end $var wire 32 ) runnerm1 [31:0] $end $var wire 1 # start $end $upscope $end $scope module c3 $end $var wire 32 ( count [31:0] $end $var wire 32 . runner [31:0] $end $var wire 32 - runnerm1 [31:0] $end $var wire 1 ' start $end $upscope $end $scope module s2 $end $var wire 32 & count [31:0] $end $var wire 32 , runner [31:0] $end $var wire 32 + runnerm1 [31:0] $end $var wire 1 # start $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000 $ b00000000000000000000000000000000 % b00000000000000000000000000000000 & 0' b00000000000000000000000000000000 ( b11111111111111111111111111111111 ) b00000000000000000000000000000000 * b11111111111111111111111111111111 + b00000000000000000000000000000000 , b11111111111111111111111111111111 - b00000000000000000000000000000000 . 0/ #10 b00000001 $ 1/ #15 0/ #20 1# b00000010 $ b00000000000000000000000000000011 % b00000000000000000000000000000011 & 1' b00000000000000000000000000000101 ( 1/ #25 0/ #30 b00000011 $ 1/ #35 0/ #40 1/ b00000100 $ verilator-4.038/test_regress/t/t_lint_defparam_bad.out0000664000177100017500000000047113702133370023160 0ustar wsnyderwsnyder%Warning-DEFPARAM: t/t_lint_defparam.v:10:19: Suggest replace defparam assignment with Verilog 2001 #(.P(...etc...)) 10 | defparam sub.P = 2; | ^ ... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_var_ref.pl0000775000177100017500000000105313702133370020775 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inside_wild.pl0000775000177100017500000000105313702133370021643 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_for_init_bug.pl0000775000177100017500000000101513702133370022015 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); #execute() ok(1); 1; verilator-4.038/test_regress/t/t_array_backw_index_bad.v0000664000177100017500000000125013702133367023467 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); logic [31:0] array_assign [3:0]; logic [31:0] larray_assign [0:3]; initial begin array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; array_assign[4:3] = '{32'd4, 32'd3}; array_assign[1:-1] = '{32'd4, 32'd3}; array_assign[1:1] = '{32'd4}; // Ok larray_assign[1:1] = '{32'd4}; // Ok $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_rand.pl0000775000177100017500000000123713702133370021314 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_dup_bad.pl0000775000177100017500000000107113702133370021606 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_vpi_1us1ns.out0000664000177100017500000000123713702133370022574 0ustar wsnyderwsnyder:: In top.t Time scale of t is 1us / 1ns [60000] time%0d=60 123%0t=123000 dig%0t=5432110000 dig%0d=5432110 rdig%0t=5432109876 rdig%0f=5432109.876543 [60000.000000ns] time%0d=60 123%0t=123000.000000ns dig%0t=5432110000.000000ns dig%0d=5432110 rdig%0t=5432109876.543209ns rdig%0f=5432109.876543 [60000.000000ns] stime%0t=60000.000000ns stime%0d=60 stime%0f=60.000000 [60000.000000ns] rtime%0t=59999.999999ns rtime%0d=60 rtime%0f=60.000000 global vpiSimTime = 0,60000 vpiScaledRealTime = 60000 global vpiTimeUnit = -6 vpiTimePrecision = -9 top.t vpiSimTime = 0,60000 vpiScaledRealTime = 60 top.t vpiTimeUnit = -6 vpiTimePrecision = -9 *-* All Finished *-* verilator-4.038/test_regress/t/t_past_bad.pl0000775000177100017500000000107113702133370021126 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_rsvd.v0000664000177100017500000000127713702133370021036 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD module t (/*AUTOARG*/ // Inputs bool ); input bool; // BAD reg vector; // OK, as not public reg switch /*verilator public*/; // Bad typedef struct packed { logic [31:0] vector; // OK, as not public } test; test t; // global is a 1800-2009 reserved word, but we allow it when possible. reg global; initial begin t.vector = 1; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_public.out0000664000177100017500000000507013702133370022201 0ustar wsnyderwsnyder$version Generated by SpTraceVcd $end $date Tue Nov 3 09:34:23 2009 $end $timescale 1ps $end $scope module top $end $var wire 1 6 CLK $end $var wire 1 7 RESET $end $scope module t $end $var wire 1 6 CLK $end $var wire 1 # RESET $end $var wire 32 $ val [31:0] $end $var wire 2 3 vec(3) [2:1] $end $var wire 2 4 vec(4) [2:1] $end $scope module glbl $end $var wire 1 5 GSR $end $upscope $end $scope module little $end $var wire 1 6 clk $end $var wire 128 / i128 [63:190] $end $var wire 49 - i48 [1:49] $end $var wire 8 , i8 [0:7] $end $upscope $end $scope module neg $end $var wire 1 6 clk $end $var wire 128 ( i128 [63:-64] $end $var wire 48 & i48 [-1:-48] $end $var wire 8 % i8 [0:-7] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 $ b00000000 % b000000000000000000000000000000000000000000000000 & b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ( b00000000 , b0000000000000000000000000000000000000000000000000 - b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00 3 b00 4 15 17 06 #1 #2 #3 b11111111 % b111111111111111111111111111111111111111111111111 & b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 ( b11111111 , b1111111111111111111111111111111111111111111111111 - b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 / 16 #4 #5 #6 06 #7 05 #8 #9 0# b00000000 % b000000000000000000000000000000000000000000000000 & b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ( b00000000 , b0000000000000000000000000000000000000000000000000 - b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / 07 16 #10 #11 #12 06 #13 #14 #15 b00000000000000000000000000000001 $ b11111111 % b111111111111111111111111111111111111111111111111 & b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 ( b11111111 , b1111111111111111111111111111111111111111111111111 - b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 / 16 #16 #17 #18 06 #19 #20 verilator-4.038/test_regress/t/t_lint_once_bad.v0000664000177100017500000000101513702133370021756 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Check that we report warnings only once on parameterized modules // Also check that we don't suppress warnings on the same line module t (); sub #(.A(1)) sub1(); sub #(.A(2)) sub2(); sub #(.A(3)) sub3(); endmodule module sub; parameter A = 0; reg [A:0] unus1; reg [A:0] unus2; endmodule verilator-4.038/test_regress/t/t_timescale.v0000664000177100017500000000002513702133370021144 0ustar wsnyderwsnydermodule t; endmodule verilator-4.038/test_regress/t/t_lint_setout_bad.out0000664000177100017500000000040413702133370022720 0ustar wsnyderwsnyder%Error-PORTSHORT: t/t_lint_setout_bad.v:17:8: Output port is connected to a constant pin, electrical short : ... In instance t 17 | .cpu_if_timeout(1'b0) | ^~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_stream3.pl0000775000177100017500000000105313702133370020727 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_dead.pl0000775000177100017500000000127213702133367021444 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, class dead"); scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); file_grep_not("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/ix); ok(1); 1; verilator-4.038/test_regress/t/t_struct_unpacked2.v0000664000177100017500000000066513702133370022470 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module x; typedef struct { int b [2]; } notpacked_t; notpacked_t n; initial begin n.b[0] = 1; if (n.b[0] != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func.pl0000775000177100017500000000105313702133370020304 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_fork.v0000664000177100017500000000062513702133370020145 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); initial begin fork : fblk begin $write("*-* All Finished *-*\n"); $finish; end join : fblk end endmodule verilator-4.038/test_regress/t/t_time_sc_us.out0000664000177100017500000000022613702133370021675 0ustar wsnyderwsnyder Warning: (W516) default time unit changed to time resolution Time scale of t is 1us / 1us [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-4.038/test_regress/t/t_lint_realcvt_bad.v0000664000177100017500000000054313702133370022477 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub; integer i; initial begin i = 23.2; i = 23.0; // No warning - often happens with units of time end endmodule verilator-4.038/test_regress/t/t_func_default_warn.pl0000775000177100017500000000112313702133370023035 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-Wno-WIDTH"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_pull_bad.pl0000775000177100017500000000111313702133370022006 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlcov_data_c.dat0000664000177100017500000000007713343101620022126 0ustar wsnyderwsnyder# SystemC::Coverage-3 C 'CoverPoint6ffile1.sphl159' 10 verilator-4.038/test_regress/t/t_display_wide.v0000664000177100017500000000600313702133370021655 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [4095:0] crc; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]}; // not a good crc :) if (cyc==0) begin // Setup crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]); $write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]); //Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc); if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc ) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_math_real_public.v0000664000177100017500000000063113702133370022473 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 module t; sub #(.REAL(2.0)) sub; endmodule module sub (); parameter REAL = 0.0; initial begin $display("REAL %g", REAL); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_class_extends_this.out0000664000177100017500000000433413702133367023443 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_extends_this.v:13:11: Unsupported: this 13 | if (this.value != 1) $stop; | ^~~~ %Error: t/t_class_extends_this.v:13:11: Can't find definition of scope/variable: 'this' 13 | if (this.value != 1) $stop; | ^~~~ %Error-UNSUPPORTED: t/t_class_extends_this.v:17:19: Unsupported: class extends 17 | class Cls extends Base; | ^~~~ %Error: t/t_class_extends_this.v:17:19: Found definition of 'Base' as a CLASS but expected a variable 17 | class Cls extends Base; | ^~~~ %Error-UNSUPPORTED: t/t_class_extends_this.v:21:11: Unsupported: this 21 | if (this.value != 2) $stop; | ^~~~ %Error: t/t_class_extends_this.v:21:11: Can't find definition of scope/variable: 'this' 21 | if (this.value != 2) $stop; | ^~~~ %Error-UNSUPPORTED: t/t_class_extends_this.v:22:11: Unsupported: super 22 | if (super.value != 1) $stop; | ^~~~~ %Error: t/t_class_extends_this.v:22:11: Can't find definition of scope/variable: 'super' 22 | if (super.value != 1) $stop; | ^~~~~ %Error-UNSUPPORTED: t/t_class_extends_this.v:23:7: Unsupported: super 23 | super.test(); | ^~~~~ %Error: t/t_class_extends_this.v:23:7: Can't find definition of scope/variable: 'super' 23 | super.test(); | ^~~~~ %Error-UNSUPPORTED: t/t_class_extends_this.v:24:7: Unsupported: super 24 | super.value = 10; | ^~~~~ %Error: t/t_class_extends_this.v:24:7: Can't find definition of scope/variable: 'super' 24 | super.value = 10; | ^~~~~ %Error-UNSUPPORTED: t/t_class_extends_this.v:25:7: Unsupported: this 25 | this.value = 20; | ^~~~ %Error: t/t_class_extends_this.v:25:7: Can't find definition of scope/variable: 'this' 25 | this.value = 20; | ^~~~ %Error-UNSUPPORTED: t/t_class_extends_this.v:26:11: Unsupported: super 26 | if (super.value != 10) $stop; | ^~~~~ %Error: t/t_class_extends_this.v:26:11: Can't find definition of scope/variable: 'super' 26 | if (super.value != 10) $stop; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_altera_lpm_ff.pl0000775000177100017500000000120613702133367022152 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_math_shiftrs.pl0000775000177100017500000000105313702133370022044 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_nest.pl0000775000177100017500000000076613702133370021740 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_stop_bad.out0000664000177100017500000000010613702133370021333 0ustar wsnyderwsnyderIntentional stop %Error: t/t_stop_bad.v:10: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_process.v0000664000177100017500000000264013702133370020661 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // class process; // enum state { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED }; // static function process self(); // function state status(); // function void kill(); // task await(); // Warn as unsupported (no UVM library use) // function void suspend(); // Warn as unsupported (no UVM library use) // function void resume(); // Warn as unsupported (no UVM library use) // function void srandom( int seed ); // Just ignore? // function string get_randstate(); // Just ignore? // function void set_randstate( string state ); // Just ignore? // endclass module t(/*AUTOARG*/); process p; initial begin if (p != null) $stop; p = process::self(); if (p.status() != process::RUNNING) $stop; if (p.status() == process::WAITING) $stop; if (p.status() == process::SUSPENDED) $stop; if (p.status() == process::KILLED) $stop; if (p.status() == process::FINISHED) $stop; if (0) p.kill(); if (0) p.await(); if (0) p.suspend(); if (0) p.resume(); p.srandom(0); p.set_randstate(p.get_randstate()); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_litendian_fst.out0000664000177100017500000002644013702133370023552 0ustar wsnyderwsnyder$date Sun May 3 21:53:46 2020 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var parameter 8 " P $end $var wire 1 ! clk $end $var int 32 # cyc $end $var parameter 8 $ Q $end $var logic 1 % v_a $end $var logic 2 & v_b $end $var logic 8 ' v_c $end $var logic 9 ( v_d $end $var logic 16 ) v_e $end $var logic 17 * v_f $end $var logic 32 + v_g $end $var logic 33 , v_h $end $var logic 64 - v_i $end $var logic 65 . v_j $end $var logic 128 / v_k $end $var logic 129 0 v_l $end $var logic 256 1 v_m $end $var logic 257 2 v_n $end $var logic 512 3 v_o $end $var logic 3 4 v_p $end $var logic 15 5 v_q $end $var logic 31 6 v_r $end $var logic 63 7 v_s $end $var logic 127 8 v_t $end $var logic 255 9 v_u $end $var logic 511 : v_v $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 9 b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 8 b000000000000000000000000000000000000000000000000000000000000000 7 b0000000000000000000000000000000 6 b000000000000000 5 b000 4 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2 b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1 b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000 . b0000000000000000000000000000000000000000000000000000000000000000 - b000000000000000000000000000000000 , b00000000000000000000000000000000 + b00000000000000000 * b0000000000000000 ) b000000000 ( b00000000 ' b00 & 0% b00010100 $ b00000000000000000000000000000000 # b00001010 " 0! $end #10 1! b00000000000000000000000000000001 # 1% b11 & b11111111 ' b111111111 ( b1111111111111111 ) b11111111111111111 * b11111111111111111111111111111111 + b111111111111111111111111111111111 , b1111111111111111111111111111111111111111111111111111111111111111 - b11111111111111111111111111111111111111111111111111111111111111111 . b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 / b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 0 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 2 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 3 b111 4 b111111111111111 5 b1111111111111111111111111111111 6 b111111111111111111111111111111111111111111111111111111111111111 7 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 8 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 9 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 : #15 0! #20 1! b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 : b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 9 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 8 b111111111111111111111111111111111111111111111111111111111111110 7 b1111111111111111111111111111110 6 b111111111111110 5 b110 4 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 3 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 2 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 1 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 0 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 / b11111111111111111111111111111111111111111111111111111111111111110 . b1111111111111111111111111111111111111111111111111111111111111110 - b111111111111111111111111111111110 , b11111111111111111111111111111110 + b11111111111111110 * b1111111111111110 ) b111111110 ( b11111110 ' b10 & 0% b00000000000000000000000000000010 # #25 0! #30 1! b00000000000000000000000000000011 # b00 & b11111100 ' b111111100 ( b1111111111111100 ) b11111111111111100 * b11111111111111111111111111111100 + b111111111111111111111111111111100 , b1111111111111111111111111111111111111111111111111111111111111100 - b11111111111111111111111111111111111111111111111111111111111111100 . b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 / b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 0 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 1 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 2 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 3 b100 4 b111111111111100 5 b1111111111111111111111111111100 6 b111111111111111111111111111111111111111111111111111111111111100 7 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 8 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 9 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 : verilator-4.038/test_regress/t/t_dpi_export.pl0000775000177100017500000000144013702133370021526 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end scenarios(simulator => 1); compile( # Amazingly VCS, NC and Verilator all just accept the C file here! v_flags2 => ["t/t_dpi_export_c.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME -no-l2name"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_overwidth_bad.pl0000775000177100017500000000126113702133370023043 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/t_var_overwidth_bad.cpp"], ); execute( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_pipe_filter.v0000664000177100017500000000073613702133370021511 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //=========================================================================== // Includes example line 10; example line 11; `include "t_pipe_filter_inc.vh" // Twice to check caching of includes `include "t_pipe_filter_inc.vh" example line 15; example line 16; verilator-4.038/test_regress/t/t_trace_litendian_fst.pl0000775000177100017500000000204613702133370023355 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_litendian.v"); # Travis environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. compile( verilator_flags2 => ['--cc --trace-fst --trace-params -Wno-LITENDIAN', ($Self->{vltmt} ? '--threads 6' : '')], ); execute( check_finished => 1, ); fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_time_cb.v0000664000177100017500000000626613702133370021473 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs input clk ); `ifndef VERILATOR reg clk_r = 0; always #10 clk_r = ~clk_r; assign clk = clk_r; `endif reg onebit /*verilator public_flat_rw @(posedge clk) */; reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */; reg [31:0] count /*verilator public_flat_rd */; reg [31:0] half_count /*verilator public_flat_rd */; reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */; reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */; reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */; reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */; reg [511:0] text /*verilator public_flat_rw @(posedge clk) */; integer status; sub sub(); // Test loop initial begin count = 0; onebit = 1'b0; fourthreetwoone[3] = 0; // stop icarus optimizing away text_byte = "B"; text_half = "Hf"; text_word = "Word"; text_long = "Long64b"; text = "Verilog Test module"; /* if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop; end $write("%%Info: Checking results\n"); if (onebit != 1'b1) $stop; if (quads[2] != 62'h12819213_abd31a1c) $stop; if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; if (text_byte != "A") $stop; if (text_half != "T2") $stop; if (text_word != "Tree") $stop; if (text_long != "44Four44") $stop; if (text != "lorem ipsum") $stop; */ end always @(posedge clk) begin count <= count + 2; if (count[1]) half_count <= half_count + 2; if (count == 1000) begin // $write("*-* All Finished *-*\n"); $finish; end end genvar i; generate for (i=1; i<=128; i=i+1) begin : arr arr #(.LENGTH(i)) arr(); end endgenerate endmodule : t module sub; reg subsig1 /*verilator public_flat_rd*/; reg subsig2 /*verilator public_flat_rd*/; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = subsig1 | subsig2; `endif endmodule : sub module arr; parameter LENGTH = 1; reg [LENGTH-1:0] sig /*verilator public_flat_rw*/; reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/; reg check /*verilator public_flat_rw*/; reg verbose /*verilator public_flat_rw*/; initial begin sig = {LENGTH{1'b0}}; rfr = {LENGTH{1'b0}}; end always @(posedge check) begin if (verbose) $display("%m : %x %x", sig, rfr); if (check && sig != rfr) $stop; check <= 0; end endmodule : arr verilator-4.038/test_regress/t/t_parse_delay.v0000664000177100017500000000101013702133370021461 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); // verilator lint_off WIDTH reg [6:0] myreg1; initial begin myreg1 = # 100 7'd0; myreg1 = # 100 'b0; // [#] [100] ['b0] myreg1 = #100'b0; // [#] [100] ['b0] myreg1 = 100'b0; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_shift.v0000664000177100017500000000113013702133370021471 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Mandy Xu. // SPDX-License-Identifier: CC0-1.0 module t #(parameter[95:0] P = 1) (input clk); localparam [32:0] M = 4; function [M:0] gen_matrix; gen_matrix[0] = 1>> M; endfunction reg [95: 0] lfsr = 0; always @(posedge clk) begin lfsr <= (1 >> P); end wire [95: 0] lfsr_w = 1 >> P; localparam [95: 0] lfsr_p = 1 >> P; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_public.pl0000775000177100017500000000135313702133370022012 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if ($Self->{vlt_all}) { compile( verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], make_top_shell => 0, make_main => 0, ); } else { compile( ); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_defaults.pl0000775000177100017500000000105313702133370022173 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_bitsel_struct.v0000664000177100017500000000131413702133367022074 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test case for struct signal bit selection. // // This test is to check that bit selection of multi-dimensional signal inside // of a struct works. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { logic [1:0][15:0] channel; logic others; } buss_t; buss_t b; reg [7:0] a; initial begin b = {16'h8765,16'h4321,1'b1}; a = b.channel[0][8+:8]; if (a != 8'h43) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_package_export_bad.pl0000775000177100017500000000122713702133370023156 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_package_export.v"); lint( v_flags2 => ['+define+T_PACKAGE_EXPORT_BAD',], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_typedef.out0000664000177100017500000000032113702133367022372 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_typedef.v:14:24: Unsupported: Parameterized classes 14 | uvm_resource_types#(1,2,3)::rsrc_q_t rtab_paramed [string]; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_struct_unpacked_bad.pl0000775000177100017500000000111313702133370023352 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_topmodule_bad.out0000664000177100017500000000117613702133370023357 0ustar wsnyderwsnyder%Warning-MULTITOP: t/t_flag_topmodule.v:15:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' 7 | module a; | ^ : ... Top module 'a2' 15 | module a2; | ^~ : ... Top module 'b' 22 | module b; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_string_fst.pl0000775000177100017500000000117213702133370022713 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_string.v"); compile( verilator_flags2 => ['--cc --trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_for0.v0000664000177100017500000000155313702133370020704 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; Testit testit (/*AUTOINST*/ // Inputs .clk (clk)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin end else if (cyc<10) begin end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Testit (clk); input clk; genvar igen; generate for (igen=0; igen<0; igen=igen+1) begin : test_gen always @ (posedge clk) begin $display("igen1 = %d", igen); $stop; end end endgenerate endmodule verilator-4.038/test_regress/t/t_lint_defparam.pl0000775000177100017500000000076313702133370022165 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex_fst_thread.out0000664000177100017500000001030613666032701024600 0ustar wsnyderwsnyder$date Wed May 1 19:09:18 2019 $end $version fstWriter $end $timescale 1ns $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $var logic 2 # v_strp $end $var logic 4 $ v_strp_strp $end $var logic 2 % v_unip_strp $end $var logic 2 & v_arrp $end $var logic 4 ' v_arrp_arrp $end $var logic 4 ( v_arrp_strp $end $var logic 1 ) v_arru(1) $end $var logic 1 * v_arru(2) $end $var logic 1 + v_arru_arru(3)(1) $end $var logic 1 , v_arru_arru(3)(2) $end $var logic 1 - v_arru_arru(4)(1) $end $var logic 1 . v_arru_arru(4)(2) $end $var logic 2 / v_arru_arrp(3) $end $var logic 2 0 v_arru_arrp(4) $end $var logic 2 1 v_arru_strp(3) $end $var logic 2 2 v_arru_strp(4) $end $var real 64 3 v_real $end $var real 64 4 v_arr_real(0) $end $var real 64 5 v_arr_real(1) $end $var logic 64 6 v_str32x2 $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var logic 32 7 v_enumed $end $attrbegin misc 07 "" 1 $end $var logic 32 8 v_enumed2 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 9 v_enumb $end $scope module unnamedblk1 $end $var integer 32 : b $end $scope module unnamedblk2 $end $var integer 32 ; a $end $upscope $end $upscope $end $scope module p2 $end $var parameter 32 < PARAM $end $upscope $end $scope module p3 $end $var parameter 32 = PARAM $end $upscope $end $upscope $end $scope module $unit $end $var bit 1 > global_bit $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000000000000000000000000000000 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( 0) 0* 0+ 0, 0- 0. b00 / b00 0 b00 1 b00 2 r0 3 r0 4 r0 5 b0000000000000000000000000000000000000000000000000000000011111111 6 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 b000 9 b00000000000000000000000000000000 : b00000000000000000000000000000000 ; b00000000000000000000000000000010 < b00000000000000000000000000000011 = 1> #10 b00000000000000000000000000000101 ; b00000000000000000000000000000101 : b111 9 b00000000000000000000000000000010 8 b00000000000000000000000000000001 7 b0000000000000000000000000000000100000000000000000000000011111110 6 r0.3 5 r0.2 4 r0.1 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000001 " 1! #15 0! #20 1! b00000000000000000000000000000010 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.2 3 r0.4 4 r0.6 5 b0000000000000000000000000000001000000000000000000000000011111101 6 b00000000000000000000000000000010 7 b00000000000000000000000000000100 8 b110 9 b00000000000000000000000000000101 : b00000000000000000000000000000101 ; #25 0! #30 1! b00000000000000000000000000000101 ; b00000000000000000000000000000101 : b101 9 b00000000000000000000000000000110 8 b00000000000000000000000000000011 7 b0000000000000000000000000000001100000000000000000000000011111100 6 r0.8999999999999999 5 r0.6000000000000001 4 r0.3 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000011 " #35 0! #40 1! b00000000000000000000000000000100 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.4 3 r0.8 4 r1.2 5 b0000000000000000000000000000010000000000000000000000000011111011 6 b00000000000000000000000000000100 7 b00000000000000000000000000001000 8 b100 9 b00000000000000000000000000000101 : b00000000000000000000000000000101 ; #45 0! #50 1! b00000000000000000000000000000101 ; b00000000000000000000000000000101 : b011 9 b00000000000000000000000000001010 8 b00000000000000000000000000000101 7 b0000000000000000000000000000010100000000000000000000000011111010 6 r1.5 5 r1 4 r0.5 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000101 " #55 0! #60 1! b00000000000000000000000000000110 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.6 3 r1.2 4 r1.8 5 b0000000000000000000000000000011000000000000000000000000011111001 6 b00000000000000000000000000000110 7 b00000000000000000000000000001100 8 b010 9 b00000000000000000000000000000101 : b00000000000000000000000000000101 ; verilator-4.038/test_regress/t/t_func_flip.pl0000775000177100017500000000105313702133370021316 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_metacmt_onoff.v0000664000177100017500000000100613702133370022017 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Test turning on and off a message on the same line; only middle reg shouldn't warn reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_parameter_access.pl0000775000177100017500000000105313702133370024672 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlcov_data_d.dat0000664000177100017500000000007713343101620022127 0ustar wsnyderwsnyder# SystemC::Coverage-3 C 'CoverPoint6ffile1.sphl159' 12 verilator-4.038/test_regress/t/t_dpi_accessors_macros_inc.vh0000664000177100017500000000173513702133370024375 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Generic accessor macros for test of DPI accessors // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // // Contributed by Jeremy Bennett and Jie Xu // // See t_dpi_accessors.v for details of the test. This file should be included // by the top level module to define the generic accessor macros. // Accessor macros, to keep stuff concise `define R_ACCESS(type_spec, name, expr) \ export "DPI-C" function name``_read; \ function bit type_spec name``_read; \ name``_read = (expr); \ endfunction `define W_ACCESS(type_spec, name, expr) \ export "DPI-C" task name``_write; \ task name``_write; \ input bit type_spec in; \ expr = in; \ endtask `define RW_ACCESS(type_spec, name, expr) \ `R_ACCESS (type_spec, name, expr); \ `W_ACCESS (type_spec, name, expr) verilator-4.038/test_regress/t/t_typename.v0000664000177100017500000000207613702133370021030 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t(/*AUTOARG*/); real r; logic l; typedef bit mybit_t; mybit_t [2:0] bitp20; mybit_t bitu32 [3:2]; mybit_t bitu31 [3:1][4:5]; initial begin `checks($typename(real), "real"); `checks($typename(bit), "bit"); `checks($typename(int), "int"); `checks($typename(logic), "logic"); `checks($typename(string), "string"); `checks($typename(r), "real"); `checks($typename(l), "logic"); `checks($typename(mybit_t), "bit"); `checks($typename(bitp20), "bit[2:0]"); `checks($typename(bitu32), "bit$[3:2]"); `checks($typename(bitu31), "bit$[3:1][4:5]"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_mul.v0000664000177100017500000000306113702133370021007 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; reg [63:0] sum; wire [31:0] out1; wire [31:0] out2; sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1}; if (cyc==1) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==90) begin if (sum !== 64'he396068aba3898a2) $stop; end else if (cyc==91) begin end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, out2, // Inputs in1, in2 ); input [15:0] in1; input [15:0] in2; output reg signed [31:0] out1; output reg unsigned [31:0] out2; always @* begin // verilator lint_off WIDTH out1 = $signed(in1) * $signed(in2); out2 = $unsigned(in1) * $unsigned(in2); // verilator lint_on WIDTH end endmodule verilator-4.038/test_regress/t/t_reloop_cam.pl0000775000177100017500000000162113702133370021472 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-unroll-count 1024", $Self->wno_unopthreads_for_few_cores(), "--stats"], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Reloop iterations\s+(\d+)/i, 768); file_grep($Self->{stats}, qr/Optimizations, Reloops\s+(\d+)/i, 3); } ok(1); 1; verilator-4.038/test_regress/t/t_for_funcbound.pl0000775000177100017500000000112413702133370022201 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect => '[10] hello [20] world ', ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_compass_bad.v0000664000177100017500000000063413702133370022335 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs o, // Inputs i ); input i; output o; sub sub(i, o); endmodule module sub(input i, output o); assign o = (i===1'bz) ? 1'b0 : i; endmodule verilator-4.038/test_regress/t/t_trace_flag_off.out0000664000177100017500000000014413702133370022463 0ustar wsnyderwsnyder-Info: t/t_trace_flag_off.v:10: $dumpvar ignored, as Verilated without --trace *-* All Finished *-* verilator-4.038/test_regress/t/t_pp_underline_bad.pl0000775000177100017500000000107113702133370022643 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_in_inc_bad.out0000664000177100017500000000050213702133370022633 0ustar wsnyderwsnyder%Error: t/t_lint_in_inc_bad_2.vh:9:7: syntax error, unexpected if, expecting '(' 9 | if if if; | ^~ t/t_lint_in_inc_bad_1.vh:8:1: ... note: In file included from t_lint_in_inc_bad_1.vh t/t_lint_in_inc_bad.v:8:1: ... note: In file included from t_lint_in_inc_bad.v %Error: Exiting due to verilator-4.038/test_regress/t/t_vlt_warn.vlt0000664000177100017500000000154113702133370021376 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule DEPRECATED -file "t/t_vlt_warn.vlt" -lines 14 lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v" lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 19 lint_off -rule DECLFILENAME -file "*/t_vlt_warn.v" // Test wildcard filenames lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 20-20 // Test global disables lint_off -file "*/t_vlt_warn.v" -lines 21-21 // Test match lint_off -rule UNUSED -file "*/t_vlt_warn.v" -match "Signal is not used: 'width_warn*'" coverage_off -file "t/t_vlt_warn.v" // Test --flag is also accepted tracing_off --file "t/t_vlt_warn.v" verilator-4.038/test_regress/t/t_mod_recurse.v0000664000177100017500000000526013702133370021513 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Sean Moore. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] tripline = crc[7:0]; /*AUTOWIRE*/ wire valid; wire [3-1:0] value; PriorityChoice #(.OCODEWIDTH(3)) pe (.out(valid), .outN(value[2:0]), .tripline(tripline)); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, valid, value}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc5fc632f816568fb if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module PriorityChoice (out, outN, tripline); parameter OCODEWIDTH = 1; localparam CODEWIDTH=OCODEWIDTH-1; localparam SCODEWIDTH= (CODEWIDTH<1) ? 1 : CODEWIDTH; output reg out; output reg [OCODEWIDTH-1:0] outN; input wire [(1< 1); top_filename("t/t_inst_tree.v"); my $default_vltmt_threads = $Self->get_default_vltmt_threads(); compile( verilator_flags2 => ['--stats', "$Self->{t_dir}/$Self->{name}.vlt", # Force 3 threads even if we have fewer cores $Self->{vltmt} ? "--threads $default_vltmt_threads" : ""] ); sub checkRelativeRefs { my ($mod, $expect_relative) = @_; my $found_relative = 0; my $file = "$Self->{obj_dir}/V$Self->{name}_${mod}.cpp"; my $text = file_contents($file); # Remove "this->__VlSymsp" which is noise $text =~ s/this->__VlSymsp//g; if ($text =~ m/this->/) { $found_relative = 1; } if ($found_relative != $expect_relative) { error("$file " . ($found_relative ? "has" : "does not have") . " relative variable references."); } } if ($Self->{vlt_all}) { # We expect to combine sequent functions across multiple instances of # l2, l3, l4, l5. If this number drops, please confirm this has not broken. file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, ($Self->{vltmt} ? 84 : 52)); # Expect absolute refs in CFuncs for t (top module) and l1 (because it # has only one instance) checkRelativeRefs("t", 0); checkRelativeRefs("l1", 0); # Others should get relative references checkRelativeRefs("l2", 1); checkRelativeRefs("l3", 1); checkRelativeRefs("l4", 1); checkRelativeRefs("l5__P1", 1); checkRelativeRefs("l5__P2", 1); } execute( check_finished => 1, expect => '\] (%m|.*t\.ps): Clocked ', ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_string_c.cpp0000664000177100017500000000207613702133370022167 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_string__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { extern int dpii_string(const char* s); } #endif //====================================================================== int dpii_string(const char* s) { printf("dpii_string: %s\n",s); return strlen(s); } verilator-4.038/test_regress/t/t_math_yosys.pl0000775000177100017500000000105313702133370021550 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_split_var_2_trace.out0000664000177100017500000010336313702133370023153 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Tue Feb 11 16:07:02 2020 $end $timescale 1ps $end $scope module top $end $var wire 1 o2 clk $end $scope module t $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 )3 NUMSUB [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 1 o2 clk $end $var wire 64 93 expc [63:0] $end $var wire 8 13 in [7:0] $end $var wire 8 M- out(0) [7:0] $end $var wire 8 N- out(1) [7:0] $end $var wire 8 O- out(2) [7:0] $end $var wire 8 P- out(3) [7:0] $end $var wire 8 Q- out(4) [7:0] $end $var wire 8 R- out(5) [7:0] $end $var wire 8 S- out(6) [7:0] $end $var wire 8 T- out(7) [7:0] $end $var wire 8 U- out(8) [7:0] $end $var wire 3 s shift [2:0] $end $var wire 8 ?. through_tmp [7:0] $end $scope module always_block $end $var wire 1 O2 failed $end $scope module unnamedblk1 $end $var wire 32 W2 i [31:0] $end $upscope $end $upscope $end $scope module i_t_array_rev $end $var wire 1 C arrd(0) $end $var wire 1 K arrd(1) $end $var wire 1 o2 clk $end $var wire 32 }5 cyc [31:0] $end $var wire 1 _2 localbkw(0) $end $var wire 1 g2 localbkw(1) $end $var wire 1 S y0 $end $var wire 1 [ y1 $end $scope module arr_rev_u $end $var wire 1 c arrbkw(0) $end $var wire 1 d arrbkw(1) $end $var wire 1 S y0 $end $var wire 1 [ y1 $end $upscope $end $upscope $end $scope module i_var_decl_with_init $end $var wire 32 # var0 [-1:30] $end $var wire 32 3 var1 [30:-1] $end $var wire 32 + var2 [-1:30] $end $var wire 32 ; var3 [30:-1] $end $upscope $end $scope module shifter0 $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 I3 OFFSET [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 13 in [7:0] $end $var wire 8 { out [7:0] $end $var wire 3 s shift [2:0] $end $var wire 8 -! tmp(-1) [7:0] $end $var wire 8 %! tmp(-2) [7:0] $end $var wire 8 13 tmp(-3) [7:0] $end $var wire 8 5! tmp(0) [7:0] $end $upscope $end $scope module shifter1 $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 I3 OFFSET [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 13 in [7:0] $end $var wire 8 =! out [7:0] $end $var wire 3 s shift [2:0] $end $var wire 8 E! tmp(-1) [7:0] $end $var wire 8 %! tmp(-2) [7:0] $end $var wire 8 13 tmp(-3) [7:0] $end $var wire 8 =! tmp(0) [7:0] $end $upscope $end $scope module shifter2 $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 Q3 OFFSET [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 13 in [7:0] $end $var wire 8 M! out [7:0] $end $var wire 3 s shift [2:0] $end $var wire 8 13 tmp(1) [7:0] $end $var wire 8 U! tmp(2) [7:0] $end $var wire 8 ]! tmp(3) [7:0] $end $var wire 8 M! tmp(4) [7:0] $end $upscope $end $scope module shifter3 $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 w2 N [31:0] $end $var wire 32 Q3 OFFSET [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 13 in [7:0] $end $var wire 8 G. out [7:0] $end $var wire 3 s shift [2:0] $end $var wire 8 13 tmp0(1)(1) [7:0] $end $var wire 8 13 tmp0(1)(2) [7:0] $end $var wire 8 13 tmp0(1)(3) [7:0] $end $var wire 8 %! tmp0(2)(1) [7:0] $end $var wire 8 %! tmp0(2)(2) [7:0] $end $var wire 8 %! tmp0(2)(3) [7:0] $end $var wire 8 e! tmp0(3)(1) [7:0] $end $var wire 8 m! tmp0(3)(2) [7:0] $end $var wire 8 u! tmp0(3)(3) [7:0] $end $var wire 8 }! tmp0(4)(1) [7:0] $end $var wire 8 '" tmp0(4)(2) [7:0] $end $var wire 8 /" tmp0(4)(3) [7:0] $end $var wire 8 7" tmp1(1)(1) [7:0] $end $var wire 8 ?" tmp1(1)(2) [7:0] $end $var wire 8 G" tmp1(1)(3) [7:0] $end $var wire 8 O" tmp1(2)(1) [7:0] $end $var wire 8 W" tmp1(2)(2) [7:0] $end $var wire 8 _" tmp1(2)(3) [7:0] $end $var wire 8 g" tmp1(3)(1) [7:0] $end $var wire 8 o" tmp1(3)(2) [7:0] $end $var wire 8 w" tmp1(3)(3) [7:0] $end $var wire 8 !# tmp1(4)(1) [7:0] $end $var wire 8 )# tmp1(4)(2) [7:0] $end $var wire 8 1# tmp1(4)(3) [7:0] $end $var wire 8 I+ tmp10(1)(1) [7:0] $end $var wire 8 Q+ tmp10(1)(2) [7:0] $end $var wire 8 Y+ tmp10(1)(3) [7:0] $end $var wire 8 a+ tmp10(2)(1) [7:0] $end $var wire 8 i+ tmp10(2)(2) [7:0] $end $var wire 8 q+ tmp10(2)(3) [7:0] $end $var wire 8 y+ tmp10(3)(1) [7:0] $end $var wire 8 #, tmp10(3)(2) [7:0] $end $var wire 8 +, tmp10(3)(3) [7:0] $end $var wire 8 3, tmp10(4)(1) [7:0] $end $var wire 8 ;, tmp10(4)(2) [7:0] $end $var wire 8 C, tmp10(4)(3) [7:0] $end $var wire 8 O. tmp12(-1)(1)(1) [7:0] $end $var wire 8 W. tmp12(-1)(1)(2) [7:0] $end $var wire 8 _. tmp12(-1)(1)(3) [7:0] $end $var wire 8 g. tmp12(-1)(2)(1) [7:0] $end $var wire 8 o. tmp12(-1)(2)(2) [7:0] $end $var wire 8 w. tmp12(-1)(2)(3) [7:0] $end $var wire 8 !/ tmp12(-1)(3)(1) [7:0] $end $var wire 8 )/ tmp12(-1)(3)(2) [7:0] $end $var wire 8 1/ tmp12(-1)(3)(3) [7:0] $end $var wire 8 G. tmp12(-1)(4)(1) [7:0] $end $var wire 8 9/ tmp12(-1)(4)(2) [7:0] $end $var wire 8 A/ tmp12(-1)(4)(3) [7:0] $end $var wire 8 I/ tmp12(0)(1)(1) [7:0] $end $var wire 8 Q/ tmp12(0)(1)(2) [7:0] $end $var wire 8 Y/ tmp12(0)(1)(3) [7:0] $end $var wire 8 a/ tmp12(0)(2)(1) [7:0] $end $var wire 8 i/ tmp12(0)(2)(2) [7:0] $end $var wire 8 q/ tmp12(0)(2)(3) [7:0] $end $var wire 8 y/ tmp12(0)(3)(1) [7:0] $end $var wire 8 #0 tmp12(0)(3)(2) [7:0] $end $var wire 8 +0 tmp12(0)(3)(3) [7:0] $end $var wire 8 30 tmp12(0)(4)(1) [7:0] $end $var wire 8 ;0 tmp12(0)(4)(2) [7:0] $end $var wire 8 C0 tmp12(0)(4)(3) [7:0] $end $var wire 8 [4 tmp13(1)(1) [7:0] $end $var wire 8 c4 tmp13(1)(2) [7:0] $end $var wire 8 k4 tmp13(1)(3) [7:0] $end $var wire 8 s4 tmp13(2)(1) [7:0] $end $var wire 8 {4 tmp13(2)(2) [7:0] $end $var wire 8 %5 tmp13(2)(3) [7:0] $end $var wire 8 -5 tmp13(3)(1) [7:0] $end $var wire 8 55 tmp13(3)(2) [7:0] $end $var wire 8 =5 tmp13(3)(3) [7:0] $end $var wire 8 E5 tmp13(4)(1) [7:0] $end $var wire 8 M5 tmp13(4)(2) [7:0] $end $var wire 8 U5 tmp13(4)(3) [7:0] $end $var wire 8 9# tmp2(1)(1) [7:0] $end $var wire 8 A# tmp2(1)(2) [7:0] $end $var wire 8 I# tmp2(1)(3) [7:0] $end $var wire 8 Q# tmp2(2)(1) [7:0] $end $var wire 8 Y# tmp2(2)(2) [7:0] $end $var wire 8 a# tmp2(2)(3) [7:0] $end $var wire 8 i# tmp2(3)(1) [7:0] $end $var wire 8 q# tmp2(3)(2) [7:0] $end $var wire 8 y# tmp2(3)(3) [7:0] $end $var wire 8 #$ tmp2(4)(1) [7:0] $end $var wire 8 +$ tmp2(4)(2) [7:0] $end $var wire 8 3$ tmp2(4)(3) [7:0] $end $var wire 8 ;$ tmp3(1)(1) [7:0] $end $var wire 8 C$ tmp3(1)(2) [7:0] $end $var wire 8 K$ tmp3(1)(3) [7:0] $end $var wire 8 S$ tmp3(2)(1) [7:0] $end $var wire 8 [$ tmp3(2)(2) [7:0] $end $var wire 8 c$ tmp3(2)(3) [7:0] $end $var wire 8 k$ tmp3(3)(1) [7:0] $end $var wire 8 s$ tmp3(3)(2) [7:0] $end $var wire 8 {$ tmp3(3)(3) [7:0] $end $var wire 8 %% tmp3(4)(1) [7:0] $end $var wire 8 -% tmp3(4)(2) [7:0] $end $var wire 8 5% tmp3(4)(3) [7:0] $end $var wire 8 =% tmp4(1)(1) [7:0] $end $var wire 8 E% tmp4(1)(2) [7:0] $end $var wire 8 M% tmp4(1)(3) [7:0] $end $var wire 8 U% tmp4(2)(1) [7:0] $end $var wire 8 ]% tmp4(2)(2) [7:0] $end $var wire 8 e% tmp4(2)(3) [7:0] $end $var wire 8 m% tmp4(3)(1) [7:0] $end $var wire 8 u% tmp4(3)(2) [7:0] $end $var wire 8 }% tmp4(3)(3) [7:0] $end $var wire 8 '& tmp4(4)(1) [7:0] $end $var wire 8 /& tmp4(4)(2) [7:0] $end $var wire 8 7& tmp4(4)(3) [7:0] $end $var wire 8 ?& tmp5(1)(1) [7:0] $end $var wire 8 G& tmp5(1)(2) [7:0] $end $var wire 8 O& tmp5(1)(3) [7:0] $end $var wire 8 W& tmp5(2)(1) [7:0] $end $var wire 8 _& tmp5(2)(2) [7:0] $end $var wire 8 g& tmp5(2)(3) [7:0] $end $var wire 8 o& tmp5(3)(1) [7:0] $end $var wire 8 w& tmp5(3)(2) [7:0] $end $var wire 8 !' tmp5(3)(3) [7:0] $end $var wire 8 )' tmp5(4)(1) [7:0] $end $var wire 8 1' tmp5(4)(2) [7:0] $end $var wire 8 9' tmp5(4)(3) [7:0] $end $var wire 8 A' tmp6(1)(1) [7:0] $end $var wire 8 I' tmp6(1)(2) [7:0] $end $var wire 8 Q' tmp6(1)(3) [7:0] $end $var wire 8 Y' tmp6(2)(1) [7:0] $end $var wire 8 a' tmp6(2)(2) [7:0] $end $var wire 8 i' tmp6(2)(3) [7:0] $end $var wire 8 q' tmp6(3)(1) [7:0] $end $var wire 8 y' tmp6(3)(2) [7:0] $end $var wire 8 #( tmp6(3)(3) [7:0] $end $var wire 8 +( tmp6(4)(1) [7:0] $end $var wire 8 3( tmp6(4)(2) [7:0] $end $var wire 8 ;( tmp6(4)(3) [7:0] $end $var wire 8 C( tmp7(2)(1) [7:0] $end $var wire 8 K( tmp7(2)(2) [7:0] $end $var wire 8 S( tmp7(2)(3) [7:0] $end $var wire 8 [( tmp7(3)(1) [7:0] $end $var wire 8 c( tmp7(3)(2) [7:0] $end $var wire 8 k( tmp7(3)(3) [7:0] $end $var wire 8 s( tmp7(4)(1) [7:0] $end $var wire 8 {( tmp7(4)(2) [7:0] $end $var wire 8 %) tmp7(4)(3) [7:0] $end $var wire 8 -) tmp7(5)(1) [7:0] $end $var wire 8 5) tmp7(5)(2) [7:0] $end $var wire 8 =) tmp7(5)(3) [7:0] $end $var wire 8 Y3 tmp8(0)(1) [7:0] $end $var wire 8 a3 tmp8(0)(2) [7:0] $end $var wire 8 i3 tmp8(0)(3) [7:0] $end $var wire 8 q3 tmp8(1)(1) [7:0] $end $var wire 8 y3 tmp8(1)(2) [7:0] $end $var wire 8 #4 tmp8(1)(3) [7:0] $end $var wire 8 E) tmp8(2)(1) [7:0] $end $var wire 8 M) tmp8(2)(2) [7:0] $end $var wire 8 U) tmp8(2)(3) [7:0] $end $var wire 8 ]) tmp8(3)(1) [7:0] $end $var wire 8 e) tmp8(3)(2) [7:0] $end $var wire 8 m) tmp8(3)(3) [7:0] $end $var wire 8 u) tmp8(4)(1) [7:0] $end $var wire 8 }) tmp8(4)(2) [7:0] $end $var wire 8 '* tmp8(4)(3) [7:0] $end $var wire 8 /* tmp8(5)(1) [7:0] $end $var wire 8 7* tmp8(5)(2) [7:0] $end $var wire 8 ?* tmp8(5)(3) [7:0] $end $var wire 8 +4 tmp8(6)(1) [7:0] $end $var wire 8 34 tmp8(6)(2) [7:0] $end $var wire 8 ;4 tmp8(6)(3) [7:0] $end $var wire 8 C4 tmp8(7)(1) [7:0] $end $var wire 8 K4 tmp8(7)(2) [7:0] $end $var wire 8 S4 tmp8(7)(3) [7:0] $end $var wire 8 G* tmp9(4)(1) [7:0] $end $var wire 8 O* tmp9(4)(2) [7:0] $end $var wire 8 W* tmp9(4)(3) [7:0] $end $var wire 8 _* tmp9(5)(1) [7:0] $end $var wire 8 g* tmp9(5)(2) [7:0] $end $var wire 8 o* tmp9(5)(3) [7:0] $end $var wire 8 w* tmp9(6)(1) [7:0] $end $var wire 8 !+ tmp9(6)(2) [7:0] $end $var wire 8 )+ tmp9(6)(3) [7:0] $end $var wire 8 1+ tmp9(7)(1) [7:0] $end $var wire 8 9+ tmp9(7)(2) [7:0] $end $var wire 8 A+ tmp9(7)(3) [7:0] $end $upscope $end $scope module shifter4 $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 ]5 OFFSET [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 13 in [7:0] $end $var wire 8 K, out [7:0] $end $var wire 24 m5 pad [23:0] $end $var wire 3 s shift [2:0] $end $var wire 32 e5 tmp(2) [31:0] $end $var wire 32 S, tmp(3) [31:0] $end $var wire 32 [, tmp(4) [31:0] $end $var wire 32 c, tmp(5) [31:0] $end $upscope $end $scope module shifter5 $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 u5 OFFSET [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 13 in [7:0] $end $var wire 8 k, out [7:0] $end $var wire 3 s shift [2:0] $end $var wire 32 s, tmp [31:0] $end $upscope $end $scope module shifter6 $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 u5 OFFSET [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 13 in [7:0] $end $var wire 8 {, out [7:0] $end $var wire 3 s shift [2:0] $end $var wire 32 %- tmp [31:0] $end $upscope $end $scope module shifter7 $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 13 in [7:0] $end $var wire 8 -- out [7:0] $end $var wire 3 s shift [2:0] $end $var wire 32 5- tmp [31:0] $end $upscope $end $scope module shifter8 $end $var wire 32 w2 DEPTH [31:0] $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 13 in [7:0] $end $var wire 8 =- out [7:0] $end $var wire 3 s shift [2:0] $end $var wire 32 E- tmp [0:31] $end $upscope $end $scope module though0 $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 7. in [7:0] $end $var wire 8 ?. out [7:0] $end $var wire 1 K0 unpack_tmp(0) $end $var wire 1 S0 unpack_tmp(1) $end $var wire 1 [0 unpack_tmp(2) $end $var wire 1 c0 unpack_tmp(3) $end $var wire 1 k0 unpack_tmp(4) $end $var wire 1 s0 unpack_tmp(5) $end $var wire 1 {0 unpack_tmp(6) $end $var wire 1 %1 unpack_tmp(7) $end $scope module i_pack2unpack $end $var wire 32 !3 WIDTH [31:0] $end $var wire 8 7. in [7:0] $end $var wire 1 -1 out(0) $end $var wire 1 .1 out(1) $end $var wire 1 /1 out(2) $end $var wire 1 01 out(3) $end $var wire 1 11 out(4) $end $var wire 1 21 out(5) $end $var wire 1 31 out(6) $end $var wire 1 41 out(7) $end $upscope $end $scope module i_unpack2pack $end $var wire 32 !3 WIDTH [31:0] $end $var wire 1 m1 in(0) $end $var wire 1 n1 in(1) $end $var wire 1 o1 in(2) $end $var wire 1 p1 in(3) $end $var wire 1 q1 in(4) $end $var wire 1 r1 in(5) $end $var wire 1 s1 in(6) $end $var wire 1 t1 in(7) $end $var wire 8 ?. out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000001001000110100010101100111 # b00100000000000000000000000000000 + b00000001001000110100000000100111 3 b00000000000000000000000000000011 ; 1C 0K 0S 1[ 0c 1d b000 s b10001110 { b10001110 %! b10001110 -! b10001110 5! b10001110 =! b10001110 E! b10001110 M! b10001110 U! b10001110 ]! b10001110 e! b10001110 m! b10001110 u! b10001110 }! b10001110 '" b10001110 /" b10001110 7" b10001110 ?" b10001110 G" b10001110 O" b10001110 W" b10001110 _" b10001110 g" b10001110 o" b10001110 w" b10001110 !# b10001110 )# b10001110 1# b10001110 9# b10001110 A# b10001110 I# b10001110 Q# b10001110 Y# b10001110 a# b10001110 i# b10001110 q# b10001110 y# b10001110 #$ b10001110 +$ b10001110 3$ b10001110 ;$ b10001110 C$ b10001110 K$ b10001110 S$ b10001110 [$ b10001110 c$ b10001110 k$ b10001110 s$ b10001110 {$ b10001110 %% b10001110 -% b10001110 5% b10001110 =% b10001110 E% b10001110 M% b10001110 U% b10001110 ]% b10001110 e% b10001110 m% b10001110 u% b10001110 }% b10001110 '& b10001110 /& b10001110 7& b10001110 ?& b10001110 G& b10001110 O& b10001110 W& b10001110 _& b10001110 g& b10001110 o& b10001110 w& b10001110 !' b10001110 )' b10001110 1' b10001110 9' b10001110 A' b10001110 I' b10001110 Q' b10001110 Y' b10001110 a' b10001110 i' b10001110 q' b10001110 y' b10001110 #( b10001110 +( b10001110 3( b10001110 ;( b10001110 C( b10001110 K( b10001110 S( b10001110 [( b10001110 c( b10001110 k( b10001110 s( b10001110 {( b10001110 %) b10001110 -) b10001110 5) b10001110 =) b10001110 E) b10001110 M) b10001110 U) b10001110 ]) b10001110 e) b10001110 m) b10001110 u) b10001110 }) b10001110 '* b10001110 /* b10001110 7* b10001110 ?* b10001110 G* b10001110 O* b10001110 W* b10001110 _* b10001110 g* b10001110 o* b10001110 w* b10001110 !+ b10001110 )+ b10001110 1+ b10001110 9+ b10001110 A+ b10001110 I+ b10001110 Q+ b10001110 Y+ b10001110 a+ b10001110 i+ b10001110 q+ b10001110 y+ b10001110 #, b10001110 +, b10001110 3, b10001110 ;, b10001110 C, b10001110 K, b00000000000000000000000010001110 S, b00000000000000000000000010001110 [, b00000000000000000000000010001110 c, b10001110 k, b10001110100011101000111010001110 s, b10001110 {, b10001110100011101000111010001110 %- b10001110 -- b10001110100011101000111010001110 5- b10001110 =- b10001110100011101000111010001110 E- b10001110 M- b10001110 N- b10001110 O- b10001110 P- b10001110 Q- b10001110 R- b10001110 S- b10001110 T- b10001110 U- b10001110 7. b10001110 ?. b10001110 G. b10001110 O. b10001110 W. b10001110 _. b10001110 g. b10001110 o. b10001110 w. b10001110 !/ b10001110 )/ b10001110 1/ b10001110 9/ b10001110 A/ b10001110 I/ b10001110 Q/ b10001110 Y/ b10001110 a/ b10001110 i/ b10001110 q/ b10001110 y/ b10001110 #0 b10001110 +0 b10001110 30 b10001110 ;0 b10001110 C0 1K0 0S0 0[0 0c0 1k0 1s0 1{0 0%1 0-1 1.1 1/1 101 011 021 031 141 0m1 1n1 1o1 1p1 0q1 0r1 0s1 1t1 0O2 b00000000000000000000000000000000 W2 0_2 0g2 0o2 b00000000000000000000000000000011 w2 b00000000000000000000000000001000 !3 b00000000000000000000000000001001 )3 b10001110 13 b1000111001000111101000111101000111101000011101000011101000011101 93 b11111111111111111111111111111101 I3 b00000000000000000000000000000001 Q3 b00000000 Y3 b00000000 a3 b00000000 i3 b00000000 q3 b00000000 y3 b00000000 #4 b00000000 +4 b00000000 34 b00000000 ;4 b00000000 C4 b00000000 K4 b00000000 S4 b00000000 [4 b00000000 c4 b00000000 k4 b00000000 s4 b00000000 {4 b00000000 %5 b00000000 -5 b00000000 55 b00000000 =5 b00000000 E5 b00000000 M5 b00000000 U5 b00000000000000000000000000000010 ]5 b00000000000000000000000010001110 e5 b000000000000000000000000 m5 b11111111111111111111111111111110 u5 b00000000000000000000000000000000 }5 #10 b001 s b01000111 { b01000111 %! b01000111 -! b01000111 5! b01000111 =! b01000111 E! b01000111 M! b01000111 U! b01000111 ]! b01000111 e! b01000111 m! b01000111 u! b01000111 }! b01000111 '" b01000111 /" b01000111 O" b01000111 W" b01000111 _" b01000111 g" b01000111 o" b01000111 w" b01000111 !# b01000111 )# b01000111 1# b01000111 Q# b01000111 Y# b01000111 a# b01000111 i# b01000111 q# b01000111 y# b01000111 #$ b01000111 +$ b01000111 3$ b01000111 S$ b01000111 [$ b01000111 c$ b01000111 k$ b01000111 s$ b01000111 {$ b01000111 %% b01000111 -% b01000111 5% b01000111 U% b01000111 ]% b01000111 e% b01000111 m% b01000111 u% b01000111 }% b01000111 '& b01000111 /& b01000111 7& b01000111 W& b01000111 _& b01000111 g& b01000111 o& b01000111 w& b01000111 !' b01000111 )' b01000111 1' b01000111 9' b01000111 Y' b01000111 a' b01000111 i' b01000111 q' b01000111 y' b01000111 #( b01000111 +( b01000111 3( b01000111 ;( b01000111 [( b01000111 c( b01000111 k( b01000111 s( b01000111 {( b01000111 %) b01000111 -) b01000111 5) b01000111 =) b01000111 ]) b01000111 e) b01000111 m) b01000111 u) b01000111 }) b01000111 '* b01000111 /* b01000111 7* b01000111 ?* b01000111 _* b01000111 g* b01000111 o* b01000111 w* b01000111 !+ b01000111 )+ b01000111 1+ b01000111 9+ b01000111 A+ b01000111 a+ b01000111 i+ b01000111 q+ b01000111 y+ b01000111 #, b01000111 +, b01000111 3, b01000111 ;, b01000111 C, b01000111 K, b00000000000000000000000001000111 S, b00000000000000000000000001000111 [, b00000000000000000000000001000111 c, b01000111 k, b10001110010001110100011101000111 s, b01000111 {, b10001110010001110100011101000111 %- b01000111 -- b10001110010001110100011101000111 5- b01000111 =- b10001110010001110100011101000111 E- b01000111 M- b01000111 N- b01000111 O- b01000111 P- b01000111 Q- b01000111 R- b01000111 S- b01000111 T- b01000111 U- b01000111 7. b01000111 ?. b01000111 G. b01000111 g. b01000111 o. b01000111 w. b01000111 !/ b01000111 )/ b01000111 1/ b01000111 9/ b01000111 A/ b01000111 a/ b01000111 i/ b01000111 q/ b01000111 y/ b01000111 #0 b01000111 +0 b01000111 30 b01000111 ;0 b01000111 C0 0K0 1S0 0k0 1%1 1-1 001 131 041 1m1 0p1 1s1 0t1 b00000000000000000000000000001001 W2 1g2 1o2 #15 0o2 #20 b010 s b10100011 { b10001110 %! b10100011 -! b10100011 5! b10100011 =! b10100011 E! b10100011 M! b10001110 U! b10100011 ]! b10100011 e! b10100011 m! b10100011 u! b10100011 }! b10100011 '" b10100011 /" b10001110 O" b10001110 W" b10001110 _" b10100011 g" b10100011 o" b10100011 w" b10100011 !# b10100011 )# b10100011 1# b10001110 Q# b10001110 Y# b10001110 a# b10100011 i# b10100011 q# b10100011 y# b10100011 #$ b10100011 +$ b10100011 3$ b10001110 S$ b10001110 [$ b10001110 c$ b10100011 k$ b10100011 s$ b10100011 {$ b10100011 %% b10100011 -% b10100011 5% b10001110 U% b10001110 ]% b10001110 e% b10100011 m% b10100011 u% b10100011 }% b10100011 '& b10100011 /& b10100011 7& b10001110 W& b10001110 _& b10001110 g& b10100011 o& b10100011 w& b10100011 !' b10100011 )' b10100011 1' b10100011 9' b10001110 Y' b10001110 a' b10001110 i' b10100011 q' b10100011 y' b10100011 #( b10100011 +( b10100011 3( b10100011 ;( b10001110 [( b10001110 c( b10001110 k( b10100011 s( b10100011 {( b10100011 %) b10100011 -) b10100011 5) b10100011 =) b10001110 ]) b10001110 e) b10001110 m) b10100011 u) b10100011 }) b10100011 '* b10100011 /* b10100011 7* b10100011 ?* b10001110 _* b10001110 g* b10001110 o* b10100011 w* b10100011 !+ b10100011 )+ b10100011 1+ b10100011 9+ b10100011 A+ b10001110 a+ b10001110 i+ b10001110 q+ b10100011 y+ b10100011 #, b10100011 +, b10100011 3, b10100011 ;, b10100011 C, b10100011 K, b00000000000000000000000010001110 S, b00000000000000000000000010100011 [, b00000000000000000000000010100011 c, b10100011 k, b10001110100011101010001110100011 s, b10100011 {, b10001110100011101010001110100011 %- b10100011 -- b10001110100011101010001110100011 5- b10100011 =- b10001110100011101010001110100011 E- b10100011 M- b10100011 N- b10100011 O- b10100011 P- b10100011 Q- b10100011 R- b10100011 S- b10100011 T- b10100011 U- b10100011 7. b10100011 ?. b10100011 G. b10001110 g. b10001110 o. b10001110 w. b10100011 !/ b10100011 )/ b10100011 1/ b10100011 9/ b10100011 A/ b10001110 a/ b10001110 i/ b10001110 q/ b10100011 y/ b10100011 #0 b10100011 +0 b10100011 30 b10100011 ;0 b10100011 C0 1K0 0S0 1[0 0s0 0/1 121 031 141 0o1 1r1 0s1 1t1 1o2 #25 0o2 #30 b011 s b11010001 { b01000111 %! b11010001 -! b11010001 5! b11010001 =! b11010001 E! b11010001 M! b01000111 U! b11010001 ]! b11010001 e! b11010001 m! b11010001 u! b11010001 }! b11010001 '" b11010001 /" b01000111 O" b01000111 W" b01000111 _" b11010001 g" b11010001 o" b11010001 w" b11010001 !# b11010001 )# b11010001 1# b01000111 Q# b01000111 Y# b01000111 a# b11010001 i# b11010001 q# b11010001 y# b11010001 #$ b11010001 +$ b11010001 3$ b01000111 S$ b01000111 [$ b01000111 c$ b11010001 k$ b11010001 s$ b11010001 {$ b11010001 %% b11010001 -% b11010001 5% b01000111 U% b01000111 ]% b01000111 e% b11010001 m% b11010001 u% b11010001 }% b11010001 '& b11010001 /& b11010001 7& b01000111 W& b01000111 _& b01000111 g& b11010001 o& b11010001 w& b11010001 !' b11010001 )' b11010001 1' b11010001 9' b01000111 Y' b01000111 a' b01000111 i' b11010001 q' b11010001 y' b11010001 #( b11010001 +( b11010001 3( b11010001 ;( b01000111 [( b01000111 c( b01000111 k( b11010001 s( b11010001 {( b11010001 %) b11010001 -) b11010001 5) b11010001 =) b01000111 ]) b01000111 e) b01000111 m) b11010001 u) b11010001 }) b11010001 '* b11010001 /* b11010001 7* b11010001 ?* b01000111 _* b01000111 g* b01000111 o* b11010001 w* b11010001 !+ b11010001 )+ b11010001 1+ b11010001 9+ b11010001 A+ b01000111 a+ b01000111 i+ b01000111 q+ b11010001 y+ b11010001 #, b11010001 +, b11010001 3, b11010001 ;, b11010001 C, b11010001 K, b00000000000000000000000001000111 S, b00000000000000000000000011010001 [, b00000000000000000000000011010001 c, b11010001 k, b10001110010001111101000111010001 s, b11010001 {, b10001110010001111101000111010001 %- b11010001 -- b10001110010001111101000111010001 5- b11010001 =- b10001110010001111101000111010001 E- b11010001 M- b11010001 N- b11010001 O- b11010001 P- b11010001 Q- b11010001 R- b11010001 S- b11010001 T- b11010001 U- b11010001 7. b11010001 ?. b11010001 G. b01000111 g. b01000111 o. b01000111 w. b11010001 !/ b11010001 )/ b11010001 1/ b11010001 9/ b11010001 A/ b01000111 a/ b01000111 i/ b01000111 q/ b11010001 y/ b11010001 #0 b11010001 +0 b11010001 30 b11010001 ;0 b11010001 C0 1S0 0[0 1c0 0{0 0.1 111 021 131 0n1 1q1 0r1 1s1 1o2 #35 0o2 #40 b100 s b11101000 { b10001110 %! b10001110 -! b11101000 5! b11101000 =! b10001110 E! b11101000 M! b10001110 U! b10001110 ]! b10001110 e! b10001110 m! b10001110 u! b11101000 }! b11101000 '" b11101000 /" b10001110 O" b10001110 W" b10001110 _" b10001110 g" b10001110 o" b10001110 w" b11101000 !# b11101000 )# b11101000 1# b10001110 Q# b10001110 Y# b10001110 a# b10001110 i# b10001110 q# b10001110 y# b11101000 #$ b11101000 +$ b11101000 3$ b10001110 S$ b10001110 [$ b10001110 c$ b10001110 k$ b10001110 s$ b10001110 {$ b11101000 %% b11101000 -% b11101000 5% b10001110 U% b10001110 ]% b10001110 e% b10001110 m% b10001110 u% b10001110 }% b11101000 '& b11101000 /& b11101000 7& b10001110 W& b10001110 _& b10001110 g& b10001110 o& b10001110 w& b10001110 !' b11101000 )' b11101000 1' b11101000 9' b10001110 Y' b10001110 a' b10001110 i' b10001110 q' b10001110 y' b10001110 #( b11101000 +( b11101000 3( b11101000 ;( b10001110 [( b10001110 c( b10001110 k( b10001110 s( b10001110 {( b10001110 %) b11101000 -) b11101000 5) b11101000 =) b10001110 ]) b10001110 e) b10001110 m) b10001110 u) b10001110 }) b10001110 '* b11101000 /* b11101000 7* b11101000 ?* b10001110 _* b10001110 g* b10001110 o* b10001110 w* b10001110 !+ b10001110 )+ b11101000 1+ b11101000 9+ b11101000 A+ b10001110 a+ b10001110 i+ b10001110 q+ b10001110 y+ b10001110 #, b10001110 +, b11101000 3, b11101000 ;, b11101000 C, b11101000 K, b00000000000000000000000010001110 S, b00000000000000000000000010001110 [, b00000000000000000000000011101000 c, b11101000 k, b10001110100011101000111011101000 s, b11101000 {, b10001110100011101000111011101000 %- b11101000 -- b10001110100011101000111011101000 5- b11101000 =- b10001110100011101000111011101000 E- b11101000 M- b11101000 N- b11101000 O- b11101000 P- b11101000 Q- b11101000 R- b11101000 S- b11101000 T- b11101000 U- b11101000 7. b11101000 ?. b11101000 G. b10001110 g. b10001110 o. b10001110 w. b10001110 !/ b10001110 )/ b10001110 1/ b11101000 9/ b11101000 A/ b10001110 a/ b10001110 i/ b10001110 q/ b10001110 y/ b10001110 #0 b10001110 +0 b11101000 30 b11101000 ;0 b11101000 C0 1[0 0c0 1k0 0%1 0-1 101 011 121 0m1 1p1 0q1 1r1 1o2 #45 0o2 #50 b101 s b01110100 { b01000111 %! b01000111 -! b01110100 5! b01110100 =! b01000111 E! b01110100 M! b01000111 U! b01000111 ]! b01000111 e! b01000111 m! b01000111 u! b01110100 }! b01110100 '" b01110100 /" b01000111 O" b01000111 W" b01000111 _" b01000111 g" b01000111 o" b01000111 w" b01110100 !# b01110100 )# b01110100 1# b01000111 Q# b01000111 Y# b01000111 a# b01000111 i# b01000111 q# b01000111 y# b01110100 #$ b01110100 +$ b01110100 3$ b01000111 S$ b01000111 [$ b01000111 c$ b01000111 k$ b01000111 s$ b01000111 {$ b01110100 %% b01110100 -% b01110100 5% b01000111 U% b01000111 ]% b01000111 e% b01000111 m% b01000111 u% b01000111 }% b01110100 '& b01110100 /& b01110100 7& b01000111 W& b01000111 _& b01000111 g& b01000111 o& b01000111 w& b01000111 !' b01110100 )' b01110100 1' b01110100 9' b01000111 Y' b01000111 a' b01000111 i' b01000111 q' b01000111 y' b01000111 #( b01110100 +( b01110100 3( b01110100 ;( b01000111 [( b01000111 c( b01000111 k( b01000111 s( b01000111 {( b01000111 %) b01110100 -) b01110100 5) b01110100 =) b01000111 ]) b01000111 e) b01000111 m) b01000111 u) b01000111 }) b01000111 '* b01110100 /* b01110100 7* b01110100 ?* b01000111 _* b01000111 g* b01000111 o* b01000111 w* b01000111 !+ b01000111 )+ b01110100 1+ b01110100 9+ b01110100 A+ b01000111 a+ b01000111 i+ b01000111 q+ b01000111 y+ b01000111 #, b01000111 +, b01110100 3, b01110100 ;, b01110100 C, b01110100 K, b00000000000000000000000001000111 S, b00000000000000000000000001000111 [, b00000000000000000000000001110100 c, b01110100 k, b10001110010001110100011101110100 s, b01110100 {, b10001110010001110100011101110100 %- b01110100 -- b10001110010001110100011101110100 5- b01110100 =- b10001110010001110100011101110100 E- b01110100 M- b01110100 N- b01110100 O- b01110100 P- b01110100 Q- b01110100 R- b01110100 S- b01110100 T- b01110100 U- b01110100 7. b01110100 ?. b01110100 G. b01000111 g. b01000111 o. b01000111 w. b01000111 !/ b01000111 )/ b01000111 1/ b01110100 9/ b01110100 A/ b01000111 a/ b01000111 i/ b01000111 q/ b01000111 y/ b01000111 #0 b01000111 +0 b01110100 30 b01110100 ;0 b01110100 C0 0K0 1c0 0k0 1s0 1/1 001 111 041 1o1 0p1 1q1 0t1 1o2 #55 0o2 #60 b110 s b00111010 { b10001110 %! b10100011 -! b00111010 5! b00111010 =! b10100011 E! b00111010 M! b10001110 U! b10100011 ]! b10100011 e! b10100011 m! b10100011 u! b00111010 }! b00111010 '" b00111010 /" b10001110 O" b10001110 W" b10001110 _" b10100011 g" b10100011 o" b10100011 w" b00111010 !# b00111010 )# b00111010 1# b10001110 Q# b10001110 Y# b10001110 a# b10100011 i# b10100011 q# b10100011 y# b00111010 #$ b00111010 +$ b00111010 3$ b10001110 S$ b10001110 [$ b10001110 c$ b10100011 k$ b10100011 s$ b10100011 {$ b00111010 %% b00111010 -% b00111010 5% b10001110 U% b10001110 ]% b10001110 e% b10100011 m% b10100011 u% b10100011 }% b00111010 '& b00111010 /& b00111010 7& b10001110 W& b10001110 _& b10001110 g& b10100011 o& b10100011 w& b10100011 !' b00111010 )' b00111010 1' b00111010 9' b10001110 Y' b10001110 a' b10001110 i' b10100011 q' b10100011 y' b10100011 #( b00111010 +( b00111010 3( b00111010 ;( b10001110 [( b10001110 c( b10001110 k( b10100011 s( b10100011 {( b10100011 %) b00111010 -) b00111010 5) b00111010 =) b10001110 ]) b10001110 e) b10001110 m) b10100011 u) b10100011 }) b10100011 '* b00111010 /* b00111010 7* b00111010 ?* b10001110 _* b10001110 g* b10001110 o* b10100011 w* b10100011 !+ b10100011 )+ b00111010 1+ b00111010 9+ b00111010 A+ b10001110 a+ b10001110 i+ b10001110 q+ b10100011 y+ b10100011 #, b10100011 +, b00111010 3, b00111010 ;, b00111010 C, b00111010 K, b00000000000000000000000010001110 S, b00000000000000000000000010100011 [, b00000000000000000000000000111010 c, b00111010 k, b10001110100011101010001100111010 s, b00111010 {, b10001110100011101010001100111010 %- b00111010 -- b10001110100011101010001100111010 5- b00111010 =- b10001110100011101010001100111010 E- b00111010 M- b00111010 N- b00111010 O- b00111010 P- b00111010 Q- b00111010 R- b00111010 S- b00111010 T- b00111010 U- b00111010 7. b00111010 ?. b00111010 G. b10001110 g. b10001110 o. b10001110 w. b10100011 !/ b10100011 )/ b10100011 1/ b00111010 9/ b00111010 A/ b10001110 a/ b10001110 i/ b10001110 q/ b10100011 y/ b10100011 #0 b10100011 +0 b00111010 30 b00111010 ;0 b00111010 C0 0S0 1k0 0s0 1{0 1.1 0/1 101 031 1n1 0o1 1p1 0s1 1o2 #65 0o2 #70 b111 s b00011101 { b01000111 %! b11010001 -! b00011101 5! b00011101 =! b11010001 E! b00011101 M! b01000111 U! b11010001 ]! b11010001 e! b11010001 m! b11010001 u! b00011101 }! b00011101 '" b00011101 /" b01000111 O" b01000111 W" b01000111 _" b11010001 g" b11010001 o" b11010001 w" b00011101 !# b00011101 )# b00011101 1# b01000111 Q# b01000111 Y# b01000111 a# b11010001 i# b11010001 q# b11010001 y# b00011101 #$ b00011101 +$ b00011101 3$ b01000111 S$ b01000111 [$ b01000111 c$ b11010001 k$ b11010001 s$ b11010001 {$ b00011101 %% b00011101 -% b00011101 5% b01000111 U% b01000111 ]% b01000111 e% b11010001 m% b11010001 u% b11010001 }% b00011101 '& b00011101 /& b00011101 7& b01000111 W& b01000111 _& b01000111 g& b11010001 o& b11010001 w& b11010001 !' b00011101 )' b00011101 1' b00011101 9' b01000111 Y' b01000111 a' b01000111 i' b11010001 q' b11010001 y' b11010001 #( b00011101 +( b00011101 3( b00011101 ;( b01000111 [( b01000111 c( b01000111 k( b11010001 s( b11010001 {( b11010001 %) b00011101 -) b00011101 5) b00011101 =) b01000111 ]) b01000111 e) b01000111 m) b11010001 u) b11010001 }) b11010001 '* b00011101 /* b00011101 7* b00011101 ?* b01000111 _* b01000111 g* b01000111 o* b11010001 w* b11010001 !+ b11010001 )+ b00011101 1+ b00011101 9+ b00011101 A+ b01000111 a+ b01000111 i+ b01000111 q+ b11010001 y+ b11010001 #, b11010001 +, b00011101 3, b00011101 ;, b00011101 C, b00011101 K, b00000000000000000000000001000111 S, b00000000000000000000000011010001 [, b00000000000000000000000000011101 c, b00011101 k, b10001110010001111101000100011101 s, b00011101 {, b10001110010001111101000100011101 %- b00011101 -- b10001110010001111101000100011101 5- b00011101 =- b10001110010001111101000100011101 E- b00011101 M- b00011101 N- b00011101 O- b00011101 P- b00011101 Q- b00011101 R- b00011101 S- b00011101 T- b00011101 U- b00011101 7. b00011101 ?. b00011101 G. b01000111 g. b01000111 o. b01000111 w. b11010001 !/ b11010001 )/ b11010001 1/ b00011101 9/ b00011101 A/ b01000111 a/ b01000111 i/ b01000111 q/ b11010001 y/ b11010001 #0 b11010001 +0 b00011101 30 b00011101 ;0 b00011101 C0 0[0 1s0 0{0 1%1 1-1 0.1 1/1 021 1m1 0n1 1o1 0r1 1o2 #75 0o2 #80 b000 s b10001110 { b10001110 %! b10001110 -! b10001110 5! b10001110 =! b10001110 E! b10001110 M! b10001110 U! b10001110 ]! b10001110 e! b10001110 m! b10001110 u! b10001110 }! b10001110 '" b10001110 /" b10001110 O" b10001110 W" b10001110 _" b10001110 g" b10001110 o" b10001110 w" b10001110 !# b10001110 )# b10001110 1# b10001110 Q# b10001110 Y# b10001110 a# b10001110 i# b10001110 q# b10001110 y# b10001110 #$ b10001110 +$ b10001110 3$ b10001110 S$ b10001110 [$ b10001110 c$ b10001110 k$ b10001110 s$ b10001110 {$ b10001110 %% b10001110 -% b10001110 5% b10001110 U% b10001110 ]% b10001110 e% b10001110 m% b10001110 u% b10001110 }% b10001110 '& b10001110 /& b10001110 7& b10001110 W& b10001110 _& b10001110 g& b10001110 o& b10001110 w& b10001110 !' b10001110 )' b10001110 1' b10001110 9' b10001110 Y' b10001110 a' b10001110 i' b10001110 q' b10001110 y' b10001110 #( b10001110 +( b10001110 3( b10001110 ;( b10001110 [( b10001110 c( b10001110 k( b10001110 s( b10001110 {( b10001110 %) b10001110 -) b10001110 5) b10001110 =) b10001110 ]) b10001110 e) b10001110 m) b10001110 u) b10001110 }) b10001110 '* b10001110 /* b10001110 7* b10001110 ?* b10001110 _* b10001110 g* b10001110 o* b10001110 w* b10001110 !+ b10001110 )+ b10001110 1+ b10001110 9+ b10001110 A+ b10001110 a+ b10001110 i+ b10001110 q+ b10001110 y+ b10001110 #, b10001110 +, b10001110 3, b10001110 ;, b10001110 C, b10001110 K, b00000000000000000000000010001110 S, b00000000000000000000000010001110 [, b00000000000000000000000010001110 c, b10001110 k, b10001110100011101000111010001110 s, b10001110 {, b10001110100011101000111010001110 %- b10001110 -- b10001110100011101000111010001110 5- b10001110 =- b10001110100011101000111010001110 E- b10001110 M- b10001110 N- b10001110 O- b10001110 P- b10001110 Q- b10001110 R- b10001110 S- b10001110 T- b10001110 U- b10001110 7. b10001110 ?. b10001110 G. b10001110 g. b10001110 o. b10001110 w. b10001110 !/ b10001110 )/ b10001110 1/ b10001110 9/ b10001110 A/ b10001110 a/ b10001110 i/ b10001110 q/ b10001110 y/ b10001110 #0 b10001110 +0 b10001110 30 b10001110 ;0 b10001110 C0 1K0 0c0 1{0 0%1 0-1 1.1 011 141 0m1 1n1 0q1 1t1 1o2 verilator-4.038/test_regress/t/t_time_vpi_1fs1fs.pl0000775000177100017500000000151113702133370022347 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator_st => 1); top_filename("t/t_time_vpi.v"); $Self->{main_time_multiplier} = 1e-15 / 1e-15; compile( v_flags2 => ['+define+time_scale_units=1fs +define+time_scale_prec=1fs', 't/t_time_vpi_c.cpp'], verilator_flags2 => ['--vpi'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_multitop_sig_bad.out0000664000177100017500000000122613702133370023071 0ustar wsnyderwsnyder%Warning-MULTITOP: t/t_multitop_sig.v:15:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' 7 | module a(in, out); | ^ : ... Top module 'b' 15 | module b(in, out); | ^ : ... Top module 'c' 23 | module c(uniq_in, uniq_out); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_case_huge.pl0000775000177100017500000000145613702133367021311 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats"], ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10); file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, ($Self->{vltmt} ? 0 : 8)); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_int.v0000664000177100017500000000470013702133370021020 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; enum integer { EP_State_IDLE , EP_State_CMDSHIFT0 , EP_State_CMDSHIFT13 , EP_State_CMDSHIFT14 , EP_State_CMDSHIFT15 , EP_State_CMDSHIFT16 , EP_State_DWAIT , EP_State_DSHIFT0 , EP_State_DSHIFT1 , EP_State_DSHIFT15 } m_state_xr, m_state2_xr; // Beginning of automatic ASCII enum decoding reg [79:0] m_stateAscii_xr; // Decode of m_state_xr always @(m_state_xr) begin case ({m_state_xr}) EP_State_IDLE: m_stateAscii_xr = "idle "; EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; EP_State_DWAIT: m_stateAscii_xr = "dwait "; EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; default: m_stateAscii_xr = "%Error "; endcase end // End of automatics integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); if (cyc==1) begin m_state_xr <= EP_State_IDLE; m_state2_xr <= EP_State_IDLE; end if (cyc==2) begin if (m_stateAscii_xr != "idle ") $stop; m_state_xr <= EP_State_CMDSHIFT13; if (m_state2_xr != EP_State_IDLE) $stop; m_state2_xr <= EP_State_CMDSHIFT13; end if (cyc==3) begin if (m_stateAscii_xr != "cmdshift13") $stop; m_state_xr <= EP_State_CMDSHIFT16; if (m_state2_xr != EP_State_CMDSHIFT13) $stop; m_state2_xr <= EP_State_CMDSHIFT16; end if (cyc==4) begin if (m_stateAscii_xr != "cmdshift16") $stop; m_state_xr <= EP_State_DWAIT; if (m_state2_xr != EP_State_CMDSHIFT16) $stop; m_state2_xr <= EP_State_DWAIT; end if (cyc==9) begin if (m_stateAscii_xr != "dwait ") $stop; if (m_state2_xr != EP_State_DWAIT) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_noprot_lib.pl0000775000177100017500000000231613702133370021523 0ustar wsnyderwsnyder#!/usr/bin/env perl # Makes the test run with tracing enabled by default, can be overridden # with --notrace unshift(@ARGV, "--trace"); if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios( vlt => 1, xsim => 1, ); $Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; top_filename("t/t_prot_lib.v"); # Tests the same code as t_prot_lib.pl but without --protect-lib compile( verilator_flags2 => ["t/t_prot_lib_secret.v"], xsim_flags2 => ["t/t_prot_lib_secret.v"], ); execute( check_finished => 1, ); if ($Self->{vlt} && $Self->{trace}) { # We can see the ports of the secret module file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/); # and we can see what's inside (because we didn't use --protect-lib) file_grep("$Self->{obj_dir}/simx.vcd", qr/secret_/); } ok(1); 1; verilator-4.038/test_regress/t/t_gen_for.pl0000775000177100017500000000105313702133370020770 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_param_another_bad.pl0000775000177100017500000000107413702133370025022 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_type3.pl0000775000177100017500000000105613702133370021600 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_var_dup_bad.out0000664000177100017500000001101013702133370022002 0ustar wsnyderwsnyder%Error: t/t_var_dup_bad.v:17:11: Duplicate declaration of signal: 'a' 17 | reg a; | ^ t/t_var_dup_bad.v:16:11: ... Location of original declaration 16 | reg a; | ^ %Error: t/t_var_dup_bad.v:20:12: Duplicate declaration of signal: 'l' 20 | integer l; | ^ t/t_var_dup_bad.v:19:12: ... Location of original declaration 19 | integer l; | ^ %Error: t/t_var_dup_bad.v:23:12: Duplicate declaration of signal: 'b' 23 | bit b; | ^ t/t_var_dup_bad.v:22:12: ... Location of original declaration 22 | bit b; | ^ %Error: t/t_var_dup_bad.v:26:11: Duplicate declaration of signal: 'o' 26 | output o; | ^ t/t_var_dup_bad.v:25:11: ... Location of original declaration 25 | output o; | ^ %Error: t/t_var_dup_bad.v:29:11: Duplicate declaration of signal: 'i' 29 | input i; | ^ t/t_var_dup_bad.v:28:11: ... Location of original declaration 28 | input i; | ^ %Error: t/t_var_dup_bad.v:32:11: Duplicate declaration of signal: 'oi' 32 | input oi; | ^~ t/t_var_dup_bad.v:31:11: ... Location of original declaration 31 | output oi; | ^~ %Error: t/t_var_dup_bad.v:39:15: Duplicate declaration of signal: 'org' 39 | output reg org; | ^~~ t/t_var_dup_bad.v:38:15: ... Location of original declaration 38 | output reg org; | ^~~ %Error: t/t_var_dup_bad.v:66:11: Duplicate declaration of signal: 'bad_reout_port' 66 | output bad_reout_port; | ^~~~~~~~~~~~~~ t/t_var_dup_bad.v:64:11: ... Location of original declaration 64 | output bad_reout_port | ^~~~~~~~~~~~~~ %Error: t/t_var_dup_bad.v:73:9: Duplicate declaration of signal: 'bad_rewire' : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2) 73 | wire bad_rewire; | ^~~~~~~~~~ t/t_var_dup_bad.v:70:16: ... Location of original declaration 70 | (output wire bad_rewire, | ^~~~~~~~~~ %Error: t/t_var_dup_bad.v:74:9: Duplicate declaration of signal: 'bad_rereg' 74 | reg bad_rereg; | ^~~~~~~~~ t/t_var_dup_bad.v:71:15: ... Location of original declaration 71 | output reg bad_rereg | ^~~~~~~~~ %Error: t/t_var_dup_bad.v:13:7: Duplicate declaration of port: 'oi' 13 | i, oi | ^~ t/t_var_dup_bad.v:31:11: ... Location of original declaration 31 | output oi; | ^~ %Error: t/t_var_dup_bad.v:50:4: Duplicate declaration of port: 'bad_duport' 50 | bad_duport | ^~~~~~~~~~ t/t_var_dup_bad.v:52:11: ... Location of original declaration 52 | output bad_duport; | ^~~~~~~~~~ %Error: t/t_var_dup_bad.v:58:11: Duplicate declaration of port: 'bad_mixport' 58 | output bad_mixport | ^~~~~~~~~~~ t/t_var_dup_bad.v:58:11: ... Location of original declaration 58 | output bad_mixport | ^~~~~~~~~~~ %Error: t/t_var_dup_bad.v:41:9: Can't find definition of variable: 'bad_duport' 41 | sub0 sub0(.*); | ^~~~ %Error: t/t_var_dup_bad.v:41:9: Duplicate pin connection: 'bad_duport' 41 | sub0 sub0(.*); | ^~~~ t/t_var_dup_bad.v:41:9: ... Location of original pin connection 41 | sub0 sub0(.*); | ^~~~ %Error: t/t_var_dup_bad.v:42:9: Can't find definition of variable: 'bad_mixport' : ... Suggested alternative: 'bad_duport' 42 | sub1 sub1(.*); | ^~~~ %Error: t/t_var_dup_bad.v:42:9: Duplicate pin connection: 'bad_mixport' 42 | sub1 sub1(.*); | ^~~~ t/t_var_dup_bad.v:42:9: ... Location of original pin connection 42 | sub1 sub1(.*); | ^~~~ %Error: t/t_var_dup_bad.v:43:9: Can't find definition of variable: 'bad_reout_port' : ... Suggested alternative: 'bad_duport' 43 | sub2 sub2(.*); | ^~~~ %Error: t/t_var_dup_bad.v:44:9: Can't find definition of variable: 'bad_rewire' 44 | sub3 sub3(.*); | ^~~~ %Error: t/t_var_dup_bad.v:44:9: Can't find definition of variable: 'bad_rereg' : ... Suggested alternative: 'bad_rewire' 44 | sub3 sub3(.*); | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_math_signed5.v0000664000177100017500000001347013702133370021555 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `ifdef VERILATOR `define c(v,vs) ($c(vs)) // Don't constify a value `else `define c(v,vs) (v) `endif module t (/*AUTOARG*/ // Outputs ow4_u ); bit fail; reg signed [3:0] w4_s; reg signed [4:0] w5_s; reg [2:0] w3_u; reg [3:0] w4_u; reg [4:0] w5_u; reg [5:0] w6_u; reg [15:0] w16a_u; reg [15:0] w16_u; reg [31:0] w32_u; real r; reg signed [4:0] bug754_a; integer i; //verilator lint_off WIDTH wire a = (5'b0 == (5'sb11111 >>> 3'd7)); wire b = (5'sb11111 == (5'sb11111 >>> 3'd7)); wire c = (1'b0+(5'sb11111 >>> 3'd7)); wire d = (1'sb0+(5'sb11111 >>> 3'd7)); wire e = (5'b0 == (5'sb11111 / 5'sd3)); wire f = (5'sb0 == (5'sb11111 / 5'sd3)); wire g = (5'b01010 == (5'b11111 / 5'sd3)); initial begin // verilator lint_off STMTDLY #1; `ifdef VCS // I-2014.03 `checkh({a, b, c, d, e, f, g}, 7'b1101111); `else `checkh({a, b, c, d, e, f, g}, 7'b1101011); `endif //====================================================================== if ((-1 >>> 3) != -1) $stop; // Decimals are signed i = 3'sb111 >>> 3; `checkh(i, -1); i = -1 >>> 3; `checkh(i, -1); bug754_a = -1; w4_u = |0 != (bug754_a >>> 3'd7); `checkh(w4_u, 4'b0); // Sanity check: -1>>7 == -1 w5_u = (5'sb11111 >>> 3'd7); `checkh(w5_u, 5'b11111); // bug756 w4_u = (5'b0 == (5'sb11111 >>> 3'd7)); `checkh(w4_u, 4'b0001); w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); // Exp 0 Vlt 0 `checkh(w4_u, 4'b0001); w4_u = ((5'b01111 == (5'sb11111 / 5'sd2))); // Strength-reduces to >>> `ifdef VCS // I-2014.03 `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate `else `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... `endif // Does == sign propagate from lhs to rhs? Yes, but not in VCS w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero `ifdef VCS // I-2014.03 `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate // Somewhat questionable, as spec says division signed depends on only LHS and RHS, however differs from others `else `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... `endif w4_u = (1'b0+(5'sb11111 >>> 3'd7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter `checkh(w4_u, 4'b0000); w4_u = (5'sb0 == (5'sb11111 / 5'sd3)); // Must be signed result (-1/3) to make this result zero `checkh(w4_u, 4'b0001); // Does == width propagate from lhs to rhs? Yes w4_u = (3'b100==(3'b111 << 2)); `checkh(w4_u, 4'b0001); w4_u = (4'b100==(3'b111 << 2)); `checkh(w4_u, 4'b0000); w4_u = (4'b1100==(3'b111 << 2)); `checkh(w4_u, 4'b0001); // Does >>> sign propagate from input same as for +? Yes w4_u = (1'b0+(5'sb11111 >>> 3'd7)); `checkh(w4_u, 4'b0000); w4_u = (1'sb0+(5'sb11111 >>> 3'd7)); `checkh(w4_u, 4'b1111); // Does << width propagate from input same as for +? Yes w4_u = (3'b0+(3'b111 << 2)); `checkh(w4_u, 4'b1100); // width 4 =='s LHS w4_u = (4'b0+(3'b111 << 2)); `checkh(w4_u, 4'b1100); w4_u = (5'sb11111 == (5'sb11111 >>> 3'd7)); // WHAT? Signedness does propagate across ==????? `checkh(w4_u, 4'b0001); w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); `checkh(w4_u, 4'b0001); // bug756 w5_s = -1; w3_u = 7; w4_u = |0 != (w5_s >>> w3_u); `checkh(w4_u, 4'b0000); // bug763 w3_u = 2; w4_u = (w3_u >> 2'b11) >> 1; `checkh(w4_u, 4'b0000); // bug766 w16a_u = 16'h1234; w16_u = (w16a_u >> 16) >>> 32'h7ffffff1; `checkh(w16_u, 16'h0000); // bug768 w4_s = 4'sd4; w4_u = $signed(5'd1 > w4_s-w4_s); `checkh(w4_u, 4'b1111); w4_s = `c(4,"4"); // Eval at runtime w4_u = $signed(5'd1 > w4_s-w4_s); `checkh(w4_u, 4'b1111); // bug772 w4_s = w4_u << 1 <<< 0/0; `ifndef VERILATOR // In v4 can't check value as not 4-state `checkh(w4_s, 4'bxxxx); `endif // bug773 w5_u = `c(31, 31); w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u); `checkh(w5_s, 5'b0); // bug774 w4_u = `c(4, 5); w6_u = `c(6, 35); w4_u = 64'd0 | (w4_u << w6_u); `checkh(w4_u, 0); // bug776 w4_u = `c(4, 1); w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u); `checkh(w4_u, 4'b1111); // bug828 // verilator lint_off WIDTH w32_u = 32'(signed'({4'b0001,5'b10000}) << 3); `checkh(w32_u, 32'h0000_0180); w32_u = 32'(signed'({4'b0011,5'b10000}) << 3); `checkh(w32_u, 32'h0000_0380); w32_u = signed'(32'({4'b0001,5'b10000}) << 3); `checkh(w32_u, 32'h0000_0180); w32_u = signed'(32'({4'b0011,5'b10000}) << 3); `checkh(w32_u, 32'h0000_0380); // verilator lint_on WIDTH w32_u = 32'(signed'({4'b0011,5'b10000})) << 3; // Check no width warning `checkh(w32_u, 32'h0000_0380); if (fail) $stop; $write("*-* All Finished *-*\n"); $finish; end // bug775 output [3:0] ow4_u; // Must be consumed assign ow4_u = ((0/0) ? 1 : 2) % 0; endmodule verilator-4.038/test_regress/t/t_interface2.v0000664000177100017500000000477113702133370021234 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; counter_io c1_data(); counter_io c2_data(); //counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells counter_io c3_data(); counter_ansi c1 (.clkm(clk), .c_data(c1_data), .i_value(4'h1)); counter_ansi c2 (.clkm(clk), .c_data(c2_data), .i_value(4'h2)); `ifdef VERILATOR counter_ansi `else counter_nansi `endif /**/ c3 (.clkm(clk), .c_data(c3_data), .i_value(4'h3)); initial begin c1_data.value = 4'h4; c2_data.value = 4'h5; c3_data.value = 4'h6; end always @ (posedge clk) begin cyc <= cyc + 1; if (cyc<2) begin c1_data.reset <= 1; c2_data.reset <= 1; c3_data.reset <= 1; end if (cyc==2) begin c1_data.reset <= 0; c2_data.reset <= 0; c3_data.reset <= 0; end if (cyc==3) begin if (c1_data.get_lcl() != 12345) $stop; end if (cyc==20) begin $write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc, c1_data.value, c1_data.reset, c2_data.value, c2_data.reset, c3_data.value, c3_data.reset); if (c1_data.value != 2) $stop; if (c2_data.value != 3) $stop; if (c3_data.value != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule interface counter_io; logic [3:0] value; logic reset; integer lcl; task set_lcl (input integer a); lcl=a; endtask function integer get_lcl (); return lcl; endfunction endinterface interface ifunused; logic unused; endinterface module counter_ansi ( input clkm, counter_io c_data, input logic [3:0] i_value ); initial begin c_data.set_lcl(12345); end always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_ansi `ifndef VERILATOR // non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. module counter_nansi(clkm, c_data, i_value); input clkm; counter_io c_data; input logic [3:0] i_value; always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_nansi `endif module modunused (ifunused ifinunused); ifunused ifunused(); endmodule verilator-4.038/test_regress/t/t_timescale_default.pl0000775000177100017500000000113513702133370023024 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_cover_sva_trace.out0000664000177100017500000000405213702133370022711 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Thu Oct 24 09:44:07 2019 $end $timescale 1ps $end $scope module top $end $var wire 1 ) clk $end $scope module t $end $var wire 1 ) clk $end $var wire 32 # cyc [31:0] $end $var wire 1 % toggle $end $scope module suba $end $var wire 1 ) clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 & cyc_eq_5_vlCoverageUserTrace [31:0] $end $var wire 1 % toggle $end $upscope $end $scope module subb $end $var wire 1 ) clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 ' cyc_eq_5_vlCoverageUserTrace [31:0] $end $var wire 1 % toggle $end $upscope $end $scope module subc $end $var wire 1 ) clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 ( cyc_eq_5_vlCoverageUserTrace [31:0] $end $var wire 1 % toggle $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # b00000000000000000000000000000001 $ 0% b00000000000000000000000000000000 & b00000000000000000000000000000000 ' b00000000000000000000000000000000 ( 0) #10 b00000000000000000000000000000010 # b00000000000000000000000000000010 $ 1) #15 0) #20 b00000000000000000000000000000011 # b00000000000000000000000000000011 $ 1% 1) #25 0) #30 b00000000000000000000000000000100 # b00000000000000000000000000000100 $ 0% 1) #35 0) #40 b00000000000000000000000000000101 # b00000000000000000000000000000101 $ 1% 1) #45 0) #50 b00000000000000000000000000000110 # b00000000000000000000000000000110 $ 0% b00000000000000000000000000000001 & b00000000000000000000000000000001 ' b00000000000000000000000000000001 ( 1) #55 0) #60 b00000000000000000000000000000111 # b00000000000000000000000000000111 $ 1% 1) #65 0) #70 b00000000000000000000000000001000 # b00000000000000000000000000001000 $ 0% 1) #75 0) #80 b00000000000000000000000000001001 # b00000000000000000000000000001001 $ 1% 1) #85 0) #90 b00000000000000000000000000001010 # b00000000000000000000000000001010 $ 0% 1) #95 0) #100 b00000000000000000000000000001011 # b00000000000000000000000000001011 $ 1% 1) verilator-4.038/test_regress/t/t_enum_type_methods.pl0000775000177100017500000000105313702133370023101 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_udp_noname.v0000664000177100017500000000145413702133370021332 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg a; wire o; udp (o, a); integer cyc; initial cyc=0; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; a <= cyc[0]; if (cyc==0) begin end else if (cyc<90) begin if (a != !cyc[0]) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule primitive udp(o,a); output o; input a; `ifdef verilator wire o = ~a; `else table //o a 0 : 1; 1 : 0; endtable `endif endprimitive verilator-4.038/test_regress/t/t_select_bad_range2.v0000664000177100017500000000240713702133370022527 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [1:0] in; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [1:0] out10; // From test of Test.v wire [1:0] out32; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out32 (out32[1:0]), .out10 (out10[1:0]), // Inputs .in (in[1:0])); // Test loop always @ (posedge clk) begin in <= in + 1; `ifdef TEST_VERBOSE $write("[%0t] in=%d out32=%d out10=%d\n",$time, in, out32, out10); `endif if (in==3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out32, out10, // Inputs in ); input [1:0] in; output [1:0] out32; output [1:0] out10; assign out32 = in[3:2]; assign out10 = in[1:0]; endmodule verilator-4.038/test_regress/t/t_math_swap.pl0000775000177100017500000000105313702133370021334 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_literal_bad.v0000664000177100017500000000040513702133370022470 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t ( ); localparam the_localparam = 8'd256; endmodule verilator-4.038/test_regress/t/t_class_vparam_unsup.out0000664000177100017500000000040113702133367023451 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_vparam_unsup.v:13:58: Unsupported: Parameter classes 13 | pure virtual function void funcname(paramed_class_t #(CTYPE_t) v); | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_typedef.v0000664000177100017500000000301413702133370020637 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 program t; parameter SIZE = 5; typedef vec_t; // Forward //UNSUP typedef vec_t; // Multi-forward is ok typedef reg [SIZE-1:0] vec_t; vec_t a; initial a =0; typedef bit [SIZE-1:0] vec_bit_t; vec_bit_t b; initial b =0; typedef int array_t [3]; typedef array_t array2_t [2]; array2_t ar [1]; // Define before use // Not sure how well supported this is elsewhere //UNSUP typedef preuse; //UNSUP preuse p; //UNSUP typedef int preuse; //reg [SIZE-1:0] a; initial a =0; //reg [SIZE-1:0] b; initial b =0; initial begin typedef logic [3:0][7:0] instr_mem_t; instr_mem_t a; a[0] = 8'h12; if (a[0] != 8'h12) $stop; end integer j; initial begin for (j=0;j<=(1< 1); compile( v_flags2 => ["t/t_dpi_threads_c.cpp --no-threads-coarsen"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dedupe_clk_gate.vlt0000664000177100017500000000012013702133370022631 0ustar wsnyderwsnyder`verilator_config clock_enable -module "clock_gate_latch" -var "clken_latched" verilator-4.038/test_regress/t/t_display_realtime.v0000664000177100017500000000104613702133370022531 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; always @ (posedge clk) begin cyc <= cyc + 1; $display("TestCase at %1t (%s)", $realtime, cyc[0] ? "Option1" : "Option2"); if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_math_concat0.v0000664000177100017500000000420113702133370021536 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [15:0] in = crc[15:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [15:0] outa; // From test of Test.v wire [15:0] outb; // From test of Test.v wire [15:0] outc; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .outa (outa[15:0]), .outb (outb[15:0]), .outc (outc[15:0]), // Inputs .clk (clk), .in (in[15:0])); // Aggregate outputs into a single result vector wire [63:0] result = {16'h0, outa, outb, outc}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h09be74b1b0f8c35d if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs outa, outb, outc, // Inputs clk, in ); input clk; input [15:0] in; output reg [15:0] outa; output reg [15:0] outb; output reg [15:0] outc; parameter WIDTH = 0; always @(posedge clk) begin outa <= {in}; outb <= {{WIDTH{1'b0}}, in}; outc <= {in, {WIDTH{1'b0}}}; end endmodule verilator-4.038/test_regress/t/t_inst_misarray_bad.out0000664000177100017500000000051613702133370023237 0ustar wsnyderwsnyder%Error: t/t_inst_misarray_bad.v:17:23: Illegal input port connection 'foo', mismatch between port which is an array, and expression which is not an array. (IEEE 1800-2017 7.6) : ... In instance t 17 | .foo(foo)); | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_altera_lpm_fifo_dc.pl0000775000177100017500000000120613702133367023150 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_property.v0000664000177100017500000000214713702133367022460 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; Test test (/*AUTOINST*/ // Inputs .clk (clk), .cyc (cyc[31:0])); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test ( input clk, input [31:0] cyc ); `ifdef FAIL_ASSERT_1 assert property (@(posedge clk) cyc==3) else $display("cyc != 3, cyc == %0d", cyc); `endif `ifdef FAIL_ASSERT_2 assert property (@(posedge clk) cyc!=3); `endif assert property (@(posedge clk) cyc < 100); restrict property (@(posedge clk) cyc==1); // Ignored in simulators // Unclocked is not supported: // assert property (cyc != 6); endmodule verilator-4.038/test_regress/t/t_protect_ids_key.out0000664000177100017500000000403313702133370022732 0ustar wsnyderwsnyder verilator-4.038/test_regress/t/t_var_pinsizes.vlt0000664000177100017500000000050413702133370022254 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config sc_bv -module "t" -var "ibv1_vlt" sc_bv -module "*" -var "ibv16_vlt" sc_bv -module "*" -var "obv*_vlt" verilator-4.038/test_regress/t/t_fuzz_eqne_bad.pl0000775000177100017500000000107413702133370022170 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_realcvt_bad.out0000664000177100017500000000041513702133370023037 0ustar wsnyderwsnyder%Warning-REALCVT: t/t_lint_realcvt_bad.v:10:11: Implicit conversion of real to integer 10 | i = 23.2; | ^~~~ ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_flag_invalid_bad.out0000664000177100017500000000004713702133370022771 0ustar wsnyderwsnyder%Error: Invalid option: --invalid-dash verilator-4.038/test_regress/t/t_param_seg.pl0000775000177100017500000000105313702133370021307 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unoptflat_simple_3.v0000664000177100017500000000235113702133370023011 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Simple test of unoptflat // // Demonstration of an UNOPTFLAT combinatorial loop using 3 bits and looping // through 2 sub-modules. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [2:0] x; initial begin x = 3'b000; end test1 test1i ( .clk (clk), .xvecin (x[1:0]), .xvecout (x[2:1])); test2 test2i ( .clk (clk), .xvecin (x[2:1]), .xvecout (x[1:0])); always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("x = %x\n", x); `endif if (x[1] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule // t module test1 (/*AUTOARG*/ // Inputs clk, xvecin, // Outputs xvecout ); input clk; input wire [1:0] xvecin; output wire [1:0] xvecout; assign xvecout = {xvecin[0], clk}; endmodule // test module test2 (/*AUTOARG*/ // Inputs clk, xvecin, // Outputs xvecout ); input clk; input wire [1:0] xvecin; output wire [1:0] xvecout; assign xvecout = {clk, xvecin[1]}; endmodule // test verilator-4.038/test_regress/t/t_pli_bad.v0000664000177100017500000000064513702133370020600 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer i; initial begin $unknown_pli_task; $unknown_pli_task("arg", i); i = $unknown_pli_function; i = $unknown_pli_function("arg", i); $stop; end endmodule verilator-4.038/test_regress/t/t_dpi_result_type_bad.v0000664000177100017500000004146013702133370023227 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t_dpi_result_type_bad; // Illegal result types for DPI functions //====================================================================== // Type definitions //====================================================================== // 2-state packed arrays of width > 32 typedef bit [ 32:0] array_2_state_33_t; typedef bit [ 63:0] array_2_state_64_t; typedef bit [ 64:0] array_2_state_65_t; typedef bit [127:0] array_2_state_128_t; // 2-state packed structures of width > 32 typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; // 2-state packed unions of width > 32 typedef union packed { bit [ 32:0] x; bit y; } union_2_state_33; typedef union packed { bit [ 63:0] x; bit y; } union_2_state_64; typedef union packed { bit [ 64:0] x; bit y; } union_2_state_65; typedef union packed { bit [127:0] x; bit y; } union_2_state_128; // 4-state packed arrays of any size typedef logic [ 0:0] array_4_state_1_t; typedef logic [ 1:0] array_4_state_2_t; typedef logic [ 7:0] array_4_state_8_t; typedef logic [ 8:0] array_4_state_9_t; typedef logic [ 15:0] array_4_state_16_t; typedef logic [ 16:0] array_4_state_17_t; typedef logic [ 31:0] array_4_state_32_t; typedef logic [ 32:0] array_4_state_33_t; typedef logic [ 63:0] array_4_state_64_t; typedef logic [ 64:0] array_4_state_65_t; typedef logic [127:0] array_4_state_128_t; // 4-state packed structures of any size typedef struct packed { logic [ 0:0] x; } struct_4_state_1; typedef struct packed { logic [ 0:0] x; bit [ 0:0] y; } struct_4_state_2; typedef struct packed { logic [ 3:0] x; bit [ 3:0] y; } struct_4_state_8; typedef struct packed { logic [ 3:0] x; bit [ 4:0] y; } struct_4_state_9; typedef struct packed { logic [ 7:0] x; bit [ 7:0] y; } struct_4_state_16; typedef struct packed { logic [ 7:0] x; bit [ 8:0] y; } struct_4_state_17; typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; // 4-state packed unions of any size typedef union packed { logic [ 0:0] x; bit y; } union_4_state_1; typedef union packed { logic [ 1:0] x; bit y; } union_4_state_2; typedef union packed { logic [ 7:0] x; bit y; } union_4_state_8; typedef union packed { logic [ 8:0] x; bit y; } union_4_state_9; typedef union packed { logic [ 15:0] x; bit y; } union_4_state_16; typedef union packed { logic [ 16:0] x; bit y; } union_4_state_17; typedef union packed { logic [ 31:0] x; bit y; } union_4_state_32; typedef union packed { logic [ 32:0] x; bit y; } union_4_state_33; typedef union packed { logic [ 63:0] x; bit y; } union_4_state_64; typedef union packed { logic [ 64:0] x; bit y; } union_4_state_65; typedef union packed { logic [127:0] x; bit y; } union_4_state_128; //====================================================================== // Imports //====================================================================== // 2-state packed arrays of width > 32 import "DPI-C" function bit [ 32:0] i_array_2_state_33(); import "DPI-C" function bit [ 63:0] i_array_2_state_64(); import "DPI-C" function bit [ 64:0] i_array_2_state_65(); import "DPI-C" function bit [127:0] i_array_2_state_128(); // 2-state packed arrays of width > 32 via typedef import "DPI-C" function array_2_state_33_t i_array_2_state_33_t(); import "DPI-C" function array_2_state_64_t i_array_2_state_64_t(); import "DPI-C" function array_2_state_65_t i_array_2_state_65_t(); import "DPI-C" function array_2_state_128_t i_array_2_state_128_t(); // 2-state packed structures of width > 32 import "DPI-C" function struct_2_state_33 i_struct_2_state_33(); import "DPI-C" function struct_2_state_64 i_struct_2_state_64(); import "DPI-C" function struct_2_state_65 i_struct_2_state_65(); import "DPI-C" function struct_2_state_128 i_struct_2_state_128(); // 2-state packed unions of width > 32 import "DPI-C" function union_2_state_33 i_union_2_state_33(); import "DPI-C" function union_2_state_64 i_union_2_state_64(); import "DPI-C" function union_2_state_65 i_union_2_state_65(); import "DPI-C" function union_2_state_128 i_union_2_state_128(); // 4-state basic types import "DPI-C" function integer i_integer(); // 4-state packed arrays of any size import "DPI-C" function logic [ 0:0] i_array_4_state_1(); import "DPI-C" function logic [ 1:0] i_array_4_state_2(); import "DPI-C" function logic [ 7:0] i_array_4_state_8(); import "DPI-C" function logic [ 8:0] i_array_4_state_9(); import "DPI-C" function logic [ 15:0] i_array_4_state_16(); import "DPI-C" function logic [ 16:0] i_array_4_state_17(); import "DPI-C" function logic [ 31:0] i_array_4_state_32(); import "DPI-C" function logic [ 32:0] i_array_4_state_33(); import "DPI-C" function logic [ 63:0] i_array_4_state_64(); import "DPI-C" function logic [ 64:0] i_array_4_state_65(); import "DPI-C" function logic [127:0] i_array_4_state_128(); // 4-state packed arrays of any size via typedef import "DPI-C" function array_4_state_1_t i_array_4_state_1_t(); import "DPI-C" function array_4_state_2_t i_array_4_state_2_t(); import "DPI-C" function array_4_state_8_t i_array_4_state_8_t(); import "DPI-C" function array_4_state_9_t i_array_4_state_9_t(); import "DPI-C" function array_4_state_16_t i_array_4_state_16_t(); import "DPI-C" function array_4_state_17_t i_array_4_state_17_t(); import "DPI-C" function array_4_state_32_t i_array_4_state_32_t(); import "DPI-C" function array_4_state_33_t i_array_4_state_33_t(); import "DPI-C" function array_4_state_64_t i_array_4_state_64_t(); import "DPI-C" function array_4_state_65_t i_array_4_state_65_t(); import "DPI-C" function array_4_state_128_t i_array_4_state_128_t(); // 4-state packed structures of any size import "DPI-C" function struct_4_state_1 i_struct_4_state_1(); import "DPI-C" function struct_4_state_2 i_struct_4_state_2(); import "DPI-C" function struct_4_state_8 i_struct_4_state_8(); import "DPI-C" function struct_4_state_9 i_struct_4_state_9(); import "DPI-C" function struct_4_state_16 i_struct_4_state_16(); import "DPI-C" function struct_4_state_17 i_struct_4_state_17(); import "DPI-C" function struct_4_state_32 i_struct_4_state_32(); import "DPI-C" function struct_4_state_33 i_struct_4_state_33(); import "DPI-C" function struct_4_state_64 i_struct_4_state_64(); import "DPI-C" function struct_4_state_65 i_struct_4_state_65(); import "DPI-C" function struct_4_state_128 i_struct_4_state_128(); // 4-state packed unions of any size import "DPI-C" function union_4_state_1 i_union_4_state_1(); import "DPI-C" function union_4_state_2 i_union_4_state_2(); import "DPI-C" function union_4_state_8 i_union_4_state_8(); import "DPI-C" function union_4_state_9 i_union_4_state_9(); import "DPI-C" function union_4_state_16 i_union_4_state_16(); import "DPI-C" function union_4_state_17 i_union_4_state_17(); import "DPI-C" function union_4_state_32 i_union_4_state_32(); import "DPI-C" function union_4_state_33 i_union_4_state_33(); import "DPI-C" function union_4_state_64 i_union_4_state_64(); import "DPI-C" function union_4_state_65 i_union_4_state_65(); import "DPI-C" function union_4_state_128 i_union_4_state_128(); //====================================================================== // Exports //====================================================================== // 2-state packed arrays of width > 32 export "DPI-C" function e_array_2_state_33; export "DPI-C" function e_array_2_state_64; export "DPI-C" function e_array_2_state_65; export "DPI-C" function e_array_2_state_128; // 2-state packed arrays of width > 32 via typedef export "DPI-C" function e_array_2_state_33_t; export "DPI-C" function e_array_2_state_64_t; export "DPI-C" function e_array_2_state_65_t; export "DPI-C" function e_array_2_state_128_t; // 2-state packed structures of width > 32 export "DPI-C" function e_struct_2_state_33; export "DPI-C" function e_struct_2_state_64; export "DPI-C" function e_struct_2_state_65; export "DPI-C" function e_struct_2_state_128; // 2-state packed unions of width > 32 export "DPI-C" function e_union_2_state_33; export "DPI-C" function e_union_2_state_64; export "DPI-C" function e_union_2_state_65; export "DPI-C" function e_union_2_state_128; // 4-state basic types export "DPI-C" function e_integer; // 4-state packed arrays of any size export "DPI-C" function e_array_4_state_1; export "DPI-C" function e_array_4_state_2; export "DPI-C" function e_array_4_state_8; export "DPI-C" function e_array_4_state_9; export "DPI-C" function e_array_4_state_16; export "DPI-C" function e_array_4_state_17; export "DPI-C" function e_array_4_state_32; export "DPI-C" function e_array_4_state_33; export "DPI-C" function e_array_4_state_64; export "DPI-C" function e_array_4_state_65; export "DPI-C" function e_array_4_state_128; // 4-state packed arrays of any size via typedef export "DPI-C" function e_array_4_state_1_t; export "DPI-C" function e_array_4_state_2_t; export "DPI-C" function e_array_4_state_8_t; export "DPI-C" function e_array_4_state_9_t; export "DPI-C" function e_array_4_state_16_t; export "DPI-C" function e_array_4_state_17_t; export "DPI-C" function e_array_4_state_32_t; export "DPI-C" function e_array_4_state_33_t; export "DPI-C" function e_array_4_state_64_t; export "DPI-C" function e_array_4_state_65_t; export "DPI-C" function e_array_4_state_128_t; // 4-state packed structures of any size export "DPI-C" function e_struct_4_state_1; export "DPI-C" function e_struct_4_state_2; export "DPI-C" function e_struct_4_state_8; export "DPI-C" function e_struct_4_state_9; export "DPI-C" function e_struct_4_state_16; export "DPI-C" function e_struct_4_state_17; export "DPI-C" function e_struct_4_state_32; export "DPI-C" function e_struct_4_state_33; export "DPI-C" function e_struct_4_state_64; export "DPI-C" function e_struct_4_state_65; export "DPI-C" function e_struct_4_state_128; // 4-state packed unions of any size export "DPI-C" function e_union_4_state_1; export "DPI-C" function e_union_4_state_2; export "DPI-C" function e_union_4_state_8; export "DPI-C" function e_union_4_state_9; export "DPI-C" function e_union_4_state_16; export "DPI-C" function e_union_4_state_17; export "DPI-C" function e_union_4_state_32; export "DPI-C" function e_union_4_state_33; export "DPI-C" function e_union_4_state_64; export "DPI-C" function e_union_4_state_65; export "DPI-C" function e_union_4_state_128; //====================================================================== // Definitions of exported functions //====================================================================== // 2-state packed arrays of width > 32 function bit [ 32:0] e_array_2_state_33(); return 0; endfunction function bit [ 63:0] e_array_2_state_64(); return 0; endfunction function bit [ 64:0] e_array_2_state_65(); return 0; endfunction function bit [127:0] e_array_2_state_128(); return 0; endfunction // 2-state packed arrays of width > 32 via typedef function array_2_state_33_t e_array_2_state_33_t(); return 0; endfunction function array_2_state_64_t e_array_2_state_64_t(); return 0; endfunction function array_2_state_65_t e_array_2_state_65_t(); return 0; endfunction function array_2_state_128_t e_array_2_state_128_t(); return 0; endfunction // 2-state packed structures of width > 32 function struct_2_state_33 e_struct_2_state_33(); return 0; endfunction function struct_2_state_64 e_struct_2_state_64(); return 0; endfunction function struct_2_state_65 e_struct_2_state_65(); return 0; endfunction function struct_2_state_128 e_struct_2_state_128(); return 0; endfunction // 2-state packed unions of width > 32 function union_2_state_33 e_union_2_state_33(); return 0; endfunction function union_2_state_64 e_union_2_state_64(); return 0; endfunction function union_2_state_65 e_union_2_state_65(); return 0; endfunction function union_2_state_128 e_union_2_state_128(); return 0; endfunction // 4-state basic types function integer e_integer(); return 0; endfunction // 4-state packed arrays of any size function logic [ 0:0] e_array_4_state_1(); return 0; endfunction function logic [ 1:0] e_array_4_state_2(); return 0; endfunction function logic [ 7:0] e_array_4_state_8(); return 0; endfunction function logic [ 8:0] e_array_4_state_9(); return 0; endfunction function logic [ 15:0] e_array_4_state_16(); return 0; endfunction function logic [ 16:0] e_array_4_state_17(); return 0; endfunction function logic [ 31:0] e_array_4_state_32(); return 0; endfunction function logic [ 32:0] e_array_4_state_33(); return 0; endfunction function logic [ 63:0] e_array_4_state_64(); return 0; endfunction function logic [ 64:0] e_array_4_state_65(); return 0; endfunction function logic [127:0] e_array_4_state_128(); return 0; endfunction // 4-state packed arrays of any size via typedef function array_4_state_1_t e_array_4_state_1_t(); return 0; endfunction function array_4_state_2_t e_array_4_state_2_t(); return 0; endfunction function array_4_state_8_t e_array_4_state_8_t(); return 0; endfunction function array_4_state_9_t e_array_4_state_9_t(); return 0; endfunction function array_4_state_16_t e_array_4_state_16_t(); return 0; endfunction function array_4_state_17_t e_array_4_state_17_t(); return 0; endfunction function array_4_state_32_t e_array_4_state_32_t(); return 0; endfunction function array_4_state_33_t e_array_4_state_33_t(); return 0; endfunction function array_4_state_64_t e_array_4_state_64_t(); return 0; endfunction function array_4_state_65_t e_array_4_state_65_t(); return 0; endfunction function array_4_state_128_t e_array_4_state_128_t(); return 0; endfunction // 4-state packed structures of any size function struct_4_state_1 e_struct_4_state_1(); return 0; endfunction function struct_4_state_2 e_struct_4_state_2(); return 0; endfunction function struct_4_state_8 e_struct_4_state_8(); return 0; endfunction function struct_4_state_9 e_struct_4_state_9(); return 0; endfunction function struct_4_state_16 e_struct_4_state_16(); return 0; endfunction function struct_4_state_17 e_struct_4_state_17(); return 0; endfunction function struct_4_state_32 e_struct_4_state_32(); return 0; endfunction function struct_4_state_33 e_struct_4_state_33(); return 0; endfunction function struct_4_state_64 e_struct_4_state_64(); return 0; endfunction function struct_4_state_65 e_struct_4_state_65(); return 0; endfunction function struct_4_state_128 e_struct_4_state_128(); return 0; endfunction // 4-state packed unions of any size function union_4_state_1 e_union_4_state_1(); return 0; endfunction function union_4_state_2 e_union_4_state_2(); return 0; endfunction function union_4_state_8 e_union_4_state_8(); return 0; endfunction function union_4_state_9 e_union_4_state_9(); return 0; endfunction function union_4_state_16 e_union_4_state_16(); return 0; endfunction function union_4_state_17 e_union_4_state_17(); return 0; endfunction function union_4_state_32 e_union_4_state_32(); return 0; endfunction function union_4_state_33 e_union_4_state_33(); return 0; endfunction function union_4_state_64 e_union_4_state_64(); return 0; endfunction function union_4_state_65 e_union_4_state_65(); return 0; endfunction function union_4_state_128 e_union_4_state_128(); return 0; endfunction endmodule verilator-4.038/test_regress/t/t_struct_array.pl0000775000177100017500000000105313702133370022073 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_sel.v0000664000177100017500000000405413702133370021147 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test #(16,2) test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hf9b3a5000165ed38 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output [31:0] out; parameter N = 0; parameter PASSDOWN = 1; add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]), .out (out)); endmodule module add (/*AUTOARG*/ // Outputs out, // Inputs in ); parameter PASSDOWN = 9999; input [31:0] in; output [31:0] out; wire out = in + PASSDOWN; endmodule verilator-4.038/test_regress/t/t_genvar_for_bad.out0000664000177100017500000000043613702133370022504 0ustar wsnyderwsnyder%Error: t/t_genvar_for_bad.v:23:10: Genvar not legal in non-generate for (IEEE 1800-2017 27.4): 't.i' : ... Suggest move for loop upwards to generate-level scope. 23 | for (i=0; i 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_langext_2.v0000664000177100017500000000222713702133370021067 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test of the +1364-1995ext+ and +systemverilogext+ flags. // // This source code contains constructs that are valid in SystemVerilog 2009 // but not in Verilog 1995. So it should fail if we set the language to be // Verilog 1995, but not SystemVerilog 2009. // // Compile only test, so no need for "All Finished" output. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [1:0] res; // Instantiate the test test test_i (/*AUTOINST*/ // Outputs .res (res), // Inputs .clk (clk), .in (1'b1)); endmodule module test (// Outputs res, // Inputs clk, in ); output [1:0] res; input clk; input in; // This is a SystemVerilog 2009 only test generate genvar i; for (i=0; i<2; i=i+1) begin always @(posedge clk) begin unique0 case (i) 0: res[0:0] <= in; 1: res[1:1] <= in; endcase end end endgenerate endmodule verilator-4.038/test_regress/t/t_tri_ifbegin.pl0000775000177100017500000000102213702133370021626 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); # No exeecution ok(1); 1; verilator-4.038/test_regress/t/t_gen_alw.v0000664000177100017500000000355113702133370020621 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [9:0] in = crc[9:0]; /*AUTOWIRE*/ Test test (/*AUTOINST*/ // Inputs .clk (clk), .in (in[9:0])); // Aggregate outputs into a single result vector wire [63:0] result = {64'h0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Inputs clk, in ); input clk; input [9:0] in; reg a [9:0]; integer ai; always @* begin for (ai=0;ai<10;ai=ai+1) begin a[ai]=in[ai]; end end reg [1:0] b [9:0]; integer j; generate genvar i; for (i=0; i<2; i=i+1) begin always @(posedge clk) begin for (j=0; j<10; j=j+1) begin if (a[j]) b[i][j] <= 1'b0; else b[i][j] <= 1'b1; end end end endgenerate endmodule verilator-4.038/test_regress/t/t_trace_cat_renew_0100.out0000664000177100017500000000510413702133370023330 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Thu Aug 30 16:11:06 2018 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #100 b00000000000000000000000000110010 # 1$ #101 0$ #102 b00000000000000000000000000110011 # 1$ #103 0$ #104 b00000000000000000000000000110100 # 1$ #105 0$ #106 b00000000000000000000000000110101 # 1$ #107 0$ #108 b00000000000000000000000000110110 # 1$ #109 0$ #110 b00000000000000000000000000110111 # 1$ #111 0$ #112 b00000000000000000000000000111000 # 1$ #113 0$ #114 b00000000000000000000000000111001 # 1$ #115 0$ #116 b00000000000000000000000000111010 # 1$ #117 0$ #118 b00000000000000000000000000111011 # 1$ #119 0$ #120 b00000000000000000000000000111100 # 1$ #121 0$ #122 b00000000000000000000000000111101 # 1$ #123 0$ #124 b00000000000000000000000000111110 # 1$ #125 0$ #126 b00000000000000000000000000111111 # 1$ #127 0$ #128 b00000000000000000000000001000000 # 1$ #129 0$ #130 b00000000000000000000000001000001 # 1$ #131 0$ #132 b00000000000000000000000001000010 # 1$ #133 0$ #134 b00000000000000000000000001000011 # 1$ #135 0$ #136 b00000000000000000000000001000100 # 1$ #137 0$ #138 b00000000000000000000000001000101 # 1$ #139 0$ #140 b00000000000000000000000001000110 # 1$ #141 0$ #142 b00000000000000000000000001000111 # 1$ #143 0$ #144 b00000000000000000000000001001000 # 1$ #145 0$ #146 b00000000000000000000000001001001 # 1$ #147 0$ #148 b00000000000000000000000001001010 # 1$ #149 0$ #150 b00000000000000000000000001001011 # 1$ #151 0$ #152 b00000000000000000000000001001100 # 1$ #153 0$ #154 b00000000000000000000000001001101 # 1$ #155 0$ #156 b00000000000000000000000001001110 # 1$ #157 0$ #158 b00000000000000000000000001001111 # 1$ #159 0$ #160 b00000000000000000000000001010000 # 1$ #161 0$ #162 b00000000000000000000000001010001 # 1$ #163 0$ #164 b00000000000000000000000001010010 # 1$ #165 0$ #166 b00000000000000000000000001010011 # 1$ #167 0$ #168 b00000000000000000000000001010100 # 1$ #169 0$ #170 b00000000000000000000000001010101 # 1$ #171 0$ #172 b00000000000000000000000001010110 # 1$ #173 0$ #174 b00000000000000000000000001010111 # 1$ #175 0$ #176 b00000000000000000000000001011000 # 1$ #177 0$ #178 b00000000000000000000000001011001 # 1$ #179 0$ #180 b00000000000000000000000001011010 # 1$ #181 0$ #182 b00000000000000000000000001011011 # 1$ #183 0$ #184 b00000000000000000000000001011100 # 1$ #185 0$ #186 b00000000000000000000000001011101 # 1$ #187 0$ #188 b00000000000000000000000001011110 # 1$ #189 0$ verilator-4.038/test_regress/t/t_trace_string.v0000664000177100017500000000310213702133370021661 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"}; initial begin $display("%s", SVEC[3'd1]); $write("*-* All Finished *-*\n"); $finish; end localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"}; function string regx (logic [5-1:0] r, bit abi=1'b0); regx = abi ? REGX[r] : $sformatf("x%0d", r); endfunction: regx function string dis32 (logic [32-1:0] op); casez (op) 32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop"); 32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-"); 32'b????_????_????_????_?000_????_?110_0111: dis32 = $sformatf("jalr %s, 0x%03x (%s)", regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0])); default: dis32 = "illegal"; endcase endfunction: dis32 always @(posedge clk) begin for (int unsigned i=0; i<32; i++) $display("REGX: %s", regx(i[4:0])); $display("OP: %s", dis32(32'h00000000)); $finish(); end endmodule verilator-4.038/test_regress/t/t_unopt_bound.v0000664000177100017500000000125213702133370021535 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jue Xu. // SPDX-License-Identifier: CC0-1.0 // bug630 module t ( clk, out ); input clk; output out; reg a; reg b; typedef struct packed { logic config_a; logic config_b; } param_t; // verilator lint_off UNOPTFLAT param_t conf [1:2] ; // verilator lint_on UNOPTFLAT always @ (posedge clk) begin conf[2].config_b <= a; $write("*-* All Finished *-*\n"); $finish; end always @ (posedge conf[2].config_b) begin a = conf[2].config_a; end endmodule verilator-4.038/test_regress/t/t_hierarchy_identifier.v0000664000177100017500000000212613702133370023362 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter SIZE = 8; integer cnt = 0; logic [SIZE-1:0] vld_for; logic vld_if = 1'b0; logic vld_else = 1'b0; genvar i; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if (cnt==SIZE) begin : \0escaped___name $write("*-* All Finished *-*\n"); $finish; end : \0escaped___name generate for (i=0; i0) begin : generate_if_if always @ (posedge clk) vld_if <= 1'b1; end : generate_if_if else begin : generate_if_else always @ (posedge clk) vld_else <= 1'b1; end : generate_if_else endgenerate endmodule : t verilator-4.038/test_regress/t/t_sv_bus_mux_demux/0000775000177100017500000000000013702335701022410 5ustar wsnyderwsnyderverilator-4.038/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv0000664000177100017500000000455713702133370027260 0ustar wsnyderwsnyder//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// import package_bus::*; import package_str::*; import package_uni::*; module sv_bus_mux_demux_mux ( // system signals input logic clk, // clock input logic rst, // reset // input bus input logic bus_vld, // valid (chip select) input logic [31:0] bus_adr, // address input logic [31:0] bus_dat, // data output logic bus_rdy, // ready (acknowledge) // output stream output logic str_vld, // valid (chip select) output logic [7:0] str_bus, // byte data bus input logic str_rdy // ready (acknowledge) ); logic bus_trn; // bus data transfer logic str_trn; // stream data transfer logic [2:0] pkt_cnt; // packet byte counter logic pkt_end; // packet byte counter end //t_bus pkt_bus; // transfer packet as a structure //t_str pkt_str; // transfer packet as an array t_uni pkt_uni; // transfer packet as an union // bus data transfer assign bus_trn = bus_vld & bus_rdy; // ready if pipe is empty or output is ready assign bus_rdy = ~str_vld | pkt_end; // writing input address/data into a structure always @ (posedge clk) if (bus_trn) begin pkt_uni.bus.adr <= bus_adr; pkt_uni.bus.dat <= bus_dat; end // output valid is set by an input transfer // or cleared by the last output transfer always @ (posedge clk, posedge rst) if (rst) str_vld <= 1'b0; else str_vld <= bus_trn | (str_vld & ~pkt_end); // packet byte counter always @ (posedge clk, posedge rst) if (rst) pkt_cnt <= '0; else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; // packet byte counter end assign pkt_end = str_rdy & (&pkt_cnt); // TODO, this should be a registered signal assign str_bus = pkt_uni.str [pkt_cnt]; // stream data transfer assign str_trn = str_vld & str_rdy; endmodule : sv_bus_mux_demux_mux verilator-4.038/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv0000664000177100017500000000212113702133370027166 0ustar wsnyderwsnyder//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// // definition of data bus structure package package_bus; typedef struct packed { logic [3:0] [7:0] adr; // address logic [3:0] [7:0] dat; // data } t_bus; endpackage : package_bus // definition of streaming bus packet as an array package package_str; typedef logic [7:0][7:0] t_str; endpackage : package_str // union of the structure and array representation package package_uni; import package_bus::*; import package_str::*; typedef union packed { t_bus bus; t_str str; } t_uni; endpackage : package_uni verilator-4.038/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv0000664000177100017500000000660313702133370027412 0ustar wsnyderwsnyder//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // // // This wrapper contains a bus multiplexer and a bus demultiplexer. Both // // modules have all ports exposed an there are no signals connecting them. // // // // --------------------- // // | wrap | // // | | // // | ----------- | // // bsi -> | -> | mux | -> | -> sto // // | ----------- | // // | | // // | ----------- | // // bso <- | <- | demux | <- | <- sto // // | ----------- | // // | | // // --------------------- // // // //////////////////////////////////////////////////////////////////////////////// module sv_bus_mux_demux_wrap ( // system signals input logic clk, input logic rst, // input bus input logic bsi_vld, // valid (chip select) input logic [31:0] bsi_adr, // address input logic [31:0] bsi_dat, // data output logic bsi_rdy, // ready (acknowledge) // output stream output logic sto_vld, output logic [7:0] sto_bus, input logic sto_rdy, // input stream input logic sti_vld, input logic [7:0] sti_bus, output logic sti_rdy, // output bus output logic bso_vld, // valid (chip select) output logic [31:0] bso_adr, // address output logic [31:0] bso_dat, // data input logic bso_rdy // ready (acknowledge) ); sv_bus_mux_demux_mux mux ( // system signals .clk (clk), .rst (rst), // input bus .bus_vld (bsi_vld), .bus_adr (bsi_adr), .bus_dat (bsi_dat), .bus_rdy (bsi_rdy), // output stream .str_vld (sto_vld), .str_bus (sto_bus), .str_rdy (sto_rdy) ); sv_bus_mux_demux_demux demux ( // system signals .clk (clk), .rst (rst), // input stream .str_vld (sti_vld), .str_bus (sti_bus), .str_rdy (sti_rdy), // output bus .bus_vld (bso_vld), .bus_adr (bso_adr), .bus_dat (bso_dat), .bus_rdy (bso_rdy) ); endmodule : sv_bus_mux_demux_wrap verilator-4.038/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv0000664000177100017500000000447513702133370027570 0ustar wsnyderwsnyder//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// import package_bus::*; import package_str::*; module sv_bus_mux_demux_demux ( // system signals input logic clk, // clock input logic rst, // reset // output stream input logic str_vld, // valid (chip select) input logic [7:0] str_bus, // byte data bus output logic str_rdy, // ready (acknowledge) // input bus output logic bus_vld, // valid (chip select) output logic [31:0] bus_adr, // address output logic [31:0] bus_dat, // data input logic bus_rdy // ready (acknowledge) ); logic bus_trn; // bus data transfer logic str_trn; // stream data transfer logic [2:0] pkt_cnt; // packet byte counter logic pkt_end; // packet byte counter end t_str pkt_str; // transfer packet as a structure t_bus pkt_bus; // transfer packet as an array // stream data transfer assign str_trn = str_vld & str_rdy; // ready if pipe is empty or output is ready assign str_rdy = ~bus_vld | bus_rdy; // packet byte counter always @ (posedge clk, posedge rst) if (rst) pkt_cnt <= 3'd0; else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; // packet byte counter end assign pkt_end = (&pkt_cnt); always @ (posedge clk) if (str_trn) pkt_str [pkt_cnt] <= str_bus; // the input packed array is mapped onto the output structure assign pkt_bus = pkt_str; // the output structure is mapped onto address/data outputs assign bus_adr = pkt_bus.adr; assign bus_dat = pkt_bus.dat; // output valid is set on the last input packed byte // or cleared by each output transfer always @ (posedge clk, posedge rst) if (rst) bus_vld <= 1'b0; else bus_vld <= str_trn & pkt_end | bus_vld & ~bus_rdy; // bus data transfer assign bus_trn = bus_vld & bus_rdy; endmodule : sv_bus_mux_demux_demux verilator-4.038/test_regress/t/t_assert_synth_parallel.pl0000775000177100017500000000145513702133367023767 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_synth.v"); compile( v_flags2 => ['+define+FAILING_PARALLEL', '+define+ATTRIBUTES'], verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], ); execute( check_finished => 0, fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_debug_graph_test.pl0000775000177100017500000000132613702133370022662 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB"); lint( # Check we can call dump() on graph, and other things v_flags => ["--lint-only --debug --debugi-V3GraphTest 9 --debugi-V3GraphDfa 9"], ); ok(1); 1; verilator-4.038/test_regress/t/t_array_packed_sysfunct.pl0000775000177100017500000000105313702133367023742 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_stream2.pl0000775000177100017500000000105313702133370020726 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_inout.cpp0000664000177100017500000000245713702133370021542 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_inout.h" Vt_tri_inout* tb = NULL; double sc_time_stamp() { return 0; } bool check() { bool pass; int Z; if (tb->SEL) { Z = tb->A; } else { Z = tb->B; } if (tb->Z == tb->Y1 && tb->Z == tb->Y2 && tb->Z == Z) { printf("PASS: "); pass = true; } else { printf("FAIL: "); pass = false; } #ifdef TEST_VERBOSE printf("SEL=%d A=%d B=%d Z=%d Y1=%d Y2=%d\n", tb->SEL, tb->A, tb->B, tb->Z, tb->Y1, tb->Y2); #endif return pass; } int main() { bool pass = true; Verilated::debug(0); tb = new Vt_tri_inout("tb"); // loop through every possibility and check the result for (tb->SEL = 0; tb->SEL < 2; tb->SEL++) { for (tb->A = 0; tb->A < 2; tb->A++) { for (tb->B = 0; tb->B < 2; tb->B++) { tb->eval(); if (!check()) { pass = false; } } } } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from inout test\n"); } return 0; } verilator-4.038/test_regress/t/t_gen_cond_const.pl0000775000177100017500000000113413702133370022333 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--language 1364-2001"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_endian.pl0000775000177100017500000000105313702133370021622 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_order_comboloop.v0000664000177100017500000000250013702133370022362 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT reg [31:0] runner; initial runner = 5; reg [31:0] runnerm1; reg [59:0] runnerq; reg [89:0] runnerw; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin `ifdef verilator if (runner != 0) $stop; // Initial settlement failed `endif end if (cyc==2) begin runner = 20; runnerq = 60'h0; runnerw = 90'h0; end if (cyc==3) begin if (runner != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end end end // This forms a "loop" where we keep going through the always till runner=0 // This isn't "regular" beh code, but ensures our change detection is working properly always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end always @ (/*AS*/runnerm1) begin if (runner > 0) begin runner = runnerm1; runnerq = runnerq - 60'd1; runnerw = runnerw - 90'd1; $write ("[%0t] runner=%d\n", $time, runner); end end endmodule verilator-4.038/test_regress/t/t_param_scope_bad.pl0000775000177100017500000000110113702133370022442 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_inc_recurse_bad.pl0000775000177100017500000000107413702133370024215 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_array.pl0000775000177100017500000000105313702133370021647 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_fuzz_genintf_bad.out0000664000177100017500000000104413702133370023060 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_fuzz_genintf_bad.v:24:12: Unsupported: Member call on object 'VARREF 'j'' which is a 'BASICDTYPE 'integer'' : ... In instance t 24 | j.e(0), | ^ %Error: Internal Error: t/t_fuzz_genintf_bad.v:24:11: ../V3Width.cpp:#: Unlinked pin data type : ... In instance t 24 | j.e(0), | ^ ... See the manual and https://verilator.org for more assistance. verilator-4.038/test_regress/t/t_past.pl0000775000177100017500000000105313702133370020320 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_dup_bad.v0000664000177100017500000000113013702133370021426 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); // Same name w/ different args import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); initial begin $stop; end endmodule verilator-4.038/test_regress/t/t_dpi_accessors.cpp0000664000177100017500000006134113702133370022344 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2012 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // // Contributed by Jeremy Bennett and Jie Xu // //************************************************************************* #include #include #include "svdpi.h" #include "Vt_dpi_accessors.h" #include "Vt_dpi_accessors__Dpi.h" using std::cout; using std::dec; using std::endl; using std::hex; using std::setfill; using std::setw; // Convenience function to check we didn't finish unexpectedly static void checkFinish(const char* msg) { if (Verilated::gotFinish()) { vl_fatal(__FILE__, __LINE__, "dut", msg); exit(1); } } // Convenience function to log the value of a register in hex. Only in verbose // mode. static void logReg(int clk, const char* desc, int val, const char* note) { #ifdef TEST_VERBOSE cout << "clk = " << clk << ", " << desc << " = " << val << note << endl; #endif } // Convenience function to log the value of a register in hex. Only in verbose // mode. static void logRegHex(int clk, const char* desc, int bitWidth, int val, const char* note) { #ifdef TEST_VERBOSE cout << "clk = " << clk << ", " << desc << " = " << bitWidth << "\'h" << hex << setw((bitWidth - 1) / 4 + 1) << setfill('0') << val << setfill(' ') << setw(0) << dec << note << endl; #endif } // Convenience function to check we got an expected result. Silent on success. static void checkResult(bool p, const char* msg_fail) { if (!p) { vl_fatal(__FILE__, __LINE__, "dut", msg_fail); } } // Main function instantiates the model and steps through the test. int main() { Vt_dpi_accessors* dut = new Vt_dpi_accessors("dut"); svScope scope = svGetScopeFromName("dut.t"); if (!scope) vl_fatal(__FILE__, __LINE__, "dut", "No svGetScopeFromName result"); svSetScope(scope); // evaluate the model with no signal changes to get the initial blocks // executed. dut->eval(); #ifdef TEST_VERBOSE cout << "Initial DPI values" << endl; cout << "==================" << endl; #endif int a = (int)a_read(); int b = (int)b_read(); int mem32 = (int)mem32_read(); int c = (int)c_read(); int d = (int)d_read(); int e = (int)e_read(); int f = (int)f_read(); #ifdef TEST_VERBOSE cout << "Read a = " << a << endl; cout << "Read b = 8'h" << hex << setw(2) << setfill('0') << b << setfill(' ') << setw(0) << dec << endl; cout << "Read mem32 = 8'h" << hex << setw(2) << setfill('0') << mem32 << setfill(' ') << setw(0) << dec << endl; cout << "Read c = " << c << endl; cout << "Read d = 8'h" << hex << setw(2) << setfill('0') << d << setfill(' ') << setw(0) << dec << endl; cout << "Read e = 8'h" << hex << setw(2) << setfill('0') << e << setfill(' ') << setw(0) << dec << endl; cout << "Read f = 8'h" << hex << setw(2) << setfill('0') << f << setfill(' ') << setw(0) << dec << endl; cout << endl; #endif checkResult((0 == a) && (0x00 == b) && (0x20 == mem32) && (1 == c) && (0xff == d) && (0x00 == e) && (0x00 == f), "Bad initial DPI values."); // Initialize the clock dut->clk = 0; // Check we can read a scalar register. #ifdef TEST_VERBOSE cout << "Test of scalar register reading" << endl; cout << "===============================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; a = (int)a_read(); logReg(dut->clk, "read a", a, " (before clk)"); dut->eval(); int a_after = (int)a_read(); logReg(dut->clk, "read a", a_after, " (after clk)"); #ifdef TEST_VERBOSE cout << endl; #endif // On a posedge, a should toggle, on a negedge it should stay the // same. checkResult(((dut->clk == 1) && (a_after == (1 - a))) || ((dut->clk == 0) && (a_after == a)), "Test of scalar register reading failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Check we can read a vector register. #ifdef TEST_VERBOSE cout << "Test of vector register reading" << endl; cout << "===============================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); logRegHex(dut->clk, "read b", 8, b, " (before clk)"); dut->eval(); int b_after = (int)b_read(); logRegHex(dut->clk, "read b", 8, b_after, " (after clk)"); // b should increment on a posedge and stay the same on a negedge. checkResult(((dut->clk == 1) && (b_after == (b + 1))) || ((dut->clk == 0) && (b_after == b)), "Test of vector register reading failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Test we can read an array element #ifdef TEST_VERBOSE cout << endl; cout << "Test of array element reading" << endl; cout << "=============================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; mem32 = (int)mem32_read(); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)"); dut->eval(); mem32 = (int)mem32_read(); logRegHex(dut->clk, "read mem32", 8, mem32, " (after clk)"); // In this case, the value never changes. But we should check it is // waht we expect (0x20). checkResult(mem32 == 0x20, "Test of array element reading failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Check we can read a scalar wire #ifdef TEST_VERBOSE cout << endl; cout << "Test of scalar wire reading" << endl; cout << "===========================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; a = (int)a_read(); c = (int)c_read(); logReg(dut->clk, "read a", a, " (before clk)"); logReg(dut->clk, "read c", c, " (before clk)"); dut->eval(); a = (int)a_read(); c = (int)c_read(); logReg(dut->clk, "read a", a, " (after clk)"); logReg(dut->clk, "read c", c, " (after clk)"); // "c" is continuously assigned as the inverse of "a", but in // Verilator, that means that it will only change value when "a" // changes on the posedge of a clock. Put simply, "c" always holds the // inverse of the "after clock" value of "a". checkResult(c == (1 - a), "Test of scalar wire reading failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Check we can read a vector wire #ifdef TEST_VERBOSE cout << endl; cout << "Test of vector wire reading" << endl; cout << "===========================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); d = (int)d_read(); logRegHex(dut->clk, "read b", 8, b, " (before clk)"); logRegHex(dut->clk, "read d", 8, d, " (before clk)"); dut->eval(); b = (int)b_read(); d = (int)d_read(); logRegHex(dut->clk, "read b", 8, b, " (after clk)"); logRegHex(dut->clk, "read d", 8, d, " (after clk)"); // "d" is continuously assigned as the (8-bit) bitwise inverse of "b", // but in Verilator, that means that it will only change value when // "b" changes on the posedge of a clock. Put simply, "d" always holds // the inverse of the "after clock" value of "b". checkResult(d == ((~b) & 0xff), "Test of vector wire reading failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Check we can write a scalar register #ifdef TEST_VERBOSE cout << endl; cout << "Test of scalar register writing" << endl; cout << "===============================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; a = 1 - (int)a_read(); a_write(reinterpret_cast(&a)); logReg(dut->clk, "write a", a, " (before clk)"); a = a_read(); logReg(dut->clk, "read a", a, " (before clk)"); dut->eval(); int a_after = (int)a_read(); logReg(dut->clk, "read a", a_after, " (after clk)"); // On a posedge clock, the value of a that is written should toggle, // on a negedge, it should not. checkResult(((dut->clk == 1) && (a_after == (1 - a))) || ((dut->clk == 0) && (a_after == a)), "Test of scalar register writing failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Check we can write a vector register #ifdef TEST_VERBOSE cout << endl; cout << "Test of vector register writing" << endl; cout << "===============================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read() - 1; b_write(reinterpret_cast(&b)); logRegHex(dut->clk, "write b", 8, b, " (before clk)"); b = (int)b_read(); logRegHex(dut->clk, "read b", 8, b, " (before clk)"); dut->eval(); int b_after = (int)b_read(); logRegHex(dut->clk, "read b", 8, b_after, " (after clk)"); // The value of "b" written should increment on a posedge and stay the // same on a negedge. checkResult(((dut->clk == 1) && (b_after == (b + 1))) || ((dut->clk == 0) && (b_after == b)), "Test of vector register writing failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Test we can write an array element #ifdef TEST_VERBOSE cout << endl; cout << "Test of array element writing" << endl; cout << "=============================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; mem32 = (int)mem32_read() - 1; mem32_write(reinterpret_cast(&mem32)); logRegHex(dut->clk, "write mem32", 8, mem32, " (before clk)"); mem32 = (int)mem32_read(); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)"); dut->eval(); int mem32_after = (int)mem32_read(); logRegHex(dut->clk, "read mem32", 8, mem32_after, " (after clk)"); // In this case, the value we write never changes (this would only // happen if this part of the test coincided with the 32nd element // being overwritten, which it does not. Check that the value after // the clock is the same as before the clock. checkResult(mem32_after == mem32, "Test of array element writing failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Check we can read a vector register slice #ifdef TEST_VERBOSE cout << endl; cout << "Test of vector register slice reading" << endl; cout << "=====================================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); int b_slice = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (before clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (before clk)"); dut->eval(); b = (int)b_read(); b_slice = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (after clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (after clk)"); // The slice of "b" should always be the bottom 4 bits of "b" checkResult(b_slice == (b & 0x0f), "Test of vector register slice reading failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Test we can read an array element slice #ifdef TEST_VERBOSE cout << endl; cout << "Test of array element slice reading" << endl; cout << "===================================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; mem32 = (int)mem32_read(); int mem32_slice = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32, " (before clk)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, " (before clk)"); dut->eval(); mem32 = (int)mem32_read(); mem32_slice = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, " (after clk)"); // The slice of "mem32" should always be the concatenation of the top // 2 and bottom 3 bits of "mem32" checkResult(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)), "Test of array element slice reading failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Check we can read a vector wire slice #ifdef TEST_VERBOSE cout << endl; cout << "Test of vector wire slice reading" << endl; cout << "=================================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); d = (int)d_read(); int d_slice = (int)d_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (before clk)"); logRegHex(dut->clk, "read d [7:0]", 8, d, " (before clk)"); logRegHex(dut->clk, "read d [6:1]", 6, d_slice, " (before clk)"); dut->eval(); b = (int)b_read(); d = (int)d_read(); d_slice = (int)d_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (after clk)"); logRegHex(dut->clk, "read d [7:0]", 8, d, " (after clk)"); logRegHex(dut->clk, "read d [6:1]", 6, d_slice, " (after clk)"); // The slice of "d" should always be the middle 6 bits of "d". checkResult(d_slice == ((d & 0x7e) >> 1), "Test of vector wire slice reading failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Check we can write a vector register slice #ifdef TEST_VERBOSE cout << endl; cout << "Test of vector register slice writing" << endl; cout << "=====================================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); int b_slice = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (before write)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (before write)"); b_slice--; b_slice_write(reinterpret_cast(&b_slice)); logRegHex(dut->clk, "write b [3:0]", 4, b_slice, " (before clk)"); int b_after = (int)b_read(); int b_slice_after = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b_after, " (before clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice_after, " (before clk)"); // We must test that when we wrote the slice of "b", we only wrote the // correct bits. The slice of b is b[3:0] int b_new = (b & 0xf0) | (b_slice & 0x0f); checkResult(b_after == b_new, "Test of vector register slice writing failed."); dut->eval(); b = (int)b_read(); b_slice = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (after clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (after clk)"); } checkFinish("t_dpi_accessors unexpected finish"); // Test we can write an array element slice #ifdef TEST_VERBOSE cout << endl; cout << "Test of array element slice writing" << endl; cout << "===================================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; mem32 = (int)mem32_read(); int mem32_slice = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32, " (before write)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, " (before write)"); mem32_slice--; mem32_slice_write(reinterpret_cast(&mem32_slice)); logRegHex(dut->clk, "write mem32 [7:6,2:0]", 5, mem32_slice, " (before clk)"); int mem32_after = (int)mem32_read(); int mem32_slice_after = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32_after, " (before clk)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice_after, " (before clk)"); // We must test that when we wrote the slice of "mem32", we only wrote // the correct bits. The slice of "mem32" is {mem32[7:6], mem32[2:0]}. int mem32_new = (mem32 & 0x38) | ((mem32_slice & 0x18) << 3) | (mem32_slice & 0x7); checkResult(mem32_after == mem32_new, "Test of vector register slice writing failed."); dut->eval(); mem32 = (int)mem32_read(); mem32_slice = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, " (after clk)"); // We have already tested that array element writing works, so we just // check that dhe slice of "mem32" after the clock is the // concatenation of the top 2 and bottom 3 bits of "mem32" checkResult(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)), "Test of array element slice writing failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Check we can read complex registers #ifdef TEST_VERBOSE cout << endl; cout << "Test of complex register reading" << endl; cout << "================================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); mem32 = (int)mem32_read(); e = (int)e_read(); int l1 = (int)l1_read(); logRegHex(dut->clk, "read b ", 8, b, " (before clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read l1 ", 15, l1, " (before clk)"); dut->eval(); b = (int)b_read(); mem32 = (int)mem32_read(); e = (int)e_read(); l1 = (int)l1_read(); logRegHex(dut->clk, "read b ", 8, b, " (after clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read e ", 8, e, " (after clk)"); logRegHex(dut->clk, "read l1 ", 15, l1, " (after clk)"); // We have already tested that reading of registers, memory elements // and wires works. So we just need to check that l1 reads back as the // correct combination of bits after the clock. It should be the 15 // bits: {b[3:0],mem[32][7:6],e[6:1],mem[32][2:0]}. checkResult(l1 == ((((b & 0x0f) >> 0) << 11) | (((mem32 & 0xc0) >> 6) << 9) | (((e & 0x7e) >> 1) << 3) | (((mem32 & 0x07) >> 0) << 0)), "Test of complex register reading l1 failed."); } #ifdef TEST_VERBOSE cout << endl; #endif checkFinish("t_dpi_accessors unexpected finish"); for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; e = 0x05 | (i << 4); f = 0xa0 | i; e_write(reinterpret_cast(&e)); f_write(reinterpret_cast(&f)); e = (int)e_read(); f = (int)f_read(); int l2 = (int)l2_read(); logRegHex(dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)"); dut->eval(); e = (int)e_read(); f = (int)f_read(); l2 = (int)l2_read(); logRegHex(dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)"); // We have already tested that reading of registers, memory elements // and wires works. So we just need to check that l1 reads back as the // correct combination of bits after the clock. It should be the 8 // bits: {e[7:4], f[3:0]}. checkResult(l2 == ((e & 0xf0) | (f & 0x0f)), "Test of complex register reading l2 failed."); } checkFinish("t_dpi_accessors unexpected finish"); // Test we can write a complex register #ifdef TEST_VERBOSE cout << endl; cout << "Test of complex register writing" << endl; cout << "================================" << endl; #endif for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); mem32 = (int)mem32_read(); e = (int)e_read(); logRegHex(dut->clk, "read b ", 8, b, " (before write)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (before write)"); logRegHex(dut->clk, "read e ", 8, e, " (before write)"); int l1 = 0x5a5a; l1_write(reinterpret_cast(&l1)); logRegHex(dut->clk, "write l1 ", 15, l1, " (before clk)"); int b_after = (int)b_read(); int mem32_after = (int)mem32_read(); int e_after = (int)e_read(); int l1_after = (int)l1_read(); logRegHex(dut->clk, "read b ", 8, b_after, " (before clk)"); logRegHex(dut->clk, "read mem32", 8, mem32_after, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e_after, " (before clk)"); logRegHex(dut->clk, "read l1 ", 15, l1_after, " (before clk)"); // We need to check that when we write l1, the correct fields, and // only the correct fields are set in its component registers, wires // and memory elements. l1 is 15 bits: // {b[3:0],mem[32][7:6],e[6:1],mem[32][2:0]}. int b_new = (b & 0xf0) | ((l1 & 0x7800) >> 11); int mem32_new = (mem32 & 0x38) | ((l1 & 0x0600) >> 3) | (l1 & 0x0007); int e_new = (e & 0x81) | ((l1 & 0x01f8) >> 2); checkResult((b_new == b_after) && (mem32_new == mem32_after) && (e_new == e_after), "Test of complex register writing l1 failed."); dut->eval(); b = (int)b_read(); mem32 = (int)mem32_read(); d = (int)d_read(); l1 = (int)l1_read(); logRegHex(dut->clk, "read b ", 8, b, " (after clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read d ", 8, d, " (after clk)"); logRegHex(dut->clk, "read l1 ", 15, l1, " (after clk)"); } #ifdef TEST_VERBOSE cout << endl; #endif checkFinish("t_dpi_accessors unexpected finish"); for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; e = (int)e_read(); f = (int)f_read(); logRegHex(dut->clk, "read e ", 8, e, " (before write)"); logRegHex(dut->clk, "read f ", 8, f, " (before write)"); int l2 = 0xa5 + i; l2_write(reinterpret_cast(&l2)); logRegHex(dut->clk, "write l2", 8, l2, " (before clk)"); int e_after = (int)e_read(); int f_after = (int)f_read(); int l2_after = (int)l2_read(); logRegHex(dut->clk, "read e ", 8, e_after, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f_after, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2_after, " (before clk)"); // We need to check that when we write l2, the correct fields, and // only the correct fields are set in its component registers. l is 8 // bits: {e[5:2], f[5:2]} int e_new = (e & 0xc3) | ((l2 & 0xf0) >> 2); int f_new = (f & 0xc3) | ((l2 & 0x0f) << 2); checkResult((e_new == e_after) && (f_new == f_after), "Test of complex register writing l2 failed."); dut->eval(); e = (int)e_read(); f = (int)f_read(); l2 = (int)l2_read(); logRegHex(dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)"); } checkFinish("t_dpi_accessors unexpected finish"); // Tidy up dut->final(); cout << "*-* All Finished *-*" << endl; } // Local Variables: // c-file-style:"cc-mode" // End: verilator-4.038/test_regress/t/t_gen_for_overlap.v0000664000177100017500000000212413702133370022347 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug749 module t (/*AUTOARG*/ // Inputs clk ); input clk; genvar g; for (g=1; g<3; ++g) begin : gblk sub2 #(.IN(g)) u (); //sub #(.IN(g)) u2 (); end sub1 #(.IN(0)) u (); always @ (posedge clk) begin if (t.u.IN != 0) $stop; if (t.u.FLAVOR != 1) $stop; //if (t.u2.IN != 0) $stop; // This should be not found if (t.gblk[1].u.IN != 1) $stop; if (t.gblk[2].u.IN != 2) $stop; if (t.gblk[1].u.FLAVOR != 2) $stop; if (t.gblk[2].u.FLAVOR != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub1 (/*AUTOARG*/); parameter [31:0] IN = 99; parameter FLAVOR = 1; `ifdef TEST_VERBOSE initial $display("%m"); `endif endmodule module sub2 (/*AUTOARG*/); parameter [31:0] IN = 99; parameter FLAVOR = 2; `ifdef TEST_VERBOSE initial $display("%m"); `endif endmodule verilator-4.038/test_regress/t/t_dpi_context_noopt.pl0000775000177100017500000000126313702133370023113 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_dpi_context.v"); compile( v_flags2 => ["t/t_dpi_context_c.cpp"], verilator_flags2 => [$Self->{vlt_all} ? "-O0" : ""], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_types_bad.out0000664000177100017500000000403713702133370022371 0ustar wsnyderwsnyder%Error: t/t_var_types_bad.v:39:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'bit' : ... In instance t 39 | d_bitz[0] = 1'b1; | ^ %Error: t/t_var_types_bad.v:40:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... In instance t 40 | d_logicz[0] = 1'b1; | ^ %Error: t/t_var_types_bad.v:41:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... In instance t 41 | d_regz[0] = 1'b1; | ^ %Error: t/t_var_types_bad.v:46:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' : ... In instance t 46 | d_real[0] = 1'b1; | ^ %Error: t/t_var_types_bad.v:46:7: Expected integral (non-real) input to SEL : ... In instance t 46 | d_real[0] = 1'b1; | ^~~~~~ %Warning-REALCVT: t/t_var_types_bad.v:46:7: Implicit conversion of real to integer 46 | d_real[0] = 1'b1; | ^~~~~~ ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: t/t_var_types_bad.v:47:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' : ... In instance t 47 | d_realtime[0] = 1'b1; | ^ %Error: t/t_var_types_bad.v:47:7: Expected integral (non-real) input to SEL : ... In instance t 47 | d_realtime[0] = 1'b1; | ^~~~~~~~~~ %Warning-REALCVT: t/t_var_types_bad.v:47:7: Implicit conversion of real to integer 47 | d_realtime[0] = 1'b1; | ^~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_savable.v0000664000177100017500000000522713702133370020624 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); /*verilator no_inline_module*/ // So we'll get hiearachy we can test input clk; sub sub (/*AUTOINST*/ // Inputs .clk (clk)); endmodule module sub (/*AUTOARG*/ // Inputs clk ); input clk; /*verilator no_inline_module*/ // So we'll get hiearachy we can test integer cyc=0; reg [127:0] save128; reg [47:0] save48; reg [1:0] save2; reg [255:0] cycdone; // Make sure each cycle executes exactly once reg [31:0] vec[2:1][2:1]; reg [2:1][2:1][31:0] pvec; real r; string s,s2; string sarr[2:1]; string assoc[string]; string si; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d\n",$time, cyc); `endif si = "siimmed"; cyc <= cyc + 1; if (cycdone[cyc[7:0]]) $stop; cycdone[cyc[7:0]] <= '1; if (cyc==0) begin // Setup save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e; save48 <= 48'h4afe43fb79d7; save2 <= 2'b10; vec[1][1] <= 32'h0101; vec[1][2] <= 32'h0102; vec[2][1] <= 32'h0201; vec[2][2] <= 32'h0202; pvec[1][1] <= 32'h10101; pvec[1][2] <= 32'h10102; pvec[2][1] <= 32'h10201; pvec[2][2] <= 32'h10202; r <= 1.234; s <= "hello"; sarr[1] <= "sarr[1]"; sarr[2] <= "sarr[2]"; assoc["mapped"] <= "Is mapped"; end if (cyc==1) begin if ($test$plusargs("save_restore")!=0) begin // Don't allow the restored model to run from time 0, it must run from a restore $write("%%Error: didn't really restore\n"); $stop; end end else if (cyc==99) begin if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop; if (save48 !== 48'h4afe43fb79d7) $stop; if (save2 !== 2'b10) $stop; if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop; if (vec[1][1] !== 32'h0101) $stop; if (vec[1][2] !== 32'h0102) $stop; if (vec[2][1] !== 32'h0201) $stop; if (vec[2][2] !== 32'h0202) $stop; if (pvec[1][1] !== 32'h10101) $stop; if (pvec[1][2] !== 32'h10102) $stop; if (pvec[2][1] !== 32'h10201) $stop; if (pvec[2][2] !== 32'h10202) $stop; if (r != 1.234) $stop; $display("%s",s); $display("%s",sarr[1]); $display("%s",sarr[2]); if (assoc["mapped"] != "Is mapped") $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_unpacked_concat_bad.v0000664000177100017500000000131113702133370023124 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; initial begin if (count_bits[0] != 16) $stop; if (count_bits[1] != 16) $stop; if (count_bitsc[0] != 16) $stop; if (count_bitsc[1] != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_only.v0000664000177100017500000000042213702133370021206 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); initial begin $stop; end endmodule verilator-4.038/test_regress/t/t_math_pow6.pl0000775000177100017500000000105313702133370021255 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_width.pl0000775000177100017500000000077313702133370021526 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_time_sc_us.pl0000775000177100017500000000141313702133370021503 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_time_sc.v"); $Self->{sc_time_resolution} = 'SC_US'; compile( verilator_flags2 => ['-sc', '-timescale 1us/1us', '+define+TEST_EXPECT=20us'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_rsvd_bad.pl0000775000177100017500000000117113702133370022164 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wwarn-REALCVT"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_memory.cpp0000664000177100017500000001775213702133370021720 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "Vt_vpi_memory.h" #include "verilated.h" #include "svdpi.h" #include "Vt_vpi_memory__Dpi.h" #include "verilated_vpi.h" #include "verilated_vcd_c.h" #endif #include #include #include #include "TestSimulator.h" #include "TestVpi.h" // __FILE__ is too long #define FILENM "t_vpi_memory.cpp" #define DEBUG \ if (0) printf unsigned int main_time = 0; //====================================================================== #define CHECK_RESULT_VH(got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d: GOT = %p EXP = %p\n", FILENM, __LINE__, (got), (exp)); \ return __LINE__; \ } #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ return __LINE__; \ } // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_HEX(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << std::hex \ << ": GOT = " << (got) << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ (got) ? (got) : "", (exp) ? (exp) : ""); \ return __LINE__; \ } #define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp) int _mon_check_range(TestVpiHandle& handle, int size, int left, int right) { TestVpiHandle iter_h, left_h, right_h; s_vpi_value value; value.format = vpiIntVal; value.value.integer = 0; // check size of object int vpisize = vpi_get(vpiSize, handle); CHECK_RESULT(vpisize, size); // check left hand side of range left_h = vpi_handle(vpiLeftRange, handle); CHECK_RESULT_NZ(left_h); vpi_get_value(left_h, &value); CHECK_RESULT(value.value.integer, left); int coherency = value.value.integer; // check right hand side of range right_h = vpi_handle(vpiRightRange, handle); CHECK_RESULT_NZ(right_h); vpi_get_value(right_h, &value); CHECK_RESULT(value.value.integer, right); coherency -= value.value.integer; // calculate size & check coherency = abs(coherency) + 1; CHECK_RESULT(coherency, size); return 0; // Ok } int _mon_check_memory() { int cnt; TestVpiHandle mem_h, lcl_h, side_h; vpiHandle iter_h; // Icarus does not like auto free of iterator handles s_vpi_value value; value.format = vpiIntVal; value.value.integer = 0; s_vpi_error_info e; vpi_printf((PLI_BYTE8*)"Check memory vpi ...\n"); mem_h = vpi_handle_by_name((PLI_BYTE8*)TestSimulator::rooted("mem0"), NULL); CHECK_RESULT_NZ(mem_h); // check type int vpitype = vpi_get(vpiType, mem_h); CHECK_RESULT(vpitype, vpiMemory); if (int status = _mon_check_range(mem_h, 16, 16, 1)) return status; // iterate and store iter_h = vpi_iterate(vpiMemoryWord, mem_h); cnt = 0; while ((lcl_h = vpi_scan(iter_h))) { value.value.integer = ++cnt; vpi_put_value(lcl_h, &value, NULL, vpiNoDelay); // check size and range if (int status = _mon_check_range(lcl_h, 32, 31, 0)) return status; } CHECK_RESULT(cnt, 16); // should be 16 addresses // iterate and accumulate iter_h = vpi_iterate(vpiMemoryWord, mem_h); cnt = 0; while ((lcl_h = vpi_scan(iter_h))) { ++cnt; vpi_get_value(lcl_h, &value); CHECK_RESULT(value.value.integer, cnt); } CHECK_RESULT(cnt, 16); // should be 16 addresses // don't care for non verilator // (crashes on Icarus) if (TestSimulator::is_icarus()) { vpi_printf((PLI_BYTE8*)"Skipping property checks for simulator %s\n", TestSimulator::get_info().product); return 0; // Ok } // make sure trying to get properties that don't exist // doesn't crash int should_be_0 = vpi_get(vpiSize, iter_h); CHECK_RESULT(should_be_0, 0); should_be_0 = vpi_get(vpiIndex, iter_h); CHECK_RESULT(should_be_0, 0); vpiHandle should_be_NULL = vpi_handle(vpiLeftRange, iter_h); CHECK_RESULT(should_be_NULL, 0); should_be_NULL = vpi_handle(vpiRightRange, iter_h); CHECK_RESULT(should_be_NULL, 0); should_be_NULL = vpi_handle(vpiScope, iter_h); CHECK_RESULT(should_be_NULL, 0); // check vpiRange iter_h = vpi_iterate(vpiRange, mem_h); CHECK_RESULT_NZ(iter_h); lcl_h = vpi_scan(iter_h); CHECK_RESULT_NZ(lcl_h); side_h = vpi_handle(vpiLeftRange, lcl_h); CHECK_RESULT_NZ(side_h); vpi_get_value(side_h, &value); CHECK_RESULT(value.value.integer, 16); side_h = vpi_handle(vpiRightRange, lcl_h); CHECK_RESULT_NZ(side_h); vpi_get_value(side_h, &value); CHECK_RESULT(value.value.integer, 1); // check writing to vpiConstant vpi_put_value(side_h, &value, NULL, vpiNoDelay); CHECK_RESULT_NZ(vpi_chk_error(&e)); return 0; // Ok } int mon_check() { // Callback from initial block in monitor if (int status = _mon_check_memory()) return status; return 0; // Ok } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { vpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); // we're going to be checking for these errors do don't crash out Verilated::fatalOnVpiError(0); VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out #ifdef VERILATOR #ifdef TEST_VERBOSE Verilated::scopesDump(); #endif #endif #if VM_TRACE Verilated::traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; main_time += 10; while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += 1; topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } if (!Verilated::gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete topp, topp); exit(0L); } #endif verilator-4.038/test_regress/t/t_var_nonamebegin.pl0000775000177100017500000000133613702133370022507 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['-trace'], ); execute( expect_filename => "t/$Self->{name}__log.out" ); if ($Self->{vlt_all}) { vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } ok(1); 1; verilator-4.038/test_regress/t/t_inst_missing_bad.out0000664000177100017500000000116713702133370023064 0ustar wsnyderwsnyder%Warning-PINNOCONNECT: t/t_inst_missing_bad.v:9:22: Cell pin is not connected: '__pinNumber2' 9 | sub sub (.ok(ok), , .nc()); | ^ ... Use "/* verilator lint_off PINNOCONNECT */" and lint_on around source to disable this message. %Warning-PINCONNECTEMPTY: t/t_inst_missing_bad.v:9:25: Cell pin connected by name with empty reference: 'nc' 9 | sub sub (.ok(ok), , .nc()); | ^~ %Warning-PINMISSING: t/t_inst_missing_bad.v:9:8: Cell has missing pin: 'missing' 9 | sub sub (.ok(ok), , .nc()); | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_clk_2in.cpp0000664000177100017500000000216213702133367021046 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = NULL; void clockit(int clk1, int clk0) { topp->clks = clk1 << 1 | clk0; #ifndef T_CLK_2IN_VEC topp->c1 = clk1; topp->c0 = clk0; #endif #ifdef TEST_VERBOSE printf("[%u] c1=%d c0=%d\n", main_time, clk1, clk0); #endif topp->eval(); main_time++; } int main(int argc, char* argv[]) { topp = new VM_PREFIX; topp->check = 0; clockit(0, 0); main_time += 10; Verilated::debug(0); for (int i = 0; i < 2; i++) { clockit(0, 0); clockit(0, 1); clockit(1, 1); clockit(0, 0); clockit(1, 1); clockit(1, 0); clockit(0, 0); clockit(0, 1); clockit(1, 0); clockit(0, 0); } topp->check = 1; clockit(0, 0); } verilator-4.038/test_regress/t/t_math_signed.v0000664000177100017500000001324713702133370021472 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; by_width #(1) w1 (.clk(clk)); by_width #(31) w31 (.clk(clk)); by_width #(32) w32 (.clk(clk)); by_width #(33) w33 (.clk(clk)); by_width #(63) w63 (.clk(clk)); by_width #(64) w64 (.clk(clk)); by_width #(65) w65 (.clk(clk)); by_width #(95) w95 (.clk(clk)); by_width #(96) w96 (.clk(clk)); by_width #(97) w97 (.clk(clk)); reg signed [15:0] a; reg signed [4:0] b; reg signed [15:0] sr,srs,sl,sls; reg [15:0] b_s; reg [15:0] b_us; task check_s(input signed [7:0] i, input [7:0] expval); //$display("check_s %x\n", i); if (i !== expval) $stop; endtask task check_us(input signed [7:0] i, input [7:0] expval); //$display("check_us %x\n", i); if (i !== expval) $stop; endtask always @* begin sr = a>>b; srs = copy_signed(a)>>>b; sl = a<>>4; // Signed b_us = b[4:0]>>>4; // Unsigned, due to extract check_s ( 3'b111, 8'h07); check_s (3'sb111, 8'hff); check_us( 3'b111, 8'h07); check_us(3'sb111, 8'hff); // Note we sign extend ignoring function's input requirements // verilator lint_on WIDTH end reg signed [32:0] bug349; initial begin end integer i; initial begin if ((-1 >>> 3) != -1) $stop; // Decimals are signed // verilator lint_off WIDTH if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers // verilator lint_on WIDTH if ( (3'sb000 > 3'sb000)) $stop; if (!(3'sb000 > 3'sb111)) $stop; if ( (3'sb111 > 3'sb000)) $stop; if ( (3'sb000 < 3'sb000)) $stop; if ( (3'sb000 < 3'sb111)) $stop; if (!(3'sb111 < 3'sb000)) $stop; if (!(3'sb000 >= 3'sb000)) $stop; if (!(3'sb000 >= 3'sb111)) $stop; if ( (3'sb111 >= 3'sb000)) $stop; if (!(3'sb000 <= 3'sb000)) $stop; if ( (3'sb000 <= 3'sb111)) $stop; if (!(3'sb111 <= 3'sb000)) $stop; // When we multiply overflow, the sign bit stays correct. if ( (4'sd2*4'sd8) != 4'd0) $stop; // From the spec: // verilator lint_off WIDTH i = -12 /3; if (i !== 32'hfffffffc) $stop; i = -'d12 /3; if (i !== 32'h55555551) $stop; i = -'sd12 /3; if (i !== 32'hfffffffc) $stop; i = -4'sd12 /3; if (i !== 32'h00000001) $stop; // verilator lint_on WIDTH // verilator lint_off WIDTH bug349 = 4'sb1111 - 1'b1; if (bug349 != 32'he) $stop; end function signed [15:0] copy_signed; input [15:0] ai; copy_signed = ai; endfunction integer cyc; initial cyc=0; wire [31:0] ucyc = cyc; always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%x %x %x %x %x %x %x\n", cyc, sr,srs,sl,sls, b_s,b_us); `endif case (cyc) 0: begin a <= 16'sh8b1b; b <= 5'sh1f; // -1 end 1: begin // Check spaces in constants a <= 16 'sh 8b1b; b <= 5'sh01; // -1 end 2: begin a <= 16'sh8b1b; b <= 5'sh1e; // shift AMOUNT is really unsigned if (ucyc / 1 != 32'd2) $stop; if (ucyc / 2 != 32'd1) $stop; if (ucyc * 1 != 32'd2) $stop; if (ucyc * 2 != 32'd4) $stop; if (ucyc * 3 != 32'd6) $stop; if (cyc * 32'sd1 != 32'sd2) $stop; if (cyc * 32'sd2 != 32'sd4) $stop; if (cyc * 32'sd3 != 32'sd6) $stop; end 3: begin a <= 16'sh0048; b <= 5'sh1f; if (ucyc * 1 != 32'd3) $stop; if (ucyc * 2 != 32'd6) $stop; if (ucyc * 3 != 32'd9) $stop; if (ucyc * 4 != 32'd12) $stop; if (cyc * 32'sd1 != 32'sd3) $stop; if (cyc * 32'sd2 != 32'sd6) $stop; if (cyc * 32'sd3 != 32'sd9) $stop; end 4: begin a <= 16'sh4154; b <= 5'sh02; end 5: begin a <= 16'shc3e8; b <= 5'sh12; end 6: begin a <= 16'sh488b; b <= 5'sh02; end 9: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase case (cyc) 0: ; 1: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; 2: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh458d_c58d_1636_1636_0000_0000) $stop; 3: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; 4: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_0000_0000_0000_ffff_0001) $stop; 5: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1055_1055_0550_0550_0000_0000) $stop; 6: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; 7: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1222_1222_222c_222c_0000_0000) $stop; 8: ; 9: ; endcase end endmodule module by_width ( input clk ); parameter WIDTH=1; reg signed i1; reg signed [62:0] i63; reg signed [64:0] i65; // verilator lint_off WIDTH wire signed [WIDTH-1:0] i1extp /*verilator public*/ = i1; wire signed [WIDTH-1:0] i1ext = i1; wire signed [WIDTH-1:0] i63ext = i63; wire signed [WIDTH-1:0] i65ext = i65; // verilator lint_on WIDTH integer cyc; initial cyc=0; always @ (posedge clk) begin cyc <= cyc + 1; i1 <= cyc[0]; i63 <= {63{cyc[0]}}; i65 <= {65{cyc[0]}}; case (cyc) 1: begin if (i1extp != {WIDTH{1'b0}}) $stop; if (i1ext != {WIDTH{1'b0}}) $stop; if (i63ext != {WIDTH{1'b0}}) $stop; if (i65ext != {WIDTH{1'b0}}) $stop; end 2: begin if (i1extp != {WIDTH{1'b1}}) $stop; if (i1ext != {WIDTH{1'b1}}) $stop; if (i63ext != {WIDTH{1'b1}}) $stop; if (i65ext != {WIDTH{1'b1}}) $stop; end default: ; endcase end endmodule verilator-4.038/test_regress/t/t_var_suggest_bad.out0000664000177100017500000000066313702133370022707 0ustar wsnyderwsnyder%Error: t/t_var_suggest_bad.v:13:11: Can't find definition of variable: 'foobat' : ... Suggested alternative: 'foobar' 13 | if (foobat) $stop; | ^~~~~~ %Error: t/t_var_suggest_bad.v:14:7: Can't find definition of task/function: 'boobat' : ... Suggested alternative: 'boobar' 14 | boobat; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_sys_fread.out0000664000177100017500000000502313650310376021527 0ustar wsnyderwsnyderDump: r_i: 00010203 r_upb: 0e 0d 0c 0b 0a 09 08 07 06 05 04 r_dnb: 19 18 17 16 15 14 13 12 11 10 0f r_ups: 2e2f 2c2d 2a2b 2829 2627 2425 2223 2021 1e1f 1c1d 1a1b r_dns: 3031 3233 3435 3637 3839 3a3b 3c3d 3e3f 0041 0243 0445 r_upi: 6e6f7071 6a6b6c6d 66676869 62636465 5e5f6061 5a5b5c5d 56575859 52535455 4e4f5051 4a4b4c4d 46474849 r_dni: 72737475 76777879 7a7b7c7d 7e7f8081 02838485 06878889 0a8b8c8d 0e8f9091 12939495 16979899 1a9b9c9d r_upq: 2eeff0f1f2f3f4f5 26e7e8e9eaebeced 1edfe0e1e2e3e4e5 16d7d8d9dadbdcdd 0ecfd0d1d2d3d4d5 06c7c8c9cacbcccd 3ebfc0c1c2c3c4c5 36b7b8b9babbbcbd 2eafb0b1b2b3b4b5 26a7a8a9aaabacad 1e9fa0a1a2a3a4a5 r_dnq: 36f7f8f9fafbfcfd 3eff000102030405 060708090a0b0c0d 0e0f101112131415 161718191a1b1c1d 1e1f202122232425 262728292a2b2c2d 2e2f303132333435 363738393a3b3c3d 3e3f404142434445 064748494a4b4c4d r_upw: a8a9aaabacadaeafb0 9fa0a1a2a3a4a5a6a7 969798999a9b9c9d9e 8d8e8f909192939495 8485868788898a8b8c 7b7c7d7e7f80818283 72737475767778797a 696a6b6c6d6e6f7071 606162636465666768 5758595a5b5c5d5e5f 4e4f50515253545556 r_dnw: b1b2b3b4b5b6b7b8b9 babbbcbdbebfc0c1c2 c3c4c5c6c7c8c9cacb cccdcecfd0d1d2d3d4 d5d6d7d8d9dadbdcdd dedfe0e1e2e3e4e5e6 e7e8e9eaebecedeeef f0f1f2f3f4f5f6f7f8 f9fafbfcfdfeff0001 02030405060708090a 0b0c0d0e0f10111213 Dump: r_i: ffffffff r_upb: 05 04 03 02 01 00 ff ff ff ff ff r_dnb: ff ff ff ff ff ff ff ff ff ff ff r_ups: 3fff 3fff 3fff 3fff 0809 0607 3fff 3fff 3fff 3fff 3fff r_dns: 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff r_upi: 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff r_dni: 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff r_upq: 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff r_dnq: 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff r_upw: ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff r_dnw: ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff *-* All Finished *-* verilator-4.038/test_regress/t/t_trace_abort.out0000664000177100017500000000067713702133370022042 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Wed Jun 10 17:27:15 2020 $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 3 $ cyc [2:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# b000 $ #10 1# b001 $ #15 0# #20 1# b010 $ #25 0# #30 1# b011 $ #35 0# #40 1# b100 $ #45 0# #50 1# b101 $ #55 0# #60 1# b110 $ #65 0# #70 1# b111 $ #75 0# verilator-4.038/test_regress/t/t_tri_gate_notif0.pl0000775000177100017500000000142113702133370022425 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_tri_gate.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ['+define+T_NOTIF0',], make_flags => 'CPPFLAGS_ADD=-DT_NOTIF0', verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_main.pl0000775000177100017500000000125713702133370021274 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--exe --build --main'], verilator_make_cmake => 0, verilator_make_gmake => 0, make_main => 0, ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_udp.out0000664000177100017500000000024713702133370020336 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_udp.v:104:4: Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables. 104 | table | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_wide_out_bad.out0000664000177100017500000000046313702133370023206 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_func_wide_out_bad.v:17:12: Unsupported: Function output argument 'data' requires 4352 bits, but connection's VARREF 'msg' generates 4350 bits. : ... In instance t 17 | func(msg); | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_gen12_noinl.pl0000775000177100017500000000116113702133370023504 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen12.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_x_assign.cpp0000664000177100017500000000255413702133370021337 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include "verilated.h" #include VM_PREFIX_INCLUDE // clang-format off #if defined(T_X_ASSIGN_0) # define EXPECTED 0 #elif defined(T_X_ASSIGN_1) # define EXPECTED 1 #elif defined(T_X_ASSIGN_UNIQUE_0) # define EXPECTED 0 #elif defined(T_X_ASSIGN_UNIQUE_1) # define EXPECTED 1 #else # error "Don't know expectd output for test" #TEST #endif // clang-format on int main(int argc, const char** argv) { VM_PREFIX* top = new VM_PREFIX(); #if defined(T_X_ASSIGN_UNIQUE_0) Verilated::randReset(0); #elif defined(T_X_ASSIGN_UNIQUE_1) Verilated::randReset(1); #endif // Evaluate one clock posedge top->clk = 0; top->eval(); top->clk = 1; top->eval(); if (top->o != EXPECTED) { vl_fatal(__FILE__, __LINE__, "TOP.t", "incorrect module output"); exit(1); } std::cout << "*-* All Finished *-*" << std::endl; return 0; } verilator-4.038/test_regress/t/t_enumeration.pl0000775000177100017500000000115613702133370021703 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug460"); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_const_bad.out0000664000177100017500000000027713702133370022355 0ustar wsnyderwsnyder%Error: t/t_var_const_bad.v:17:7: Assigning to const variable: 'five' : ... In instance t 17 | five = 3'd4; | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_struct_init_bad.pl0000775000177100017500000000121713702133370022530 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_struct_init.v"); lint( v_flags2 => ['+define+T_STRUCT_INIT_BAD'], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex_params.pl0000775000177100017500000000144313702133370023544 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_complex.v"); compile( verilator_flags2 => ['--cc --trace --no-trace-structs --trace-params'], ); execute( check_finished => 1, ); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ PARAM /); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_class_extends_bad.v0000664000177100017500000000052013702133367022651 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base1; endclass class Base2; endclass class Cls extends Base1, Base2; endclass module t (/*AUTOARG*/); endmodule verilator-4.038/test_regress/t/t_clk_2in.pl0000775000177100017500000000127513702133367020706 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"], vcs_flags2 => ['-assert'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_in_assign_bad.v0000664000177100017500000000074313702133370022635 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [3:0] value; assign value = 4'h0; sub sub(.valueSub(value[3:0])); endmodule module sub (/*AUTOARG*/ // Inputs valueSub ); input [3:0] valueSub; assign valueSub = 4'h0; endmodule verilator-4.038/test_regress/t/t_time_sc.v0000664000177100017500000000133613702133370020627 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; time texpect = `TEST_EXPECT; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin $printtimescale; $write("[%0t] In %m: Hi - expect this is %0t\n", $time, texpect); if ($time != texpect) begin $write("[%0t] delta = %d\n", $time, $time - texpect); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_var_port2_bad.v0000664000177100017500000000041513702133370021725 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (portwithoin); input portwithin; endmodule verilator-4.038/test_regress/t/t_gen_forif.pl0000775000177100017500000000111313702133370021304 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( nc_flags2 => ['+access+r'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_fi.cpp0000664000177100017500000000140613702133370021106 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include "Vt_flag_fi.h" //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = NULL; bool gotit = false; void myfunction() { gotit = true; } int main(int argc, char* argv[]) { topp = new VM_PREFIX; Verilated::debug(0); topp->eval(); if (!gotit) { vl_fatal(__FILE__, __LINE__, "dut", "Never got call to myfunction"); } topp->final(); return 0; } verilator-4.038/test_regress/t/t_gate_elim.pl0000775000177100017500000000105313702133370021277 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_timescale_override.v0000664000177100017500000000054213702133370024040 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1s/1s module t; initial begin $printtimescale; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_subout_bad.out0000664000177100017500000000133513702133370022722 0ustar wsnyderwsnyder%Error-PORTSHORT: t/t_lint_subout_bad.v:12:14: Output port is connected to a constant pin, electrical short : ... In instance t 12 | sub sub1(.out({32'b0, sig})); | ^~~ %Error-PORTSHORT: t/t_lint_subout_bad.v:13:14: Output port is connected to a constant pin, electrical short : ... In instance t 13 | sub sub2(.out({32'b1, sig})); | ^~~ %Error-PORTSHORT: t/t_lint_subout_bad.v:11:14: Output port is connected to a constant pin, electrical short : ... In instance t 11 | sub sub0(.out(33'b0)); | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_clocker.pl0000775000177100017500000000122613702133367021003 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--trace"] ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_const_bad.out0000664000177100017500000000175113702133367021511 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_const_bad.v:13:39: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : ... In instance t 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; | ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... In instance t 14 | if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; | ^~~ %Warning-WIDTH: t/t_const_bad.v:15:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... In instance t 15 | if (68'h?_????????_???????? !== 'd?) $stop; | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface1.pl0000775000177100017500000000106013702133370021370 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_shortreal.v0000664000177100017500000001054213702133370022217 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off SHORTREAL integer i; reg [63:0] b; shortreal r, r2; integer cyc=0; realtime uninit; initial if (uninit != 0.0) $stop; initial begin if (1_00_0.0_1 != 1000.01) $stop; // rtoi truncates if ($rtoi(36.7) != 36) $stop; if ($rtoi(36.5) != 36) $stop; if ($rtoi(36.4) != 36) $stop; // casting rounds if ((integer '(36.7)) != 37) $stop; if ((integer '(36.5)) != 37) $stop; if ((integer '(36.4)) != 36) $stop; // assignment rounds // verilator lint_off REALCVT i = 36.7; if (i != 37) $stop; i = 36.5; if (i != 37) $stop; i = 36.4; if (i != 36) $stop; r = 10'd38; if (r!=38.0) $stop; // verilator lint_on REALCVT // operators if ((-(1.5)) != -1.5) $stop; if ((+(1.5)) != 1.5) $stop; if (((1.5)+(1.25)) != 2.75) $stop; if (((1.5)-(1.25)) != 0.25) $stop; if (((1.5)*(1.25)) != 1.875) $stop; if (((1.5)/(1.25)) != 1.2) $stop; // if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0 if (((1.5)!=(2)) != 1'b1) $stop; if (((1.5)> (2)) != 1'b0) $stop; if (((1.5)>=(2)) != 1'b0) $stop; if (((1.5)< (2)) != 1'b1) $stop; if (((1.5)<=(2)) != 1'b1) $stop; if (((1.5)==(1.5)) != 1'b1) $stop; if (((1.5)!=(1.5)) != 1'b0) $stop; if (((1.5)> (1.5)) != 1'b0) $stop; if (((1.5)>=(1.5)) != 1'b1) $stop; if (((1.5)< (1.5)) != 1'b0) $stop; if (((1.5)<=(1.5)) != 1'b1) $stop; if (((1.6)==(1.5)) != 1'b0) $stop; if (((1.6)!=(1.5)) != 1'b1) $stop; if (((1.6)> (1.5)) != 1'b1) $stop; if (((1.6)>=(1.5)) != 1'b1) $stop; if (((1.6)< (1.5)) != 1'b0) $stop; if (((1.6)<=(1.5)) != 1'b0) $stop; // if (((0.0)?(2.0):(1.1)) != 1.1) $stop; if (((1.5)?(2.0):(1.1)) != 2.0) $stop; // if (!1.7) $stop; if (!(!0.0)) $stop; if (1.8 && 0.0) $stop; if (!(1.8 || 0.0)) $stop; // i=0; for (r=1.0; r<2.0; r=r+0.1) i++; if (i!=10) $stop; // bug r = $bitstoshortreal($shortrealtobits(1.414)); if (r != 1.414) $stop; end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; if (cyc==0) begin // Setup end else if (cyc<90) begin if ($time != {32'h0, $rtoi($realtime)}) $stop; if ($itor(cyc) != cyc) $stop; //Unsup: if ((real `($time)) != $realtime) $stop; r = $itor(cyc*2); i = $rtoi(r); if (i!=cyc*2) $stop; // r = $itor(cyc)/1.5; b = $realtobits(r); r2 = $bitstoreal(b); if (r != r2) $stop; // // Trust the integer math as a comparison r = $itor(cyc); if ($rtoi(-r) != -cyc) $stop; if ($rtoi(+r) != cyc) $stop; if ($rtoi(r+2.0) != (cyc+2)) $stop; if ($rtoi(r-2.0) != (cyc-2)) $stop; if ($rtoi(r*2.0) != (cyc*2)) $stop; if ($rtoi(r/2.0) != (cyc/2)) $stop; r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash // r2 = $itor(cyc); case (r) (r2-1.0): $stop; r2: ; default: $stop; endcase // r = $itor(cyc); if ((r==50.0) != (cyc==50)) $stop; if ((r!=50.0) != (cyc!=50)) $stop; if ((r> 50.0) != (cyc> 50)) $stop; if ((r>=50.0) != (cyc>=50)) $stop; if ((r< 50.0) != (cyc< 50)) $stop; if ((r<=50.0) != (cyc<=50)) $stop; // if ($rtoi((r-50.0) ? 10.0 : 20.0) != (((cyc-50)!=0) ? 10 : 20)) $stop; // if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_emit_constw.v0000664000177100017500000001342413702133370021540 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkhw(gotv,w,expv) do if (gotv[(w)*32+:$bits(expv)] !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv[(w)*32+:32]), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad}; bit [8*32-2:0] w8m = {31'h7146e1bf, 32'ha8549e42, 32'hca6960bd, 32'h191b7f9b, 32'h93d79866, 32'hf4489e2b, 32'h8e9a3236, 32'h1d2a2d1d}; bit [8*32-1:0] w8 = {32'hc211addc, 32'he5d4a057, 32'h5cbf88fe, 32'h42cf42e2, 32'heb584263, 32'ha585f118, 32'h231531c8, 32'hc73f7b06}; bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199}; bit [9*32-1:0] w9 = {32'hca800ac1, 32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621}; bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32, 32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8}; bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e, 32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784}; bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e, 32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302}; bit [17*32-1:0] w17 = {32'hf1e322ac, 32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23, 32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1}; function [7:0] bytehash (input [32*32-1:0] data); integer i; bytehash = 0; for (i=0; i<32*32; ++i) begin bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8]; end return bytehash; endfunction // Aggregate outputs into a single result vector // verilator lint_off WIDTH wire [63:0] result = (bytehash(w4) ^ bytehash(w8m) ^ bytehash(w8) ^ bytehash(w8p) ^ bytehash(w9) ^ bytehash(w16m) ^ bytehash(w16) ^ bytehash(w16p) ^ bytehash(w17)); // verilator lint_on WIDTH `define EXPECTED_SUM 64'hb6fdb64085fc17f5 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; // verilator lint_off SELRANGE `checkhw(w4,3,32'h7c709753); `checkhw(w4,2,32'hbc8f6059); `checkhw(w4,1,32'h3b0db464); `checkhw(w4,0,32'h721a8fad); `checkhw(w8m,7,31'h7146e1bf); `checkhw(w8m,6,32'ha8549e42); `checkhw(w8m,5,32'hca6960bd); `checkhw(w8m,4,32'h191b7f9b); `checkhw(w8m,3,32'h93d79866); `checkhw(w8m,2,32'hf4489e2b); `checkhw(w8m,1,32'h8e9a3236); `checkhw(w8m,0,32'h1d2a2d1d); `checkhw(w8,7,32'hc211addc); `checkhw(w8,6,32'he5d4a057); `checkhw(w8,5,32'h5cbf88fe); `checkhw(w8,4,32'h42cf42e2); `checkhw(w8,3,32'heb584263); `checkhw(w8,2,32'ha585f118); `checkhw(w8,1,32'h231531c8); `checkhw(w8,0,32'hc73f7b06); `checkhw(w8p,8,1'b1); `checkhw(w8p,7,32'h096aa54b); `checkhw(w8p,6,32'h48aae18e); `checkhw(w8p,5,32'hf9502cea); `checkhw(w8p,4,32'h518c8b61); `checkhw(w8p,3,32'h9e8641a2); `checkhw(w8p,2,32'h0dc0249c); `checkhw(w8p,1,32'hd421a87a); `checkhw(w8p,0,32'hb8ee9199); `checkhw(w9,8,32'hca800ac1); `checkhw(w9,7,32'h0de4823a); `checkhw(w9,6,32'ha51663ac); `checkhw(w9,5,32'h96351446); `checkhw(w9,4,32'h6b0bbcd5); `checkhw(w9,3,32'h4a64b530); `checkhw(w9,2,32'h4967d59a); `checkhw(w9,1,32'hfcc17292); `checkhw(w9,0,32'h57926621); `checkhw(w16m,15,31'h77ad72c7); `checkhw(w16m,14,32'h73aa9cbb); `checkhw(w16m,13,32'h7ecf026d); `checkhw(w16m,12,32'h985a3ed2); `checkhw(w16m,11,32'hfe961c1d); `checkhw(w16m,10,32'h7a01df72); `checkhw(w16m,9,32'h79e13d71); `checkhw(w16m,8,32'hb69e2e32); `checkhw(w16m,7,32'h09fcbc45); `checkhw(w16m,6,32'hcfd738c1); `checkhw(w16m,5,32'hc197ac7c); `checkhw(w16m,4,32'hc316d727); `checkhw(w16m,3,32'h903034e4); `checkhw(w16m,2,32'h92a047d1); `checkhw(w16m,1,32'h6a5357af); `checkhw(w16m,0,32'ha82ce9c8); // verilator lint_on SELRANGE end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin w4 = w4 >>> 1; w8m = w8m >>> 1; w8 = w8 >>> 1; w8p = w8p >>> 1; w9 = w9 >>> 1; w16m = w16m >>> 1; w16 = w16 >>> 1; w16p = w16p >>> 1; w17 = w17 >>> 1; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_udp.v0000664000177100017500000000734613702133370020003 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Async clears must not race with clocks if we want repeatable results reg set_l = in[20]; reg clr_l = in[21]; always @ (negedge clk) begin set_l <= in[20]; clr_l <= in[21]; end //====== Mux wire [1:0] qm; // delay z a b sel udp_mux2 #(0.1) m0 (qm[0], in[0], in[2], in[4]); udp_mux2 #0.1 m1 (qm[1], in[1], in[3], in[4]); `define verilatorxx `ifdef verilatorxx reg [1:0] ql; reg [1:0] qd; // No sequential tables, yet // always @* begin // if (!clk) ql = in[13:12]; // end always @(posedge clk or negedge set_l or negedge clr_l) begin if (!set_l) qd <= ~2'b0; else if (!clr_l) qd <= 2'b0; else qd <= in[17:16]; end `else //====== Latch // wire [1:0] ql; // // q clk d // udp_latch l0 (ql[0], !in[8], in[12]); // udp_latch l1 (ql[1], !in[8], in[13]); //====== DFF wire [1:0] qd; //always @* $display("UL q=%b c=%b d=%b", ql[1:0], in[8], in[13:12]); // q clk d set_l clr_l udp_dff d0 (qd[0], in[8], in[16], set_l, clr_l); udp_dff d2 (qd[1], in[8], in[17], set_l, clr_l); `endif // Aggregate outputs into a single result vector wire [63:0] result = {52'h0, 2'b0,qd, 4'b0, 2'b0,qm}; // wire [63:0] result = {52'h0, 2'b0,qd, 2'b0,ql, 2'b0,qm}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) // Note not all simulators agree about the latch result. Maybe have a race? `define EXPECTED_SUM 64'hb73acf228acaeaa3 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule primitive udp_mux2 (z, a, b, sel); output z; input a, b, sel; table //a b s o ? 1 1 : 1 ; ? 0 1 : 0 ; 1 ? 0 : 1 ; 0 ? 0 : 0 ; 1 1 x : 1 ; 0 0 x : 0 ; endtable endprimitive primitive udp_latch (q, clk, d); output q; reg q; input clk, d; table //clk d q q' 0 1 : ? : 1; 0 0 : ? : 0; 1 ? : ? : -; endtable endprimitive primitive udp_dff (q, clk, d, set_l, clr_l); output q; input clk, d, set_l, clr_l; reg q; table //ck d s c : q : q' r 0 1 ? : ? : 0 ; r 1 ? 1 : ? : 1 ; * 1 ? 1 : 1 : 1 ; * 0 1 ? : 0 : 0 ; f ? ? ? : ? : - ; b * ? ? : ? : - ; ? ? 0 ? : ? : 1 ; b ? * 1 : 1 : 1 ; x 1 * 1 : 1 : 1 ; ? ? 1 0 : ? : 0 ; b ? 1 * : 0 : 0 ; x 0 1 * : 0 : 0 ; endtable endprimitive verilator-4.038/test_regress/t/t_case_write2_tasks.v0000664000177100017500000025441713702133367022640 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "verilated.v" module t_case_write2_tasks (); // verilator lint_off WIDTH // verilator lint_off CASEINCOMPLETE `define FD_BITS 31:0 parameter STRLEN = 78; task ozonerab; input [6:0] rab; input [`FD_BITS] fd; // verilator no_inline_task begin case (rab[6:0]) 7'h00 : $fwrite (fd, " 0"); 7'h01 : $fwrite (fd, " 1"); 7'h02 : $fwrite (fd, " 2"); 7'h03 : $fwrite (fd, " 3"); 7'h04 : $fwrite (fd, " 4"); 7'h05 : $fwrite (fd, " 5"); 7'h06 : $fwrite (fd, " 6"); 7'h07 : $fwrite (fd, " 7"); 7'h08 : $fwrite (fd, " 8"); 7'h09 : $fwrite (fd, " 9"); 7'h0a : $fwrite (fd, " 10"); 7'h0b : $fwrite (fd, " 11"); 7'h0c : $fwrite (fd, " 12"); 7'h0d : $fwrite (fd, " 13"); 7'h0e : $fwrite (fd, " 14"); 7'h0f : $fwrite (fd, " 15"); 7'h10 : $fwrite (fd, " 16"); 7'h11 : $fwrite (fd, " 17"); 7'h12 : $fwrite (fd, " 18"); 7'h13 : $fwrite (fd, " 19"); 7'h14 : $fwrite (fd, " 20"); 7'h15 : $fwrite (fd, " 21"); 7'h16 : $fwrite (fd, " 22"); 7'h17 : $fwrite (fd, " 23"); 7'h18 : $fwrite (fd, " 24"); 7'h19 : $fwrite (fd, " 25"); 7'h1a : $fwrite (fd, " 26"); 7'h1b : $fwrite (fd, " 27"); 7'h1c : $fwrite (fd, " 28"); 7'h1d : $fwrite (fd, " 29"); 7'h1e : $fwrite (fd, " 30"); 7'h1f : $fwrite (fd, " 31"); 7'h20 : $fwrite (fd, " 32"); 7'h21 : $fwrite (fd, " 33"); 7'h22 : $fwrite (fd, " 34"); 7'h23 : $fwrite (fd, " 35"); 7'h24 : $fwrite (fd, " 36"); 7'h25 : $fwrite (fd, " 37"); 7'h26 : $fwrite (fd, " 38"); 7'h27 : $fwrite (fd, " 39"); 7'h28 : $fwrite (fd, " 40"); 7'h29 : $fwrite (fd, " 41"); 7'h2a : $fwrite (fd, " 42"); 7'h2b : $fwrite (fd, " 43"); 7'h2c : $fwrite (fd, " 44"); 7'h2d : $fwrite (fd, " 45"); 7'h2e : $fwrite (fd, " 46"); 7'h2f : $fwrite (fd, " 47"); 7'h30 : $fwrite (fd, " 48"); 7'h31 : $fwrite (fd, " 49"); 7'h32 : $fwrite (fd, " 50"); 7'h33 : $fwrite (fd, " 51"); 7'h34 : $fwrite (fd, " 52"); 7'h35 : $fwrite (fd, " 53"); 7'h36 : $fwrite (fd, " 54"); 7'h37 : $fwrite (fd, " 55"); 7'h38 : $fwrite (fd, " 56"); 7'h39 : $fwrite (fd, " 57"); 7'h3a : $fwrite (fd, " 58"); 7'h3b : $fwrite (fd, " 59"); 7'h3c : $fwrite (fd, " 60"); 7'h3d : $fwrite (fd, " 61"); 7'h3e : $fwrite (fd, " 62"); 7'h3f : $fwrite (fd, " 63"); 7'h40 : $fwrite (fd, " 64"); 7'h41 : $fwrite (fd, " 65"); 7'h42 : $fwrite (fd, " 66"); 7'h43 : $fwrite (fd, " 67"); 7'h44 : $fwrite (fd, " 68"); 7'h45 : $fwrite (fd, " 69"); 7'h46 : $fwrite (fd, " 70"); 7'h47 : $fwrite (fd, " 71"); 7'h48 : $fwrite (fd, " 72"); 7'h49 : $fwrite (fd, " 73"); 7'h4a : $fwrite (fd, " 74"); 7'h4b : $fwrite (fd, " 75"); 7'h4c : $fwrite (fd, " 76"); 7'h4d : $fwrite (fd, " 77"); 7'h4e : $fwrite (fd, " 78"); 7'h4f : $fwrite (fd, " 79"); 7'h50 : $fwrite (fd, " 80"); 7'h51 : $fwrite (fd, " 81"); 7'h52 : $fwrite (fd, " 82"); 7'h53 : $fwrite (fd, " 83"); 7'h54 : $fwrite (fd, " 84"); 7'h55 : $fwrite (fd, " 85"); 7'h56 : $fwrite (fd, " 86"); 7'h57 : $fwrite (fd, " 87"); 7'h58 : $fwrite (fd, " 88"); 7'h59 : $fwrite (fd, " 89"); 7'h5a : $fwrite (fd, " 90"); 7'h5b : $fwrite (fd, " 91"); 7'h5c : $fwrite (fd, " 92"); 7'h5d : $fwrite (fd, " 93"); 7'h5e : $fwrite (fd, " 94"); 7'h5f : $fwrite (fd, " 95"); 7'h60 : $fwrite (fd, " 96"); 7'h61 : $fwrite (fd, " 97"); 7'h62 : $fwrite (fd, " 98"); 7'h63 : $fwrite (fd, " 99"); 7'h64 : $fwrite (fd, " 100"); 7'h65 : $fwrite (fd, " 101"); 7'h66 : $fwrite (fd, " 102"); 7'h67 : $fwrite (fd, " 103"); 7'h68 : $fwrite (fd, " 104"); 7'h69 : $fwrite (fd, " 105"); 7'h6a : $fwrite (fd, " 106"); 7'h6b : $fwrite (fd, " 107"); 7'h6c : $fwrite (fd, " 108"); 7'h6d : $fwrite (fd, " 109"); 7'h6e : $fwrite (fd, " 110"); 7'h6f : $fwrite (fd, " 111"); 7'h70 : $fwrite (fd, " 112"); 7'h71 : $fwrite (fd, " 113"); 7'h72 : $fwrite (fd, " 114"); 7'h73 : $fwrite (fd, " 115"); 7'h74 : $fwrite (fd, " 116"); 7'h75 : $fwrite (fd, " 117"); 7'h76 : $fwrite (fd, " 118"); 7'h77 : $fwrite (fd, " 119"); 7'h78 : $fwrite (fd, " 120"); 7'h79 : $fwrite (fd, " 121"); 7'h7a : $fwrite (fd, " 122"); 7'h7b : $fwrite (fd, " 123"); 7'h7c : $fwrite (fd, " 124"); 7'h7d : $fwrite (fd, " 125"); 7'h7e : $fwrite (fd, " 126"); 7'h7f : $fwrite (fd, " 127"); default:$fwrite (fd, " 128"); endcase end endtask task ozonerb; input [5:0] rb; input [`FD_BITS] fd; // verilator no_inline_task begin case (rb[5:0]) 6'h10, 6'h17, 6'h1e, 6'h1f: $fwrite (fd, " 129"); default: ozonerab({1'b1, rb}, fd); endcase end endtask task ozonef3f4_iext; input [1:0] foo; input [15:0] im16; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo) 2'h0 : begin skyway({4{im16[15]}}, fd); skyway({4{im16[15]}}, fd); skyway(im16[15:12], fd); skyway(im16[11: 8], fd); skyway(im16[ 7: 4], fd); skyway(im16[ 3:0], fd); $fwrite (fd, " 130"); end 2'h1 : begin $fwrite (fd, " 131"); skyway(im16[15:12], fd); skyway(im16[11: 8], fd); skyway(im16[ 7: 4], fd); skyway(im16[ 3:0], fd); end 2'h2 : begin skyway({4{im16[15]}}, fd); skyway({4{im16[15]}}, fd); skyway(im16[15:12], fd); skyway(im16[11: 8], fd); skyway(im16[ 7: 4], fd); skyway(im16[ 3:0], fd); $fwrite (fd, " 132"); end 2'h3 : begin $fwrite (fd, " 133"); skyway(im16[15:12], fd); skyway(im16[11: 8], fd); skyway(im16[ 7: 4], fd); skyway(im16[ 3:0], fd); end endcase end endtask task skyway; input [ 3:0] hex; input [`FD_BITS] fd; // verilator no_inline_task begin case (hex) 4'h0 : $fwrite (fd, " 134"); 4'h1 : $fwrite (fd, " 135"); 4'h2 : $fwrite (fd, " 136"); 4'h3 : $fwrite (fd, " 137"); 4'h4 : $fwrite (fd, " 138"); 4'h5 : $fwrite (fd, " 139"); 4'h6 : $fwrite (fd, " 140"); 4'h7 : $fwrite (fd, " 141"); 4'h8 : $fwrite (fd, " 142"); 4'h9 : $fwrite (fd, " 143"); 4'ha : $fwrite (fd, " 144"); 4'hb : $fwrite (fd, " 145"); 4'hc : $fwrite (fd, " 146"); 4'hd : $fwrite (fd, " 147"); 4'he : $fwrite (fd, " 148"); 4'hf : $fwrite (fd, " 149"); endcase end endtask task ozonesr; input [ 15:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[11: 9]) 3'h0 : $fwrite (fd, " 158"); 3'h1 : $fwrite (fd, " 159"); 3'h2 : $fwrite (fd, " 160"); 3'h3 : $fwrite (fd, " 161"); 3'h4 : $fwrite (fd, " 162"); 3'h5 : $fwrite (fd, " 163"); 3'h6 : $fwrite (fd, " 164"); 3'h7 : $fwrite (fd, " 165"); endcase end endtask task ozonejk; input k; input [`FD_BITS] fd; // verilator no_inline_task begin if (k) $fwrite (fd, " 166"); else $fwrite (fd, " 167"); end endtask task ozoneae; input [ 2:0] ae; input [`FD_BITS] fd; // verilator no_inline_task begin case (ae) 3'b000 : $fwrite (fd, " 168"); 3'b001 : $fwrite (fd, " 169"); 3'b010 : $fwrite (fd, " 170"); 3'b011 : $fwrite (fd, " 171"); 3'b100 : $fwrite (fd, " 172"); 3'b101 : $fwrite (fd, " 173"); 3'b110 : $fwrite (fd, " 174"); 3'b111 : $fwrite (fd, " 175"); endcase end endtask task ozoneaee; input [ 2:0] aee; input [`FD_BITS] fd; // verilator no_inline_task begin case (aee) 3'b001, 3'b011, 3'b101, 3'b111 : $fwrite (fd, " 176"); 3'b000 : $fwrite (fd, " 177"); 3'b010 : $fwrite (fd, " 178"); 3'b100 : $fwrite (fd, " 179"); 3'b110 : $fwrite (fd, " 180"); endcase end endtask task ozoneape; input [ 2:0] ape; input [`FD_BITS] fd; // verilator no_inline_task begin case (ape) 3'b001, 3'b011, 3'b101, 3'b111 : $fwrite (fd, " 181"); 3'b000 : $fwrite (fd, " 182"); 3'b010 : $fwrite (fd, " 183"); 3'b100 : $fwrite (fd, " 184"); 3'b110 : $fwrite (fd, " 185"); endcase end endtask task ozonef1; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[24:21]) 4'h0 : if (foo[26]) $fwrite (fd, " 186"); else $fwrite (fd, " 187"); 4'h1 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 188"); 2'b01 : $fwrite (fd, " 189"); 2'b10 : $fwrite (fd, " 190"); 2'b11 : $fwrite (fd, " 191"); endcase 4'h2 : $fwrite (fd, " 192"); 4'h3 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 193"); 2'b01 : $fwrite (fd, " 194"); 2'b10 : $fwrite (fd, " 195"); 2'b11 : $fwrite (fd, " 196"); endcase 4'h4 : if (foo[26]) $fwrite (fd, " 197"); else $fwrite (fd, " 198"); 4'h5 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 199"); 2'b01 : $fwrite (fd, " 200"); 2'b10 : $fwrite (fd, " 201"); 2'b11 : $fwrite (fd, " 202"); endcase 4'h6 : $fwrite (fd, " 203"); 4'h7 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 204"); 2'b01 : $fwrite (fd, " 205"); 2'b10 : $fwrite (fd, " 206"); 2'b11 : $fwrite (fd, " 207"); endcase 4'h8 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 208"); 2'b01 : $fwrite (fd, " 209"); 2'b10 : $fwrite (fd, " 210"); 2'b11 : $fwrite (fd, " 211"); endcase 4'h9 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 212"); 2'b01 : $fwrite (fd, " 213"); 2'b10 : $fwrite (fd, " 214"); 2'b11 : $fwrite (fd, " 215"); endcase 4'ha : if (foo[25]) $fwrite (fd, " 216"); else $fwrite (fd, " 217"); 4'hb : if (foo[25]) $fwrite (fd, " 218"); else $fwrite (fd, " 219"); 4'hc : if (foo[26]) $fwrite (fd, " 220"); else $fwrite (fd, " 221"); 4'hd : case (foo[26:25]) 2'b00 : $fwrite (fd, " 222"); 2'b01 : $fwrite (fd, " 223"); 2'b10 : $fwrite (fd, " 224"); 2'b11 : $fwrite (fd, " 225"); endcase 4'he : case (foo[26:25]) 2'b00 : $fwrite (fd, " 226"); 2'b01 : $fwrite (fd, " 227"); 2'b10 : $fwrite (fd, " 228"); 2'b11 : $fwrite (fd, " 229"); endcase 4'hf : case (foo[26:25]) 2'b00 : $fwrite (fd, " 230"); 2'b01 : $fwrite (fd, " 231"); 2'b10 : $fwrite (fd, " 232"); 2'b11 : $fwrite (fd, " 233"); endcase endcase end endtask task ozonef1e; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[27:21]) 7'h00: begin ozoneae(foo[20:18], fd); $fwrite (fd," 234"); $fwrite (fd, " 235"); end 7'h01: begin ozoneae(foo[20:18], fd); $fwrite (fd," 236"); ozoneae(foo[17:15], fd); $fwrite (fd," 237"); $fwrite (fd, " 238"); end 7'h02: $fwrite (fd, " 239"); 7'h03: begin ozoneae(foo[20:18], fd); $fwrite (fd," 240"); ozoneae(foo[17:15], fd); $fwrite (fd," 241"); $fwrite (fd, " 242"); end 7'h04: begin ozoneae(foo[20:18], fd); $fwrite (fd," 243"); $fwrite (fd," 244"); end 7'h05: begin ozoneae(foo[20:18], fd); $fwrite (fd," 245"); ozoneae(foo[17:15], fd); $fwrite (fd," 246"); end 7'h06: $fwrite (fd, " 247"); 7'h07: begin ozoneae(foo[20:18], fd); $fwrite (fd," 248"); ozoneae(foo[17:15], fd); $fwrite (fd," 249"); end 7'h08: begin ozoneae(foo[20:18], fd); $fwrite (fd," 250"); ozoneae(foo[17:15], fd); $fwrite (fd," 251"); end 7'h09: begin ozoneae(foo[20:18], fd); $fwrite (fd," 252"); ozoneae(foo[17:15], fd); $fwrite (fd," 253"); end 7'h0a: begin ozoneae(foo[17:15], fd); $fwrite (fd," 254"); end 7'h0b: begin ozoneae(foo[17:15], fd); $fwrite (fd," 255"); end 7'h0c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 256"); end 7'h0d: begin ozoneae(foo[20:18], fd); $fwrite (fd," 257"); ozoneae(foo[17:15], fd); $fwrite (fd," 258"); end 7'h0e: begin ozoneae(foo[20:18], fd); $fwrite (fd," 259"); ozoneae(foo[17:15], fd); $fwrite (fd," 260"); end 7'h0f: begin ozoneae(foo[20:18], fd); $fwrite (fd," 261"); ozoneae(foo[17:15], fd); $fwrite (fd," 262"); end 7'h10: begin ozoneae(foo[20:18], fd); $fwrite (fd," 263"); ozoneae(foo[17:15], fd); $fwrite (fd," 264"); $fwrite (fd, " 265"); $fwrite (fd, " 266"); end 7'h11: begin ozoneae(foo[20:18], fd); $fwrite (fd," 267"); ozoneae(foo[17:15], fd); $fwrite (fd," 268"); $fwrite (fd, " 269"); $fwrite (fd, " 270"); end 7'h12: begin ozoneae(foo[20:18], fd); $fwrite (fd," 271"); ozoneae(foo[17:15], fd); $fwrite (fd," 272"); $fwrite (fd, " 273"); $fwrite (fd, " 274"); end 7'h13: begin ozoneae(foo[20:18], fd); $fwrite (fd," 275"); ozoneae(foo[17:15], fd); $fwrite (fd," 276"); $fwrite (fd, " 277"); $fwrite (fd, " 278"); end 7'h14: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 279"); ozoneaee(foo[17:15], fd); $fwrite (fd," 280"); ozoneape(foo[20:18], fd); $fwrite (fd," 281"); ozoneape(foo[17:15], fd); $fwrite (fd," 282"); $fwrite (fd, " 283"); $fwrite (fd, " 284"); end 7'h15: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 285"); ozoneaee(foo[17:15], fd); $fwrite (fd," 286"); ozoneape(foo[20:18], fd); $fwrite (fd," 287"); ozoneape(foo[17:15], fd); $fwrite (fd," 288"); $fwrite (fd, " 289"); $fwrite (fd, " 290"); end 7'h16: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 291"); ozoneaee(foo[17:15], fd); $fwrite (fd," 292"); ozoneape(foo[20:18], fd); $fwrite (fd," 293"); ozoneape(foo[17:15], fd); $fwrite (fd," 294"); $fwrite (fd, " 295"); $fwrite (fd, " 296"); end 7'h17: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 297"); ozoneaee(foo[17:15], fd); $fwrite (fd," 298"); ozoneape(foo[20:18], fd); $fwrite (fd," 299"); ozoneape(foo[17:15], fd); $fwrite (fd," 300"); $fwrite (fd, " 301"); $fwrite (fd, " 302"); end 7'h18: begin ozoneae(foo[20:18], fd); $fwrite (fd," 303"); ozoneae(foo[17:15], fd); $fwrite (fd," 304"); $fwrite (fd, " 305"); $fwrite (fd, " 306"); end 7'h19: begin ozoneae(foo[20:18], fd); $fwrite (fd," 307"); ozoneae(foo[17:15], fd); $fwrite (fd," 308"); $fwrite (fd, " 309"); $fwrite (fd, " 310"); end 7'h1a: begin ozoneae(foo[20:18], fd); $fwrite (fd," 311"); ozoneae(foo[17:15], fd); $fwrite (fd," 312"); $fwrite (fd, " 313"); $fwrite (fd, " 314"); end 7'h1b: begin ozoneae(foo[20:18], fd); $fwrite (fd," 315"); ozoneae(foo[17:15], fd); $fwrite (fd," 316"); $fwrite (fd, " 317"); $fwrite (fd, " 318"); end 7'h1c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 319"); ozoneae(foo[17:15], fd); $fwrite (fd," 320"); $fwrite (fd, " 321"); $fwrite (fd, " 322"); end 7'h1d: begin ozoneae(foo[20:18], fd); $fwrite (fd," 323"); ozoneae(foo[17:15], fd); $fwrite (fd," 324"); $fwrite (fd, " 325"); $fwrite (fd, " 326"); end 7'h1e: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 327"); ozoneaee(foo[17:15], fd); $fwrite (fd," 328"); ozoneape(foo[20:18], fd); $fwrite (fd," 329"); ozoneape(foo[17:15], fd); $fwrite (fd," 330"); $fwrite (fd, " 331"); $fwrite (fd, " 332"); end 7'h1f: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 333"); ozoneaee(foo[17:15], fd); $fwrite (fd," 334"); ozoneape(foo[20:18], fd); $fwrite (fd," 335"); ozoneape(foo[17:15], fd); $fwrite (fd," 336"); $fwrite (fd, " 337"); $fwrite (fd, " 338"); end 7'h20: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 339"); ozoneaee(foo[17:15], fd); $fwrite (fd," 340"); ozoneape(foo[20:18], fd); $fwrite (fd," 341"); ozoneape(foo[17:15], fd); $fwrite (fd," 342"); $fwrite (fd, " 343"); $fwrite (fd, " 344"); end 7'h21: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 345"); ozoneaee(foo[17:15], fd); $fwrite (fd," 346"); ozoneape(foo[20:18], fd); $fwrite (fd," 347"); ozoneape(foo[17:15], fd); $fwrite (fd," 348"); $fwrite (fd, " 349"); $fwrite (fd, " 350"); end 7'h22: begin ozoneae(foo[20:18], fd); $fwrite (fd," 351"); ozoneae(foo[17:15], fd); $fwrite (fd," 352"); $fwrite (fd, " 353"); $fwrite (fd, " 354"); end 7'h23: begin ozoneae(foo[20:18], fd); $fwrite (fd," 355"); ozoneae(foo[17:15], fd); $fwrite (fd," 356"); $fwrite (fd, " 357"); $fwrite (fd, " 358"); end 7'h24: begin ozoneae(foo[20:18], fd); $fwrite (fd," 359"); ozoneae(foo[17:15], fd); $fwrite (fd," 360"); $fwrite (fd, " 361"); $fwrite (fd, " 362"); end 7'h25: begin ozoneae(foo[20:18], fd); $fwrite (fd," 363"); ozoneae(foo[17:15], fd); $fwrite (fd," 364"); $fwrite (fd, " 365"); $fwrite (fd, " 366"); end 7'h26: begin ozoneae(foo[20:18], fd); $fwrite (fd," 367"); ozoneae(foo[17:15], fd); $fwrite (fd," 368"); $fwrite (fd, " 369"); $fwrite (fd, " 370"); end 7'h27: begin ozoneae(foo[20:18], fd); $fwrite (fd," 371"); ozoneae(foo[17:15], fd); $fwrite (fd," 372"); $fwrite (fd, " 373"); $fwrite (fd, " 374"); end 7'h28: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 375"); ozoneaee(foo[17:15], fd); $fwrite (fd," 376"); ozoneape(foo[20:18], fd); $fwrite (fd," 377"); ozoneape(foo[17:15], fd); $fwrite (fd," 378"); $fwrite (fd, " 379"); $fwrite (fd, " 380"); end 7'h29: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 381"); ozoneaee(foo[17:15], fd); $fwrite (fd," 382"); ozoneape(foo[20:18], fd); $fwrite (fd," 383"); ozoneape(foo[17:15], fd); $fwrite (fd," 384"); $fwrite (fd, " 385"); $fwrite (fd, " 386"); end 7'h2a: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 387"); ozoneaee(foo[17:15], fd); $fwrite (fd," 388"); ozoneape(foo[20:18], fd); $fwrite (fd," 389"); ozoneape(foo[17:15], fd); $fwrite (fd," 390"); $fwrite (fd, " 391"); $fwrite (fd, " 392"); end 7'h2b: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 393"); ozoneaee(foo[17:15], fd); $fwrite (fd," 394"); ozoneape(foo[20:18], fd); $fwrite (fd," 395"); ozoneape(foo[17:15], fd); $fwrite (fd," 396"); $fwrite (fd, " 397"); $fwrite (fd, " 398"); end 7'h2c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 399"); ozoneae(foo[17:15], fd); $fwrite (fd," 400"); $fwrite (fd, " 401"); $fwrite (fd, " 402"); end 7'h2d: begin ozoneae(foo[20:18], fd); $fwrite (fd," 403"); ozoneae(foo[17:15], fd); $fwrite (fd," 404"); $fwrite (fd, " 405"); $fwrite (fd, " 406"); end 7'h2e: begin ozoneae(foo[20:18], fd); $fwrite (fd," 407"); ozoneae(foo[17:15], fd); $fwrite (fd," 408"); $fwrite (fd, " 409"); $fwrite (fd, " 410"); end 7'h2f: begin ozoneae(foo[20:18], fd); $fwrite (fd," 411"); ozoneae(foo[17:15], fd); $fwrite (fd," 412"); $fwrite (fd, " 413"); $fwrite (fd, " 414"); end 7'h30: begin ozoneae(foo[20:18], fd); $fwrite (fd," 415"); ozoneae(foo[17:15], fd); $fwrite (fd," 416"); $fwrite (fd, " 417"); $fwrite (fd, " 418"); end 7'h31: begin ozoneae(foo[20:18], fd); $fwrite (fd," 419"); ozoneae(foo[17:15], fd); $fwrite (fd," 420"); $fwrite (fd, " 421"); $fwrite (fd, " 422"); end 7'h32: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 423"); ozoneaee(foo[17:15], fd); $fwrite (fd," 424"); ozoneape(foo[20:18], fd); $fwrite (fd," 425"); ozoneape(foo[17:15], fd); $fwrite (fd," 426"); $fwrite (fd, " 427"); $fwrite (fd, " 428"); end 7'h33: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 429"); ozoneaee(foo[17:15], fd); $fwrite (fd," 430"); ozoneape(foo[20:18], fd); $fwrite (fd," 431"); ozoneape(foo[17:15], fd); $fwrite (fd," 432"); $fwrite (fd, " 433"); $fwrite (fd, " 434"); end 7'h34: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 435"); ozoneaee(foo[17:15], fd); $fwrite (fd," 436"); ozoneape(foo[20:18], fd); $fwrite (fd," 437"); ozoneape(foo[17:15], fd); $fwrite (fd," 438"); $fwrite (fd, " 439"); $fwrite (fd, " 440"); end 7'h35: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 441"); ozoneaee(foo[17:15], fd); $fwrite (fd," 442"); ozoneape(foo[20:18], fd); $fwrite (fd," 443"); ozoneape(foo[17:15], fd); $fwrite (fd," 444"); $fwrite (fd, " 445"); $fwrite (fd, " 446"); end 7'h36: begin ozoneae(foo[20:18], fd); $fwrite (fd," 447"); ozoneae(foo[17:15], fd); $fwrite (fd," 448"); $fwrite (fd, " 449"); $fwrite (fd, " 450"); end 7'h37: begin ozoneae(foo[20:18], fd); $fwrite (fd," 451"); ozoneae(foo[17:15], fd); $fwrite (fd," 452"); $fwrite (fd, " 453"); $fwrite (fd, " 454"); end 7'h38: begin ozoneae(foo[20:18], fd); $fwrite (fd," 455"); ozoneae(foo[17:15], fd); $fwrite (fd," 456"); $fwrite (fd, " 457"); end 7'h39: begin ozoneae(foo[20:18], fd); $fwrite (fd," 458"); ozoneae(foo[17:15], fd); $fwrite (fd," 459"); $fwrite (fd, " 460"); end 7'h3a: begin ozoneae(foo[20:18], fd); $fwrite (fd," 461"); ozoneae(foo[17:15], fd); $fwrite (fd," 462"); $fwrite (fd, " 463"); end 7'h3b: begin ozoneae(foo[20:18], fd); $fwrite (fd," 464"); ozoneae(foo[17:15], fd); $fwrite (fd," 465"); $fwrite (fd, " 466"); end 7'h3c: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 467"); ozoneaee(foo[17:15], fd); $fwrite (fd," 468"); ozoneape(foo[20:18], fd); $fwrite (fd," 469"); ozoneape(foo[17:15], fd); $fwrite (fd," 470"); $fwrite (fd, " 471"); end 7'h3d: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 472"); ozoneaee(foo[17:15], fd); $fwrite (fd," 473"); ozoneape(foo[20:18], fd); $fwrite (fd," 474"); ozoneape(foo[17:15], fd); $fwrite (fd," 475"); $fwrite (fd, " 476"); end 7'h3e: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 477"); ozoneaee(foo[17:15], fd); $fwrite (fd," 478"); ozoneape(foo[20:18], fd); $fwrite (fd," 479"); ozoneape(foo[17:15], fd); $fwrite (fd," 480"); $fwrite (fd, " 481"); end 7'h3f: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 482"); ozoneaee(foo[17:15], fd); $fwrite (fd," 483"); ozoneape(foo[20:18], fd); $fwrite (fd," 484"); ozoneape(foo[17:15], fd); $fwrite (fd," 485"); $fwrite (fd, " 486"); end 7'h40: begin ozoneae(foo[20:18], fd); $fwrite (fd," 487"); ozoneae(foo[17:15], fd); $fwrite (fd," 488"); $fwrite (fd, " 489"); $fwrite (fd, " 490"); end 7'h41: begin $fwrite (fd, " 491"); $fwrite (fd, " 492"); end 7'h42: begin $fwrite (fd, " 493"); $fwrite (fd, " 494"); end 7'h43: begin $fwrite (fd, " 495"); $fwrite (fd, " 496"); end 7'h44: begin $fwrite (fd, " 497"); $fwrite (fd, " 498"); end 7'h45: $fwrite (fd, " 499"); 7'h46: begin ozoneae(foo[20:18], fd); $fwrite (fd," 500"); $fwrite (fd, " 501"); $fwrite (fd, " 502"); end 7'h47: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 503"); ozoneae(foo[17:15], fd); $fwrite (fd," 504"); ozoneape(foo[20:18], fd); $fwrite (fd," 505"); ozoneape(foo[20:18], fd); $fwrite (fd," 506"); $fwrite (fd, " 507"); $fwrite (fd, " 508"); end 7'h48: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 509"); ozoneape(foo[20:18], fd); $fwrite (fd," 510"); ozoneape(foo[20:18], fd); $fwrite (fd," 511"); ozoneaee(foo[17:15], fd); $fwrite (fd," 512"); ozoneape(foo[17:15], fd); $fwrite (fd," 513"); end 7'h49: begin ozoneae(foo[20:18], fd); $fwrite (fd," 514"); ozoneaee(foo[17:15], fd); $fwrite (fd," 515"); ozoneape(foo[17:15], fd); $fwrite (fd," 516"); end 7'h4a: $fwrite (fd," 517"); 7'h4b: $fwrite (fd, " 518"); 7'h4c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 519"); $fwrite (fd, " 520"); $fwrite (fd, " 521"); end 7'h4d: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 522"); ozoneae(foo[17:15], fd); $fwrite (fd," 523"); ozoneape(foo[20:18], fd); $fwrite (fd," 524"); ozoneape(foo[20:18], fd); $fwrite (fd," 525"); $fwrite (fd, " 526"); $fwrite (fd, " 527"); end 7'h4e: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 528"); ozoneae(foo[17:15], fd); $fwrite (fd," 529"); ozoneape(foo[20:18], fd); $fwrite (fd," 530"); ozoneape(foo[20:18], fd); $fwrite (fd," 531"); end 7'h4f: begin ozoneae(foo[20:18], fd); $fwrite (fd," 532"); end 7'h50: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 533"); ozoneae(foo[17:15], fd); $fwrite (fd," 534"); ozoneaee(foo[20:18], fd); $fwrite (fd," 535"); ozoneae(foo[17:15], fd); $fwrite (fd," 536"); ozoneape(foo[20:18], fd); $fwrite (fd," 537"); ozoneae(foo[17:15], fd); $fwrite (fd," 538"); ozoneape(foo[20:18], fd); $fwrite (fd," 539"); ozoneae(foo[17:15], fd); $fwrite (fd," 540"); end 7'h51: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 541"); ozoneape(foo[20:18], fd); $fwrite (fd," 542"); ozoneaee(foo[20:18], fd); $fwrite (fd," 543"); ozoneape(foo[20:18], fd); $fwrite (fd," 544"); ozoneae(foo[17:15], fd); $fwrite (fd," 545"); end 7'h52: $fwrite (fd, " 546"); 7'h53: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 547"); end 7'h54: begin ozoneae(foo[20:18], fd); $fwrite (fd," 548"); ozoneae(foo[17:15], fd); $fwrite (fd," 549"); end 7'h55: begin ozoneae(foo[20:18], fd); $fwrite (fd," 550"); ozoneae(foo[17:15], fd); $fwrite (fd," 551"); end 7'h56: begin ozoneae(foo[20:18], fd); $fwrite (fd," 552"); ozoneae(foo[17:15], fd); $fwrite (fd," 553"); $fwrite (fd, " 554"); end 7'h57: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 555"); ozoneae(foo[17:15], fd); $fwrite (fd," 556"); ozoneape(foo[20:18], fd); $fwrite (fd," 557"); ozoneape(foo[20:18], fd); $fwrite (fd," 558"); end 7'h58: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 559"); end 7'h59: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 560"); ozoneae(foo[17:15], fd); $fwrite (fd," 561"); ozoneape(foo[20:18], fd); $fwrite (fd," 562"); ozoneape(foo[20:18], fd); $fwrite (fd," 563"); end 7'h5a: begin ozoneae(foo[20:18], fd); $fwrite (fd," 564"); ozoneae(foo[17:15], fd); $fwrite (fd, " 565"); end 7'h5b: begin ozoneae(foo[20:18], fd); $fwrite (fd," 566"); ozoneae(foo[17:15], fd); $fwrite (fd, " 567"); end 7'h5c: begin $fwrite (fd," 568"); ozoneape(foo[17:15], fd); $fwrite (fd," 569"); $fwrite (fd," 570"); ozoneape(foo[17:15], fd); $fwrite (fd," 571"); ozoneae(foo[20:18], fd); $fwrite (fd," 572"); ozoneaee(foo[17:15], fd); $fwrite (fd, " 573"); end 7'h5d: begin $fwrite (fd," 574"); ozoneape(foo[17:15], fd); $fwrite (fd," 575"); $fwrite (fd," 576"); ozoneape(foo[17:15], fd); $fwrite (fd," 577"); ozoneae(foo[20:18], fd); $fwrite (fd," 578"); ozoneaee(foo[17:15], fd); $fwrite (fd, " 579"); end 7'h5e: begin ozoneae(foo[20:18], fd); $fwrite (fd," 580"); ozoneae(foo[17:15], fd); $fwrite (fd, " 581"); end 7'h5f: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 582"); ozoneae(foo[17:15], fd); $fwrite (fd," 583"); ozoneaee(foo[20:18], fd); $fwrite (fd," 584"); ozoneae(foo[17:15], fd); $fwrite (fd," 585"); ozoneape(foo[20:18], fd); $fwrite (fd," 586"); ozoneae(foo[17:15], fd); $fwrite (fd," 587"); ozoneape(foo[20:18], fd); $fwrite (fd," 588"); ozoneae(foo[17:15], fd); $fwrite (fd," 589"); end 7'h60: begin ozoneae(foo[20:18], fd); $fwrite (fd," 590"); ozoneae(foo[17:15], fd); $fwrite (fd," 591"); end 7'h61: begin ozoneae(foo[20:18], fd); $fwrite (fd," 592"); ozoneae(foo[17:15], fd); $fwrite (fd," 593"); end 7'h62: begin ozoneae(foo[20:18], fd); $fwrite (fd," 594"); ozoneae(foo[17:15], fd); $fwrite (fd," 595"); end 7'h63: begin ozoneae(foo[20:18], fd); $fwrite (fd," 596"); ozoneae(foo[17:15], fd); $fwrite (fd," 597"); end 7'h64: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 598"); ozoneaee(foo[17:15], fd); $fwrite (fd," 599"); ozoneape(foo[20:18], fd); $fwrite (fd," 600"); ozoneape(foo[17:15], fd); $fwrite (fd," 601"); end 7'h65: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 602"); ozoneaee(foo[17:15], fd); $fwrite (fd," 603"); ozoneape(foo[20:18], fd); $fwrite (fd," 604"); ozoneape(foo[17:15], fd); $fwrite (fd," 605"); end 7'h66: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 606"); ozoneaee(foo[17:15], fd); $fwrite (fd," 607"); ozoneape(foo[20:18], fd); $fwrite (fd," 608"); ozoneape(foo[17:15], fd); $fwrite (fd," 609"); end 7'h67: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 610"); ozoneaee(foo[17:15], fd); $fwrite (fd," 611"); ozoneape(foo[20:18], fd); $fwrite (fd," 612"); ozoneape(foo[17:15], fd); $fwrite (fd," 613"); end 7'h68: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 614"); ozoneaee(foo[17:15], fd); $fwrite (fd," 615"); ozoneaee(foo[20:18], fd); $fwrite (fd," 616"); ozoneape(foo[20:18], fd); $fwrite (fd," 617"); ozoneape(foo[20:18], fd); $fwrite (fd," 618"); ozoneape(foo[17:15], fd); end 7'h69: begin ozoneae(foo[20:18], fd); $fwrite (fd," 619"); ozoneae(foo[17:15], fd); $fwrite (fd," 620"); ozoneae(foo[20:18], fd); $fwrite (fd," 621"); end 7'h6a: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 622"); ozoneae(foo[17:15], fd); $fwrite (fd," 623"); ozoneaee(foo[20:18], fd); $fwrite (fd," 624"); ozoneape(foo[20:18], fd); $fwrite (fd," 625"); ozoneaee(foo[20:18], fd); $fwrite (fd," 626"); ozoneae(foo[17:15], fd); end 7'h6b: begin ozoneae(foo[20:18], fd); $fwrite (fd," 627"); ozoneae(foo[17:15], fd); $fwrite (fd," 628"); ozoneae(foo[20:18], fd); $fwrite (fd," 629"); end 7'h6c: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 630"); ozoneae(foo[17:15], fd); $fwrite (fd," 631"); ozoneaee(foo[20:18], fd); $fwrite (fd," 632"); ozoneape(foo[20:18], fd); $fwrite (fd," 633"); ozoneaee(foo[20:18], fd); $fwrite (fd," 634"); ozoneae(foo[17:15], fd); end 7'h6d: begin ozoneae(foo[20:18], fd); $fwrite (fd," 635"); ozoneae(foo[17:15], fd); $fwrite (fd," 636"); ozoneae(foo[20:18], fd); $fwrite (fd," 637"); end 7'h6e: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 638"); ozoneaee(foo[17:15], fd); $fwrite (fd," 639"); ozoneape(foo[20:18], fd); $fwrite (fd," 640"); ozoneape(foo[17:15], fd); $fwrite (fd," 641"); end 7'h6f: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 642"); ozoneaee(foo[17:15], fd); $fwrite (fd," 643"); ozoneape(foo[20:18], fd); $fwrite (fd," 644"); ozoneape(foo[17:15], fd); $fwrite (fd," 645"); end 7'h70: begin ozoneae(foo[20:18], fd); $fwrite (fd," 646"); ozoneae(foo[20:18], fd); $fwrite (fd," 647"); ozoneae(foo[17:15], fd); $fwrite (fd," 648"); ozoneae(foo[17:15], fd); $fwrite (fd, " 649"); end 7'h71: begin ozoneae(foo[20:18], fd); $fwrite (fd," 650"); ozoneae(foo[17:15], fd); $fwrite (fd, " 651"); end 7'h72: begin ozoneae(foo[20:18], fd); $fwrite (fd," 652"); ozoneae(foo[17:15], fd); $fwrite (fd, " 653"); end 7'h73: begin ozoneae(foo[20:18], fd); $fwrite (fd," 654"); ozoneae(foo[20:18], fd); $fwrite (fd," 655"); ozoneae(foo[17:15], fd); end 7'h74: begin ozoneae(foo[20:18], fd); $fwrite (fd," 656"); ozoneae(foo[20:18], fd); $fwrite (fd," 657"); ozoneae(foo[17:15], fd); end 7'h75: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 658"); ozoneaee(foo[17:15], fd); $fwrite (fd," 659"); ozoneape(foo[20:18], fd); $fwrite (fd," 660"); ozoneape(foo[17:15], fd); $fwrite (fd," 661"); $fwrite (fd, " 662"); $fwrite (fd, " 663"); end 7'h76: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 664"); ozoneaee(foo[17:15], fd); $fwrite (fd," 665"); ozoneaee(foo[20:18], fd); $fwrite (fd," 666"); ozoneape(foo[20:18], fd); $fwrite (fd," 667"); ozoneape(foo[17:15], fd); $fwrite (fd," 668"); ozoneape(foo[20:18], fd); $fwrite (fd," 669"); end 7'h77: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 670"); ozoneaee(foo[17:15], fd); $fwrite (fd," 671"); ozoneaee(foo[17:15], fd); $fwrite (fd," 672"); ozoneape(foo[20:18], fd); $fwrite (fd," 673"); ozoneape(foo[17:15], fd); $fwrite (fd," 674"); ozoneape(foo[17:15], fd); $fwrite (fd," 675"); end 7'h78, 7'h79, 7'h7a, 7'h7b, 7'h7c, 7'h7d, 7'h7e, 7'h7f: $fwrite (fd," 676"); endcase end endtask task ozonef2; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[24:21]) 4'h0 : case (foo[26:25]) 2'b00 : $fwrite (fd," 677"); 2'b01 : $fwrite (fd," 678"); 2'b10 : $fwrite (fd," 679"); 2'b11 : $fwrite (fd," 680"); endcase 4'h1 : case (foo[26:25]) 2'b00 : $fwrite (fd," 681"); 2'b01 : $fwrite (fd," 682"); 2'b10 : $fwrite (fd," 683"); 2'b11 : $fwrite (fd," 684"); endcase 4'h2 : case (foo[26:25]) 2'b00 : $fwrite (fd," 685"); 2'b01 : $fwrite (fd," 686"); 2'b10 : $fwrite (fd," 687"); 2'b11 : $fwrite (fd," 688"); endcase 4'h3 : case (foo[26:25]) 2'b00 : $fwrite (fd," 689"); 2'b01 : $fwrite (fd," 690"); 2'b10 : $fwrite (fd," 691"); 2'b11 : $fwrite (fd," 692"); endcase 4'h4 : case (foo[26:25]) 2'b00 : $fwrite (fd," 693"); 2'b01 : $fwrite (fd," 694"); 2'b10 : $fwrite (fd," 695"); 2'b11 : $fwrite (fd," 696"); endcase 4'h5 : case (foo[26:25]) 2'b00 : $fwrite (fd," 697"); 2'b01 : $fwrite (fd," 698"); 2'b10 : $fwrite (fd," 699"); 2'b11 : $fwrite (fd," 700"); endcase 4'h6 : case (foo[26:25]) 2'b00 : $fwrite (fd," 701"); 2'b01 : $fwrite (fd," 702"); 2'b10 : $fwrite (fd," 703"); 2'b11 : $fwrite (fd," 704"); endcase 4'h7 : case (foo[26:25]) 2'b00 : $fwrite (fd," 705"); 2'b01 : $fwrite (fd," 706"); 2'b10 : $fwrite (fd," 707"); 2'b11 : $fwrite (fd," 708"); endcase 4'h8 : if (foo[26]) $fwrite (fd," 709"); else $fwrite (fd," 710"); 4'h9 : case (foo[26:25]) 2'b00 : $fwrite (fd," 711"); 2'b01 : $fwrite (fd," 712"); 2'b10 : $fwrite (fd," 713"); 2'b11 : $fwrite (fd," 714"); endcase 4'ha : case (foo[26:25]) 2'b00 : $fwrite (fd," 715"); 2'b01 : $fwrite (fd," 716"); 2'b10 : $fwrite (fd," 717"); 2'b11 : $fwrite (fd," 718"); endcase 4'hb : case (foo[26:25]) 2'b00 : $fwrite (fd," 719"); 2'b01 : $fwrite (fd," 720"); 2'b10 : $fwrite (fd," 721"); 2'b11 : $fwrite (fd," 722"); endcase 4'hc : if (foo[26]) $fwrite (fd," 723"); else $fwrite (fd," 724"); 4'hd : case (foo[26:25]) 2'b00 : $fwrite (fd," 725"); 2'b01 : $fwrite (fd," 726"); 2'b10 : $fwrite (fd," 727"); 2'b11 : $fwrite (fd," 728"); endcase 4'he : case (foo[26:25]) 2'b00 : $fwrite (fd," 729"); 2'b01 : $fwrite (fd," 730"); 2'b10 : $fwrite (fd," 731"); 2'b11 : $fwrite (fd," 732"); endcase 4'hf : case (foo[26:25]) 2'b00 : $fwrite (fd," 733"); 2'b01 : $fwrite (fd," 734"); 2'b10 : $fwrite (fd," 735"); 2'b11 : $fwrite (fd," 736"); endcase endcase end endtask task ozonef2e; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin casez (foo[25:21]) 5'h00 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 737"); ozoneae(foo[17:15], fd); $fwrite (fd," 738"); end 5'h01 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 739"); ozoneae(foo[17:15], fd); $fwrite (fd," 740"); end 5'h02 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 741"); ozoneae(foo[17:15], fd); $fwrite (fd," 742"); end 5'h03 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 743"); ozoneae(foo[17:15], fd); $fwrite (fd," 744"); end 5'h04 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 745"); ozoneae(foo[17:15], fd); $fwrite (fd," 746"); end 5'h05 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 747"); ozoneae(foo[17:15], fd); $fwrite (fd," 748"); end 5'h06 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 749"); ozoneae(foo[17:15], fd); $fwrite (fd," 750"); end 5'h07 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 751"); ozoneae(foo[17:15], fd); $fwrite (fd," 752"); end 5'h08 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 753"); if (foo[ 6]) $fwrite (fd," 754"); else $fwrite (fd," 755"); end 5'h09 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 756"); ozoneae(foo[17:15], fd); $fwrite (fd," 757"); end 5'h0a : begin ozoneae(foo[20:18], fd); $fwrite (fd," 758"); ozoneae(foo[17:15], fd); end 5'h0b : begin ozoneae(foo[20:18], fd); $fwrite (fd," 759"); ozoneae(foo[17:15], fd); $fwrite (fd," 760"); end 5'h0c : begin ozoneae(foo[20:18], fd); $fwrite (fd," 761"); end 5'h0d : begin ozoneae(foo[20:18], fd); $fwrite (fd," 762"); ozoneae(foo[17:15], fd); $fwrite (fd," 763"); end 5'h0e : begin ozoneae(foo[20:18], fd); $fwrite (fd," 764"); ozoneae(foo[17:15], fd); end 5'h0f : begin ozoneae(foo[20:18], fd); $fwrite (fd," 765"); ozoneae(foo[17:15], fd); end 5'h10 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 766"); ozoneae(foo[17:15], fd); $fwrite (fd," 767"); end 5'h11 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 768"); ozoneae(foo[17:15], fd); $fwrite (fd," 769"); end 5'h18 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 770"); if (foo[ 6]) $fwrite (fd," 771"); else $fwrite (fd," 772"); end 5'h1a : begin ozoneae(foo[20:18], fd); $fwrite (fd," 773"); ozoneae(foo[17:15], fd); $fwrite (fd," 774"); end 5'h1b : begin ozoneae(foo[20:18], fd); $fwrite (fd," 775"); ozoneae(foo[17:15], fd); $fwrite (fd," 776"); if (foo[ 6]) $fwrite (fd," 777"); else $fwrite (fd," 778"); $fwrite (fd," 779"); end 5'h1c : begin ozoneae(foo[20:18], fd); $fwrite (fd," 780"); end 5'h1d : begin ozoneae(foo[20:18], fd); $fwrite (fd," 781"); if (foo[ 6]) $fwrite (fd," 782"); else $fwrite (fd," 783"); $fwrite (fd," 784"); end 5'h1e : begin ozoneae(foo[20:18], fd); $fwrite (fd," 785"); if (foo[ 6]) $fwrite (fd," 786"); else $fwrite (fd," 787"); $fwrite (fd," 788"); end 5'h1f : begin ozoneae(foo[20:18], fd); $fwrite (fd," 789"); ozoneae(foo[17:15], fd); $fwrite (fd," 790"); if (foo[ 6]) $fwrite (fd," 791"); else $fwrite (fd," 792"); $fwrite (fd," 793"); end default : $fwrite (fd," 794"); endcase end endtask task ozonef3e; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[25:21]) 5'h00, 5'h01, 5'h02: begin ozoneae(foo[20:18], fd); case (foo[22:21]) 2'h0: $fwrite (fd," 795"); 2'h1: $fwrite (fd," 796"); 2'h2: $fwrite (fd," 797"); endcase ozoneae(foo[17:15], fd); $fwrite (fd," 798"); if (foo[ 9]) ozoneae(foo[ 8: 6], fd); else ozonef3e_te(foo[ 8: 6], fd); $fwrite (fd," 799"); end 5'h08, 5'h09, 5'h0d, 5'h0e, 5'h0f: begin ozoneae(foo[20:18], fd); $fwrite (fd," 800"); ozoneae(foo[17:15], fd); case (foo[23:21]) 3'h0: $fwrite (fd," 801"); 3'h1: $fwrite (fd," 802"); 3'h5: $fwrite (fd," 803"); 3'h6: $fwrite (fd," 804"); 3'h7: $fwrite (fd," 805"); endcase if (foo[ 9]) ozoneae(foo[ 8: 6], fd); else ozonef3e_te(foo[ 8: 6], fd); end 5'h0a, 5'h0b: begin ozoneae(foo[17:15], fd); if (foo[21]) $fwrite (fd," 806"); else $fwrite (fd," 807"); if (foo[ 9]) ozoneae(foo[ 8: 6], fd); else ozonef3e_te(foo[ 8: 6], fd); end 5'h0c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 808"); if (foo[ 9]) ozoneae(foo[ 8: 6], fd); else ozonef3e_te(foo[ 8: 6], fd); $fwrite (fd," 809"); ozoneae(foo[17:15], fd); end 5'h10, 5'h11, 5'h12, 5'h13: begin ozoneae(foo[20:18], fd); $fwrite (fd," 810"); ozoneae(foo[17:15], fd); case (foo[22:21]) 2'h0, 2'h2: $fwrite (fd," 811"); 2'h1, 2'h3: $fwrite (fd," 812"); endcase ozoneae(foo[ 8: 6], fd); $fwrite (fd," 813"); ozoneae((foo[20:18]+1), fd); $fwrite (fd," 814"); ozoneae((foo[17:15]+1), fd); case (foo[22:21]) 2'h0, 2'h3: $fwrite (fd," 815"); 2'h1, 2'h2: $fwrite (fd," 816"); endcase ozoneae((foo[ 8: 6]+1), fd); end 5'h18: begin ozoneae(foo[20:18], fd); $fwrite (fd," 817"); ozoneae(foo[17:15], fd); $fwrite (fd," 818"); ozoneae(foo[ 8: 6], fd); $fwrite (fd," 819"); ozoneae(foo[20:18], fd); $fwrite (fd," 820"); ozoneae(foo[17:15], fd); $fwrite (fd," 821"); ozoneae(foo[ 8: 6], fd); end default : $fwrite (fd," 822"); endcase end endtask task ozonef3e_te; input [ 2:0] te; input [`FD_BITS] fd; // verilator no_inline_task begin case (te) 3'b100 : $fwrite (fd, " 823"); 3'b101 : $fwrite (fd, " 824"); 3'b110 : $fwrite (fd, " 825"); default: $fwrite (fd, " 826"); endcase end endtask task ozonearm; input [ 2:0] ate; input [`FD_BITS] fd; // verilator no_inline_task begin case (ate) 3'b000 : $fwrite (fd, " 827"); 3'b001 : $fwrite (fd, " 828"); 3'b010 : $fwrite (fd, " 829"); 3'b011 : $fwrite (fd, " 830"); 3'b100 : $fwrite (fd, " 831"); 3'b101 : $fwrite (fd, " 832"); 3'b110 : $fwrite (fd, " 833"); 3'b111 : $fwrite (fd, " 834"); endcase end endtask task ozonebmuop; input [ 4:0] f4; input [`FD_BITS] fd; // verilator no_inline_task begin case (f4[ 4:0]) 5'h00, 5'h04 : $fwrite (fd, " 835"); 5'h01, 5'h05 : $fwrite (fd, " 836"); 5'h02, 5'h06 : $fwrite (fd, " 837"); 5'h03, 5'h07 : $fwrite (fd, " 838"); 5'h08, 5'h18 : $fwrite (fd, " 839"); 5'h09, 5'h19 : $fwrite (fd, " 840"); 5'h0a, 5'h1a : $fwrite (fd, " 841"); 5'h0b : $fwrite (fd, " 842"); 5'h1b : $fwrite (fd, " 843"); 5'h0c, 5'h1c : $fwrite (fd, " 844"); 5'h0d, 5'h1d : $fwrite (fd, " 845"); 5'h1e : $fwrite (fd, " 846"); endcase end endtask task ozonef3; input [ 31:0] foo; input [`FD_BITS] fd; reg nacho; // verilator no_inline_task begin : f3_body nacho = 1'b0; case (foo[24:21]) 4'h0: case (foo[26:25]) 2'b00 : $fwrite (fd, " 847"); 2'b01 : $fwrite (fd, " 848"); 2'b10 : $fwrite (fd, " 849"); 2'b11 : $fwrite (fd, " 850"); endcase 4'h1: case (foo[26:25]) 2'b00 : $fwrite (fd, " 851"); 2'b01 : $fwrite (fd, " 852"); 2'b10 : $fwrite (fd, " 853"); 2'b11 : $fwrite (fd, " 854"); endcase 4'h2: case (foo[26:25]) 2'b00 : $fwrite (fd, " 855"); 2'b01 : $fwrite (fd, " 856"); 2'b10 : $fwrite (fd, " 857"); 2'b11 : $fwrite (fd, " 858"); endcase 4'h8, 4'h9, 4'hd, 4'he, 4'hf : case (foo[26:25]) 2'b00 : $fwrite (fd, " 859"); 2'b01 : $fwrite (fd, " 860"); 2'b10 : $fwrite (fd, " 861"); 2'b11 : $fwrite (fd, " 862"); endcase 4'ha, 4'hb : if (foo[25]) $fwrite (fd, " 863"); else $fwrite (fd, " 864"); 4'hc : if (foo[26]) $fwrite (fd, " 865"); else $fwrite (fd, " 866"); default : begin $fwrite (fd, " 867"); nacho = 1'b1; end endcase if (~nacho) begin case (foo[24:21]) 4'h8 : $fwrite (fd, " 868"); 4'h9 : $fwrite (fd, " 869"); 4'ha, 4'he : $fwrite (fd, " 870"); 4'hb, 4'hf : $fwrite (fd, " 871"); 4'hd : $fwrite (fd, " 872"); endcase if (foo[20]) case (foo[18:16]) 3'b000 : $fwrite (fd, " 873"); 3'b100 : $fwrite (fd, " 874"); default: $fwrite (fd, " 875"); endcase else ozoneae(foo[18:16], fd); if (foo[24:21] === 4'hc) if (foo[25]) $fwrite (fd, " 876"); else $fwrite (fd, " 877"); case (foo[24:21]) 4'h0, 4'h1, 4'h2: $fwrite (fd, " 878"); endcase end end endtask task ozonerx; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[19:18]) 2'h0 : $fwrite (fd, " 879"); 2'h1 : $fwrite (fd, " 880"); 2'h2 : $fwrite (fd, " 881"); 2'h3 : $fwrite (fd, " 882"); endcase case (foo[17:16]) 2'h1 : $fwrite (fd, " 883"); 2'h2 : $fwrite (fd, " 884"); 2'h3 : $fwrite (fd, " 885"); endcase end endtask task ozonerme; input [ 2:0] rme; input [`FD_BITS] fd; // verilator no_inline_task begin case (rme) 3'h0 : $fwrite (fd, " 886"); 3'h1 : $fwrite (fd, " 887"); 3'h2 : $fwrite (fd, " 888"); 3'h3 : $fwrite (fd, " 889"); 3'h4 : $fwrite (fd, " 890"); 3'h5 : $fwrite (fd, " 891"); 3'h6 : $fwrite (fd, " 892"); 3'h7 : $fwrite (fd, " 893"); endcase end endtask task ozoneye; input [5:0] ye; input l; input [`FD_BITS] fd; // verilator no_inline_task begin $fwrite (fd, " 894"); ozonerme(ye[5:3], fd); case ({ye[ 2:0], l}) 4'h2, 4'ha: $fwrite (fd, " 895"); 4'h4, 4'hb: $fwrite (fd, " 896"); 4'h6, 4'he: $fwrite (fd, " 897"); 4'h8, 4'hc: $fwrite (fd, " 898"); endcase end endtask task ozonef1e_ye; input [5:0] ye; input l; input [`FD_BITS] fd; // verilator no_inline_task begin $fwrite (fd, " 899"); ozonerme(ye[5:3], fd); ozonef1e_inc_dec(ye[5:0], l , fd); end endtask task ozonef1e_h; input [ 2:0] e; input [`FD_BITS] fd; // verilator no_inline_task begin if (e[ 2:0] <= 3'h4) $fwrite (fd, " 900"); end endtask task ozonef1e_inc_dec; input [5:0] ye; input l; input [`FD_BITS] fd; // verilator no_inline_task begin case ({ye[ 2:0], l}) 4'h2, 4'h3, 4'ha: $fwrite (fd, " 901"); 4'h4, 4'h5, 4'hb: $fwrite (fd, " 902"); 4'h6, 4'h7, 4'he: $fwrite (fd, " 903"); 4'h8, 4'h9, 4'hc: $fwrite (fd, " 904"); 4'hf: $fwrite (fd, " 905"); endcase end endtask task ozonef1e_hl; input [ 2:0] e; input l; input [`FD_BITS] fd; // verilator no_inline_task begin case ({e[ 2:0], l}) 4'h0, 4'h2, 4'h4, 4'h6, 4'h8: $fwrite (fd, " 906"); 4'h1, 4'h3, 4'h5, 4'h7, 4'h9: $fwrite (fd, " 907"); endcase end endtask task ozonexe; input [ 3:0] xe; input [`FD_BITS] fd; // verilator no_inline_task begin case (xe[3]) 1'b0 : $fwrite (fd, " 908"); 1'b1 : $fwrite (fd, " 909"); endcase case (xe[ 2:0]) 3'h1, 3'h5: $fwrite (fd, " 910"); 3'h2, 3'h6: $fwrite (fd, " 911"); 3'h3, 3'h7: $fwrite (fd, " 912"); 3'h4: $fwrite (fd, " 913"); endcase end endtask task ozonerp; input [ 2:0] rp; input [`FD_BITS] fd; // verilator no_inline_task begin case (rp) 3'h0 : $fwrite (fd, " 914"); 3'h1 : $fwrite (fd, " 915"); 3'h2 : $fwrite (fd, " 916"); 3'h3 : $fwrite (fd, " 917"); 3'h4 : $fwrite (fd, " 918"); 3'h5 : $fwrite (fd, " 919"); 3'h6 : $fwrite (fd, " 920"); 3'h7 : $fwrite (fd, " 921"); endcase end endtask task ozonery; input [ 3:0] ry; input [`FD_BITS] fd; // verilator no_inline_task begin case (ry) 4'h0 : $fwrite (fd, " 922"); 4'h1 : $fwrite (fd, " 923"); 4'h2 : $fwrite (fd, " 924"); 4'h3 : $fwrite (fd, " 925"); 4'h4 : $fwrite (fd, " 926"); 4'h5 : $fwrite (fd, " 927"); 4'h6 : $fwrite (fd, " 928"); 4'h7 : $fwrite (fd, " 929"); 4'h8 : $fwrite (fd, " 930"); 4'h9 : $fwrite (fd, " 931"); 4'ha : $fwrite (fd, " 932"); 4'hb : $fwrite (fd, " 933"); 4'hc : $fwrite (fd, " 934"); 4'hd : $fwrite (fd, " 935"); 4'he : $fwrite (fd, " 936"); 4'hf : $fwrite (fd, " 937"); endcase end endtask task ozonearx; input [ 15:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[1:0]) 2'h0 : $fwrite (fd, " 938"); 2'h1 : $fwrite (fd, " 939"); 2'h2 : $fwrite (fd, " 940"); 2'h3 : $fwrite (fd, " 941"); endcase end endtask task ozonef3f4imop; input [ 4:0] f3f4iml; input [`FD_BITS] fd; // verilator no_inline_task begin casez (f3f4iml) 5'b000??: $fwrite (fd, " 942"); 5'b001??: $fwrite (fd, " 943"); 5'b?10??: $fwrite (fd, " 944"); 5'b0110?: $fwrite (fd, " 945"); 5'b01110: $fwrite (fd, " 946"); 5'b01111: $fwrite (fd, " 947"); 5'b10???: $fwrite (fd, " 948"); 5'b11100: $fwrite (fd, " 949"); 5'b11101: $fwrite (fd, " 950"); 5'b11110: $fwrite (fd, " 951"); 5'b11111: $fwrite (fd, " 952"); endcase end endtask task ozonecon; input [ 4:0] con; input [`FD_BITS] fd; // verilator no_inline_task begin case (con) 5'h00 : $fwrite (fd, " 953"); 5'h01 : $fwrite (fd, " 954"); 5'h02 : $fwrite (fd, " 955"); 5'h03 : $fwrite (fd, " 956"); 5'h04 : $fwrite (fd, " 957"); 5'h05 : $fwrite (fd, " 958"); 5'h06 : $fwrite (fd, " 959"); 5'h07 : $fwrite (fd, " 960"); 5'h08 : $fwrite (fd, " 961"); 5'h09 : $fwrite (fd, " 962"); 5'h0a : $fwrite (fd, " 963"); 5'h0b : $fwrite (fd, " 964"); 5'h0c : $fwrite (fd, " 965"); 5'h0d : $fwrite (fd, " 966"); 5'h0e : $fwrite (fd, " 967"); 5'h0f : $fwrite (fd, " 968"); 5'h10 : $fwrite (fd, " 969"); 5'h11 : $fwrite (fd, " 970"); 5'h12 : $fwrite (fd, " 971"); 5'h13 : $fwrite (fd, " 972"); 5'h14 : $fwrite (fd, " 973"); 5'h15 : $fwrite (fd, " 974"); 5'h16 : $fwrite (fd, " 975"); 5'h17 : $fwrite (fd, " 976"); 5'h18 : $fwrite (fd, " 977"); 5'h19 : $fwrite (fd, " 978"); 5'h1a : $fwrite (fd, " 979"); 5'h1b : $fwrite (fd, " 980"); 5'h1c : $fwrite (fd, " 981"); 5'h1d : $fwrite (fd, " 982"); 5'h1e : $fwrite (fd, " 983"); 5'h1f : $fwrite (fd, " 984"); endcase end endtask task ozonedr; input [ 15:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[ 9: 6]) 4'h0 : $fwrite (fd, " 985"); 4'h1 : $fwrite (fd, " 986"); 4'h2 : $fwrite (fd, " 987"); 4'h3 : $fwrite (fd, " 988"); 4'h4 : $fwrite (fd, " 989"); 4'h5 : $fwrite (fd, " 990"); 4'h6 : $fwrite (fd, " 991"); 4'h7 : $fwrite (fd, " 992"); 4'h8 : $fwrite (fd, " 993"); 4'h9 : $fwrite (fd, " 994"); 4'ha : $fwrite (fd, " 995"); 4'hb : $fwrite (fd, " 996"); 4'hc : $fwrite (fd, " 997"); 4'hd : $fwrite (fd, " 998"); 4'he : $fwrite (fd, " 999"); 4'hf : $fwrite (fd, " 1000"); endcase end endtask task ozoneshift; input [ 15:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[ 4: 3]) 2'h0 : $fwrite (fd, " 1001"); 2'h1 : $fwrite (fd, " 1002"); 2'h2 : $fwrite (fd, " 1003"); 2'h3 : $fwrite (fd, " 1004"); endcase end endtask task ozoneacc; input foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo) 2'h0 : $fwrite (fd, " 1005"); 2'h1 : $fwrite (fd, " 1006"); endcase end endtask task ozonehl; input foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo) 2'h0 : $fwrite (fd, " 1007"); 2'h1 : $fwrite (fd, " 1008"); endcase end endtask task dude; input [`FD_BITS] fd; // verilator no_inline_task $fwrite(fd," dude"); endtask task big_case; input [ `FD_BITS] fd; input [ 31:0] foo; // verilator no_inline_task begin $fwrite(fd," 1009"); if (&foo === 1'bx) $fwrite(fd, " 1010"); else casez ( {foo[31:26], foo[19:15], foo[5:0]} ) 17'b00_111?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1011"); ozoneacc(~foo[26], fd); ozonehl(foo[20], fd); $fwrite (fd, " 1012"); ozonerx(foo, fd); dude(fd); $fwrite (fd, " 1013"); end 17'b01_001?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1014"); ozonerx(foo, fd); $fwrite (fd, " 1015"); $fwrite (fd, " 1016:%x", foo[20]); ozonehl(foo[20], fd); dude(fd); $fwrite (fd, " 1017"); end 17'b10_100?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1018"); ozonerx(foo, fd); $fwrite (fd, " 1019"); $fwrite (fd, " 1020"); ozonehl(foo[20], fd); dude(fd); $fwrite (fd, " 1021"); end 17'b10_101?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1022"); if (foo[20]) begin $fwrite (fd, " 1023"); ozoneacc(foo[18], fd); $fwrite (fd, " 1024"); $fwrite (fd, " 1025"); if (foo[19]) $fwrite (fd, " 1026"); else $fwrite (fd, " 1027"); end else ozonerx(foo, fd); dude(fd); $fwrite (fd, " 1028"); end 17'b10_110?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1029"); $fwrite (fd, " 1030"); ozonehl(foo[20], fd); $fwrite (fd, " 1031"); ozonerx(foo, fd); dude(fd); $fwrite (fd, " 1032"); end 17'b10_111?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1033"); $fwrite (fd, " 1034"); ozonehl(foo[20], fd); $fwrite (fd, " 1035"); ozonerx(foo, fd); dude(fd); $fwrite (fd, " 1036"); end 17'b11_001?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1037"); ozonerx(foo, fd); $fwrite (fd, " 1038"); $fwrite (fd, " 1039"); ozonehl(foo[20], fd); dude(fd); $fwrite (fd, " 1040"); end 17'b11_111?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1041"); $fwrite (fd, " 1042"); ozonerx(foo, fd); $fwrite (fd, " 1043"); if (foo[20]) $fwrite (fd, " 1044"); else $fwrite (fd, " 1045"); dude(fd); $fwrite (fd, " 1046"); end 17'b00_10??_?_????_?1_1111 : casez (foo[11: 5]) 7'b??_0_010_0: begin $fwrite (fd, " 1047"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1048"); ozonef1e(foo, fd); dude(fd); $fwrite (fd, " 1049"); end 7'b00_?_110_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1050"); case ({foo[ 9],foo[ 5]}) 2'b00: begin $fwrite (fd, " 1051"); ozoneae(foo[14:12], fd); ozonehl(foo[ 5], fd); end 2'b01: begin $fwrite (fd, " 1052"); ozoneae(foo[14:12], fd); ozonehl(foo[ 5], fd); end 2'b10: begin $fwrite (fd, " 1053"); ozoneae(foo[14:12], fd); end 2'b11: $fwrite (fd, " 1054"); endcase dude(fd); $fwrite (fd, " 1055"); end 7'b01_?_110_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1056"); case ({foo[ 9],foo[ 5]}) 2'b00: begin ozoneae(foo[14:12], fd); ozonehl(foo[ 5], fd); $fwrite (fd, " 1057"); end 2'b01: begin ozoneae(foo[14:12], fd); ozonehl(foo[ 5], fd); $fwrite (fd, " 1058"); end 2'b10: begin ozoneae(foo[14:12], fd); $fwrite (fd, " 1059"); end 2'b11: $fwrite (fd, " 1060"); endcase dude(fd); $fwrite (fd, " 1061"); end 7'b10_0_110_0: begin ozonef1e(foo, fd); $fwrite (fd, " 1062"); $fwrite (fd, " 1063"); if (foo[12]) $fwrite (fd, " 1064"); else ozonerab({4'b1001, foo[14:12]}, fd); dude(fd); $fwrite (fd, " 1065"); end 7'b10_0_110_1: begin ozonef1e(foo, fd); $fwrite (fd, " 1066"); if (foo[12]) $fwrite (fd, " 1067"); else ozonerab({4'b1001, foo[14:12]}, fd); $fwrite (fd, " 1068"); dude(fd); $fwrite (fd, " 1069"); end 7'b??_?_000_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1070"); $fwrite (fd, " 1071"); ozonef1e_hl(foo[11:9],foo[ 5], fd); $fwrite (fd, " 1072"); ozonef1e_ye(foo[14:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1073"); end 7'b??_?_100_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1074"); $fwrite (fd, " 1075"); ozonef1e_hl(foo[11:9],foo[ 5], fd); $fwrite (fd, " 1076"); ozonef1e_ye(foo[14:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1077"); end 7'b??_?_001_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1078"); ozonef1e_ye(foo[14:9],foo[ 5], fd); $fwrite (fd, " 1079"); $fwrite (fd, " 1080"); ozonef1e_hl(foo[11:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1081"); end 7'b??_?_011_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1082"); ozonef1e_ye(foo[14:9],foo[ 5], fd); $fwrite (fd, " 1083"); $fwrite (fd, " 1084"); ozonef1e_hl(foo[11:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1085"); end 7'b??_?_101_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1086"); ozonef1e_ye(foo[14:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1087"); end endcase 17'b00_10??_?_????_?0_0110 : begin ozonef1e(foo, fd); $fwrite (fd, " 1088"); ozoneae(foo[ 8: 6], fd); ozonef1e_hl(foo[11:9],foo[ 5], fd); $fwrite (fd, " 1089"); ozonef1e_ye(foo[14:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1090"); end 17'b00_10??_?_????_00_0111 : begin ozonef1e(foo, fd); $fwrite (fd, " 1091"); if (foo[ 6]) $fwrite (fd, " 1092"); else ozonerab({4'b1001, foo[ 8: 6]}, fd); $fwrite (fd, " 1093"); $fwrite (fd, " 1094"); ozonerme(foo[14:12], fd); case (foo[11: 9]) 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9],1'b0, fd); 3'h1, 3'h3, 3'h4: $fwrite (fd, " 1095"); endcase dude(fd); $fwrite (fd, " 1096"); end 17'b00_10??_?_????_?0_0100 : begin ozonef1e(foo, fd); $fwrite (fd, " 1097"); ozonef1e_ye(foo[14:9],foo[ 5], fd); $fwrite (fd, " 1098"); ozoneae(foo[ 8: 6], fd); ozonef1e_hl(foo[11:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1099"); end 17'b00_10??_?_????_10_0111 : begin ozonef1e(foo, fd); $fwrite (fd, " 1100"); $fwrite (fd, " 1101"); ozonerme(foo[14:12], fd); case (foo[11: 9]) 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9],1'b0, fd); 3'h1, 3'h3, 3'h4: $fwrite (fd, " 1102"); endcase $fwrite (fd, " 1103"); if (foo[ 6]) $fwrite (fd, " 1104"); else ozonerab({4'b1001, foo[ 8: 6]}, fd); dude(fd); $fwrite (fd, " 1105"); end 17'b00_10??_?_????_?0_1110 : begin ozonef1e(foo, fd); $fwrite (fd, " 1106"); case (foo[11:9]) 3'h2: begin $fwrite (fd, " 1107"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1108"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1109"); end 3'h6: begin $fwrite (fd, " 1110"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1111"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1112"); end 3'h0: begin $fwrite (fd, " 1113"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1114"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1115"); if (foo[ 7: 5] >= 3'h5) $fwrite (fd, " 1116"); else ozonexe(foo[ 8: 5], fd); end 3'h1: begin $fwrite (fd, " 1117"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1118"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1119"); if (foo[ 7: 5] >= 3'h5) $fwrite (fd, " 1120"); else ozonexe(foo[ 8: 5], fd); end 3'h4: begin $fwrite (fd, " 1121"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1122"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1123"); if (foo[ 7: 5] >= 3'h5) $fwrite (fd, " 1124"); else ozonexe(foo[ 8: 5], fd); end 3'h5: begin $fwrite (fd, " 1125"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1126"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1127"); if (foo[ 7: 5] >= 3'h5) $fwrite (fd, " 1128"); else ozonexe(foo[ 8: 5], fd); end endcase dude(fd); $fwrite (fd, " 1129"); end 17'b00_10??_?_????_?0_1111 : casez (foo[14: 9]) 6'b001_10_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1130"); $fwrite (fd, " 1131"); ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); $fwrite (fd, " 1132"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1133"); end 6'b???_11_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1134"); ozoneae(foo[14:12], fd); ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); $fwrite (fd, " 1135"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1136"); end 6'b000_10_1, 6'b010_10_1, 6'b100_10_1, 6'b110_10_1: begin ozonef1e(foo, fd); $fwrite (fd, " 1137"); ozonerab({4'b1001, foo[14:12]}, fd); $fwrite (fd, " 1138"); if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) $fwrite (fd, " 1139"); else ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1140"); end 6'b000_10_0, 6'b010_10_0, 6'b100_10_0, 6'b110_10_0: begin ozonef1e(foo, fd); $fwrite (fd, " 1141"); $fwrite (fd, " 1142"); ozonerab({4'b1001, foo[14:12]}, fd); $fwrite (fd, " 1143"); $fwrite (fd, " 1144"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1145"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1146"); end 6'b???_00_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1147"); if (foo[ 9]) begin $fwrite (fd, " 1148"); ozoneae(foo[14:12], fd); end else begin $fwrite (fd, " 1149"); ozoneae(foo[14:12], fd); $fwrite (fd, " 1150"); end $fwrite (fd, " 1151"); $fwrite (fd, " 1152"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1153"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1154"); end 6'b???_01_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1155"); ozoneae(foo[14:12], fd); if (foo[ 9]) $fwrite (fd, " 1156"); else $fwrite (fd, " 1157"); $fwrite (fd, " 1158"); $fwrite (fd, " 1159"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1160"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1161"); end 6'b011_10_0: begin ozonef1e(foo, fd); $fwrite (fd, " 1162"); case (foo[ 8: 5]) 4'h0: $fwrite (fd, " 1163"); 4'h1: $fwrite (fd, " 1164"); 4'h2: $fwrite (fd, " 1165"); 4'h3: $fwrite (fd, " 1166"); 4'h4: $fwrite (fd, " 1167"); 4'h5: $fwrite (fd, " 1168"); 4'h8: $fwrite (fd, " 1169"); 4'h9: $fwrite (fd, " 1170"); 4'ha: $fwrite (fd, " 1171"); 4'hb: $fwrite (fd, " 1172"); 4'hc: $fwrite (fd, " 1173"); 4'hd: $fwrite (fd, " 1174"); default: $fwrite (fd, " 1175"); endcase dude(fd); $fwrite (fd, " 1176"); end default: $fwrite (fd, " 1177"); endcase 17'b00_10??_?_????_?0_110? : begin ozonef1e(foo, fd); $fwrite (fd, " 1178"); $fwrite (fd, " 1179"); ozonef1e_hl(foo[11:9], foo[0], fd); $fwrite (fd, " 1180"); ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1181"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1182"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1183"); end 17'b00_10??_?_????_?1_110? : begin ozonef1e(foo, fd); $fwrite (fd, " 1184"); $fwrite (fd, " 1185"); ozonef1e_hl(foo[11:9],foo[0], fd); $fwrite (fd, " 1186"); ozonef1e_ye(foo[14:9],foo[ 0], fd); $fwrite (fd, " 1187"); $fwrite (fd, " 1188"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1189"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1190"); end 17'b00_10??_?_????_?0_101? : begin ozonef1e(foo, fd); $fwrite (fd, " 1191"); ozonef1e_ye(foo[14:9],foo[ 0], fd); $fwrite (fd, " 1192"); $fwrite (fd, " 1193"); ozonef1e_hl(foo[11:9],foo[0], fd); $fwrite (fd, " 1194"); $fwrite (fd, " 1195"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1196"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1197"); end 17'b00_10??_?_????_?0_1001 : begin ozonef1e(foo, fd); $fwrite (fd, " 1198"); $fwrite (fd, " 1199"); ozonef1e_h(foo[11:9], fd); $fwrite (fd, " 1200"); ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1201"); case (foo[ 7: 5]) 3'h1, 3'h2, 3'h3: $fwrite (fd, " 1202"); default: begin $fwrite (fd, " 1203"); $fwrite (fd, " 1204"); ozonexe(foo[ 8: 5], fd); end endcase dude(fd); $fwrite (fd, " 1205"); end 17'b00_10??_?_????_?0_0101 : begin ozonef1e(foo, fd); $fwrite (fd, " 1206"); case (foo[11: 9]) 3'h1, 3'h3, 3'h4: $fwrite (fd, " 1207"); default: begin ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1208"); $fwrite (fd, " 1209"); end endcase $fwrite (fd, " 1210"); $fwrite (fd, " 1211"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1212"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1213"); end 17'b00_10??_?_????_?1_1110 : begin ozonef1e(foo, fd); $fwrite (fd, " 1214"); ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1215"); $fwrite (fd, " 1216"); ozonef1e_h(foo[11: 9], fd); $fwrite (fd, " 1217"); $fwrite (fd, " 1218"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1219"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1220"); end 17'b00_10??_?_????_?0_1000 : begin ozonef1e(foo, fd); $fwrite (fd, " 1221"); ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1222"); $fwrite (fd, " 1223"); ozonef1e_h(foo[11: 9], fd); $fwrite (fd, " 1224"); $fwrite (fd, " 1225"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1226"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1227"); end 17'b10_01??_?_????_??_???? : begin if (foo[27]) $fwrite (fd," 1228"); else $fwrite (fd," 1229"); ozonecon(foo[20:16], fd); $fwrite (fd, " 1230"); ozonef2(foo[31:0], fd); dude(fd); $fwrite (fd, " 1231"); end 17'b00_1000_?_????_01_0011 : if (~|foo[ 9: 8]) begin if (foo[ 7]) $fwrite (fd," 1232"); else $fwrite (fd," 1233"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1234"); ozonef2e(foo[31:0], fd); dude(fd); $fwrite (fd, " 1235"); end else begin $fwrite (fd, " 1236"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1237"); ozonef3e(foo[31:0], fd); dude(fd); $fwrite (fd, " 1238"); end 17'b11_110?_1_????_??_???? : begin ozonef3(foo[31:0], fd); dude(fd); $fwrite(fd, " 1239"); end 17'b11_110?_0_????_??_???? : begin : f4_body casez (foo[24:20]) 5'b0_1110, 5'b1_0???, 5'b1_1111: begin $fwrite (fd, " 1240"); end 5'b0_00??: begin ozoneacc(foo[26], fd); $fwrite (fd, " 1241"); ozoneacc(foo[25], fd); ozonebmuop(foo[24:20], fd); ozoneae(foo[18:16], fd); $fwrite (fd, " 1242"); dude(fd); $fwrite(fd, " 1243"); end 5'b0_01??: begin ozoneacc(foo[26], fd); $fwrite (fd, " 1244"); ozoneacc(foo[25], fd); ozonebmuop(foo[24:20], fd); ozonearm(foo[18:16], fd); dude(fd); $fwrite(fd, " 1245"); end 5'b0_1011: begin ozoneacc(foo[26], fd); $fwrite (fd, " 1246"); ozonebmuop(foo[24:20], fd); $fwrite (fd, " 1247"); ozoneae(foo[18:16], fd); $fwrite (fd, " 1248"); dude(fd); $fwrite(fd, " 1249"); end 5'b0_100?, 5'b0_1010, 5'b0_110? : begin ozoneacc(foo[26], fd); $fwrite (fd, " 1250"); ozonebmuop(foo[24:20], fd); $fwrite (fd, " 1251"); ozoneacc(foo[25], fd); $fwrite (fd, " 1252"); ozoneae(foo[18:16], fd); $fwrite (fd, " 1253"); dude(fd); $fwrite(fd, " 1254"); end 5'b0_1111 : begin ozoneacc(foo[26], fd); $fwrite (fd, " 1255"); ozoneacc(foo[25], fd); $fwrite (fd, " 1256"); ozoneae(foo[18:16], fd); dude(fd); $fwrite(fd, " 1257"); end 5'b1_10??, 5'b1_110?, 5'b1_1110 : begin ozoneacc(foo[26], fd); $fwrite (fd, " 1258"); ozonebmuop(foo[24:20], fd); $fwrite (fd, " 1259"); ozoneacc(foo[25], fd); $fwrite (fd, " 1260"); ozonearm(foo[18:16], fd); $fwrite (fd, " 1261"); dude(fd); $fwrite(fd, " 1262"); end endcase end 17'b11_100?_?_????_??_???? : casez (foo[23:19]) 5'b111??, 5'b0111?: begin ozoneae(foo[26:24], fd); $fwrite (fd, " 1263"); ozonef3f4imop(foo[23:19], fd); $fwrite (fd, " 1264"); ozoneae(foo[18:16], fd); $fwrite (fd, " 1265"); skyway(foo[15:12], fd); skyway(foo[11: 8], fd); skyway(foo[ 7: 4], fd); skyway(foo[ 3:0], fd); $fwrite (fd, " 1266"); dude(fd); $fwrite(fd, " 1267"); end 5'b?0???, 5'b110??: begin ozoneae(foo[26:24], fd); $fwrite (fd, " 1268"); if (foo[23:21] == 3'b100) $fwrite (fd, " 1269"); ozoneae(foo[18:16], fd); if (foo[19]) $fwrite (fd, " 1270"); else $fwrite (fd, " 1271"); ozonef3f4imop(foo[23:19], fd); $fwrite (fd, " 1272"); ozonef3f4_iext(foo[20:19], foo[15:0], fd); dude(fd); $fwrite(fd, " 1273"); end 5'b010??, 5'b0110?: begin ozoneae(foo[18:16], fd); if (foo[19]) $fwrite (fd, " 1274"); else $fwrite (fd, " 1275"); ozonef3f4imop(foo[23:19], fd); $fwrite (fd, " 1276"); ozonef3f4_iext(foo[20:19], foo[15:0], fd); dude(fd); $fwrite(fd, " 1277"); end endcase 17'b00_1000_?_????_11_0011 : begin $fwrite (fd," 1278"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1279"); casez (foo[25:21]) 5'b0_1110, 5'b1_0???, 5'b1_1111: begin $fwrite(fd, " 1280"); end 5'b0_00??: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1281"); ozoneae(foo[17:15], fd); ozonebmuop(foo[25:21], fd); ozoneae(foo[ 8: 6], fd); $fwrite (fd, " 1282"); dude(fd); $fwrite(fd, " 1283"); end 5'b0_01??: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1284"); ozoneae(foo[17:15], fd); ozonebmuop(foo[25:21], fd); ozonearm(foo[ 8: 6], fd); dude(fd); $fwrite(fd, " 1285"); end 5'b0_1011: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1286"); ozonebmuop(foo[25:21], fd); $fwrite (fd, " 1287"); ozoneae(foo[ 8: 6], fd); $fwrite (fd, " 1288"); dude(fd); $fwrite(fd, " 1289"); end 5'b0_100?, 5'b0_1010, 5'b0_110? : begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1290"); ozonebmuop(foo[25:21], fd); $fwrite (fd, " 1291"); ozoneae(foo[17:15], fd); $fwrite (fd, " 1292"); ozoneae(foo[ 8: 6], fd); $fwrite (fd, " 1293"); dude(fd); $fwrite(fd, " 1294"); end 5'b0_1111 : begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1295"); ozoneae(foo[17:15], fd); $fwrite (fd, " 1296"); ozoneae(foo[ 8: 6], fd); dude(fd); $fwrite(fd, " 1297"); end 5'b1_10??, 5'b1_110?, 5'b1_1110 : begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1298"); ozonebmuop(foo[25:21], fd); $fwrite (fd, " 1299"); ozoneae(foo[17:15], fd); $fwrite (fd, " 1300"); ozonearm(foo[ 8: 6], fd); $fwrite (fd, " 1301"); dude(fd); $fwrite(fd, " 1302"); end endcase end 17'b00_0010_?_????_??_???? : begin ozonerab({1'b0, foo[25:20]}, fd); $fwrite (fd, " 1303"); skyway(foo[19:16], fd); dude(fd); $fwrite(fd, " 1304"); end 17'b00_01??_?_????_??_???? : begin if (foo[27]) begin $fwrite (fd, " 1305"); if (foo[26]) $fwrite (fd, " 1306"); else $fwrite (fd, " 1307"); skyway(foo[19:16], fd); $fwrite (fd, " 1308"); ozonerab({1'b0, foo[25:20]}, fd); end else begin ozonerab({1'b0, foo[25:20]}, fd); $fwrite (fd, " 1309"); if (foo[26]) $fwrite (fd, " 1310"); else $fwrite (fd, " 1311"); skyway(foo[19:16], fd); $fwrite (fd, " 1312"); end dude(fd); $fwrite(fd, " 1313"); end 17'b01_000?_?_????_??_???? : begin if (foo[26]) begin ozonerb(foo[25:20], fd); $fwrite (fd, " 1314"); ozoneae(foo[18:16], fd); ozonehl(foo[19], fd); end else begin ozoneae(foo[18:16], fd); ozonehl(foo[19], fd); $fwrite (fd, " 1315"); ozonerb(foo[25:20], fd); end dude(fd); $fwrite(fd, " 1316"); end 17'b01_10??_?_????_??_???? : begin if (foo[27]) begin ozonerab({1'b0, foo[25:20]}, fd); $fwrite (fd, " 1317"); ozonerx(foo, fd); end else begin ozonerx(foo, fd); $fwrite (fd, " 1318"); ozonerab({1'b0, foo[25:20]}, fd); end dude(fd); $fwrite(fd, " 1319"); end 17'b11_101?_?_????_??_???? : begin ozonerab (foo[26:20], fd); $fwrite (fd, " 1320"); skyway(foo[19:16], fd); skyway(foo[15:12], fd); skyway(foo[11: 8], fd); skyway(foo[ 7: 4], fd); skyway(foo[ 3: 0], fd); dude(fd); $fwrite(fd, " 1321"); end 17'b11_0000_?_????_??_???? : begin casez (foo[25:23]) 3'b00?: begin ozonerab(foo[22:16], fd); $fwrite (fd, " 1322"); end 3'b01?: begin $fwrite (fd, " 1323"); if (foo[22:16]>=7'h60) $fwrite (fd, " 1324"); else ozonerab(foo[22:16], fd); end 3'b110: $fwrite (fd, " 1325"); 3'b10?: begin $fwrite (fd, " 1326"); if (foo[22:16]>=7'h60) $fwrite (fd, " 1327"); else ozonerab(foo[22:16], fd); end 3'b111: begin $fwrite (fd, " 1328"); ozonerab(foo[22:16], fd); $fwrite (fd, " 1329"); end endcase dude(fd); $fwrite(fd, " 1330"); end 17'b00_10??_?_????_?1_0000 : begin if (foo[27]) begin $fwrite (fd, " 1331"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1332"); skyway(foo[19:16], fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); $fwrite (fd, " 1333"); if (foo[26:20]>=7'h60) $fwrite (fd, " 1334"); else ozonerab(foo[26:20], fd); end else begin ozonerab(foo[26:20], fd); $fwrite (fd, " 1335"); $fwrite (fd, " 1336"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1337"); skyway(foo[19:16], fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); $fwrite (fd, " 1338"); end dude(fd); $fwrite(fd, " 1339"); end 17'b00_101?_1_0000_?1_0010 : if (~|foo[11: 7]) begin if (foo[ 6]) begin $fwrite (fd, " 1340"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1341"); ozonejk(foo[ 5], fd); $fwrite (fd, " 1342"); if (foo[26:20]>=7'h60) $fwrite (fd, " 1343"); else ozonerab(foo[26:20], fd); end else begin ozonerab(foo[26:20], fd); $fwrite (fd, " 1344"); $fwrite (fd, " 1345"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1346"); ozonejk(foo[ 5], fd); $fwrite (fd, " 1347"); end dude(fd); $fwrite(fd, " 1348"); end else $fwrite(fd, " 1349"); 17'b00_100?_0_0011_?1_0101 : if (~|foo[ 8: 7]) begin if (foo[6]) begin ozonerab(foo[26:20], fd); $fwrite (fd, " 1350"); ozoneye(foo[14: 9],foo[ 5], fd); end else begin ozoneye(foo[14: 9],foo[ 5], fd); $fwrite (fd, " 1351"); if (foo[26:20]>=7'h60) $fwrite (fd, " 1352"); else ozonerab(foo[26:20], fd); end dude(fd); $fwrite(fd, " 1353"); end else $fwrite(fd, " 1354"); 17'b00_1001_0_0000_?1_0010 : if (~|foo[25:20]) begin ozoneye(foo[14: 9],1'b0, fd); $fwrite (fd, " 1355"); ozonef1e_h(foo[11: 9], fd); $fwrite (fd, " 1356"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1357"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite(fd, " 1358"); end else $fwrite(fd, " 1359"); 17'b00_101?_0_????_?1_0010 : if (~foo[13]) begin if (foo[12]) begin $fwrite (fd, " 1360"); if (foo[26:20]>=7'h60) $fwrite (fd, " 1361"); else ozonerab(foo[26:20], fd); $fwrite (fd, " 1362"); $fwrite (fd, " 1363"); skyway({1'b0,foo[18:16]}, fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); dude(fd); $fwrite(fd, " 1364"); end else begin ozonerab(foo[26:20], fd); $fwrite (fd, " 1365"); $fwrite (fd, " 1366"); skyway({1'b0,foo[18:16]}, fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); dude(fd); $fwrite(fd, " 1367"); end end else $fwrite(fd, " 1368"); 17'b01_01??_?_????_??_???? : begin ozonerab({1'b0,foo[27:26],foo[19:16]}, fd); $fwrite (fd, " 1369"); ozonerab({1'b0,foo[25:20]}, fd); dude(fd); $fwrite(fd, " 1370"); end 17'b00_100?_?_???0_11_0101 : if (~foo[6]) begin $fwrite (fd," 1371"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1372"); ozonerab({foo[ 9: 7],foo[19:16]}, fd); $fwrite (fd, " 1373"); ozonerab({foo[26:20]}, fd); dude(fd); $fwrite(fd, " 1374"); end else $fwrite(fd, " 1375"); 17'b00_1000_?_????_?1_0010 : if (~|foo[25:24]) begin ozonery(foo[23:20], fd); $fwrite (fd, " 1376"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1377"); skyway(foo[19:16], fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); dude(fd); $fwrite(fd, " 1378"); end else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) begin ozonery(foo[23:20], fd); $fwrite (fd, " 1379"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1380"); ozonejk(foo[ 5], fd); dude(fd); $fwrite(fd, " 1381"); end else $fwrite(fd, " 1382"); 17'b11_01??_?_????_??_????, 17'b10_00??_?_????_??_???? : if (foo[30]) $fwrite(fd, " 1383:%x", foo[27:16]); else $fwrite(fd, " 1384:%x", foo[27:16]); 17'b00_10??_?_????_01_1000 : if (~foo[6]) begin if (foo[7]) $fwrite(fd, " 1385:%x", foo[27: 8]); else $fwrite(fd, " 1386:%x", foo[27: 8]); end else $fwrite(fd, " 1387"); 17'b00_10??_?_????_11_1000 : begin $fwrite (fd," 1388"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1389"); if (foo[15]) $fwrite (fd, " 1390"); else $fwrite (fd, " 1391"); skyway(foo[27:24], fd); skyway(foo[23:20], fd); skyway(foo[19:16], fd); skyway(foo[ 9: 6], fd); dude(fd); $fwrite(fd, " 1392"); end 17'b11_0001_?_????_??_???? : casez (foo[25:22]) 4'b01?? : begin $fwrite (fd," 1393"); ozonecon(foo[20:16], fd); case (foo[23:21]) 3'h0 : $fwrite (fd, " 1394"); 3'h1 : $fwrite (fd, " 1395"); 3'h2 : $fwrite (fd, " 1396"); 3'h3 : $fwrite (fd, " 1397"); 3'h4 : $fwrite (fd, " 1398"); 3'h5 : $fwrite (fd, " 1399"); 3'h6 : $fwrite (fd, " 1400"); 3'h7 : $fwrite (fd, " 1401"); endcase dude(fd); $fwrite(fd, " 1402"); end 4'b0000 : $fwrite(fd, " 1403:%x", foo[21:16]); 4'b0010 : if (~|foo[21:16]) $fwrite(fd, " 1404"); 4'b1010 : if (~|foo[21:17]) begin if (foo[16]) $fwrite(fd, " 1405"); else $fwrite(fd, " 1406"); end default : $fwrite(fd, " 1407"); endcase 17'b01_11??_?_????_??_???? : if (foo[27:23] === 5'h00) $fwrite(fd, " 1408:%x", foo[22:16]); else $fwrite(fd, " 1409:%x", foo[22:16]); default: $fwrite(fd, " 1410"); endcase end endtask //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) endmodule verilator-4.038/test_regress/t/t_class_member_bad.pl0000775000177100017500000000107413702133367022624 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_literals.v0000664000177100017500000000171413702133370022041 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `timescale 1ns/1ps module t; time t; // realtime value scaled to timeunit, rounded to timeprecision initial begin // verilator lint_off REALCVT t = 1s; `checkd(t, 64'd1000000000); t = 2ms; `checkd(t, 2000000); t = 1ms; `checkd(t, 1000000); t = 1us; `checkd(t, 1000); t = 1ns; `checkd(t, 1); t = 1ps; `checkd(t, 0); // Below precision t = 1fs; `checkd(t, 0); t = 2.3ps; `checkd(t, 0); t = 2.4us; `checkd(t, 2400); // verilator lint_on REALCVT $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_enum_bad_hide.out0000664000177100017500000000101613702133370022304 0ustar wsnyderwsnyder%Warning-VARHIDDEN: t/t_enum_bad_hide.v:11:19: Declaration of enum value hides declaration in upper scope: HIDE_VALUE 11 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; | ^~~~~~~~~~ t/t_enum_bad_hide.v:7:16: ... Location of original declaration 11 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; | ^~~~~~~~~~ ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_math_shift_sel.pl0000775000177100017500000000105313702133370022342 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_input_eq_bad.pl0000775000177100017500000000107113702133370023031 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_shortcircuit.v0000664000177100017500000002055013702133370022561 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_SHORTREAL `endif `ifdef NC `define NO_SHORTREAL `endif `ifdef VERILATOR // Unsupported `define NO_SHORTREAL `endif module t (/*AUTOARG*/); // Note these are NOT pure. import "DPI-C" function int dpii_clear (); import "DPI-C" function int dpii_count (input int ctr); import "DPI-C" function bit dpii_inc0 (input int ctr); import "DPI-C" function bit dpii_inc1 (input int ctr); import "DPI-C" function bit dpii_incx (input int ctr, input bit value); integer i; integer j; bit b; integer errors; task check1(integer line, bit got, bit ex); if (got != ex) begin $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); errors++; end endtask task check(integer line, int got, int ex); if (got != ex) begin $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); errors++; end endtask // Test loop initial begin // Spec says && || -> and ?: short circuit, no others do. // Check both constant & non constants. dpii_clear(); check1(`__LINE__, (1'b0 && dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 && dpii_inc0(1)), 1'b0); check1(`__LINE__, (dpii_inc0(2) && dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) && dpii_inc0(5)), 1'b0); check1(`__LINE__, (dpii_inc0(6) && dpii_inc1(7)), 1'b0); check1(`__LINE__, (!(dpii_inc1(8) && dpii_inc1(9))), 1'b0); check (`__LINE__, dpii_count(0), 0); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 0); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 0); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); // dpii_clear(); check1(`__LINE__, (1'b0 & dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 & dpii_inc0(1)), 1'b0); check1(`__LINE__, (dpii_inc0(2) & dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) & dpii_inc0(5)), 1'b0); check1(`__LINE__, (dpii_inc0(6) & dpii_inc1(7)), 1'b0); check1(`__LINE__, (!(dpii_inc1(8) & dpii_inc1(9))), 1'b0); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); // dpii_clear(); check1(`__LINE__, (1'b0 || dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 || dpii_inc0(1)), 1'b1); check1(`__LINE__, (dpii_inc0(2) || dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) || dpii_inc0(5)), 1'b1); check1(`__LINE__, (dpii_inc0(6) || dpii_inc1(7)), 1'b1); check1(`__LINE__, (!(dpii_inc1(8) || dpii_inc1(9))), 1'b0); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 0); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 0); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 0); // dpii_clear(); check1(`__LINE__, (1'b0 | dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 | dpii_inc0(1)), 1'b1); check1(`__LINE__, (dpii_inc0(2) | dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) | dpii_inc0(5)), 1'b1); check1(`__LINE__, (dpii_inc0(6) | dpii_inc1(7)), 1'b1); check1(`__LINE__, (!(dpii_inc1(8) | dpii_inc1(9))), 1'b0); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); // dpii_clear(); check1(`__LINE__, (1'b0 -> dpii_inc0(0)), 1'b1); check1(`__LINE__, (1'b1 -> dpii_inc0(1)), 1'b0); check1(`__LINE__, (dpii_inc0(2) -> dpii_inc0(3)), 1'b1); check1(`__LINE__, (dpii_inc1(4) -> dpii_inc0(5)), 1'b0); check1(`__LINE__, (dpii_inc0(6) -> dpii_inc1(7)), 1'b1); check1(`__LINE__, (!(dpii_inc1(8) -> dpii_inc1(9))), 1'b0); check (`__LINE__, dpii_count(0), 0); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 0); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 0); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); // dpii_clear(); check1(`__LINE__, (1'b0 ? dpii_inc0(0) : dpii_inc0(1)), 1'b0); check1(`__LINE__, (1'b1 ? dpii_inc0(2) : dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc0(4) ? dpii_inc0(5) : dpii_inc0(6)), 1'b0); check1(`__LINE__, (dpii_inc1(7) ? dpii_inc0(8) : dpii_inc0(9)), 1'b0); check (`__LINE__, dpii_count(0), 0); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 0); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 0); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 0); // dpii_clear(); check1(`__LINE__, (1'b0 * dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 * dpii_inc0(1)), 1'b0); check1(`__LINE__, (dpii_inc0(2) * dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) * dpii_inc0(5)), 1'b0); check1(`__LINE__, (dpii_inc0(6) * dpii_inc1(7)), 1'b0); check1(`__LINE__, (!(dpii_inc1(8) * dpii_inc1(9))), 1'b0); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); // dpii_clear(); check1(`__LINE__, (1'b0 + dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 + dpii_inc0(1)), 1'b1); check1(`__LINE__, (dpii_inc0(2) + dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) + dpii_inc0(5)), 1'b1); check1(`__LINE__, (dpii_inc0(6) + dpii_inc1(7)), 1'b1); check1(`__LINE__, (dpii_inc1(8) + dpii_inc1(9)), 1'b0); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); // // Something a lot more complicated dpii_clear(); for (i=0; i<64; i++) begin b = ( ((dpii_incx(0,i[0]) && (dpii_incx(1,i[1]) || dpii_incx(2,i[2]) | dpii_incx(3,i[3]))) // | not || || dpii_incx(4,i[4])) -> dpii_incx(5,i[5])); end check (`__LINE__, dpii_count(0), 64); check (`__LINE__, dpii_count(1), 32); check (`__LINE__, dpii_count(2), 16); check (`__LINE__, dpii_count(3), 16); check (`__LINE__, dpii_count(4), 36); check (`__LINE__, dpii_count(5), 46); if (|errors) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_enum_type_methods_bad.out0000664000177100017500000000055013702133370024101 0ustar wsnyderwsnyder%Error: Internal Error: t/t_enum_type_methods_bad.v:24:14: ../V3Width.cpp:#: Unsupported: enum next/prev with non-const argument : ... In instance t 24 | e.next(increment); | ^~~~~~~~~ ... See the manual and https://verilator.org for more assistance. verilator-4.038/test_regress/t/t_dist_install.pl0000775000177100017500000000314413702133370022045 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use Cwd; scenarios(dist => 1); my $root = ".."; my $Debug; if (!-r "$root/.git") { skip("Not in a git repository"); } else { my $cwd = getcwd(); my $destdir = "$cwd/".$Self->{obj_dir}; # Start clean run(cmd => ["rm -rf $destdir && mkdir -p $destdir"], check_finished => 0); # Install into temp area print "Install...\n"; run(cmd => ["cd $root && $ENV{MAKE} DESTDIR=$destdir install-all"], check_finished => 0); # Check we can run a test # Unfortunately the prefix was hardcoded in the exec at a different place, # so we can't do much here. #print "Check install...\n"; # Uninstall print "Uninstall...\n"; run(cmd => ["cd $root && $ENV{MAKE} DESTDIR=$destdir uninstall"], check_finished => 0); # Check empty my @files; $finds = `find $destdir -type f -print`; foreach my $file (split /\n/, $finds) { next if $file =~ /\.status/; # Made by driver.pl, not Verilator print "\tLEFT: $file\n"; $file =~ s!^$cwd!.!; push @files, $file; } if ($#files >= 0) { error("Uninstall missed files: ",join(' ',@files)); } } ok(1); 1; verilator-4.038/test_regress/t/t_assert_comp_bad.out0000664000177100017500000000162213702133367022677 0ustar wsnyderwsnyder-Info: t/t_assert_comp_bad.v:10:7: User compile-time info : ... In instance t 10 | $info("User compile-time info"); | ^~~~~ %Warning-USERWARN: t/t_assert_comp_bad.v:11:7: User compile-time warning : ... In instance t 11 | $warning("User compile-time warning"); | ^~~~~~~~ ... Use "/* verilator lint_off USERWARN */" and lint_on around source to disable this message. %Warning-USERWARN: t/t_assert_comp_bad.v:12:7: 1 : ... In instance t 12 | $warning(1); | ^~~~~~~~ %Warning-USERERROR: t/t_assert_comp_bad.v:13:7: User compile-time error : ... In instance t 13 | $error("User compile-time error"); | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_string_type_methods.pl0000775000177100017500000000105313702133370023443 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_cond.v0000664000177100017500000000103613702133370020762 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs b, // Inputs clk, en, a ); // bug1017 input clk; input en; input a[1]; output logic b[1]; always_ff @ (posedge clk) begin b <= en ? a : b; end always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_select_plus.v0000664000177100017500000000724113702133370021527 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [83:4] from; reg [83:4] to; reg [6:0] bitn; reg [3:0] nibblep; reg [3:0] nibblem; reg [7:0] cyc; initial cyc=0; always @* begin nibblep = from[bitn +: 4]; nibblem = from[bitn -: 4]; to = from; to[bitn +: 4] = cyc[3:0]; to[bitn -: 4] = cyc[3:0]; end always @ (posedge clk) begin //$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n",$time, cyc, nibblep, nibblem, from^to); cyc <= cyc + 8'd1; case (cyc) 8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end 8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end 8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -: 8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end 8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +: 8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc 8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc 8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end 8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate 8'd09: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase case (cyc) 8'd00: ; 8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end 8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end 8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end 8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end 8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end 8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end 8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end 8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end 8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end default: $stop; endcase case (cyc) 8'd00: ; 8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end 8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end 8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end 8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end 8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0 8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0 8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end 8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end 8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end default: $stop; endcase end // Additional constant folding check - this used to trigger a bug reg [23:0] a; reg [3:0] b; initial begin a = 24'd0; b = 4'b0111; a[3*(b[2:0]+0)+:3] = 3'd7; // Check LSB expression goes to 32-bits if (a != 24'b11100000_00000000_00000000) $stop; a = 24'd0; b = 4'b0110; a[3*(b[2:0]+0)-:3] = 3'd7; // Check MSB expression goes to 32-bits if (a != 24'b00000111_00000000_00000000) $stop; end endmodule verilator-4.038/test_regress/t/t_class_null_bad.pl0000775000177100017500000000112313702133367022322 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_timing_clkgen.pl0000775000177100017500000000157513702133370022174 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, clocking"); compile( #verilator_flags2 => ['--exe --build --main --timing'], # Unsupported verilator_flags2 => ['--exe --build --main --bbox-unsup -Wno-STMTDLY -Wno-INITIALDLY'], verilator_make_cmake => 0, verilator_make_gmake => 0, make_main => 0, make_top => 1, ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sv_bus_mux_demux.pl0000775000177100017500000000115613702133370022751 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug181"); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_overwide.pl0000775000177100017500000000121213702133370022227 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => [qw(-sc -Wno-WIDTH)], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); #No execute() ok(1); 1; verilator-4.038/test_regress/t/t_gate_delref.pl0000775000177100017500000000100113702133370021603 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_var_dotted_dup_bad.v0000664000177100017500000000066613702133370023022 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); generate begin eh2_ram dccm_bank (.*); end begin eh2_ram dccm_bank (.*); // Error: duplicate end endgenerate endmodule module eh2_ram (); endmodule verilator-4.038/test_regress/t/t_select_lhs_oob.v0000664000177100017500000000417413702133370022173 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [6:0] mem1d; reg [6:0] mem2d [5:0]; reg [6:0] mem3d [4:0][5:0]; integer i,j,k; // Four different test cases for out of bounds // = // <= // Continuous assigns // Output pin interconnect (also covers cont assigns) // Each with both bit selects and array selects initial begin mem1d[0] = 1'b0; i=7; mem1d[i] = 1'b1; if (mem1d[0] !== 1'b0) $stop; // for (i=0; i<8; i=i+1) begin for (j=0; j<8; j=j+1) begin for (k=0; k<8; k=k+1) begin mem1d[k] = k[0]; mem2d[j][k] = j[0]+k[0]; mem3d[i][j][k] = i[0]+j[0]+k[0]; end end end for (i=0; i<5; i=i+1) begin for (j=0; j<6; j=j+1) begin for (k=0; k<7; k=k+1) begin if (mem1d[k] !== k[0]) $stop; if (mem2d[j][k] !== j[0]+k[0]) $stop; if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop; end end end end integer wi; wire [31:0] wd = cyc; reg [31:0] reg2d[6:0]; always @ (posedge clk) reg2d[wi[2:0]] <= wd; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd); `endif cyc <= cyc + 1; if (cyc<10) begin wi <= 0; end else if (cyc==10) begin wi <= 1; end else if (cyc==11) begin if (reg2d[0] !== 10) $stop; wi <= 6; end else if (cyc==12) begin if (reg2d[0] !== 10) $stop; if (reg2d[1] !== 11) $stop; wi <= 7; // Will be ignored end else if (cyc==13) begin if (reg2d[0] !== 10) $stop; if (reg2d[1] !== 11) $stop; if (reg2d[6] !== 12) $stop; end else if (cyc==14) begin if (reg2d[0] !== 10) $stop; if (reg2d[1] !== 11) $stop; if (reg2d[6] !== 12) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_lint_comb_bad.out0000664000177100017500000000035413702133370022321 0ustar wsnyderwsnyder%Error: t/t_lint_comb_bad.v:14:4: Timing control statements not legal under always_comb : ... Suggest use a normal 'always' 14 | always_comb @(*) begin | ^~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_dotted.v0000664000177100017500000001033313702133370021477 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // verilator lint_off MULTIDRIVEN ma ma0 (); initial t.ma0.u_b[0].f(1); initial t.ma0.u_b[0].f(clk); global_mod #(32'hf00d) global_cell (); global_mod #(32'hf22d) global_cell2 (); input clk; integer cyc=1; function [31:0] getName; input fake; getName = "t "; endfunction always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==2) begin if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop; if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop; end if (cyc==3) begin if (ma0. getName(1'b0) !== "ma ") $stop; if (ma0.mb0. getName(1'b0) !== "mb ") $stop; if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop; end if (cyc==4) begin if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop; if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop; if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop; end if (cyc==5) begin ma0. checkName(ma0. getName(1'b0)); ma0.mb0. checkName(ma0.mb0. getName(1'b0)); ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0)); end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule `ifdef ATTRIBUTES `ifdef USE_INLINE_MID `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator no_inline_module*/ `else `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `define INLINE_MID_MODULE /*verilator public_module*/ `endif `endif `else `define INLINE_MODULE `define INLINE_MID_MODULE `endif module global_mod; `INLINE_MODULE parameter INITVAL = 0; integer globali; initial globali = INITVAL; function [31:0] getName; input fake; getName = "gmod"; endfunction function [31:0] getGlob; input fake; getGlob = globali; endfunction endmodule module ma (); `INLINE_MODULE mb #(0) mb0 (); reg [31:0] gName; initial gName = "ma "; function [31:0] getName; input fake; getName = "ma "; endfunction task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask initial begin if (ma.getName(1'b0) !== "ma ") $stop; if (mb0.getName(1'b0) !== "mb ") $stop; if (mb0.mc0.getName(1'b0) !== "mc ") $stop; end endmodule module mb (); `INLINE_MID_MODULE parameter P2 = 0; mc #(P2,0) mc0 (); mc #(P2,1) mc1 (); global_mod #(32'hf33d) global_cell2 (); reg [31:0] gName; initial gName = "mb "; function [31:0] getName; input fake; getName = "mb "; endfunction function [31:0] getP2 ; input fake; getP2 = P2; endfunction task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask initial begin `ifndef verilator #1; `endif if (ma. getName(1'b0) !== "ma ") $stop; if ( getName(1'b0) !== "mb ") $stop; if (mc1.getName(1'b0) !== "mc ") $stop; ma. checkName (ma. gName); /**/checkName ( gName); mc1.checkName (mc1.gName); ma. checkName (ma. getName(1'b0)); /**/checkName ( getName(1'b0)); mc1.checkName (mc1.getName(1'b0)); end endmodule module mc (); `INLINE_MODULE parameter P2 = 0; parameter P3 = 0; reg [31:0] gName; initial gName = "mc "; function [31:0] getName; input fake; getName = "mc "; endfunction function [31:0] getP3 ; input fake; getP3 = P3; endfunction task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask initial begin `ifndef verilator #1; `endif if (ma.getName(1'b0) !== "ma ") $stop; if (mb.getName(1'b0) !== "mb ") $stop; if (mc.getName(1'b0) !== "mc ") $stop; ma.checkName (ma.gName); mb.checkName (mb.gName); mc.checkName (mc.gName); ma.checkName (ma.getName(1'b0)); mb.checkName (mb.getName(1'b0)); mc.checkName (mc.getName(1'b0)); end endmodule module b; function void f(bit v); $display("%m"); endfunction : f; endmodule : b bind ma b u_b[0:1]; verilator-4.038/test_regress/t/t_tri_pull2_bad.out0000664000177100017500000000054213702133370022266 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_tri_pull2_bad.v:12:11: Unsupported: Conflicting pull directions. : ... In instance t 12 | pullup p1(A); | ^~ t/t_tri_pull2_bad.v:22:13: ... Location of conflicting pull. 22 | pulldown p2(A); | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_foreach.pl0000775000177100017500000000217713702133370020770 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert'] ); execute( check_finished => 1, ); # We expect all loops should be unrolled by verilator, # none of the loop variables should exist in the output: file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", qr/index_/); file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}__Slow.cpp", qr/index_/); # Further, we expect that all logic within the loop should # have been evaluated inside the compiler. So there should be # no references to 'sum' in the .cpp. file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", qr/sum/); file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}__Slow.cpp", qr/sum/); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_var.vlt0000664000177100017500000000065613702133370021174 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config sformat -task "mon_scope_name" -var "formatted" public_flat_rd -module "sub" -var "in" public_flat_rw -module "sub" -var "fr_a" @(posedge t.monclk) public_flat_rw -module "sub" -var "fr_b" @(posedge t.monclk) verilator-4.038/test_regress/t/t_runflag_seed.v0000664000177100017500000000113113702133370021633 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t; initial begin integer r = $random; integer ex; if ($value$plusargs("SEED=%x", ex) !== 1) $stop; `checkh(r, ex); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_enum_x_bad.v0000664000177100017500000000064513702133370021307 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); enum bit [1:0] { BADX = 2'b1x } BAD1; enum logic [3:0] { e0 = 4'b1xx1, e1 } BAD2; initial begin $stop; end endmodule verilator-4.038/test_regress/t/t_class_null_bad.v0000664000177100017500000000074013702133367022155 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int imembera; endclass : Cls module t (/*AUTOARG*/); Cls c; initial begin c = null; // Not really required as null is default c.imembera = 10; // BAD IEEE 8.4 $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_threads_counter_4.pl0000775000177100017500000000120213702133370022761 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); top_filename("t/t_threads_counter.v"); compile( verilator_flags2 => ['--cc --threads 4'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unopt_combo.v0000664000177100017500000000671213702133370021533 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; reg [63:0] sum; `ifdef ALLOW_UNOPT /*verilator lint_off UNOPTFLAT*/ `endif /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] b; // From file of file.v wire [31:0] c; // From file of file.v wire [31:0] d; // From file of file.v // End of automatics file file (/*AUTOINST*/ // Outputs .b (b[31:0]), .c (c[31:0]), .d (d[31:0]), // Inputs .crc (crc[31:0])); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= {b, d} ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== 64'h649ee1713d624dd9) $stop; $finish; end end endmodule module file (/*AUTOARG*/ // Outputs b, c, d, // Inputs crc ); input [31:0] crc; `ifdef ISOLATE output reg [31:0] b /* verilator isolate_assignments*/; `else output reg [31:0] b; `endif output reg [31:0] c; output reg [31:0] d; always @* begin // Note that while c and b depend on crc, b doesn't depend on c. casez (crc[3:0]) 4'b??01: begin b = {crc[15:0],get_31_16(crc)}; d = c; end 4'b??00: begin b = {crc[15:0],~crc[31:16]}; d = {crc[15:0],~c[31:16]}; end default: begin set_b_d(crc, c); end endcase end `ifdef ISOLATE function [31:16] get_31_16 /* verilator isolate_assignments*/; input [31:0] t_crc /* verilator isolate_assignments*/; get_31_16 = t_crc[31:16]; endfunction `else function [31:16] get_31_16; input [31:0] t_crc; get_31_16 = t_crc[31:16]; endfunction `endif task set_b_d; `ifdef ISOLATE input [31:0] t_crc /* verilator isolate_assignments*/; input [31:0] t_c /* verilator isolate_assignments*/; `else input [31:0] t_crc; input [31:0] t_c; `endif begin b = {t_crc[31:16],~t_crc[23:8]}; d = {t_crc[31:16], ~t_c[23:8]}; end endtask always @* begin // Any complicated equation we can't optimize casez (crc[3:0]) 4'b00??: begin c = {b[29:0],2'b11}; end 4'b01??: begin c = {b[30:1],2'b01}; end 4'b10??: begin c = {b[31:2],2'b10}; end 4'b11??: begin c = {b[31:2],2'b00}; end endcase end endmodule verilator-4.038/test_regress/t/t_fuzz_eqne_bad.out0000664000177100017500000000041113702133370022353 0ustar wsnyderwsnyder%Error: t/t_fuzz_eqne_bad.v:12:23: Slice operator VARREF 't.b' on non-slicable (e.g. non-vector) right-hand-side operand : ... In instance t.b 12 | initial c = (a != &b); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_math_eq.v0000664000177100017500000000416713702133370020627 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[3:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'h1a0d07009b6a30d2 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output [3:0] out; assign out[0] = in[3:0] ==? 4'b1001; assign out[1] = in[3:0] !=? 4'b1001; assign out[2] = in[3:0] ==? 4'bx01x; assign out[3] = in[3:0] !=? 4'bx01x; wire signed [3:0] ins = in[3:0]; wire signed [3:0] outs; assign outs[0] = ins ==? 4'sb1001; assign outs[1] = ins !=? 4'sb1001; assign outs[2] = ins ==? 4'sbx01x; assign outs[3] = ins !=? 4'sbx01x; always_comb if (out != outs) $stop; endmodule verilator-4.038/test_regress/t/t_sv_conditional.pl0000775000177100017500000000105313702133370022364 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_multitop1.pl0000775000177100017500000000142313702133370021310 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( ); execute( check_finished => 0, ); # Order of lines is unspecified, so don't use a golden file file_grep($Self->{run_log_filename}, qr!In 'top.t'!); file_grep($Self->{run_log_filename}, qr!In 'top.t.s'!); file_grep_not($Self->{run_log_filename}, qr!in_subfile!); ok(1); 1; verilator-4.038/test_regress/t/t_func_const_struct_bad.out0000664000177100017500000000155513702133370024124 0ustar wsnyderwsnyder%Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_struct_bad.v:17:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t t/t_func_const_struct_bad.v:28:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_struct_bad.v:38:16: ... Called from f_add() with parameters: params = '{a: 32'h7, b: 32'h8} t/t_func_const_struct_bad.v:17:21: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 17 | localparam P24 = f_add2(7, 8, 9); | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_bench_mux4k_onecpu.pl0000775000177100017500000000147013702133367023142 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_bench_mux4k.v"); compile( v_flags2 => ["--stats", $Self->wno_unopthreads_for_few_cores()] ); if (`numactl --show` !~ /cpu/) { skip("No numactl available"); } else { execute( run_env => 'numactl -m 0 -C 0,0,0,0,0,0,0,0', check_finished => 1, ); ok(1); } 1; verilator-4.038/test_regress/t/t_flag_errorlimit_bad.v0000664000177100017500000000050713702133370023172 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); int u1; int u1; int u1; int u1; int u1; int u1; int u1; endmodule verilator-4.038/test_regress/t/t_unbounded.v0000664000177100017500000000121013702133370021156 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(); localparam UNB = $; localparam int UNB2 = $; localparam SIX = 6; initial begin if ($bits($isunbounded(0)) !== 1) $stop; if ($isunbounded(0) !== 1'b0) $stop; if ($isunbounded(SIX) !== 0) $stop; if ($isunbounded($) !== 1) $stop; if ($isunbounded(UNB) !== 1) $stop; if ($isunbounded(UNB2) !== 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_clk_concat4.v0000664000177100017500000000347413702133367021403 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input wrclk ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (wrclk) some_other_state <= 0; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); generate genvar i; for (i = 0; i < 2; i = i + 1) begin: a_generate_block some_module some_module ( `ifdef BROKEN .wrclk (i_clks[3]) `else .wrclk (i_clk1) `endif ); end endgenerate endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; assign the_clks[3] = i_clk1; assign the_clks[2] = i_clk2; assign the_clks[1] = i_clk1; assign the_clks[0] = i_clk0; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk1), .i_clk2 (clk2), .i_data (data_in) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_xml_flat.pl0000775000177100017500000000142613702133370021163 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2012 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; top_filename("t/t_xml_first.v"); compile( verilator_flags2 => ['--xml-only', '--flatten'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); files_identical("$out_filename", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_fuzz_always_bad.pl0000775000177100017500000000107413702133370022540 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_fuzz_negwidth_bad.out0000664000177100017500000000035413702133370023242 0ustar wsnyderwsnyder%Error: t/t_fuzz_negwidth_bad.v:9:9: Unsupported: Width of number exceeds implementation limit: 1231232312312312'd1 (IEEE 1800-2017 6.9.1) 9 | int c = 1231232312312312'd1; | ^~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_preproc.pl0000775000177100017500000000415313702133370021027 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; compile( verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, stdout_filename => $stdout_filename, ); preproc_check($Self->{top_filename}, $stdout_filename); files_identical($stdout_filename, $Self->{golden_filename}); ok(1); sub preproc_check { my $filename1 = shift; my $filename2 = shift; my @Line_Checks; { # Read line comments. my $fh = IO::File->new($filename1) or die "%Error: $! $filename1\n"; while (defined(my $line = $fh->getline)) { if ($line =~ /^Line_Preproc_Check/) { push @Line_Checks, $.; } } $fh->close; } { # See if output file agrees. my $fh = IO::File->new($filename2) or die "%Error: $! $filename2\n"; my $lineno = 0; while (defined(my $line = $fh->getline)) { $lineno++; if ($line =~ /^\`line\s+(\d+)/) { $lineno = $1 - 1; } if ($line =~ /^Line_Preproc_Check\s+(\d+)/) { my $linecmt = $1; my $check = shift @Line_Checks; if (!$check) { error("$filename2:$.: Extra Line_Preproc_Check\n"); } if ($linecmt != $check) { error("$filename2:$.: __LINE__ inserted $linecmt, exp=$check\n"); } if ($lineno != $check) { error("$filename2:$.: __LINE__ on `line $lineno, exp=$check\n"); } } } $fh->close; } if ($Line_Checks[0]) { error("$filename2: Missing a Line_Preproc_Check\n"); } } 1; verilator-4.038/test_regress/t/t_flag_wfatal.out0000664000177100017500000000056313702133370022016 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_flag_wfatal.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. verilator-4.038/test_regress/t/t_order_wireloop.v0000664000177100017500000000055513702133370022241 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs bar ); wire foo; output bar; // Oh dear. assign foo = bar; assign bar = foo; endmodule verilator-4.038/test_regress/t/t_param_array3.pl0000775000177100017500000000105313702133370021732 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_disabled.pl0000775000177100017500000000105713702133367022513 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_on.v"); compile(); execute(); ok(1); 1; verilator-4.038/test_regress/t/t_param_seg.v0000664000177100017500000000113313702133370021135 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Mandy Xu. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH //bug1088 module t (/*AUTOARG*/ // Outputs err_count, // Inputs clk, syndromes ); input clk; input [7:0] syndromes; output reg [1:0] err_count = 0; localparam [95:0] M = 96'h4; wire [3:0] syn1 = syndromes[0+:M]; always @(posedge clk) begin err_count <= {1'b0, |syn1}; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_type3.v0000664000177100017500000000143313702133370021426 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 typedef logic T_t; module t (/*AUTOARG*/ // Outputs o, o2, // Inputs i ); input T_t i; output T_t o; output T_t o2; sub #(.T_t(T_t)) sub (.i, .o); sub2 #(.T_t(T_t)) sub2 (.i, .o(o2)); endmodule module sub (i,o); parameter type T_t = logic; localparam type T2_t = T_t; input T_t i; output T2_t o; assign o = i; endmodule module sub2 #( parameter type T_t = logic, localparam type T2_t = T_t ) ( input T_t i, output T_t o ); assign o = i; endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-4.038/test_regress/t/t_order_quad.pl0000775000177100017500000000123613702133370021501 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_packed.v0000664000177100017500000001133213702133370021266 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; //Simple debug: //wire [1:1] wir_a [3:3] [2:2]; //11 //logic [1:1] log_a [3:3] [2:2]; //12 //wire [3:3] [2:2] [1:1] wir_p; //13 //logic [3:3] [2:2] [1:1] log_p; //14 integer cyc; initial cyc = 0; `ifdef IVERILOG reg [7:0] arr [3:0]; wire [7:0] arr_w [3:0]; `else reg [3:0] [7:0] arr; wire [3:0] [7:0] arr_w; `endif reg [7:0] sum; reg [7:0] sum_w; integer i0; initial begin for (i0=0; i0<5; i0=i0+1) begin arr[i0] = 1 << (i0[1:0]*2); end end assign arr_w = arr; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup sum <= 0; sum_w <= 0; end else if (cyc >= 10 && cyc < 14) begin sum <= sum + arr[cyc-10]; sum_w <= sum_w + arr_w[cyc-10]; end else if (cyc==99) begin $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum); if (sum != 8'h55) $stop; if (sum != sum_w) $stop; $write("*-* All Finished *-*\n"); $finish; end end // Test ordering of packed dimensions logic [31:0] data_out; logic [31:0] data_out2; logic [0:0] [2:0] [31:0] data_in; logic [31:0] data_in2 [0:0] [2:0]; assign data_out = data_in[0][0] + data_in[0][1] + data_in[0][2]; assign data_out2 = data_in2[0][0] + data_in2[0][1] + data_in2[0][2]; logic [31:0] last_data_out; always @ (posedge clk) begin if (cyc <= 2) begin data_in[0][0] <= 0; data_in[0][1] <= 0; data_in[0][2] <= 0; data_in2[0][0] <= 0; data_in2[0][1] <= 0; data_in2[0][2] <= 0; end else if (cyc > 2 && cyc < 99) begin data_in[0][0] <= data_in[0][0] + 1; data_in[0][1] <= data_in[0][1] + 1; data_in[0][2] <= data_in[0][2] + 1; data_in2[0][0] <= data_in2[0][0] + 1; data_in2[0][1] <= data_in2[0][1] + 1; data_in2[0][2] <= data_in2[0][2] + 1; last_data_out <= data_out; `ifdef TEST_VERBOSE $write("data_out %0x %0x\n", data_out, last_data_out); `endif if (cyc > 4 && data_out != last_data_out + 3) $stop; if (cyc > 4 && data_out != data_out2) $stop; end end // Test for mixed implicit/explicit dimensions and all implicit packed bit [3:0][7:0][1:0] vld [1:0][1:0]; bit [3:0][7:0][1:0] vld2; // There are specific nodes for Or, Xor, Xnor and And logic vld_or; logic vld2_or; assign vld_or = |vld[0][0]; assign vld2_or = |vld2; logic vld_xor; logic vld2_xor; assign vld_xor = ^vld[0][0]; assign vld2_xor = ^vld2; logic vld_xnor; logic vld2_xnor; assign vld_xnor = ~^vld[0][0]; assign vld2_xnor = ~^vld2; logic vld_and; logic vld2_and; assign vld_and = &vld[0][0]; assign vld2_and = &vld2; // Bit reductions should be cloned, other unary operations should clone the // entire assign. bit [3:0][7:0][1:0] not_lhs; bit [3:0][7:0][1:0] not_rhs; assign not_lhs = ~not_rhs; // Test an AstNodeUniop that shouldn't be expanded bit [3:0][7:0][1:0] vld2_inv; assign vld2_inv = ~vld2; initial begin for (int i=0; i<4; i=i+2) begin for (int j=0; j<8; j=j+2) begin vld[0][0][i][j] = 2'b00; vld[0][0][i+1][j+1] = 2'b00; vld2[i][j] = 2'b00; vld2[i+1][j+1] = 2'b00; not_rhs[i][j] = i[1:0]; not_rhs[i+1][j+1] = i[1:0]; end end end logic [3:0] expect_cyc; initial expect_cyc = 'd15; always @(posedge clk) begin expect_cyc <= expect_cyc + 1; for (int i=0; i<4; i=i+1) begin for (int j=0; j<8; j=j+1) begin vld[0][0][i][j] <= vld[0][0][i][j] + 1; vld2[i][j] <= vld2[i][j] + 1; if (not_rhs[i][j] != ~not_lhs[i][j]) $stop; not_rhs[i][j] <= not_rhs[i][j] + 1; end end if (cyc % 8 == 0) begin vld[0][0][0][0] <= vld[0][0][0][0] - 1; vld2[0][0] <= vld2[0][0] - 1; end if (expect_cyc < 8 && !vld_xor) $stop; else if (expect_cyc > 7 && vld_xor) $stop; if (expect_cyc < 8 && vld_xnor) $stop; else if (expect_cyc > 7 && !vld_xnor) $stop; if (expect_cyc == 15 && vld_or) $stop; else if (expect_cyc == 11 && vld_or) $stop; else if (expect_cyc != 15 && expect_cyc != 11 && !vld_or) $stop; if (expect_cyc == 10 && !vld_and) $stop; else if (expect_cyc == 14 && !vld_and) $stop; else if (expect_cyc != 10 && expect_cyc != 14 && vld_and) $stop; if (vld_xor != vld2_xor) $stop; if (vld_xnor != vld2_xnor) $stop; if (vld_or != vld2_or) $stop; if (vld_and != vld2_and) $stop; end endmodule verilator-4.038/test_regress/t/t_param_wide_io.pl0000775000177100017500000000101613702133370022147 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); #execute(); ok(1); 1; verilator-4.038/test_regress/t/t_func_dotted_inl0.pl0000775000177100017500000000223113702133370022570 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_func_dotted.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( v_flags2 => ['+define+ATTRIBUTES', '+define+NOUSE_INLINE',], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_public.pl0000775000177100017500000000135313702133370021656 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if ($Self->{vlt_all}) { compile( verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], make_top_shell => 0, make_main => 0, ); } else { compile( ); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_type2.v0000664000177100017500000000117413702133370021427 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 package tt_pkg; typedef enum logic [1:0] {L0, L1, L2, L3} test_t; endpackage module t (/*AUTOARG*/ // Outputs ob ); output [1:0] ob; import tt_pkg::*; test_t a; test_t b; assign a = L0; assign ob = b; tt_buf #(.T_t(test_t)) u_test (.i(a), .o(b)); endmodule module tt_buf #( parameter type T_t = logic [0:0] ) ( input T_t i, output T_t o ); assign o = i; endmodule verilator-4.038/test_regress/t/t_unroll_genf.v0000664000177100017500000000104413702133370021512 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug830 module sub(); endmodule function integer cdiv(input integer x); begin cdiv = 10; end endfunction module t (/*AUTOARG*/); genvar j; generate for (j = 0; j < cdiv(10); j=j+1) sub sub(); endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_gen3.pl0000775000177100017500000000106013702133370022223 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_gate.v0000664000177100017500000000220313702133370020774 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module top (input SEL, input[1:0] A, output W, output X, output Y, output Z); mux mux2 (.A(A), .SEL(SEL), .Z(W)); pass mux1 (.A(A), .SEL(SEL), .Z(X)); tbuf mux0[1:0] (.A(A), .OE({SEL,!SEL}), .Z(Y)); assign Z = ( SEL) ? A[1] : 1'bz; tbuf tbuf (.A(A[0]), .OE(!SEL), .Z(Z)); endmodule module pass (input[1:0] A, input SEL, output Z); tbuf tbuf1 (.A(A[1]), .OE(SEL), .Z(Z)); tbuf tbuf0 (.A(A[0]), .OE(!SEL),.Z(Z)); endmodule module tbuf (input A, input OE, output Z); `ifdef T_BUFIF0 bufif0 (Z, A, !OE); `elsif T_BUFIF1 bufif1 (Z, A, OE); `elsif T_NOTIF0 notif0 (Z, !A, !OE); `elsif T_NOTIF1 notif1 (Z, !A, OE); `elsif T_PMOS pmos (Z, A, !OE); `elsif T_NMOS nmos (Z, A, OE); `elsif T_COND assign Z = (OE) ? A : 1'bz; `else `error "Unknown test name" `endif endmodule module mux (input[1:0] A, input SEL, output Z); assign Z = (SEL) ? A[1] : 1'bz; assign Z = (!SEL)? A[0] : 1'bz; assign Z = 1'bz; endmodule verilator-4.038/test_regress/t/t_var_dup2_bad.v0000664000177100017500000000054513702133370021535 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Illegal with ANSI Verilog 2001 style ports module t ( output bad_o_w, output bad_o_r); wire bad_o_w; reg bad_o_r; endmodule verilator-4.038/test_regress/t/t_time_sc_ns.out0000664000177100017500000000013013702133370021660 0ustar wsnyderwsnyderTime scale of t is 1ns / 1ns [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-4.038/test_regress/t/t_lint_literal_bad.pl0000775000177100017500000000107113702133370022641 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2017 by Todd Strader. This program is free software; you # can predistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_rand_seed.out0000664000177100017500000000061313702133370022365 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_sys_rand_seed.v:13:16: Unsupported: Seed on $random. Suggest use +verilator+seed+ runtime flag 13 | valuea = $random(10); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_rand_seed.v:14:16: Unsupported: Seed on $random. Suggest use +verilator+seed+ runtime flag 14 | valueb = $random(10); | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_math_divw.v0000664000177100017500000001372113702133370021167 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off WIDTH //============================================================ reg bad; initial begin bad=0; c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0); c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0); c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0); c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888); c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0); c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888); c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0); c96(96'h0003, 96'h0002, 96'h0001, 96'h0001); c96(96'h0003, 96'h0003, 96'h0001, 96'h0000); c96(96'h0003, 96'h0004, 96'h0000, 96'h0003); c96(96'h0000, 96'hffff, 96'h0000, 96'h0000); c96(96'hffff, 96'h0001, 96'hffff, 96'h0000); c96(96'hffff, 96'hffff, 96'h0001, 96'h0000); c96(96'hffff, 96'h0003, 96'h5555, 96'h0000); c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000); c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000); c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe); c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70); c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000); c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000); c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005); c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000); c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001); c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000); c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001); c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899); c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000); c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff); c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab); c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff); c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000); c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000); c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000); c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000); c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000); c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000); c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000); c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000); c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000); c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000); c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000); c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000); c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000); c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002); c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff); c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888); if (bad) $stop; $write("*-* All Finished *-*\n"); $finish; end task c96; input [95:0] u; input [95:0] v; input [95:0] expq; input [95:0] expr; c96u( u, v, expq, expr); c96s( u, v, expq, expr); c96s(-u, v,-expq,-expr); c96s( u,-v,-expq, expr); c96s(-u,-v, expq,-expr); endtask task c96u; input [95:0] u; input [95:0] v; input [95:0] expq; input [95:0] expr; reg [95:0] gotq; reg [95:0] gotr; gotq = u/v; gotr = u%v; if (gotq != expq && v!=0) begin bad = 1; end if (gotr != expr && v!=0) begin bad = 1; end if (bad `ifdef TEST_VERBOSE || 1 `endif ) begin $write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); // Test for v=0 to prevent Xs causing grief if (gotq != expq && v!=0) $write(" BADQ"); if (gotr != expr && v!=0) $write(" BADR"); $write("\n"); end endtask task c96s; input signed [95:0] u; input signed [95:0] v; input signed [95:0] expq; input signed [95:0] expr; reg signed [95:0] gotq; reg signed [95:0] gotr; gotq = u/v; gotr = u%v; if (gotq != expq && v!=0) begin bad = 1; end if (gotr != expr && v!=0) begin bad = 1; end if (bad `ifdef TEST_VERBOSE || 1 `endif ) begin $write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); // Test for v=0 to prevent Xs causing grief if (gotq != expq && v!=0) $write(" BADQ"); if (gotr != expr && v!=0) $write(" BADR"); $write("\n"); end endtask endmodule verilator-4.038/test_regress/t/t_func_real_param.pl0000775000177100017500000000105313702133370022467 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_xml_tag.v0000664000177100017500000000332413702133370020636 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Chris Randall. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; modport out_modport (output value); endinterface module m ( input clk_ip, // verilator tag clk_ip input rst_ip, output foo_op); // verilator tag foo_op // This is a comment typedef struct packed { logic clk; /* verilator tag this is clk */ logic k; /* verilator lint_off UNUSED */ logic enable; // verilator tag enable logic data; // verilator tag data } my_struct; // verilator tag my_struct // This is a comment ifc itop(); my_struct this_struct [2]; // verilator tag this_struct wire [31:0] dotted = itop.value; function f(input string m); $display("%s", m); endfunction initial begin // Contains all 256 characters except 0 (null character) f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"); end endmodule verilator-4.038/test_regress/t/t_class_method.pl0000775000177100017500000000105313702133367022024 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_modport_noinl.pl0000775000177100017500000000116313702133370024256 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_modport.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen4_noinl.pl0000775000177100017500000000116013702133370023424 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen4.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_detectarray_1.v0000664000177100017500000000132113702133370021725 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Simple test of unoptflat // // Trigger the DETECTARRAY error. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { logic [ID_MSB:0] id; } context_t; context_t tsb; assign tsb.id = {tsb.id[0], clk}; initial begin tsb.id = 0; end always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("tsb.id = %x\n", tsb.id); `endif if (tsb.id[1] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_for_comma_bad.pl0000775000177100017500000000107413702133370022124 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_huge.v0000664000177100017500000001605613702133367021142 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [9:0] index; wire [7:0] index0 = index[7:0] + 8'h0; wire [7:0] index1 = index[7:0] + 8'h1; wire [7:0] index2 = index[7:0] + 8'h2; wire [7:0] index3 = index[7:0] + 8'h3; wire [7:0] index4 = index[7:0] + 8'h4; wire [7:0] index5 = index[7:0] + 8'h5; wire [7:0] index6 = index[7:0] + 8'h6; wire [7:0] index7 = index[7:0] + 8'h7; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [9:0] outa0; // From s0 of t_case_huge_sub.v wire [9:0] outa1; // From s1 of t_case_huge_sub.v wire [9:0] outa2; // From s2 of t_case_huge_sub.v wire [9:0] outa3; // From s3 of t_case_huge_sub.v wire [9:0] outa4; // From s4 of t_case_huge_sub.v wire [9:0] outa5; // From s5 of t_case_huge_sub.v wire [9:0] outa6; // From s6 of t_case_huge_sub.v wire [9:0] outa7; // From s7 of t_case_huge_sub.v wire [1:0] outb0; // From s0 of t_case_huge_sub.v wire [1:0] outb1; // From s1 of t_case_huge_sub.v wire [1:0] outb2; // From s2 of t_case_huge_sub.v wire [1:0] outb3; // From s3 of t_case_huge_sub.v wire [1:0] outb4; // From s4 of t_case_huge_sub.v wire [1:0] outb5; // From s5 of t_case_huge_sub.v wire [1:0] outb6; // From s6 of t_case_huge_sub.v wire [1:0] outb7; // From s7 of t_case_huge_sub.v wire outc0; // From s0 of t_case_huge_sub.v wire outc1; // From s1 of t_case_huge_sub.v wire outc2; // From s2 of t_case_huge_sub.v wire outc3; // From s3 of t_case_huge_sub.v wire outc4; // From s4 of t_case_huge_sub.v wire outc5; // From s5 of t_case_huge_sub.v wire outc6; // From s6 of t_case_huge_sub.v wire outc7; // From s7 of t_case_huge_sub.v wire [9:0] outq; // From q of t_case_huge_sub4.v wire [3:0] outr; // From sub3 of t_case_huge_sub3.v wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v // End of automatics t_case_huge_sub2 sub2 ( // Outputs .outa (outsmall[9:0]), /*AUTOINST*/ // Inputs .index (index[9:0])); t_case_huge_sub3 sub3 (/*AUTOINST*/ // Outputs .outr (outr[3:0]), // Inputs .clk (clk), .index (index[9:0])); /* t_case_huge_sub AUTO_TEMPLATE ( .outa (outa@[]), .outb (outb@[]), .outc (outc@[]), .index (index@[])); */ t_case_huge_sub s0 (/*AUTOINST*/ // Outputs .outa (outa0[9:0]), // Templated .outb (outb0[1:0]), // Templated .outc (outc0), // Templated // Inputs .index (index0[7:0])); // Templated t_case_huge_sub s1 (/*AUTOINST*/ // Outputs .outa (outa1[9:0]), // Templated .outb (outb1[1:0]), // Templated .outc (outc1), // Templated // Inputs .index (index1[7:0])); // Templated t_case_huge_sub s2 (/*AUTOINST*/ // Outputs .outa (outa2[9:0]), // Templated .outb (outb2[1:0]), // Templated .outc (outc2), // Templated // Inputs .index (index2[7:0])); // Templated t_case_huge_sub s3 (/*AUTOINST*/ // Outputs .outa (outa3[9:0]), // Templated .outb (outb3[1:0]), // Templated .outc (outc3), // Templated // Inputs .index (index3[7:0])); // Templated t_case_huge_sub s4 (/*AUTOINST*/ // Outputs .outa (outa4[9:0]), // Templated .outb (outb4[1:0]), // Templated .outc (outc4), // Templated // Inputs .index (index4[7:0])); // Templated t_case_huge_sub s5 (/*AUTOINST*/ // Outputs .outa (outa5[9:0]), // Templated .outb (outb5[1:0]), // Templated .outc (outc5), // Templated // Inputs .index (index5[7:0])); // Templated t_case_huge_sub s6 (/*AUTOINST*/ // Outputs .outa (outa6[9:0]), // Templated .outb (outb6[1:0]), // Templated .outc (outc6), // Templated // Inputs .index (index6[7:0])); // Templated t_case_huge_sub s7 (/*AUTOINST*/ // Outputs .outa (outa7[9:0]), // Templated .outb (outb7[1:0]), // Templated .outc (outc7), // Templated // Inputs .index (index7[7:0])); // Templated t_case_huge_sub4 q (/*AUTOINST*/ // Outputs .outq (outq[9:0]), // Inputs .index (index[7:0])); integer cyc; initial cyc=1; initial index = 10'h0; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%x: %x\n",cyc,outr); //$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1); if (cyc==1) begin index <= 10'h236; end if (cyc==2) begin index <= 10'h022; if (outsmall != 10'h282) $stop; if (outr != 4'b0) $stop; if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop; if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop; if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop; if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop; if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop; if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop; if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop; if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop; if (outq != 10'h001) $stop; end if (cyc==3) begin index <= 10'h165; if (outsmall != 10'h191) $stop; if (outr != 4'h5) $stop; if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop; if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop; if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop; if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop; if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop; if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop; if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop; if (outq != 10'h001) $stop; end if (cyc==4) begin index <= 10'h201; if (outsmall != 10'h268) $stop; if (outr != 4'h2) $stop; if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop; if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop; if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop; if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop; if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop; if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop; if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop; if (outq != 10'h001) $stop; end if (cyc==5) begin index <= 10'h3ff; if (outr != 4'hd) $stop; if (outq != 10'h001) $stop; end if (cyc==6) begin index <= 10'h0; if (outr != 4'hd) $stop; if (outq != 10'h114) $stop; end if (cyc==7) begin if (outr != 4'h4) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_split_var_0.vlt0000664000177100017500000000041213702133370021760 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Marco Widmer. // SPDX-License-Identifier: CC0-1.0 `verilator_config split_var -module "barshift_1d_unpacked" -var "tmp" verilator-4.038/test_regress/t/t_interface_modport_dir_bad.v0000664000177100017500000000234213702133370024352 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi // SPDX-License-Identifier: CC0-1.0 interface validData ( input wire clk, input wire rst ); logic data; logic valid; modport sink ( input data, valid, clk, rst ); modport source ( input clk, rst, output data, valid ); endinterface module sinkMod ( validData.sink ctrl, output logic valid_data ); always_ff @(posedge ctrl.clk) begin if (ctrl.valid) valid_data <= ctrl.data; end endmodule module sourceMod ( validData.source ctrl ); always_ff @(posedge ctrl.clk) begin ctrl.data <= ~ctrl.data; ctrl.valid <= ~ctrl.valid; end endmodule module parentSourceMod ( validData.sink ctrl ); sourceMod source_i (.ctrl); endmodule module t (/*AUTOARG*/ // Outputs data, // Inputs clk, rst ); input clk; input rst; output logic data; validData ctrl(.clk, .rst); sinkMod sink_i (.ctrl, .valid_data(data)); parentSourceMod source_i (.ctrl); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_vcmarker_bad.pl0000775000177100017500000000107613702133370023024 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_semaphore_parse.pl0000775000177100017500000000111013702133370022520 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t_semaphore.v"); lint( verilator_flags2 => ["--debug-exit-parse"], ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_array_connect.pl0000775000177100017500000000105313702133370023235 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_import_name_bad.out0000664000177100017500000000023013702133370023704 0ustar wsnyderwsnyder%Error: t/t_lint_import_name_bad.v:11:12: Import object not found: 'defs::sigs' 11 | import defs::sigs; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_block_redecl_bad.pl0000775000177100017500000000130513702133370023615 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug485, false begin due to WHILE conversion blocks duplicate name detection"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_types_bad.pl0000775000177100017500000000124013702133370022171 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); $Self->{verilated_randReset} = 1; # allow checking if we initialize vars to zero only when needed lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_check.v0000664000177100017500000000272313702133370021275 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH // verilator lint_off VARHIDDEN module t ( clk ); input clk; integer cyc=0; reg [63:0] crc; initial crc = 64'h1; chk chk (.clk (clk), .rst_l (1'b1), .expr (|crc) ); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==0) begin crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module chk (input clk, input rst_l, input expr); integer errors; initial errors = 0; task printerr; input [8*64:1] msg; begin errors = errors + 1; $write("%%Error: %0s\n", msg); $stop; end endtask always @(posedge clk) begin if (rst_l) begin if (expr == 1'b0) begin printerr("expr not asserted"); end end end wire noxs = ((expr ^ expr) == 1'b0); reg hasx; always @ (noxs) begin if (noxs) begin hasx = 1'b0; end else begin hasx = 1'b1; end end always @(posedge clk) begin if (rst_l) begin if (hasx) begin printerr("expr has unknowns"); end end end endmodule verilator-4.038/test_regress/t/t_var_bad_hide2.v0000664000177100017500000000076313702133370021660 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Arguable, but we won't throw a hidden warning on tcp_port parameter tcp_port = 5678; import "DPI-C" function int dpii_func ( input integer tcp_port, output longint obj ); // 't' is hidden: integer t; endmodule verilator-4.038/test_regress/t/t_interface_gen3_noinl.pl0000775000177100017500000000116013702133370023423 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen3.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_timescale_parse.cpp0000664000177100017500000000062513702133370022661 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Wilson Snyder #include "Vt_timescale_parse.h" VM_PREFIX* tb = NULL; double sc_time_stamp() { return 2 * 1e9; // e.g. 2 seconds in ns units } int main() { tb = new VM_PREFIX("tb"); tb->eval(); tb->eval(); tb->eval(); tb->final(); } verilator-4.038/test_regress/t/t_lint_incabspath.v0000664000177100017500000000040013702133370022335 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "/dev/null" module t; endmodule verilator-4.038/test_regress/t/t_altera_lpm_divide.pl0000775000177100017500000000120613702133367023023 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc.out0000664000177100017500000003061513702133370021222 0ustar wsnyderwsnyder`line 1 "t/t_preproc.v" 1 `line 6 "t/t_preproc.v" 0 `line 8 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 `line 2 "t/t_preproc_inc2.vh" 0 At file "t/t_preproc_inc2.vh" line 5 `line 7 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 `line 2 "inc3_a_filename_from_line_directive" 0 `line 7 "inc3_a_filename_from_line_directive" 0 At file "inc3_a_filename_from_line_directive" line 11 `line 13 "inc3_a_filename_from_line_directive" 0 `line 16 "inc3_a_filename_from_line_directive" 0 `line 20 "inc3_a_filename_from_line_directive" 2 `line 7 "t/t_preproc_inc2.vh" 0 `line 9 "t/t_preproc_inc2.vh" 2 `line 8 "t/t_preproc.v" 0 `line 10 "t/t_preproc.v" 0 `line 13 "t/t_preproc.v" 0 /*verilator pass_thru comment*/ `line 15 "t/t_preproc.v" 0 /*verilator pass_thru_comment2*/ `line 17 "t/t_preproc.v" 0 `line 20 "t/t_preproc.v" 0 wire [3:0] q = { 1'b1 , 1'b0 , 1'b1 , 1'b1 }; `line 30 "t/t_preproc.v" 0 text. `line 32 "t/t_preproc.v" 0 foo bar foobar2 `line 37 "t/t_preproc.v" 0 `line 41 "t/t_preproc.v" 0 `line 46 "t/t_preproc.v" 0 first part `line 47 "t/t_preproc.v" 0 second part `line 47 "t/t_preproc.v" 0 third part { `line 48 "t/t_preproc.v" 0 a, `line 48 "t/t_preproc.v" 0 b, `line 48 "t/t_preproc.v" 0 c} Line_Preproc_Check 49 `line 51 "t/t_preproc.v" 0 `line 53 "t/t_preproc.v" 0 `line 55 "t/t_preproc.v" 0 deep deep `line 59 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" `line 64 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s `line 70 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line `line 72 "t/t_preproc.v" 0 x y LLZZ "x" y `line 75 "t/t_preproc.v" 0 (a,b)(a,b) `line 78 "t/t_preproc.v" 0 $display("left side: \"right side\"") `line 81 "t/t_preproc.v" 0 bar_suffix more `line 84 "t/t_preproc.v" 0 `line 86 "t/t_preproc.v" 0 $c("Zap(\"",bug1,"\");");; `line 87 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; `line 89 "t/t_preproc.v" 0 `line 92 "t/t_preproc.v" 0 `line 95 "t/t_preproc.v" 0 initial begin $display("pre thrupre thrumid thrupost post: \"right side\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("left_side: \"right_side\""); $display("na: \"right_side\""); $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); $display("na: \"nana\""); $display("left_side right_side: \"left_side right_side\""); $display(": \"\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("standalone"); `line 116 "t/t_preproc.v" 0 $display("twoline: \"first second\""); $write("*-* All Finished *-*\n"); $finish; end endmodule `line 126 "t/t_preproc.v" 0 `line 129 "t/t_preproc.v" 0 `line 134 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); `line 135 "t/t_preproc.v" 0 wire tmp_d1 = d1; `line 135 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; `line 135 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; endmodule module add2 ( input wire d2, output wire o2); `line 138 "t/t_preproc.v" 0 wire tmp_d2 = d2; `line 138 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; `line 138 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; endmodule `line 141 "t/t_preproc.v" 0 `line 147 "t/t_preproc.v" 0 `line 152 "t/t_preproc.v" 0 `line 152 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin `line 152 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; `line 152 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; `line 152 "t/t_preproc.v" 0 end endgenerate `line 154 "t/t_preproc.v" 0 module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `line 160 "t/t_preproc.v" 0 `endprotected endmodule `line 164 "t/t_preproc.v" 0 `line 174 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 178 "t/t_preproc.v" 0 `line 181 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 2 `line 181 "t/t_preproc.v" 0 `line 182 "t/t_preproc.v" 0 `line 185 "t/t_preproc.v" 0 `line 187 "t/t_preproc.v" 0 `line 191 "t/t_preproc.v" 0 `line 194 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); `line 200 "t/t_preproc.v" 0 `line 203 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire `line 207 "t/t_preproc.v" 0 `line 210 "t/t_preproc.v" 0 `line 214 "t/t_preproc.v" 0 Line_Preproc_Check 214 `line 216 "t/t_preproc.v" 0 `line 219 "t/t_preproc.v" 0 (p,q) `line 226 "t/t_preproc.v" 0 (x,y) Line_Preproc_Check 227 `line 229 "t/t_preproc.v" 0 `line 232 "t/t_preproc.v" 0 beginend beginend "beginend" `line 240 "t/t_preproc.v" 0 `\esc`def `line 246 "t/t_preproc.v" 0 Not a \`define `line 248 "t/t_preproc.v" 0 x,y)--bee submacro has comma paren `line 256 "t/t_preproc.v" 0 $display("10 %d %d", $bits(foo), 10); `line 261 "t/t_preproc.v" 0 `line 266 "t/t_preproc.v" 0 `line 269 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 assign a3 = ~b3 ; `line 283 "t/t_preproc.v" 0 `line 285 "t/t_preproc.v" 0 \ `line 294 "t/t_preproc.v" 0 `line 294 "t/t_preproc.v" 0 `line 294 "t/t_preproc.v" 0 def i `line 296 "t/t_preproc.v" 0 `line 298 "t/t_preproc.v" 0 `line 302 "t/t_preproc.v" 0 `line 308 "t/t_preproc.v" 0 1 /*verilator NOT IN DEFINE*/ (nodef) 2 /*verilator PART OF DEFINE*/ (hasdef) 3 `line 310 "t/t_preproc.v" 0 /*verilator NOT PART OF DEFINE*/ (nodef) `line 311 "t/t_preproc.v" 0 4 `line 311 "t/t_preproc.v" 0 /*verilator PART OF DEFINE*/ (nodef) `line 312 "t/t_preproc.v" 0 5 also in `line 312 "t/t_preproc.v" 0 also3 (nodef) HAS a NEW `line 315 "t/t_preproc.v" 0 LINE `line 317 "t/t_preproc.v" 0 `line 319 "t/t_preproc.v" 0 `line 332 "t/t_preproc.v" 0 `line 335 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen "clxx_scen" EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `line 341 "t/t_preproc.v" 0 do `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 if (start("t/t_preproc.v", 341)) begin `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); `line 341 "t/t_preproc.v" 0 end `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 while(0); `line 343 "t/t_preproc.v" 0 `line 345 "t/t_preproc.v" 0 `line 349 "t/t_preproc.v" 0 `line 349 "t/t_preproc.v" 0 `line 350 "t/t_preproc.v" 0 EXP: This is fooed This is fooed EXP: This is fooed_2 This is fooed_2 `line 357 "t/t_preproc.v" 0 np np `line 368 "t/t_preproc.v" 0 `line 371 "t/t_preproc.v" 0 `line 379 "t/t_preproc.v" 0 `line 383 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 `line 389 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 2 `line 389 "t/t_preproc.v" 0 `line 390 "t/t_preproc.v" 0 `line 398 "t/t_preproc.v" 0 Line_Preproc_Check 402 Line_Preproc_Check 408 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " `line 411 "t/t_preproc.v" 0 Line_Preproc_Check 411 `line 415 "t/t_preproc.v" 0 abc `line 425 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame `line 431 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame EXP: sonet_frame sonet_frame `line 441 "t/t_preproc.v" 0 EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule `line 448 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule `line 453 "t/t_preproc.v" 0 integer foo; module t; initial begin : \`LEX_CAT(a[0],_assignment) `line 465 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end initial begin : \a[0]_assignment_a[1] `line 472 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end initial begin : \`CAT(ff,bb) `line 486 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end initial begin : \`zzz `line 492 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end initial begin : \`FOO `line 499 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end initial begin : \xx`FOO `line 501 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz"); initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz"); initial $write("Slashed=`%s'\n", "1//2.3"); initial `line 532 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule `line 535 "t/t_preproc.v" 0 `line 538 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); `line 543 "t/t_preproc.v" 0 `line 548 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ $display("XXE_ is defined"); `line 555 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ $display("XYE_ is defined"); `line 562 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some $display("XXS_some is defined"); `line 569 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); `line 576 "t/t_preproc.v" 0 `line 578 "t/t_preproc.v" 0 `line 586 "t/t_preproc.v" 0 `line 593 "t/t_preproc.v" 0 `line 600 "t/t_preproc.v" 0 `line 607 "t/t_preproc.v" 0 `line 609 "t/t_preproc.v" 0 `line 611 "t/t_preproc.v" 0 (.mySig (myInterface.pa5), `line 615 "t/t_preproc.v" 0 `line 618 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); `line 621 "t/t_preproc.v" 0 `line 629 "t/t_preproc.v" 0 module pcc2_cfg; generate `line 631 "t/t_preproc.v" 0 covergroup a @(posedge b); `line 631 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup `line 631 "t/t_preproc.v" 0 a u_a; `line 631 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule `line 635 "t/t_preproc.v" 0 predef 0 0 predef 1 1 predef 2 2 predef 3 3 predef 10 10 predef 11 11 predef 20 20 predef 21 21 predef 22 22 predef 23 23 predef -2 -2 predef -1 -1 predef 0 0 predef 1 1 predef 2 2 `line 657 "t/t_preproc.v" 2 verilator-4.038/test_regress/t/t_gate_basic.v0000664000177100017500000000377313702133370021274 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] a; reg [31:0] b; wire [2:0] bf; buf BF0 (bf[0], a[0]), BF1 (bf[1], a[1]), BF2 (bf[2], a[2]); // verilator lint_off IMPLICIT not #(0.108) NT0 (nt0, a[0]); and #1 AN0 (an0, a[0], b[0]); nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); or OR0 (or0, a[0], b[0]); nor NR0 (nr0, a[0], b[0], b[2]); xor (xo0, a[0], b[0]); xnor (xn0, a[0], b[0], b[2]); // verilator lint_on IMPLICIT parameter BITS=32; wire [BITS-1:0] ba; buf BARRAY [BITS-1:0] (ba, a); `ifdef verilator specify specparam CDS_LIBNAME = "foobar"; (nt0 *> nt0) = (0, 0); endspecify specify // delay parameters specparam a$A1$Y = 1.0, b$A0$Z = 1.0; // path delays (A1 *> Q) = (a$A1$Y, a$A1$Y); (A0 *> Q) = (b$A0$Y, a$A0$Z); endspecify `endif always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 32'h18f6b034; b <= 32'h834bf892; end if (cyc==2) begin a <= 32'h529ab56f; b <= 32'h7835a237; if (bf !== 3'b100) $stop; if (nt0 !== 1'b1) $stop; if (an0 !== 1'b0) $stop; if (nd0 !== 1'b1) $stop; if (or0 !== 1'b0) $stop; if (nr0 !== 1'b1) $stop; if (xo0 !== 1'b0) $stop; if (xn0 !== 1'b1) $stop; if (ba != 32'h18f6b034) $stop; end if (cyc==3) begin if (bf !== 3'b111) $stop; if (nt0 !== 1'b0) $stop; if (an0 !== 1'b1) $stop; if (nd0 !== 1'b0) $stop; if (or0 !== 1'b1) $stop; if (nr0 !== 1'b0) $stop; if (xo0 !== 1'b0) $stop; if (xn0 !== 1'b0) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_struct_genfor.v0000664000177100017500000000120113702133370022057 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); for (genvar g = 0; g < 2; ++g) begin : genfor typedef struct packed { logic [31:0] val1; logic [31:0] val2; } struct_t; struct_t forvar; initial begin forvar.val1 = 1; forvar.val2 = 2; if (forvar.val1 != 1) $stop; if (forvar.val2 != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_arraysel_wide.v0000664000177100017500000000121613702133367022041 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs nnext, // Inputs inibble, onibble ); input [3:0] inibble; input [106:0] onibble; output reg [3:0] nnext [0:7]; // verilator lint_off WIDTH wire [2:0] selline = (onibble >>> 102) & 7; // verilator lint_on WIDTH always_comb begin for (integer i=0; i<8; i=i+1) begin nnext[i] = '0; end nnext[selline] = inibble; end endmodule verilator-4.038/test_regress/t/t_lint_mod_paren_bad.v0000664000177100017500000000052213702133370023000 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Should have been: //module t #( module t ( FOO=1 ) ( output bar ); assign bar = FOO; endmodule verilator-4.038/test_regress/t/t_multitop_sig.v0000664000177100017500000000124313702133370021720 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module a(in, out); input in; output out; assign out = !in; sub sub (); initial $display("In '%m'"); endmodule module b(in, out); input in; output out; assign out = in; sub sub (); initial $display("In '%m'"); endmodule module c(uniq_in, uniq_out); input uniq_in; output uniq_out; assign uniq_out = !uniq_in; sub sub (); initial $display("In '%m'"); endmodule module sub; initial $display("In '%m'"); endmodule verilator-4.038/test_regress/t/t_altera_lpm_rom.pl0000775000177100017500000000120613702133367022354 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_math_countbits_bad.pl0000775000177100017500000000107313702133370023204 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename} ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_memory.pl0000775000177100017500000000163213702133370021542 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); skip("Known compiler limitation") if $Self->cxx_version =~ /\(GCC\) 4.4/; compile( make_top_shell => 0, make_main => 0, make_pli => 1, iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2 => ["+define+USE_VPI_NOT_DPI"], verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_memory.cpp"], ); execute( iv_pli => 1, check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen11.pl0000775000177100017500000000106013702133370022302 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_importstar_bad.pl0000775000177100017500000000117213702133370023413 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_package_enum.pl0000775000177100017500000000105313702133370021770 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_orig.pl0000775000177100017500000000105313702133367021312 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vams_wreal.pl0000775000177100017500000000105313702133370021511 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gate_implicit.pl0000775000177100017500000000105313702133370022163 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_final.v0000664000177100017500000000121513702133370020271 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Charlie Brej. // SPDX-License-Identifier: CC0-1.0 module submodule (); // This bug only appears when not inlining // verilator no_inline_module initial begin $write("d"); end final begin $write("d"); end final ; // Empty test endmodule module t (); generate for (genvar i = 0; i < 100; i = i + 1) begin : module_set submodule u_submodule(); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_semaphore.v0000664000177100017500000000204113702133370021161 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // class semaphore; // function new(int keyCount = 0); // function void put(int keyCount = 1); // task get(int keyCount = 1); // function int try_get(int keyCount = 1); // endclass module t(/*AUTOARG*/); //From UVM: semaphore s; int msg; initial begin s = new(4); if (s.try_get() != 0) $stop; s.put(); s.get(); s.put(2); s.get(2); s.put(2); if (s.try_get(2) <= 0) $stop; fork begin #10; // So later then get() starts below s.put(1); s.put(1); end begin if (s.try_get(1) != 0) $stop; s.get(); // Blocks until put s.get(); end join $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_declfilename_bad.out0000664000177100017500000000044713702133370024014 0ustar wsnyderwsnyder%Warning-DECLFILENAME: t/t_lint_declfilename.v:7:8: Filename 't_lint_declfilename' does not match MODULE name: 't' 7 | module t; | ^ ... Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_flag_getenv.pl0000775000177100017500000000162513702133370021637 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); setenv('FOOBARTEST', "gotit"); run( cmd => ["../bin/verilator --getenv FOOBARTEST"], expect => 'gotit ', logfile => "$Self->{obj_dir}/simx.log", verilator_run => 1, ); foreach my $var (qw(MAKE PERL SYSTEMC SYSTEMC_ARCH SYSTEMC_LIBDIR VERILATOR_ROOT)) { run( cmd => ["../bin/verilator --getenv ${var}"], logfile => "$Self->{obj_dir}/simx.log", verilator_run => 1, ); } ok(1); 1; verilator-4.038/test_regress/t/t_dist_error_format.pl0000775000177100017500000000505513702133370023103 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; scenarios(dist => 1); my $root = ".."; my $Debug; if (!-r "$root/.git") { skip("Not in a git repository"); } else { formats(); } ok(1); # Check all error messages match our standard format # This assumes .out files cover all important errors sub formats { my $files = "../test_regress/t/*.out"; my %warns; my $lnmatch = 0; foreach my $file (glob $files) { my $wholefile = file_contents($file); $file =~ s!.*/!!; if ($wholefile =~ /Exiting due to/ || $wholefile =~ /%(Error|Warning)/) { my $lineno = 0; foreach my $line (split /\n/, $wholefile) { ++$lineno; if ($line =~ /(Error|Warning)/) { # These formats are documented in bin/verilator # Error with fileline # For testing only: we assume no : in filename my $match = $line; $match =~ s/^\[\d+\] //; # Simplify runtime errors if ($match =~ /^%(Error|Warning)(-[A-Z0-9_]+)?: ([^:]+):(\d+):((\d+):)? /) { ++$lnmatch; print "ok-el $file $line\n" if $Self->{verbose}; } # Error no fileline # For testing only: we assume any : is single quoted elsif ($match =~ /^%(Error|Warning)(-[A-Z0-9_]+)?: [^:']+/) { print "ok-en $file $line\n" if $Self->{verbose}; } else { #print "FF $file $line\n"; $warns{$file.":".$lineno} = "Non-standard warning/error: $file:$lineno: $line"; } } } } } $lnmatch or error("Check line number regexp is correct, no matches"); if (keys %warns) { # First warning lists everything as that's shown in the driver summary error($summary." ",join(' ',sort keys %warns)); foreach my $file (sort keys %warns) { error($warns{$file}); } } } 1; verilator-4.038/test_regress/t/t_math_cond_clean.pl0000775000177100017500000000105313702133370022447 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_while.pl0000775000177100017500000000105313702133370021641 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_with_bbox.pl0000775000177100017500000000112413702133370021335 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_with_unsup.v"); lint( verilator_flags => ["--bbox-unsup"], fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gate_implicit.v0000664000177100017500000000352413702133370022017 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire RBL2; // From t of Test.v // End of automatics wire RWL1 = crc[2]; wire RWL2 = crc[3]; Test t (/*AUTOINST*/ // Outputs .RBL2 (RBL2), // Inputs .RWL1 (RWL1), .RWL2 (RWL2)); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, RBL2}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hb6d6b86aa20a882a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( output RBL2, input RWL1, RWL2); // verilator lint_off IMPLICIT not I1 (RWL2_n, RWL2); bufif1 I2 (RBL2, n3, 1'b1); Mxor I3 (n3, RWL1, RWL2_n); // verilator lint_on IMPLICIT endmodule module Mxor (output out, input a, b); assign out = (a ^ b); endmodule verilator-4.038/test_regress/t/t_vlt_warn.v0000664000177100017500000000132213702133370021033 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Try inline config `ifdef verilator `verilator_config lint_off -rule CASEX -file "t/t_vlt_warn.v" `verilog `endif module t; reg width_warn_var_line18 = 2'b11; // Width warning - must be line 18 reg width_warn2_var_line19 = 2'b11; // Width warning - must be line 19 reg width_warn3_var_line20 = 2'b11; // Width warning - must be line 20 initial begin casex (1'b1) 1'b0: $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_gen_index.pl0000775000177100017500000000103213702133370021306 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Compile time only test compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_init.v0000664000177100017500000000660613702133370021560 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; //Several simulators don't support this. //typedef struct pack2; // Forward declaration typedef struct packed { // [3:0] bit b3; bit b2; bit b1; bit b0; } b4_t; typedef struct packed { // [3:0] b4_t x1; b4_t x0; } b4x2_t; typedef union packed { // [3:0] bit [3:0] quad0; b4_t quad1; } q4_t; typedef struct packed { // [5:0] bit msb; q4_t four; bit lsb; } pack2_t; typedef union packed { // [5:0] pack2_t pack2; bit [6:1] pvec; // Vector not allowed in packed structure, per spec: // bit vec[6]; // bit vec2d[2][3]; } pack3_t; const b4_t b4_const_a = '{1'b1, 1'b0, 1'b0, 1'b1}; // Cast to a pattern - note bits are tagged out of order const b4_t b4_const_b = b4_t'{ b1 : 1'b0, b0 : 1'b1, b3 : 1'b1, b2 : 1'b0 }; wire b4_t b4_wire; assign b4_wire = '{1'b1, 1'b0, 1'b1, 1'b0}; pack2_t arr[2]; `ifdef T_STRUCT_INIT_BAD const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1}; `endif initial begin pack3_t tsu; tsu = 6'b110110; // 543210 if (tsu!=6'b110110) $stop; if (tsu[5:4]!=2'b11) $stop; if (tsu[5:4] == tsu[1:0]) $stop; // Not a good extraction test if LSB subtraction doesn't matter if (tsu.pvec!=6'b110110) $stop; if (tsu.pvec[6:5]!=2'b11) $stop; if (tsu.pack2[5:1] != 5'b11011) $stop; if (tsu.pack2.msb != 1'b1) $stop; if (tsu.pack2.lsb != 1'b0) $stop; if (tsu.pack2.four.quad0 != 4'b1011) $stop; if (tsu.pack2.four.quad1.b0 != 1'b1) $stop; if (tsu.pack2.four.quad1.b1 != 1'b1) $stop; if (tsu.pack2.four.quad1.b2 != 1'b0) $stop; if (tsu.pack2.four.quad1.b3 != 1'b1) $stop; // tsu = 1'b0 ? '0 : '{pvec: 6'b101011}; if (tsu!=6'b101011) $stop; // arr[0] = 6'b101010; arr[1] = 6'b010101; if (arr[0].four !== 4'b0101) $stop; if (arr[1].four !== 4'b1010) $stop; // // Initialization begin b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0}; if (q != 4'b1100) $stop; end begin b4_t q = '{3{1'b1}, 1'b0}; if (q != 4'b1110) $stop; end begin b4_t q = '{4{1'b1}}; // Repeats the {} if (q != 4'b1111) $stop; end begin b4x2_t m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}}; if (m != 8'b10011011) $stop; end begin b4_t q = '{default:1'b1}; if (q != 4'b1111) $stop; end begin b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0}; if (q != 4'b1101) $stop; end begin b4_t q = '{b2:1'b0, default:1'b1}; if (q != 4'b1011) $stop; end if (b4_const_a != 4'b1001) $stop; if (b4_const_b != 4'b1001) $stop; if (b4_wire != 4'b1010) $stop; if (pat(4'b1100, 4'b1100)) $stop; if (pat('{1'b1, 1'b0, 1'b1, 1'b1}, 4'b1011)) $stop; $write("*-* All Finished *-*\n"); $finish; end function pat(b4_t in, logic [3:0] cmp); if (in !== cmp) $stop; pat = 1'b0; endfunction endmodule verilator-4.038/test_regress/t/t_interface_bind_public.pl0000775000177100017500000000112013702133370023636 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['-public'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_const_packed_struct_bad.out0000664000177100017500000000166613702133370025436 0ustar wsnyderwsnyder%Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_struct_bad.v:14:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t t/t_func_const_packed_struct_bad.v:25:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_packed_struct_bad.v:33:16: ... Called from f_add() with parameters: params = [0 = '{a: 32'h7, b: 32'h22b}, 1 = '{a: 32'h3039, b: 32'h8}] t/t_func_const_packed_struct_bad.v:14:21: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 14 | localparam P24 = f_add2(7, 8, 9); | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_fst.pl0000775000177100017500000000133113702133370021322 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } scenarios(vlt_all => 1); compile( v_flags2 => ["--trace-fst"], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_interface_nest.v0000664000177100017500000000236713702133370022202 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017. // SPDX-License-Identifier: CC0-1.0 interface if1; integer var1; endinterface interface if2; if1 i1 (); integer var2; endinterface module mod1 ( input clk, input integer modnum, // Don't use parameter, want same module twice for better checking if2 foo ); logic l1, l2; always_ff @(posedge clk) begin if (modnum==1) begin if (foo.i1.var1 != 1) $stop; if (foo.var2 != 2) $stop; end if (modnum==2) begin if (foo.i1.var1 != 1) $stop; if (foo.var2 != 2) $stop; end end endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; if2 i2a (); if2 i2b (); assign i2a.i1.var1 = 1; assign i2a.var2 = 2; assign i2b.i1.var1 = 3; assign i2b.var2 = 4; mod1 mod1a ( .modnum (1), .clk (clk), .foo (i2a) ); mod1 mod1b ( .modnum (2), .clk (clk), .foo (i2a) ); integer cyc = 0; always_ff @(posedge clk) begin cyc <= cyc+1; if (cyc==2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_package.pl0000775000177100017500000000105313702133370020744 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_split_var_3_wreal.pl0000775000177100017500000000135513702133370022775 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--stats'], ); execute( check_finished => 1, ); file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 0); file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 3); ok(1); 1; verilator-4.038/test_regress/t/t_gate_elim.v0000664000177100017500000000432113702133370021127 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg b; wire vconst1 = 1'b0; wire vconst2 = !(vconst1); wire vconst3 = !vconst2; wire vconst = vconst3; wire qa; wire qb; wire qc; wire qd; wire qe; ta ta (.b(b), .vconst(vconst), .q(qa)); tb tb (.clk(clk), .vconst(vconst), .q(qb)); tc tc (.b(b), .vconst(vconst), .q(qc)); td td (.b(b), .vconst(vconst), .q(qd)); te te (.clk(clk), .b(b), .vconst(vconst), .q(qe)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $display("%b",{qa,qb,qc,qd,qe}); `endif if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin b <= 1'b1; end if (cyc==2) begin if (qa!=1'b1) $stop; if (qb!=1'b0) $stop; if (qd!=1'b0) $stop; b <= 1'b0; end if (cyc==3) begin if (qa!=1'b0) $stop; if (qb!=1'b0) $stop; if (qd!=1'b0) $stop; if (qe!=1'b0) $stop; b <= 1'b1; end if (cyc==4) begin if (qa!=1'b1) $stop; if (qb!=1'b0) $stop; if (qd!=1'b0) $stop; if (qe!=1'b1) $stop; b <= 1'b0; end if (cyc==5) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module ta ( input vconst, input b, output reg q); always @ (/*AS*/b or vconst) begin q = vconst | b; end endmodule module tb ( input vconst, input clk, output reg q); always @ (posedge clk) begin q <= vconst; end endmodule module tc ( input vconst, input b, output reg q); always @ (posedge vconst) begin q <= b; $stop; end endmodule module td ( input vconst, input b, output reg q); always @ (/*AS*/vconst) begin q = vconst; end endmodule module te ( input clk, input vconst, input b, output reg q); reg qmid; always @ (posedge vconst or posedge clk) begin qmid <= b; end always @ (posedge clk or posedge vconst) begin q <= qmid; end endmodule verilator-4.038/test_regress/t/t_altera_lpm_abs.pl0000775000177100017500000000120613702133367022324 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_array_packed_write_read.pl0000775000177100017500000000115613702133367024215 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug446"); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_f__3.v0000664000177100017500000000002313343101620020765 0ustar wsnyderwsnyder`define GOT_DEF3 1 verilator-4.038/test_regress/t/t_event_control_unsup.pl0000775000177100017500000000117613702133370023472 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_func_return.v0000664000177100017500000000322613702133370021536 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug420 typedef logic [7-1:0] wb_ind_t; typedef logic [7-1:0] id_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ wire [6:0] out = line_wb_ind( in[6:0] ); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc918fa0aa882a206 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end function wb_ind_t line_wb_ind( id_t id ); if( id[$bits(id_t)-1] == 0 ) return {2'b00, id[$bits(wb_ind_t)-3:0]}; else return {2'b01, id[$bits(wb_ind_t)-3:0]}; endfunction // line_wb_ind endmodule verilator-4.038/test_regress/t/t_sys_fread.pl0000775000177100017500000000163313702133370021334 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; #use Data::Dumper; use strict; use vars qw($Self); scenarios(simulator => 1); sub gen { my $filename = shift; my $fh = IO::File->new(">$filename"); for (my $copy=0; $copy<32; ++$copy) { for (my $i=0; $i<=255; ++$i) { $fh->print(chr($i)); } } } gen("$Self->{obj_dir}/t_sys_fread.mem"); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_abort_fst.out0000664000177100017500000000064613702133370022712 0ustar wsnyderwsnyder$date Wed Jun 10 20:47:01 2020 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var logic 3 " cyc $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b000 " 0! $end #10 1! b001 " #15 0! #20 1! b010 " #25 0! #30 1! b011 " #35 0! #40 1! b100 " #45 0! #50 1! b101 " #55 0! #60 1! b110 " #65 0! #70 1! b111 " #75 0! verilator-4.038/test_regress/t/t_trace_two_hdr_cc.pl0000775000177100017500000000222413702133370022643 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); top_filename("t_trace_two_a.v"); compile( make_main => 0, verilator_make_gmake => 0, top_filename => 't_trace_two_b.v', VM_PREFIX => 'Vt_trace_two_b', verilator_flags2 => ['-trace'], ); compile( make_main => 0, top_filename => 't_trace_two_a.v', make_flags => 'CPPFLAGS_ADD=-DTEST_HDR_TRACE=1', verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } ok(1); 1; verilator-4.038/test_regress/t/t_case_huge_sub2.v0000664000177100017500000002262713702133367022076 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub2 (/*AUTOARG*/ // Outputs outa, // Inputs index ); input [9:0] index; output [9:0] outa; // ============================= /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [9:0] outa; // End of automatics // ============================= // Created from perl // for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); }; always @(/*AS*/index) begin case (index[7:0]) `ifdef VERILATOR // Harder test 8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable `else 8'h00: begin outa = 10'h0; end `endif 8'h01: begin outa = 10'h318; end 8'h02: begin outa = 10'h29f; end 8'h03: begin outa = 10'h392; end 8'h04: begin outa = 10'h1ef; end 8'h05: begin outa = 10'h06c; end 8'h06: begin outa = 10'h29f; end 8'h07: begin outa = 10'h29a; end 8'h08: begin outa = 10'h3ce; end 8'h09: begin outa = 10'h37c; end 8'h0a: begin outa = 10'h058; end 8'h0b: begin outa = 10'h3b2; end 8'h0c: begin outa = 10'h36f; end 8'h0d: begin outa = 10'h2c5; end 8'h0e: begin outa = 10'h23a; end 8'h0f: begin outa = 10'h222; end 8'h10: begin outa = 10'h328; end 8'h11: begin outa = 10'h3c3; end 8'h12: begin outa = 10'h12c; end 8'h13: begin outa = 10'h1d0; end 8'h14: begin outa = 10'h3ff; end 8'h15: begin outa = 10'h115; end 8'h16: begin outa = 10'h3ba; end 8'h17: begin outa = 10'h3ba; end 8'h18: begin outa = 10'h10d; end 8'h19: begin outa = 10'h13b; end 8'h1a: begin outa = 10'h0a0; end 8'h1b: begin outa = 10'h264; end 8'h1c: begin outa = 10'h3a2; end 8'h1d: begin outa = 10'h07c; end 8'h1e: begin outa = 10'h291; end 8'h1f: begin outa = 10'h1d1; end 8'h20: begin outa = 10'h354; end 8'h21: begin outa = 10'h0c0; end 8'h22: begin outa = 10'h191; end 8'h23: begin outa = 10'h379; end 8'h24: begin outa = 10'h073; end 8'h25: begin outa = 10'h2fd; end 8'h26: begin outa = 10'h2e0; end 8'h27: begin outa = 10'h337; end 8'h28: begin outa = 10'h2c7; end 8'h29: begin outa = 10'h19e; end 8'h2a: begin outa = 10'h107; end 8'h2b: begin outa = 10'h06a; end 8'h2c: begin outa = 10'h1c7; end 8'h2d: begin outa = 10'h107; end 8'h2e: begin outa = 10'h0cf; end 8'h2f: begin outa = 10'h009; end 8'h30: begin outa = 10'h09d; end 8'h31: begin outa = 10'h28e; end 8'h32: begin outa = 10'h010; end 8'h33: begin outa = 10'h1e0; end 8'h34: begin outa = 10'h079; end 8'h35: begin outa = 10'h13e; end 8'h36: begin outa = 10'h282; end 8'h37: begin outa = 10'h21c; end 8'h38: begin outa = 10'h148; end 8'h39: begin outa = 10'h3c0; end 8'h3a: begin outa = 10'h176; end 8'h3b: begin outa = 10'h3fc; end 8'h3c: begin outa = 10'h295; end 8'h3d: begin outa = 10'h113; end 8'h3e: begin outa = 10'h354; end 8'h3f: begin outa = 10'h0db; end 8'h40: begin outa = 10'h238; end 8'h41: begin outa = 10'h12b; end 8'h42: begin outa = 10'h1dc; end 8'h43: begin outa = 10'h137; end 8'h44: begin outa = 10'h1e2; end 8'h45: begin outa = 10'h3d5; end 8'h46: begin outa = 10'h30c; end 8'h47: begin outa = 10'h298; end 8'h48: begin outa = 10'h080; end 8'h49: begin outa = 10'h35a; end 8'h4a: begin outa = 10'h01b; end 8'h4b: begin outa = 10'h0a3; end 8'h4c: begin outa = 10'h0b3; end 8'h4d: begin outa = 10'h17a; end 8'h4e: begin outa = 10'h3ae; end 8'h4f: begin outa = 10'h078; end 8'h50: begin outa = 10'h322; end 8'h51: begin outa = 10'h213; end 8'h52: begin outa = 10'h11a; end 8'h53: begin outa = 10'h1a7; end 8'h54: begin outa = 10'h35a; end 8'h55: begin outa = 10'h233; end 8'h56: begin outa = 10'h01d; end 8'h57: begin outa = 10'h2d5; end 8'h58: begin outa = 10'h1a0; end 8'h59: begin outa = 10'h3d0; end 8'h5a: begin outa = 10'h181; end 8'h5b: begin outa = 10'h219; end 8'h5c: begin outa = 10'h26a; end 8'h5d: begin outa = 10'h050; end 8'h5e: begin outa = 10'h189; end 8'h5f: begin outa = 10'h1eb; end 8'h60: begin outa = 10'h224; end 8'h61: begin outa = 10'h2fe; end 8'h62: begin outa = 10'h0ae; end 8'h63: begin outa = 10'h1cd; end 8'h64: begin outa = 10'h273; end 8'h65: begin outa = 10'h268; end 8'h66: begin outa = 10'h111; end 8'h67: begin outa = 10'h1f9; end 8'h68: begin outa = 10'h232; end 8'h69: begin outa = 10'h255; end 8'h6a: begin outa = 10'h34c; end 8'h6b: begin outa = 10'h049; end 8'h6c: begin outa = 10'h197; end 8'h6d: begin outa = 10'h0fe; end 8'h6e: begin outa = 10'h253; end 8'h6f: begin outa = 10'h2de; end 8'h70: begin outa = 10'h13b; end 8'h71: begin outa = 10'h040; end 8'h72: begin outa = 10'h0b4; end 8'h73: begin outa = 10'h233; end 8'h74: begin outa = 10'h198; end 8'h75: begin outa = 10'h018; end 8'h76: begin outa = 10'h2f7; end 8'h77: begin outa = 10'h134; end 8'h78: begin outa = 10'h1ca; end 8'h79: begin outa = 10'h286; end 8'h7a: begin outa = 10'h0e6; end 8'h7b: begin outa = 10'h064; end 8'h7c: begin outa = 10'h257; end 8'h7d: begin outa = 10'h31a; end 8'h7e: begin outa = 10'h247; end 8'h7f: begin outa = 10'h299; end 8'h80: begin outa = 10'h02c; end 8'h81: begin outa = 10'h2bb; end 8'h82: begin outa = 10'h180; end 8'h83: begin outa = 10'h245; end 8'h84: begin outa = 10'h0da; end 8'h85: begin outa = 10'h367; end 8'h86: begin outa = 10'h304; end 8'h87: begin outa = 10'h38b; end 8'h88: begin outa = 10'h09f; end 8'h89: begin outa = 10'h1f0; end 8'h8a: begin outa = 10'h281; end 8'h8b: begin outa = 10'h019; end 8'h8c: begin outa = 10'h1f2; end 8'h8d: begin outa = 10'h0b1; end 8'h8e: begin outa = 10'h058; end 8'h8f: begin outa = 10'h39b; end 8'h90: begin outa = 10'h2ec; end 8'h91: begin outa = 10'h250; end 8'h92: begin outa = 10'h3f4; end 8'h93: begin outa = 10'h057; end 8'h94: begin outa = 10'h18f; end 8'h95: begin outa = 10'h105; end 8'h96: begin outa = 10'h1ae; end 8'h97: begin outa = 10'h04e; end 8'h98: begin outa = 10'h240; end 8'h99: begin outa = 10'h3e4; end 8'h9a: begin outa = 10'h3c6; end 8'h9b: begin outa = 10'h109; end 8'h9c: begin outa = 10'h073; end 8'h9d: begin outa = 10'h19f; end 8'h9e: begin outa = 10'h3b8; end 8'h9f: begin outa = 10'h00e; end 8'ha0: begin outa = 10'h1b3; end 8'ha1: begin outa = 10'h2bd; end 8'ha2: begin outa = 10'h324; end 8'ha3: begin outa = 10'h343; end 8'ha4: begin outa = 10'h1c9; end 8'ha5: begin outa = 10'h185; end 8'ha6: begin outa = 10'h37a; end 8'ha7: begin outa = 10'h0e0; end 8'ha8: begin outa = 10'h0a3; end 8'ha9: begin outa = 10'h019; end 8'haa: begin outa = 10'h099; end 8'hab: begin outa = 10'h376; end 8'hac: begin outa = 10'h077; end 8'had: begin outa = 10'h2b1; end 8'hae: begin outa = 10'h27f; end 8'haf: begin outa = 10'h265; end 8'hb0: begin outa = 10'h156; end 8'hb1: begin outa = 10'h1ce; end 8'hb2: begin outa = 10'h008; end 8'hb3: begin outa = 10'h12e; end 8'hb4: begin outa = 10'h199; end 8'hb5: begin outa = 10'h330; end 8'hb6: begin outa = 10'h1ab; end 8'hb7: begin outa = 10'h3bd; end 8'hb8: begin outa = 10'h0ca; end 8'hb9: begin outa = 10'h367; end 8'hba: begin outa = 10'h334; end 8'hbb: begin outa = 10'h040; end 8'hbc: begin outa = 10'h1a7; end 8'hbd: begin outa = 10'h036; end 8'hbe: begin outa = 10'h223; end 8'hbf: begin outa = 10'h075; end 8'hc0: begin outa = 10'h3c4; end 8'hc1: begin outa = 10'h2cc; end 8'hc2: begin outa = 10'h123; end 8'hc3: begin outa = 10'h3fd; end 8'hc4: begin outa = 10'h11e; end 8'hc5: begin outa = 10'h27c; end 8'hc6: begin outa = 10'h1e2; end 8'hc7: begin outa = 10'h377; end 8'hc8: begin outa = 10'h33a; end 8'hc9: begin outa = 10'h32d; end 8'hca: begin outa = 10'h014; end 8'hcb: begin outa = 10'h332; end 8'hcc: begin outa = 10'h359; end 8'hcd: begin outa = 10'h0a4; end 8'hce: begin outa = 10'h348; end 8'hcf: begin outa = 10'h04b; end 8'hd0: begin outa = 10'h147; end 8'hd1: begin outa = 10'h026; end 8'hd2: begin outa = 10'h103; end 8'hd3: begin outa = 10'h106; end 8'hd4: begin outa = 10'h35a; end 8'hd5: begin outa = 10'h254; end 8'hd6: begin outa = 10'h0cd; end 8'hd7: begin outa = 10'h17c; end 8'hd8: begin outa = 10'h37e; end 8'hd9: begin outa = 10'h0a9; end 8'hda: begin outa = 10'h0fe; end 8'hdb: begin outa = 10'h3c0; end 8'hdc: begin outa = 10'h1d9; end 8'hdd: begin outa = 10'h10e; end 8'hde: begin outa = 10'h394; end 8'hdf: begin outa = 10'h316; end 8'he0: begin outa = 10'h05b; end 8'he1: begin outa = 10'h126; end 8'he2: begin outa = 10'h369; end 8'he3: begin outa = 10'h291; end 8'he4: begin outa = 10'h2ca; end 8'he5: begin outa = 10'h25b; end 8'he6: begin outa = 10'h106; end 8'he7: begin outa = 10'h172; end 8'he8: begin outa = 10'h2f7; end 8'he9: begin outa = 10'h2d3; end 8'hea: begin outa = 10'h182; end 8'heb: begin outa = 10'h327; end 8'hec: begin outa = 10'h1d0; end 8'hed: begin outa = 10'h204; end 8'hee: begin outa = 10'h11f; end 8'hef: begin outa = 10'h365; end 8'hf0: begin outa = 10'h2c2; end 8'hf1: begin outa = 10'h2b5; end 8'hf2: begin outa = 10'h1f8; end 8'hf3: begin outa = 10'h2a7; end 8'hf4: begin outa = 10'h1be; end 8'hf5: begin outa = 10'h25e; end 8'hf6: begin outa = 10'h032; end 8'hf7: begin outa = 10'h2ef; end 8'hf8: begin outa = 10'h02f; end 8'hf9: begin outa = 10'h201; end 8'hfa: begin outa = 10'h054; end 8'hfb: begin outa = 10'h013; end 8'hfc: begin outa = 10'h249; end 8'hfd: begin outa = 10'h09a; end 8'hfe: begin outa = 10'h012; end 8'hff: begin outa = 10'h114; end endcase end endmodule verilator-4.038/test_regress/t/t_var_dup2.v0000664000177100017500000000055013702133370020723 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Legal with ANSI Verilog 2001 style ports module t ( output wire ok_ow, output reg ok_or); wire ok_o_w; reg ok_o_r; endmodule verilator-4.038/test_regress/t/t_select_param.v0000664000177100017500000000075313702133370021645 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter [ BMSB : BLSB ] B = A[23:20]; // 3 parameter A = 32'h12345678; parameter BLSB = A[16+:4]; // 4 parameter BMSB = A[7:4]; // 7 initial begin if (B !== 4'h3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_order_multialways.pl0000775000177100017500000000105313702133370023117 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_udp_lint.pl0000775000177100017500000000115013702133370021165 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_udp.v"); lint( # Unsupported: UDP Tables verilator_flags2 => ["--lint-only --bbox-unsup"], ); ok(1); 1; verilator-4.038/test_regress/t/t_string_type_methods_bad.v0000664000177100017500000000064713702133370024110 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); string s; integer i; // Check constification initial begin s="1234"; i = s.len(0); // BAD s.itoa; // BAD s.itoa(1,2,3); // BAD end endmodule verilator-4.038/test_regress/t/t_tri_pull01.pl0000775000177100017500000000105313702133370021344 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_recurse2_bad.pl0000775000177100017500000000107413702133370022751 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_dupitems.v0000664000177100017500000000353313702133367022040 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [1:0] in = crc[1:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [1:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[1:0]), // Inputs .in (in[1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {62'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'hbb2d9709592f64bd // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [1:0] in; output reg [1:0] out; always @* begin // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked? case (in[1:0]) 2'd0, 2'd1, 2'd2, 2'd3: begin out = in; end endcase end endmodule verilator-4.038/test_regress/t/t_preproc_ifdef.v0000664000177100017500000000154213702133370022012 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); integer num; initial begin num = 0; `define EMPTY_TRUE `ifndef EMPTY_TRUE `error "Empty is still true" `endif `define A `ifdef A $display("1A"); num = num + 1; `ifdef C $stop; `elsif A $display("2A"); num = num + 1; `ifdef C $stop; `elsif B $stop; `else $display("3A"); num = num + 1; `endif `else $stop; `endif `elsif B $stop; `ifdef A $stop; `elsif A $stop; `else `endif `elsif C $stop; `else $stop; `endif if (num == 3) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("%%Error: Bad count: %d\n", num); $stop; end end endmodule verilator-4.038/test_regress/t/t_vlcov_flag_invalid_bad.out0000664000177100017500000000004713702133370024202 0ustar wsnyderwsnyder%Error: Invalid option: --invalid-dash verilator-4.038/test_regress/t/t_display_mcd.pl0000775000177100017500000000113513702133370021642 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_concat_large_bad.v0000664000177100017500000000050513702133367022436 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); wire [32767:0] a = {32768{1'b1}}; initial begin $stop; end endmodule verilator-4.038/test_regress/t/t_param_type_bad.v0000664000177100017500000000046613702133370022156 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam type t = logic; // Fine localparam type bad2 = 2; // Bad endmodule verilator-4.038/test_regress/t/t_mem_multidim_trace.pl0000775000177100017500000000117713702133370023220 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_mem_multidim.v"); compile( verilator_flags2 => ['--cc --trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_order_multialways.v0000664000177100017500000000243413702133370022752 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] in_a; reg [31:0] in_b; reg [31:0] e,f,g,h; always @ (/*AS*/in_a) begin e = in_a; f = {e[15:0], e[31:16]}; g = {f[15:0], f[31:16]}; h = {g[15:0], g[31:16]}; end // verilator lint_off UNOPTFLAT reg [31:0] e2,f2,g2,h2; always @ (/*AS*/f2) begin h2 = {g2[15:0], g2[31:16]}; g2 = {f2[15:0], f2[31:16]}; end always @ (/*AS*/in_a) begin f2 = {e2[15:0], e2[31:16]}; e2 = in_a; end // verilator lint_on UNOPTFLAT integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x\n", cyc, h, h2); if (h != h2) $stop; if (cyc==1) begin in_a <= 32'h89a14fab; in_b <= 32'h7ab512fa; end if (cyc==2) begin in_a <= 32'hf4c11a42; in_b <= 32'h359967c6; if (h != 32'h4fab89a1) $stop; end if (cyc==3) begin if (h != 32'h1a42f4c1) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_enum_name3.v0000664000177100017500000000073013702133370021230 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 // bug855 module our; typedef enum logic {n,N} T_Flg_N; typedef struct packed { T_Flg_N N; } T_PS_Reg; T_PS_Reg PS = 1'b1; initial begin $write ("P:%s\n", PS.N.name); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_class_new.pl0000775000177100017500000000105313702133367021335 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_2in.v0000664000177100017500000000712013702133367020530 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef VERILATOR module t; /*AUTOREGINPUT*/ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) reg c0; // To t2 of t2.v reg c1; // To t2 of t2.v reg check; // To t2 of t2.v reg [1:0] clks; // To t2 of t2.v // End of automatics t2 t2 (/*AUTOINST*/ // Inputs .clks (clks[1:0]), .c0 (c0), .c1 (c1), .check (check)); task clockit (input v1, v0); c1 = v1; c0 = v0; clks[1] = v1; clks[0] = v0; `ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif #1; endtask initial begin check = '0; c0 = '0; c1 = '0; clks = '0; #1 t2.clear(); #10; for (int i=0; i<2; i++) begin clockit(0, 0); clockit(0, 0); clockit(0, 1); clockit(1, 1); clockit(0, 0); clockit(1, 1); clockit(1, 0); clockit(0, 0); clockit(1, 0); clockit(0, 1); clockit(0, 0); end check = 1; clockit(0, 0); end endmodule `endif `ifdef VERILATOR `define t2 t `else `define t2 t2 `endif module `t2 ( input [1:0] clks, input c0, input c1, input check ); `ifdef T_CLK_2IN_VEC wire clk0 = clks[0]; wire clk1 = clks[1]; `else wire clk0 = c0; wire clk1 = c1; `endif integer p0 = 0; integer p1 = 0; integer p01 = 0; integer n0 = 0; integer n1 = 0; integer n01 = 0; integer vp = 0; integer vn = 0; integer vpn = 0; task clear; `ifdef TEST_VERBOSE $display("[%0t] clear\n",$time); `endif p0 = 0; p1 = 0; p01 = 0; n0 = 0; n1 = 0; n01 = 0; vp = 0; vn = 0; vpn = 0; endtask `define display_counts(text) begin \ $write("[%0t] ",$time); \ `ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \ $write(text); \ $write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \ end always @ (posedge clk0) begin p0 = p0 + 1; // Want blocking, so don't miss clock counts `ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif end always @ (posedge clk1) begin p1 = p1 + 1; `ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif end always @ (posedge clk0 or posedge clk1) begin p01 = p01 + 1; `ifdef TEST_VERBOSE `display_counts("posedge *"); `endif end always @ (negedge clk0) begin n0 = n0 + 1; `ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif end always @ (negedge clk1) begin n1 = n1 + 1; `ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif end always @ (negedge clk0 or negedge clk1) begin n01 = n01 + 1; `ifdef TEST_VERBOSE `display_counts("negedge *"); `endif end `ifndef VERILATOR always @ (posedge clks) begin vp = vp + 1; `ifdef TEST_VERBOSE `display_counts("pos vec"); `endif end always @ (negedge clks) begin vn = vn + 1; `ifdef TEST_VERBOSE `display_counts("neg vec"); `endif end always @ (posedge clks or negedge clks) begin vpn = vpn + 1; `ifdef TEST_VERBOSE `display_counts("or vec"); `endif end `endif always @ (posedge check) begin if (p0!=6) $stop; if (p1!=6) $stop; if (p01!=10) $stop; if (n0!=6) $stop; if (n1!=6) $stop; if (n01!=10) $stop; `ifndef VERILATOR if (vp!=6) $stop; if (vn!=6) $stop; if (vpn!=12) $stop; `endif $write("*-* All Finished *-*\n"); end endmodule verilator-4.038/test_regress/t/t_gen_alw.pl0000775000177100017500000000105313702133370020765 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_ifdepth_bad.v0000664000177100017500000000226113702133370022461 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer value = 19; initial begin if (value==1) begin end else if (value==2) begin end else if (value==3) begin end else if (value==4) begin end else if (value==5) begin end else if (value==6) begin end else if (value==7) begin end else if (value==8) begin end else if (value==9) begin end else if (value==10) begin end else if (value==11) begin end // Warn about this one else if (value==12) begin end end initial begin unique0 if (value==1) begin end else if (value==2) begin end else if (value==3) begin end else if (value==4) begin end else if (value==5) begin end else if (value==6) begin end else if (value==7) begin end else if (value==8) begin end else if (value==9) begin end else if (value==10) begin end else if (value==11) begin end // Warn about this one else if (value==12) begin end end endmodule verilator-4.038/test_regress/t/t_fork_disable.v0000664000177100017500000000066513702133370021634 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); logic never; initial begin fork #10; #10; join_none disable fork; wait fork; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_order_2d.pl0000775000177100017500000000105313702133370021051 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_prot_lib_inout_bad.out0000664000177100017500000000030413702133370023376 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_prot_lib_inout_bad.v:9:28: Unsupported: protect-lib port direction: INOUT 9 | inout z, | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_langext_3.v0000664000177100017500000000101713702133370021064 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // // This source code uses the uwire declaration, which is only valid in Verilog // 2005. // // Compile only test, so no need for "All Finished" output. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; uwire w; // Only in Verilog 2005 endmodule verilator-4.038/test_regress/t/t_iff.v0000664000177100017500000000364413702133370017754 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] result; // From test of Test.v // End of automatics Test test (.*); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'he58508de5310b541 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input [63:0] crc, input [31:0] cyc, output wire [31:0] result); wire enable = crc[32]; wire [31:0] d = crc[31:0]; logic [31:0] y; always @(d iff enable == 1) begin y <= d; end wire reset = (cyc < 10); assert property (@(posedge clk iff enable) disable iff (reset) (crc != '0)); // Aggregate outputs into a single result vector assign result = {32'h0, y}; endmodule verilator-4.038/test_regress/t/t_interface_modportlist.v0000664000177100017500000000104713702133370023603 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Adrian Wise. // SPDX-License-Identifier: CC0-1.0 //bug1246 module t(input clk); my_interface iface(); my_module m(.clk(clk), iface); endmodule module my_module(input clk, my_interface.my_port iface); always @(posedge clk) begin iface.b <= iface.a; iface.c <= iface.a; end endmodule interface my_interface; logic a, b, c; modport my_port(input a, output b, c); endinterface verilator-4.038/test_regress/t/t_interface_down_inlad.pl0000775000177100017500000000125513702133370023513 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_A +define+INLINE_D'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_rsvd_port.pl0000775000177100017500000000107113702133370022243 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2=>["-Wno-SYMRSVDWORD"], ); execute(); ok(1); 1; verilator-4.038/test_regress/t/t_inst_v2k__sub.vi0000664000177100017500000000110113702133370022112 0ustar wsnyderwsnyder// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // This file is named .vi to test +libext+ flags. module t_inst_v2k__sub ( output reg [7:0] osizedreg, output wire oonewire /*verilator public*/, input [7:0] isizedwire, input wire ionewire, output reg [1:0] tied = 2'b10 ); assign oonewire = ionewire; always @* begin osizedreg = isizedwire; end endmodule verilator-4.038/test_regress/t/t_if_swap.pl0000775000177100017500000000100113702133370020772 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_program.pl0000775000177100017500000000105313702133370021020 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_sel_range.pl0000775000177100017500000000106213702133370022470 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wno-SELRANGE"], ); ok(1); 1; verilator-4.038/test_regress/t/t_increment_bad.pl0000775000177100017500000000077413702133370022154 0ustar wsnyderwsnyder#!/usr/bin/perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_xml_output.pl0000775000177100017500000000210313702133370021566 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2012 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $out_filename = "$Self->{obj_dir}/renamed-$Self->{name}.xml"; compile( verilator_flags2 => ["--xml-only --xml-output $out_filename"], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); files_identical("$out_filename", $Self->{golden_filename}); foreach my $file (glob("$Self->{obj_dir}/*")) { next if $file =~ /\.log/; # Made by driver.pl, not Verilator next if $file =~ /\.status/; # Made by driver.pl, not Verilator next if $file =~ /renamed-/; # Requested output error("%Error: Created $file, but --xml-only shouldn't create files"); } ok(1); 1; verilator-4.038/test_regress/t/t_math_reverse.v0000664000177100017500000000420513702133370021666 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [7:0] crc; // Build up assignments wire [7:0] bitrev; assign bitrev[7] = crc[0]; assign bitrev[6] = crc[1]; assign bitrev[5] = crc[2]; assign bitrev[4] = crc[3]; assign bitrev[0] = crc[7]; assign bitrev[1] = crc[6]; assign bitrev[2] = crc[5]; assign bitrev[3] = crc[4]; // Build up always assignments reg [7:0] bitrevb; always @ (/*AS*/crc) begin bitrevb[7] = crc[0]; bitrevb[6] = crc[1]; bitrevb[5] = crc[2]; bitrevb[4] = crc[3]; bitrevb[0] = crc[7]; bitrevb[1] = crc[6]; bitrevb[2] = crc[5]; bitrevb[3] = crc[4]; end // Build up always assignments reg [7:0] bitrevr; always @ (posedge clk) begin bitrevr[7] <= crc[0]; bitrevr[6] <= crc[1]; bitrevr[5] <= crc[2]; bitrevr[4] <= crc[3]; bitrevr[0] <= crc[7]; bitrevr[1] <= crc[6]; bitrevr[2] <= crc[5]; bitrevr[3] <= crc[4]; end always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; //$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev); crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==1) begin crc <= 8'hed; end if (cyc==2 && bitrev!=8'hb7) $stop; if (cyc==3 && bitrev!=8'h5b) $stop; if (cyc==4 && bitrev!=8'h2d) $stop; if (cyc==5 && bitrev!=8'h16) $stop; if (cyc==6 && bitrev!=8'h8b) $stop; if (cyc==7 && bitrev!=8'hc5) $stop; if (cyc==8 && bitrev!=8'he2) $stop; if (cyc==9 && bitrev!=8'hf1) $stop; if (bitrevb != bitrev) $stop; if (cyc==3 && bitrevr!=8'hb7) $stop; if (cyc==4 && bitrevr!=8'h5b) $stop; if (cyc==5 && bitrevr!=8'h2d) $stop; if (cyc==6 && bitrevr!=8'h16) $stop; if (cyc==7 && bitrevr!=8'h8b) $stop; if (cyc==8 && bitrevr!=8'hc5) $stop; if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_clk_concat.pl0000775000177100017500000000224513702133367021463 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( verilator_flags2 => ["+define+ATTRIBUTES"], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_shift_over_bad.v0000664000177100017500000000061213702133370023167 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, // Inputs clk, i ); input clk; input [31:0] i; output [31:0] o; assign o = i << 64'h01234567_89abcdef; endmodule verilator-4.038/test_regress/t/t_math_real_round.v0000664000177100017500000000554513702133370022355 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; real r; reg [31:0] v32; reg [63:0] v64; reg [95:0] v96; initial begin // verilator lint_off REALCVT v32 = -1.5; v64 = -1.5; v96 = -1.5; // verilator lint_on REALCVT `checkh(v32, 32'hfffffffe); `checkh(v64, 64'hfffffffffffffffe); `checkh(v96, 96'hfffffffffffffffffffffffe); // verilator lint_off REALCVT v32 = 12456789012345678912345.5; v64 = 12456789012345678912345.5; v96 = 12456789012345678912345.5; // verilator lint_on REALCVT `checkh(v32, 32'he5400000); `checkh(v64, 64'h48acb7d4e5400000); `checkh(v96, 96'h000002a348acb7d4e5400000); // verilator lint_off REALCVT v32 = -12456789012345678912345.5; v64 = -12456789012345678912345.5; v96 = -12456789012345678912345.5; // verilator lint_on REALCVT `checkh(v32, 32'h1ac00000); `checkh(v64, 64'hb753482b1ac00000); `checkh(v96, 96'hfffffd5cb753482b1ac00000); end // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin r <= 0; end else if (cyc == 11) begin // verilator lint_off REALCVT v32 = r; v64 = r; v96 = r; // verilator lint_on REALCVT `checkh(v32, '0); `checkh(v64, '0); `checkh(v96, '0); end else if (cyc == 20) begin r <= -5.24567; end else if (cyc == 21) begin // verilator lint_off REALCVT v32 = r; v64 = r; v96 = r; // verilator lint_on REALCVT `checkh(v32, 32'hfffffffb); `checkh(v64, 64'hfffffffffffffffb); `checkh(v96, 96'hfffffffffffffffffffffffb); end else if (cyc == 30) begin r <= 12456789012345678912345.5; end else if (cyc == 31) begin // verilator lint_off REALCVT v32 = r; v64 = r; v96 = r; // verilator lint_on REALCVT `checkh(v32, 32'he5400000); `checkh(v64, 64'h48acb7d4e5400000); `checkh(v96, 96'h000002a348acb7d4e5400000); end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_tri_graph.pl0000775000177100017500000000102513702133370021327 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Compile only test compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_order_clkinst_bad.pl0000775000177100017500000000122613702133370023023 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_order_clkinst.v"); compile( v_flags2 => ["-Wwarn-IMPERFECTSCH"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_sel.pl0000775000177100017500000000105313702133370021314 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_lib.pl0000775000177100017500000000120713702133370020754 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["t/t_dpi_lib_c.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_langext_1.v0000664000177100017500000000232013702133370021060 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test of the +verilog1995ext+ and +verilog2001ext+ flags. // // This source code contains constructs that are valid in Verilog 2001 and // SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we // set the language to be 1995, but not 2001. // // Compile only test, so no need for "All Finished" output. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [1:0] res; // Instantiate the test test test_i (// Outputs .res (res[1:0]), // Inputs .clk (clk), .in (1'b1)); endmodule module test (// Outputs res, // Inputs clk, in ); output reg [1:0] res; input clk; input in; // This is a Verilog 2001 test generate genvar i; for (i=0; i<2; i=i+1) begin always @(posedge clk) begin res[i:i] <= in; end end endgenerate endmodule verilator-4.038/test_regress/t/t_clk_dsp.pl0000775000177100017500000000105313702133367020776 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_b.v0000664000177100017500000000101313702133370021464 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; integer c_trace_on; real r; sub sub (); always @ (posedge clk) begin if (cyc != 0) begin r <= r + 0.1; end end endmodule module sub; integer inside_sub_a = 2; endmodule verilator-4.038/test_regress/t/t_flag_xinitial_unique.v0000664000177100017500000000060013702133370023375 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs value ); output reg [63:0] value; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_gen_for2.pl0000775000177100017500000000105313702133370021052 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_concat64.pl0000775000177100017500000000105313702133370022003 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_module.pl0000775000177100017500000000163213702133370021517 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); skip("Known compiler limitation") if $Self->cxx_version =~ /\(GCC\) 4.4/; compile( make_top_shell => 0, make_main => 0, make_pli => 1, iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2 => ["+define+USE_VPI_NOT_DPI"], verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_module.cpp"], ); execute( iv_pli => 1, check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_param_avec.v0000664000177100017500000000214113702133370021275 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; sub #(.IDX(0), .CHK(10)) i0; sub #(.IDX(2), .CHK(12)) i2; sub #(.IDX(7), .CHK(17)) i7; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (); function integer get_element; input integer index; input integer array_arg[7:0]; get_element = array_arg[index]; endfunction parameter integer IDX = 5; parameter integer CHK = 5; localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17}; localparam element1 = array[IDX]; localparam elementf = get_element(IDX, array); initial begin `checkh (element1, CHK); `checkh (elementf, CHK); end endmodule verilator-4.038/test_regress/t/t_gen_defparam.v0000664000177100017500000000154713702133370021620 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter PAR = 3; wire [31:0] o1a,o1b; m1 #(0) m1a(.o(o1a)); m1 #(1) m1b(.o(o1b)); always @ (posedge clk) begin if (o1a != 8) $stop; if (o1b != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module m1 (output wire [31:0] o); parameter W = 0; generate if (W == 0) begin m2 m2 (.o(o)); defparam m2.PAR2 = 8; end else begin m2 m2 (.o(o)); defparam m2.PAR2 = 4; end endgenerate endmodule module m2 (output wire [31:0] o); parameter PAR2 = 10; assign o = PAR2; endmodule verilator-4.038/test_regress/t/t_assert_synth_parallel_vlt.out0000664000177100017500000000025213702133367025037 0ustar wsnyderwsnyder[40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found %Error: t/t_assert_synth.v:55: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_initarray_nonarray.pl0000775000177100017500000000100113702133370023255 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_self_return.v0000664000177100017500000000303213702133370022360 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Roman Popov. // SPDX-License-Identifier: CC0-1.0 module dut #( parameter DEPTH = 16, parameter WIDTH = 32, parameter RAM_SPLIT_WIDTH = 16 ) ( output logic [WIDTH-1:0] ram_dataout ); localparam RAM_ADDR_WIDTH = $clog2(DEPTH); // = 4 localparam NUM_RAM_BLOCKS = (WIDTH/RAM_SPLIT_WIDTH) + {31'h0, ((WIDTH % RAM_SPLIT_WIDTH) > 0)}; // = 2 typedef logic [NUM_RAM_BLOCKS:0][31:0] block_index_t; // width 96 function automatic block_index_t index_calc(input int WIDTH, NUM_RAM_BLOCKS); index_calc[0] = '0; for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = WIDTH/NUM_RAM_BLOCKS + {31'h0, (i < (WIDTH%NUM_RAM_BLOCKS))}; for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = index_calc[i+1] + index_calc[i]; // bug1467 was this return return index_calc; endfunction localparam block_index_t RAM_BLOCK_INDEX = index_calc(WIDTH, NUM_RAM_BLOCKS); generate begin : ram_dataout_gen for (genvar i = 0; i < NUM_RAM_BLOCKS; i++) begin always_comb ram_dataout[RAM_BLOCK_INDEX[i+1]-1:RAM_BLOCK_INDEX[i]] = 0; end end endgenerate initial begin if (RAM_BLOCK_INDEX != {32'd32, 32'd16, 32'd0}) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module t ( input clk, output logic [31:0] ram_dataout ); dut dut0(.*); endmodule verilator-4.038/test_regress/t/t_order_comboloop.pl0000775000177100017500000000105313702133370022535 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_const_part.v0000664000177100017500000000126713702133370022543 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function integer bottom_4bits; input [7:0] i; bottom_4bits = 0; bottom_4bits[3:0] = i[3:0]; endfunction function integer bottom_2_unknown; input [7:0] i; // bottom_4bits = 0; 'x bottom_2_unknown[1:0] = i[1:0]; endfunction localparam p = bottom_4bits(8'h13); localparam bu = bottom_2_unknown(8'h13); initial begin if (p != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_xml_first.v0000664000177100017500000000173013702133370021211 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs q, // Inputs clk, d ); input clk; input [3:0] d; output wire [3:0] q; logic [3:0] between; mod1 #(.WIDTH(4)) cell1 (.q(between), .clk (clk), .d (d[3:0])); mod2 cell2 (.d(between), .q (q[3:0]), .clk (clk)); endmodule module mod1 #(parameter WIDTH = 32) ( input clk, input [WIDTH-1:0] d, output logic [WIDTH-1:0] q ); localparam IGNORED = 1; always @(posedge clk) q <= d; endmodule module mod2 ( input clk, input [3:0] d, output wire [3:0] q ); assign q = d; endmodule verilator-4.038/test_regress/t/t_interface_gen2.pl0000775000177100017500000000106013702133370022222 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_timescale_parse_bad.v0000664000177100017500000000067313702133370023155 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // units < precision `timescale 1ps/1ns // Bad scale `timescale frump `timescale 1xs `timescale 2ps `timescale 1ns / frump `timescale 1ns / 1ps /extra module t; timeunit 2ps; // Bad timeprecision 2ps; // Bad endmodule verilator-4.038/test_regress/t/t_math_pick.pl0000775000177100017500000000105313702133370021310 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_sys_c.cpp0000664000177100017500000000213613702133370021474 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_sys__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { extern void dpii_sys_task(int i); extern int dpii_sys_func(int i); } #endif //====================================================================== static int hidden = 0; void dpii_sys_task(int i) { hidden = i; } int dpii_sys_func(int i) { return i + hidden; } verilator-4.038/test_regress/t/t_string_type_methods.v0000664000177100017500000001163313702133370023277 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; string s; integer cyc=0; // Check constification initial begin s="1234"; `checkh(s.len(),4); s="ab7CD"; `checks(s.toupper(), "AB7CD"); s="ab7CD"; `checks(s.tolower(), "ab7cd"); s="1234"; s.putc(-1, "z"); `checks(s, "1234"); s="1234"; s.putc(4, "z"); `checks(s, "1234"); s="1234"; s.putc(2, 0); `checks(s, "1234"); s="1234"; s.putc(2, "z"); `checks(s, "12z4"); s="1234"; `checkh(s.getc(-1), 0); s="1234"; `checkh(s.getc(4), 0); s="1234"; `checkh(s.getc(2), "3"); s="b"; if (s.compare("a") <= 0) $stop; s="b"; if (s.compare("b") != 0) $stop; s="b"; if (s.compare("c") >= 0) $stop; s="b"; if (s.compare("A") <= 0) $stop; s="b"; if (s.compare("B") <= 0) $stop; s="b"; if (s.compare("C") <= 0) $stop; s="B"; if (s.compare("a") >= 0) $stop; s="B"; if (s.compare("b") >= 0) $stop; s="B"; if (s.compare("c") >= 0) $stop; s="b"; if (s.icompare("A") < 0) $stop; s="b"; if (s.icompare("B") != 0) $stop; s="b"; if (s.icompare("C") >= 0) $stop; s="abcd"; `checks(s.substr(-1,1), ""); s="abcd"; `checks(s.substr(1,0), ""); s="abcd"; `checks(s.substr(1,4), ""); s="abcd"; `checks(s.substr(2,3), "cd"); s="101"; `checkh(s.atoi(), 'd101); s="101"; `checkh(s.atohex(), 'h101); s="101"; `checkh(s.atooct(), 'o101); s="101"; `checkh(s.atobin(), 'b101); s="1.23"; `checkg(s.atoreal(), 1.23); s.itoa(123); `checks(s, "123"); s.hextoa(123); `checks(s, "7b"); s.octtoa(123); `checks(s, "173"); s.bintoa(123); `checks(s, "1111011"); s.realtoa(1.23); `checks(s, "1.23"); s = "bAr"; s = s.toupper; `checks(s, "BAR"); s = s.tolower; `checks(s, "bar"); end // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup s = "1234"; end else if (cyc==1) begin `checkh(s.len(),4); end else if (cyc==2) begin s.putc(-1, "z"); end else if (cyc==3) begin `checks(s, "1234"); s.putc(4, "z"); end else if (cyc==4) begin `checks(s, "1234"); s.putc(2, 0); end else if (cyc==5) begin `checks(s, "1234"); s.putc(2, "z"); end else if (cyc==6) begin `checks(s, "12z4"); end else if (cyc==7) begin `checkh(s.getc(-1), 0); `checkh(s.getc(4), 0); `checkh(s.getc(2), "z"); s="ab3CD"; end else if (cyc==8) begin `checks(s.toupper(), "AB3CD"); `checks(s.tolower(), "ab3cd"); s="b"; end else if (cyc==9) begin if (s.compare("a") <= 0) $stop; if (s.compare("b") != 0) $stop; if (s.compare("c") >= 0) $stop; if (s.compare("A") <= 0) $stop; if (s.compare("B") <= 0) $stop; if (s.compare("C") <= 0) $stop; if (s.icompare("A") < 0) $stop; if (s.icompare("B") != 0) $stop; if (s.icompare("C") >= 0) $stop; s="abcd"; end else if (cyc==10) begin `checks(s.substr(-1,1), ""); `checks(s.substr(1,0), ""); `checks(s.substr(1,4), ""); `checks(s.substr(2,3), "cd"); s="101"; end else if (cyc==11) begin `checkh(s.atoi(), 'd101); `checkh(s.atohex(), 'h101); `checkh(s.atooct(), 'o101); `checkh(s.atobin(), 'b101); s="1.23"; end else if (cyc==12) begin `checkg(s.atoreal(), 1.23); end else if (cyc==13) begin s.itoa(123); end else if (cyc==14) begin `checks(s, "123"); s.hextoa(123); end else if (cyc==15) begin `checks(s, "7b"); s.octtoa(123); end else if (cyc==16) begin `checks(s, "173"); s.bintoa(123); end else if (cyc==17) begin `checks(s, "1111011"); s.realtoa(1.23); end else if (cyc==18) begin `checks(s, "1.23"); end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_interface_ref_trace_inlb.pl0000775000177100017500000000150313702133370024327 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_ref_trace.v"); $Self->{golden_filename} = "t/t_interface_ref_trace.out"; compile( v_flags2 => ['+define+NO_INLINE_B'], verilator_flags2 => ['--trace-structs --trace'], ); execute( check_finished => 1, ); vcd_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_display.out0000664000177100017500000000051013650310376022045 0ustar wsnyderwsnyderdpii_display_call: '' dpii_display_call: 'c' dpii_display_call: 'co' dpii_display_call: 'cons' dpii_display_call: 'constant' dpii_display_call: 'constant_value' one10=0000000a dpii_display_call: 'one10=0000000a' Mod=top.t 16= 10 10=0000000a dpii_display_call: 'Mod=top.t 16= 10 10=0000000a' *-* All Finished *-* verilator-4.038/test_regress/t/t_trace_two_sc.cpp0000664000177100017500000000360413702133370022175 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #include "verilatedos.h" #include VM_PREFIX_INCLUDE #include "Vt_trace_two_b.h" #include "verilated.h" #ifdef TEST_HDR_TRACE # include "verilated_vcd_sc.h" #endif // Compile in place #include "Vt_trace_two_b.cpp" #include "Vt_trace_two_b__Slow.cpp" #include "Vt_trace_two_b__Syms.cpp" #include "Vt_trace_two_b__Trace.cpp" #include "Vt_trace_two_b__Trace__Slow.cpp" // General headers #include "verilated.h" #include "systemc.h" VM_PREFIX* ap; Vt_trace_two_b* bp; int sc_main(int argc, char** argv) { sc_signal clk; sc_time sim_time(1100, SC_NS); Verilated::commandArgs(argc, argv); Verilated::traceEverOn(true); Verilated::debug(0); srand48(5); ap = new VM_PREFIX("topa"); bp = new Vt_trace_two_b("topb"); ap->clk(clk); bp->clk(clk); #ifdef TEST_HDR_TRACE VerilatedVcdSc* tfp = new VerilatedVcdSc; ap->trace(tfp, 99); bp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif { clk = false; #if (SYSTEMC_VERSION>=20070314) sc_start(10, SC_NS); #else sc_start(10); #endif } while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { clk = !clk; #if (SYSTEMC_VERSION>=20070314) sc_start(5, SC_NS); #else sc_start(5); #endif } if (!Verilated::gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } ap->final(); bp->final(); #ifdef TEST_HDR_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete ap, ap); VL_DO_DANGLING(delete bp, bp); exit(0L); } verilator-4.038/test_regress/t/t_interface_mismodport_bad.out0000664000177100017500000000036413702133370024571 0ustar wsnyderwsnyder%Error: t/t_interface_mismodport_bad.v:36:12: Can't find definition of 'bad' in dotted signal: 'isub.bad' 36 | isub.bad = i_value; | ^~~ ... Known scopes under 'bad': %Error: Exiting due to verilator-4.038/test_regress/t/t_math_concat.v0000664000177100017500000000555313702133370021471 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [255:0] i; wire [255:0] q; assign q = { i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] }; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%x %x\n", q, i); `endif if (cyc==1) begin i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; end if (cyc==2) begin i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; end if (cyc==3) begin if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_flag_wfatal.v0000664000177100017500000000045513702133370021454 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); // Width error below wire [3:0] foo = 6'h2e; endmodule verilator-4.038/test_regress/t/t_func_const_struct_bad.v0000664000177100017500000000175413702133370023563 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { logic [ 31 : 0 ] a; logic [ 31 : 0 ] b; } params_t; localparam params_t P = '{a:5, b:1}; localparam P6 = f_add(P); localparam P14 = f_add2(2, 3, f_add(P)); localparam P24 = f_add2(7, 8, 9); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end function integer f_add(input params_t params); f_add = params.a+params.b; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); params_t params; params = '{ a: a, b: b }; f_add2 = f_add(params)+c; endfunction endmodule verilator-4.038/test_regress/t/t_mem_multi_io.v0000664000177100017500000000231413702133370021660 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [7:0] arr [7:0]; logic [7:0] arri [7:0]; has_array am1 (.clk(clk), .arri(arr), .arro(arri)); integer cyc; initial cyc = 0; initial begin for (int i = 0; i < 8; i++) begin arr[i] = 0; end end always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 5 && arri[1] != 8) begin $stop; end for (int i = 0; i < 7; ++i) begin arr[i+1] <= arr[i]; end arr[0] <= arr[0] + 1; end endmodule : t module has_array ( input clk, input logic [7:0] arri [7:0], output logic [7:0] arro [7:0] ); integer cyc; initial cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (arri[0] == 10 && cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end always @(posedge clk) begin for (integer i = 0; i < 7; ++i) begin arro[i+1] <= arro[i]; end arro[0] = arro[0] + 2; end endmodule : has_array verilator-4.038/test_regress/t/t_hierarchy_identifier.pl0000775000177100017500000000105313702133370023531 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface1_modport.v0000664000177100017500000000205413702133370022767 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing interface ifc; integer hidden_from_isub; integer value; modport out_modport (output value); endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc itop(); sub c1 (.isub(itop), .i_value(4)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (itop.value != 4) $stop; itop.hidden_from_isub = 20; if (itop.hidden_from_isub != 20) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub `ifdef NANSI // bug868 ( isub, i_value ); ifc.out_modport isub; // Note parenthesis are not legal here input integer i_value; `else ( ifc.out_modport isub, input integer i_value ); `endif always @* begin isub.value = i_value; end endmodule verilator-4.038/test_regress/t/t_runflag.v0000664000177100017500000000047113702133370020641 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_always_comb_iface.v0000664000177100017500000000404213702133370023656 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if; logic valid; logic [7:0] data ; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire in_valid, input wire [7:0] in_data ); my_if in_i (); my_if out1_i (); my_if out2_i (); my_if out3_i (); assign in_i.valid = in_valid; assign in_i.data = in_data ; my_module1 my_module1_i ( .in_i (in_i ), .out_i (out1_i) ); my_module2 my_module2_i ( .in_i (in_i ), .out_i (out2_i) ); my_module3 my_module3_i ( .in_i (in_i ), .out_i (out3_i) ); endmodule module my_module1 ( my_if.slave_mp in_i, my_if.master_mp out_i ); // Gives ALWCOMBORDER warning always_comb begin out_i.valid = in_i.valid; out_i.data = in_i.data ; end endmodule module my_module2 ( my_if.slave_mp in_i, my_if.master_mp out_i ); // Works if you initialise to non-interface signal first always_comb begin out_i.valid = '0; out_i.data = 'X; out_i.valid = in_i.valid; out_i.data = in_i.data ; end endmodule module my_module3 ( my_if.slave_mp in_i, my_if.master_mp out_i ); // Works if you use assign signal assign out_i.valid = in_i.valid; assign out_i.data = in_i.data ; endmodule verilator-4.038/test_regress/t/t_var_vec_sel.pl0000775000177100017500000000076613702133370021653 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_param.v0000664000177100017500000000303713702133370020304 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; m1 #(PAR) m1(); m3 #(PAR) m3(); mnooverride #(10) mno(); input clk; integer cyc=1; reg [4:0] bitsel; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin bitsel = 0; if (PAR[bitsel]!==1'b1) $stop; bitsel = 1; if (PAR[bitsel]!==1'b1) $stop; bitsel = 2; if (PAR[bitsel]!==1'b0) $stop; end if (cyc==1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module m1; localparam PAR1MINUS1 = PAR1DUP-2-1; localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly parameter PAR1 = 0; m2 #(PAR1MINUS1) m2 (); // Packed arrays localparam [1:0][3:0] PACKED_PARAM = { 4'h3, 4'h6 }; initial if (PACKED_PARAM != 8'h36) $stop; endmodule // bug 810 module m2 #(/*parameter*/ integer PAR2 = 10); initial begin $display("%x",PAR2); if (PAR2 !== 2) $stop; end endmodule module m3; localparam LOC = 13; parameter PAR = 10; initial begin $display("%x %x",LOC,PAR); if (LOC !== 13) $stop; if (PAR !== 3) $stop; end endmodule module mnooverride; localparam LOC = 13; parameter PAR = 10; initial begin $display("%x %x",LOC,PAR); if (LOC !== 13) $stop; if (PAR !== 10) $stop; end endmodule verilator-4.038/test_regress/t/t_interface_gen2_collision.pl0000775000177100017500000000120513702133370024276 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen2.v"); compile( verilator_flags2 => ["--debug-collision"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_local.v0000664000177100017500000000115613702133367021471 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); class Cls; typedef enum {A = 10, B = 20, C = 30} en_t; local int m_loc = 2; protected int m_prot = B; endclass initial begin Cls c; if (c.A != 10) $stop; c = new; if (c.m_loc != 2) $stop; c.m_loc = 10; if (c.m_loc != 10) $stop; if (c.m_prot != 20) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_waiveroutput.v0000664000177100017500000000046713702133370021766 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_waiveroutput; reg width_warn = 2'b11; // Width warning - must be line 18 endmodule verilator-4.038/test_regress/t/t_package_param.v0000664000177100017500000000145613702133370021762 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // IEEE 1800-2009 requires that any local definitions take precedence over // definitions in wildcard imported packages (section 26.3). Thus the code // below is valid SystemVerilog. // // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2013 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 package defs; parameter NUMBER = 8; localparam NUM = NUMBER; endpackage module t(/*AUTOARG*/ // Inputs clk ); input clk; import defs::*; // This also fails if we use localparam parameter NUM = 32; // Check we have the right definition always @(posedge clk) begin if (NUM == 32) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-4.038/test_regress/t/t_class_copy_bad.pl0000775000177100017500000000107413702133367022327 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_dump_sc.pl0000775000177100017500000000243713702133370023061 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if (!$Self->have_sc) { skip("No SystemC installed"); } else { top_filename("t_trace_two_a.v"); compile( make_main => 0, verilator_make_gmake => 0, top_filename => 't_trace_two_b.v', VM_PREFIX => 'Vt_trace_two_b', verilator_flags2 => ['-sc -trace'], ); compile( make_main => 0, top_filename => 't_trace_two_a.v', verilator_flags2 => ['-sc', '-exe', '-trace', "$Self->{t_dir}/t_trace_two_sc.cpp"], v_flags2 => ['+define+TEST_DUMP'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } } ok(1); 1; verilator-4.038/test_regress/t/t_mem_first.v0000664000177100017500000000611013702133370021164 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; initial _mode = 0; // verilator lint_off LITENDIAN reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [34:0] vec_wide; // verilator lint_on LITENDIAN reg [31:0] wrd0 [15:0]; wire [3:0] sel = 4'h3; wire [31:0] selout = wrd0[sel]; // Must take LSBs into account in bit extract widths. wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB wire [3:0] sixfrom = 13; wire [4:0] sixfrom2 = 16; wire sixtext = sixt[sixfrom]; wire sixtext2 = sixt2[sixfrom2]; // Non-power of 2 memory overwriting checks reg [2:0] np2_mem [5:0] /*verilator public*/; reg [2:0] np2_guard [7:6] /*verilator public*/; integer i; always @ (posedge clk) begin if (_mode!=0) begin wrd0[0] = 32'h1; // for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR mem_narrow[i] = i[7:0]; mem_wide[i] = {i[7:0],70'hfeed}; end // for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR if (mem_narrow[i] !== i[7:0]) $stop; if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop; end // vec_wide <= 0; // np2_guard[6] = 0; np2_guard[7] = 0; // $write("selout %b %b %b\n", selout, sixtext, sixtext2); end if (_mode == 1) begin _mode <= 2; // i=0; mem_dly_narrow[0] <= ~i[7:0]; mem_dly_wide[0] <= {~i[7:0],70'hface}; i=1; mem_dly_narrow[i] <= ~i[7:0]; mem_dly_wide[i] <= {~i[7:0],70'hface}; // for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR // verilator lint_off width np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB // verilator lint_on width if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop; end // verilator lint_off SELRANGE if (np2_mem[6] !== np2_mem[7]) begin $write("Mem[6]!=Mem[7] during randomize...\n"); //$stop; // Random value, so this can happen end // verilator lint_on SELRANGE //if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's // vec_wide[32:31] <= 2'b11; vec_wide[34] <= 1'b1; $display("%x",vec_wide); end if (_mode == 2) begin _mode <= 3; // for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR if (mem_dly_narrow[i] !== ~i[7:0]) $stop; if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop; end // //$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]); if (vec_wide != {4'b101_1,31'd0}) $stop; // $write("*-* All Finished *-*\n"); $finish; end _mode <= _mode + 1; end endmodule verilator-4.038/test_regress/t/t_for_local.v0000664000177100017500000000233513702133370021144 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc=0; reg [31:0] loops; reg [31:0] loops2; always @ (posedge clk) begin cyc <= cyc+8'd1; if (cyc == 8'd1) begin $write("[%0t] t_loop: Running\n",$time); // Unwind < loops = 0; loops2 = 0; for (int i=0; i<16; i=i+1) begin loops = loops + i; // surefire lint_off_line ASWEMB loops2 = loops2 + i; // surefire lint_off_line ASWEMB end if (loops !== 120) $stop; if (loops2 !== 120) $stop; // Check we can declare the same signal twice loops = 0; for (int i=0; i<=16; i=i+1) begin loops = loops + 1; end if (loops !== 17) $stop; // Check type is correct loops = 0; for (byte unsigned i=5; i>4; i=i+1) begin loops = loops + 1; end if (loops !== 251) $stop; // Check large loops loops = 0; for (int i=0; i<100000; i=i+1) begin loops = loops + 1; end if (loops !== 100000) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_lint_width_genfor_bad.pl0000775000177100017500000000110113702133370023656 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_hierarchy_unnamed.pl0000775000177100017500000000076613702133370023050 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_func_lib.v0000664000177100017500000000047613702133370020771 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_colonplus_bad.pl0000775000177100017500000000107113702133370023223 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_missing.v0000664000177100017500000000254413702133370021510 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off PINMISSING `ifdef T_GEN_MISSING_BAD foobar #(.FOO_TYPE(1)) foobar; // This means we should instatiate missing module `elsif T_GEN_MISSING foobar #(.FOO_TYPE(0)) foobar; // This means we should instatiate foo0 `else `error "Bad Test" `endif endmodule module foobar #( parameter FOO_START = 0, FOO_NUM = 2, FOO_TYPE = 1 ) ( input wire[FOO_NUM-1:0] foo, output wire[FOO_NUM-1:0] bar); generate begin: g genvar j; for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1) begin: foo_inst; if (FOO_TYPE == 0) begin: foo_0 // instatiate foo0 foo0 i_foo(.x(foo[j]), .y(bar[j])); end if (FOO_TYPE == 1) begin: foo_1 // instatiate foo1 foo_not_needed i_foo(.x(foo[j]), .y(bar[j])); end end end endgenerate endmodule module foo0(input wire x, output wire y); assign y = ~x; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_gate_unsup.v0000664000177100017500000000135413702133370021356 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); wire d, en, nc, pc; // verilator lint_off IMPLICIT cmos (cm0, d, nc, pc); rcmos (rc0, d, nc, pc); nmos (nm0, d, en); pmos (pm0, d, en); rnmos (rn0, d, en); rpmos (rp0, d, en); rtran (rt0, d); tran (tr0, d); rtranif0 (r00, d, en); rtranif1 (r10, d, en); tranif0 (t00, d, en); tranif1 (t10, d, en); // verilator lint_on IMPLICIT initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_pow4.v0000664000177100017500000000261213702133370021104 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Clifford Wolf. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; wire [31:0] y; reg a; test004 sub (/*AUTOINST*/ // Outputs .y (y[31:0]), // Inputs .a (a)); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d a=%x y=%x\n",$time, cyc, a, y); `endif cyc <= cyc + 1; if (cyc==0) begin a <= 0; end else if (cyc==1) begin a <= 1; if (y != 32'h0) $stop; end else if (cyc==2) begin if (y != 32'h010000ff) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module test004(a, y); input a; output [31:0] y; wire [7:0] y0; wire [7:0] y1; wire [7:0] y2; wire [7:0] y3; assign y = {y0,y1,y2,y3}; localparam [7:0] v0 = +8'sd1 ** -8'sd2; //'h01 localparam [7:0] v1 = +8'sd2 ** -8'sd2; //'h00 localparam [7:0] v2 = -8'sd2 ** -8'sd3; //'h00 localparam [7:0] v3 = -8'sd1 ** -8'sd3; //'hff localparam [7:0] zero = 0; initial $display("v0=%x v1=%x v2=%x v3=%x", v0,v1,v2,v3); assign y0 = a ? v0 : zero; assign y1 = a ? v1 : zero; assign y2 = a ? v2 : zero; assign y3 = a ? v3 : zero; endmodule verilator-4.038/test_regress/t/t_dpi_arg_input_type.cpp0000664000177100017500000004617413702133370023417 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_input_type__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL # define CONSTARG const #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define CONSTARG const #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL // Sadly NC does not declare pass-by reference input arguments as const # define CONSTARG #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; # define CONSTARG const #else # error "Unknown simulator for DPI test" #endif //====================================================================== // Implementations of imported functions //====================================================================== #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void check_bvals(CONSTARG svLogicVecVal* v, unsigned n); void check_bvals(CONSTARG svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { if (v[i].bval != 0) { printf(__FILE__ ":%d Bad svLogicVecVal bval\n", __LINE__); abort(); } } } // Basic types as per IEEE 1800-2017 35.5.6 void i_byte(char i) { static int n = 0; if (i != 10 - n++) stop(); } void i_byte_unsigned(unsigned char i) { static int n = 0; if (i != 20 - n++) stop(); } void i_shortint(short i) { static int n = 0; if (i != 30 - n++) stop(); } void i_shortint_unsigned(unsigned short i) { static int n = 0; if (i != 40 - n++) stop(); } void i_int(int i) { static int n = 0; if (i != 50 - n++) stop(); } void i_int_unsigned(unsigned i) { static int n = 0; if (i != 60 - n++) stop(); } void i_longint(sv_longint_t i) { static int n = 0; if (i != 70 - n++) stop(); } void i_longint_unsigned(sv_longint_unsigned_t i) { static int n = 0; if (i != 80 - n++) stop(); } #ifndef NO_TIME void i_time(CONSTARG svLogicVecVal* i) { static int n = 0; if (i[0].aval != 90 - n++) stop(); if (i[1].aval != 0) stop(); check_bvals(i, 2); } #endif #ifndef NO_INTEGER void i_integer(CONSTARG svLogicVecVal* i) { static int n = 0; if (i[0].aval != 100 - n++) stop(); check_bvals(i, 1); } #endif void i_real(double i) { static int n = 0; if (i != (-2.0 * n++ - 1.0) / 2.0) stop(); } #ifndef NO_SHORTREAL void i_shortreal(float i) { static int n = 0; if (i != (-4.0f * n++ - 1.0f) / 4.0f) stop(); } #endif void i_chandle(void* i) { static int n = 0; printf("i_chandle %d\n", n); if (i != NULL) stop(); n++; } void i_string(const char* i) { static int n = 0; printf("i_string %d\n", n); if (n++ % 2 == 0) { if (strcmp(i, "World") != 0) stop(); } else { if (strcmp(i, "Hello") != 0) stop(); } } void i_bit(svBit i) { static int n = 0; printf("i_bit %d\n", n); if (i != !(n++ % 2)) stop(); } void i_logic(svLogic i) { static int n = 0; printf("i_logic %d\n", n); if (i != n++ % 2) stop(); } // Basic types via typedefs void i_byte_t(char i) { static int n = 0; if (i != 10 - n) stop(); n += 2; } void i_byte_unsigned_t(unsigned char i) { static int n = 0; if (i != 20 - n) stop(); n += 2; } void i_shortint_t(short i) { static int n = 0; if (i != 30 - n) stop(); n += 2; } void i_shortint_unsigned_t(unsigned short i) { static int n = 0; if (i != 40 - n) stop(); n += 2; } void i_int_t(int i) { static int n = 0; if (i != 50 - n) stop(); n += 2; } void i_int_unsigned_t(unsigned i) { static int n = 0; if (i != 60 - n) stop(); n += 2; } void i_longint_t(sv_longint_t i) { static int n = 0; if (i != 70 - n) stop(); n += 2; } void i_longint_unsigned_t(sv_longint_unsigned_t i) { static int n = 0; if (i != 80 - n) stop(); n += 2; } #ifndef NO_TIME void i_time_t(CONSTARG svLogicVecVal* i) { static int n = 0; if (i[0].aval != 90 - n) stop(); if (i[1].aval != 0) stop(); check_bvals(i, 2); n += 2; } #endif #ifndef NO_INTEGER void i_integer_t(CONSTARG svLogicVecVal* i) { static int n = 0; if (i[0].aval != 100 - n) stop(); check_bvals(i, 1); n += 2; } #endif void i_real_t(double i) { static int n = 0; if (i != (-2.0 * n - 1.0) / 2.0) stop(); n += 2; } #ifndef NO_SHORTREAL void i_shortreal_t(float i) { static int n = 0; if (i != (-4.0f * n - 1.0f) / 4.0f) stop(); n += 2; } #endif void i_chandle_t(void* i) { static int n = 0; printf("i_chandle_t %d\n", n); if (i != NULL) stop(); n++; } void i_string_t(const char* i) { static int n = 0; printf("i_string_t %d\n", n); if (n++ % 2 == 0) { if (strcmp(i, "World") != 0) stop(); } else { if (strcmp(i, "Hello") != 0) stop(); } } void i_bit_t(svBit i) { static int n = 0; printf("i_bit_t %d\n", n); if (i != !(n++ % 2)) stop(); } void i_logic_t(svLogic i) { static int n = 0; printf("i_logic_t %d\n", n); if (i != n++ % 2) stop(); } // 2-state packed arrays void i_array_2_state_1(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_1 %d\n", n); if ((*i & 1) != !(n++ % 2)) stop(); } void i_array_2_state_32(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_32 %d\n", n); if (*i != 0xffffffffU << n++) stop(); } void i_array_2_state_33(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_33 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if ((i[1] & 1) != 1) stop(); } void i_array_2_state_64(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_64 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); } void i_array_2_state_65(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_65 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if ((i[2] & 1) != 1) stop(); } void i_array_2_state_128(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_128 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if (i[2] != -1) stop(); if (i[3] != -1) stop(); } // 2-state packed structures void i_struct_2_state_1(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_1 %d\n", n); if ((*i & 1) != !(n++ % 2)) stop(); } void i_struct_2_state_32(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_32 %d\n", n); if (*i != 0xffffffffU << n++) stop(); } void i_struct_2_state_33(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_33 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if ((i[1] & 1) != 1) stop(); } void i_struct_2_state_64(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_64 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); } void i_struct_2_state_65(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_65 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if ((i[2] & 1) != 1) stop(); } void i_struct_2_state_128(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_128 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if (i[2] != -1) stop(); if (i[3] != -1) stop(); } // 2-state packed unions void i_union_2_state_1(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_1 %d\n", n); if ((*i & 1) != !(n++ % 2)) stop(); } void i_union_2_state_32(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_32 %d\n", n); if (*i != 0xffffffffU << n++) stop(); } void i_union_2_state_33(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_33 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if ((i[1] & 1) != 1) stop(); } void i_union_2_state_64(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_64 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); } void i_union_2_state_65(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_65 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if ((i[2] & 1) != 1) stop(); } void i_union_2_state_128(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_128 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if (i[2] != -1) stop(); if (i[3] != -1) stop(); } // 4-state packed arrays void i_array_4_state_1(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_1 %d\n", n); if ((i->aval & 1) != !(n++ % 2)) stop(); check_bvals(i, 1); } void i_array_4_state_32(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_32 %d\n", n); if (i->aval != 0xffffffffU << n++) stop(); check_bvals(i, 1); } void i_array_4_state_33(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_33 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if ((i[1].aval & 1) != 1) stop(); check_bvals(i, 2); } void i_array_4_state_64(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_64 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); check_bvals(i, 2); } void i_array_4_state_65(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_65 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if ((i[2].aval & 1) != 1) stop(); check_bvals(i, 3); } void i_array_4_state_128(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_128 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if (i[2].aval != -1) stop(); if (i[3].aval != -1) stop(); check_bvals(i, 4); } // 4-state packed structures void i_struct_4_state_1(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_1 %d\n", n); if ((i->aval & 1) != !(n++ % 2)) stop(); check_bvals(i, 1); } void i_struct_4_state_32(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_32 %d\n", n); if (i->aval != 0xffffffffU << n++) stop(); check_bvals(i, 1); } void i_struct_4_state_33(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_33 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if ((i[1].aval & 1) != 1) stop(); check_bvals(i, 2); } void i_struct_4_state_64(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_64 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); check_bvals(i, 2); } void i_struct_4_state_65(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_65 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if ((i[2].aval & 1) != 1) stop(); check_bvals(i, 3); } void i_struct_4_state_128(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_128 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if (i[2].aval != -1) stop(); if (i[3].aval != -1) stop(); check_bvals(i, 4); } // 4-state packed unions void i_union_4_state_1(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_1 %d\n", n); if ((i->aval & 1) != !(n++ % 2)) stop(); check_bvals(i, 1); } void i_union_4_state_32(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_32 %d\n", n); if (i->aval != 0xffffffffU << n++) stop(); check_bvals(i, 1); } void i_union_4_state_33(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_33 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if ((i[1].aval & 1) != 1) stop(); check_bvals(i, 2); } void i_union_4_state_64(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_64 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); check_bvals(i, 2); } void i_union_4_state_65(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_65 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if ((i[2].aval & 1) != 1) stop(); check_bvals(i, 3); } void i_union_4_state_128(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_128 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if (i[2].aval != -1) stop(); if (i[3].aval != -1) stop(); check_bvals(i, 4); } //====================================================================== // Check exported functions //====================================================================== void set_bvals(svLogicVecVal* v, unsigned n); void set_bvals(svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { v[i].bval = 0; } } void check_exports() { static int n = 0; #ifndef NO_TIME svLogicVecVal x_time[2]; svLogicVecVal x_time_t[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer[1]; svLogicVecVal x_integer_t[1]; #endif #ifndef NO_TIME set_bvals(x_time, 2); set_bvals(x_time_t, 2); #endif #ifndef NO_INTEGER set_bvals(x_integer, 1); set_bvals(x_integer_t, 1); #endif // Basic types as per IEEE 1800-2017 35.5.6 e_byte(10 + n); e_byte_unsigned(20 + n); e_shortint(30 + n); e_shortint_unsigned(40 + n); e_int(50 + n); e_int_unsigned(60 + n); e_longint(70 + n); e_longint_unsigned(80 + n); #ifndef NO_TIME x_time[0].aval = 90 + n; x_time[1].aval = 0; e_time(x_time); #endif #ifndef NO_INTEGER x_integer[0].aval = 100 + n; e_integer(x_integer); #endif e_real(1.0 * n + 0.5); #ifndef NO_SHORTREAL e_shortreal(1.0f * n + 0.25f); #endif e_chandle((n % 2) ? reinterpret_cast(&e_chandle) : NULL); e_string((n % 2) ? "World" : "Hello"); e_bit(n % 2); e_logic(!(n % 2)); // Basic types via tyepdef e_byte_t(10 + 2 * n); e_byte_unsigned_t(20 + 2 * n); e_shortint_t(30 + 2 * n); e_shortint_unsigned_t(40 + 2 * n); e_int_t(50 + 2 * n); e_int_unsigned_t(60 + 2 * n); e_longint_t(70 + 2 * n); e_longint_unsigned_t(80 + 2 * n); #ifndef NO_TIME x_time_t[0].aval = 90 + 2 * n; x_time_t[1].aval = 0; e_time_t(x_time_t); #endif #ifndef NO_INTEGER x_integer_t[0].aval = 100 + 2 * n; e_integer_t(x_integer_t); #endif e_real_t(1.0 * (2 * n) + 0.5); #ifndef NO_SHORTREAL e_shortreal_t(1.0f * (2 * n) + 0.25f); #endif e_chandle_t((n % 2) ? NULL : reinterpret_cast(&e_chandle_t)); e_string_t((n % 2) ? "Hello" : "World"); e_bit_t(n % 2); e_logic_t(!(n % 2)); const int m = n == 0 ? 0 : n - 1; svBitVecVal b1[1]; svBitVecVal b2[2]; svBitVecVal b3[3]; svBitVecVal b4[4]; b3[0] = 0xffffffff; b4[0] = 0xffffffff; b4[1] = 0xffffffff; b4[2] = 0xffffffff; // 2-state packed arrays b1[0] = n % 2; e_array_2_state_1(b1); b1[0] = 0xffffffff >> n; e_array_2_state_32(b1); b2[1] = 1 >> n; b2[0] = 0xffffffff >> m; e_array_2_state_33(b2); b2[1] = 0xffffffff >> n; b2[0] = 0xffffffff; e_array_2_state_64(b2); b3[2] = 1 >> n; b3[1] = 0xffffffff >> m; e_array_2_state_65(b3); b4[3] = 0xffffffff >> n; e_array_2_state_128(b4); // 2-state packed structures b1[0] = n % 2; e_struct_2_state_1(b1); b1[0] = 0xffffffff >> n; e_struct_2_state_32(b1); b2[1] = 1 >> n; b2[0] = 0xffffffff >> m; e_struct_2_state_33(b2); b2[1] = 0xffffffff >> n; b2[0] = 0xffffffff; e_struct_2_state_64(b2); b3[2] = 1 >> n; b3[1] = 0xffffffff >> m; e_struct_2_state_65(b3); b4[3] = 0xffffffff >> n; e_struct_2_state_128(b4); // 2-state packed unions b1[0] = n % 2; e_union_2_state_1(b1); b1[0] = 0xffffffff >> n; e_union_2_state_32(b1); b2[1] = 1 >> n; b2[0] = 0xffffffff >> m; e_union_2_state_33(b2); b2[1] = 0xffffffff >> n; b2[0] = 0xffffffff; e_union_2_state_64(b2); b3[2] = 1 >> n; b3[1] = 0xffffffff >> m; e_union_2_state_65(b3); b4[3] = 0xffffffff >> n; e_union_2_state_128(b4); svLogicVecVal l1[1]; svLogicVecVal l2[2]; svLogicVecVal l3[3]; svLogicVecVal l4[4]; // bvals should be ignored, leave them un-initialized set_bvals(l1, 1); set_bvals(l2, 2); set_bvals(l3, 3); set_bvals(l4, 4); l3[0].aval = 0xffffffff; l4[0].aval = 0xffffffff; l4[1].aval = 0xffffffff; l4[2].aval = 0xffffffff; // 4-state packed arrays l1[0].aval = n % 2; e_array_4_state_1(l1); l1[0].aval = 0xffffffff >> n; e_array_4_state_32(l1); l2[1].aval = 1 >> n; l2[0].aval = 0xffffffff >> m; e_array_4_state_33(l2); l2[1].aval = 0xffffffff >> n; l2[0].aval = 0xffffffff; e_array_4_state_64(l2); l3[2].aval = 1 >> n; l3[1].aval = 0xffffffff >> m; e_array_4_state_65(l3); l4[3].aval = 0xffffffff >> n; e_array_4_state_128(l4); // 4-state packed structures l1[0].aval = n % 2; e_struct_4_state_1(l1); l1[0].aval = 0xffffffff >> n; e_struct_4_state_32(l1); l2[1].aval = 1 >> n; l2[0].aval = 0xffffffff >> m; e_struct_4_state_33(l2); l2[1].aval = 0xffffffff >> n; l2[0].aval = 0xffffffff; e_struct_4_state_64(l2); l3[2].aval = 1 >> n; l3[1].aval = 0xffffffff >> m; e_struct_4_state_65(l3); l4[3].aval = 0xffffffff >> n; e_struct_4_state_128(l4); // 4-state packed unions l1[0].aval = n % 2; e_union_4_state_1(l1); l1[0].aval = 0xffffffff >> n; e_union_4_state_32(l1); l2[1].aval = 1 >> n; l2[0].aval = 0xffffffff >> m; e_union_4_state_33(l2); l2[1].aval = 0xffffffff >> n; l2[0].aval = 0xffffffff; e_union_4_state_64(l2); l3[2].aval = 1 >> n; l3[1].aval = 0xffffffff >> m; e_union_4_state_65(l3); l4[3].aval = 0xffffffff >> n; e_union_4_state_128(l4); n++; } verilator-4.038/test_regress/t/t_delay_stmtdly_bad.pl0000775000177100017500000000121413702133370023034 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_delay.v"); lint( verilator_flags2 => ['-Wall -Wno-DECLFILENAME'], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_shift_over_bad.out0000664000177100017500000000044613702133370023536 0ustar wsnyderwsnyder%Error: t/t_math_shift_over_bad.v:19:20: Value too wide for 32-bits expected in this context 64'h123456789abcdef : ... In instance t 19 | assign o = i << 64'h01234567_89abcdef; | ^~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_gate_lvalue_const.v0000664000177100017500000000261713702133370022705 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, rst ); input clk; input rst; logic [2:0] ctrl_inc_single; logic [2:0] ctrl_inc_double; logic [2:0] cnt_single; always_ff @(posedge clk) begin if (rst) begin cnt_single <= '0; end else if (ctrl_inc_single != '0 && cnt_single != '1) begin cnt_single <= cnt_single + 1'd1; end end logic [2:0] cnt_double; always_ff @(posedge clk) begin if (rst) begin cnt_double <= '0; end else if (ctrl_inc_double != '0 && cnt_double != '1) begin cnt_double <= cnt_double + 1'd1; end end always_comb ctrl_inc_single = '0; always_comb ctrl_inc_double = '0; testMod test_i (.data_i(cnt_single)); testMod test_j (.data_i(cnt_double)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module testMod (input wire [2:0] data_i); typedef logic [63:0] time_t; time_t [2:0] last_transition; genvar b; generate for (b = 0; b <= 2; b++) begin : gen_trans always_ff @(posedge data_i[b] or negedge data_i[b]) begin last_transition[b] <= $time; end end endgenerate endmodule verilator-4.038/test_regress/t/t_flag_woff.v0000664000177100017500000000101513702133370021130 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // width warnings off due to command line wire A = 15'd1234; // width warnings off due to command line + manual switch // verilator lint_off WIDTH wire B = 15'd1234; // this turnon does nothing as off on command line // verilator lint_on WIDTH wire C = 15'd1234; endmodule verilator-4.038/test_regress/t/t_func_tie_bad.out0000664000177100017500000000026513702133370022150 0ustar wsnyderwsnyder%Error: t/t_func_tie_bad.v:11:15: Function/task output connected to constant instead of variable: 'b' 11 | func(0, 1'b1); | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_concat_large_bad.pl0000775000177100017500000000107413702133367022611 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_unsized_bad.out0000664000177100017500000000057413702133370023066 0ustar wsnyderwsnyder%Error: t/t_lint_unsized_bad.v:8:22: Too many digits for 32 bit number: 'd123456789123456789123456789 ... As that number was unsized ('d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1) ... Suggest adding a size to it. 8 | bit [256:0] num = 'd123456789123456789123456789; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_cover_sva_notflat.pl0000775000177100017500000000165013702133370023072 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert --cc --coverage-user'], ); execute( check_finished => 1, ); #if ($Self->{nc}) ... # See t_assert_cover.pl for NC version # Allow old Perl format dump, or new binary dump # Check that the hierarchy doesn't include __PVT__ # Otherwise our coverage reports would look really ugly if ($Self->{vlt_all}) { file_grep($Self->{coverage_filename}, qr/(top\.t\.sub.*.cyc_eq_5)/) } ok(1); 1; verilator-4.038/test_regress/t/t_f_bad.pl0000775000177100017500000000117413702133370020410 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -f file_will_not_exist.vc"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_typedef_param.pl0000775000177100017500000000105313702133370022171 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_altera_lpm_mux.pl0000775000177100017500000000120613702133367022370 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_mailbox_parse.pl0000775000177100017500000000110613702133370022175 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t_mailbox.v"); lint( verilator_flags2 => ["--debug-exit-parse"], ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_param_another_bad.v0000664000177100017500000000070213702133370024646 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 module t (); simple_bus sb_intf(); simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule interface simple_bus #(PARAMETER = 0); logic dummy; endinterface verilator-4.038/test_regress/t/t_past_bad.v0000664000177100017500000000064013702133370020756 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (d, clk); input d; input clk; always @ (posedge clk) begin if ($past(d, 0)) $stop; // IEEE 16.9.3 must be >- 0 if ($past(d, 10000)) $stop; // TICKCOUNT end endmodule verilator-4.038/test_regress/t/t_gen_mislevel.v0000664000177100017500000000130013702133370021644 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 /// We define the modules in "backward" order. module d; endmodule module b; generate if (1) begin c c1 (); c c2 (); end endgenerate endmodule module c; generate if (1) begin d d1 (); d d2 (); end endgenerate endmodule module a; generate if (1) begin b b1 (); b b2 (); end endgenerate endmodule module t (/*AUTOARG*/); a a1 (); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_asvar_bad.out0000664000177100017500000000100513702133370023501 0ustar wsnyderwsnyder%Error: t/t_interface_asvar_bad.v:29:16: Operator ASSIGN expected non-interface on Assign RHS but 'itf' is an interface. : ... In instance t.source 29 | getter = itf; | ^~~ %Error: t/t_interface_asvar_bad.v:30:23: Operator ADD expected non-interface on RHS but 'itf' is an interface. : ... In instance t.source 30 | getter = 4'd3 + itf; | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_sys_readmem_bad_end.mem0000664000177100017500000000057513702133370023465 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 00 01 10 // Missing additional data verilator-4.038/test_regress/t/t_interface_down_gen.pl0000775000177100017500000000133613702133370023175 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, interface generates changing types"); $Self->{vcs} and unsupported("Commercially unsupported, interface crossrefs"); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_bind2.pl0000775000177100017500000000105313702133367020355 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_defparam.v0000664000177100017500000000047513702133370022014 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub (); defparam sub.P = 2; endmodule module sub; parameter P = 6; endmodule verilator-4.038/test_regress/t/t_inst_slice_noinl.pl0000775000177100017500000000115413702133370022706 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_slice.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_default_bad.v0000664000177100017500000000067013702133367022437 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [3:0] value; always @ (/*AS*/value) begin case (value) default: $stop; 4'd0000: $stop; default: $stop; endcase end endmodule verilator-4.038/test_regress/t/t_var_xref_gen.pl0000775000177100017500000000105513702133370022020 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--debug-check"], ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_recurse2_bad.v0000664000177100017500000000056313702133370022602 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; looped looped (); endmodule module looped (/*AUTOARG*/); looped looped (); endmodule verilator-4.038/test_regress/t/t_mem_slice_dtype_bad.pl0000775000177100017500000000107413702133370023324 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_synth_parallel.out0000664000177100017500000000025213702133367024152 0ustar wsnyderwsnyder[40] %Error: t_assert_synth.v:50: Assertion failed in top.t: synthesis parallel_case, but multiple matches found %Error: t/t_assert_synth.v:50: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_var_ref_noinline.pl0000775000177100017500000000116313702133370022672 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 top_filename("t/t_var_ref.v"); scenarios(simulator => 1); compile( v_flags2 => ['+define+T_NOINLINE'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_public.cpp0000664000177100017500000000131613702133370022021 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include "Vt_enum_public.h" #include "Vt_enum_public_p3.h" #include "Vt_enum_public_p62.h" int main(int argc, char* argv[]) { Vt_enum_public* topp = new Vt_enum_public; Verilated::debug(0); // Make sure public tag worked if (Vt_enum_public_p3::ZERO == Vt_enum_public_p3::ONE) {} if (Vt_enum_public_p62::ZERO == Vt_enum_public_p62::ALLONE) {} for (int i = 0; i < 10; i++) { topp->eval(); } } verilator-4.038/test_regress/t/t_lint_restore_prag_bad.pl0000775000177100017500000000107613702133370023706 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_pinsizes.cpp0000664000177100017500000000111213702133370022225 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = NULL; double sc_time_stamp() { return 0; } int main() { Verilated::debug(0); tb = new VM_PREFIX("tb"); VL_PRINTF("*-* All Finished *-*\n"); tb->final(); return 0; } int sc_main(int argc, char* argv[]) { tb = new VM_PREFIX("tb"); VL_PRINTF("*-* All Finished *-*\n"); tb->final(); return 0; } verilator-4.038/test_regress/t/t_tri_pull_bad.out0000664000177100017500000000053713702133370022210 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_tri_pull_bad.v:13:13: Unsupported: Conflicting pull directions. : ... In instance t 13 | pulldown p2(A); | ^~ t/t_tri_pull_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p1(A); | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_clk_dsp.v0000664000177100017500000000732313702133367020633 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off GENCLK reg [7:0] cyc; initial cyc=0; reg [7:0] padd; reg dsp_ph1, dsp_ph2, dsp_reset; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] out; // From dspchip of t_dspchip.v // End of automatics t_dspchip dspchip (/*AUTOINST*/ // Outputs .out (out[7:0]), // Inputs .dsp_ph1 (dsp_ph1), .dsp_ph2 (dsp_ph2), .dsp_reset (dsp_reset), .padd (padd[7:0])); always @ (posedge clk) begin $write("cyc %d\n",cyc); if (cyc == 8'd0) begin cyc <= 8'd1; dsp_reset <= 0; // Need a posedge padd <= 0; end else if (cyc == 8'd20) begin $write("*-* All Finished *-*\n"); $finish; end else begin cyc <= cyc + 8'd1; dsp_ph1 <= ((cyc&8'd3) == 8'd0); dsp_ph2 <= ((cyc&8'd3) == 8'd2); dsp_reset <= (cyc == 8'd1); padd <= cyc; //$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out); case (cyc) default: $stop; 8'd01: ; 8'd02: ; 8'd03: ; 8'd04: ; 8'd05: ; 8'd06: ; 8'd07: ; 8'd08: ; 8'd09: if (out!==8'h04) $stop; 8'd10: if (out!==8'h04) $stop; 8'd11: if (out!==8'h08) $stop; 8'd12: if (out!==8'h08) $stop; 8'd13: if (out!==8'h00) $stop; 8'd14: if (out!==8'h00) $stop; 8'd15: if (out!==8'h00) $stop; 8'd16: if (out!==8'h00) $stop; 8'd17: if (out!==8'h0c) $stop; 8'd18: if (out!==8'h0c) $stop; 8'd19: if (out!==8'h10) $stop; endcase end end endmodule module t_dspchip (/*AUTOARG*/ // Outputs out, // Inputs dsp_ph1, dsp_ph2, dsp_reset, padd ); input dsp_ph1, dsp_ph2, dsp_reset; input [7:0] padd; output [7:0] out; wire dsp_ph1, dsp_ph2; wire [7:0] out; wire pla_ph1, pla_ph2; wire out1_r; wire [7:0] out2_r, padd; wire clk_en; t_dspcore t_dspcore (/*AUTOINST*/ // Outputs .out1_r (out1_r), .pla_ph1 (pla_ph1), .pla_ph2 (pla_ph2), // Inputs .dsp_ph1 (dsp_ph1), .dsp_ph2 (dsp_ph2), .dsp_reset (dsp_reset), .clk_en (clk_en)); t_dsppla t_dsppla (/*AUTOINST*/ // Outputs .out2_r (out2_r[7:0]), // Inputs .pla_ph1 (pla_ph1), .pla_ph2 (pla_ph2), .dsp_reset (dsp_reset), .padd (padd[7:0])); assign out = out1_r ? 8'h00 : out2_r; assign clk_en = 1'b1; endmodule module t_dspcore (/*AUTOARG*/ // Outputs out1_r, pla_ph1, pla_ph2, // Inputs dsp_ph1, dsp_ph2, dsp_reset, clk_en ); input dsp_ph1, dsp_ph2, dsp_reset; input clk_en; output out1_r, pla_ph1, pla_ph2; wire dsp_ph1, dsp_ph2, dsp_reset; wire pla_ph1, pla_ph2; reg out1_r; always @(posedge dsp_ph1 or posedge dsp_reset) begin if (dsp_reset) out1_r <= 1'h0; else out1_r <= ~out1_r; end assign pla_ph1 = dsp_ph1; assign pla_ph2 = dsp_ph2 & clk_en; endmodule module t_dsppla (/*AUTOARG*/ // Outputs out2_r, // Inputs pla_ph1, pla_ph2, dsp_reset, padd ); input pla_ph1, pla_ph2, dsp_reset; input [7:0] padd; output [7:0] out2_r; wire pla_ph1, pla_ph2, dsp_reset; wire [7:0] padd; reg [7:0] out2_r; reg [7:0] latched_r; always @(posedge pla_ph1 or posedge dsp_reset) begin if (dsp_reset) latched_r <= 8'h00; else latched_r <= padd; end always @(posedge pla_ph2 or posedge dsp_reset) begin if (dsp_reset) out2_r <= 8'h00; else out2_r <= latched_r; end endmodule verilator-4.038/test_regress/t/t_unoptflat_simple_3_bad.pl0000775000177100017500000000111213702133370023762 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_unoptflat_simple_3.v"); # Compile only compile( fails => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_array_list_bad.v0000664000177100017500000000172013702133367022166 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef struct packed { logic t1; logic t2; logic t3; } type_t; endpackage : pkg module t ( input logic sys_clk, input logic sys_rst_n, input logic sys_ena, input pkg::type_t test_in, output pkg::type_t test_out ); import pkg::*; always_ff @(posedge sys_clk or negedge sys_rst_n) begin if (~sys_rst_n) begin test_out <= '{'0, '0, '0}; end else begin if(sys_ena) begin test_out.t1 <= ~test_in.t1; test_out.t2 <= ~test_in.t2; test_out.t3 <= ~test_in.t3; end else begin test_out <= '{'0, '0}; /* Inconsistent array list; */ end end end endmodule: t verilator-4.038/test_regress/t/t_gen_intdot2.pl0000775000177100017500000000105313702133370021565 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_vams.pl0000775000177100017500000000123613702133370021156 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_bitsel_struct3.v0000664000177100017500000000270713702133367022166 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test case for struct signal bit selection. // // This test is to check that bit selection of multi-dimensional signal inside // of a packed struct works. Currently +: and -: blow up with packed structs. // // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2013 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t(/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { logic [15:0] channel; logic [15:0] others; } buss_t; buss_t b; reg [7:0] a; reg [7:0] c; reg [7:0] d; union packed { logic [31:0] [7:0] idx; struct packed { logic [15:0] z, y, x; logic [25:0] [7:0] r; } nam; } gpr; reg [14:0] gpr_a; initial begin b = {16'h8765,16'h4321}; a = b[19:12]; // This works c = b[8+:8]; // This fails d = b[11-:8]; // This fails `checkh(a, 8'h54); `checkh(c, 8'h43); `checkh(d, 8'h32); gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345; `checkh (gpr[255:255-14], 15'h091a); gpr_a = gpr.nam.z[15:1]; `checkh (gpr_a, 15'h091a); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_dpi_import.pl0000775000177100017500000000132113702133370021515 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( # Amazingly VCS, NC and Verilator all just accept the C file here! v_flags2 => ["t/t_dpi_import_c.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_packed_write_read.v0000664000177100017500000002355213702133367024050 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // parameters for array sizes localparam WA = 8; // address dimension size localparam WB = 8; // bit dimension size localparam NO = 10; // number of access events // 2D packed arrays logic [WA-1:0] [WB-1:0] array_bg; // big endian array /* verilator lint_off LITENDIAN */ logic [0:WA-1] [0:WB-1] array_lt; // little endian array /* verilator lint_on LITENDIAN */ integer cnt = 0; // msg926 logic [3:0][31:0] packedArray; initial packedArray = '0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin $write("*-* All Finished *-*\n"); $finish; end // big endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) array_bg <= '0; else if (cnt[30:2]==1) array_bg <= '0; else if (cnt[30:2]==2) array_bg <= '0; else if (cnt[30:2]==3) array_bg <= '0; else if (cnt[30:2]==4) array_bg <= '0; else if (cnt[30:2]==5) array_bg <= '0; else if (cnt[30:2]==6) array_bg <= '0; else if (cnt[30:2]==7) array_bg <= '0; else if (cnt[30:2]==8) array_bg <= '0; else if (cnt[30:2]==9) array_bg <= '0; end else if (cnt[1:0]==2'd1) begin // write value to array if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) array_bg <= {WA *WB +0{1'b1}}; else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==3) array_bg [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==4) array_bg [ 0 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==5) array_bg [WA -1 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; end else if (cnt[1:0]==2'd2) begin // check array value if (cnt[30:2]==0) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]==2) begin if (array_bg !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]==3) begin if (array_bg !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]==4) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]==5) begin if (array_bg !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]==6) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]==8) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]==9) begin if (array_bg !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from array (not a very good test for now) if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end end // little endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) array_lt <= '0; else if (cnt[30:2]==1) array_lt <= '0; else if (cnt[30:2]==2) array_lt <= '0; else if (cnt[30:2]==3) array_lt <= '0; else if (cnt[30:2]==4) array_lt <= '0; else if (cnt[30:2]==5) array_lt <= '0; else if (cnt[30:2]==6) array_lt <= '0; else if (cnt[30:2]==7) array_lt <= '0; else if (cnt[30:2]==8) array_lt <= '0; else if (cnt[30:2]==9) array_lt <= '0; end else if (cnt[1:0]==2'd1) begin // write value to array if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) array_lt <= {WA *WB +0{1'b1}}; else if (cnt[30:2]==2) array_lt [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==3) array_lt [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==4) array_lt [0 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==5) array_lt [ WA -1] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==8) array_lt [0 ][0 ] <= {1 *1 +0{1'b1}}; else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; end else if (cnt[1:0]==2'd2) begin // check array value if (cnt[30:2]==0) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==2) begin if (array_lt !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==3) begin if (array_lt !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==4) begin if (array_lt !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==5) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==7) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==8) begin if (array_lt !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==9) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_lt); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from array (not a very good test for now) if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end end endmodule verilator-4.038/test_regress/t/t_hierarchy_identifier_bad.out0000664000177100017500000000212313702133370024527 0ustar wsnyderwsnyder%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:34:10: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' 34 | end : if_cnt_finish_bad | ^~~~~~~~~~~~~~~~~ ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message. %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:40:10: End label 'generate_for_bad' does not match begin label 'generate_for' 40 | end : generate_for_bad | ^~~~~~~~~~~~~~~~ %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:47:10: End label 'generate_if_if_bad' does not match begin label 'generate_if_if' 47 | end : generate_if_if_bad | ^~~~~~~~~~~~~~~~~~ %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:51:10: End label 'generate_if_else_bad' does not match begin label 'generate_if_else' 51 | end : generate_if_else_bad | ^~~~~~~~~~~~~~~~~~~~ %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:54:13: End label 't_bad' does not match begin label 't' 54 | endmodule : t_bad | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_timescale_parse_bad.pl0000775000177100017500000000111313702133370023314 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_inout2.v0000664000177100017500000000274213702133370021304 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [2:0] in; wire a,y,y_fixed; wire b = in[0]; wire en = in[1]; pullup(a); ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) ); initial in=0; // Test loop always @ (posedge clk) begin in <= in + 1; $display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed); if (en) begin // driving b // a should be b // y and yfix should also be b if (a!=b || y != b || y_fixed != b) begin $display ( "Expected a %d y %b yfix %b" , a, y, y_fixed); $stop; end end else begin // not driving b // a should be 1 (pullup) // y and yfix shold be 1 if (a!=1 || y != 1 || y_fixed != 1) begin $display( "Expected a,y,yfix == 1"); $stop; end end if (in==3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module ChildA(inout A, input B, input en, output Y, output Yfix); // workaround wire a_in = A; ChildB childB(.A(A), .Y(Y)); assign A = en ? B : 1'bz; ChildB childBfix(.A(a_in),.Y(Yfix)); endmodule module ChildB(input A, output Y); assign Y = A; endmodule verilator-4.038/test_regress/t/t_struct_unpacked2.pl0000775000177100017500000000111313702133370022626 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_recurse_bad.v0000664000177100017500000000066313702133370022521 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; looped looped (); endmodule module looped (/*AUTOARG*/); looped2 looped2 (); endmodule module looped2 (/*AUTOARG*/); looped looped (); endmodule verilator-4.038/test_regress/t/t_param_array3.v0000664000177100017500000000142613702133370021565 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter int SIZES [3:0] = '{1,2,3,4}; typedef int calc_sums_t [3:0]; function calc_sums_t calc_sums; int sum = 0; for (int i=0; i<4; i++) begin sum = sum + SIZES[i]; calc_sums[i] = sum; //TODO: calc_sums[i][31:0] = sum; end endfunction parameter int SUMS[3:0] = calc_sums(); initial begin if (SUMS[0] != 4) $stop; if (SUMS[1] != 4+3) $stop; if (SUMS[2] != 4+3+2) $stop; if (SUMS[3] != 4+3+2+1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_equal.v0000664000177100017500000000323413702133370021323 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; reg _guard1; reg [127:0] r_wide0; reg _guard2; wire [63:0] r_wide1; reg _guard3; reg _guard4; reg _guard5; reg _guard6; assign r_wide1 = r_wide0[127:64]; // surefire lint_off STMINI initial _mode = 0; always @ (posedge clk) begin if (_mode==0) begin $write("[%0t] t_equal: Running\n", $time); _guard1 <= 0; _guard2 <= 0; _guard3 <= 0; _guard4 <= 0; _guard5 <= 0; _guard6 <= 0; _mode<=1; r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; end else if (_mode==1) begin _mode<=2; // if (5'd10 != 5'b1010) $stop; if (5'd10 != 5'd10) $stop; if (5'd10 != 5'ha) $stop; if (5'd10 != 5'o12) $stop; if (5'd10 != 5'B 1010) $stop; if (5'd10 != 5'D10) $stop; if (5'd10 != 5'H a) $stop; if (5'd10 != 5 'O 12) $stop; if (24'h29cbb8 != 24'o12345670) $stop; if (6'b111xxx !== 6'o7x) $stop; if (6'b111??? !== 6'o7?) $stop; if (6'b111zzz !== 6'o7z) $stop; // if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_trace_two_port_cc.out0000664000177100017500000000271213702133370023245 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sat Mar 7 18:38:11 2020 $end $timescale 1ps $end $scope module topa $end $var wire 1 3 clk $end $scope module t $end $var wire 32 + c_trace_on [31:0] $end $var wire 1 3 clk $end $var wire 32 # cyc [31:0] $end $scope module sub $end $var wire 32 ; inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #10 b00000000000000000000000000000001 # b00000000000000000000000000000000 + 13 b00000000000000000000000000000001 ; #10 #15 #15 03 #20 #20 b00000000000000000000000000000010 # b00000000000000000000000000000011 + 13 #25 #25 03 #30 #30 b00000000000000000000000000000011 # b00000000000000000000000000000100 + 13 #35 #35 03 #40 #40 b00000000000000000000000000000100 # b00000000000000000000000000000101 + 13 #45 #45 03 #50 #50 b00000000000000000000000000000101 # b00000000000000000000000000000110 + 13 #55 #55 03 #60 #60 b00000000000000000000000000000110 # b00000000000000000000000000000111 + 13 #65 #65 03 #70 #70 b00000000000000000000000000000111 # b00000000000000000000000000001000 + 13 #75 #75 03 #80 #80 b00000000000000000000000000001000 # b00000000000000000000000000001001 + 13 #85 #85 03 #90 #90 b00000000000000000000000000001001 # b00000000000000000000000000001010 + 13 #95 #95 03 #100 #100 b00000000000000000000000000001010 # b00000000000000000000000000001011 + 13 #105 #105 03 #110 #110 13 b00000000000000000000000000001011 # b00000000000000000000000000001100 + verilator-4.038/test_regress/t/t_unroll_forfor.pl0000775000177100017500000000105313702133370022241 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_foreach_bad.pl0000775000177100017500000000107413702133370021571 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_param2.pl0000775000177100017500000000115713702133370022560 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug1104"); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_package.v0000664000177100017500000000110613702133370021752 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; Test0 t0 (.val0('0)); Test1 t1 (.val1('0)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule package params; parameter P = 7; endpackage module Test0 (val0); parameter Z = 1; input [Z : 0] val0; endmodule module Test1 (val1); input logic [params::P : 0] val1; // Fully qualified parameter endmodule verilator-4.038/test_regress/t/t_dpi_name_bad.pl0000775000177100017500000000111313702133370021730 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface1_noinl.pl0000775000177100017500000000115413702133370022573 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface1.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gate_unsup.pl0000775000177100017500000000111713702133370021524 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( # Unsupported: UDP Tables verilator_flags2 => ["--lint-only --bbox-unsup"], ); ok(1); 1; verilator-4.038/test_regress/t/t_param_chain.pl0000775000177100017500000000105313702133370021613 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_libinc.v0000664000177100017500000000105613702133370021434 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module liblib_a (/*AUTOARG*/); liblib_b b (); endmodule module liblib_b (/*AUTOARG*/); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module liblib_c (/*AUTOARG*/); // Unused initial $stop; liblib_d d (); endmodule module liblib_d (/*AUTOARG*/); // Unused initial $stop; endmodule verilator-4.038/test_regress/t/t_clk_first_deprecated.v0000664000177100017500000000046713702133367023356 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk /*verilator sc_clock*/; endmodule verilator-4.038/test_regress/t/t_interface_gen11.v0000664000177100017500000000131313702133370022132 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); logic val; function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t2(intf mod_intfs [1:0]); generate begin t1 t(.mod_intf(mod_intfs[0])); end endgenerate endmodule module t(); intf #(.PARAM(1)) my_intf [1:0] (); t2 t2 (.mod_intfs(my_intf)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_ena_sc.out0000664000177100017500000000316413702133370022155 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Tue Apr 7 19:56:41 2020 $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 32 3 c_trace_on [31:0] $end $var wire 1 # clk $end $var wire 32 + cyc [31:0] $end $var real 64 ; r $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 + b00000000000000000000000000000000 3 r0 ; #10 1# b00000000000000000000000000000010 + r0.1 ; #11 #12 #13 #14 #15 0# #16 #17 #18 #19 #20 1# b00000000000000000000000000000011 + b00000000000000000000000000000001 3 r0.2 ; #21 #22 #23 #24 #25 0# #26 #27 #28 #29 #30 1# b00000000000000000000000000000100 + b00000000000000000000000000000010 3 r0.3 ; #31 #32 #33 #34 #35 0# #36 #37 #38 #39 #40 1# b00000000000000000000000000000101 + b00000000000000000000000000000011 3 r0.4 ; #41 #42 #43 #44 #45 0# #46 #47 #48 #49 #50 1# b00000000000000000000000000000110 + b00000000000000000000000000000100 3 r0.5 ; #51 #52 #53 #54 #55 0# #56 #57 #58 #59 #60 1# b00000000000000000000000000000111 + b00000000000000000000000000000101 3 r0.6 ; #61 #62 #63 #64 #65 0# #66 #67 #68 #69 #70 1# b00000000000000000000000000001000 + b00000000000000000000000000000110 3 r0.7 ; #71 #72 #73 #74 #75 0# #76 #77 #78 #79 #80 1# b00000000000000000000000000001001 + b00000000000000000000000000000111 3 r0.7999999999999999 ; #81 #82 #83 #84 #85 0# #86 #87 #88 #89 #90 1# b00000000000000000000000000001010 + b00000000000000000000000000001000 3 r0.8999999999999999 ; #91 #92 #93 #94 #95 0# #96 #97 #98 #99 #100 1# b00000000000000000000000000001011 + b00000000000000000000000000001001 3 r0.9999999999999999 ; #101 #102 #103 #104 verilator-4.038/test_regress/t/t_assign_inline.v0000664000177100017500000000212413702133367022030 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Mike Thyer. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cycle=0; // verilator lint_off UNOPTFLAT reg [7:0] a_r; wire [7:0] a_w; reg [7:0] b_r; reg [7:0] c_d_r, c_q_r; assign a_w = a_r; always @(*) begin a_r = 0; b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete" a_r = c_q_r; c_d_r = c_q_r; end // stimulus + checks always @(posedge clk) begin cycle <= cycle+1; if (cycle==0) begin c_q_r <= 8'b0; end else begin c_q_r <= c_d_r+1; `ifdef TEST_VERBOSE $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same `endif end if (cycle >= 10) begin if (b_r==9) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end end endmodule verilator-4.038/test_regress/t/t_number_bad.pl0000775000177100017500000000107413702133370021452 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_mism.v0000664000177100017500000000142013702133370021200 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Alex Solomatnikov. // SPDX-License-Identifier: CC0-1.0 //bug595 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [6-1:0] foo; initial foo = 20; dut #(.W(6)) udut(.clk(clk), .foo(foo-16)); endmodule module dut #(parameter W = 1) (input logic clk, input logic [W-1:0] foo); genvar i; generate for (i = 0; i < W; i++) begin suba ua(.clk(clk), .foo(foo[i])); end endgenerate endmodule module suba (input logic clk, input logic foo); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_mem_bound_bad.v0000664000177100017500000000106013702133370021751 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); logic [1:0][31:0] tt; logic [31:0] a; logic [31:0] b; logic [31:0] c; initial begin a = 1; b = 2; c = 3; tt[0] = a; tt[1] = b; tt[2] = c; // Out of bounds if (tt[0]!=a) $stop; if (tt[1]!=b) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_wire_beh1800_bad.pl0000775000177100017500000000116713702133370022262 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only --language 1800-2017"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_implicit_def_bad.out0000664000177100017500000000076513702133370024037 0ustar wsnyderwsnyder%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:13:11: Signal definition not found, creating implicitly: 'imp_warn' 13 | assign imp_warn = 1'b1; | ^~~~~~~~ ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: t/t_lint_implicit_def_bad.v:18:11: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err' 18 | assign imp_err = 1'b1; | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_assert_implication_bad.pl0000775000177100017500000000141313702133367024056 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_implication.v"); compile( v_flags2 => ['+define+FAIL_ASSERT_1'], verilator_flags2 => ['--assert --cc'], ); execute( ); # We expect to get a message when this assert fires: file_grep($Self->{run_log_filename}, qr/wrong implication/); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen10.pl0000775000177100017500000000106013702133370022301 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_array_fst_threads_2.pl0000775000177100017500000000142513702133370024457 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_trace_array.v"); $Self->{golden_filename} = "t/t_trace_array_fst.out"; compile( verilator_flags2 => ['--cc --trace-fst --trace-threads 2 --trace-structs'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_param_default.pl0000775000177100017500000000105613702133370022160 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_noval_bad.v0000664000177100017500000000052313702133370022306 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t #(parameter P); generate var j; for (j=0; P; j++) initial begin end endgenerate endmodule verilator-4.038/test_regress/t/t_func_sum.pl0000775000177100017500000000105313702133370021170 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_for.v0000664000177100017500000000721413702133370020624 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [7:0] crc; genvar g; wire [7:0] out_p1; wire [15:0] out_p2; wire [7:0] out_p3; wire [7:0] out_p4; paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1)); paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2)); paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3)); gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4)); wire [7:0] out_ef; enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef); cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==0) begin // Setup crc <= 8'hed; end else if (cyc==1) begin end else if (cyc==3) begin if (out_p1 !== 8'h2d) $stop; if (out_p2 !== 16'h2d2d) $stop; if (out_p3 !== 8'h78) $stop; if (out_p4 !== 8'h44) $stop; if (out_ef !== 8'hda) $stop; end else if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module gencase (/*AUTOARG*/ // Outputs out, // Inputs in ); parameter MODE = 0; input [7:0] in; output [7:0] out; generate // : genblk1 begin case (MODE) 2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]})); default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]})); endcase end endgenerate endmodule module paramed (/*AUTOARG*/ // Outputs out, // Inputs in ); parameter WIDTH = 1; parameter MODE = 0; input [WIDTH-1:0] in; output [WIDTH-1:0] out; generate if (MODE==0) initial $write("Mode=0\n"); // No else endgenerate `ifndef NC // for(genvar) unsupported `ifndef ATSIM // for(genvar) unsupported generate // Empty loop body, local genvar for (genvar j=0; j<3; j=j+1) begin end // Ditto to make sure j has new scope for (genvar j=0; j<5; j=j+1) begin end endgenerate `endif `endif generate endgenerate genvar i; generate if (MODE==0) begin // Flip bitorder, direct assign method for (i=0; i 1); top_filename("t/t_unopt_converge_initial.v"); compile( v_flags2 => ['+define+ALLOW_UNOPT --output-split 0'], ); execute( fails => 1, expect_filename => $Self->{golden_filename}, ) if $Self->{vlt_all}; ok(1); 1; verilator-4.038/test_regress/t/t_unpacked_slice.v0000664000177100017500000000357513702133370022164 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) module t (/*AUTOARG*/); parameter int sliceddn[7:0] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; parameter int slicedup[0:7] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; int alldn[7:0]; int allup[0:7]; int twodn[1:0]; int twoup[0:1]; initial begin `checkh(sliceddn[7], 'h100); alldn[7:0] = sliceddn[7:0]; `checkh(alldn[7], 'h100); alldn[7:0] = sliceddn[0 +: 8]; // down: lsb/lo +: width `checkh(alldn[7], 'h100); alldn[7:0] = sliceddn[7 -: 8]; // down: msb/hi -: width `checkh(alldn[7], 'h100); twodn[1:0] = sliceddn[6:5]; `checkh(twodn[1], 'h101); `checkh(twodn[0], 'h102); twodn[1:0] = sliceddn[4 +: 2]; `checkh(twodn[1], 'h102); `checkh(twodn[0], 'h103); twodn[1:0] = sliceddn[4 -: 2]; `checkh(twodn[1], 'h103); `checkh(twodn[0], 'h104); `checkh(slicedup[7], 'h107); allup[0:7] = slicedup[0:7]; `checkh(alldn[7], 'h100); allup[0:7] = slicedup[0 +: 8]; // up: msb/lo +: width `checkh(alldn[7], 'h100); allup[0:7] = slicedup[7 -: 8]; // up: lsb/hi -: width `checkh(alldn[7], 'h100); twoup[0:1] = slicedup[5:6]; `checkh(twoup[1], 'h106); `checkh(twoup[0], 'h105); twoup[0:1] = slicedup[4 +: 2]; `checkh(twoup[1], 'h105); `checkh(twoup[0], 'h104); twoup[0:1] = slicedup[4 -: 2]; `checkh(twoup[1], 'h104); `checkh(twoup[0], 'h103); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_modport_bad.out0000664000177100017500000000041213702133370024052 0ustar wsnyderwsnyder%Error: t/t_interface_modport_bad.v:23:8: Modport not found under interface 'ifc': 'oop_modport' : ... Suggested alternative: 'out_modport' 23 | ifc.oop_modport isub, | ^~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_dpi_lib.v0000664000177100017500000000131613702133370020604 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/); import "DPI-C" function int dpii_failure(); import "DPI-C" function void dpii_check(); initial begin dpii_check(); if (dpii_failure()!=0) begin $write("%%Error: Failure in DPI tests\n"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_lint_declfilename.pl0000775000177100017500000000076313702133370023016 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_hdrfst_cc.pl0000775000177100017500000000231013702133370023354 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); top_filename("t_trace_two_a.v"); compile( make_main => 0, verilator_make_gmake => 0, top_filename => 't_trace_two_b.v', VM_PREFIX => 'Vt_trace_two_b', verilator_flags2 => ['--trace-fst --trace-threads 1'], ); compile( make_main => 0, top_filename => 't_trace_two_a.v', make_flags => 'CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"', verilator_flags2 => ['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', "$Self->{t_dir}/t_trace_two_cc.cpp"], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { fst_identical($Self->trace_filename, $Self->{golden_filename}); } ok(1); 1; verilator-4.038/test_regress/t/t_merge_cond.pl0000775000177100017500000000176113702133370021461 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( verilator_flags2 => ["-unroll-count 64", "--stats"], ); execute( check_finished => 1, ); if ($Self->{vlt}) { # Note, with vltmt this might be split differently, so only checking vlt file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i, 11); file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/i, 644); file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/i, 64); } ok(1); 1; verilator-4.038/test_regress/t/t_case_x.v0000664000177100017500000000246113702133367020454 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg [3:0] value; reg [3:0] valuex; // verilator lint_off CASEOVERLAP // verilator lint_off CASEWITHX // verilator lint_off CASEX // Note for Verilator Xs must become zeros, or the Xs may match. initial begin value = 4'b1001; valuex = 4'b1xxx; case (value) 4'b1xxx: $stop; 4'b1???: $stop; 4'b1001: ; default: $stop; endcase case (valuex) 4'b1???: $stop; 4'b1xxx: ; 4'b1001: ; 4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 default: $stop; endcase // casex (value) 4'b100x: ; default: $stop; endcase casex (value) 4'b100?: ; default: $stop; endcase casex (valuex) 4'b100x: ; default: $stop; endcase casex (valuex) 4'b100?: ; default: $stop; endcase // casez (value) 4'bxxxx: $stop; 4'b100?: ; default: $stop; endcase casez (valuex) 4'b1xx?: ; 4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 default: $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_imm2.v0000664000177100017500000000240313702133370021055 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // Example module to create problem. // // generate a 64 bit value with bits // [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 // [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 // all other bits zero. module t_math_imm2 (/*AUTOARG*/ // Outputs LogicImm, LowLogicImm, HighLogicImm, // Inputs LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot ); input [4:0] LowMaskSel_Top, HighMaskSel_Top; input [4:0] LowMaskSel_Bot, HighMaskSel_Bot; output [63:0] LogicImm; output [63:0] LowLogicImm, HighLogicImm; /* verilator lint_off UNSIGNED */ /* verilator lint_off CMPCONST */ genvar i; generate for (i=0;i<64;i=i+1) begin : MaskVal if (i >= 32) begin assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]); assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]); end else begin assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]); assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]); end end endgenerate assign LogicImm = LowLogicImm & HighLogicImm; endmodule verilator-4.038/test_regress/t/t_math_shift_sel.v0000664000177100017500000000432113702133370022172 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [106:0] in = {~crc[42:0], crc[63:0]}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] out1; // From test of Test.v wire [7:0] out2; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out1 (out1[7:0]), .out2 (out2[7:0]), // Inputs .in (in[106:0])); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, out1, out1}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc746017202a24ecc if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out1, out2, // Inputs in ); // Replace this module with the device under test. // // Change the code in the t module to apply values to the inputs and // merge the output values into the result vector. input [106:0] in; output [7:0] out1, out2; // verilator lint_off WIDTH // Better written as onibble[99 +: 8]. Verilator will convert it. wire [7:0] out1 = (in >>> 99) & 255; // verilator lint_on WIDTH wire [7:0] out2 = in[106:99]; endmodule verilator-4.038/test_regress/t/t_langext_2_bad.pl0000775000177100017500000000115513702133370022045 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_langext_2.v"); # This is a lint only test. lint( v_flags2 => ["+1364-1995ext+v"], fails => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_flag_off.v0000664000177100017500000000060313702133370022121 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); initial begin $dumpfile("/should/not/be/opened"); $dumpvars(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_savable.pl0000775000177100017500000000144713702133370020775 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["--savable"], save_time => 500, ); execute( check_finished => 0, all_run_flags => ['+save_time=500'], ); -r "$Self->{obj_dir}/saved.vltsv" or error("Saved.vltsv not created\n"); execute( all_run_flags => ['+save_restore=1'], check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex_structs_fst.out0000664000177100017500000001170613702133370025040 0ustar wsnyderwsnyder$date Sun Apr 19 04:15:33 2020 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $scope module v_strp $end $var logic 1 # b1 $end $var logic 1 $ b0 $end $upscope $end $scope module v_strp_strp $end $scope module x1 $end $var logic 1 % b1 $end $var logic 1 & b0 $end $upscope $end $scope module x0 $end $var logic 1 ' b1 $end $var logic 1 ( b0 $end $upscope $end $upscope $end $scope module v_unip_strp $end $scope module x1 $end $var logic 1 ) b1 $end $var logic 1 * b0 $end $upscope $end $scope module x0 $end $var logic 1 ) b1 $end $var logic 1 * b0 $end $upscope $end $upscope $end $var logic 2 + v_arrp $end $var logic 2 , v_arrp_arrp(3) $end $var logic 2 - v_arrp_arrp(4) $end $scope module v_arrp_strp(3) $end $var logic 1 . b1 $end $var logic 1 / b0 $end $upscope $end $scope module v_arrp_strp(4) $end $var logic 1 0 b1 $end $var logic 1 1 b0 $end $upscope $end $var logic 1 2 v_arru(1) $end $var logic 1 3 v_arru(2) $end $var logic 1 4 v_arru_arru(3)(1) $end $var logic 1 5 v_arru_arru(3)(2) $end $var logic 1 6 v_arru_arru(4)(1) $end $var logic 1 7 v_arru_arru(4)(2) $end $var logic 2 8 v_arru_arrp(3) $end $var logic 2 9 v_arru_arrp(4) $end $scope module v_arru_strp(3) $end $var logic 1 : b1 $end $var logic 1 ; b0 $end $upscope $end $scope module v_arru_strp(4) $end $var logic 1 < b1 $end $var logic 1 = b0 $end $upscope $end $var real 64 > v_real $end $var real 64 ? v_arr_real(0) $end $var real 64 @ v_arr_real(1) $end $scope module v_str32x2(0) $end $var logic 32 A data $end $upscope $end $scope module v_str32x2(1) $end $var logic 32 B data $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $upscope $end $attrbegin misc 07 "" 1 $end $var logic 32 C v_enumed $end $attrbegin misc 07 "" 1 $end $var logic 32 D v_enumed2 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 E v_enumb $end $scope module v_enumb2_str $end $attrbegin misc 07 "" 2 $end $var logic 3 F a $end $attrbegin misc 07 "" 2 $end $var logic 3 G b $end $upscope $end $var logic 8 H unpacked_array(-2) $end $var logic 8 I unpacked_array(-1) $end $var logic 8 J unpacked_array(0) $end $scope module unnamedblk1 $end $var integer 32 K b $end $scope module unnamedblk2 $end $var integer 32 L a $end $upscope $end $upscope $end $upscope $end $scope module $unit $end $var bit 1 M global_bit $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000000000000000000000000000000 " 0# 0$ 0% 0& 0' 0( 0) 0* b00 + b00 , b00 - 0. 0/ 00 01 02 03 04 05 06 07 b00 8 b00 9 0: 0; 0< 0= r0 > r0 ? r0 @ b00000000000000000000000011111111 A b00000000000000000000000000000000 B b00000000000000000000000000000000 C b00000000000000000000000000000000 D b000 E b000 F b000 G b00000000 H b00000000 I b00000000 J b00000000000000000000000000000000 K b00000000000000000000000000000000 L 1M #10 b00000000000000000000000000000101 L b00000000000000000000000000000101 K b111 E b00000000000000000000000000000010 D b00000000000000000000000000000001 C b00000000000000000000000000000001 B b00000000000000000000000011111110 A r0.3 @ r0.2 ? r0.1 > 1= 1< 1; 1: b11 9 b11 8 11 10 1/ 1. b11 - b11 , b11 + 1* 1) 1( 1' 1& 1% 1$ 1# b00000000000000000000000000000001 " 1! #15 0! #20 1! b00000000000000000000000000000010 " 0# 0$ 0% 0& 0' 0( 0) 0* b00 + b00 , b00 - 0. 0/ 00 01 b00 8 b00 9 0: 0; 0< 0= r0.2 > r0.4 ? r0.6 @ b00000000000000000000000011111101 A b00000000000000000000000000000010 B b00000000000000000000000000000010 C b00000000000000000000000000000100 D b110 E b111 G b111 F #25 0! #30 1! b110 F b110 G b101 E b00000000000000000000000000000110 D b00000000000000000000000000000011 C b00000000000000000000000000000011 B b00000000000000000000000011111100 A r0.8999999999999999 @ r0.6000000000000001 ? r0.3 > 1= 1< 1; 1: b11 9 b11 8 11 10 1/ 1. b11 - b11 , b11 + 1* 1) 1( 1' 1& 1% 1$ 1# b00000000000000000000000000000011 " #35 0! #40 1! b00000000000000000000000000000100 " 0# 0$ 0% 0& 0' 0( 0) 0* b00 + b00 , b00 - 0. 0/ 00 01 b00 8 b00 9 0: 0; 0< 0= r0.4 > r0.8 ? r1.2 @ b00000000000000000000000011111011 A b00000000000000000000000000000100 B b00000000000000000000000000000100 C b00000000000000000000000000001000 D b100 E b101 G b101 F #45 0! #50 1! b100 F b100 G b011 E b00000000000000000000000000001010 D b00000000000000000000000000000101 C b00000000000000000000000000000101 B b00000000000000000000000011111010 A r1.5 @ r1 ? r0.5 > 1= 1< 1; 1: b11 9 b11 8 11 10 1/ 1. b11 - b11 , b11 + 1* 1) 1( 1' 1& 1% 1$ 1# b00000000000000000000000000000101 " #55 0! #60 1! b00000000000000000000000000000110 " 0# 0$ 0% 0& 0' 0( 0) 0* b00 + b00 , b00 - 0. 0/ 00 01 b00 8 b00 9 0: 0; 0< 0= r0.6 > r1.2 ? r1.8 @ b00000000000000000000000011111001 A b00000000000000000000000000000110 B b00000000000000000000000000000110 C b00000000000000000000000000001100 D b010 E b011 G b011 F verilator-4.038/test_regress/t/t_dpi_shortcircuit2.pl0000775000177100017500000000132113702133370023007 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( # Amazingly VCS, NC and Verilator all just accept the C file here! v_flags2 => ["t/t_dpi_shortcircuit_c.cpp"], verilator_flags2 => ["-Wno-DECLFILENAME"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_noinl.pl0000775000177100017500000000114613702133370022513 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_tree.v0000664000177100017500000000373113702133370021201 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // verilator lint_off GENCLK reg printclk; // verilator lint_on GENCLK ps ps (printclk); reg [7:0] a; wire [7:0] z; l1 u (~a,z); always @ (posedge clk) begin printclk <= 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin printclk <= 1'b1; end if (cyc==2) begin a <= 8'b1; end if (cyc==3) begin if (z !== 8'hf8) $stop; //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module ps (input printclk); // Check that %m stays correct across inlines always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time); endmodule module l1 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; l2 u0 (a, z0); l2 u1 (a, z1); endmodule module l2 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l3 u0 (a, z0); l3 u1 (a1, z1); endmodule module l3 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l4 u0 (a, z0); l4 u1 (a1, z1); endmodule module l4 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1); endmodule module l5 (input [7:0] a, output [7:0] z); parameter PARAM = 5; wire [7:0] z0; wire [7:0] z1; assign z = a; endmodule verilator-4.038/test_regress/t/t_inst_overwide.v0000664000177100017500000000235413702133370022066 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs outc_w30, outd_w73, // Inputs clk, ina_w1, inb_w61 ); input clk; input ina_w1; input [60:0] inb_w61; output [29:0] outc_w30; output [72:0] outd_w73; sub sub ( // Outputs .outy_w92 (outc_w30), // .large => (small) .outz_w22 (outd_w73), // .small => (large) // Inputs .clk (clk), .inw_w31 (ina_w1), // .large <= (small) .inx_w11 (inb_w61) // .small <= (large) ); endmodule module sub (/*AUTOARG*/ // Outputs outy_w92, outz_w22, // Inputs clk, inw_w31, inx_w11 ); input clk; input [30:0] inw_w31; input [10:0] inx_w11; output reg [91:0] outy_w92 /*verilator public*/; output reg [21:0] outz_w22 /*verilator public*/; always @(posedge clk) begin outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00}; outz_w22 <= {inx_w11[10:0],inx_w11[10:0]}; end endmodule // regfile verilator-4.038/test_regress/t/t_class_virtual.out0000664000177100017500000000021713702133367022424 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_virtual.v:7:9: Unsupported: virtual class 7 | virtual class VC; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_const.pl0000775000177100017500000000105313702133370021512 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_stringend_bad.v0000664000177100017500000000033413702133370023536 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 "Blah verilator-4.038/test_regress/t/t_lint_pkg_colon_bad.out0000664000177100017500000000062113702133370023351 0ustar wsnyderwsnyder%Error: t/t_lint_pkg_colon_bad.v:7:17: Package/class 'mispkg' not found, and needs to be predeclared (IEEE 1800-2017 26.3) 7 | module t (input mispkg::foo_t a); | ^~~~~~ %Error: t/t_lint_pkg_colon_bad.v:7:25: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER 7 | module t (input mispkg::foo_t a); | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_unpacked_slice.pl0000775000177100017500000000105313702133370022322 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex_structs_fst.pl0000775000177100017500000000134713702133370024647 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_complex.v"); compile( verilator_flags2 => ['--cc --trace-fst --trace-structs --no-trace-params'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_flag_csplit_off.pl0000775000177100017500000000521013702133370022471 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_flag_csplit.v"); while (1) { # Thi rule requires GNU make > 4.1 (or so, known broken in 3.81) #%__Slow.o: %__Slow.cpp # $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< if (make_version() < 4.1) { skip("Test requires GNU Make version >= 4.1"); last; } compile( v_flags2 => ["--trace --output-split 0 --exe ../$Self->{main_filename}"], verilator_make_gmake => 0, ); # We don't use the standard test_regress rules, as want to test the rules # properly build run(logfile => "$Self->{obj_dir}/vlt_gcc.log", tee => $self->{verbose}, cmd=>[$ENV{MAKE}, "-C ".$Self->{obj_dir}, "-f $Self->{VM_PREFIX}.mk", "-j 4", "VM_PREFIX=$Self->{VM_PREFIX}", "TEST_OBJ_DIR=$Self->{obj_dir}", "CPPFLAGS_DRIVER=-D".uc($Self->{name}), ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1":""), "OPT_FAST=-O2", "OPT_SLOW=-O0", ($param{make_flags}||""), ]); execute( check_finished => 1, ); # Never spliting, so should set VM_PARALLEL_BUILDS to 0 by default file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}_classes.mk", qr/VM_PARALLEL_BUILDS\s*=\s*0/); check_no_splits(); check_all_file(); check_gcc_flags("$Self->{obj_dir}/vlt_gcc.log"); ok(1); last; } 1; sub check_no_splits { foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { if ($file =~ qr/__\d/) { error("Split file found: $file"); } } } sub check_all_file { foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { if ($file =~ qr/__ALL.cpp/) { return; } } error("__ALL.cpp file not found"); } sub check_gcc_flags { my $filename = shift; my $fh = IO::File->new("<$filename") or error("$! $filenme"); while (defined (my $line = $fh->getline)) { chomp $line; print ":log: $line\n" if $Self->{verbose}; if ($line =~ /\.cpp/ && $line =~ qr/-O0/) { error("File built as slow (should be in __ALL.cpp) : $line"); } } } verilator-4.038/test_regress/t/t_enum_name2.pl0000775000177100017500000000105313702133370021377 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_void.pl0000775000177100017500000000105313702133370021325 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_parent_scope_bad.v0000664000177100017500000000100413702133370024504 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 interface Foo(); logic quux; endinterface module Bar(); always_comb foo.quux = '0; endmodule module Baz(); Foo foo(); Bar bar(); endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; Baz baz(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/bootstrap.pl0000775000177100017500000000133213702133367021051 0ustar wsnyderwsnyder#!/usr/bin/env perl # DESCRIPTION: Verilator: Verilog Test driver bootstrapper # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This is exec'ed by every test that is run standalone (called from the # shell as ./t_test_name.pl) use FindBin; use Cwd qw(chdir); my @args = @ARGV; chdir("$FindBin::Bin/.."); $ENV{PWD} = Cwd::getcwd(); # Else chdir leaves the .. which confuses later commands @args = map { s!.*test_regress/!!; $_; } @args; exec("./driver.pl", @args); die "$!, in exec"; verilator-4.038/test_regress/t/t_bitsel_struct3.pl0000775000177100017500000000105313702133367022330 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen8.pl0000775000177100017500000000106013702133370022230 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_dotted2.v0000664000177100017500000000635213702133370021424 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `endif module t (/*AUTOARG*/); `define DRAM1(bank) mem.mem_bank[bank].dccm.dccm_bank.ram_core `define DRAM2(bank) mem.mem_bank2[bank].dccm.dccm_bank.ram_core `define DRAM3(bank) mem.mem_bank3[bank].dccm.dccm_bank.ram_core `define DRAM4(bank) mem.sub4.mem_bank4[bank].dccm.dccm_bank.ram_core initial begin `DRAM1(0)[3] = 130; `DRAM1(1)[3] = 131; `DRAM2(0)[3] = 230; `DRAM2(1)[3] = 231; `DRAM3(0)[3] = 330; `DRAM3(1)[3] = 331; `DRAM4(0)[3] = 430; `DRAM4(1)[3] = 431; if (`DRAM1(0)[3] !== 130) $stop; if (`DRAM1(1)[3] !== 131) $stop; if (`DRAM2(0)[3] !== 230) $stop; if (`DRAM2(1)[3] !== 231) $stop; if (`DRAM3(0)[3] !== 330) $stop; if (`DRAM3(1)[3] !== 331) $stop; if (`DRAM4(0)[3] !== 430) $stop; if (`DRAM4(1)[3] !== 431) $stop; $write("*-* All Finished *-*\n"); $finish; end eh2_lsu_dccm_mem mem (/*AUTOINST*/); endmodule module eh2_lsu_dccm_mem #( DCCM_INDEX_DEPTH = 8192, DCCM_NUM_BANKS = 2 )( ); `INLINE_MODULE // 8 Banks, 16KB each (2048 x 72) for (genvar i=0; i 1); compile( v_flags2 => ["--top-module b"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_emit_constw.pl0000775000177100017500000000111513702133370021703 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--Ox'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_comma.v0000664000177100017500000000316113702133370021333 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; parameter ONE = 1; wire [17:10] bitout; reg [7:0] allbits; reg [15:0] onebit; sub #(1) sub0 (allbits, onebit[1:0], bitout[10]), sub1 (allbits, onebit[3:2], bitout[11]), sub2 (allbits, onebit[5:4], bitout[12]), sub3 (allbits, onebit[7:6], bitout[13]), sub4 (allbits, onebit[9:8], bitout[14]), sub5 (allbits, onebit[11:10], bitout[15]), sub6 (allbits, onebit[13:12], bitout[16]), sub7 (allbits, onebit[15:14], bitout[17]); integer x; always @ (posedge clk) begin //$write("%x\n", bitout); if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin allbits <= 8'hac; onebit <= 16'hc01a; end if (cyc==2) begin if (bitout !== 8'h07) $stop; allbits <= 8'hca; onebit <= 16'h1f01; end if (cyc==3) begin if (bitout !== 8'h41) $stop; if (sub0.bitout !== 1'b1) $stop; if (sub1.bitout !== 1'b0) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `endif module sub (input [7:0] allbits, input [1:0] onebit, output bitout); `INLINE_MODULE parameter integer P = 0; initial if (P != 1) $stop; assign bitout = (^ onebit) ^ (^ allbits); endmodule verilator-4.038/test_regress/t/t_case_inside.pl0000775000177100017500000000105313702133367021625 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_cond_bitrange.v0000664000177100017500000000564013702133370022635 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if" // // The given generate loops should only access valid bits of mask, since that // is defined by SIZE. However since the loop range is larger, this only works // if short-circuited evaluation of the generate loop is in place. // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 4 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Set the parameters, so that we use a size less than MAX_SIZE test_gen #(.SIZE (2), .MASK (2'b11)) i_test_gen (.clk (clk)); // This is only a compilation test, but for good measure we do one clock // cycle. integer count; initial begin count = 0; end always @(posedge clk) begin if (count == 1) begin $write("*-* All Finished *-*\n"); $finish; end else begin count = count + 1; end end endmodule // t module test_gen #( parameter SIZE = `MAX_SIZE, MASK = `MAX_SIZE'b0) (/*AUTOARG*/ // Inputs clk ); input clk; // Generate blocks that rely on short-circuiting of the logic to avoid errors. generate genvar g; for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ((g < SIZE) && MASK[g]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g >= SIZE) || ~MASK[g])) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g < SIZE) -> ~MASK[g])) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ( g < SIZE ? MASK[g] : 1'b0) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate // The other way round generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ( g >= SIZE ? 1'b0 : MASK[g]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate endmodule verilator-4.038/test_regress/t/t_math_shift_rep.pl0000775000177100017500000000114713702133370022351 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb -O0'"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_while.v0000664000177100017500000000134613702133370021475 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug505 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter WIDTH = 33; localparam MAX_WIDTH = 11; localparam NUM_OUT = num_out(WIDTH); wire [NUM_OUT-1:0] z; function integer num_out; input integer width; num_out = 1; while ((width + num_out - 1) / num_out > MAX_WIDTH) num_out = num_out * 2; endfunction initial begin if (NUM_OUT != 4) $stop; if ($bits(z) != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_vpi_unimpl.v0000664000177100017500000000163713702133370021372 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function integer mon_check(); `endif module t (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; reg onebit /*verilator public_flat_rw @(posedge clk) */; integer status; // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `else status = mon_check(); `endif $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-4.038/test_regress/t/t_param_ddeep_width.v0000664000177100017500000000122713702133370022643 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use. // SPDX-License-Identifier: CC0-1.0 // bug541 module t(clk,odata); input clk; output [7:0] odata; paramtest_DFFRE #(1) dffre0(clk,odata[7]); paramtest_WRAP #(7) dffe0(clk,odata[6:0]); endmodule module paramtest_WRAP(clk,q); parameter W=1; input clk; output [W-1:0] q; paramtest_DFFRE #(W) dffre0(clk,q); endmodule module paramtest_DFFRE(clk,q); parameter W=1; parameter [W-1:0] INIT={W{1'b0}}; input clk; output [W-1:0] q; reg [W-1:0] q; always @(posedge clk) begin q <= INIT; end endmodule verilator-4.038/test_regress/t/t_vpi_unimpl.cpp0000664000177100017500000001506713702133370021711 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "Vt_vpi_unimpl.h" #include "verilated.h" #include "svdpi.h" #include "Vt_vpi_unimpl__Dpi.h" #include "verilated_vcd_c.h" // No verilated_vpi.h, make sure can link without it #include #include "TestVpi.h" // __FILE__ is too long #define FILENM "t_vpi_unimpl.cpp" #define DEBUG \ if (0) printf unsigned int main_time = 0; unsigned int callback_count = 0; //====================================================================== #define CHECK_RESULT_VH(got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d: GOT = %p EXP = %p\n", FILENM, __LINE__, (got), (exp)); \ return __LINE__; \ } #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ return __LINE__; \ } // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_HEX(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << std::hex \ << ": GOT = " << (got) << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ (got) ? (got) : "", (exp) ? (exp) : ""); \ return __LINE__; \ } #define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp) int _mon_check_unimpl(p_cb_data cb_data) { static TestVpiHandle cb, clk_h; vpiHandle handle; if (cb_data) { // this is the callback s_vpi_error_info info; vpi_chk_error(&info); callback_count++; printf("%%Info: got pli message %s\n", info.message); } else { // setup and install static t_cb_data cb_data; clk_h = vpi_handle_by_name((PLI_BYTE8*)"t.clk", NULL); cb_data.reason = cbPLIError; cb_data.cb_rtn = _mon_check_unimpl; // this function cb = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(cb); // now exercise unimplemented fns vpi_get_cb_info(cb, NULL); CHECK_RESULT(callback_count, 1); vpi_register_systf(NULL); CHECK_RESULT(callback_count, 2); vpi_get_systf_info(NULL, NULL); CHECK_RESULT(callback_count, 3); vpi_handle_multi(0, NULL, NULL); CHECK_RESULT(callback_count, 4); vpi_get64(0, NULL); CHECK_RESULT(callback_count, 5); vpi_get_delays(NULL, NULL); CHECK_RESULT(callback_count, 6); vpi_put_delays(NULL, NULL); CHECK_RESULT(callback_count, 7); vpi_get_value_array(NULL, NULL, NULL, 0); CHECK_RESULT(callback_count, 8); vpi_put_value_array(NULL, NULL, NULL, 0); CHECK_RESULT(callback_count, 9); vpi_get_time(NULL, NULL); CHECK_RESULT(callback_count, 10); vpi_mcd_name(0); CHECK_RESULT(callback_count, 11); vpi_compare_objects(NULL, NULL); CHECK_RESULT(callback_count, 12); vpi_get_data(0, NULL, 0); CHECK_RESULT(callback_count, 13); vpi_put_data(0, NULL, 0); CHECK_RESULT(callback_count, 14); vpi_get_userdata(NULL); CHECK_RESULT(callback_count, 15); vpi_put_userdata(NULL, NULL); CHECK_RESULT(callback_count, 16); vpi_handle_by_multi_index(NULL, 0, NULL); CHECK_RESULT(callback_count, 17); vpi_control(0); CHECK_RESULT(callback_count, 18); s_vpi_time time_s; time_s.type = 0; vpi_get_time(NULL, &time_s); CHECK_RESULT(callback_count, 19); handle = vpi_put_value(NULL, NULL, NULL, 0); CHECK_RESULT(callback_count, 20); CHECK_RESULT(handle, 0); handle = vpi_handle(0, NULL); CHECK_RESULT(callback_count, 21); CHECK_RESULT(handle, 0); vpi_iterate(0, NULL); CHECK_RESULT(callback_count, 22); handle = vpi_register_cb(NULL); CHECK_RESULT(callback_count, 23); CHECK_RESULT(handle, 0); s_cb_data cb_data_s; cb_data_s.reason = 0; // Bad handle = vpi_register_cb(&cb_data_s); CHECK_RESULT(callback_count, 24); CHECK_RESULT(handle, 0); } return 0; // Ok } int mon_check() { // Callback from initial block in monitor if (int status = _mon_check_unimpl(NULL)) return status; return 0; // Ok } //====================================================================== double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); // we're going to be checking for these errors do don't crash out Verilated::fatalOnVpiError(0); VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out #ifdef VERILATOR #ifdef TEST_VERBOSE Verilated::scopesDump(); #endif #endif #if VM_TRACE Verilated::traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; main_time += 10; while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += 1; topp->eval(); // VerilatedVpi::callValueCbs(); // Make sure can link without verilated_vpi.h included topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } if (!callback_count) { vl_fatal(FILENM, __LINE__, "main", "%Error: never got callbacks"); } if (!Verilated::gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete topp, topp); exit(0L); } verilator-4.038/test_regress/t/t_interface_param1.pl0000775000177100017500000000076613702133370022564 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_var_dotted_dup_bad.out0000664000177100017500000000052213702133370023353 0ustar wsnyderwsnyder%Error: t/t_var_dotted_dup_bad.v:14:18: Duplicate declaration of cell: 'dccm_bank' 14 | eh2_ram dccm_bank (.*); | ^~~~~~~~~ t/t_var_dotted_dup_bad.v:11:18: ... Location of original declaration 11 | eh2_ram dccm_bank (.*); | ^~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_xml_first.out0000664000177100017500000001135413702133370021556 0ustar wsnyderwsnyder verilator-4.038/test_regress/t/t_select_negative.v0000664000177100017500000000364713702133370022354 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; wire [15:-16] sel2 = crc[31:0]; wire [80:-10] sel3 = {crc[26:0],crc}; wire [3:0] out21 = sel2[-3 : -6]; wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4]; wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4]; wire [3:0] out31 = sel3[-3 : -6]; wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4]; wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4]; // Aggregate outputs into a single result vector wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33}; reg [15:-16] sel1; initial begin // Path clearing sel1 = 32'h12345678; if (sel1 != 32'h12345678) $stop; if (sel1[-13 : -16] != 4'h8) $stop; if (sel1[3:0] != 4'h4) $stop; if (sel1[4 +: 4] != 4'h3) $stop; if (sel1[11 -: 4] != 4'h2) $stop; end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] sels=%x,%x,%x %x,%x,%x\n",$time, out21,out22,out23, out31,out32,out33); $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'hba7fe1e7ac128362 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_math_pow3.v0000664000177100017500000001010213702133370021074 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0) module t (/*AUTOARG*/); bit fail; // IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below. initial begin // NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21 $display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110); // NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed) $display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2))); // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2))); // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14))); // NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321 $display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321); $display("\n"); `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21); `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730 `checkh( (-4'd1 ** -4'd2), 4'h1); `checkh( (4'd15 ** 4'd14), 4'h1); `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321); `checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27) `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1 `checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1 `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0 `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1 `checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27) `checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27) `checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216) `checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216) `checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1 `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27) `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27) `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216) `checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216) `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug `checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 `checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1 // `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug `checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1 `checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug `checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug if (fail) $stop; else $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_notfound_bad.v0000664000177100017500000000143713702133370022520 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); integer i; integer a_var; sub sub (); task nottask(); endtask function int notfunc(); return 0; endfunction initial begin nf = 0; // z not found sub.subsubz.inss = 0; // subsub not found i = nofunc(); // nofunc not found i = sub.nofuncs(); // nofuncs not found notask(); // notask not found a_var(); // Calling variable as task $finish; end endmodule module sub; subsub subsub (); function int notfuncs(); return 0; endfunction endmodule module subsub; integer inss; endmodule verilator-4.038/test_regress/t/t_a2_first_sc.pl0000775000177100017500000000154113702133367021557 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test runs the very first time we've executed Verilator --sc # after building so we make sure to run with --gdbbt, so if it dumps we'll # get a trace. scenarios(simulator => 1); top_filename("t/t_a1_first_cc.v"); $DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; compile( verilator_flags2 => [$DEBUG_QUIET, "-sc --trace"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_public.cpp0000664000177100017500000000115513702133370022156 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include "Vt_param_public.h" #include "Vt_param_public_p.h" int main(int argc, char* argv[]) { Vt_param_public* topp = new Vt_param_public; Verilated::debug(0); // Make sure public tag worked if (static_cast(Vt_param_public_p::INPACK) != 0) {} for (int i = 0; i < 10; i++) { topp->eval(); } } verilator-4.038/test_regress/t/t_concat_opt.v0000664000177100017500000000345513702133367021347 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2004 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 // // The test was added together with the concat optimization. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] in_a; reg [31:0] in_b; reg [31:0] in_c; reg [31:0] in_d; reg [31:0] in_e; reg [15:0] in_f; wire [31:0] in_g; assign in_g = in_a << 4; reg [31:0] out_x; reg [31:0] out_y; reg [31:0] out_z; reg [31:0] out_o; reg [31:0] out_p; reg [31:0] out_q; assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f}; assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]}; assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]}; assign out_o = out_z | out_y; assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]}; assign out_q = {{in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]}}; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; in_a <= cyc; in_b <= cyc + 1; in_c <= cyc + 3; in_d <= cyc + 8; in_e <= cyc; in_f <= cyc[15:0]; if (out_x != (in_a & {2{in_f}})) $stop; if (out_y != (in_a&in_b)) $stop; if (out_z != (in_e&in_d&in_c)) $stop; if (out_o != (((in_a&in_b)|(in_c&in_e&in_d)))) $stop; if (out_p != (in_a & {2{in_f}} | in_e)) $stop; if (out_q != (in_a ^ in_g)) $stop; if (cyc==100) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_struct_unaligned.pl0000775000177100017500000000121613702133370022724 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Note: need to run at a higher optimization level to reproduce the issue $Self->{benchmark} = 1; compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_static_order.v0000664000177100017500000000226013702133367023056 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsZ; function new(); $display("ClsZ::new"); endfunction endclass class ClsA; function new(); $display("ClsA::new"); endfunction function void access; $display("ClsA::access"); endfunction endclass class ClsB; static ClsZ z = new; function new(); $display("ClsB::new"); endfunction function void access; $display("ClsB::access"); endfunction endclass class ClsC; // Elaboration will call these static ClsA a = new; static ClsB b = new; function new(); $display("ClsC::new"); endfunction function void access; $display("ClsC::access"); a = new; a.access; endfunction endclass module t (/*AUTOARG*/); function void makec; ClsC c; $display("c = new;"); c = new; $display("c.access;"); c.access; endfunction initial begin $display("makec;"); makec; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_dups.pl0000775000177100017500000000106013702133370022342 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_names.v0000664000177100017500000000111513702133370021273 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub (); endmodule module sub; //verilator no_inline_module string scope; initial begin scope = $sformatf("%m"); $write("[%0t] In %s\n", $time, scope); `ifdef VERILATOR if (scope != "top.l2Name.sub") $stop; `else if (scope != "top.t.sub") $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_altera_lpm_mult.pl0000775000177100017500000000120613702133367022540 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_fork_disable.pl0000775000177100017500000000114513702133370021777 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ['--lint-only'], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_enum.v0000664000177100017500000000066513702133367021347 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); class Cls; typedef enum {A = 10, B = 20, C = 30} en_t; endclass initial begin Cls c; if (c.A != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_enum.pl0000775000177100017500000000105313702133370020315 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_genblk.pl0000775000177100017500000000110313702133370021440 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_const2_bad.v0000664000177100017500000000173113702133370022234 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 function integer f_add(input [31:0] a, input [31:0] b); f_add = a+b; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); f_add2 = f_add(a,b)+c; endfunction module c9 #(parameter A = 1, parameter B = 1); localparam SOMEP = f_add2(A, B, 9); endmodule module b8 #(parameter A = 1); c9 #(.A (A), .B (8)) c9; endmodule module t; localparam P6 = f_add(5, 1); localparam P14 = f_add2(2, 3, f_add(4, 5)); //localparam P24 = f_add2(7, 8, 9); b8 b8; b8 #(.A (6)) b8_a6; b8 #(.A (7)) b8_a7; initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_assoc_pattern_unsup.v0000664000177100017500000000217513702133367023313 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/); initial begin int i; string a [string]; string k; string v; a = '{ "f": "fooed", "b": "bared", default: "defaulted" }; i = a.size(); `checkh(i, 2); // Default doesn't count v = a["f"]; `checks(v, "fooed"); v = a["b"]; `checks(v, "bared"); v = a["NEXISTS"]; `checks(v, "defaulted"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_alw_reorder.v0000664000177100017500000000271213702133367021516 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [15:0] m_din; reg [15:0] v1; reg [15:0] v2; reg [15:0] v3; integer nosplit; always @ (posedge clk) begin // write needed so that V3Dead doesn't kill v0..v3 $write(" values %x %x %x\n", v1, v2, v3); // Locally-set 'nosplit' will prevent the if from splitting // in splitAlwaysAll(). This whole always block should still be // intact when we call splitReorderAll() which is the subject // of this test. nosplit = cyc; if (nosplit > 2) begin /* S1 */ v1 <= 16'h0; /* S2 */ v1 <= m_din; /* S3 */ if (m_din == 16'h0) begin /* X1 */ v2 <= v1; /* X2 */ v3 <= v2; end end // We expect to swap S2 and S3, and to swap X1 and X2. // We can check that this worked by the absense of dly vars // in the generated output; if the reorder fails (or is disabled) // we should see dly vars for v1 and v2. end always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==7) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_func_lib_sub.pl0000775000177100017500000000101313702133370021777 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( ); # No execute ok(1); 1; verilator-4.038/test_regress/t/t_func_endian.v0000664000177100017500000000460713702133370021461 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; wire noswap = crc[32]; wire nibble = crc[33]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .noswap (noswap), .nibble (nibble), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== 64'h89522c3f5e5ca324) $stop; $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, noswap, nibble, in ); input clk; input noswap; input nibble; input [31:0] in; output [31:0] out; function [7:0] EndianSwap; input Nibble; input [7:0] Data; begin EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3], Data[4], Data[5], Data[6], Data[7] } : { 4'h0, Data[0], Data[1], Data[2], Data[3] }); end endfunction assign out[31:24] = (noswap ? in[31:24] : EndianSwap(nibble, in[31:24])); assign out[23:16] = (noswap ? in[23:16] : EndianSwap(nibble, in[23:16])); assign out[15:8] = (noswap ? in[15:8] : EndianSwap(nibble, in[15:8])); assign out[7:0] = (noswap ? in[7:0] : EndianSwap(nibble, in[7:0])); endmodule verilator-4.038/test_regress/t/t_select_index.pl0000775000177100017500000000105313702133370022017 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_slice.v0000664000177100017500000000365513702133370021346 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 // bug1015 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [1:0] i = crc[1:0]; logic [1:0] o [13:10] ; Test test (/*AUTOINST*/ // Outputs .o (o/*[1:0].[3:0]*/), // Inputs .i (i[1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n",$time, cyc, crc, result, sum); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hb42b2f48a0a9375a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( output logic [1:0] o [3:0], //but this works //logic [N-1:0] o input [1:0] i); parameter N = 4; logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3}; sub sub [N-1:0] (.o (o), // many-to-many .a (a), // many-to-many .i (i)); // many-to-one endmodule module sub ( input logic [1:0] i, input logic [1:0] a, output logic [1:0] o ); assign o = i + a; endmodule verilator-4.038/test_regress/t/t_interface_twod.v0000664000177100017500000000163013702133370022176 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; modport i (output value); modport o (input value); endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc itop1a(), itop1b(); wrapper c1 (.isuba(itop1a), .isubb(itop1b), .i_valuea(14), .i_valueb(15)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (itop1a.value != 14) $stop; if (itop1b.value != 15) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module wrapper ( ifc.i isuba, isubb, input integer i_valuea, i_valueb ); always @* begin isuba.value = i_valuea; isubb.value = i_valueb; end endmodule verilator-4.038/test_regress/t/t_func_under.v0000664000177100017500000000136713702133370021340 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] counter = 0; integer l2; function log2 (input [3:0] x); integer log2 = (x < 2) ? 1 : (x < 4) ? 2 : (x < 8) ? 3 : 4; endfunction always @(posedge clk) begin counter <= counter + 1; l2 <= log2(counter); // bug589: This failed with (%Error: Internal Error: Function not underneath a statement): $display("log2(%d) == %d", counter, log2(counter)); // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_public_trace.pl0000775000177100017500000000121013702133370023013 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_func_public.v"); compile( verilator_flags2 => ["--trace"], fails => $fail, ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_altera_lpm_compare.pl0000775000177100017500000000120613702133367023205 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_ttempty.v0000664000177100017500000000043113702133370022437 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //`define TARGET_PACKAGE `define TARGET_PACKAGE_```TARGET_PACKAGE verilator-4.038/test_regress/t/t_fork_func2_bad.v0000664000177100017500000000060613702133370022047 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); function int f; fork ; join_any // Illegal 13.4.4 endfunction int i; initial begin i = f(); end endmodule verilator-4.038/test_regress/t/t_struct_genfor.pl0000775000177100017500000000076613702133370022247 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_embed1.pl0000775000177100017500000000324613702133370020514 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use File::Spec; scenarios(simulator => 1); my $self = $Self; my $child_dir = "$Self->{obj_dir}_child"; mkdir $child_dir; # Compile the child { my @cmdargs = $Self->compile_vlt_cmd (VM_PREFIX => "$Self->{VM_PREFIX}_child", top_filename => "$Self->{name}_child.v", verilator_flags => ["-cc", "-Mdir", "${child_dir}", "--debug-check"], ); run(logfile => "${child_dir}/vlt_compile.log", cmd => \@cmdargs); run(logfile => "${child_dir}/vlt_gcc.log", cmd => ["cd ${child_dir} && ", $ENV{MAKE}, "-f".getcwd()."/Makefile_obj", "CPPFLAGS_DRIVER=-D".uc($self->{name}), ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1":""), "VM_PREFIX=$self->{VM_PREFIX}_child", "V$self->{name}_child__ALL.a", # bypass default rule, make archive ($param{make_flags}||""), ]); } # Compile the parent (might be with other than verilator) compile( v_flags2 => [File::Spec->rel2abs("${child_dir}/V$self->{name}_child__ALL.a"), # TODO would be nice to have this in embedded archive "t/t_embed1_c.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_define.v0000664000177100017500000000653013702133370021430 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // Special cases of "string parameters" : // This table compares obtain results from big-3 simulators to Verilator // expected behavior. Base specified integer literals are also included as // string detection may impact results for such cases. // // | In the options file | simulator 1 | simulator 2 | simulator 3 | verilator | // |----------------------- ---|-------------|-------------|-------------|-------------| // | +define+C0='"AB CD"' | AB CD | UNSUPPORTED | AB CD | AB CD | // | +define+C1=\"AB\ CD\" | AB CD | UNSUPPORTED | AB CD | AB CD | // | +define+C2="\"AB CD\"" | AB CD | AB CD | UNSUPPORTED | AB CD | // | +define+C3="\"AB\ CD\"" | AB CD | AB CD | UNSUPPORTED | AB CD | // | +define+C4=32'h600D600D | UNSUPPORTED | 32'h600D600D| 32'h600D600D| 32'h600D600D| // | +define+C5=32\'h600D600D | 32'h600D600D| UNSUPPORTED | UNSUPPORTED | 32'h600D600D| // | +define+C6="32'h600D600D" | 32'h600D600D| 32'h600D600D| 32'h600D600D| 32'h600D600D| // | +define+C7='AB CD' | AB CD | UNSUPPORTED | UNSUPPORTED | UNSUPPORTED | `define STRINGIFY(x) `"x`" module t; initial begin `ifdef D1A if (`STRINGIFY(`D4B) !== "") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef D2A if (`STRINGIFY(`D2A) !== "VALA") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef D3A if (`STRINGIFY(`D4B) !== "") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef D3B if (`STRINGIFY(`D4B) !== "") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef D4A if (`STRINGIFY(`D4A) !== "VALA") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef D4B if (`STRINGIFY(`D4B) !== "") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef D5A if (`STRINGIFY(`D5A) !== "VALA") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef D5A if (`STRINGIFY(`D5B) !== "VALB") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef STRING1 if (`STRING1 !== "New String") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef STRING2 if (`STRING2 !== "New String") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef STRING3 if (`STRING3 !== "New String") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef LIT1 if (`STRINGIFY(`LIT1) !== "32'h600D600D") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef LIT2 if (`STRINGIFY(`LIT2) !== "32'h600D600D") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifdef LIT3 if (`STRINGIFY(`LIT3) !== "32'h600D600D") $stop; `else $write("%%Error: Missing define\n"); $stop; `endif `ifndef CMD_DEF $write("%%Error: Missing define\n"); $stop; `endif `ifndef CMD_DEF2 $write("%%Error: Missing define\n"); $stop; `endif `ifdef CMD_UNDEF $write("%%Error: Extra define\n"); $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_real_round.pl0000775000177100017500000000105313702133370022514 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_timescale_parse_bad.out0000664000177100017500000000215513702133370023514 0ustar wsnyderwsnyder%Error: t/t_timescale_parse_bad.v:8:1: `timescale timeunit '1ps' must be greater than or equal to timeprecision '1ns' 8 | `timescale 1ps/1ns | ^~~~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:11:1: `timescale timeunit syntax error: 'frump' 11 | `timescale frump | ^~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:12:1: `timescale timeunit syntax error: '1xs' 12 | `timescale 1xs | ^~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:13:1: `timescale timeunit syntax error: '2ps' 13 | `timescale 2ps | ^~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:14:1: `timescale timeprecision syntax error: 'frump' 14 | `timescale 1ns / frump | ^~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:15:1: `timescale syntax error: ' 1ns / 1ps /extra' 15 | `timescale 1ns / 1ps /extra | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:18:13: timeunit illegal value 18 | timeunit 2ps; | ^~~ %Error: t/t_timescale_parse_bad.v:19:18: timeprecision illegal value 19 | timeprecision 2ps; | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_assert_basic_off.pl0000775000177100017500000000115113702133367022652 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_basic.v"); compile( v_flags2 => [], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_inz.pl0000775000177100017500000000123713702133370021033 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2018 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_comp_bad.v0000664000177100017500000000071313702133367022335 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); if (1) begin $info("User compile-time info"); $warning("User compile-time warning"); $warning(1); // Check can convert arguments to format $error("User compile-time error"); end endmodule verilator-4.038/test_regress/t/t_waiveroutput_allgood.pl0000775000177100017500000000142513702133370023633 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2012 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.vlt"; my $waiver_filename = "t/$Self->{name}.vlt"; top_filename("t/t_waiveroutput.v"); compile( v_flags2 => [$waiver_filename, '--waiver-output', $out_filename], ); files_identical("$out_filename", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_tri_inz.v0000664000177100017500000000066513702133370020666 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top (input d, output ext0, output ext1, output extx, output extz); assign ext0 = (d === 1'b0); assign ext1 = (d === 1'b1); assign extx = (d === 1'bx); assign extz = (d === 1'bz); endmodule verilator-4.038/test_regress/t/t_func_return_bad.v0000664000177100017500000000112013702133370022333 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); task t1; return 1; // Shouldn't return value endtask function int f1; return; // Should return value endfunction initial begin return; // Not under function continue; // Not under loop break; // Not under loop begin : foo end disable foo; // Disabling outside block end endmodule verilator-4.038/test_regress/t/t_gen_mislevel.pl0000775000177100017500000000105313702133370022022 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_prepost.pl0000775000177100017500000000100113702133370022073 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_fi.v0000664000177100017500000000072713702133370020576 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); initial begin $c("myfunction();"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_types.v0000664000177100017500000001754113702133370021225 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); // IEEE: integer_atom_type byte d_byte; shortint d_shortint; int d_int; longint d_longint; integer d_integer; time d_time; chandle d_chandle; // IEEE: integer_atom_type bit d_bit; logic d_logic; reg d_reg; bit [1:0] d_bit2; logic [1:0] d_logic2; reg [1:0] d_reg2; // IEEE: non_integer_type //UNSUP shortreal d_shortreal; real d_real; realtime d_realtime; // Declarations using var var byte v_b; `ifndef VCS var [2:0] v_b3; var signed [2:0] v_bs; `endif // verilator lint_off WIDTH localparam p_implicit = {96{1'b1}}; localparam [89:0] p_explicit = {96{1'b1}}; localparam byte p_byte = {96{1'b1}}; localparam shortint p_shortint = {96{1'b1}}; localparam int p_int = {96{1'b1}}; localparam longint p_longint = {96{1'b1}}; localparam integer p_integer = {96{1'b1}}; localparam reg p_reg = {96{1'b1}}; localparam bit p_bit = {96{1'b1}}; localparam logic p_logic = {96{1'b1}}; localparam reg [0:0] p_reg1 = {96{1'b1}}; localparam bit [0:0] p_bit1 = {96{1'b1}}; localparam logic [0:0] p_logic1= {96{1'b1}}; localparam reg [1:0] p_reg2 = {96{1'b1}}; localparam bit [1:0] p_bit2 = {96{1'b1}}; localparam logic [1:0] p_logic2= {96{1'b1}}; // verilator lint_on WIDTH byte v_byte[2]; shortint v_shortint[2]; int v_int[2]; longint v_longint[2]; integer v_integer[2]; time v_time[2]; chandle v_chandle[2]; bit v_bit[2]; logic v_logic[2]; reg v_reg[2]; real v_real[2]; realtime v_realtime[2]; // We do this in two steps so we can check that initialization inside functions works properly // verilator lint_off WIDTH function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction function int f_int; int lv_int; f_int = lv_int; endfunction function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction function time f_time; time lv_time; f_time = lv_time; endfunction function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction // verilator lint_on WIDTH `ifdef verilator // For verilator zeroinit detection to work properly, we need to x-rand-reset to all 1s. This is the default! `define XINIT 1'b1 `define ALL_TWOSTATE 1'b1 `else `define XINIT 1'bx `define ALL_TWOSTATE 1'b0 `endif `define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \ if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \ begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \ name = {96{1'b1}}; \ if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \ name = {96{1'bx}}; \ if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \ begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \ initial begin // verilator lint_off WIDTH // verilator lint_off UNSIGNED // name b sign twost 0init `CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1); `CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1); `CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1); `CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1); `CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0); `CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0); `CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1); `CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0); `CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0); `CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1); `CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0); `CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0); // verilator lint_on WIDTH // verilator lint_on UNSIGNED // Can't CHECK_ALL(d_chandle), as many operations not legal on chandles `ifdef VERILATOR // else indeterminate if ($bits(d_chandle) !== 64) $stop; `endif `define CHECK_P(name,nbits) \ if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ // name b `CHECK_P(p_implicit ,96); `CHECK_P(p_implicit[0] ,1 ); `CHECK_P(p_explicit ,90); `CHECK_P(p_explicit[0] ,1 ); `CHECK_P(p_byte ,8 ); `CHECK_P(p_byte[0] ,1 ); `CHECK_P(p_shortint ,16); `CHECK_P(p_shortint[0] ,1 ); `CHECK_P(p_int ,32); `CHECK_P(p_int[0] ,1 ); `CHECK_P(p_longint ,64); `CHECK_P(p_longint[0] ,1 ); `CHECK_P(p_integer ,32); `CHECK_P(p_integer[0] ,1 ); `CHECK_P(p_bit ,1 ); `CHECK_P(p_logic ,1 ); `CHECK_P(p_reg ,1 ); `CHECK_P(p_bit1 ,1 ); `CHECK_P(p_logic1 ,1 ); `CHECK_P(p_reg1 ,1 ); `CHECK_P(p_bit1[0] ,1 ); `CHECK_P(p_logic1[0] ,1 ); `CHECK_P(p_reg1[0] ,1 ); `CHECK_P(p_bit2 ,2 ); `CHECK_P(p_logic2 ,2 ); `CHECK_P(p_reg2 ,2 ); `define CHECK_B(varname,nbits) \ if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \ `CHECK_B(v_byte[1] ,8 ); `CHECK_B(v_shortint[1] ,16); `CHECK_B(v_int[1] ,32); `CHECK_B(v_longint[1] ,64); `CHECK_B(v_integer[1] ,32); `CHECK_B(v_time[1] ,64); //`CHECK_B(v_chandle[1] `CHECK_B(v_bit[1] ,1 ); `CHECK_B(v_logic[1] ,1 ); `CHECK_B(v_reg[1] ,1 ); //`CHECK_B(v_real[1] ,64); // $bits not allowed //`CHECK_B(v_realtime[1] ,64); // $bits not allowed `define CHECK_F(fname,nbits,zeroinit) \ if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \ // name b 0init `CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96 `CHECK_F(f_explicit ,90,1'b0); `CHECK_F(f_byte ,8 ,1'b1); `CHECK_F(f_shortint ,16,1'b1); `CHECK_F(f_int ,32,1'b1); `CHECK_F(f_longint ,64,1'b1); `CHECK_F(f_integer ,32,1'b0); `CHECK_F(f_time ,64,1'b0); `ifdef VERILATOR // else indeterminate `CHECK_F(f_chandle ,64,1'b0); `endif `CHECK_F(f_bit ,1 ,1'b1); `CHECK_F(f_logic ,1 ,1'b0); `CHECK_F(f_reg ,1 ,1'b0); `CHECK_F(f_bit1 ,1 ,1'b1); `CHECK_F(f_logic1 ,1 ,1'b0); `CHECK_F(f_reg1 ,1 ,1'b0); `CHECK_F(f_bit2 ,2 ,1'b1); `CHECK_F(f_logic2 ,2 ,1'b0); `CHECK_F(f_reg2 ,2 ,1'b0); // For unpacked types we don't want width warnings for unsized numbers that fit d_byte = 2; d_shortint= 2; d_int = 2; d_longint = 2; d_integer = 2; // Special check d_time = $time; if ($time !== d_time) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_bad_width.pl0000775000177100017500000000111313702133370022306 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_dtree_inlad.pl0000775000177100017500000000125113702133370022660 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_A +define+INLINE_D'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_var.pl0000775000177100017500000000163013702133370021020 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( make_top_shell => 0, make_main => 0, make_pli => 1, sim_time => 2100, iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], v_flags2 => ["+define+USE_VPI_NOT_DPI"], verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_var.cpp"], ); execute( iv_pli => 1, check_finished => 1, all_run_flags => ['+PLUS +INT=1234 +STRSTR'] ); ok(1); 1; verilator-4.038/test_regress/t/t_math_shift_rep.v0000664000177100017500000000353213702133370022200 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; //bug765; disappears if add this wire //wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values wire [7:0] a = crc[7:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [15:0] y; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .y (y[15:0]), // Inputs .a (a[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, y}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs y, // Inputs a ); input signed [7:0] a; output [15:0] y; // verilator lint_off WIDTH assign y = ~66'd0 <<< {4{a}}; // verilator lint_on WIDTH endmodule verilator-4.038/test_regress/t/t_vams_kwd_bad.out0000664000177100017500000002346013702133370022171 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:12:8: Unsupported: AMS reserved word not implemented: 'above' 12 | int above; | ^~~~~ %Error: t/t_vams_kwd_bad.v:12:13: syntax error, unexpected ';', expecting IDENTIFIER or randomize 12 | int above; | ^ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:13:8: Unsupported: AMS reserved word not implemented: 'abs' 13 | int abs; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:14:8: Unsupported: AMS reserved word not implemented: 'absdelay' 14 | int absdelay; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:15:8: Unsupported: AMS reserved word not implemented: 'abstol' 15 | int abstol; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:16:8: Unsupported: AMS reserved word not implemented: 'ac_stim' 16 | int ac_stim; | ^~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:17:8: Unsupported: AMS reserved word not implemented: 'access' 17 | int access; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:18:8: Unsupported: AMS reserved word not implemented: 'acos' 18 | int acos; | ^~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:19:8: Unsupported: AMS reserved word not implemented: 'acosh' 19 | int acosh; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:20:8: Unsupported: AMS reserved word not implemented: 'aliasparam' 20 | int aliasparam; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:21:8: Unsupported: AMS reserved word not implemented: 'analog' 21 | int analog; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:22:8: Unsupported: AMS reserved word not implemented: 'analysis' 22 | int analysis; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:23:8: Unsupported: AMS reserved word not implemented: 'assert' 23 | int assert; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:24:8: Unsupported: AMS reserved word not implemented: 'branch' 24 | int branch; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:25:8: Unsupported: AMS reserved word not implemented: 'connect' 25 | int connect; | ^~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:26:8: Unsupported: AMS reserved word not implemented: 'connectmodule' 26 | int connectmodule; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:27:8: Unsupported: AMS reserved word not implemented: 'connectrules' 27 | int connectrules; | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:28:8: Unsupported: AMS reserved word not implemented: 'continuous' 28 | int continuous; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:29:8: Unsupported: AMS reserved word not implemented: 'cross' 29 | int cross; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:30:8: Unsupported: AMS reserved word not implemented: 'ddt' 30 | int ddt; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:31:8: Unsupported: AMS reserved word not implemented: 'ddt_nature' 31 | int ddt_nature; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:32:8: Unsupported: AMS reserved word not implemented: 'ddx' 32 | int ddx; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:33:8: Unsupported: AMS reserved word not implemented: 'discipline' 33 | int discipline; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:34:8: Unsupported: AMS reserved word not implemented: 'discrete' 34 | int discrete; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:35:8: Unsupported: AMS reserved word not implemented: 'domain' 35 | int domain; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:36:8: Unsupported: AMS reserved word not implemented: 'driver_update' 36 | int driver_update; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:37:8: Unsupported: AMS reserved word not implemented: 'endconnectrules' 37 | int endconnectrules; | ^~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:38:8: Unsupported: AMS reserved word not implemented: 'enddiscipline' 38 | int enddiscipline; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:39:8: Unsupported: AMS reserved word not implemented: 'endnature' 39 | int endnature; | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:40:8: Unsupported: AMS reserved word not implemented: 'endparamset' 40 | int endparamset; | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:41:8: Unsupported: AMS reserved word not implemented: 'exclude' 41 | int exclude; | ^~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:42:8: Unsupported: AMS reserved word not implemented: 'final_step' 42 | int final_step; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:43:8: Unsupported: AMS reserved word not implemented: 'flicker_noise' 43 | int flicker_noise; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:44:8: Unsupported: AMS reserved word not implemented: 'flow' 44 | int flow; | ^~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:45:8: Unsupported: AMS reserved word not implemented: 'from' 45 | int from; | ^~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:46:8: Unsupported: AMS reserved word not implemented: 'ground' 46 | int ground; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:47:8: Unsupported: AMS reserved word not implemented: 'idt' 47 | int idt; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:48:8: Unsupported: AMS reserved word not implemented: 'idt_nature' 48 | int idt_nature; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:49:8: Unsupported: AMS reserved word not implemented: 'idtmod' 49 | int idtmod; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:50:8: Unsupported: AMS reserved word not implemented: 'inf' 50 | int inf; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:51:8: Unsupported: AMS reserved word not implemented: 'initial_step' 51 | int initial_step; | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:52:8: Unsupported: AMS reserved word not implemented: 'laplace_nd' 52 | int laplace_nd; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:53:8: Unsupported: AMS reserved word not implemented: 'laplace_np' 53 | int laplace_np; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:54:8: Unsupported: AMS reserved word not implemented: 'laplace_zd' 54 | int laplace_zd; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:55:8: Unsupported: AMS reserved word not implemented: 'laplace_zp' 55 | int laplace_zp; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:56:8: Unsupported: AMS reserved word not implemented: 'last_crossing' 56 | int last_crossing; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:57:8: Unsupported: AMS reserved word not implemented: 'limexp' 57 | int limexp; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:58:8: Unsupported: AMS reserved word not implemented: 'max' 58 | int max; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:59:8: Unsupported: AMS reserved word not implemented: 'merged' 59 | int merged; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:60:8: Unsupported: AMS reserved word not implemented: 'min' 60 | int min; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:61:8: Unsupported: AMS reserved word not implemented: 'nature' 61 | int nature; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:62:8: Unsupported: AMS reserved word not implemented: 'net_resolution' 62 | int net_resolution; | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:63:8: Unsupported: AMS reserved word not implemented: 'noise_table' 63 | int noise_table; | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:64:8: Unsupported: AMS reserved word not implemented: 'paramset' 64 | int paramset; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:65:8: Unsupported: AMS reserved word not implemented: 'potential' 65 | int potential; | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:66:8: Unsupported: AMS reserved word not implemented: 'resolveto' 66 | int resolveto; | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:67:8: Unsupported: AMS reserved word not implemented: 'slew' 67 | int slew; | ^~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:68:8: Unsupported: AMS reserved word not implemented: 'split' 68 | int split; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:69:8: Unsupported: AMS reserved word not implemented: 'timer' 69 | int timer; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:70:8: Unsupported: AMS reserved word not implemented: 'transition' 70 | int transition; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:71:8: Unsupported: AMS reserved word not implemented: 'units' 71 | int units; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:72:8: Unsupported: AMS reserved word not implemented: 'white_noise' 72 | int white_noise; | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:73:8: Unsupported: AMS reserved word not implemented: 'zi_nd' 73 | int zi_nd; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:74:8: Unsupported: AMS reserved word not implemented: 'zi_np' 74 | int zi_np; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:75:8: Unsupported: AMS reserved word not implemented: 'zi_zd' 75 | int zi_zd; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:76:8: Unsupported: AMS reserved word not implemented: 'zi_zp' 76 | int zi_zp; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_past_unsup_bad.v0000664000177100017500000000055613702133370022216 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (d, clk); input d; input clk; always @ (posedge clk) begin // Unsupported if ($past(d, 0, 0, 0)) $stop; end endmodule verilator-4.038/test_regress/t/t_lint_restore_bad.pl0000775000177100017500000000107613702133370022675 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_export.v0000664000177100017500000000617013702133370021362 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `endif module t; sub a (.inst(1)); sub b (.inst(2)); // Returns integer line number, or -1 for all ok import "DPI-C" context function int dpix_run_tests(); export "DPI-C" task dpix_t_int; task dpix_t_int(input int i, output int o); o = ~i; endtask export "DPI-C" dpix_t_renamed = task dpix_t_ren; task dpix_t_ren(input int i, output int o); o = i+2; endtask export "DPI-C" function dpix_int123; function int dpix_int123(); dpix_int123 = 32'h123; endfunction export "DPI-C" function dpix_f_bit; export "DPI-C" function dpix_f_bit15; export "DPI-C" function dpix_f_int; export "DPI-C" function dpix_f_byte; export "DPI-C" function dpix_f_shortint; export "DPI-C" function dpix_f_longint; export "DPI-C" function dpix_f_chandle; function bit dpix_f_bit (bit i); dpix_f_bit = ~i; endfunction function bit [14:0] dpix_f_bit15 (bit [14:0] i); dpix_f_bit15 = ~i; endfunction function int dpix_f_int (int i); dpix_f_int = ~i; endfunction function byte dpix_f_byte (byte i); dpix_f_byte = ~i; endfunction function shortint dpix_f_shortint(shortint i); dpix_f_shortint = ~i; endfunction function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction export "DPI-C" task dpix_t_bit48; task dpix_t_bit48(input bit [47:0] i, output bit [47:0] o); o = ~i; endtask export "DPI-C" task dpix_t_bit95; task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask export "DPI-C" task dpix_t_bit96; task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask export "DPI-C" task dpix_t_reg; task dpix_t_reg(input reg i, output reg o); o = ~i; endtask export "DPI-C" task dpix_t_reg15; task dpix_t_reg15(input reg [14:0] i, output reg [14:0] o); o = ~i; endtask export "DPI-C" task dpix_t_reg95; task dpix_t_reg95(input reg [94:0] i, output reg [94:0] o); o = ~i; endtask export "DPI-C" task dpix_t_integer; task dpix_t_integer(input integer i, output integer o); o = ~i; endtask `ifndef NO_TIME export "DPI-C" task dpix_t_time; `endif task dpix_t_time(input time i, output time o); o = ~i; endtask int lineno; initial begin lineno = dpix_run_tests(); if (lineno != -1) begin $display("[%0t] %%Error: t_dpix_ort_c.c:%0d: dpix_run_tests returned an error", $time, lineno); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (input int inst); export "DPI-C" function dpix_sub_inst; function int dpix_sub_inst (int i); dpix_sub_inst = inst + i; endfunction endmodule verilator-4.038/test_regress/t/t_time_vpi_1ps1fs.out0000664000177100017500000000125613702133370022560 0ustar wsnyderwsnyder:: In top.t Time scale of t is 1ps / 1fs [60000] time%0d=60 123%0t=123000 dig%0t=5432109876543000 dig%0d=5432109876543 rdig%0t=5432109876543209 rdig%0f=5432109876543.209961 [0.060000ns] time%0d=60 123%0t=0.123000ns dig%0t=5432109876.543000ns dig%0d=5432109876543 rdig%0t=5432109876.543209ns rdig%0f=5432109876543.209961 [0.060000ns] stime%0t=0.060000ns stime%0d=60 stime%0f=60.000000 [0.060000ns] rtime%0t=0.059999ns rtime%0d=60 rtime%0f=60.000000 global vpiSimTime = 0,60000 vpiScaledRealTime = 60000 global vpiTimeUnit = -12 vpiTimePrecision = -15 top.t vpiSimTime = 0,60000 vpiScaledRealTime = 60 top.t vpiTimeUnit = -12 vpiTimePrecision = -15 *-* All Finished *-* verilator-4.038/test_regress/t/t_class_typedef.pl0000775000177100017500000000117613702133367022212 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_class_extends.out0000664000177100017500000000273613702133367022420 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_extends.v:13:21: Unsupported: class extends 13 | class Base1 extends Base0; | ^~~~~ %Error: t/t_class_extends.v:13:21: Found definition of 'Base0' as a CLASS but expected a variable 13 | class Base1 extends Base0; | ^~~~~ %Error-UNSUPPORTED: t/t_class_extends.v:18:21: Unsupported: class extends 18 | class Base2 extends Base1; | ^~~~~ %Error: t/t_class_extends.v:18:21: Found definition of 'Base1' as a CLASS but expected a variable 18 | class Base2 extends Base1; | ^~~~~ %Error-UNSUPPORTED: t/t_class_extends.v:22:19: Unsupported: class extends 22 | class Cls extends Base2; | ^~~~~ %Error: t/t_class_extends.v:22:19: Found definition of 'Base2' as a CLASS but expected a variable 22 | class Cls extends Base2; | ^~~~~ %Error: t/t_class_extends.v:25:4: Can't find typedef: 'T' 25 | T imemberc; | ^ %Error-UNSUPPORTED: t/t_class_extends.v:33:43: Unsupported: class extends 33 | class uvm__registry #(type T=int) extends uvm_object_wrapper; | ^~~~~~~~~~~~~~~~~~ %Error: t/t_class_extends.v:33:43: Found definition of 'uvm_object_wrapper' as a CLASS but expected a variable 33 | class uvm__registry #(type T=int) extends uvm_object_wrapper; | ^~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_tri_inz.cpp0000664000177100017500000000246113702133370021177 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_inz.h" Vt_tri_inz* tb = NULL; bool pass = true; double sc_time_stamp() { return 0; } void checkone(const char* name, int got, int exp) { if (got != exp) { printf("%%Error: For %s got=%d exp=%d\n", name, got, exp); pass = false; } } void check(int d, int en, int exp0, int exp1, int expx, int expz) { tb->d = d; tb->d__en0 = en; tb->eval(); #ifdef TEST_VERBOSE printf("Drive d=%d en=%d got0=%d/1=%d/x=%d/z=%d exp0=%d/1=%d/x=%d/z=%d\n", d, en, tb->ext0, tb->ext1, tb->extx, tb->extz, exp0, exp1, expx, expz); #endif if (!expz) checkone("ext0", tb->ext0, exp0); if (!expz) checkone("ext1", tb->ext1, exp1); checkone("extx", tb->extx, expx); checkone("extz", tb->extz, expz); } int main() { Verilated::debug(0); tb = new Vt_tri_inz("tb"); check(0, 1, 1,0,0,0); check(1, 1, 0,1,0,0); check(0, 0, 0,0,0,1); if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from t_tri_inz\n"); } return 0; } verilator-4.038/test_regress/t/TestSimulator.h0000664000177100017500000000522313702133367021467 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2013-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "vpi_user.h" #include class TestSimulator { private: struct SimTypes { int verilator; int icarus; int mti; int ncsim; int vcs; }; s_vpi_vlog_info m_info; SimTypes m_simulators; public: TestSimulator() { vpi_get_vlog_info(&m_info); if (0 == strcmp(m_info.product, "Verilator")) { m_simulators.verilator = true; } else if (0 == strcmp(m_info.product, "Verilator")) { m_simulators.icarus = true; } else if (0 == strncmp(m_info.product, "Chronologic Simulation VCS", strlen("Chronologic Simulation VCS"))) { m_simulators.vcs = true; } else { printf("%%Warning: %s:%d: Unknown simulator in TestSimulator.h: %s\n", __FILE__, __LINE__, m_info.product); } } ~TestSimulator() { } // METHORS private: static TestSimulator& singleton() { static TestSimulator s_singleton; return s_singleton; } static const SimTypes& simulators() { return singleton().m_simulators; } public: static const s_vpi_vlog_info& get_info() { return singleton().m_info; } // Simulator names static bool is_icarus() { return simulators().icarus; } static bool is_verilator() { return simulators().verilator; } static bool is_mti() { return simulators().mti; } static bool is_ncsim() { return simulators().ncsim; } static bool is_vcs() { return simulators().vcs; } // Simulator properties static bool is_event_driven() { return !simulators().verilator; } static bool has_get_scalar() { return !simulators().icarus; } // return test level scope static const char* top() { if (simulators().verilator) { return "t"; } else { return "top.t"; } } // return absolute scope of obj static const char* rooted(const char* obj) { static std::string buf; std::ostringstream os; os< 1); lint( v_flags2 => ["-Wall -Wno-DECLFILENAME --if-depth 10"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_bound1.pl0000775000177100017500000000105313702133370022100 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface.v0000664000177100017500000000624313702133370021146 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic rst = 1'b1; // reset integer rst_cnt = 0; // reset is removed after a delay always @ (posedge clk) begin rst_cnt <= rst_cnt + 1; rst <= rst_cnt <= 3; end // counters int cnt; int cnt_src; int cnt_drn; // add all counters assign cnt = cnt_src + cnt_drn + inf.cnt; // finish report always @ (posedge clk) if (cnt == 3*16) begin $write("*-* All Finished *-*\n"); $finish; end // interface instance handshake inf ( .clk (clk), .rst (rst) ); // source instance source #( .RW (8), .RP (8'b11100001) ) source ( .clk (clk), .rst (rst), .inf (inf), .cnt (cnt_src) ); // drain instance drain #( .RW (8), .RP (8'b11010100) ) drain ( .clk (clk), .rst (rst), .inf (inf), .cnt (cnt_drn) ); endmodule : t // interface definition interface handshake #( parameter int unsigned WC = 32 )( input logic clk, input logic rst ); // modport signals logic req; // request logic grt; // grant logic inc; // increment // local signals integer cnt; // counter // source modport src ( output req, input grt ); // drain modport drn ( input req, output grt ); // incremet condition assign inc = req & grt; // local logic (counter) always @ (posedge clk, posedge rst) if (rst) cnt <= '0; else cnt <= cnt + {31'h0, inc}; endinterface : handshake // source module module source #( // random generator parameters parameter int unsigned RW=1, // LFSR width parameter bit [RW-1:0] RP='0, // LFSR polinom parameter bit [RW-1:0] RR='1 // LFSR reset state )( input logic clk, input logic rst, handshake.src inf, output integer cnt ); // LFSR logic [RW-1:0] rnd; // LFSR in Galois form always @ (posedge clk, posedge rst) if (rst) rnd <= RR; else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); // counter always @ (posedge clk, posedge rst) if (rst) cnt <= 32'd0; else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; // request signal assign inf.req = rnd[0]; endmodule : source // drain module module drain #( // random generator parameters parameter int unsigned RW=1, // LFSR width parameter bit [RW-1:0] RP='0, // LFSR polinom parameter bit [RW-1:0] RR='1 // LFSR reset state )( input logic clk, input logic rst, handshake.drn inf, output integer cnt ); // LFSR logic [RW-1:0] rnd; // LFSR in Galois form always @ (posedge clk, posedge rst) if (rst) rnd <= RR; else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); // counter always @ (posedge clk, posedge rst) if (rst) cnt <= 32'd0; else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; // grant signal assign inf.grt = rnd[0]; endmodule : drain verilator-4.038/test_regress/t/t_delay.pl0000775000177100017500000000114413702133370020450 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['-Wno-STMTDLY -Wno-ASSIGNDLY'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_missing_bad.v0000664000177100017500000000104513702133370023500 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Missing interface test // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 // Interface intentionally not defined //interface foo_intf; // logic a; //endinterface module foo_mod ( foo_intf foo ); endmodule module t (/*AUTOARG*/); foo_intf the_foo (); foo_mod foo_mod ( .foo (the_foo) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_array5.pl0000775000177100017500000000105313702133370021734 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex_structs.pl0000775000177100017500000000244013702133370023766 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_complex.v"); compile( verilator_flags2 => ['--cc --trace --trace-structs --no-trace-params'], ); execute( check_finished => 1, ); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp /); file_grep_not ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_arrp /); file_grep_not ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arrp\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_strp\(/); vcd_identical ("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_mem_packed_bad.pl0000775000177100017500000000107413702133370022247 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen9.pl0000775000177100017500000000106013702133370022231 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_alias_unsup.out0000664000177100017500000000025313702133367022074 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_alias_unsup.v:46:4: Unsupported: alias statements 46 | alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_wire_beh1364_bad.pl0000775000177100017500000000146013702133370022263 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $waiver_filename = "$Self->{obj_dir}/$Self->{name}_waiver.vlt"; lint( verilator_flags2 => ["--lint-only --language 1364-2001 --waiver-output ${waiver_filename}"], fails => 1, expect_filename => $Self->{golden_filename}, ); if (-e $waiver_filename) { error("Waiver file generated, not expected.."); } ok(1); 1; verilator-4.038/test_regress/t/t_gen_missing_bad.out0000664000177100017500000000132013702133370022647 0ustar wsnyderwsnyder%Error: t/t_gen_missing.v:43:20: Cannot find file containing module: 'foo_not_needed' 43 | foo_not_needed i_foo(.x(foo[j]), .y(bar[j])); | ^~~~~~~~~~~~~~ ... Looked in: t/foo_not_needed t/foo_not_needed.v t/foo_not_needed.sv ../include/foo_not_needed ../include/foo_not_needed.v ../include/foo_not_needed.sv foo_not_needed foo_not_needed.v foo_not_needed.sv obj_vlt/t_gen_missing_bad/foo_not_needed obj_vlt/t_gen_missing_bad/foo_not_needed.v obj_vlt/t_gen_missing_bad/foo_not_needed.sv %Error: Exiting due to verilator-4.038/test_regress/t/t_func_const.v0000664000177100017500000000624313702133370021347 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package testpackage; localparam PARAM = 1024 >> 3; endpackage import testpackage::*; module t; localparam P4 = f_add(P3,1); localparam P8 = f_add2(P3,P3,f_add(1,1)); localparam P5 = f_while(7); localparam P16 = f_for(P4); localparam P18 = f_case(P4); localparam P6 = f_return(P4); localparam P3 = 3; localparam P128 = f_package(); typedef struct packed { logic [7:0] data; } type_t; typedef type_t [1:0] flist; localparam flist PLIST = {8'd4,8'd8}; localparam flist PARR = f_list_swap_2(PLIST); typedef struct packed { logic first; logic second; logic [31:0] data; } bigstruct_t; localparam bigstruct_t bigparam = f_return_struct(1'b1, 1'b0, 32'hfff12fff); initial begin `ifdef TEST_VERBOSE $display("P5=%0d P8=%0d P16=%0d P18=%0d",P5,P8,P16,P18); `endif if (P3 !== 3) $stop; if (P4 !== 4) $stop; if (P5 !== 5) $stop; if (P6 !== 6) $stop; if (P8 !== 8) $stop; if (P16 !== 16) $stop; if (P18 !== 18) $stop; if (PARR[0] != PLIST[1]) $stop; if (PARR[1] != PLIST[0]) $stop; if (bigparam.first != 1'b1) $stop; if (bigparam.second != 1'b0) $stop; if (bigparam.data != 32'hfff12fff) $stop; if (P128 != 128) $stop; $write("*-* All Finished *-*\n"); $finish; end function integer f_package(); return PARAM; endfunction function integer f_add(input [31:0] a, input [31:0] b); f_add = a+b; endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); f_add2 = f_add(a,b)+c; endfunction // Speced ok: local variables function integer f_for(input [31:0] a); integer i; integer times; begin times = 1; for (i=0; i1) break; end while (1) begin out = out+1; if (a>1) return 2+out; end f_return = 0; endfunction function flist f_list_swap_2(input flist in_list); f_list_swap_2[0].data = in_list[1].data; f_list_swap_2[1].data = in_list[0].data; endfunction function bigstruct_t f_return_struct(input first, input second, input [31:0] data); bigstruct_t result; result.data = data; result.first = first; result.second = second; return result; endfunction endmodule verilator-4.038/test_regress/t/t_pp_display.pl0000775000177100017500000000112613702133370021516 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_dumporder_bad.pl0000775000177100017500000000117213702133370023340 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ["-trace"], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_overlap_bad.pl0000775000177100017500000000107413702133370022656 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_modport_bad.v0000664000177100017500000000100713702133370023511 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer ok; modport out_modport (output ok); endinterface module t (/*AUTOARG*/); ifc itop(); counter_ansi c1 (.isub(itop), .i_value(4'h4)); endmodule module counter_ansi ( ifc.oop_modport isub, // Bad input logic [3:0] i_value ); endmodule verilator-4.038/test_regress/t/t_interface_ref_trace_inla.pl0000775000177100017500000000150313702133370024326 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_ref_trace.v"); $Self->{golden_filename} = "t/t_interface_ref_trace.out"; compile( v_flags2 => ['+define+NO_INLINE_A'], verilator_flags2 => ['--trace-structs --trace'], ); execute( check_finished => 1, ); vcd_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_flag_future_bad.pl0000775000177100017500000000113613702133370022464 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_future.v"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_misarray_bad.pl0000775000177100017500000000107513702133370023047 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen11_noinl.pl0000775000177100017500000000116113702133370023503 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen11.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_persist2.v0000664000177100017500000000041413702133370022505 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 Inside `__FILE__. `include "t_preproc_persist_inc.v" verilator-4.038/test_regress/t/t_sys_writemem.gold5.mem0000664000177100017500000000005213631173020023244 0ustar wsnyderwsnyder02 03 04 05 06 07 10 00 00 00 14 15 00 00 verilator-4.038/test_regress/t/t_unopt_combo_waive.pl0000775000177100017500000000126513702133370023075 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_unopt_combo.v"); compile( v_flags2 => ['+define+ATTRIBUTES', "t/t_unopt_combo.vlt"], expect_filename => $Self->{golden_filename}, # Expect no output, as we waived ); ok(1); 1; verilator-4.038/test_regress/t/t_alw_splitord.pl0000775000177100017500000000126713702133367022071 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats"], ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_bind2.v0000664000177100017500000000413613702133367020211 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Ed Lander. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] p1; reg [7:0] p2; reg [7:0] p3; initial begin p1 = 8'h01; p2 = 8'h02; p3 = 8'h03; end parameter int param1 = 8'h11; parameter int param2 = 8'h12; parameter int param3 = 8'h13; targetmod i_targetmod (/*AUTOINST*/ // Inputs .clk (clk)); //Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod //param1 not over-riden (as mycheck) (=> 0x31) //param2 explicitly bound to targetmod value (=> 0x22) //param3 explicitly bound to top value (=> 0x13) //p1 implictly bound (.*), takes value from targetmod (=> 0x04) //p2 explictly bound to targetmod (=> 0x05) //p3 explictly bound to top (=> 0x03) // Alternative unsupported form is i_targetmod bind targetmod mycheck #( .param2(param2), .param3(param3) ) i_mycheck (.p2(p2), .p3(p3), .*); endmodule module targetmod (input clk); reg [7:0] p1; reg [7:0] p2; reg [7:0] p3; parameter int param1 = 8'h21; parameter int param2 = 8'h22; parameter int param3 = 8'h23; initial begin p1 = 8'h04; p2 = 8'h05; p3 = 8'h06; end endmodule module mycheck (/*AUTOARG*/ // Inputs clk, p1, p2, p3 ); input clk; input [7:0] p1; input [7:0] p2; input [7:0] p3; parameter int param1 = 8'h31; parameter int param2 = 8'h32; parameter int param3 = 8'h33; always @ (posedge clk) begin `checkh(param1,8'h31); `checkh(param2,8'h22); `checkh(param3,8'h23); `checkh(p1,8'h04); `checkh(p2,8'h05); `checkh(p3,8'h06); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_slice_cond.v0000664000177100017500000000171713702133370021311 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dataout, // Inputs clk, sel, d0, d1 ); input clk; input sel; logic [7:0] data [1:0][3:0]; input [7:0] d0, d1; output wire [8*2*4-1:0] dataout; always_comb begin for ( integer j = 0; j <= 1; j++ ) begin if (sel) data[j] = '{ d0, d1, 8'h00, 8'h00 }; else data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 }; end for ( integer j = 0; j <= 1; j++ ) begin data[j] = sel ? '{ d0, d1, 8'h00, 8'h00 } : '{ 8'h00, 8'h00, 8'h00, 8'h00 }; end end assign dataout = {data[0][0], data[0][1], data[0][2], data[0][3], data[1][0], data[1][1], data[1][2], data[1][3]}; endmodule verilator-4.038/test_regress/t/t_param_chain.v0000664000177100017500000000151013702133370021440 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); function integer max2; input integer x; input integer y; begin begin : blk automatic int temp; temp = x; end end max2 = ( x > y ) ? x : y; endfunction function integer max4; input integer x; input integer y; input integer z; input integer w; // MAX2 is used multiple times max4 = max2( max2( x, y ), max2( z, w ) ); endfunction localparam MAX4 = max4( 1, 1, 0, 0 ); initial begin if (MAX4 != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_alw_split_cond.pl0000775000177100017500000000100113702133367022351 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_assoc.v0000664000177100017500000000705113702133367020322 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; integer i; always @ (posedge clk) begin cyc <= cyc + 1; begin // Type typedef bit [3:0] nibble_t; string a [nibble_t]; string b [nibble_t]; nibble_t k; string v; a[4'd3] = "fooed"; a[4'd2] = "bared"; i = a.num(); `checkh(i, 2); i = a.size; `checkh(i, 2); // Also checks no parens v = a[4'd3]; `checks(v, "fooed"); v = a[4'd2]; `checks(v, "bared"); i = a.exists(4'd0); `checkh(i, 0); i = a.exists(4'd2); `checkh(i, 1); i = a.first(k); `checkh(i, 1); `checks(k, 4'd2); i = a.next(k); `checkh(i, 1); `checks(k, 4'd3); i = a.next(k); `checkh(i, 0); i = a.last(k); `checkh(i, 1); `checks(k, 4'd3); i = a.prev(k); `checkh(i, 1); `checks(k, 4'd2); i = a.prev(k); `checkh(i, 0); v = $sformatf("%p", a); `checks(v, "'{'h2:\"bared\", 'h3:\"fooed\"} "); a.delete(4'd2); i = a.size(); `checkh(i, 1); b = a; // Copy assignment i = b.size(); `checkh(i, 1); end begin // Strings string a [string]; string k; string v; a["foo"] = "fooed"; a["bar"] = "bared"; i = a.num(); `checkh(i, 2); i = a.size(); `checkh(i, 2); v = a["foo"]; `checks(v, "fooed"); v = a["bar"]; `checks(v, "bared"); i = a.exists("baz"); `checkh(i, 0); i = a.exists("bar"); `checkh(i, 1); i = a.first(k); `checkh(i, 1); `checks(k, "bar"); i = a.next(k); `checkh(i, 1); `checks(k, "foo"); i = a.next(k); `checkh(i, 0); i = a.last(k); `checkh(i, 1); `checks(k, "foo"); i = a.prev(k); `checkh(i, 1); `checks(k, "bar"); i = a.prev(k); `checkh(i, 0); v = $sformatf("%p", a["foo"]); `checks(v, "\"fooed\""); v = $sformatf("%p", a); `checks(v, "'{\"bar\":\"bared\", \"foo\":\"fooed\"} "); a.delete("bar"); i = a.size(); `checkh(i, 1); a.delete(); i = a.size(); `checkh(i, 0); i = a.first(k); `checkh(i, 0); i = a.last(k); `checkh(i, 0); // Patterns & default `ifndef VERILATOR // Unsupported: Pattern assignment a = '{ "f": "fooed", "b": "bared", default: "defaulted" }; i = a.size(); `checkh(i, 2); // Default doesn't count v = a["f"]; `checks(v, "fooed"); v = a["b"]; `checks(v, "bared"); v = a["NEXISTS"]; `checks(v, "defaulted"); `endif end begin // Wide-wides - need special array container classes, ick. logic [91:2] a [ logic [65:1] ]; a[~65'hfe] = ~ 90'hfee; `checkh(a[~65'hfe], ~ 90'hfee); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_sys_file_basic_uz.pl0000775000177100017500000000147213702133370023052 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); unlink("$Self->{obj_dir}/t_sys_file_basic_uz_test.log"); compile(); execute( check_finished => 1, ); files_identical("$Self->{obj_dir}/t_sys_file_basic_uz_test.log", $Self->{golden_filename}); files_identical("$Self->{obj_dir}/t_sys_file_basic_uz_test.bin", "$Self->{t_dir}/t_sys_file_basic_uz.dat"); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_sys.pl0000775000177100017500000000112213702133370021020 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["t/t_dpi_sys_c.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_genfor_hier.pl0000775000177100017500000000105313702133370021640 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl0000775000177100017500000000263013702133370025621 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_tree.v"); compile( verilator_flags2 => ['--stats', '--norelative-cfuncs', "$Self->{t_dir}/t_inst_tree_inl0_pub1.vlt", $Self->wno_unopthreads_for_few_cores()] ); if ($Self->{vlt_all}) { # Fewer optimizations than t_inst_tree_inl0_pub1 which allows # relative CFuncs: file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, ($Self->{vltmt} ? 0 : 31)); # Should not find any 'this->' except some 'this->__VlSymsp' my @files = `ls $Self->{obj_dir}/*.cpp`; foreach my $file (@files) { chomp $file; my $text = file_contents($file); $text =~ s/this->__VlSymsp//g; if ($text =~ m/this->/) { error("$file has unexpected this-> refs when --norelative-cfuncs"); } } } execute( check_finished => 1, expect => '\] (%m|.*t\.ps): Clocked ', ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_down.pl0000775000177100017500000000106013702133370022336 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_sc_bad.pl0000775000177100017500000000144213702133370021604 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_time_sc.v"); $Self->{sc_time_resolution} = 'SC_NS'; compile( verilator_flags2 => ['-sc', '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution '+define+TEST_EXPECT=2us'], ); execute( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_banks.pl0000775000177100017500000000105313702133370021305 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_l.v0000664000177100017500000000061113702133370021157 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: $display() test for %l // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); initial begin assert (0 == 0) else $fatal(2, "%l %m : %d", 0); $display("%l %m"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_modport_export.pl0000775000177100017500000000115613702133370024462 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug696"); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_bad_msb.v0000664000177100017500000000067213702133370022134 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [43:0] mi; reg [3:0] sel2; reg [0:22] backwd; always @ (posedge clk) begin mi = 44'h123; sel2 = mi[1:4]; $write ("Bad select %x\n", sel2); end endmodule verilator-4.038/test_regress/t/t_inst_dearray_slice.pl0000775000177100017500000000105313702133370023214 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_nonamebegin.v0000664000177100017500000000320313702133370022331 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, reset_l ); input clk; input reset_l; reg inmod; generate if (1) begin // Traces as genblk1.ingen integer ingen; initial $display("ingen: {mod}.genblk1 %m"); end endgenerate integer rawmod; initial begin begin integer upa; begin : d3nameda // %m='.d3nameda' var=_unnamed#.d3nameda.b1 integer d3a; $display("d3a: {mod}.d3nameda %m"); end end end initial begin integer b2; $display("b2: {mod} %m"); begin : b3named integer b3n; $display("b3n: {mod}.b3named: %m"); end if (1) begin integer b3; $display("b3: {mod} %m"); if (1) begin begin begin begin integer b4; $display("b4: {mod} %m"); end end end end else begin integer b4; $display("bb %m"); end end else begin integer b4; $display("b4 %m"); end tsk; $write("*-* All Finished *-*\n"); $finish; end task tsk; integer t1; $display("t1 {mod}.tsk %m"); begin integer t2; $display("t2 {mod}.tsk %m"); end endtask endmodule verilator-4.038/test_regress/t/t_math_repl.pl0000775000177100017500000000105313702133370021324 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_default_warn.v0000664000177100017500000000115213702133370022666 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed // default function argument // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 function logic foo ( // Intentionally provide a non-width'ed default value // This should warn, not error out input logic x = 0 ); return x; endfunction module t (/*AUTOARG*/); logic foo_val; initial begin foo_val = foo(); if (foo_val != 1'b0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_bad_hide2.out0000664000177100017500000000062613702133370022220 0ustar wsnyderwsnyder%Warning-VARHIDDEN: t/t_var_bad_hide2.v:14:12: Declaration of signal hides declaration in upper scope: 't' 14 | integer t; | ^ t/t_var_bad_hide2.v:7:8: ... Location of original declaration 7 | module t; | ^ ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_flag_xinitial_0.pl0000775000177100017500000000125013702133370022401 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( verilator_flags2 => ["--x-initial 0"], ); execute( check_finished => 1, ); file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}__Slow.cpp", qr/VL_RAND_RESET/); ok(1); 1; verilator-4.038/test_regress/t/t_array_backw_index_bad.out0000664000177100017500000000240113702133367024030 0ustar wsnyderwsnyder%Error: t/t_array_backw_index_bad.v:14:19: Slice selection '[1:3]' has backward indexing versus data type's '[3:0]' : ... In instance t 14 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; | ^ %Error: t/t_array_backw_index_bad.v:15:20: Slice selection '[3:1]' has backward indexing versus data type's '[0:3]' : ... In instance t 15 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; | ^ %Error: t/t_array_backw_index_bad.v:17:19: Slice selection index '[4:3]' outside data type's '[3:0]' : ... In instance t 17 | array_assign[4:3] = '{32'd4, 32'd3}; | ^ %Error: t/t_array_backw_index_bad.v:18:19: Slice selection index '[1:-1]' outside data type's '[3:0]' : ... In instance t 18 | array_assign[1:-1] = '{32'd4, 32'd3}; | ^ %Error: t/t_array_backw_index_bad.v:18:28: Assignment pattern missed initializing elements: -1 : ... In instance t 18 | array_assign[1:-1] = '{32'd4, 32'd3}; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_off_cc.pl0000775000177100017500000000133413702133370021750 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_ena.v"); compile( verilator_flags2 => ['-notrace'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { !-r "$Self->{obj_dir}/simx.vcd" or error("Tracing should be off\n"); } ok(1); 1; verilator-4.038/test_regress/t/t_vpi_stop_bad.pl0000775000177100017500000000123713702133370022026 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["--vpi t/t_vpi_stop_bad_c.cpp"], ); execute( fails => 1, check_finished => 0, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_unimpl.pl0000775000177100017500000000130713702133370021535 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_unimpl.cpp"], ); execute( check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_bad_notfound.out0000664000177100017500000000012013702133370024566 0ustar wsnyderwsnyder%Error: t/t_sys_readmem_bad_NOTFOUND.mem:0: $readmem file not found Aborting... verilator-4.038/test_regress/t/t_package_abs.v0000664000177100017500000000144213702133370021422 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // see bug491 package functions; function real abs (real num); abs = (num <0) ? -num : num; endfunction function real neg (real num); return -abs(num); // Check package funcs can call package funcs endfunction endpackage module t (); import functions::*; localparam P = 1; generate if (P == 1) begin initial begin if (abs(-2.1) != 2.1) $stop; if (abs(2.2) != 2.2) $stop; if (neg(-2.1) != -2.1) $stop; if (neg(2.2) != -2.2) $stop; $write("*-* All Finished *-*\n"); $finish; end end endgenerate endmodule verilator-4.038/test_regress/t/t_typedef_signed.pl0000775000177100017500000000105313702133370022342 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_display_c.cpp0000664000177100017500000000214313702133370022321 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_display__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { extern void dpii_display_call(const char* c); } #endif #ifndef VL_PRINTF # define VL_PRINTF printf #endif //====================================================================== void dpii_display_call(const char* c) { VL_PRINTF("dpii_display_call: '%s'\n", c); } verilator-4.038/test_regress/t/t_lint_setout_bad_noinl.pl0000775000177100017500000000122113702133370023724 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_lint_setout_bad.v"); lint( verilator_flags2 => ["--lint-only -Oi"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inside.pl0000775000177100017500000000105313702133370020624 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_port_bad.pl0000775000177100017500000000107413702133370022016 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_array_fst_threads_1.pl0000775000177100017500000000142513702133370024456 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_trace_array.v"); $Self->{golden_filename} = "t/t_trace_array_fst.out"; compile( verilator_flags2 => ['--cc --trace-fst --trace-threads 1 --trace-structs'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_get.pl0000775000177100017500000000165213702133370021013 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); skip("Known compiler limitation") if $Self->cxx_version =~ /\(GCC\) 4.4/; compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_get.cpp"], make_pli => 1, iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2 => ["+define+USE_VPI_NOT_DPI +define+VERILATOR_COMMENTS"], ); execute( iv_pli => 1, check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_down_gen.v0000664000177100017500000000327613702133370023031 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // This test demonstrates how not only parameters but the type of a parent // interface could propagate down to child modules, changing their data type // determinations. Note presently unsupported in all commercial simulators. interface ifc; parameter MODE = 0; generate // Note block must be named per SystemVerilog 2005 if (MODE==1) begin : g integer value; end else if (MODE==2) begin : g real value; end endgenerate endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc #(1) itop1a(); ifc #(1) itop1b(); ifc #(2) itop2a(); ifc #(2) itop2b(); wrapper c1 (.isuba(itop1a), .isubb(itop1b), .i_valuea(14.1), .i_valueb(15.2)); wrapper c2 (.isuba(itop2a), .isubb(itop2b), .i_valuea(24.3), .i_valueb(25.4)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (itop1a.g.value != 14) $stop; if (itop1b.g.value != 15) $stop; if (itop2a.g.value != 24) $stop; if (itop2b.g.value != 25) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module wrapper ( ifc isuba, ifc isubb, input real i_valuea, input real i_valueb ); lower subsuba (.isub(isuba), .i_value(i_valuea)); lower subsubb (.isub(isubb), .i_value(i_valueb)); endmodule module lower ( ifc isub, input real i_value ); always @* begin `error Commercial sims choke on cross ref here isub.g.value = i_value; end endmodule verilator-4.038/test_regress/t/t_interface_param_acc_bits.out0000664000177100017500000000050513702133370024512 0ustar wsnyderwsnyder%Error: t/t_interface_param_acc_bits.v:15:42: Parameter-resolved constants must not use dotted references: 'dummy' : ... In instance t 15 | simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_dup_bad.pl0000775000177100017500000000107113702133370021617 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_inout_type__Dpi.out0000664000177100017500000003323713702133370024372 0ustar wsnyderwsnyder// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS // DPI export at t/t_dpi_arg_inout_type.v:571:18 extern void e_array_2_state_1(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:611:18 extern void e_array_2_state_128(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:579:18 extern void e_array_2_state_32(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:587:18 extern void e_array_2_state_33(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:595:18 extern void e_array_2_state_64(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:603:18 extern void e_array_2_state_65(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:718:18 extern void e_array_4_state_1(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:758:18 extern void e_array_4_state_128(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:726:18 extern void e_array_4_state_32(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:734:18 extern void e_array_4_state_33(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:742:18 extern void e_array_4_state_64(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:750:18 extern void e_array_4_state_65(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:422:18 extern void e_bit(svBit* x); // DPI export at t/t_dpi_arg_inout_type.v:554:18 extern void e_bit_t(svBit* x); // DPI export at t/t_dpi_arg_inout_type.v:307:18 extern void e_byte(char* x); // DPI export at t/t_dpi_arg_inout_type.v:439:18 extern void e_byte_t(char* x); // DPI export at t/t_dpi_arg_inout_type.v:314:18 extern void e_byte_unsigned(unsigned char* x); // DPI export at t/t_dpi_arg_inout_type.v:446:18 extern void e_byte_unsigned_t(unsigned char* x); // DPI export at t/t_dpi_arg_inout_type.v:397:18 extern void e_chandle(void** x); // DPI export at t/t_dpi_arg_inout_type.v:529:18 extern void e_chandle_t(void** x); // DPI export at t/t_dpi_arg_inout_type.v:335:18 extern void e_int(int* x); // DPI export at t/t_dpi_arg_inout_type.v:467:18 extern void e_int_t(int* x); // DPI export at t/t_dpi_arg_inout_type.v:342:18 extern void e_int_unsigned(unsigned int* x); // DPI export at t/t_dpi_arg_inout_type.v:474:18 extern void e_int_unsigned_t(unsigned int* x); // DPI export at t/t_dpi_arg_inout_type.v:373:18 extern void e_integer(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:505:18 extern void e_integer_t(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:430:18 extern void e_logic(svLogic* x); // DPI export at t/t_dpi_arg_inout_type.v:562:18 extern void e_logic_t(svLogic* x); // DPI export at t/t_dpi_arg_inout_type.v:349:18 extern void e_longint(long long* x); // DPI export at t/t_dpi_arg_inout_type.v:481:18 extern void e_longint_t(long long* x); // DPI export at t/t_dpi_arg_inout_type.v:356:18 extern void e_longint_unsigned(unsigned long long* x); // DPI export at t/t_dpi_arg_inout_type.v:488:18 extern void e_longint_unsigned_t(unsigned long long* x); // DPI export at t/t_dpi_arg_inout_type.v:381:18 extern void e_real(double* x); // DPI export at t/t_dpi_arg_inout_type.v:513:18 extern void e_real_t(double* x); // DPI export at t/t_dpi_arg_inout_type.v:321:18 extern void e_shortint(short* x); // DPI export at t/t_dpi_arg_inout_type.v:453:18 extern void e_shortint_t(short* x); // DPI export at t/t_dpi_arg_inout_type.v:328:18 extern void e_shortint_unsigned(unsigned short* x); // DPI export at t/t_dpi_arg_inout_type.v:460:18 extern void e_shortint_unsigned_t(unsigned short* x); // DPI export at t/t_dpi_arg_inout_type.v:409:18 extern void e_string(const char** x); // DPI export at t/t_dpi_arg_inout_type.v:541:18 extern void e_string_t(const char** x); // DPI export at t/t_dpi_arg_inout_type.v:620:18 extern void e_struct_2_state_1(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:660:18 extern void e_struct_2_state_128(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:628:18 extern void e_struct_2_state_32(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:636:18 extern void e_struct_2_state_33(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:644:18 extern void e_struct_2_state_64(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:652:18 extern void e_struct_2_state_65(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:767:18 extern void e_struct_4_state_1(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:807:18 extern void e_struct_4_state_128(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:775:18 extern void e_struct_4_state_32(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:783:18 extern void e_struct_4_state_33(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:791:18 extern void e_struct_4_state_64(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:799:18 extern void e_struct_4_state_65(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:364:18 extern void e_time(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:496:18 extern void e_time_t(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:669:18 extern void e_union_2_state_1(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:709:18 extern void e_union_2_state_128(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:677:18 extern void e_union_2_state_32(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:685:18 extern void e_union_2_state_33(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:693:18 extern void e_union_2_state_64(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:701:18 extern void e_union_2_state_65(svBitVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:816:18 extern void e_union_4_state_1(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:856:18 extern void e_union_4_state_128(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:824:18 extern void e_union_4_state_32(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:832:18 extern void e_union_4_state_33(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:840:18 extern void e_union_4_state_64(svLogicVecVal* x); // DPI export at t/t_dpi_arg_inout_type.v:848:18 extern void e_union_4_state_65(svLogicVecVal* x); // DPI IMPORTS // DPI import at t/t_dpi_arg_inout_type.v:867:41 extern void check_exports(); // DPI import at t/t_dpi_arg_inout_type.v:154:33 extern void i_array_2_state_1(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:159:33 extern void i_array_2_state_128(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:155:33 extern void i_array_2_state_32(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:156:33 extern void i_array_2_state_33(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:157:33 extern void i_array_2_state_64(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:158:33 extern void i_array_2_state_65(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:178:33 extern void i_array_4_state_1(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:183:33 extern void i_array_4_state_128(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:179:33 extern void i_array_4_state_32(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:180:33 extern void i_array_4_state_33(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:181:33 extern void i_array_4_state_64(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:182:33 extern void i_array_4_state_65(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:126:33 extern void i_bit(svBit* x); // DPI import at t/t_dpi_arg_inout_type.v:150:33 extern void i_bit_t(svBit* x); // DPI import at t/t_dpi_arg_inout_type.v:106:33 extern void i_byte(char* x); // DPI import at t/t_dpi_arg_inout_type.v:130:33 extern void i_byte_t(char* x); // DPI import at t/t_dpi_arg_inout_type.v:107:33 extern void i_byte_unsigned(unsigned char* x); // DPI import at t/t_dpi_arg_inout_type.v:131:33 extern void i_byte_unsigned_t(unsigned char* x); // DPI import at t/t_dpi_arg_inout_type.v:124:33 extern void i_chandle(void** x); // DPI import at t/t_dpi_arg_inout_type.v:148:33 extern void i_chandle_t(void** x); // DPI import at t/t_dpi_arg_inout_type.v:110:33 extern void i_int(int* x); // DPI import at t/t_dpi_arg_inout_type.v:134:33 extern void i_int_t(int* x); // DPI import at t/t_dpi_arg_inout_type.v:111:33 extern void i_int_unsigned(unsigned int* x); // DPI import at t/t_dpi_arg_inout_type.v:135:33 extern void i_int_unsigned_t(unsigned int* x); // DPI import at t/t_dpi_arg_inout_type.v:118:33 extern void i_integer(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:142:33 extern void i_integer_t(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:127:33 extern void i_logic(svLogic* x); // DPI import at t/t_dpi_arg_inout_type.v:151:33 extern void i_logic_t(svLogic* x); // DPI import at t/t_dpi_arg_inout_type.v:112:33 extern void i_longint(long long* x); // DPI import at t/t_dpi_arg_inout_type.v:136:33 extern void i_longint_t(long long* x); // DPI import at t/t_dpi_arg_inout_type.v:113:33 extern void i_longint_unsigned(unsigned long long* x); // DPI import at t/t_dpi_arg_inout_type.v:137:33 extern void i_longint_unsigned_t(unsigned long long* x); // DPI import at t/t_dpi_arg_inout_type.v:120:33 extern void i_real(double* x); // DPI import at t/t_dpi_arg_inout_type.v:144:33 extern void i_real_t(double* x); // DPI import at t/t_dpi_arg_inout_type.v:108:33 extern void i_shortint(short* x); // DPI import at t/t_dpi_arg_inout_type.v:132:33 extern void i_shortint_t(short* x); // DPI import at t/t_dpi_arg_inout_type.v:109:33 extern void i_shortint_unsigned(unsigned short* x); // DPI import at t/t_dpi_arg_inout_type.v:133:33 extern void i_shortint_unsigned_t(unsigned short* x); // DPI import at t/t_dpi_arg_inout_type.v:125:33 extern void i_string(const char** x); // DPI import at t/t_dpi_arg_inout_type.v:149:33 extern void i_string_t(const char** x); // DPI import at t/t_dpi_arg_inout_type.v:162:33 extern void i_struct_2_state_1(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:167:33 extern void i_struct_2_state_128(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:163:33 extern void i_struct_2_state_32(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:164:33 extern void i_struct_2_state_33(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:165:33 extern void i_struct_2_state_64(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:166:33 extern void i_struct_2_state_65(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:186:33 extern void i_struct_4_state_1(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:191:33 extern void i_struct_4_state_128(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:187:33 extern void i_struct_4_state_32(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:188:33 extern void i_struct_4_state_33(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:189:33 extern void i_struct_4_state_64(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:190:33 extern void i_struct_4_state_65(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:115:33 extern void i_time(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:139:33 extern void i_time_t(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:170:33 extern void i_union_2_state_1(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:175:33 extern void i_union_2_state_128(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:171:33 extern void i_union_2_state_32(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:172:33 extern void i_union_2_state_33(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:173:33 extern void i_union_2_state_64(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:174:33 extern void i_union_2_state_65(svBitVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:194:33 extern void i_union_4_state_1(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:199:33 extern void i_union_4_state_128(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:195:33 extern void i_union_4_state_32(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:196:33 extern void i_union_4_state_33(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:197:33 extern void i_union_4_state_64(svLogicVecVal* x); // DPI import at t/t_dpi_arg_inout_type.v:198:33 extern void i_union_4_state_65(svLogicVecVal* x); #ifdef __cplusplus } #endif verilator-4.038/test_regress/t/t_class_forward.pl0000775000177100017500000000105313702133367022210 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_ref.v0000664000177100017500000000357613702133370020640 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));; end while(0); module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc; int vr; int va[2]; `ifdef T_NOINLINE // verilator no_inline_module `endif //==== task fun(ref int r, const ref int c); `ifdef T_NOINLINE // verilator no_inline_task `endif `checkh(c, 32'h1234); r = 32'h4567; endtask initial begin int ci; int ri; ci = 32'h1234; fun(ri, ci); `checkh(ri, 32'h4567); end //==== task fun_array(ref int af[2], const ref int cf[2]); `ifdef T_NOINLINE // verilator no_inline_task `endif `checkh(cf[0], 32'h1234); `checkh(cf[1], 32'h2345); af[0] = 32'h5678; af[1] = 32'h6789; endtask // Not checkint - element of unpacked array initial begin int ca[2]; int ra[2]; ca[0] = 32'h1234; ca[1] = 32'h2345; fun_array(ra, ca); `checkh(ra[0], 32'h5678); `checkh(ra[1], 32'h6789); end //==== sub sub(.clk, .vr, .va); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin vr <= 32'h789; va[0] <= 32'h89a; va[1] <= 32'h9ab; end else if (cyc == 2) begin `checkh(vr, 32'h987); `checkh(va[0], 32'ha98); `checkh(va[1], 32'ha9b); $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub(input clk, ref int vr, ref int va[2]); always @(posedge clk) begin vr <= 32'h987; va[0] <= 32'ha98; va[1] <= 32'ha9b; end endmodule verilator-4.038/test_regress/t/t_pp_underline_bad.out0000664000177100017500000000062713702133370023042 0ustar wsnyderwsnyder%Error: t/t_pp_underline_bad.v:8:4: Extra underscore in meta-comment; use /*verilator {...}*/ not /*verilator_{...}*/ 8 | // verilator_no_inline_module | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_pp_underline_bad.v:8:4: Unknown verilator comment: '/*verilator _no_inline_module*/' 8 | /*verilator _no_inline_module*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_sys_fread.v0000664000177100017500000000614513702133370021166 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); //====================================================================== module t; integer file; integer r_i; byte r_upb[20:10]; byte r_dnb[20:10]; reg [13:0] r_ups[20:10]; reg [13:0] r_dns[10:20]; reg [30:0] r_upi[20:10]; reg [30:0] r_dni[10:20]; reg [61:0] r_upq[20:10]; reg [61:0] r_dnq[10:20]; reg [71:0] r_upw[20:10]; reg [71:0] r_dnw[10:20]; task clear; // Initialize memories to zero, // avoid differences between 2-state and 4-state. r_i = ~0; foreach (r_upb[i]) r_upb[i] = ~0; foreach (r_dnb[i]) r_dnb[i] = ~0; foreach (r_ups[i]) r_ups[i] = ~0; foreach (r_dns[i]) r_dns[i] = ~0; foreach (r_upi[i]) r_upi[i] = ~0; foreach (r_dni[i]) r_dni[i] = ~0; foreach (r_upq[i]) r_upq[i] = ~0; foreach (r_dnq[i]) r_dnq[i] = ~0; foreach (r_upw[i]) r_upw[i] = ~0; foreach (r_dnw[i]) r_dnw[i] = ~0; // Open file $fclose(file); file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_fread.mem"}, "r"); if ($feof(file)) $stop; endtask task dump; $write("Dump:"); $write("\n r_i:"); $write(" %x",r_i); $write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]); $write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]); $write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]); $write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]); $write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]); $write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]); $write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]); $write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]); $write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]); $write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]); $write("\n\n"); endtask integer code; initial begin clear; code = $fread(r_i, file); `checkd(code, 4); code = $fread(r_upb, file); `checkd(code, 11); code = $fread(r_dnb, file); `checkd(code, 11); code = $fread(r_ups, file); `checkd(code, 22); code = $fread(r_dns, file); `checkd(code, 22); code = $fread(r_upi, file); `checkd(code, 44); code = $fread(r_dni, file); `checkd(code, 44); code = $fread(r_upq, file); `checkd(code, 88); code = $fread(r_dnq, file); `checkd(code, 88); code = $fread(r_upw, file); `checkd(code, 99); code = $fread(r_dnw, file); `checkd(code, 99); dump; clear; code = $fread(r_upb, file, 15); `checkd(code, 6); code = $fread(r_ups, file, 15, 2); `checkd(code, 4); dump; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_tri_gen.v0000664000177100017500000000141713702133370020633 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; tri z0; tri z1; updown #(0) updown0 (.z(z0)); updown #(1) updown1 (.z(z1)); always @ (posedge clk) begin if (z0 !== 0) $stop; if (z1 !== 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module updown #(parameter UP=0) (inout z); generate if (UP) begin t_up sub (.z); end else begin t_down sub (.z); end endgenerate endmodule module t_up (inout tri1 z); endmodule module t_down (inout tri0 z); endmodule verilator-4.038/test_regress/t/t_inst_recurse_bad.out0000664000177100017500000000050413702133370023055 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_inst_recurse_bad.v:18:8: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): 'looped' ... note: self-recursion (module instantiating itself directly) is supported. 18 | module looped ( ); | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_verilated_debug.out0000664000177100017500000000214213702133370022667 0ustar wsnyderwsnyder-V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_verilated_debug::_ctor_var_reset internalsDump: Version: Verilator ### Argv: obj_vlt/t_verilated_debug/Vt_verilated_debug scopesDump: -V{t#,#}+++++TOP Evaluate Vt_verilated_debug::eval -V{t#,#}+ Vt_verilated_debug::_eval_debug_assertions -V{t#,#}+ Vt_verilated_debug::_eval_initial -V{t#,#}+ Vt_verilated_debug::_eval_settle -V{t#,#}+ Vt_verilated_debug::_eval -V{t#,#}+ Vt_verilated_debug::_change_request -V{t#,#}+ Vt_verilated_debug::_change_request_1 -V{t#,#}+ Clock loop -V{t#,#}+ Vt_verilated_debug::_eval -V{t#,#}+ Vt_verilated_debug::_change_request -V{t#,#}+ Vt_verilated_debug::_change_request_1 -V{t#,#}+++++TOP Evaluate Vt_verilated_debug::eval -V{t#,#}+ Vt_verilated_debug::_eval_debug_assertions -V{t#,#}+ Clock loop -V{t#,#}+ Vt_verilated_debug::_eval -V{t#,#}+ Vt_verilated_debug::_sequent__TOP__1 *-* All Finished *-* -V{t#,#}+ Vt_verilated_debug::_change_request -V{t#,#}+ Vt_verilated_debug::_change_request_1 -V{t#,#}+ Vt_verilated_debug::final verilator-4.038/test_regress/t/t_vlt_syntax_bad.pl0000775000177100017500000000116213702133370022373 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["t/t_vlt_syntax_bad.vlt"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_cat.cpp0000664000177100017500000000303313702133370021442 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include VM_PREFIX_INCLUDE unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const char* trace_name() { static char name[1000]; VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simpart_%04d.vcd", (int)main_time); return name; } int main(int argc, char** argv, char** env) { VM_PREFIX* top = new VM_PREFIX("top"); Verilated::debug(0); Verilated::traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; top->trace(tfp, 99); tfp->open(trace_name()); top->clk = 0; while (main_time < 190) { // Creates 2 files top->clk = !top->clk; top->eval(); if ((main_time % 100) == 0) { #if defined(T_TRACE_CAT) tfp->openNext(true); #elif defined(T_TRACE_CAT_REOPEN) tfp->close(); tfp->open(trace_name()); #elif defined(T_TRACE_CAT_RENEW) tfp->close(); delete tfp; tfp = new VerilatedVcdC; top->trace(tfp, 99); tfp->open(trace_name()); #else # error "Unknown test" #endif } tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); printf("*-* All Finished *-*\n"); return 0; } verilator-4.038/test_regress/t/t_display_esc_bad.pl0000775000177100017500000000107113702133370022456 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_default_presv_bad.pl0000775000177100017500000000124413702133370024204 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_param_default_bad.v"); lint( verilator_flags2 => ["--lint-only --language 1800-2005"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_type_bad.pl0000775000177100017500000000120413702133370022316 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( # Bug1575 required trace to crash verilator_flags2 => ["--trace"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_pattern_bad.pl0000775000177100017500000000107413702133367023043 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_write2.pl0000775000177100017500000000130213702133367021563 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats --O3 -x-assign fast"], ); execute( check_finished => 1, ); files_identical("$Self->{obj_dir}/$Self->{name}_logger.log", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_math_signed_wire.pl0000775000177100017500000000105313702133370022661 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_const_bad.v0000664000177100017500000000313313702133370022150 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Speced ignored: system calls. I think this is nasty, so we error instead. // Speced Illegal: inout/output/ref not allowed localparam B1 = f_bad_output(1,2); function integer f_bad_output(input [31:0] a, output [31:0] o); f_bad_output = 0; endfunction // Speced Illegal: void // Speced Illegal: dotted localparam EIGHT = 8; localparam B2 = f_bad_dotted(2); function integer f_bad_dotted(input [31:0] a); f_bad_dotted = t.EIGHT; endfunction // Speced Illegal: ref to non-local var integer modvar; localparam B3 = f_bad_nonparam(3); function integer f_bad_nonparam(input [31:0] a); f_bad_nonparam = modvar; endfunction // Speced Illegal: needs constant function itself // Our own - infinite loop localparam B4 = f_bad_infinite(3); function integer f_bad_infinite(input [31:0] a); while (1) begin f_bad_infinite = 0; end endfunction // Our own - stop localparam BSTOP = f_bad_stop(3); function integer f_bad_stop(input [31:0] a); $stop; endfunction // Verify $fatal works with sformatf as argument localparam BFATAL = f_bad_fatal(3); function integer f_bad_fatal(input [31:0] a); for (integer i=0;i<3;i++) begin $display("Printing in loop: %s", $sformatf("%d", i)); end $fatal(2, "%s", $sformatf("Fatal Error")); endfunction endmodule verilator-4.038/test_regress/t/t_dedupe_clk_gate.pl0000775000177100017500000000164513702133370022457 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( verilator_flags2 => ["--stats $Self->{t_dir}/t_dedupe_clk_gate.vlt"], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 4); } ok(1); 1; verilator-4.038/test_regress/t/t_protect_ids.pl0000775000177100017500000000335513702133370021677 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); # Use --debug-protect to assist debug # This test makes randomly named .cpp/.h files, which tend to collect, so remove them first foreach my $filename (glob ("$Self->{obj_dir}/*_PS*.cpp" ." $Self->{obj_dir}/*_PS*.h" ." $Self->{obj_dir}/*.d" )) { print "rm $filename\n" if $Self->{verbose}; unlink $filename; } compile( verilator_flags2 => ["--protect-ids", "--protect-key SECRET_KEY", "--trace", "--coverage", "-Wno-INSECURE", "t/t_protect_ids_c.cpp"], ); execute( check_finished => 1, ); # 'to="PS"' indicates means we probably mis-protected something already protected # Use --debug-protect to assist debugging these file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}__idmap.xml", qr/to="PS/); if ($Self->{vlt_all}) { # Check for secret in any outputs my $any; foreach my $filename (glob $Self->{obj_dir}."/*.[ch]*") { if ($filename =~ /secret/i) { $Self->error("Secret found in a filename: ".$filename); } file_grep_not($filename, qr/secret/i); $any = 1; } $any or $Self->error("No outputs found"); } ok(1); 1; verilator-4.038/test_regress/t/t_clk_latch.pl0000775000177100017500000000114713702133367021307 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); my $fail = $Self->{vlt_all}; compile( ); execute( check_finished => !$fail, fails => $fail, ); ok(1); 1; verilator-4.038/test_regress/t/t_timescale_lint_bad.out0000664000177100017500000000043313702133370023345 0ustar wsnyderwsnyder%Error-TIMESCALEMOD: t/t_timescale_lint_bad.v:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2) t/t_timescale_lint_bad.v:12:8: ... Location of module with timescale 12 | module t; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_format_wide_decimal.out0000664000177100017500000000166713702133370023533 0ustar wsnyderwsnyder179769313486231590772930519078902473361797697894230657273430081157732675805500963132708477322407536021120113879871393357658789768814416622492847430639474124377767893424865485276302219601246094119453082952085005768838150682342462881473913110540827237163350510684586298239947245938479716304835356329624224137215 89884656743115795386465259539451236680898848947115328636715040578866337902750481566354238661203768010560056939935696678829394884407208311246423715319737062188883946712432742638151109800623047059726541476042502884419075341171231440736956555270413618581675255342293149119973622969239858152417678164812112068607 44942328371557897693232629769725618340449424473557664318357520289433168951375240783177119330601884005280028469967848339414697442203604155623211857659868531094441973356216371319075554900311523529863270738021251442209537670585615720368478277635206809290837627671146574559986811484619929076208839082406056034303 *-* All Finished *-* verilator-4.038/test_regress/t/t_func_crc.v0000664000177100017500000002143513702133370020770 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [63:0] d; reg [31:0] c; wire [31:0] q = crc (d, c); reg [31:0] q_r; integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; q_r <= q; c <= q; d <= {d[62:0], ^d[63:48]}; //$write("%d crc(%x,%x)=%x\n", cyc, d, c, q); if (cyc==1) begin // Assign inputs randomly q_r <= 32'h12345678; c <= 32'h12345678; d <= 64'hffffffff_ffffffff; end if (cyc==2) begin d <= 64'hffffffff_ffffffff; end if (cyc==3) begin d <= 64'hffffffff_ffffffff; end if (cyc==4) begin d <= 64'h50183721_81a04b1a; end if (cyc==5) begin end if (cyc==9) begin if (q !== 32'h38295e96) $stop; $write("*-* All Finished *-*\n"); $finish; end end end function [31:0] crc; input [63:0] di; input [31:0] ci; reg [63:0] drev; begin drev = reverse(di); crc = newcrc(drev, ci); end endfunction function [63:0] reverse; input [63:0] di; integer i; begin reverse = 64'b0; for (i=0; i<64; i=i+1) reverse[i] = di[63-i]; end endfunction function [31:0] newcrc; input [63:0] D; input [31:0] C; reg [31:0] N; reg [31:0] DT; begin N = 32'b0; // Note this isn't a real CRC code; it's been munged for privacy N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0] ^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1]; N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0] ^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0]; N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11] ^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7]; N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0] ^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1]; N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0] ^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2]; N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1] ^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1]; N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1] ^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0]; N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0] ^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4]; N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2] ^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6]; N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7] ^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1]; N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1] ^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2]; N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1] ^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1]; N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2] ^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6]; N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11] ^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9]; N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0] ^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1]; N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2] ^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5]; N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1] ^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6]; N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0] ^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0]; N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7] ^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0]; N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2] ^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0]; N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1] ^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4]; N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1] ^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2]; N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3] ^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5]; N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3] ^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1]; N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0] ^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0]; N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2] ^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6]; N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0] ^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1]; N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2] ^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3]; N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0] ^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0]; N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0] ^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0]; N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0] ^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0]; N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0] ^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2]; newcrc = N; end endfunction endmodule verilator-4.038/test_regress/t/t_flag_woff_bad.pl0000775000177100017500000000117113702133370022112 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wno-NOSUCHERRORASTHIS"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_star.v0000664000177100017500000000143313702133370022173 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; counter_io c_data(); counter_ansi c1 (.clk, .*); counter_ansi c2 (.clk, .c_data); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (c_data.value != 12345) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule interface counter_io; integer value; endinterface module counter_ansi ( input clk, counter_io c_data ); always_ff @ (posedge clk) begin c_data.value <= 12345; end endmodule : counter_ansi verilator-4.038/test_regress/t/t_sys_writemem.gold2.mem0000664000177100017500000000003013631173020023235 0ustar wsnyderwsnyder10 11 12 13 14 15 16 17 verilator-4.038/test_regress/t/t_gen_var_bad.out0000664000177100017500000000031513702133370021771 0ustar wsnyderwsnyder%Error: t/t_gen_var_bad.v:10:7: Non-genvar used in generate for: 'i' : ... In instance t 10 | for (i=0; i<3; i=i+1) begin | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_restore_prag_bad.v0000664000177100017500000000044313702133370023532 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); // No matching save // verilator lint_restore endmodule verilator-4.038/test_regress/t/t_pp_underline_bad.v0000664000177100017500000000046313702133370022476 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator_no_inline_module initial $stop; // Should have failed endmodule verilator-4.038/test_regress/t/t_multitop1s.v0000664000177100017500000000052313702133370021322 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_multitop1s; initial $display("In '%m'"); endmodule module in_subfile; initial $display("In '%m'"); endmodule verilator-4.038/test_regress/t/t_time_vpi_1us1ns.pl0000775000177100017500000000150713702133370022403 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator_st => 1); top_filename("t/t_time_vpi.v"); $Self->{main_time_multiplier} = 1e-6 / 1e-9; compile( v_flags2 => ['+define+time_scale_units=1us +define+time_scale_prec=1ns', 't/t_time_vpi_c.cpp'], verilator_flags2 => ['--vpi'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_comments.pl0000775000177100017500000000154313702133370022734 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_preproc.v"); my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; compile( verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --pp-comments'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, stdout_filename => $stdout_filename, ); files_identical($stdout_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_interface_typo_bad.pl0000775000177100017500000000133413702133370023174 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2005 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. # However we no longer gate optimize this expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_extend.pl0000775000177100017500000000106013702133370020636 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_input_type__Dpi.out0000664000177100017500000003411313702133370024365 0ustar wsnyderwsnyder// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS // DPI export at t/t_dpi_arg_input_type.v:537:18 extern void e_array_2_state_1(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:572:18 extern void e_array_2_state_128(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:544:18 extern void e_array_2_state_32(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:551:18 extern void e_array_2_state_33(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:558:18 extern void e_array_2_state_64(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:565:18 extern void e_array_2_state_65(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:666:18 extern void e_array_4_state_1(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:701:18 extern void e_array_4_state_128(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:673:18 extern void e_array_4_state_32(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:680:18 extern void e_array_4_state_33(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:687:18 extern void e_array_4_state_64(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:694:18 extern void e_array_4_state_65(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:407:18 extern void e_bit(svBit i); // DPI export at t/t_dpi_arg_input_type.v:522:18 extern void e_bit_t(svBit i); // DPI export at t/t_dpi_arg_input_type.v:307:18 extern void e_byte(char i); // DPI export at t/t_dpi_arg_input_type.v:422:18 extern void e_byte_t(char i); // DPI export at t/t_dpi_arg_input_type.v:313:18 extern void e_byte_unsigned(unsigned char i); // DPI export at t/t_dpi_arg_input_type.v:428:18 extern void e_byte_unsigned_t(unsigned char i); // DPI export at t/t_dpi_arg_input_type.v:385:18 extern void e_chandle(void* i); // DPI export at t/t_dpi_arg_input_type.v:500:18 extern void e_chandle_t(void* i); // DPI export at t/t_dpi_arg_input_type.v:331:18 extern void e_int(int i); // DPI export at t/t_dpi_arg_input_type.v:446:18 extern void e_int_t(int i); // DPI export at t/t_dpi_arg_input_type.v:337:18 extern void e_int_unsigned(unsigned int i); // DPI export at t/t_dpi_arg_input_type.v:452:18 extern void e_int_unsigned_t(unsigned int i); // DPI export at t/t_dpi_arg_input_type.v:364:18 extern void e_integer(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:479:18 extern void e_integer_t(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:414:18 extern void e_logic(svLogic i); // DPI export at t/t_dpi_arg_input_type.v:529:18 extern void e_logic_t(svLogic i); // DPI export at t/t_dpi_arg_input_type.v:343:18 extern void e_longint(long long i); // DPI export at t/t_dpi_arg_input_type.v:458:18 extern void e_longint_t(long long i); // DPI export at t/t_dpi_arg_input_type.v:349:18 extern void e_longint_unsigned(unsigned long long i); // DPI export at t/t_dpi_arg_input_type.v:464:18 extern void e_longint_unsigned_t(unsigned long long i); // DPI export at t/t_dpi_arg_input_type.v:371:18 extern void e_real(double i); // DPI export at t/t_dpi_arg_input_type.v:486:18 extern void e_real_t(double i); // DPI export at t/t_dpi_arg_input_type.v:319:18 extern void e_shortint(short i); // DPI export at t/t_dpi_arg_input_type.v:434:18 extern void e_shortint_t(short i); // DPI export at t/t_dpi_arg_input_type.v:325:18 extern void e_shortint_unsigned(unsigned short i); // DPI export at t/t_dpi_arg_input_type.v:440:18 extern void e_shortint_unsigned_t(unsigned short i); // DPI export at t/t_dpi_arg_input_type.v:396:18 extern void e_string(const char* i); // DPI export at t/t_dpi_arg_input_type.v:511:18 extern void e_string_t(const char* i); // DPI export at t/t_dpi_arg_input_type.v:580:18 extern void e_struct_2_state_1(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:615:18 extern void e_struct_2_state_128(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:587:18 extern void e_struct_2_state_32(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:594:18 extern void e_struct_2_state_33(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:601:18 extern void e_struct_2_state_64(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:608:18 extern void e_struct_2_state_65(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:709:18 extern void e_struct_4_state_1(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:744:18 extern void e_struct_4_state_128(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:716:18 extern void e_struct_4_state_32(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:723:18 extern void e_struct_4_state_33(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:730:18 extern void e_struct_4_state_64(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:737:18 extern void e_struct_4_state_65(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:356:18 extern void e_time(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:471:18 extern void e_time_t(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:623:18 extern void e_union_2_state_1(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:658:18 extern void e_union_2_state_128(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:630:18 extern void e_union_2_state_32(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:637:18 extern void e_union_2_state_33(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:644:18 extern void e_union_2_state_64(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:651:18 extern void e_union_2_state_65(const svBitVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:752:18 extern void e_union_4_state_1(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:787:18 extern void e_union_4_state_128(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:759:18 extern void e_union_4_state_32(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:766:18 extern void e_union_4_state_33(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:773:18 extern void e_union_4_state_64(const svLogicVecVal* i); // DPI export at t/t_dpi_arg_input_type.v:780:18 extern void e_union_4_state_65(const svLogicVecVal* i); // DPI IMPORTS // DPI import at t/t_dpi_arg_input_type.v:797:41 extern void check_exports(); // DPI import at t/t_dpi_arg_input_type.v:154:33 extern void i_array_2_state_1(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:159:33 extern void i_array_2_state_128(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:155:33 extern void i_array_2_state_32(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:156:33 extern void i_array_2_state_33(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:157:33 extern void i_array_2_state_64(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:158:33 extern void i_array_2_state_65(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:178:33 extern void i_array_4_state_1(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:183:33 extern void i_array_4_state_128(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:179:33 extern void i_array_4_state_32(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:180:33 extern void i_array_4_state_33(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:181:33 extern void i_array_4_state_64(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:182:33 extern void i_array_4_state_65(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:126:33 extern void i_bit(svBit i); // DPI import at t/t_dpi_arg_input_type.v:150:33 extern void i_bit_t(svBit i); // DPI import at t/t_dpi_arg_input_type.v:106:33 extern void i_byte(char i); // DPI import at t/t_dpi_arg_input_type.v:130:33 extern void i_byte_t(char i); // DPI import at t/t_dpi_arg_input_type.v:107:33 extern void i_byte_unsigned(unsigned char i); // DPI import at t/t_dpi_arg_input_type.v:131:33 extern void i_byte_unsigned_t(unsigned char i); // DPI import at t/t_dpi_arg_input_type.v:124:33 extern void i_chandle(void* i); // DPI import at t/t_dpi_arg_input_type.v:148:33 extern void i_chandle_t(void* i); // DPI import at t/t_dpi_arg_input_type.v:110:33 extern void i_int(int i); // DPI import at t/t_dpi_arg_input_type.v:134:33 extern void i_int_t(int i); // DPI import at t/t_dpi_arg_input_type.v:111:33 extern void i_int_unsigned(unsigned int i); // DPI import at t/t_dpi_arg_input_type.v:135:33 extern void i_int_unsigned_t(unsigned int i); // DPI import at t/t_dpi_arg_input_type.v:118:33 extern void i_integer(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:142:33 extern void i_integer_t(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:127:33 extern void i_logic(svLogic i); // DPI import at t/t_dpi_arg_input_type.v:151:33 extern void i_logic_t(svLogic i); // DPI import at t/t_dpi_arg_input_type.v:112:33 extern void i_longint(long long i); // DPI import at t/t_dpi_arg_input_type.v:136:33 extern void i_longint_t(long long i); // DPI import at t/t_dpi_arg_input_type.v:113:33 extern void i_longint_unsigned(unsigned long long i); // DPI import at t/t_dpi_arg_input_type.v:137:33 extern void i_longint_unsigned_t(unsigned long long i); // DPI import at t/t_dpi_arg_input_type.v:120:33 extern void i_real(double i); // DPI import at t/t_dpi_arg_input_type.v:144:33 extern void i_real_t(double i); // DPI import at t/t_dpi_arg_input_type.v:108:33 extern void i_shortint(short i); // DPI import at t/t_dpi_arg_input_type.v:132:33 extern void i_shortint_t(short i); // DPI import at t/t_dpi_arg_input_type.v:109:33 extern void i_shortint_unsigned(unsigned short i); // DPI import at t/t_dpi_arg_input_type.v:133:33 extern void i_shortint_unsigned_t(unsigned short i); // DPI import at t/t_dpi_arg_input_type.v:125:33 extern void i_string(const char* i); // DPI import at t/t_dpi_arg_input_type.v:149:33 extern void i_string_t(const char* i); // DPI import at t/t_dpi_arg_input_type.v:162:33 extern void i_struct_2_state_1(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:167:33 extern void i_struct_2_state_128(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:163:33 extern void i_struct_2_state_32(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:164:33 extern void i_struct_2_state_33(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:165:33 extern void i_struct_2_state_64(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:166:33 extern void i_struct_2_state_65(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:186:33 extern void i_struct_4_state_1(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:191:33 extern void i_struct_4_state_128(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:187:33 extern void i_struct_4_state_32(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:188:33 extern void i_struct_4_state_33(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:189:33 extern void i_struct_4_state_64(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:190:33 extern void i_struct_4_state_65(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:115:33 extern void i_time(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:139:33 extern void i_time_t(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:170:33 extern void i_union_2_state_1(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:175:33 extern void i_union_2_state_128(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:171:33 extern void i_union_2_state_32(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:172:33 extern void i_union_2_state_33(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:173:33 extern void i_union_2_state_64(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:174:33 extern void i_union_2_state_65(const svBitVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:194:33 extern void i_union_4_state_1(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:199:33 extern void i_union_4_state_128(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:195:33 extern void i_union_4_state_32(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:196:33 extern void i_union_4_state_33(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:197:33 extern void i_union_4_state_64(const svLogicVecVal* i); // DPI import at t/t_dpi_arg_input_type.v:198:33 extern void i_union_4_state_65(const svLogicVecVal* i); #ifdef __cplusplus } #endif verilator-4.038/test_regress/t/t_struct_packed_write_read.v0000664000177100017500000001244013702133370024242 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam NO = 10; // number of access events // packed structures struct packed { logic e0; logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; } struct_bg; // big endian structure /* verilator lint_off LITENDIAN */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; } struct_lt; // little endian structure /* verilator lint_on LITENDIAN */ localparam WS = 15; // $bits(struct_bg) integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin $write("*-* All Finished *-*\n"); $finish; end // big endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) struct_bg <= '0; else if (cnt[30:2]==1) struct_bg <= '0; else if (cnt[30:2]==2) struct_bg <= '0; else if (cnt[30:2]==3) struct_bg <= '0; else if (cnt[30:2]==4) struct_bg <= '0; else if (cnt[30:2]==5) struct_bg <= '0; end else if (cnt[1:0]==2'd1) begin // write value to structure if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) struct_bg <= '1; else if (cnt[30:2]==2) struct_bg.e0 <= '1; else if (cnt[30:2]==3) struct_bg.e1 <= '1; else if (cnt[30:2]==4) struct_bg.e2 <= '1; else if (cnt[30:2]==5) struct_bg.e3 <= '1; end else if (cnt[1:0]==2'd2) begin // check structure value if (cnt[30:2]==0) begin if (struct_bg !== 15'b000000000000000) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==1) begin if (struct_bg !== 15'b111111111111111) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==2) begin if (struct_bg !== 15'b100000000000000) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==3) begin if (struct_bg !== 15'b011000000000000) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==4) begin if (struct_bg !== 15'b000111100000000) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==5) begin if (struct_bg !== 15'b000000011111111) begin $display("%b", struct_bg); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from structure (not a very good test for now) if (cnt[30:2]==0) begin if (struct_bg !== {WS{1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (struct_bg !== {WS{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (struct_bg.e0 !== { 1{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (struct_bg.e1 !== { 2{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (struct_bg.e2 !== { 4{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (struct_bg.e3 !== { 8{1'b1}}) $stop(); end end // little endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) struct_lt <= '0; else if (cnt[30:2]==1) struct_lt <= '0; else if (cnt[30:2]==2) struct_lt <= '0; else if (cnt[30:2]==3) struct_lt <= '0; else if (cnt[30:2]==4) struct_lt <= '0; else if (cnt[30:2]==5) struct_lt <= '0; end else if (cnt[1:0]==2'd1) begin // write value to structure if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) struct_lt <= '1; else if (cnt[30:2]==2) struct_lt.e0 <= '1; else if (cnt[30:2]==3) struct_lt.e1 <= '1; else if (cnt[30:2]==4) struct_lt.e2 <= '1; else if (cnt[30:2]==5) struct_lt.e3 <= '1; end else if (cnt[1:0]==2'd2) begin // check structure value if (cnt[30:2]==0) begin if (struct_lt !== 15'b000000000000000) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==1) begin if (struct_lt !== 15'b111111111111111) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==2) begin if (struct_lt !== 15'b100000000000000) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==3) begin if (struct_lt !== 15'b011000000000000) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==4) begin if (struct_lt !== 15'b000111100000000) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==5) begin if (struct_lt !== 15'b000000011111111) begin $display("%b", struct_lt); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from structure (not a very good test for now) if (cnt[30:2]==0) begin if (struct_lt !== {WS{1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (struct_lt !== {WS{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (struct_lt.e0 !== { 1{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (struct_lt.e1 !== { 2{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (struct_lt.e2 !== { 4{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (struct_lt.e3 !== { 8{1'b1}}) $stop(); end end endmodule verilator-4.038/test_regress/t/t_var_const.v0000664000177100017500000000114313702133370021176 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; const logic [2:0] five = 3'd5; const logic unsigned [31:0] var_const = 22; logic [7:0] res_const; assign res_const = var_const[7:0]; // bug693 always @ (posedge clk) begin if (five !== 3'd5) $stop; if (res_const !== 8'd22) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_dpi_2exp_bad.v0000664000177100017500000000105413702133370021521 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; export "DPI-C" task dpix_twice; export "DPI-C" dpix_t_int_renamed = task dpix_twice; task dpix_twice(input int i, output int o); o = ~i; endtask initial begin $stop; end endmodule verilator-4.038/test_regress/t/t_flag_make_cmake.v0000664000177100017500000000057513702133370022256 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_init.v0000664000177100017500000000132713702133370021017 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter [31:0] p2=2, p3=3; integer i2=2, i3=3; reg [31:0] r2=2, r3=3; wire [31:0] w2=2, w3=3; always @ (posedge clk) begin if (p2 !== 2) $stop; if (p3 !== 3) $stop; if (i2 !== 2) $stop; if (i3 !== 3) $stop; if (r2 !== 2) $stop; if (r3 !== 3) $stop; if (w2 !== 2) $stop; if (w3 !== 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_down_inld.pl0000775000177100017500000000123413702133370023347 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_D'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_method.v0000664000177100017500000000150113702133367021651 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Cls; int imembera; function int get_methoda; return imembera; endfunction task set_methoda(input int val); imembera = val; endtask function void setv_methoda(input int val); imembera = val; endfunction endclass : Cls module t (/*AUTOARG*/); initial begin Cls c; if (c != null) $stop; c = new; c.imembera = 10; if (c.get_methoda() != 10) $stop; c.set_methoda(20); if (c.get_methoda() != 20) $stop; c.setv_methoda(30); if (c.get_methoda() != 30) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_dpi_shortcircuit_c.cpp0000664000177100017500000000344613702133370023405 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2011-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # if defined(T_DPI_SHORTCIRCUIT) # include "Vt_dpi_shortcircuit__Dpi.h" # elif defined(T_DPI_SHORTCIRCUIT2) # include "Vt_dpi_shortcircuit2__Dpi.h" # else # error "Unknown test" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { extern int dpii_clear(); extern int dpii_count(int idx); extern unsigned char dpii_inc0(int idx); extern unsigned char dpii_inc1(int idx); extern unsigned char dpii_incx(int idx, unsigned char value); } #endif //====================================================================== #define COUNTERS 16 static int global_count[COUNTERS]; int dpii_clear() { for (int i = 0; i < COUNTERS; ++i) global_count[i] = 0; return 0; } int dpii_count(int idx) { return (idx >= 0 && idx < COUNTERS) ? global_count[idx] : -1; } unsigned char dpii_incx(int idx, unsigned char value) { if (idx >= 0 && idx < COUNTERS) global_count[idx]++; return value; } unsigned char dpii_inc0(int idx) { return dpii_incx(idx, 0); } unsigned char dpii_inc1(int idx) { return dpii_incx(idx, 1); } verilator-4.038/test_regress/t/t_struct_packed_write_read.pl0000775000177100017500000000105313702133370024411 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_x_assign_1.pl0000775000177100017500000000131213702133370021402 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_x_assign.v"); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--x-assign 1 --exe $Self->{t_dir}/t_x_assign.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_self_return.pl0000775000177100017500000000105313702133370022532 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_darray.pl0000775000177100017500000000105313702133370021670 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_numwidth.v0000664000177100017500000000046213702133370022070 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 logic [65535:0] a = 65536'd1; logic [65536:0] b = 65537'd1; logic [131071:0] c = 131072'd1; verilator-4.038/test_regress/t/t_mod_nomod.v0000664000177100017500000000041713702133370021156 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug 1381 logic root_var; // No module statements.... verilator-4.038/test_regress/t/t_preproc_cmtend_bad.pl0000775000177100017500000000107413702133370023166 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_port2_bad.pl0000775000177100017500000000107413702133370022100 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_no_parentheses.pl0000775000177100017500000000105313702133370023546 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_default_bad.out0000664000177100017500000000024313702133367022775 0ustar wsnyderwsnyder%Error: t/t_case_default_bad.v:16:9: Multiple default statements in case statement. 16 | default: $stop; | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_inst_long_bad.out0000664000177100017500000000145113702133370022346 0ustar wsnyderwsnyder%Error: obj_vlt/t_inst_long_bad/t_inst_long.v:4:3: Cannot find file containing module: 'long_long_long_long_long_long_lo__Vhsh1JZCXQVBM1QiASYlLmgTuAXYyUr7VAbJYwVHfiAD' 4 | long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_ inst (); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... Unsupported: Name is longer than 127 characters; automatic file lookup not supported. ... Suggest putting filename with this module/package onto command line instead. %Error: Exiting due to verilator-4.038/test_regress/t/t_flag_make_cmake_sc.pl0000775000177100017500000000126713702133370023113 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test tests CMake support for SystemC scenarios(simulator => 1); compile( verilator_make_gmake => 0, verilator_make_cmake => 1, verilator_flags2 => ["-sc"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_init_concat.v0000664000177100017500000000350513702133370021476 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] wr_data; reg wr_en; wire [31:0] rd_data; wire [1:0] rd_guards; wire [1:0] rd_guardsok; regfile regfile (/*AUTOINST*/ // Outputs .rd_data (rd_data[31:0]), .rd_guards (rd_guards[1:0]), .rd_guardsok (rd_guardsok[1:0]), // Inputs .wr_data (wr_data[31:0]), .wr_en (wr_en), .clk (clk)); initial wr_en = 0; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin if (!rd_guards[0]) $stop; if (!rd_guardsok[0]) $stop; wr_en <= 1'b1; wr_data <= 32'hfeedf; end if (cyc==2) begin wr_en <= 0; end if (cyc==3) begin wr_en <= 0; if (rd_data != 32'hfeedf) $stop; if (rd_guards != 2'b11) $stop; if (rd_guardsok != 2'b11) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module regfile ( input [31:0] wr_data, input wr_en, output reg [31:0] rd_data, output [1:0] rd_guards /*verilator public*/, output [1:0] rd_guardsok /*verilator public*/, input clk ); always @(posedge clk) begin if (wr_en) begin rd_data <= wr_data; end end // this initial statement will induce correct initialize behavior // initial rd_guards= { 2'b11 }; assign rd_guards= { rd_data[0], 1'b1 }; assign rd_guardsok[0] = 1'b1; assign rd_guardsok[1] = rd_data[0]; endmodule // regfile verilator-4.038/test_regress/t/t_lint_importstar_bad.v0000664000177100017500000000044113702133370023240 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package defs; int sig; endpackage import defs::*; module t; endmodule verilator-4.038/test_regress/t/t_case_write1_tasks.v0000664000177100017500000030202413702133367022623 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "verilated.v" module t_case_write1_tasks (); // verilator lint_off WIDTH // verilator lint_off CASEINCOMPLETE parameter STRLEN = 78; task ozonerab; input [6:0] rab; inout [STRLEN*8:1] foobar; // verilator no_inline_task begin case (rab[6:0]) 7'h00 : foobar = {foobar, " 0"}; 7'h01 : foobar = {foobar, " 1"}; 7'h02 : foobar = {foobar, " 2"}; 7'h03 : foobar = {foobar, " 3"}; 7'h04 : foobar = {foobar, " 4"}; 7'h05 : foobar = {foobar, " 5"}; 7'h06 : foobar = {foobar, " 6"}; 7'h07 : foobar = {foobar, " 7"}; 7'h08 : foobar = {foobar, " 8"}; 7'h09 : foobar = {foobar, " 9"}; 7'h0a : foobar = {foobar, " 10"}; 7'h0b : foobar = {foobar, " 11"}; 7'h0c : foobar = {foobar, " 12"}; 7'h0d : foobar = {foobar, " 13"}; 7'h0e : foobar = {foobar, " 14"}; 7'h0f : foobar = {foobar, " 15"}; 7'h10 : foobar = {foobar, " 16"}; 7'h11 : foobar = {foobar, " 17"}; 7'h12 : foobar = {foobar, " 18"}; 7'h13 : foobar = {foobar, " 19"}; 7'h14 : foobar = {foobar, " 20"}; 7'h15 : foobar = {foobar, " 21"}; 7'h16 : foobar = {foobar, " 22"}; 7'h17 : foobar = {foobar, " 23"}; 7'h18 : foobar = {foobar, " 24"}; 7'h19 : foobar = {foobar, " 25"}; 7'h1a : foobar = {foobar, " 26"}; 7'h1b : foobar = {foobar, " 27"}; 7'h1c : foobar = {foobar, " 28"}; 7'h1d : foobar = {foobar, " 29"}; 7'h1e : foobar = {foobar, " 30"}; 7'h1f : foobar = {foobar, " 31"}; 7'h20 : foobar = {foobar, " 32"}; 7'h21 : foobar = {foobar, " 33"}; 7'h22 : foobar = {foobar, " 34"}; 7'h23 : foobar = {foobar, " 35"}; 7'h24 : foobar = {foobar, " 36"}; 7'h25 : foobar = {foobar, " 37"}; 7'h26 : foobar = {foobar, " 38"}; 7'h27 : foobar = {foobar, " 39"}; 7'h28 : foobar = {foobar, " 40"}; 7'h29 : foobar = {foobar, " 41"}; 7'h2a : foobar = {foobar, " 42"}; 7'h2b : foobar = {foobar, " 43"}; 7'h2c : foobar = {foobar, " 44"}; 7'h2d : foobar = {foobar, " 45"}; 7'h2e : foobar = {foobar, " 46"}; 7'h2f : foobar = {foobar, " 47"}; 7'h30 : foobar = {foobar, " 48"}; 7'h31 : foobar = {foobar, " 49"}; 7'h32 : foobar = {foobar, " 50"}; 7'h33 : foobar = {foobar, " 51"}; 7'h34 : foobar = {foobar, " 52"}; 7'h35 : foobar = {foobar, " 53"}; 7'h36 : foobar = {foobar, " 54"}; 7'h37 : foobar = {foobar, " 55"}; 7'h38 : foobar = {foobar, " 56"}; 7'h39 : foobar = {foobar, " 57"}; 7'h3a : foobar = {foobar, " 58"}; 7'h3b : foobar = {foobar, " 59"}; 7'h3c : foobar = {foobar, " 60"}; 7'h3d : foobar = {foobar, " 61"}; 7'h3e : foobar = {foobar, " 62"}; 7'h3f : foobar = {foobar, " 63"}; 7'h40 : foobar = {foobar, " 64"}; 7'h41 : foobar = {foobar, " 65"}; 7'h42 : foobar = {foobar, " 66"}; 7'h43 : foobar = {foobar, " 67"}; 7'h44 : foobar = {foobar, " 68"}; 7'h45 : foobar = {foobar, " 69"}; 7'h46 : foobar = {foobar, " 70"}; 7'h47 : foobar = {foobar, " 71"}; 7'h48 : foobar = {foobar, " 72"}; 7'h49 : foobar = {foobar, " 73"}; 7'h4a : foobar = {foobar, " 74"}; 7'h4b : foobar = {foobar, " 75"}; 7'h4c : foobar = {foobar, " 76"}; 7'h4d : foobar = {foobar, " 77"}; 7'h4e : foobar = {foobar, " 78"}; 7'h4f : foobar = {foobar, " 79"}; 7'h50 : foobar = {foobar, " 80"}; 7'h51 : foobar = {foobar, " 81"}; 7'h52 : foobar = {foobar, " 82"}; 7'h53 : foobar = {foobar, " 83"}; 7'h54 : foobar = {foobar, " 84"}; 7'h55 : foobar = {foobar, " 85"}; 7'h56 : foobar = {foobar, " 86"}; 7'h57 : foobar = {foobar, " 87"}; 7'h58 : foobar = {foobar, " 88"}; 7'h59 : foobar = {foobar, " 89"}; 7'h5a : foobar = {foobar, " 90"}; 7'h5b : foobar = {foobar, " 91"}; 7'h5c : foobar = {foobar, " 92"}; 7'h5d : foobar = {foobar, " 93"}; 7'h5e : foobar = {foobar, " 94"}; 7'h5f : foobar = {foobar, " 95"}; 7'h60 : foobar = {foobar, " 96"}; 7'h61 : foobar = {foobar, " 97"}; 7'h62 : foobar = {foobar, " 98"}; 7'h63 : foobar = {foobar, " 99"}; 7'h64 : foobar = {foobar, " 100"}; 7'h65 : foobar = {foobar, " 101"}; 7'h66 : foobar = {foobar, " 102"}; 7'h67 : foobar = {foobar, " 103"}; 7'h68 : foobar = {foobar, " 104"}; 7'h69 : foobar = {foobar, " 105"}; 7'h6a : foobar = {foobar, " 106"}; 7'h6b : foobar = {foobar, " 107"}; 7'h6c : foobar = {foobar, " 108"}; 7'h6d : foobar = {foobar, " 109"}; 7'h6e : foobar = {foobar, " 110"}; 7'h6f : foobar = {foobar, " 111"}; 7'h70 : foobar = {foobar, " 112"}; 7'h71 : foobar = {foobar, " 113"}; 7'h72 : foobar = {foobar, " 114"}; 7'h73 : foobar = {foobar, " 115"}; 7'h74 : foobar = {foobar, " 116"}; 7'h75 : foobar = {foobar, " 117"}; 7'h76 : foobar = {foobar, " 118"}; 7'h77 : foobar = {foobar, " 119"}; 7'h78 : foobar = {foobar, " 120"}; 7'h79 : foobar = {foobar, " 121"}; 7'h7a : foobar = {foobar, " 122"}; 7'h7b : foobar = {foobar, " 123"}; 7'h7c : foobar = {foobar, " 124"}; 7'h7d : foobar = {foobar, " 125"}; 7'h7e : foobar = {foobar, " 126"}; 7'h7f : foobar = {foobar, " 127"}; default:foobar = {foobar, " 128"}; endcase end endtask task ozonerb; input [5:0] rb; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (rb[5:0]) 6'h10, 6'h17, 6'h1e, 6'h1f: foobar = {foobar, " 129"}; default: ozonerab({1'b1, rb}, foobar); endcase end endtask task ozonef3f4_iext; input [1:0] foo; input [15:0] im16; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo) 2'h0 : begin skyway({4{im16[15]}}, foobar); skyway({4{im16[15]}}, foobar); skyway(im16[15:12], foobar); skyway(im16[11: 8], foobar); skyway(im16[ 7: 4], foobar); skyway(im16[ 3:0], foobar); foobar = {foobar, " 130"}; end 2'h1 : begin foobar = {foobar, " 131"}; skyway(im16[15:12], foobar); skyway(im16[11: 8], foobar); skyway(im16[ 7: 4], foobar); skyway(im16[ 3:0], foobar); end 2'h2 : begin skyway({4{im16[15]}}, foobar); skyway({4{im16[15]}}, foobar); skyway(im16[15:12], foobar); skyway(im16[11: 8], foobar); skyway(im16[ 7: 4], foobar); skyway(im16[ 3:0], foobar); foobar = {foobar, " 132"}; end 2'h3 : begin foobar = {foobar, " 133"}; skyway(im16[15:12], foobar); skyway(im16[11: 8], foobar); skyway(im16[ 7: 4], foobar); skyway(im16[ 3:0], foobar); end endcase end endtask task skyway; input [ 3:0] hex; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (hex) 4'h0 : foobar = {foobar, " 134"}; 4'h1 : foobar = {foobar, " 135"}; 4'h2 : foobar = {foobar, " 136"}; 4'h3 : foobar = {foobar, " 137"}; 4'h4 : foobar = {foobar, " 138"}; 4'h5 : foobar = {foobar, " 139"}; 4'h6 : foobar = {foobar, " 140"}; 4'h7 : foobar = {foobar, " 141"}; 4'h8 : foobar = {foobar, " 142"}; 4'h9 : foobar = {foobar, " 143"}; 4'ha : foobar = {foobar, " 144"}; 4'hb : foobar = {foobar, " 145"}; 4'hc : foobar = {foobar, " 146"}; 4'hd : foobar = {foobar, " 147"}; 4'he : foobar = {foobar, " 148"}; 4'hf : foobar = {foobar, " 149"}; endcase end endtask task ozonesr; input [ 15:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[11: 9]) 3'h0 : foobar = {foobar, " 158"}; 3'h1 : foobar = {foobar, " 159"}; 3'h2 : foobar = {foobar, " 160"}; 3'h3 : foobar = {foobar, " 161"}; 3'h4 : foobar = {foobar, " 162"}; 3'h5 : foobar = {foobar, " 163"}; 3'h6 : foobar = {foobar, " 164"}; 3'h7 : foobar = {foobar, " 165"}; endcase end endtask task ozonejk; input k; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin if (k) foobar = {foobar, " 166"}; else foobar = {foobar, " 167"}; end endtask task ozoneae; input [ 2:0] ae; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (ae) 3'b000 : foobar = {foobar, " 168"}; 3'b001 : foobar = {foobar, " 169"}; 3'b010 : foobar = {foobar, " 170"}; 3'b011 : foobar = {foobar, " 171"}; 3'b100 : foobar = {foobar, " 172"}; 3'b101 : foobar = {foobar, " 173"}; 3'b110 : foobar = {foobar, " 174"}; 3'b111 : foobar = {foobar, " 175"}; endcase end endtask task ozoneaee; input [ 2:0] aee; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (aee) 3'b001, 3'b011, 3'b101, 3'b111 : foobar = {foobar, " 176"}; 3'b000 : foobar = {foobar, " 177"}; 3'b010 : foobar = {foobar, " 178"}; 3'b100 : foobar = {foobar, " 179"}; 3'b110 : foobar = {foobar, " 180"}; endcase end endtask task ozoneape; input [ 2:0] ape; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (ape) 3'b001, 3'b011, 3'b101, 3'b111 : foobar = {foobar, " 181"}; 3'b000 : foobar = {foobar, " 182"}; 3'b010 : foobar = {foobar, " 183"}; 3'b100 : foobar = {foobar, " 184"}; 3'b110 : foobar = {foobar, " 185"}; endcase end endtask task ozonef1; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[24:21]) 4'h0 : if (foo[26]) foobar = {foobar, " 186"}; else foobar = {foobar, " 187"}; 4'h1 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 188"}; 2'b01 : foobar = {foobar, " 189"}; 2'b10 : foobar = {foobar, " 190"}; 2'b11 : foobar = {foobar, " 191"}; endcase 4'h2 : foobar = {foobar, " 192"}; 4'h3 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 193"}; 2'b01 : foobar = {foobar, " 194"}; 2'b10 : foobar = {foobar, " 195"}; 2'b11 : foobar = {foobar, " 196"}; endcase 4'h4 : if (foo[26]) foobar = {foobar, " 197"}; else foobar = {foobar, " 198"}; 4'h5 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 199"}; 2'b01 : foobar = {foobar, " 200"}; 2'b10 : foobar = {foobar, " 201"}; 2'b11 : foobar = {foobar, " 202"}; endcase 4'h6 : foobar = {foobar, " 203"}; 4'h7 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 204"}; 2'b01 : foobar = {foobar, " 205"}; 2'b10 : foobar = {foobar, " 206"}; 2'b11 : foobar = {foobar, " 207"}; endcase 4'h8 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 208"}; 2'b01 : foobar = {foobar, " 209"}; 2'b10 : foobar = {foobar, " 210"}; 2'b11 : foobar = {foobar, " 211"}; endcase 4'h9 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 212"}; 2'b01 : foobar = {foobar, " 213"}; 2'b10 : foobar = {foobar, " 214"}; 2'b11 : foobar = {foobar, " 215"}; endcase 4'ha : if (foo[25]) foobar = {foobar, " 216"}; else foobar = {foobar, " 217"}; 4'hb : if (foo[25]) foobar = {foobar, " 218"}; else foobar = {foobar, " 219"}; 4'hc : if (foo[26]) foobar = {foobar, " 220"}; else foobar = {foobar, " 221"}; 4'hd : case (foo[26:25]) 2'b00 : foobar = {foobar, " 222"}; 2'b01 : foobar = {foobar, " 223"}; 2'b10 : foobar = {foobar, " 224"}; 2'b11 : foobar = {foobar, " 225"}; endcase 4'he : case (foo[26:25]) 2'b00 : foobar = {foobar, " 226"}; 2'b01 : foobar = {foobar, " 227"}; 2'b10 : foobar = {foobar, " 228"}; 2'b11 : foobar = {foobar, " 229"}; endcase 4'hf : case (foo[26:25]) 2'b00 : foobar = {foobar, " 230"}; 2'b01 : foobar = {foobar, " 231"}; 2'b10 : foobar = {foobar, " 232"}; 2'b11 : foobar = {foobar, " 233"}; endcase endcase end endtask task ozonef1e; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[27:21]) 7'h00: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 234"}; foobar = {foobar, " 235"}; end 7'h01: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 236"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 237"}; foobar = {foobar, " 238"}; end 7'h02: foobar = {foobar, " 239"}; 7'h03: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 240"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 241"}; foobar = {foobar, " 242"}; end 7'h04: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 243"}; foobar = {foobar," 244"}; end 7'h05: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 245"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 246"}; end 7'h06: foobar = {foobar, " 247"}; 7'h07: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 248"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 249"}; end 7'h08: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 250"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 251"}; end 7'h09: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 252"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 253"}; end 7'h0a: begin ozoneae(foo[17:15], foobar); foobar = {foobar," 254"}; end 7'h0b: begin ozoneae(foo[17:15], foobar); foobar = {foobar," 255"}; end 7'h0c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 256"}; end 7'h0d: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 257"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 258"}; end 7'h0e: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 259"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 260"}; end 7'h0f: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 261"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 262"}; end 7'h10: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 263"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 264"}; foobar = {foobar, " 265"}; foobar = {foobar, " 266"}; end 7'h11: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 267"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 268"}; foobar = {foobar, " 269"}; foobar = {foobar, " 270"}; end 7'h12: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 271"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 272"}; foobar = {foobar, " 273"}; foobar = {foobar, " 274"}; end 7'h13: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 275"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 276"}; foobar = {foobar, " 277"}; foobar = {foobar, " 278"}; end 7'h14: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 279"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 280"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 281"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 282"}; foobar = {foobar, " 283"}; foobar = {foobar, " 284"}; end 7'h15: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 285"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 286"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 287"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 288"}; foobar = {foobar, " 289"}; foobar = {foobar, " 290"}; end 7'h16: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 291"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 292"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 293"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 294"}; foobar = {foobar, " 295"}; foobar = {foobar, " 296"}; end 7'h17: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 297"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 298"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 299"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 300"}; foobar = {foobar, " 301"}; foobar = {foobar, " 302"}; end 7'h18: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 303"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 304"}; foobar = {foobar, " 305"}; foobar = {foobar, " 306"}; end 7'h19: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 307"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 308"}; foobar = {foobar, " 309"}; foobar = {foobar, " 310"}; end 7'h1a: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 311"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 312"}; foobar = {foobar, " 313"}; foobar = {foobar, " 314"}; end 7'h1b: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 315"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 316"}; foobar = {foobar, " 317"}; foobar = {foobar, " 318"}; end 7'h1c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 319"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 320"}; foobar = {foobar, " 321"}; foobar = {foobar, " 322"}; end 7'h1d: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 323"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 324"}; foobar = {foobar, " 325"}; foobar = {foobar, " 326"}; end 7'h1e: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 327"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 328"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 329"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 330"}; foobar = {foobar, " 331"}; foobar = {foobar, " 332"}; end 7'h1f: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 333"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 334"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 335"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 336"}; foobar = {foobar, " 337"}; foobar = {foobar, " 338"}; end 7'h20: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 339"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 340"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 341"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 342"}; foobar = {foobar, " 343"}; foobar = {foobar, " 344"}; end 7'h21: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 345"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 346"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 347"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 348"}; foobar = {foobar, " 349"}; foobar = {foobar, " 350"}; end 7'h22: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 351"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 352"}; foobar = {foobar, " 353"}; foobar = {foobar, " 354"}; end 7'h23: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 355"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 356"}; foobar = {foobar, " 357"}; foobar = {foobar, " 358"}; end 7'h24: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 359"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 360"}; foobar = {foobar, " 361"}; foobar = {foobar, " 362"}; end 7'h25: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 363"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 364"}; foobar = {foobar, " 365"}; foobar = {foobar, " 366"}; end 7'h26: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 367"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 368"}; foobar = {foobar, " 369"}; foobar = {foobar, " 370"}; end 7'h27: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 371"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 372"}; foobar = {foobar, " 373"}; foobar = {foobar, " 374"}; end 7'h28: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 375"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 376"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 377"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 378"}; foobar = {foobar, " 379"}; foobar = {foobar, " 380"}; end 7'h29: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 381"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 382"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 383"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 384"}; foobar = {foobar, " 385"}; foobar = {foobar, " 386"}; end 7'h2a: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 387"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 388"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 389"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 390"}; foobar = {foobar, " 391"}; foobar = {foobar, " 392"}; end 7'h2b: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 393"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 394"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 395"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 396"}; foobar = {foobar, " 397"}; foobar = {foobar, " 398"}; end 7'h2c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 399"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 400"}; foobar = {foobar, " 401"}; foobar = {foobar, " 402"}; end 7'h2d: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 403"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 404"}; foobar = {foobar, " 405"}; foobar = {foobar, " 406"}; end 7'h2e: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 407"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 408"}; foobar = {foobar, " 409"}; foobar = {foobar, " 410"}; end 7'h2f: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 411"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 412"}; foobar = {foobar, " 413"}; foobar = {foobar, " 414"}; end 7'h30: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 415"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 416"}; foobar = {foobar, " 417"}; foobar = {foobar, " 418"}; end 7'h31: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 419"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 420"}; foobar = {foobar, " 421"}; foobar = {foobar, " 422"}; end 7'h32: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 423"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 424"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 425"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 426"}; foobar = {foobar, " 427"}; foobar = {foobar, " 428"}; end 7'h33: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 429"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 430"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 431"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 432"}; foobar = {foobar, " 433"}; foobar = {foobar, " 434"}; end 7'h34: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 435"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 436"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 437"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 438"}; foobar = {foobar, " 439"}; foobar = {foobar, " 440"}; end 7'h35: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 441"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 442"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 443"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 444"}; foobar = {foobar, " 445"}; foobar = {foobar, " 446"}; end 7'h36: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 447"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 448"}; foobar = {foobar, " 449"}; foobar = {foobar, " 450"}; end 7'h37: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 451"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 452"}; foobar = {foobar, " 453"}; foobar = {foobar, " 454"}; end 7'h38: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 455"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 456"}; foobar = {foobar, " 457"}; end 7'h39: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 458"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 459"}; foobar = {foobar, " 460"}; end 7'h3a: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 461"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 462"}; foobar = {foobar, " 463"}; end 7'h3b: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 464"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 465"}; foobar = {foobar, " 466"}; end 7'h3c: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 467"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 468"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 469"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 470"}; foobar = {foobar, " 471"}; end 7'h3d: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 472"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 473"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 474"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 475"}; foobar = {foobar, " 476"}; end 7'h3e: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 477"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 478"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 479"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 480"}; foobar = {foobar, " 481"}; end 7'h3f: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 482"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 483"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 484"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 485"}; foobar = {foobar, " 486"}; end 7'h40: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 487"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 488"}; foobar = {foobar, " 489"}; foobar = {foobar, " 490"}; end 7'h41: begin foobar = {foobar, " 491"}; foobar = {foobar, " 492"}; end 7'h42: begin foobar = {foobar, " 493"}; foobar = {foobar, " 494"}; end 7'h43: begin foobar = {foobar, " 495"}; foobar = {foobar, " 496"}; end 7'h44: begin foobar = {foobar, " 497"}; foobar = {foobar, " 498"}; end 7'h45: foobar = {foobar, " 499"}; 7'h46: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 500"}; foobar = {foobar, " 501"}; foobar = {foobar, " 502"}; end 7'h47: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 503"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 504"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 505"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 506"}; foobar = {foobar, " 507"}; foobar = {foobar, " 508"}; end 7'h48: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 509"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 510"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 511"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 512"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 513"}; end 7'h49: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 514"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 515"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 516"}; end 7'h4a: foobar = {foobar," 517"}; 7'h4b: foobar = {foobar, " 518"}; 7'h4c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 519"}; foobar = {foobar, " 520"}; foobar = {foobar, " 521"}; end 7'h4d: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 522"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 523"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 524"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 525"}; foobar = {foobar, " 526"}; foobar = {foobar, " 527"}; end 7'h4e: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 528"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 529"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 530"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 531"}; end 7'h4f: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 532"}; end 7'h50: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 533"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 534"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 535"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 536"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 537"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 538"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 539"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 540"}; end 7'h51: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 541"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 542"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 543"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 544"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 545"}; end 7'h52: foobar = {foobar, " 546"}; 7'h53: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 547"}; end 7'h54: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 548"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 549"}; end 7'h55: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 550"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 551"}; end 7'h56: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 552"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 553"}; foobar = {foobar, " 554"}; end 7'h57: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 555"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 556"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 557"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 558"}; end 7'h58: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 559"}; end 7'h59: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 560"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 561"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 562"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 563"}; end 7'h5a: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 564"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 565"}; end 7'h5b: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 566"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 567"}; end 7'h5c: begin foobar = {foobar," 568"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 569"}; foobar = {foobar," 570"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 571"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 572"}; ozoneaee(foo[17:15], foobar); foobar = {foobar, " 573"}; end 7'h5d: begin foobar = {foobar," 574"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 575"}; foobar = {foobar," 576"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 577"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 578"}; ozoneaee(foo[17:15], foobar); foobar = {foobar, " 579"}; end 7'h5e: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 580"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 581"}; end 7'h5f: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 582"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 583"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 584"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 585"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 586"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 587"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 588"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 589"}; end 7'h60: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 590"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 591"}; end 7'h61: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 592"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 593"}; end 7'h62: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 594"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 595"}; end 7'h63: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 596"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 597"}; end 7'h64: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 598"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 599"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 600"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 601"}; end 7'h65: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 602"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 603"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 604"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 605"}; end 7'h66: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 606"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 607"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 608"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 609"}; end 7'h67: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 610"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 611"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 612"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 613"}; end 7'h68: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 614"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 615"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 616"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 617"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 618"}; ozoneape(foo[17:15], foobar); end 7'h69: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 619"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 620"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 621"}; end 7'h6a: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 622"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 623"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 624"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 625"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 626"}; ozoneae(foo[17:15], foobar); end 7'h6b: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 627"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 628"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 629"}; end 7'h6c: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 630"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 631"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 632"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 633"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 634"}; ozoneae(foo[17:15], foobar); end 7'h6d: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 635"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 636"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 637"}; end 7'h6e: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 638"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 639"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 640"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 641"}; end 7'h6f: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 642"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 643"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 644"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 645"}; end 7'h70: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 646"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 647"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 648"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 649"}; end 7'h71: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 650"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 651"}; end 7'h72: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 652"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 653"}; end 7'h73: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 654"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 655"}; ozoneae(foo[17:15], foobar); end 7'h74: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 656"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 657"}; ozoneae(foo[17:15], foobar); end 7'h75: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 658"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 659"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 660"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 661"}; foobar = {foobar, " 662"}; foobar = {foobar, " 663"}; end 7'h76: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 664"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 665"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 666"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 667"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 668"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 669"}; end 7'h77: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 670"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 671"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 672"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 673"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 674"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 675"}; end 7'h78, 7'h79, 7'h7a, 7'h7b, 7'h7c, 7'h7d, 7'h7e, 7'h7f: foobar = {foobar," 676"}; endcase end endtask task ozonef2; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[24:21]) 4'h0 : case (foo[26:25]) 2'b00 : foobar = {foobar," 677"}; 2'b01 : foobar = {foobar," 678"}; 2'b10 : foobar = {foobar," 679"}; 2'b11 : foobar = {foobar," 680"}; endcase 4'h1 : case (foo[26:25]) 2'b00 : foobar = {foobar," 681"}; 2'b01 : foobar = {foobar," 682"}; 2'b10 : foobar = {foobar," 683"}; 2'b11 : foobar = {foobar," 684"}; endcase 4'h2 : case (foo[26:25]) 2'b00 : foobar = {foobar," 685"}; 2'b01 : foobar = {foobar," 686"}; 2'b10 : foobar = {foobar," 687"}; 2'b11 : foobar = {foobar," 688"}; endcase 4'h3 : case (foo[26:25]) 2'b00 : foobar = {foobar," 689"}; 2'b01 : foobar = {foobar," 690"}; 2'b10 : foobar = {foobar," 691"}; 2'b11 : foobar = {foobar," 692"}; endcase 4'h4 : case (foo[26:25]) 2'b00 : foobar = {foobar," 693"}; 2'b01 : foobar = {foobar," 694"}; 2'b10 : foobar = {foobar," 695"}; 2'b11 : foobar = {foobar," 696"}; endcase 4'h5 : case (foo[26:25]) 2'b00 : foobar = {foobar," 697"}; 2'b01 : foobar = {foobar," 698"}; 2'b10 : foobar = {foobar," 699"}; 2'b11 : foobar = {foobar," 700"}; endcase 4'h6 : case (foo[26:25]) 2'b00 : foobar = {foobar," 701"}; 2'b01 : foobar = {foobar," 702"}; 2'b10 : foobar = {foobar," 703"}; 2'b11 : foobar = {foobar," 704"}; endcase 4'h7 : case (foo[26:25]) 2'b00 : foobar = {foobar," 705"}; 2'b01 : foobar = {foobar," 706"}; 2'b10 : foobar = {foobar," 707"}; 2'b11 : foobar = {foobar," 708"}; endcase 4'h8 : if (foo[26]) foobar = {foobar," 709"}; else foobar = {foobar," 710"}; 4'h9 : case (foo[26:25]) 2'b00 : foobar = {foobar," 711"}; 2'b01 : foobar = {foobar," 712"}; 2'b10 : foobar = {foobar," 713"}; 2'b11 : foobar = {foobar," 714"}; endcase 4'ha : case (foo[26:25]) 2'b00 : foobar = {foobar," 715"}; 2'b01 : foobar = {foobar," 716"}; 2'b10 : foobar = {foobar," 717"}; 2'b11 : foobar = {foobar," 718"}; endcase 4'hb : case (foo[26:25]) 2'b00 : foobar = {foobar," 719"}; 2'b01 : foobar = {foobar," 720"}; 2'b10 : foobar = {foobar," 721"}; 2'b11 : foobar = {foobar," 722"}; endcase 4'hc : if (foo[26]) foobar = {foobar," 723"}; else foobar = {foobar," 724"}; 4'hd : case (foo[26:25]) 2'b00 : foobar = {foobar," 725"}; 2'b01 : foobar = {foobar," 726"}; 2'b10 : foobar = {foobar," 727"}; 2'b11 : foobar = {foobar," 728"}; endcase 4'he : case (foo[26:25]) 2'b00 : foobar = {foobar," 729"}; 2'b01 : foobar = {foobar," 730"}; 2'b10 : foobar = {foobar," 731"}; 2'b11 : foobar = {foobar," 732"}; endcase 4'hf : case (foo[26:25]) 2'b00 : foobar = {foobar," 733"}; 2'b01 : foobar = {foobar," 734"}; 2'b10 : foobar = {foobar," 735"}; 2'b11 : foobar = {foobar," 736"}; endcase endcase end endtask task ozonef2e; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin casez (foo[25:21]) 5'h00 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 737"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 738"}; end 5'h01 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 739"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 740"}; end 5'h02 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 741"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 742"}; end 5'h03 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 743"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 744"}; end 5'h04 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 745"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 746"}; end 5'h05 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 747"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 748"}; end 5'h06 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 749"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 750"}; end 5'h07 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 751"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 752"}; end 5'h08 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 753"}; if (foo[ 6]) foobar = {foobar," 754"}; else foobar = {foobar," 755"}; end 5'h09 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 756"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 757"}; end 5'h0a : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 758"}; ozoneae(foo[17:15], foobar); end 5'h0b : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 759"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 760"}; end 5'h0c : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 761"}; end 5'h0d : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 762"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 763"}; end 5'h0e : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 764"}; ozoneae(foo[17:15], foobar); end 5'h0f : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 765"}; ozoneae(foo[17:15], foobar); end 5'h10 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 766"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 767"}; end 5'h11 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 768"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 769"}; end 5'h18 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 770"}; if (foo[ 6]) foobar = {foobar," 771"}; else foobar = {foobar," 772"}; end 5'h1a : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 773"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 774"}; end 5'h1b : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 775"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 776"}; if (foo[ 6]) foobar = {foobar," 777"}; else foobar = {foobar," 778"}; foobar = {foobar," 779"}; end 5'h1c : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 780"}; end 5'h1d : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 781"}; if (foo[ 6]) foobar = {foobar," 782"}; else foobar = {foobar," 783"}; foobar = {foobar," 784"}; end 5'h1e : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 785"}; if (foo[ 6]) foobar = {foobar," 786"}; else foobar = {foobar," 787"}; foobar = {foobar," 788"}; end 5'h1f : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 789"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 790"}; if (foo[ 6]) foobar = {foobar," 791"}; else foobar = {foobar," 792"}; foobar = {foobar," 793"}; end default : foobar = {foobar," 794"}; endcase end endtask task ozonef3e; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[25:21]) 5'h00, 5'h01, 5'h02: begin ozoneae(foo[20:18], foobar); case (foo[22:21]) 2'h0: foobar = {foobar," 795"}; 2'h1: foobar = {foobar," 796"}; 2'h2: foobar = {foobar," 797"}; endcase ozoneae(foo[17:15], foobar); foobar = {foobar," 798"}; if (foo[ 9]) ozoneae(foo[ 8: 6], foobar); else ozonef3e_te(foo[ 8: 6], foobar); foobar = {foobar," 799"}; end 5'h08, 5'h09, 5'h0d, 5'h0e, 5'h0f: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 800"}; ozoneae(foo[17:15], foobar); case (foo[23:21]) 3'h0: foobar = {foobar," 801"}; 3'h1: foobar = {foobar," 802"}; 3'h5: foobar = {foobar," 803"}; 3'h6: foobar = {foobar," 804"}; 3'h7: foobar = {foobar," 805"}; endcase if (foo[ 9]) ozoneae(foo[ 8: 6], foobar); else ozonef3e_te(foo[ 8: 6], foobar); end 5'h0a, 5'h0b: begin ozoneae(foo[17:15], foobar); if (foo[21]) foobar = {foobar," 806"}; else foobar = {foobar," 807"}; if (foo[ 9]) ozoneae(foo[ 8: 6], foobar); else ozonef3e_te(foo[ 8: 6], foobar); end 5'h0c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 808"}; if (foo[ 9]) ozoneae(foo[ 8: 6], foobar); else ozonef3e_te(foo[ 8: 6], foobar); foobar = {foobar," 809"}; ozoneae(foo[17:15], foobar); end 5'h10, 5'h11, 5'h12, 5'h13: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 810"}; ozoneae(foo[17:15], foobar); case (foo[22:21]) 2'h0, 2'h2: foobar = {foobar," 811"}; 2'h1, 2'h3: foobar = {foobar," 812"}; endcase ozoneae(foo[ 8: 6], foobar); foobar = {foobar," 813"}; ozoneae((foo[20:18]+1), foobar); foobar = {foobar," 814"}; ozoneae((foo[17:15]+1), foobar); case (foo[22:21]) 2'h0, 2'h3: foobar = {foobar," 815"}; 2'h1, 2'h2: foobar = {foobar," 816"}; endcase ozoneae((foo[ 8: 6]+1), foobar); end 5'h18: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 817"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 818"}; ozoneae(foo[ 8: 6], foobar); foobar = {foobar," 819"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 820"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 821"}; ozoneae(foo[ 8: 6], foobar); end default : foobar = {foobar," 822"}; endcase end endtask task ozonef3e_te; input [ 2:0] te; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (te) 3'b100 : foobar = {foobar, " 823"}; 3'b101 : foobar = {foobar, " 824"}; 3'b110 : foobar = {foobar, " 825"}; default: foobar = {foobar, " 826"}; endcase end endtask task ozonearm; input [ 2:0] ate; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (ate) 3'b000 : foobar = {foobar, " 827"}; 3'b001 : foobar = {foobar, " 828"}; 3'b010 : foobar = {foobar, " 829"}; 3'b011 : foobar = {foobar, " 830"}; 3'b100 : foobar = {foobar, " 831"}; 3'b101 : foobar = {foobar, " 832"}; 3'b110 : foobar = {foobar, " 833"}; 3'b111 : foobar = {foobar, " 834"}; endcase end endtask task ozonebmuop; input [ 4:0] f4; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (f4[ 4:0]) 5'h00, 5'h04 : foobar = {foobar, " 835"}; 5'h01, 5'h05 : foobar = {foobar, " 836"}; 5'h02, 5'h06 : foobar = {foobar, " 837"}; 5'h03, 5'h07 : foobar = {foobar, " 838"}; 5'h08, 5'h18 : foobar = {foobar, " 839"}; 5'h09, 5'h19 : foobar = {foobar, " 840"}; 5'h0a, 5'h1a : foobar = {foobar, " 841"}; 5'h0b : foobar = {foobar, " 842"}; 5'h1b : foobar = {foobar, " 843"}; 5'h0c, 5'h1c : foobar = {foobar, " 844"}; 5'h0d, 5'h1d : foobar = {foobar, " 845"}; 5'h1e : foobar = {foobar, " 846"}; endcase end endtask task ozonef3; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; reg nacho; // verilator no_inline_task begin : f3_body nacho = 1'b0; case (foo[24:21]) 4'h0: case (foo[26:25]) 2'b00 : foobar = {foobar, " 847"}; 2'b01 : foobar = {foobar, " 848"}; 2'b10 : foobar = {foobar, " 849"}; 2'b11 : foobar = {foobar, " 850"}; endcase 4'h1: case (foo[26:25]) 2'b00 : foobar = {foobar, " 851"}; 2'b01 : foobar = {foobar, " 852"}; 2'b10 : foobar = {foobar, " 853"}; 2'b11 : foobar = {foobar, " 854"}; endcase 4'h2: case (foo[26:25]) 2'b00 : foobar = {foobar, " 855"}; 2'b01 : foobar = {foobar, " 856"}; 2'b10 : foobar = {foobar, " 857"}; 2'b11 : foobar = {foobar, " 858"}; endcase 4'h8, 4'h9, 4'hd, 4'he, 4'hf : case (foo[26:25]) 2'b00 : foobar = {foobar, " 859"}; 2'b01 : foobar = {foobar, " 860"}; 2'b10 : foobar = {foobar, " 861"}; 2'b11 : foobar = {foobar, " 862"}; endcase 4'ha, 4'hb : if (foo[25]) foobar = {foobar, " 863"}; else foobar = {foobar, " 864"}; 4'hc : if (foo[26]) foobar = {foobar, " 865"}; else foobar = {foobar, " 866"}; default : begin foobar = {foobar, " 867"}; nacho = 1'b1; end endcase if (~nacho) begin case (foo[24:21]) 4'h8 : foobar = {foobar, " 868"}; 4'h9 : foobar = {foobar, " 869"}; 4'ha, 4'he : foobar = {foobar, " 870"}; 4'hb, 4'hf : foobar = {foobar, " 871"}; 4'hd : foobar = {foobar, " 872"}; endcase if (foo[20]) case (foo[18:16]) 3'b000 : foobar = {foobar, " 873"}; 3'b100 : foobar = {foobar, " 874"}; default: foobar = {foobar, " 875"}; endcase else ozoneae(foo[18:16], foobar); if (foo[24:21] === 4'hc) if (foo[25]) foobar = {foobar, " 876"}; else foobar = {foobar, " 877"}; case (foo[24:21]) 4'h0, 4'h1, 4'h2: foobar = {foobar, " 878"}; endcase end end endtask task ozonerx; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[19:18]) 2'h0 : foobar = {foobar, " 879"}; 2'h1 : foobar = {foobar, " 880"}; 2'h2 : foobar = {foobar, " 881"}; 2'h3 : foobar = {foobar, " 882"}; endcase case (foo[17:16]) 2'h1 : foobar = {foobar, " 883"}; 2'h2 : foobar = {foobar, " 884"}; 2'h3 : foobar = {foobar, " 885"}; endcase end endtask task ozonerme; input [ 2:0] rme; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (rme) 3'h0 : foobar = {foobar, " 886"}; 3'h1 : foobar = {foobar, " 887"}; 3'h2 : foobar = {foobar, " 888"}; 3'h3 : foobar = {foobar, " 889"}; 3'h4 : foobar = {foobar, " 890"}; 3'h5 : foobar = {foobar, " 891"}; 3'h6 : foobar = {foobar, " 892"}; 3'h7 : foobar = {foobar, " 893"}; endcase end endtask task ozoneye; input [5:0] ye; input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin foobar = {foobar, " 894"}; ozonerme(ye[5:3],foobar); case ({ye[ 2:0], l}) 4'h2, 4'ha: foobar = {foobar, " 895"}; 4'h4, 4'hb: foobar = {foobar, " 896"}; 4'h6, 4'he: foobar = {foobar, " 897"}; 4'h8, 4'hc: foobar = {foobar, " 898"}; endcase end endtask task ozonef1e_ye; input [5:0] ye; input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin foobar = {foobar, " 899"}; ozonerme(ye[5:3],foobar); ozonef1e_inc_dec(ye[5:0], l ,foobar); end endtask task ozonef1e_h; input [ 2:0] e; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin if (e[ 2:0] <= 3'h4) foobar = {foobar, " 900"}; end endtask task ozonef1e_inc_dec; input [5:0] ye; input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case ({ye[ 2:0], l}) 4'h2, 4'h3, 4'ha: foobar = {foobar, " 901"}; 4'h4, 4'h5, 4'hb: foobar = {foobar, " 902"}; 4'h6, 4'h7, 4'he: foobar = {foobar, " 903"}; 4'h8, 4'h9, 4'hc: foobar = {foobar, " 904"}; 4'hf: foobar = {foobar, " 905"}; endcase end endtask task ozonef1e_hl; input [ 2:0] e; input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case ({e[ 2:0], l}) 4'h0, 4'h2, 4'h4, 4'h6, 4'h8: foobar = {foobar, " 906"}; 4'h1, 4'h3, 4'h5, 4'h7, 4'h9: foobar = {foobar, " 907"}; endcase end endtask task ozonexe; input [ 3:0] xe; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (xe[3]) 1'b0 : foobar = {foobar, " 908"}; 1'b1 : foobar = {foobar, " 909"}; endcase case (xe[ 2:0]) 3'h1, 3'h5: foobar = {foobar, " 910"}; 3'h2, 3'h6: foobar = {foobar, " 911"}; 3'h3, 3'h7: foobar = {foobar, " 912"}; 3'h4: foobar = {foobar, " 913"}; endcase end endtask task ozonerp; input [ 2:0] rp; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (rp) 3'h0 : foobar = {foobar, " 914"}; 3'h1 : foobar = {foobar, " 915"}; 3'h2 : foobar = {foobar, " 916"}; 3'h3 : foobar = {foobar, " 917"}; 3'h4 : foobar = {foobar, " 918"}; 3'h5 : foobar = {foobar, " 919"}; 3'h6 : foobar = {foobar, " 920"}; 3'h7 : foobar = {foobar, " 921"}; endcase end endtask task ozonery; input [ 3:0] ry; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (ry) 4'h0 : foobar = {foobar, " 922"}; 4'h1 : foobar = {foobar, " 923"}; 4'h2 : foobar = {foobar, " 924"}; 4'h3 : foobar = {foobar, " 925"}; 4'h4 : foobar = {foobar, " 926"}; 4'h5 : foobar = {foobar, " 927"}; 4'h6 : foobar = {foobar, " 928"}; 4'h7 : foobar = {foobar, " 929"}; 4'h8 : foobar = {foobar, " 930"}; 4'h9 : foobar = {foobar, " 931"}; 4'ha : foobar = {foobar, " 932"}; 4'hb : foobar = {foobar, " 933"}; 4'hc : foobar = {foobar, " 934"}; 4'hd : foobar = {foobar, " 935"}; 4'he : foobar = {foobar, " 936"}; 4'hf : foobar = {foobar, " 937"}; endcase end endtask task ozonearx; input [ 15:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[1:0]) 2'h0 : foobar = {foobar, " 938"}; 2'h1 : foobar = {foobar, " 939"}; 2'h2 : foobar = {foobar, " 940"}; 2'h3 : foobar = {foobar, " 941"}; endcase end endtask task ozonef3f4imop; input [ 4:0] f3f4iml; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin casez (f3f4iml) 5'b000??: foobar = {foobar, " 942"}; 5'b001??: foobar = {foobar, " 943"}; 5'b?10??: foobar = {foobar, " 944"}; 5'b0110?: foobar = {foobar, " 945"}; 5'b01110: foobar = {foobar, " 946"}; 5'b01111: foobar = {foobar, " 947"}; 5'b10???: foobar = {foobar, " 948"}; 5'b11100: foobar = {foobar, " 949"}; 5'b11101: foobar = {foobar, " 950"}; 5'b11110: foobar = {foobar, " 951"}; 5'b11111: foobar = {foobar, " 952"}; endcase end endtask task ozonecon; input [ 4:0] con; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (con) 5'h00 : foobar = {foobar, " 953"}; 5'h01 : foobar = {foobar, " 954"}; 5'h02 : foobar = {foobar, " 955"}; 5'h03 : foobar = {foobar, " 956"}; 5'h04 : foobar = {foobar, " 957"}; 5'h05 : foobar = {foobar, " 958"}; 5'h06 : foobar = {foobar, " 959"}; 5'h07 : foobar = {foobar, " 960"}; 5'h08 : foobar = {foobar, " 961"}; 5'h09 : foobar = {foobar, " 962"}; 5'h0a : foobar = {foobar, " 963"}; 5'h0b : foobar = {foobar, " 964"}; 5'h0c : foobar = {foobar, " 965"}; 5'h0d : foobar = {foobar, " 966"}; 5'h0e : foobar = {foobar, " 967"}; 5'h0f : foobar = {foobar, " 968"}; 5'h10 : foobar = {foobar, " 969"}; 5'h11 : foobar = {foobar, " 970"}; 5'h12 : foobar = {foobar, " 971"}; 5'h13 : foobar = {foobar, " 972"}; 5'h14 : foobar = {foobar, " 973"}; 5'h15 : foobar = {foobar, " 974"}; 5'h16 : foobar = {foobar, " 975"}; 5'h17 : foobar = {foobar, " 976"}; 5'h18 : foobar = {foobar, " 977"}; 5'h19 : foobar = {foobar, " 978"}; 5'h1a : foobar = {foobar, " 979"}; 5'h1b : foobar = {foobar, " 980"}; 5'h1c : foobar = {foobar, " 981"}; 5'h1d : foobar = {foobar, " 982"}; 5'h1e : foobar = {foobar, " 983"}; 5'h1f : foobar = {foobar, " 984"}; endcase end endtask task ozonedr; input [ 15:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[ 9: 6]) 4'h0 : foobar = {foobar, " 985"}; 4'h1 : foobar = {foobar, " 986"}; 4'h2 : foobar = {foobar, " 987"}; 4'h3 : foobar = {foobar, " 988"}; 4'h4 : foobar = {foobar, " 989"}; 4'h5 : foobar = {foobar, " 990"}; 4'h6 : foobar = {foobar, " 991"}; 4'h7 : foobar = {foobar, " 992"}; 4'h8 : foobar = {foobar, " 993"}; 4'h9 : foobar = {foobar, " 994"}; 4'ha : foobar = {foobar, " 995"}; 4'hb : foobar = {foobar, " 996"}; 4'hc : foobar = {foobar, " 997"}; 4'hd : foobar = {foobar, " 998"}; 4'he : foobar = {foobar, " 999"}; 4'hf : foobar = {foobar, " 1000"}; endcase end endtask task ozoneshift; input [ 15:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[ 4: 3]) 2'h0 : foobar = {foobar, " 1001"}; 2'h1 : foobar = {foobar, " 1002"}; 2'h2 : foobar = {foobar, " 1003"}; 2'h3 : foobar = {foobar, " 1004"}; endcase end endtask task ozoneacc; input foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo) 2'h0 : foobar = {foobar, " 1005"}; 2'h1 : foobar = {foobar, " 1006"}; endcase end endtask task ozonehl; input foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo) 2'h0 : foobar = {foobar, " 1007"}; 2'h1 : foobar = {foobar, " 1008"}; endcase end endtask task dude; inout [STRLEN*8: 1] foobar; reg [ 7:0] temp; integer i; reg nacho; // verilator no_inline_task begin : justify_block nacho = 1'b0; for (i=STRLEN-1; i>1; i=i-1) begin temp = foobar>>((STRLEN-1)*8); if (temp || nacho) nacho = 1'b1; else begin foobar = foobar<<8; foobar[8:1] = 32; end end end endtask task big_case; input [ 31:0] fd; input [ 31:0] foo; reg [STRLEN*8: 1] foobar; // verilator no_inline_task begin foobar = " 1009"; if (&foo === 1'bx) $fwrite(fd, " 1010"); else casez ( {foo[31:26], foo[19:15], foo[5:0]} ) 17'b00_111?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1011"}; ozoneacc(~foo[26], foobar); ozonehl(foo[20], foobar); foobar = {foobar, " 1012"}; ozonerx(foo, foobar); dude(foobar); $fwrite (fd, " 1013:%s", foobar); end 17'b01_001?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1014"}; ozonerx(foo, foobar); foobar = {foobar, " 1015"}; foobar = {foobar, " 1016"}; ozonehl(foo[20], foobar); dude(foobar); $fwrite (fd, " 1017:%s", foobar); end 17'b10_100?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1018"}; ozonerx(foo, foobar); foobar = {foobar, " 1019"}; foobar = {foobar, " 1020"}; ozonehl(foo[20], foobar); dude(foobar); $fwrite (fd, " 1021:%s", foobar); end 17'b10_101?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1022"}; if (foo[20]) begin foobar = {foobar, " 1023"}; ozoneacc(foo[18], foobar); foobar = {foobar, " 1024"}; foobar = {foobar, " 1025"}; if (foo[19]) foobar = {foobar, " 1026"}; else foobar = {foobar, " 1027"}; end else ozonerx(foo, foobar); dude(foobar); $fwrite (fd, " 1028:%s", foobar); end 17'b10_110?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1029"}; foobar = {foobar, " 1030"}; ozonehl(foo[20], foobar); foobar = {foobar, " 1031"}; ozonerx(foo, foobar); dude(foobar); $fwrite (fd, " 1032:%s", foobar); end 17'b10_111?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1033"}; foobar = {foobar, " 1034"}; ozonehl(foo[20], foobar); foobar = {foobar, " 1035"}; ozonerx(foo, foobar); dude(foobar); $fwrite (fd, " 1036:%s", foobar); end 17'b11_001?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1037"}; ozonerx(foo, foobar); foobar = {foobar, " 1038"}; foobar = {foobar, " 1039"}; ozonehl(foo[20], foobar); dude(foobar); $fwrite (fd, " 1040:%s", foobar); end 17'b11_111?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1041"}; foobar = {foobar, " 1042"}; ozonerx(foo, foobar); foobar = {foobar, " 1043"}; if (foo[20]) foobar = {foobar, " 1044"}; else foobar = {foobar, " 1045"}; dude(foobar); $fwrite (fd, " 1046:%s", foobar); end 17'b00_10??_?_????_?1_1111 : casez (foo[11: 5]) 7'b??_0_010_0: begin foobar = " 1047"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1048"}; ozonef1e(foo, foobar); dude(foobar); $fwrite (fd, " 1049:%s", foobar); end 7'b00_?_110_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1050"}; case ({foo[ 9],foo[ 5]}) 2'b00: begin foobar = {foobar, " 1051"}; ozoneae(foo[14:12], foobar); ozonehl(foo[ 5], foobar); end 2'b01: begin foobar = {foobar, " 1052"}; ozoneae(foo[14:12], foobar); ozonehl(foo[ 5], foobar); end 2'b10: begin foobar = {foobar, " 1053"}; ozoneae(foo[14:12], foobar); end 2'b11: foobar = {foobar, " 1054"}; endcase dude(foobar); $fwrite (fd, " 1055:%s", foobar); end 7'b01_?_110_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1056"}; case ({foo[ 9],foo[ 5]}) 2'b00: begin ozoneae(foo[14:12], foobar); ozonehl(foo[ 5], foobar); foobar = {foobar, " 1057"}; end 2'b01: begin ozoneae(foo[14:12], foobar); ozonehl(foo[ 5], foobar); foobar = {foobar, " 1058"}; end 2'b10: begin ozoneae(foo[14:12], foobar); foobar = {foobar, " 1059"}; end 2'b11: foobar = {foobar, " 1060"}; endcase dude(foobar); $fwrite (fd, " 1061:%s", foobar); end 7'b10_0_110_0: begin ozonef1e(foo, foobar); foobar = {foobar, " 1062"}; foobar = {foobar, " 1063"}; if (foo[12]) foobar = {foobar, " 1064"}; else ozonerab({4'b1001, foo[14:12]}, foobar); dude(foobar); $fwrite (fd, " 1065:%s", foobar); end 7'b10_0_110_1: begin ozonef1e(foo, foobar); foobar = {foobar, " 1066"}; if (foo[12]) foobar = {foobar, " 1067"}; else ozonerab({4'b1001, foo[14:12]}, foobar); foobar = {foobar, " 1068"}; dude(foobar); $fwrite (fd, " 1069:%s", foobar); end 7'b??_?_000_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1070"}; foobar = {foobar, " 1071"}; ozonef1e_hl(foo[11:9],foo[ 5],foobar); foobar = {foobar, " 1072"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1073:%s", foobar); end 7'b??_?_100_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1074"}; foobar = {foobar, " 1075"}; ozonef1e_hl(foo[11:9],foo[ 5],foobar); foobar = {foobar, " 1076"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1077:%s", foobar); end 7'b??_?_001_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1078"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); foobar = {foobar, " 1079"}; foobar = {foobar, " 1080"}; ozonef1e_hl(foo[11:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1081:%s", foobar); end 7'b??_?_011_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1082"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); foobar = {foobar, " 1083"}; foobar = {foobar, " 1084"}; ozonef1e_hl(foo[11:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1085:%s", foobar); end 7'b??_?_101_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1086"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1087:%s", foobar); end endcase 17'b00_10??_?_????_?0_0110 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1088"}; ozoneae(foo[ 8: 6], foobar); ozonef1e_hl(foo[11:9],foo[ 5],foobar); foobar = {foobar, " 1089"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1090:%s", foobar); end 17'b00_10??_?_????_00_0111 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1091"}; if (foo[ 6]) foobar = {foobar, " 1092"}; else ozonerab({4'b1001, foo[ 8: 6]}, foobar); foobar = {foobar, " 1093"}; foobar = {foobar, " 1094"}; ozonerme(foo[14:12],foobar); case (foo[11: 9]) 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9],1'b0,foobar); 3'h1, 3'h3, 3'h4: foobar = {foobar, " 1095"}; endcase dude(foobar); $fwrite (fd, " 1096:%s", foobar); end 17'b00_10??_?_????_?0_0100 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1097"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); foobar = {foobar, " 1098"}; ozoneae(foo[ 8: 6], foobar); ozonef1e_hl(foo[11:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1099:%s", foobar); end 17'b00_10??_?_????_10_0111 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1100"}; foobar = {foobar, " 1101"}; ozonerme(foo[14:12],foobar); case (foo[11: 9]) 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9],1'b0,foobar); 3'h1, 3'h3, 3'h4: foobar = {foobar, " 1102"}; endcase foobar = {foobar, " 1103"}; if (foo[ 6]) foobar = {foobar, " 1104"}; else ozonerab({4'b1001, foo[ 8: 6]}, foobar); dude(foobar); $fwrite (fd, " 1105:%s", foobar); end 17'b00_10??_?_????_?0_1110 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1106"}; case (foo[11:9]) 3'h2: begin foobar = {foobar, " 1107"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1108"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1109"}; end 3'h6: begin foobar = {foobar, " 1110"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1111"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1112"}; end 3'h0: begin foobar = {foobar, " 1113"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1114"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1115"}; if (foo[ 7: 5] >= 3'h5) foobar = {foobar, " 1116"}; else ozonexe(foo[ 8: 5], foobar); end 3'h1: begin foobar = {foobar, " 1117"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1118"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1119"}; if (foo[ 7: 5] >= 3'h5) foobar = {foobar, " 1120"}; else ozonexe(foo[ 8: 5], foobar); end 3'h4: begin foobar = {foobar, " 1121"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1122"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1123"}; if (foo[ 7: 5] >= 3'h5) foobar = {foobar, " 1124"}; else ozonexe(foo[ 8: 5], foobar); end 3'h5: begin foobar = {foobar, " 1125"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1126"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1127"}; if (foo[ 7: 5] >= 3'h5) foobar = {foobar, " 1128"}; else ozonexe(foo[ 8: 5], foobar); end endcase dude(foobar); $fwrite (fd, " 1129:%s", foobar); end 17'b00_10??_?_????_?0_1111 : casez (foo[14: 9]) 6'b001_10_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1130"}; foobar = {foobar, " 1131"}; ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); foobar = {foobar, " 1132"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1133:%s", foobar); end 6'b???_11_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1134"}; ozoneae(foo[14:12], foobar); ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); foobar = {foobar, " 1135"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1136:%s", foobar); end 6'b000_10_1, 6'b010_10_1, 6'b100_10_1, 6'b110_10_1: begin ozonef1e(foo, foobar); foobar = {foobar, " 1137"}; ozonerab({4'b1001, foo[14:12]}, foobar); foobar = {foobar, " 1138"}; if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) foobar = {foobar, " 1139"}; else ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1140:%s", foobar); end 6'b000_10_0, 6'b010_10_0, 6'b100_10_0, 6'b110_10_0: begin ozonef1e(foo, foobar); foobar = {foobar, " 1141"}; foobar = {foobar, " 1142"}; ozonerab({4'b1001, foo[14:12]}, foobar); foobar = {foobar, " 1143"}; foobar = {foobar, " 1144"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1145"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1146:%s", foobar); end 6'b???_00_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1147"}; if (foo[ 9]) begin foobar = {foobar, " 1148"}; ozoneae(foo[14:12], foobar); end else begin foobar = {foobar, " 1149"}; ozoneae(foo[14:12], foobar); foobar = {foobar, " 1150"}; end foobar = {foobar, " 1151"}; foobar = {foobar, " 1152"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1153"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1154:%s", foobar); end 6'b???_01_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1155"}; ozoneae(foo[14:12], foobar); if (foo[ 9]) foobar = {foobar, " 1156"}; else foobar = {foobar, " 1157"}; foobar = {foobar, " 1158"}; foobar = {foobar, " 1159"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1160"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1161:%s", foobar); end 6'b011_10_0: begin ozonef1e(foo, foobar); foobar = {foobar, " 1162"}; case (foo[ 8: 5]) 4'h0: foobar = {foobar, " 1163"}; 4'h1: foobar = {foobar, " 1164"}; 4'h2: foobar = {foobar, " 1165"}; 4'h3: foobar = {foobar, " 1166"}; 4'h4: foobar = {foobar, " 1167"}; 4'h5: foobar = {foobar, " 1168"}; 4'h8: foobar = {foobar, " 1169"}; 4'h9: foobar = {foobar, " 1170"}; 4'ha: foobar = {foobar, " 1171"}; 4'hb: foobar = {foobar, " 1172"}; 4'hc: foobar = {foobar, " 1173"}; 4'hd: foobar = {foobar, " 1174"}; default: foobar = {foobar, " 1175"}; endcase dude(foobar); $fwrite (fd, " 1176:%s", foobar); end default: foobar = {foobar, " 1177"}; endcase 17'b00_10??_?_????_?0_110? : begin ozonef1e(foo, foobar); foobar = {foobar, " 1178"}; foobar = {foobar, " 1179"}; ozonef1e_hl(foo[11:9], foo[0], foobar); foobar = {foobar, " 1180"}; ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1181"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1182"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1183:%s", foobar); end 17'b00_10??_?_????_?1_110? : begin ozonef1e(foo, foobar); foobar = {foobar, " 1184"}; foobar = {foobar, " 1185"}; ozonef1e_hl(foo[11:9],foo[0],foobar); foobar = {foobar, " 1186"}; ozonef1e_ye(foo[14:9],foo[ 0],foobar); foobar = {foobar, " 1187"}; foobar = {foobar, " 1188"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1189"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1190:%s", foobar); end 17'b00_10??_?_????_?0_101? : begin ozonef1e(foo, foobar); foobar = {foobar, " 1191"}; ozonef1e_ye(foo[14:9],foo[ 0],foobar); foobar = {foobar, " 1192"}; foobar = {foobar, " 1193"}; ozonef1e_hl(foo[11:9],foo[0],foobar); foobar = {foobar, " 1194"}; foobar = {foobar, " 1195"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1196"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1197:%s", foobar); end 17'b00_10??_?_????_?0_1001 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1198"}; foobar = {foobar, " 1199"}; ozonef1e_h(foo[11:9],foobar); foobar = {foobar, " 1200"}; ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1201"}; case (foo[ 7: 5]) 3'h1, 3'h2, 3'h3: foobar = {foobar, " 1202"}; default: begin foobar = {foobar, " 1203"}; foobar = {foobar, " 1204"}; ozonexe(foo[ 8: 5], foobar); end endcase dude(foobar); $fwrite (fd, " 1205:%s", foobar); end 17'b00_10??_?_????_?0_0101 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1206"}; case (foo[11: 9]) 3'h1, 3'h3, 3'h4: foobar = {foobar, " 1207"}; default: begin ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1208"}; foobar = {foobar, " 1209"}; end endcase foobar = {foobar, " 1210"}; foobar = {foobar, " 1211"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1212"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1213:%s", foobar); end 17'b00_10??_?_????_?1_1110 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1214"}; ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1215"}; foobar = {foobar, " 1216"}; ozonef1e_h(foo[11: 9],foobar); foobar = {foobar, " 1217"}; foobar = {foobar, " 1218"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1219"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1220:%s", foobar); end 17'b00_10??_?_????_?0_1000 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1221"}; ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1222"}; foobar = {foobar, " 1223"}; ozonef1e_h(foo[11: 9],foobar); foobar = {foobar, " 1224"}; foobar = {foobar, " 1225"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1226"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1227:%s", foobar); end 17'b10_01??_?_????_??_???? : begin if (foo[27]) foobar = " 1228"; else foobar = " 1229"; ozonecon(foo[20:16], foobar); foobar = {foobar, " 1230"}; ozonef2(foo[31:0], foobar); dude(foobar); $fwrite (fd, " 1231:%s", foobar); end 17'b00_1000_?_????_01_0011 : if (~|foo[ 9: 8]) begin if (foo[ 7]) foobar = " 1232"; else foobar = " 1233"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1234"}; ozonef2e(foo[31:0], foobar); dude(foobar); $fwrite (fd, " 1235:%s", foobar); end else begin foobar = " 1236"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1237"}; ozonef3e(foo[31:0], foobar); dude(foobar); $fwrite (fd, " 1238:%s", foobar); end 17'b11_110?_1_????_??_???? : begin ozonef3(foo[31:0], foobar); dude(foobar); $fwrite(fd, " 1239:%s", foobar); end 17'b11_110?_0_????_??_???? : begin : f4_body casez (foo[24:20]) 5'b0_1110, 5'b1_0???, 5'b1_1111: begin $fwrite (fd, " 1240"); end 5'b0_00??: begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1241"}; ozoneacc(foo[25], foobar); ozonebmuop(foo[24:20], foobar); ozoneae(foo[18:16], foobar); foobar = {foobar, " 1242"}; dude(foobar); $fwrite(fd, " 1243:%s", foobar); end 5'b0_01??: begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1244"}; ozoneacc(foo[25], foobar); ozonebmuop(foo[24:20], foobar); ozonearm(foo[18:16], foobar); dude(foobar); $fwrite(fd, " 1245:%s", foobar); end 5'b0_1011: begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1246"}; ozonebmuop(foo[24:20], foobar); foobar = {foobar, " 1247"}; ozoneae(foo[18:16], foobar); foobar = {foobar, " 1248"}; dude(foobar); $fwrite(fd, " 1249:%s", foobar); end 5'b0_100?, 5'b0_1010, 5'b0_110? : begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1250"}; ozonebmuop(foo[24:20], foobar); foobar = {foobar, " 1251"}; ozoneacc(foo[25], foobar); foobar = {foobar, " 1252"}; ozoneae(foo[18:16], foobar); foobar = {foobar, " 1253"}; dude(foobar); $fwrite(fd, " 1254:%s", foobar); end 5'b0_1111 : begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1255"}; ozoneacc(foo[25], foobar); foobar = {foobar, " 1256"}; ozoneae(foo[18:16], foobar); dude(foobar); $fwrite(fd, " 1257:%s", foobar); end 5'b1_10??, 5'b1_110?, 5'b1_1110 : begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1258"}; ozonebmuop(foo[24:20], foobar); foobar = {foobar, " 1259"}; ozoneacc(foo[25], foobar); foobar = {foobar, " 1260"}; ozonearm(foo[18:16], foobar); foobar = {foobar, " 1261"}; dude(foobar); $fwrite(fd, " 1262:%s", foobar); end endcase end 17'b11_100?_?_????_??_???? : casez (foo[23:19]) 5'b111??, 5'b0111?: begin ozoneae(foo[26:24], foobar); foobar = {foobar, " 1263"}; ozonef3f4imop(foo[23:19], foobar); foobar = {foobar, " 1264"}; ozoneae(foo[18:16], foobar); foobar = {foobar, " 1265"}; skyway(foo[15:12], foobar); skyway(foo[11: 8], foobar); skyway(foo[ 7: 4], foobar); skyway(foo[ 3:0], foobar); foobar = {foobar, " 1266"}; dude(foobar); $fwrite(fd, " 1267:%s", foobar); end 5'b?0???, 5'b110??: begin ozoneae(foo[26:24], foobar); foobar = {foobar, " 1268"}; if (foo[23:21] == 3'b100) foobar = {foobar, " 1269"}; ozoneae(foo[18:16], foobar); if (foo[19]) foobar = {foobar, " 1270"}; else foobar = {foobar, " 1271"}; ozonef3f4imop(foo[23:19], foobar); foobar = {foobar, " 1272"}; ozonef3f4_iext(foo[20:19], foo[15:0], foobar); dude(foobar); $fwrite(fd, " 1273:%s", foobar); end 5'b010??, 5'b0110?: begin ozoneae(foo[18:16], foobar); if (foo[19]) foobar = {foobar, " 1274"}; else foobar = {foobar, " 1275"}; ozonef3f4imop(foo[23:19], foobar); foobar = {foobar, " 1276"}; ozonef3f4_iext(foo[20:19], foo[15:0], foobar); dude(foobar); $fwrite(fd, " 1277:%s", foobar); end endcase 17'b00_1000_?_????_11_0011 : begin foobar = " 1278"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1279"}; casez (foo[25:21]) 5'b0_1110, 5'b1_0???, 5'b1_1111: begin $fwrite(fd, " 1280"); end 5'b0_00??: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1281"}; ozoneae(foo[17:15], foobar); ozonebmuop(foo[25:21], foobar); ozoneae(foo[ 8: 6], foobar); foobar = {foobar, " 1282"}; dude(foobar); $fwrite(fd, " 1283:%s", foobar); end 5'b0_01??: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1284"}; ozoneae(foo[17:15], foobar); ozonebmuop(foo[25:21], foobar); ozonearm(foo[ 8: 6], foobar); dude(foobar); $fwrite(fd, " 1285:%s", foobar); end 5'b0_1011: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1286"}; ozonebmuop(foo[25:21], foobar); foobar = {foobar, " 1287"}; ozoneae(foo[ 8: 6], foobar); foobar = {foobar, " 1288"}; dude(foobar); $fwrite(fd, " 1289:%s", foobar); end 5'b0_100?, 5'b0_1010, 5'b0_110? : begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1290"}; ozonebmuop(foo[25:21], foobar); foobar = {foobar, " 1291"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 1292"}; ozoneae(foo[ 8: 6], foobar); foobar = {foobar, " 1293"}; dude(foobar); $fwrite(fd, " 1294:%s", foobar); end 5'b0_1111 : begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1295"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 1296"}; ozoneae(foo[ 8: 6], foobar); dude(foobar); $fwrite(fd, " 1297:%s", foobar); end 5'b1_10??, 5'b1_110?, 5'b1_1110 : begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1298"}; ozonebmuop(foo[25:21], foobar); foobar = {foobar, " 1299"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 1300"}; ozonearm(foo[ 8: 6], foobar); foobar = {foobar, " 1301"}; dude(foobar); $fwrite(fd, " 1302:%s", foobar); end endcase end 17'b00_0010_?_????_??_???? : begin $fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]); ozonerab({1'b0, foo[25:20]}, foobar); $fwrite(fd, " 1304b:%x", foobar); foobar = {foobar, " 1303"}; $fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]); skyway(foo[19:16], foobar); $fwrite(fd, " 1304d:%x", foobar); dude(foobar); $fwrite(fd, " 1304e:%x", foobar); $fwrite(fd, " 1304:%s", foobar); end 17'b00_01??_?_????_??_???? : begin if (foo[27]) begin foobar = {foobar, " 1305"}; if (foo[26]) foobar = {foobar, " 1306"}; else foobar = {foobar, " 1307"}; skyway(foo[19:16], foobar); foobar = {foobar, " 1308"}; ozonerab({1'b0, foo[25:20]}, foobar); end else begin ozonerab({1'b0, foo[25:20]}, foobar); foobar = {foobar, " 1309"}; if (foo[26]) foobar = {foobar, " 1310"}; else foobar = {foobar, " 1311"}; skyway(foo[19:16], foobar); foobar = {foobar, " 1312"}; end dude(foobar); $fwrite(fd, " 1313:%s", foobar); end 17'b01_000?_?_????_??_???? : begin if (foo[26]) begin ozonerb(foo[25:20], foobar); foobar = {foobar, " 1314"}; ozoneae(foo[18:16], foobar); ozonehl(foo[19], foobar); end else begin ozoneae(foo[18:16], foobar); ozonehl(foo[19], foobar); foobar = {foobar, " 1315"}; ozonerb(foo[25:20], foobar); end dude(foobar); $fwrite(fd, " 1316:%s", foobar); end 17'b01_10??_?_????_??_???? : begin if (foo[27]) begin ozonerab({1'b0, foo[25:20]}, foobar); foobar = {foobar, " 1317"}; ozonerx(foo, foobar); end else begin ozonerx(foo, foobar); foobar = {foobar, " 1318"}; ozonerab({1'b0, foo[25:20]}, foobar); end dude(foobar); $fwrite(fd, " 1319:%s", foobar); end 17'b11_101?_?_????_??_???? : begin ozonerab (foo[26:20], foobar); foobar = {foobar, " 1320"}; skyway(foo[19:16], foobar); skyway(foo[15:12], foobar); skyway(foo[11: 8], foobar); skyway(foo[ 7: 4], foobar); skyway(foo[ 3: 0], foobar); dude(foobar); $fwrite(fd, " 1321:%s", foobar); end 17'b11_0000_?_????_??_???? : begin casez (foo[25:23]) 3'b00?: begin ozonerab(foo[22:16], foobar); foobar = {foobar, " 1322"}; end 3'b01?: begin foobar = {foobar, " 1323"}; if (foo[22:16]>=7'h60) foobar = {foobar, " 1324"}; else ozonerab(foo[22:16], foobar); end 3'b110: foobar = {foobar, " 1325"}; 3'b10?: begin foobar = {foobar, " 1326"}; if (foo[22:16]>=7'h60) foobar = {foobar, " 1327"}; else ozonerab(foo[22:16], foobar); end 3'b111: begin foobar = {foobar, " 1328"}; ozonerab(foo[22:16], foobar); foobar = {foobar, " 1329"}; end endcase dude(foobar); $fwrite(fd, " 1330:%s", foobar); end 17'b00_10??_?_????_?1_0000 : begin if (foo[27]) begin foobar = {foobar, " 1331"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1332"}; skyway(foo[19:16], foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); foobar = {foobar, " 1333"}; if (foo[26:20]>=7'h60) foobar = {foobar, " 1334"}; else ozonerab(foo[26:20], foobar); end else begin ozonerab(foo[26:20], foobar); foobar = {foobar, " 1335"}; foobar = {foobar, " 1336"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1337"}; skyway(foo[19:16], foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); foobar = {foobar, " 1338"}; end dude(foobar); $fwrite(fd, " 1339:%s", foobar); end 17'b00_101?_1_0000_?1_0010 : if (~|foo[11: 7]) begin if (foo[ 6]) begin foobar = {foobar, " 1340"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1341"}; ozonejk(foo[ 5], foobar); foobar = {foobar, " 1342"}; if (foo[26:20]>=7'h60) foobar = {foobar, " 1343"}; else ozonerab(foo[26:20], foobar); end else begin ozonerab(foo[26:20], foobar); foobar = {foobar, " 1344"}; foobar = {foobar, " 1345"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1346"}; ozonejk(foo[ 5], foobar); foobar = {foobar, " 1347"}; end dude(foobar); $fwrite(fd, " 1348:%s", foobar); end else $fwrite(fd, " 1349"); 17'b00_100?_0_0011_?1_0101 : if (~|foo[ 8: 7]) begin if (foo[6]) begin ozonerab(foo[26:20], foobar); foobar = {foobar, " 1350"}; ozoneye(foo[14: 9],foo[ 5], foobar); end else begin ozoneye(foo[14: 9],foo[ 5], foobar); foobar = {foobar, " 1351"}; if (foo[26:20]>=7'h60) foobar = {foobar, " 1352"}; else ozonerab(foo[26:20], foobar); end dude(foobar); $fwrite(fd, " 1353:%s", foobar); end else $fwrite(fd, " 1354"); 17'b00_1001_0_0000_?1_0010 : if (~|foo[25:20]) begin ozoneye(foo[14: 9],1'b0, foobar); foobar = {foobar, " 1355"}; ozonef1e_h(foo[11: 9],foobar); foobar = {foobar, " 1356"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1357"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite(fd, " 1358:%s", foobar); end else $fwrite(fd, " 1359"); 17'b00_101?_0_????_?1_0010 : if (~foo[13]) begin if (foo[12]) begin foobar = {foobar, " 1360"}; if (foo[26:20]>=7'h60) foobar = {foobar, " 1361"}; else ozonerab(foo[26:20], foobar); foobar = {foobar, " 1362"}; foobar = {foobar, " 1363"}; skyway({1'b0,foo[18:16]}, foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); dude(foobar); $fwrite(fd, " 1364:%s", foobar); end else begin ozonerab(foo[26:20], foobar); foobar = {foobar, " 1365"}; foobar = {foobar, " 1366"}; skyway({1'b0,foo[18:16]}, foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); dude(foobar); $fwrite(fd, " 1367:%s", foobar); end end else $fwrite(fd, " 1368"); 17'b01_01??_?_????_??_???? : begin ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar); foobar = {foobar, " 1369"}; ozonerab({1'b0,foo[25:20]}, foobar); dude(foobar); $fwrite(fd, " 1370:%s", foobar); end 17'b00_100?_?_???0_11_0101 : if (~foo[6]) begin foobar = " 1371"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1372"}; ozonerab({foo[ 9: 7],foo[19:16]}, foobar); foobar = {foobar, " 1373"}; ozonerab({foo[26:20]}, foobar); dude(foobar); $fwrite(fd, " 1374:%s", foobar); end else $fwrite(fd, " 1375"); 17'b00_1000_?_????_?1_0010 : if (~|foo[25:24]) begin ozonery(foo[23:20], foobar); foobar = {foobar, " 1376"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1377"}; skyway(foo[19:16], foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); dude(foobar); $fwrite(fd, " 1378:%s", foobar); end else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) begin ozonery(foo[23:20], foobar); foobar = {foobar, " 1379"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1380"}; ozonejk(foo[ 5], foobar); dude(foobar); $fwrite(fd, " 1381:%s", foobar); end else $fwrite(fd, " 1382"); 17'b11_01??_?_????_??_????, 17'b10_00??_?_????_??_???? : if (foo[30]) $fwrite(fd, " 1383:%s", foo[27:16]); else $fwrite(fd, " 1384:%s", foo[27:16]); 17'b00_10??_?_????_01_1000 : if (~foo[6]) begin if (foo[7]) $fwrite(fd, " 1385:%s", foo[27: 8]); else $fwrite(fd, " 1386:%s", foo[27: 8]); end else $fwrite(fd, " 1387"); 17'b00_10??_?_????_11_1000 : begin foobar = " 1388"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1389"}; if (foo[15]) foobar = {foobar, " 1390"}; else foobar = {foobar, " 1391"}; skyway(foo[27:24], foobar); skyway(foo[23:20], foobar); skyway(foo[19:16], foobar); skyway(foo[ 9: 6], foobar); dude(foobar); $fwrite(fd, " 1392:%s", foobar); end 17'b11_0001_?_????_??_???? : casez (foo[25:22]) 4'b01?? : begin foobar = " 1393"; ozonecon(foo[20:16], foobar); case (foo[23:21]) 3'h0 : foobar = {foobar, " 1394"}; 3'h1 : foobar = {foobar, " 1395"}; 3'h2 : foobar = {foobar, " 1396"}; 3'h3 : foobar = {foobar, " 1397"}; 3'h4 : foobar = {foobar, " 1398"}; 3'h5 : foobar = {foobar, " 1399"}; 3'h6 : foobar = {foobar, " 1400"}; 3'h7 : foobar = {foobar, " 1401"}; endcase dude(foobar); $fwrite(fd, " 1402:%s", foobar); end 4'b0000 : $fwrite(fd, " 1403:%s", foo[21:16]); 4'b0010 : if (~|foo[21:16]) $fwrite(fd, " 1404"); 4'b1010 : if (~|foo[21:17]) begin if (foo[16]) $fwrite(fd, " 1405"); else $fwrite(fd, " 1406"); end default : $fwrite(fd, " 1407"); endcase 17'b01_11??_?_????_??_???? : if (foo[27:23] === 5'h00) $fwrite(fd, " 1408:%s", foo[22:16]); else $fwrite(fd, " 1409:%s", foo[22:16]); default: $fwrite(fd, " 1410"); endcase end endtask //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) endmodule verilator-4.038/test_regress/t/t_param_type_bad2.pl0000775000177100017500000000121413702133370022401 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( # Bug1575 required trace to crash verilator_flags2 => ["--trace --cc"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_casez.v0000664000177100017500000000116213702133367021675 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [1:0] value; initial begin value = 2'b00; unique casez (value) 2'b00 : ; 2'b01 : ; 2'b1? : ; endcase value = 2'b11; unique casez (value) 2'b00 : ; 2'b01 : ; 2'b1? : ; endcase unique casez (1'b1) default: ; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_assert_implication.v0000664000177100017500000000171713702133367023106 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Peter Monsson. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; Test test (/*AUTOINST*/ // Inputs .clk (clk)); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test ( input clk ); `ifdef FAIL_ASSERT_1 assert property ( @(posedge clk) 1 |-> 0 ) else $display("[%0t] wrong implication", $time); `endif assert property ( @(posedge clk) 1 |-> 1 ); assert property ( @(posedge clk) 0 |-> 0 ); assert property ( @(posedge clk) 0 |-> 1 ); endmodule verilator-4.038/test_regress/t/t_clk_concat3.pl0000775000177100017500000000106013702133367021540 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_dumpfst_cc.pl0000775000177100017500000000226613702133370023556 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); top_filename("t_trace_two_a.v"); compile( make_main => 0, verilator_make_gmake => 0, top_filename => 't_trace_two_b.v', VM_PREFIX => 'Vt_trace_two_b', verilator_flags2 => ['--trace-fst --trace-threads 1 -DTEST_FST'], ); compile( make_main => 0, top_filename => 't_trace_two_a.v', verilator_flags2 => ['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', "$Self->{t_dir}/t_trace_two_cc.cpp"], v_flags2 => ['+define+TEST_DUMP'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { fst_identical($Self->trace_filename, $Self->{golden_filename}); } ok(1); 1; verilator-4.038/test_regress/t/t_param_first_b.v0000664000177100017500000000075713702133370022022 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_param_first_b (/*AUTOARG*/ // Outputs par, varwidth ); parameter X = 1; parameter FIVE = 0; // Overridden parameter TWO = 2; output [4:0] par; output [X:0] varwidth; wire [4:0] par = X; wire [X:0] varwidth = (FIVE==5)?TWO:0; endmodule verilator-4.038/test_regress/t/t_mem_packed_assign.pl0000775000177100017500000000105313702133370023002 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_werror_bad3.pl0000775000177100017500000000123113702133370022551 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_werror.v"); lint( fails => 1, verilator_flags => [qw(-cc -Werror-NOSUCHERRORASTHIS)], expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_lsb.pl0000775000177100017500000000105313702133370020762 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_sformat.v0000664000177100017500000000435313702133370021557 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "verilated.v" module t; // Note $sscanf already tested elsewhere reg [3:0] n; reg [63:0] q; reg [16*8:1] wide; reg [8:1] ochar; reg [48*8:1] str; reg [48*8:1] str2; string str3; real r; initial begin n = 4'b1100; q = 64'h1234_5678_abcd_0123; wide = "hello-there12345"; $sformat(str, "n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str=%0s",str); `endif if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop; q = {q[62:0],1'b1}; $swrite(str2, "n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; str3 = $sformatf("n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; $swrite(str2, "e=%e", r); $swrite(str2, "e=%f", r); $swrite(str2, "e=%g", r); str3 = "hello"; $swrite(str2, {str3, str3}); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "hellohello") $stop; r = 0.01; $swrite(str2, "e=%e f=%f g=%g", r, r, r); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop; $swrite(str2, "mod=%m"); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "mod=top.t") $stop; $swrite(str2, "lib=%l"); `ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif if (str2 !== "lib=t") $stop; str3 = $sformatf("u=%u", {"a","b","c","d"}); // Value selected so is printable `ifdef TEST_VERBOSE $display("chku %s", str3); `endif if (str3 !== "u=dcba") $stop; str3 = $sformatf("v=%v", {"a","b","c","d"}); // Value selected so is printable `ifdef TEST_VERBOSE $display("chkv %s", str3); `endif $sformat(ochar,"%s","c"); if (ochar != "c") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_array_list_bad.out0000664000177100017500000000120513702133367022526 0ustar wsnyderwsnyder%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: MEMBERDTYPE 't3' : ... In instance t 38 | test_out <= '{'0, '0}; | ^~ %Warning-WIDTH: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. : ... In instance t 38 | test_out <= '{'0, '0}; | ^~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_dpi_openfirst.v0000664000177100017500000000255713702133370022057 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) `else `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) `endif module t (/*AUTOARG*/); int i_i [2:0]; int o_i [2:0]; import "DPI-C" function int dpii_failure(); import "DPI-C" function void dpii_open_i(input int i [], output int o []); reg [95:0] crc; initial begin crc = 96'h8a10a572_5aef0c8d_d70a4497; i_i[0] = crc[31:0]; i_i[1] = crc[63:32]; i_i[2] = crc[95:64]; dpii_open_i(i_i, o_i); `checkh(o_i[0], ~i_i[0]); `checkh(o_i[1], ~i_i[1]); `checkh(o_i[2], ~i_i[2]); if (dpii_failure()!=0) begin $write("%%Error: Failure in DPI tests\n"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_altera_lpm_and.pl0000775000177100017500000000120613702133367022321 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_math_vliw.pl0000775000177100017500000000105313702133370021343 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_c_api.pl0000775000177100017500000000155413702133370021610 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_c_api.cpp", "-CFLAGS -DVERILATED_VCD_TEST", "-CFLAGS -DVL_TRACE_VCD_OLD_API"], ); execute( check_finished => 1, ); # vcddiff bug crashes #vcd_identical("$Self->{obj_dir}/simx.vcd", # $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_inst_array_partial.pl0000775000177100017500000000105313702133370023240 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_array_noinl.pl0000775000177100017500000000115413702133370023710 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_array.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_timescale_parse.pl0000775000177100017500000000123413702133370022512 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_multi_io2.v0000664000177100017500000000153613702133370021747 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o3, o34, o345, // Inputs i3, i34, i345 ); input [15:0] i3; output wire [15:0] o3; input [15:0] i34 [3:0]; output wire [15:0] o34 [3:0]; input [15:0] i345 [3:0][4:0]; output wire [15:0] o345 [3:0][4:0]; sub sub (.*); endmodule module sub (/*AUTOARG*/ // Outputs o3, o34, o345, // Inputs i3, i34, i345 ); input [15:0] i3; output wire [15:0] o3; input [15:0] i34 [3:0]; output wire [15:0] o34 [3:0]; input [15:0] i345 [3:0][4:0]; output wire [15:0] o345 [3:0][4:0]; assign o3 = i3; assign o34 = i34; assign o345 = i345; endmodule verilator-4.038/test_regress/t/t_time_sc_sec.out0000664000177100017500000000022413702133370022016 0ustar wsnyderwsnyder Warning: (W516) default time unit changed to time resolution Time scale of t is 1s / 1s [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-4.038/test_regress/t/t_math_imm.v0000664000177100017500000000624113702133370020777 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // Example module to create problem. // // generate a 64 bit value with bits // [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 // [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 // all other bits zero. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [7:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [63:0] HighLogicImm; // From example of example.v wire [63:0] LogicImm; // From example of example.v wire [63:0] LowLogicImm; // From example of example.v // End of automatics wire [5:0] LowMaskSel_Top = crc[5:0]; wire [5:0] LowMaskSel_Bot = crc[5:0]; wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]}; wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]}; example example (/*AUTOINST*/ // Outputs .LogicImm (LogicImm[63:0]), .LowLogicImm (LowLogicImm[63:0]), .HighLogicImm (HighLogicImm[63:0]), // Inputs .LowMaskSel_Top (LowMaskSel_Top[5:0]), .HighMaskSel_Top (HighMaskSel_Top[5:0]), .LowMaskSel_Bot (LowMaskSel_Bot[5:0]), .HighMaskSel_Bot (HighMaskSel_Bot[5:0])); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc, LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot, LowLogicImm, HighLogicImm, LogicImm); `endif if (cyc==0) begin // Single case crc <= 8'h0; sum <= 64'h0; end else if (cyc==1) begin // Setup crc <= 8'hed; sum <= 64'h0; end else if (cyc<90) begin sum <= {sum[62:0],sum[63]} ^ LogicImm; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum); if (crc !== 8'b00111000) $stop; if (sum !== 64'h58743ffa61e41075) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module example (/*AUTOARG*/ // Outputs LogicImm, LowLogicImm, HighLogicImm, // Inputs LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot ); input [5:0] LowMaskSel_Top, HighMaskSel_Top; input [5:0] LowMaskSel_Bot, HighMaskSel_Bot; output [63:0] LogicImm; output [63:0] LowLogicImm, HighLogicImm; wire [63:0] LowLogicImm, HighLogicImm; /* verilator lint_off UNSIGNED */ /* verilator lint_off CMPCONST */ genvar i; generate for (i=0;i<64;i=i+1) begin : MaskVal if (i >= 32) begin assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]); assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]); end else begin assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]); assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]); end end endgenerate /* verilator lint_on UNSIGNED */ /* verilator lint_on CMPCONST */ assign LogicImm = LowLogicImm & HighLogicImm; endmodule verilator-4.038/test_regress/t/t_class_dead.v0000664000177100017500000000106613702133367021274 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class EmptyClass_Dead; endclass module Mod_Dead; class ModClass_Dead; int memberb_dead; endclass endmodule //TODO dead check with class extends module t (/*AUTOARG*/); generate if (0) begin Mod_Dead cell_dead(); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_repeat_bad.pl0000775000177100017500000000107413702133370022470 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_ena.v0000664000177100017500000000164413702133370021127 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // verilator tracing_off integer b_trace_off; // verilator tracing_on integer c_trace_on; real r; // verilator tracing_off sub sub (); // verilator tracing_on always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; b_trace_off <= cyc; c_trace_on <= b_trace_off; r <= r + 0.1; if (cyc==4) begin if (c_trace_on != 2) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module sub; integer inside_sub = 0; endmodule verilator-4.038/test_regress/t/t_sys_writemem.gold3.mem0000664000177100017500000000132013631173020023241 0ustar wsnyderwsnyder00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 400437654321276543211765432107654321abcdef10 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 400a37654321276543211765432107654321abcdef11 400b37654321276543211765432107654321abcdef12 400c37654321276543211765432107654321abcdef13 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 verilator-4.038/test_regress/t/t_interface_down_inlcd.pl0000775000177100017500000000125513702133370023515 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_C +define+INLINE_D'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_unit.v0000664000177100017500000000071213702133370021173 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 task tsk(output tfo); tfo = 1'b0; endtask module t (/*AUTOARG*/ // Outputs to ); output reg to[2:0]; integer i = 0; initial begin tsk(to[i]); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_altera_lpm.v0000664000177100017500000072121613631173020021327 0ustar wsnyderwsnyder//------------------------------------------------------------------------- // This Verilog file was developed by Altera Corporation. It may be // freely copied and/or distributed at no cost. Any persons using this // file for any purpose do so at their own risk, and are responsible for // the results of such use. Altera Corporation does not guarantee that // this file is complete, correct, or fit for any particular purpose. // NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must // accompany any copy of this file. //------------------------------------------------------------------------ // // Quartus Prime 16.1.0 Build 196 10/24/2016 // //------------------------------------------------------------------------ // LPM Synthesizable Models (Support string type generic) // These models are based on LPM version 220 (EIA-IS103 October 1998). //------------------------------------------------------------------------ // //----------------------------------------------------------------------------- // Assumptions: // // 1. The default value for LPM_SVALUE, LPM_AVALUE, LPM_PVALUE, and // LPM_STRENGTH is string UNUSED. // //----------------------------------------------------------------------------- // Verilog Language Issues: // // Two dimensional ports are not supported. Modules with two dimensional // ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH) // bits wide. // //----------------------------------------------------------------------------- //START_MODULE_NAME------------------------------------------------------------ // // Module Name : LPM_MEMORY_INITIALIZATION // // Description : Common function to read intel-hex format data file with // extension .hex and creates the equivalent verilog format // data file with extension .ver. // // Limitation : Supports only record type '00'(data record), '01'(end of // file record) and '02'(extended segment address record). // // Results expected: Creates the verilog format data file with extension .ver // and return the name of the file. // //END_MODULE_NAME-------------------------------------------------------------- //See also: https://github.com/twosigma/verilator_support // verilator lint_off COMBDLY // verilator lint_off INITIALDLY // verilator lint_off MULTIDRIVEN // verilator lint_off UNSIGNED // verilator lint_off WIDTH // BEGINNING OF MODULE `timescale 1 ps / 1 ps `define LPM_TRUE 1 `define LPM_FALSE 0 `define LPM_NULL 0 `define LPM_EOF -1 `define LPM_MAX_NAME_SZ 128 `define LPM_MAX_WIDTH 256 `define LPM_COLON ":" `define LPM_DOT "." `define LPM_NEWLINE "\n" `define LPM_CARRIAGE_RETURN 8'h0D `define LPM_SPACE " " `define LPM_TAB "\t" `define LPM_OPEN_BRACKET "[" `define LPM_CLOSE_BRACKET "]" `define LPM_OFFSET 9 `define LPM_H10 8'h10 `define LPM_H10000 20'h10000 `define LPM_AWORD 8 `define LPM_MASK15 32'h000000FF `define LPM_EXT_STR "ver" `define LPM_PERCENT "%" `define LPM_MINUS "-" `define LPM_SEMICOLON ";" `define LPM_EQUAL "=" // MODULE DECLARATION module LPM_MEMORY_INITIALIZATION; /****************************************************************/ /* convert uppercase character values to lowercase. */ /****************************************************************/ function [8:1] tolower; input [8:1] given_character; reg [8:1] conv_char; begin if ((given_character >= 65) && (given_character <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 begin conv_char = given_character + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set tolower = conv_char; end else tolower = given_character; end endfunction /****************************************************************/ /* Read in Altera-mif format data to verilog format data. */ /****************************************************************/ task convert_mif2ver; input[`LPM_MAX_NAME_SZ*8 : 1] in_file; input width; output [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [`LPM_MAX_NAME_SZ*8 : 1] in_file; reg [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [`LPM_MAX_NAME_SZ*8 : 1] buffer; reg [`LPM_MAX_WIDTH : 0] memory_data1, memory_data2; reg [8 : 1] c; reg [3 : 0] hex, tmp_char; reg [24 : 1] address_radix, data_radix; reg get_width; reg get_depth; reg get_data_radix; reg get_address_radix; reg width_found; reg depth_found; reg data_radix_found; reg address_radix_found; reg get_address_data_pairs; reg get_address; reg get_data; reg display_address; reg invalid_address; reg get_start_address; reg get_end_address; reg done; reg error_status; reg first_rec; reg last_rec; integer width; integer memory_width, memory_depth; integer value; integer ifp, ofp, r, r2; integer i, j, k, m, n; integer off_addr, nn, address, tt, cc, aah, aal, dd, sum ; integer start_address, end_address; integer line_no; integer character_count; integer comment_with_percent_found; integer comment_with_double_minus_found; begin done = `LPM_FALSE; error_status = `LPM_FALSE; first_rec = `LPM_FALSE; last_rec = `LPM_FALSE; comment_with_percent_found = `LPM_FALSE; comment_with_double_minus_found = `LPM_FALSE; off_addr= 0; nn= 0; address = 0; start_address = 0; end_address = 0; tt= 0; cc= 0; aah= 0; aal= 0; dd= 0; sum = 0; line_no = 1; c = 0; hex = 0; value = 0; buffer = ""; character_count = 0; memory_width = 0; memory_depth = 0; memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}}; memory_data2 = {(`LPM_MAX_WIDTH+1) {1'b0}}; address_radix = "hex"; data_radix = "hex"; get_width = `LPM_FALSE; get_depth = `LPM_FALSE; get_data_radix = `LPM_FALSE; get_address_radix = `LPM_FALSE; width_found = `LPM_FALSE; depth_found = `LPM_FALSE; data_radix_found = `LPM_FALSE; address_radix_found = `LPM_FALSE; get_address_data_pairs = `LPM_FALSE; display_address = `LPM_FALSE; invalid_address = `LPM_FALSE; get_start_address = `LPM_FALSE; get_end_address = `LPM_FALSE; if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) out_file = in_file; else begin ifp = $fopen(in_file, "r"); if (ifp == `LPM_NULL) begin $display("ERROR: cannot read %0s.", in_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end out_file = in_file; if((out_file[4*8 : 1] == ".mif") || (out_file[4*8 : 1] == ".MIF")) out_file[3*8 : 1] = `LPM_EXT_STR; else begin $display("ERROR: Invalid input file name %0s. Expecting file with .mif extension and Altera-mif data format.", in_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end if (!done) begin ofp = $fopen(out_file, "w"); if (ofp == `LPM_NULL) begin $display("ERROR : cannot write %0s.", out_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end end while((!done) && (!error_status)) begin : READER r = $fgetc(ifp); if (r == `LPM_EOF) begin // to do : add more checking on whether a particular assigment(width, depth, memory/address) are mising if(!first_rec) begin error_status = `LPM_TRUE; $display("WARNING: %0s, Intel-hex data file is empty.", in_file); $display ("Time: %0t Instance: %m", $time); end else if (!get_address_data_pairs) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end else if(!last_rec) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing `end` statement.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end done = `LPM_TRUE; end else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) begin if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE)) begin get_address_data_pairs = `LPM_TRUE; get_address = `LPM_TRUE; buffer = ""; end else if (buffer == "content") begin // continue to next character end else if (buffer != "") begin // found invalid syntax in the particular line. error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); disable READER; end line_no = line_no +1; end else if ((r == `LPM_SPACE) || (r == `LPM_TAB)) begin // continue to next character; end else if (r == `LPM_PERCENT) begin // Ignore all the characters which which is part of comment. r = $fgetc(ifp); while ((r != `LPM_PERCENT) && (r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN)) begin r = $fgetc(ifp); end if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) begin line_no = line_no +1; if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE)) begin get_address_data_pairs = `LPM_TRUE; get_address = `LPM_TRUE; buffer = ""; end end end else if (r == `LPM_MINUS) begin r = $fgetc(ifp); if (r == `LPM_MINUS) begin // Ignore all the characters which which is part of comment. r = $fgetc(ifp); while ((r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN)) begin r = $fgetc(ifp); end if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) begin line_no = line_no +1; if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE)) begin get_address_data_pairs = `LPM_TRUE; get_address = `LPM_TRUE; buffer = ""; end end end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end else if (r == `LPM_EQUAL) begin if (buffer == "width") begin if (width_found == `LPM_FALSE) begin get_width = `LPM_TRUE; buffer = ""; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Width has already been specified once.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if (buffer == "depth") begin get_depth = `LPM_TRUE; buffer = ""; end else if (buffer == "data_radix") begin get_data_radix = `LPM_TRUE; buffer = ""; end else if (buffer == "address_radix") begin get_address_radix = `LPM_TRUE; buffer = ""; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Unknown setting (%0s).", in_file, line_no, buffer); $display("Time: %0t Instance: %m", $time); end end else if (r == `LPM_COLON) begin if (!get_address_data_pairs) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end else if (invalid_address == `LPM_TRUE) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end begin get_address = `LPM_FALSE; get_data = `LPM_TRUE; display_address = `LPM_TRUE; end end else if (r == `LPM_DOT) begin r = $fgetc(ifp); if (r == `LPM_DOT) begin if (get_start_address == `LPM_TRUE) begin start_address = address; address = 0; get_start_address = `LPM_FALSE; get_end_address = `LPM_TRUE; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end else if (r == `LPM_OPEN_BRACKET) begin get_start_address = `LPM_TRUE; end else if (r == `LPM_CLOSE_BRACKET) begin if (get_end_address == `LPM_TRUE) begin end_address = address; address = 0; get_end_address = `LPM_FALSE; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end else if (r == `LPM_SEMICOLON) begin if (get_width == `LPM_TRUE) begin width_found = `LPM_TRUE; memory_width = value; value = 0; get_width = `LPM_FALSE; end else if (get_depth == `LPM_TRUE) begin depth_found = `LPM_TRUE; memory_depth = value; value = 0; get_depth = `LPM_FALSE; end else if (get_data_radix == `LPM_TRUE) begin data_radix_found = `LPM_TRUE; get_data_radix = `LPM_FALSE; if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") || (buffer == "hex")) begin data_radix = buffer[24 : 1]; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid assignment (%0s) to data_radix.", in_file, line_no, buffer); $display("Time: %0t Instance: %m", $time); end buffer = ""; end else if (get_address_radix == `LPM_TRUE) begin address_radix_found = `LPM_TRUE; get_address_radix = `LPM_FALSE; if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") || (buffer == "hex")) begin address_radix = buffer[24 : 1]; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid assignment (%0s) to address radix.", in_file, line_no, buffer); $display("Time: %0t Instance: %m", $time); end buffer = ""; end else if (buffer == "end") begin if (get_address_data_pairs == `LPM_TRUE) begin last_rec = `LPM_TRUE; buffer = ""; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if (get_data == `LPM_TRUE) begin get_address = `LPM_TRUE; get_data = `LPM_FALSE; buffer = ""; character_count = 0; if (start_address != end_address) begin for (address = start_address; address <= end_address; address = address+1) begin $fdisplay(ofp,"@%0h", address); for (i = memory_width -1; i >= 0; i = i-1 ) begin hex[(i % 4)] = memory_data1[i]; if ((i % 4) == 0) begin $fwrite(ofp, "%0h", hex); hex = 0; end end $fwrite(ofp, "\n"); end start_address = 0; end_address = 0; address = 0; hex = 0; memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}}; end else begin if (display_address == `LPM_TRUE) begin $fdisplay(ofp,"@%0h", address); display_address = `LPM_FALSE; end for (i = memory_width -1; i >= 0; i = i-1 ) begin hex[(i % 4)] = memory_data1[i]; if ((i % 4) == 0) begin $fwrite(ofp, "%0h", hex); hex = 0; end end $fwrite(ofp, "\n"); address = 0; hex = 0; memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}}; end end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid assigment.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if ((get_width == `LPM_TRUE) || (get_depth == `LPM_TRUE)) begin if ((r >= "0") && (r <= "9")) value = (value * 10) + (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid assignment to width/depth.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if (get_address == `LPM_TRUE) begin if (address_radix == "hex") begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else if ((r >= "A") && (r <= "F")) value = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) value = 10 + (r - 'h61); else begin invalid_address = `LPM_TRUE; end address = (address * 16) + value; end else if ((address_radix == "dec")) begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else begin invalid_address = `LPM_TRUE; end address = (address * 10) + value; end else if (address_radix == "uns") begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else begin invalid_address = `LPM_TRUE; end address = (address * 10) + value; end else if (address_radix == "bin") begin if ((r >= "0") && (r <= "1")) value = (r - 'h30); else begin invalid_address = `LPM_TRUE; end address = (address * 2) + value; end else if (address_radix == "oct") begin if ((r >= "0") && (r <= "7")) value = (r - 'h30); else begin invalid_address = `LPM_TRUE; end address = (address * 8) + value; end if ((r >= 65) && (r <= 90)) c = tolower(r); else c = r; {tmp_char,buffer} = {buffer, c}; end else if (get_data == `LPM_TRUE) begin character_count = character_count +1; if (data_radix == "hex") begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else if ((r >= "A") && (r <= "F")) value = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) value = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 16) + value; end else if ((data_radix == "dec")) begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 10) + value; end else if (data_radix == "uns") begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 10) + value; end else if (data_radix == "bin") begin if ((r >= "0") && (r <= "1")) value = (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 2) + value; end else if (data_radix == "oct") begin if ((r >= "0") && (r <= "7")) value = (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 8) + value; end end else begin first_rec = `LPM_TRUE; if ((r >= 65) && (r <= 90)) c = tolower(r); else c = r; {tmp_char,buffer} = {buffer, c}; end end $fclose(ifp); $fclose(ofp); end end endtask // convert_mif2ver /****************************************************************/ /* Read in Intel-hex format data to verilog format data. */ /* Intel-hex format :nnaaaaattddddcc */ /****************************************************************/ task convert_hex2ver; input[`LPM_MAX_NAME_SZ*8 : 1] in_file; input width; output [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [`LPM_MAX_NAME_SZ*8 : 1] in_file; reg [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [8:1] c; reg [3:0] hex, tmp_char; reg done; reg error_status; reg first_rec; reg last_rec; integer width; integer ifp, ofp, r, r2; integer i, j, k, m, n; integer off_addr, nn, aaaa, tt, cc, aah, aal, dd, sum ; integer line_no; begin done = `LPM_FALSE; error_status = `LPM_FALSE; first_rec = `LPM_FALSE; last_rec = `LPM_FALSE; off_addr= 0; nn= 0; aaaa= 0; tt= 0; cc= 0; aah= 0; aal= 0; dd= 0; sum = 0; line_no = 1; c = 0; hex = 0; if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) out_file = in_file; else begin ifp = $fopen(in_file, "r"); if (ifp == `LPM_NULL) begin $display("ERROR: cannot read %0s.", in_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end out_file = in_file; if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX")) out_file[3*8 : 1] = `LPM_EXT_STR; else begin $display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end if (!done) begin ofp = $fopen(out_file, "w"); if (ofp == `LPM_NULL) begin $display("ERROR : cannot write %0s.", out_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end end while((!done) && (!error_status)) begin : READER r = $fgetc(ifp); if (r == `LPM_EOF) begin if(!first_rec) begin error_status = `LPM_TRUE; $display("WARNING: %0s, Intel-hex data file is empty.", in_file); $display ("Time: %0t Instance: %m", $time); end else if(!last_rec) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if (r == `LPM_COLON) begin first_rec = `LPM_TRUE; nn= 0; aaaa= 0; tt= 0; cc= 0; aah= 0; aal= 0; dd= 0; sum = 0; // get record length bytes for (i = 0; i < 2; i = i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) nn = (nn * 16) + (r - 'h30); else if ((r >= "A") && (r <= "F")) nn = (nn * 16) + 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) nn = (nn * 16) + 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end // get address bytes for (i = 0; i < 4; i = i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end aaaa = (aaaa * 16) + hex; if (i < 2) aal = (aal * 16) + hex; else aah = (aah * 16) + hex; end // get record type bytes for (i = 0; i < 2; i = i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) tt = (tt * 16) + (r - 'h30); else if ((r >= "A") && (r <= "F")) tt = (tt * 16) + 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) tt = (tt * 16) + 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end if((tt == 2) && (nn != 2) ) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end else begin // get the sum of all the bytes for record length, address and record types sum = nn + aah + aal + tt ; // check the record type case(tt) // normal_record 8'h00 : begin first_rec = `LPM_TRUE; i = 0; k = width / `LPM_AWORD; if ((width % `LPM_AWORD) != 0) k = k + 1; // k = no. of bytes per entry. while (i < nn) begin $fdisplay(ofp,"@%0h", (aaaa + off_addr)); for (j = 1; j <= k; j = j +1) begin if ((k - j +1) > nn) begin for(m = 1; m <= 2; m= m+1) begin if((((k-j)*8) + ((3-m)*4) - width) < 4) $fwrite(ofp, "0"); end end else begin // get the data bytes for(m = 1; m <= 2; m= m+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end if((((k-j)*8) + ((3-m)*4) - width) < 4) $fwrite(ofp, "%h", hex); dd = (dd * 16) + hex; if(m % 2 == 0) begin sum = sum + dd; dd = 0; end end end end $fwrite(ofp, "\n"); i = i + k; aaaa = aaaa + 1; end // end of while (i < nn) end // last record 8'h01: begin last_rec = `LPM_TRUE; done = `LPM_TRUE; end // address base record 8'h02: begin off_addr= 0; // get the extended segment address record for(i = 1; i <= (nn*2); i= i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end off_addr = (off_addr * `LPM_H10) + hex; dd = (dd * 16) + hex; if(i % 2 == 0) begin sum = sum + dd; dd = 0; end end off_addr = off_addr * `LPM_H10; end // address base record 8'h03: // get the start segment address record for(i = 1; i <= (nn*2); i= i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end dd = (dd * 16) + hex; if(i % 2 == 0) begin sum = sum + dd; dd = 0; end end // address base record 8'h04: begin off_addr= 0; // get the extended linear address record for(i = 1; i <= (nn*2); i= i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end off_addr = (off_addr * `LPM_H10) + hex; dd = (dd * 16) + hex; if(i % 2 == 0) begin sum = sum + dd; dd = 0; end end off_addr = off_addr * `LPM_H10000; end // address base record 8'h05: // get the start linear address record for(i = 1; i <= (nn*2); i= i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end dd = (dd * 16) + hex; if(i % 2 == 0) begin sum = sum + dd; dd = 0; end end default: begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end endcase // get the checksum bytes for (i = 0; i < 2; i = i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) cc = (cc * 16) + (r - 'h30); else if ((r >= "A") && (r <= "F")) cc = 10 + (cc * 16) + (r - 'h41); else if ((r >= "a") && (r <= "f")) cc = 10 + (cc * 16) + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end // Perform check sum. if(((~sum+1)& `LPM_MASK15) != cc) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end end else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) begin line_no = line_no +1; end else if (r == `LPM_SPACE) begin // continue to next character; end else begin error_status = `LPM_TRUE; $display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end end $fclose(ifp); $fclose(ofp); end end endtask // convert_hex2ver task convert_to_ver_file; input[`LPM_MAX_NAME_SZ*8 : 1] in_file; input width; output [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [`LPM_MAX_NAME_SZ*8 : 1] in_file; reg [`LPM_MAX_NAME_SZ*8 : 1] out_file; integer width; begin if((in_file[4*8 : 1] == ".hex") || (in_file[4*8 : 1] == ".HEX") || (in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) convert_hex2ver(in_file, width, out_file); else if((in_file[4*8 : 1] == ".mif") || (in_file[4*8 : 1] == ".MIF")) convert_mif2ver(in_file, width, out_file); else begin $display("ERROR: Invalid input file name %0s. Expecting file with .hex extension (with Intel-hex data format) or .mif extension (with Altera-mif data format).", in_file); $display("Time: %0t Instance: %m", $time); end end endtask // convert_to_ver_file endmodule // LPM_MEMORY_INITIALIZATION //START_MODULE_NAME------------------------------------------------------------ // // Module Name : LPM_HINT_EVALUATION // // Description : Common function to grep the value of altera specific parameters // within the lpm_hint parameter. // // Limitation : No error checking to check whether the content of the lpm_hint // is valid or not. // // Results expected: If the target parameter found, return the value of the parameter. // Otherwise, return empty string. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module LPM_HINT_EVALUATION; // FUNCTON DECLARATION // This function will search through the string (given string) to look for a match for the // a given parameter(compare_param_name). It will return the value for the given parameter. function [8*200:1] GET_PARAMETER_VALUE; input [8*200:1] given_string; // string to be searched input [8*50:1] compare_param_name; // parameter name to be looking for in the given_string. integer param_value_char_count; // to indicate current character count in the param_value integer param_name_char_count; // to indicate current character count in the param_name integer white_space_count; reg extract_param_value; // if 1 mean extracting parameters value from given string reg extract_param_name; // if 1 mean extracting parameters name from given string reg param_found; // to indicate whether compare_param_name have been found in the given_string reg include_white_space; // if 1, include white space in the parameter value reg [8*200:1] reg_string; // to store the value of the given string reg [8*50:1] param_name; // to store parameter name reg [8*20:1] param_value; // to store parameter value reg [8:1] tmp; // to get the value of the current byte begin reg_string = given_string; param_value_char_count = 0; param_name_char_count =0; extract_param_value = 1; extract_param_name = 0; param_found = 0; include_white_space = 0; white_space_count = 0; tmp = reg_string[8:1]; // checking every bytes of the reg_string from right to left. while ((tmp != 0 ) && (param_found != 1)) begin tmp = reg_string[8:1]; //if tmp != ' ' or should include white space (trailing white space are ignored) if((tmp != 32) || (include_white_space == 1)) begin if(tmp == 32) begin white_space_count = 1; end else if(tmp == 61) // if tmp = '=' begin extract_param_value = 0; extract_param_name = 1; // subsequent bytes should be part of param_name include_white_space = 0; // ignore the white space (if any) between param_name and '=' white_space_count = 0; param_value = param_value >> (8 * (20 - param_value_char_count)); param_value_char_count = 0; end else if (tmp == 44) // if tmp = ',' begin extract_param_value = 1; // subsequent bytes should be part of param_value extract_param_name = 0; param_name = param_name >> (8 * (50 - param_name_char_count)); param_name_char_count = 0; if(param_name == compare_param_name) param_found = 1; // the compare_param_name have been found in the reg_string end else begin if(extract_param_value == 1) begin param_value_char_count = param_value_char_count + white_space_count + 1; include_white_space = 1; if(white_space_count > 0) begin param_value = {8'b100000, param_value[20*8:9]}; white_space_count = 0; end param_value = {tmp, param_value[20*8:9]}; end else if(extract_param_name == 1) begin param_name = {tmp, param_name[50*8:9]}; param_name_char_count = param_name_char_count + 1; end end end reg_string = reg_string >> 8; // shift 1 byte to the right end // for the case whether param_name is the left most part of the reg_string if(extract_param_name == 1) begin param_name = param_name >> (8 * (50 - param_name_char_count)); if(param_name == compare_param_name) param_found = 1; end if (param_found == 1) GET_PARAMETER_VALUE = param_value; // return the value of the parameter been looking for else GET_PARAMETER_VALUE = ""; // return empty string if parameter not found end endfunction endmodule // LPM_HINT_EVALUATION // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module LPM_DEVICE_FAMILIES; function IS_FAMILY_CYCLONE; input[8*20:1] device; reg is_cyclone; begin if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) is_cyclone = 1; else is_cyclone = 0; IS_FAMILY_CYCLONE = is_cyclone; end endfunction //IS_FAMILY_CYCLONE function IS_FAMILY_MAX3000A; input[8*20:1] device; reg is_max3000a; begin if ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a")) is_max3000a = 1; else is_max3000a = 0; IS_FAMILY_MAX3000A = is_max3000a; end endfunction //IS_FAMILY_MAX3000A function IS_FAMILY_MAX7000A; input[8*20:1] device; reg is_max7000a; begin if ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a")) is_max7000a = 1; else is_max7000a = 0; IS_FAMILY_MAX7000A = is_max7000a; end endfunction //IS_FAMILY_MAX7000A function IS_FAMILY_MAX7000AE; input[8*20:1] device; reg is_max7000ae; begin if ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae")) is_max7000ae = 1; else is_max7000ae = 0; IS_FAMILY_MAX7000AE = is_max7000ae; end endfunction //IS_FAMILY_MAX7000AE function IS_FAMILY_MAX7000B; input[8*20:1] device; reg is_max7000b; begin if ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b")) is_max7000b = 1; else is_max7000b = 0; IS_FAMILY_MAX7000B = is_max7000b; end endfunction //IS_FAMILY_MAX7000B function IS_FAMILY_MAX7000S; input[8*20:1] device; reg is_max7000s; begin if ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s")) is_max7000s = 1; else is_max7000s = 0; IS_FAMILY_MAX7000S = is_max7000s; end endfunction //IS_FAMILY_MAX7000S function IS_FAMILY_STRATIXGX; input[8*20:1] device; reg is_stratixgx; begin if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) is_stratixgx = 1; else is_stratixgx = 0; IS_FAMILY_STRATIXGX = is_stratixgx; end endfunction //IS_FAMILY_STRATIXGX function IS_FAMILY_STRATIX; input[8*20:1] device; reg is_stratix; begin if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) is_stratix = 1; else is_stratix = 0; IS_FAMILY_STRATIX = is_stratix; end endfunction //IS_FAMILY_STRATIX function FEATURE_FAMILY_BASE_STRATIX; input[8*20:1] device; reg var_family_base_stratix; begin if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) ) var_family_base_stratix = 1; else var_family_base_stratix = 0; FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix; end endfunction //FEATURE_FAMILY_BASE_STRATIX function FEATURE_FAMILY_BASE_CYCLONE; input[8*20:1] device; reg var_family_base_cyclone; begin if (IS_FAMILY_CYCLONE(device) ) var_family_base_cyclone = 1; else var_family_base_cyclone = 0; FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone; end endfunction //FEATURE_FAMILY_BASE_CYCLONE function FEATURE_FAMILY_MAX; input[8*20:1] device; reg var_family_max; begin if ((device == "MAX5000") || IS_FAMILY_MAX3000A(device) || (device == "MAX7000") || IS_FAMILY_MAX7000A(device) || IS_FAMILY_MAX7000AE(device) || (device == "MAX7000E") || IS_FAMILY_MAX7000S(device) || IS_FAMILY_MAX7000B(device) || (device == "MAX9000") ) var_family_max = 1; else var_family_max = 0; FEATURE_FAMILY_MAX = var_family_max; end endfunction //FEATURE_FAMILY_MAX function IS_VALID_FAMILY; input[8*20:1] device; reg is_valid; begin if (((device == "Arria 10") || (device == "ARRIA 10") || (device == "arria 10") || (device == "Arria10") || (device == "ARRIA10") || (device == "arria10") || (device == "Arria VI") || (device == "ARRIA VI") || (device == "arria vi") || (device == "ArriaVI") || (device == "ARRIAVI") || (device == "arriavi") || (device == "Night Fury") || (device == "NIGHT FURY") || (device == "night fury") || (device == "nightfury") || (device == "NIGHTFURY") || (device == "Arria 10 (GX/SX/GT)") || (device == "ARRIA 10 (GX/SX/GT)") || (device == "arria 10 (gx/sx/gt)") || (device == "Arria10(GX/SX/GT)") || (device == "ARRIA10(GX/SX/GT)") || (device == "arria10(gx/sx/gt)") || (device == "Arria 10 (GX)") || (device == "ARRIA 10 (GX)") || (device == "arria 10 (gx)") || (device == "Arria10(GX)") || (device == "ARRIA10(GX)") || (device == "arria10(gx)") || (device == "Arria 10 (SX)") || (device == "ARRIA 10 (SX)") || (device == "arria 10 (sx)") || (device == "Arria10(SX)") || (device == "ARRIA10(SX)") || (device == "arria10(sx)") || (device == "Arria 10 (GT)") || (device == "ARRIA 10 (GT)") || (device == "arria 10 (gt)") || (device == "Arria10(GT)") || (device == "ARRIA10(GT)") || (device == "arria10(gt)")) || ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite")) || ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha")) || ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz")) || ((device == "Arria V GZ") || (device == "ARRIA V GZ") || (device == "arria v gz") || (device == "ArriaVGZ") || (device == "ARRIAVGZ") || (device == "arriavgz")) || ((device == "Arria V") || (device == "ARRIA V") || (device == "arria v") || (device == "Arria V (GT/GX)") || (device == "ARRIA V (GT/GX)") || (device == "arria v (gt/gx)") || (device == "ArriaV(GT/GX)") || (device == "ARRIAV(GT/GX)") || (device == "arriav(gt/gx)") || (device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V (GT/GX/ST/SX)") || (device == "ARRIA V (GT/GX/ST/SX)") || (device == "arria v (gt/gx/st/sx)") || (device == "ArriaV(GT/GX/ST/SX)") || (device == "ARRIAV(GT/GX/ST/SX)") || (device == "arriav(gt/gx/st/sx)") || (device == "Arria V (GT)") || (device == "ARRIA V (GT)") || (device == "arria v (gt)") || (device == "ArriaV(GT)") || (device == "ARRIAV(GT)") || (device == "arriav(gt)") || (device == "Arria V (GX)") || (device == "ARRIA V (GX)") || (device == "arria v (gx)") || (device == "ArriaV(GX)") || (device == "ARRIAV(GX)") || (device == "arriav(gx)") || (device == "Arria V (ST)") || (device == "ARRIA V (ST)") || (device == "arria v (st)") || (device == "ArriaV(ST)") || (device == "ARRIAV(ST)") || (device == "arriav(st)") || (device == "Arria V (SX)") || (device == "ARRIA V (SX)") || (device == "arria v (sx)") || (device == "ArriaV(SX)") || (device == "ARRIAV(SX)") || (device == "arriav(sx)")) || ((device == "BS") || (device == "bs")) || ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan") || (device == "CycloneII") || (device == "CYCLONEII") || (device == "cycloneii")) || ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie")) || ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii")) || ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive")) || ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray")) || ((device == "Cyclone V") || (device == "CYCLONE V") || (device == "cyclone v") || (device == "CycloneV") || (device == "CYCLONEV") || (device == "cyclonev") || (device == "Cyclone V (GT/GX/E/SX)") || (device == "CYCLONE V (GT/GX/E/SX)") || (device == "cyclone v (gt/gx/e/sx)") || (device == "CycloneV(GT/GX/E/SX)") || (device == "CYCLONEV(GT/GX/E/SX)") || (device == "cyclonev(gt/gx/e/sx)") || (device == "Cyclone V (E/GX/GT/SX/SE/ST)") || (device == "CYCLONE V (E/GX/GT/SX/SE/ST)") || (device == "cyclone v (e/gx/gt/sx/se/st)") || (device == "CycloneV(E/GX/GT/SX/SE/ST)") || (device == "CYCLONEV(E/GX/GT/SX/SE/ST)") || (device == "cyclonev(e/gx/gt/sx/se/st)") || (device == "Cyclone V (E)") || (device == "CYCLONE V (E)") || (device == "cyclone v (e)") || (device == "CycloneV(E)") || (device == "CYCLONEV(E)") || (device == "cyclonev(e)") || (device == "Cyclone V (GX)") || (device == "CYCLONE V (GX)") || (device == "cyclone v (gx)") || (device == "CycloneV(GX)") || (device == "CYCLONEV(GX)") || (device == "cyclonev(gx)") || (device == "Cyclone V (GT)") || (device == "CYCLONE V (GT)") || (device == "cyclone v (gt)") || (device == "CycloneV(GT)") || (device == "CYCLONEV(GT)") || (device == "cyclonev(gt)") || (device == "Cyclone V (SX)") || (device == "CYCLONE V (SX)") || (device == "cyclone v (sx)") || (device == "CycloneV(SX)") || (device == "CYCLONEV(SX)") || (device == "cyclonev(sx)") || (device == "Cyclone V (SE)") || (device == "CYCLONE V (SE)") || (device == "cyclone v (se)") || (device == "CycloneV(SE)") || (device == "CYCLONEV(SE)") || (device == "cyclonev(se)") || (device == "Cyclone V (ST)") || (device == "CYCLONE V (ST)") || (device == "cyclone v (st)") || (device == "CycloneV(ST)") || (device == "CYCLONEV(ST)") || (device == "cyclonev(st)")) || ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) || ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion")) || ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx")) || ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)")) || ((device == "MAX 10") || (device == "max 10") || (device == "MAX 10 FPGA") || (device == "max 10 fpga") || (device == "Zippleback") || (device == "ZIPPLEBACK") || (device == "zippleback") || (device == "MAX10") || (device == "max10") || (device == "MAX 10 (DA/DF/DC/SA/SC)") || (device == "max 10 (da/df/dc/sa/sc)") || (device == "MAX10(DA/DF/DC/SA/SC)") || (device == "max10(da/df/dc/sa/sc)") || (device == "MAX 10 (DA)") || (device == "max 10 (da)") || (device == "MAX10(DA)") || (device == "max10(da)") || (device == "MAX 10 (DF)") || (device == "max 10 (df)") || (device == "MAX10(DF)") || (device == "max10(df)") || (device == "MAX 10 (DC)") || (device == "max 10 (dc)") || (device == "MAX10(DC)") || (device == "max10(dc)") || (device == "MAX 10 (SA)") || (device == "max 10 (sa)") || (device == "MAX10(SA)") || (device == "max10(sa)") || (device == "MAX 10 (SC)") || (device == "max 10 (sc)") || (device == "MAX10(SC)") || (device == "max10(sc)")) || ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami")) || ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade")) || ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a")) || ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a")) || ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae")) || ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b")) || ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s")) || ((device == "Stratix 10") || (device == "STRATIX 10") || (device == "stratix 10") || (device == "Stratix10") || (device == "STRATIX10") || (device == "stratix10") || (device == "nadder") || (device == "NADDER") || (device == "Stratix 10 (GX/SX)") || (device == "STRATIX 10 (GX/SX)") || (device == "stratix 10 (gx/sx)") || (device == "Stratix10(GX/SX)") || (device == "STRATIX10(GX/SX)") || (device == "stratix10(gx/sx)") || (device == "Stratix 10 (GX)") || (device == "STRATIX 10 (GX)") || (device == "stratix 10 (gx)") || (device == "Stratix10(GX)") || (device == "STRATIX10(GX)") || (device == "stratix10(gx)") || (device == "Stratix 10 (SX)") || (device == "STRATIX 10 (SX)") || (device == "stratix 10 (sx)") || (device == "Stratix10(SX)") || (device == "STRATIX10(SX)") || (device == "stratix10(sx)")) || ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) || ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx")) || ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong")) || ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii")) || ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)")) || ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GT)") || (device == "STRATIX V (GT)") || (device == "stratix v (gt)") || (device == "StratixV(GT)") || (device == "STRATIXV(GT)") || (device == "stratixv(gt)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GS/GT)") || (device == "STRATIX V (GS/GT)") || (device == "stratix v (gs/gt)") || (device == "StratixV(GS/GT)") || (device == "STRATIXV(GS/GT)") || (device == "stratixv(gs/gt)") || (device == "Stratix V (GT/GX)") || (device == "STRATIX V (GT/GX)") || (device == "stratix v (gt/gx)") || (device == "StratixV(GT/GX)") || (device == "STRATIXV(GT/GX)") || (device == "stratixv(gt/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)") || (device == "Stratix V (GT/GS)") || (device == "STRATIX V (GT/GS)") || (device == "stratix v (gt/gs)") || (device == "StratixV(GT/GS)") || (device == "STRATIXV(GT/GS)") || (device == "stratixv(gt/gs)") || (device == "Stratix V (GX/GT)") || (device == "STRATIX V (GX/GT)") || (device == "stratix v (gx/gt)") || (device == "StratixV(GX/GT)") || (device == "STRATIXV(GX/GT)") || (device == "stratixv(gx/gt)") || (device == "Stratix V (GS/GT/GX)") || (device == "STRATIX V (GS/GT/GX)") || (device == "stratix v (gs/gt/gx)") || (device == "Stratix V (GS/GX/GT)") || (device == "STRATIX V (GS/GX/GT)") || (device == "stratix v (gs/gx/gt)") || (device == "Stratix V (GT/GS/GX)") || (device == "STRATIX V (GT/GS/GX)") || (device == "stratix v (gt/gs/gx)") || (device == "Stratix V (GT/GX/GS)") || (device == "STRATIX V (GT/GX/GS)") || (device == "stratix v (gt/gx/gs)") || (device == "Stratix V (GX/GS/GT)") || (device == "STRATIX V (GX/GS/GT)") || (device == "stratix v (gx/gs/gt)") || (device == "Stratix V (GX/GT/GS)") || (device == "STRATIX V (GX/GT/GS)") || (device == "stratix v (gx/gt/gs)") || (device == "StratixV(GS/GT/GX)") || (device == "STRATIXV(GS/GT/GX)") || (device == "stratixv(gs/gt/gx)") || (device == "StratixV(GS/GX/GT)") || (device == "STRATIXV(GS/GX/GT)") || (device == "stratixv(gs/gx/gt)") || (device == "StratixV(GT/GS/GX)") || (device == "STRATIXV(GT/GS/GX)") || (device == "stratixv(gt/gs/gx)") || (device == "StratixV(GT/GX/GS)") || (device == "STRATIXV(GT/GX/GS)") || (device == "stratixv(gt/gx/gs)") || (device == "StratixV(GX/GS/GT)") || (device == "STRATIXV(GX/GS/GT)") || (device == "stratixv(gx/gs/gt)") || (device == "StratixV(GX/GT/GS)") || (device == "STRATIXV(GX/GT/GS)") || (device == "stratixv(gx/gt/gs)") || (device == "Stratix V (GS/GT/GX/E)") || (device == "STRATIX V (GS/GT/GX/E)") || (device == "stratix v (gs/gt/gx/e)") || (device == "StratixV(GS/GT/GX/E)") || (device == "STRATIXV(GS/GT/GX/E)") || (device == "stratixv(gs/gt/gx/e)") || (device == "Stratix V (E)") || (device == "STRATIX V (E)") || (device == "stratix v (e)") || (device == "StratixV(E)") || (device == "STRATIXV(E)") || (device == "stratixv(e)")) || ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) || ((device == "eFPGA 28 HPM") || (device == "EFPGA 28 HPM") || (device == "efpga 28 hpm") || (device == "eFPGA28HPM") || (device == "EFPGA28HPM") || (device == "efpga28hpm") || (device == "Bedrock") || (device == "BEDROCK") || (device == "bedrock"))) is_valid = 1; else is_valid = 0; IS_VALID_FAMILY = is_valid; end endfunction // IS_VALID_FAMILY endmodule // LPM_DEVICE_FAMILIES //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_constant // // Description : Parameterized constant generator megafunction. lpm_constant // may be useful for convert a parameter into a constant. // // Limitation : n/a // // Results expected: Value specified by the argument to LPM_CVALUE. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_constant ( result // Value specified by the argument to LPM_CVALUE. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the result[] port. (Required) parameter lpm_cvalue = 0; // Constant value to be driven out on the // result[] port. (Required) parameter lpm_strength = "UNUSED"; parameter lpm_type = "lpm_constant"; parameter lpm_hint = "UNUSED"; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; // INTERNAL REGISTERS DECLARATION reg[32:0] int_value; // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end int_value = lpm_cvalue; end // CONTINOUS ASSIGNMENT assign result = int_value[lpm_width-1:0]; endmodule // lpm_constant //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_inv // // Description : Parameterized inverter megafunction. // // Limitation : n/a // // Results expected: Inverted value of input data // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_inv ( data, // Data input to the lpm_inv. (Required) result // inverted result. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and result[] ports. (Required) parameter lpm_type = "lpm_inv"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] result; // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end end // ALWAYS CONSTRUCT BLOCK always @(data) result = ~data; endmodule // lpm_inv //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_and // // Description : Parameterized AND gate. This megafunction takes in data inputs // for a number of AND gates. // // Limitation : n/a // // Results expected: Each result[] bit is the result of each AND gate. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_and ( data, // Data input to the AND gate. (Required) result // Result of the AND operators. (Required) ); // GLOBAL PARAMETER DECLARATION // Width of the data[][] and result[] ports. Number of AND gates. (Required) parameter lpm_width = 1; // Number of inputs to each AND gate. Number of input buses. (Required) parameter lpm_size = 1; parameter lpm_type = "lpm_and"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [(lpm_size * lpm_width)-1:0] data; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] result_tmp; // LOCAL INTEGER DECLARATION integer i; integer j; integer k; // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_size <= 0) begin $display("Value of lpm_size parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end end // ALWAYS CONSTRUCT BLOCK always @(data) begin for (i=0; i 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end // CONTINOUS ASSIGNMENT assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result; endmodule // lpm_mux // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_decode // // Description : Parameterized decoder megafunction. // // Limitation : n/a // // Results expected: Decoded output. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_decode ( data, // Data input. Treated as an unsigned binary encoded number. (Required) enable, // Enable. All outputs low when not active. clock, // Clock for pipelined usage. aclr, // Asynchronous clear for pipelined usage. clken, // Clock enable for pipelined usage. eq // Decoded output. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] port, or the // input value to be decoded. (Required) parameter lpm_decodes = 1 << lpm_width; // Number of explicit decoder outputs. (Required) parameter lpm_pipeline = 0; // Number of Clock cycles of latency parameter lpm_type = "lpm_decode"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input enable; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output [lpm_decodes-1:0] eq; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_decodes-1:0] eq_pipe [(lpm_pipeline+1):0]; reg [lpm_decodes-1:0] tmp_eq; // LOCAL INTEGER DECLARATION integer i; integer pipe_ptr; // INTERNAL TRI DECLARATION tri1 enable; tri0 clock; tri0 aclr; tri1 clken; wire i_clock; wire i_clken; wire i_aclr; wire i_enable; buf (i_clock, clock); buf (i_clken, clken); buf (i_aclr, aclr); buf (i_enable, enable); // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_decodes <= 0) begin $display("Value of lpm_decodes parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_decodes > (1 << lpm_width)) begin $display("Value of lpm_decodes parameter must be less or equal to 2^lpm_width (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_pipeline < 0) begin $display("Value of lpm_pipeline parameter must be greater or equal to 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(data or i_enable) begin tmp_eq = {lpm_decodes{1'b0}}; if (i_enable) tmp_eq[data] = 1'b1; end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) begin for (i = 0; i <= lpm_pipeline; i = i + 1) eq_pipe[i] <= {lpm_decodes{1'b0}}; pipe_ptr <= 0; end else if (clken == 1'b1) begin eq_pipe[pipe_ptr] <= tmp_eq; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end assign eq = (lpm_pipeline > 0) ? eq_pipe[pipe_ptr] : tmp_eq; endmodule // lpm_decode // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_clshift // // Description : Parameterized combinatorial logic shifter or barrel shifter // megafunction. // // Limitation : n/a // // Results expected: Return the shifted data and underflow/overflow status bit. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_clshift ( data, // Data to be shifted. (Required) distance, // Number of positions to shift data[] in the direction specified // by the direction port. (Required) direction, // Direction of shift. Low = left (toward the MSB), // high = right (toward the LSB). clock, // Clock for pipelined usage. aclr, // Asynchronous clear for pipelined usage. clken, // Clock enable for pipelined usage. result, // Shifted data. (Required) underflow, // Logical or arithmetic underflow. overflow // Logical or arithmetic overflow. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and result[] ports. Must be // greater than 0 (Required) parameter lpm_widthdist = 1; // Width of the distance[] input port. (Required) parameter lpm_shifttype = "LOGICAL"; // Type of shifting operation to be performed. parameter lpm_pipeline = 0; // Number of Clock cycles of latency parameter lpm_type = "lpm_clshift"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input [lpm_widthdist-1:0] distance; input direction; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; output underflow; output overflow; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] ONES; reg [lpm_width-1:0] ZEROS; reg [lpm_width-1:0] tmp_result; reg tmp_underflow; reg tmp_overflow; reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0]; reg [(lpm_pipeline+1):0] overflow_pipe; reg [(lpm_pipeline+1):0] underflow_pipe; // LOCAL INTEGER DECLARATION integer i; integer i1; integer pipe_ptr; // INTERNAL TRI DECLARATION tri0 direction; tri0 clock; tri0 aclr; tri1 clken; wire i_direction; wire i_clock; wire i_clken; wire i_aclr; buf (i_direction, direction); buf (i_clock, clock); buf (i_clken, clken); buf (i_aclr, aclr); // FUNCTON DECLARATION // Perform logival shift operation function [lpm_width+1:0] LogicShift; input [lpm_width-1:0] data; input [lpm_widthdist-1:0] shift_num; input direction; reg [lpm_width-1:0] tmp_buf; reg underflow; reg overflow; begin tmp_buf = data; overflow = 1'b0; underflow = 1'b0; if ((direction) && (shift_num > 0)) // shift right begin tmp_buf = data >> shift_num; if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS))) underflow = 1'b1; end else if (shift_num > 0) // shift left begin tmp_buf = data << shift_num; if ((data != ZEROS) && ((shift_num >= lpm_width) || ((data >> (lpm_width-shift_num)) != ZEROS))) overflow = 1'b1; end LogicShift = {overflow,underflow,tmp_buf[lpm_width-1:0]}; end endfunction // LogicShift // Perform Arithmetic shift operation function [lpm_width+1:0] ArithShift; input [lpm_width-1:0] data; input [lpm_widthdist-1:0] shift_num; input direction; reg [lpm_width-1:0] tmp_buf; reg underflow; reg overflow; integer i; integer i1; begin tmp_buf = data; overflow = 1'b0; underflow = 1'b0; if (shift_num < lpm_width) begin if ((direction) && (shift_num > 0)) // shift right begin if (data[lpm_width-1] == 1'b0) // positive number begin tmp_buf = data >> shift_num; if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS))) underflow = 1'b1; end else // negative number begin tmp_buf = (data >> shift_num) | (ONES << (lpm_width - shift_num)); if ((data != ONES) && ((shift_num >= lpm_width-1) || (tmp_buf == ONES))) underflow = 1'b1; end end else if (shift_num > 0) // shift left begin tmp_buf = data << shift_num; for (i=lpm_width-1; i >= lpm_width-shift_num; i=i-1) begin if(data[i-1] != data[lpm_width-1]) overflow = 1'b1; end end end else // shift_num >= lpm_width begin if (direction) begin for (i=0; i < lpm_width; i=i+1) tmp_buf[i] = data[lpm_width-1]; underflow = 1'b1; end else begin tmp_buf = {lpm_width{1'b0}}; if (data != ZEROS) begin overflow = 1'b1; end end end ArithShift = {overflow,underflow,tmp_buf[lpm_width-1:0]}; end endfunction // ArithShift // Perform rotate shift operation function [lpm_width+1:0] RotateShift; input [lpm_width-1:0] data; input [lpm_widthdist-1:0] shift_num; input direction; reg [lpm_width-1:0] tmp_buf; begin tmp_buf = data; if ((direction) && (shift_num > 0)) // shift right tmp_buf = (data >> shift_num) | (data << (lpm_width - shift_num)); else if (shift_num > 0) // shift left tmp_buf = (data << shift_num) | (data >> (lpm_width - shift_num)); RotateShift = {2'bx, tmp_buf[lpm_width-1:0]}; end endfunction // RotateShift // INITIAL CONSTRUCT BLOCK initial begin if ((lpm_shifttype != "LOGICAL") && (lpm_shifttype != "ARITHMETIC") && (lpm_shifttype != "ROTATE") && (lpm_shifttype != "UNUSED")) // non-LPM 220 standard begin $display("Error! LPM_SHIFTTYPE value must be \"LOGICAL\", \"ARITHMETIC\", or \"ROTATE\"."); $display("Time: %0t Instance: %m", $time); end if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthdist <= 0) begin $display("Value of lpm_widthdist parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end for (i=0; i < lpm_width; i=i+1) begin ONES[i] = 1'b1; ZEROS[i] = 1'b0; end for (i = 0; i <= lpm_pipeline; i = i + 1) begin result_pipe[i] = ZEROS; overflow_pipe[i] = 1'b0; underflow_pipe[i] = 1'b0; end tmp_result = ZEROS; tmp_underflow = 1'b0; tmp_overflow = 1'b0; pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(data or i_direction or distance) begin if ((lpm_shifttype == "LOGICAL") || (lpm_shifttype == "UNUSED")) {tmp_overflow, tmp_underflow, tmp_result} = LogicShift(data, distance, i_direction); else if (lpm_shifttype == "ARITHMETIC") {tmp_overflow, tmp_underflow, tmp_result} = ArithShift(data, distance, i_direction); else if (lpm_shifttype == "ROTATE") {tmp_overflow, tmp_underflow, tmp_result} = RotateShift(data, distance, i_direction); end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) begin for (i1 = 0; i1 <= lpm_pipeline; i1 = i1 + 1) begin result_pipe[i1] <= {lpm_width{1'b0}}; overflow_pipe[i1] <= 1'b0; underflow_pipe[i1] <= 1'b0; end pipe_ptr <= 0; end else if (i_clken == 1'b1) begin result_pipe[pipe_ptr] <= tmp_result; overflow_pipe[pipe_ptr] <= tmp_overflow; underflow_pipe[pipe_ptr] <= tmp_underflow; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result; assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow; assign underflow = (lpm_pipeline > 0) ? underflow_pipe[pipe_ptr] : tmp_underflow; endmodule // lpm_clshift //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_add_sub // // Description : Parameterized adder/subtractor megafunction. // // Limitation : n/a // // Results expected: If performs as adder, the result will be dataa[]+datab[]+cin. // If performs as subtractor, the result will be dataa[]-datab[]+cin-1. // Also returns carry out bit and overflow status bit. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_add_sub ( dataa, // Augend/Minuend datab, // Addend/Subtrahend cin, // Carry-in to the low-order bit. add_sub, // If the signal is high, the operation = dataa[]+datab[]+cin. // If the signal is low, the operation = dataa[]-datab[]+cin-1. clock, // Clock for pipelined usage. aclr, // Asynchronous clear for pipelined usage. clken, // Clock enable for pipelined usage. result, // dataa[]+datab[]+cin or dataa[]-datab[]+cin-1 cout, // Carry-out (borrow-in) of the MSB. overflow // Result exceeds available precision. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the dataa[],datab[], and result[] ports. parameter lpm_representation = "SIGNED"; // Type of addition performed parameter lpm_direction = "UNUSED"; // Specify the operation of the lpm_add_sub function parameter lpm_pipeline = 0; // Number of Clock cycles of latency parameter lpm_type = "lpm_add_sub"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] dataa; input [lpm_width-1:0] datab; input cin; input add_sub; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; output cout; output overflow; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0]; reg [(lpm_pipeline+1):0] cout_pipe; reg [(lpm_pipeline+1):0] overflow_pipe; reg tmp_cout; reg tmp_overflow; reg [lpm_width-1:0] tmp_result; reg i_cin; // LOCAL INTEGER DECLARATION integer borrow; integer i; integer pipe_ptr; // INTERNAL TRI DECLARATION tri1 i_add_sub; tri0 i_aclr; tri1 i_clken; tri0 i_clock; // INITIAL CONSTRUCT BLOCK initial begin // check if lpm_width < 0 if (lpm_width <= 0) begin $display("Error! LPM_WIDTH must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_direction != "ADD") && (lpm_direction != "SUB") && (lpm_direction != "UNUSED") && // non-LPM 220 standard (lpm_direction != "DEFAULT")) // non-LPM 220 standard begin $display("Error! LPM_DIRECTION value must be \"ADD\" or \"SUB\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_representation != "SIGNED") && (lpm_representation != "UNSIGNED")) begin $display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_pipeline < 0) begin $display("Error! LPM_PIPELINE must be greater than or equal to 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end for (i = 0; i <= (lpm_pipeline+1); i = i + 1) begin result_pipe[i] = 'b0; cout_pipe[i] = 1'b0; overflow_pipe[i] = 1'b0; end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(cin or dataa or datab or i_add_sub) begin i_cin = 1'b0; borrow = 1'b0; // cout is the same for both signed and unsign representation. if ((lpm_direction == "ADD") || ((i_add_sub == 1) && ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) begin i_cin = (cin === 1'bz) ? 0 : cin; {tmp_cout, tmp_result} = dataa + datab + i_cin; tmp_overflow = tmp_cout; end else if ((lpm_direction == "SUB") || ((i_add_sub == 0) && ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) begin i_cin = (cin === 1'bz) ? 1 : cin; borrow = (~i_cin) ? 1 : 0; {tmp_overflow, tmp_result} = dataa - datab - borrow; tmp_cout = (dataa >= (datab+borrow))?1:0; end if (lpm_representation == "SIGNED") begin // perform the addtion or subtraction operation if ((lpm_direction == "ADD") || ((i_add_sub == 1) && ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) begin tmp_result = dataa + datab + i_cin; tmp_overflow = ((dataa[lpm_width-1] == datab[lpm_width-1]) && (dataa[lpm_width-1] != tmp_result[lpm_width-1])) ? 1 : 0; end else if ((lpm_direction == "SUB") || ((i_add_sub == 0) && ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) begin tmp_result = dataa - datab - borrow; tmp_overflow = ((dataa[lpm_width-1] != datab[lpm_width-1]) && (dataa[lpm_width-1] != tmp_result[lpm_width-1])) ? 1 : 0; end end end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) begin for (i = 0; i <= (lpm_pipeline+1); i = i + 1) begin result_pipe[i] <= {lpm_width{1'b0}}; cout_pipe[i] <= 1'b0; overflow_pipe[i] <= 1'b0; end pipe_ptr <= 0; end else if (i_clken == 1) begin result_pipe[pipe_ptr] <= tmp_result; cout_pipe[pipe_ptr] <= tmp_cout; overflow_pipe[pipe_ptr] <= tmp_overflow; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end // CONTINOUS ASSIGNMENT assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result; assign cout = (lpm_pipeline > 0) ? cout_pipe[pipe_ptr] : tmp_cout; assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow; assign i_clock = clock; assign i_aclr = aclr; assign i_clken = clken; assign i_add_sub = add_sub; endmodule // lpm_add_sub // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_compare // // Description : Parameterized comparator megafunction. The comparator will // compare between data[] and datab[] and return the status of // comparation for the following operation. // 1) dataa[] < datab[]. // 2) dataa[] == datab[]. // 3) dataa[] > datab[]. // 4) dataa[] >= datab[]. // 5) dataa[] != datab[]. // 6) dataa[] <= datab[]. // // Limitation : n/a // // Results expected: Return status bits of the comparision between dataa[] and // datab[]. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_compare ( dataa, // Value to be compared to datab[]. (Required) datab, // Value to be compared to dataa[]. (Required) clock, // Clock for pipelined usage. aclr, // Asynchronous clear for pipelined usage. clken, // Clock enable for pipelined usage. // One of the following ports must be present. alb, // High (1) if dataa[] < datab[]. aeb, // High (1) if dataa[] == datab[]. agb, // High (1) if dataa[] > datab[]. aleb, // High (1) if dataa[] <= datab[]. aneb, // High (1) if dataa[] != datab[]. ageb // High (1) if dataa[] >= datab[]. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the dataa[] and datab[] ports. (Required) parameter lpm_representation = "UNSIGNED"; // Type of comparison performed: // "SIGNED", "UNSIGNED" parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency // associated with the alb, aeb, agb, ageb, aleb, // or aneb output. parameter lpm_type = "lpm_compare"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] dataa; input [lpm_width-1:0] datab; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output alb; output aeb; output agb; output aleb; output aneb; output ageb; // INTERNAL REGISTERS DECLARATION reg [lpm_pipeline+1:0] alb_pipe; reg [lpm_pipeline+1:0] aeb_pipe; reg [lpm_pipeline+1:0] agb_pipe; reg [lpm_pipeline+1:0] aleb_pipe; reg [lpm_pipeline+1:0] aneb_pipe; reg [lpm_pipeline+1:0] ageb_pipe; reg tmp_alb; reg tmp_aeb; reg tmp_agb; reg tmp_aleb; reg tmp_aneb; reg tmp_ageb; // LOCAL INTEGER DECLARATION integer i; integer pipe_ptr; // INTERNAL TRI DECLARATION tri0 aclr; tri0 clock; tri1 clken; wire i_aclr; wire i_clock; wire i_clken; buf (i_aclr, aclr); buf (i_clock, clock); buf (i_clken, clken); // INITIAL CONSTRUCT BLOCK initial begin if ((lpm_representation != "SIGNED") && (lpm_representation != "UNSIGNED")) begin $display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK // get the status of comparison always @(dataa or datab) begin tmp_aeb = (dataa == datab); tmp_aneb = (dataa != datab); if ((lpm_representation == "SIGNED") && ((dataa[lpm_width-1] ^ datab[lpm_width-1]) == 1)) begin // create latency tmp_alb = (dataa > datab); tmp_agb = (dataa < datab); tmp_aleb = (dataa >= datab); tmp_ageb = (dataa <= datab); end else begin // create latency tmp_alb = (dataa < datab); tmp_agb = (dataa > datab); tmp_aleb = (dataa <= datab); tmp_ageb = (dataa >= datab); end end // pipelining process always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) // reset all variables begin for (i = 0; i <= (lpm_pipeline + 1); i = i + 1) begin aeb_pipe[i] <= 1'b0; agb_pipe[i] <= 1'b0; alb_pipe[i] <= 1'b0; aleb_pipe[i] <= 1'b0; aneb_pipe[i] <= 1'b0; ageb_pipe[i] <= 1'b0; end pipe_ptr <= 0; end else if (i_clken == 1) begin alb_pipe[pipe_ptr] <= tmp_alb; aeb_pipe[pipe_ptr] <= tmp_aeb; agb_pipe[pipe_ptr] <= tmp_agb; aleb_pipe[pipe_ptr] <= tmp_aleb; aneb_pipe[pipe_ptr] <= tmp_aneb; ageb_pipe[pipe_ptr] <= tmp_ageb; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end // CONTINOUS ASSIGNMENT assign alb = (lpm_pipeline > 0) ? alb_pipe[pipe_ptr] : tmp_alb; assign aeb = (lpm_pipeline > 0) ? aeb_pipe[pipe_ptr] : tmp_aeb; assign agb = (lpm_pipeline > 0) ? agb_pipe[pipe_ptr] : tmp_agb; assign aleb = (lpm_pipeline > 0) ? aleb_pipe[pipe_ptr] : tmp_aleb; assign aneb = (lpm_pipeline > 0) ? aneb_pipe[pipe_ptr] : tmp_aneb; assign ageb = (lpm_pipeline > 0) ? ageb_pipe[pipe_ptr] : tmp_ageb; endmodule // lpm_compare //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_mult // // Description : Parameterized multiplier megafunction. // // Limitation : n/a // // Results expected: dataa[] * datab[] + sum[]. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_mult ( dataa, // Multiplicand. (Required) datab, // Multiplier. (Required) sum, // Partial sum. aclr, // Asynchronous clear for pipelined usage. sclr, // Synchronous clear for pipelined usage. clock, // Clock for pipelined usage. clken, // Clock enable for pipelined usage. result // result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB. ); // GLOBAL PARAMETER DECLARATION parameter lpm_widtha = 1; // Width of the dataa[] port. (Required) parameter lpm_widthb = 1; // Width of the datab[] port. (Required) parameter lpm_widthp = 1; // Width of the result[] port. (Required) parameter lpm_widths = 1; // Width of the sum[] port. (Required) parameter lpm_representation = "UNSIGNED"; // Type of multiplication performed parameter lpm_pipeline = 0; // Number of clock cycles of latency parameter lpm_type = "lpm_mult"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_widtha-1:0] dataa; input [lpm_widthb-1:0] datab; input [lpm_widths-1:0] sum; input aclr; input sclr; input clock; input clken; // OUTPUT PORT DECLARATION output [lpm_widthp-1:0] result; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_widthp-1:0] result_pipe [lpm_pipeline+1:0]; reg [lpm_widthp-1:0] i_prod; reg [lpm_widthp-1:0] t_p; reg [lpm_widths-1:0] i_prod_s; reg [lpm_widths-1:0] t_s; reg [lpm_widtha+lpm_widthb-1:0] i_prod_ab; reg [lpm_widtha-1:0] t_a; reg [lpm_widthb-1:0] t_b; reg sign_ab; reg sign_s; reg [8*5:1] input_a_is_constant; reg [8*5:1] input_b_is_constant; reg [8*lpm_widtha:1] input_a_fixed_value; reg [8*lpm_widthb:1] input_b_fixed_value; reg [lpm_widtha-1:0] dataa_fixed; reg [lpm_widthb-1:0] datab_fixed; // LOCAL INTEGER DECLARATION integer i; integer pipe_ptr; // INTERNAL WIRE DECLARATION wire [lpm_widtha-1:0] dataa_wire; wire [lpm_widthb-1:0] datab_wire; // INTERNAL TRI DECLARATION tri0 aclr; tri0 sclr; tri0 clock; tri1 clken; wire i_aclr; wire i_sclr; wire i_clock; wire i_clken; buf (i_aclr, aclr); buf (i_sclr, sclr); buf (i_clock, clock); buf (i_clken, clken); // COMPONENT INSTANTIATIONS LPM_HINT_EVALUATION eva(); // FUNCTION DECLARATION // convert string to binary bits. function integer str2bin; input [8*256:1] str; input str_width; reg [8*256:1] reg_str; reg [255:0] bin; reg [8:1] tmp; integer m; integer str_width; begin reg_str = str; for (m=0; m < str_width; m=m+1) begin tmp = reg_str[8:1]; reg_str = reg_str >> 8; case (tmp) "0" : bin[m] = 1'b0; "1" : bin[m] = 1'b1; default: bin[m] = 1'bx; endcase end str2bin = bin; end endfunction // INITIAL CONSTRUCT BLOCK initial begin // check if lpm_widtha > 0 if (lpm_widtha <= 0) begin $display("Error! lpm_widtha must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_widthb > 0 if (lpm_widthb <= 0) begin $display("Error! lpm_widthb must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_widthp > 0 if (lpm_widthp <= 0) begin $display("Error! lpm_widthp must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_widthp > 0 if (lpm_widths <= 0) begin $display("Error! lpm_widths must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check for valid lpm_rep value if ((lpm_representation != "SIGNED") && (lpm_representation != "UNSIGNED")) begin $display("Error! lpm_representation value must be \"SIGNED\" or \"UNSIGNED\".", $time); $display("Time: %0t Instance: %m", $time); $finish; end input_a_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_IS_CONSTANT"); if (input_a_is_constant == "FIXED") begin input_a_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_FIXED_VALUE"); dataa_fixed = str2bin(input_a_fixed_value, lpm_widtha); end input_b_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_IS_CONSTANT"); if (input_b_is_constant == "FIXED") begin input_b_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_FIXED_VALUE"); datab_fixed = str2bin(input_b_fixed_value, lpm_widthb); end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(dataa_wire or datab_wire or sum) begin t_a = dataa_wire; t_b = datab_wire; t_s = sum; sign_ab = 1'b0; sign_s = 1'b0; // if inputs are sign number if (lpm_representation == "SIGNED") begin sign_ab = dataa_wire[lpm_widtha-1] ^ datab_wire[lpm_widthb-1]; sign_s = sum[lpm_widths-1]; // if negative number, represent them as 2 compliment number. if (dataa_wire[lpm_widtha-1] == 1) t_a = (~dataa_wire) + 1; if (datab_wire[lpm_widthb-1] == 1) t_b = (~datab_wire) + 1; if (sum[lpm_widths-1] == 1) t_s = (~sum) + 1; end // if sum port is not used if (sum === {lpm_widths{1'bz}}) begin t_s = {lpm_widths{1'b0}}; sign_s = 1'b0; end if (sign_ab == sign_s) begin i_prod = (t_a * t_b) + t_s; i_prod_s = (t_a * t_b) + t_s; i_prod_ab = (t_a * t_b) + t_s; end else begin i_prod = (t_a * t_b) - t_s; i_prod_s = (t_a * t_b) - t_s; i_prod_ab = (t_a * t_b) - t_s; end // if dataa[] * datab[] produces negative number, compliment the result if (sign_ab) begin i_prod = (~i_prod) + 1; i_prod_s = (~i_prod_s) + 1; i_prod_ab = (~i_prod_ab) + 1; end if ((lpm_widthp < lpm_widths) || (lpm_widthp < (lpm_widtha+lpm_widthb))) for (i = 0; i < lpm_widthp; i = i + 1) i_prod[lpm_widthp-1-i] = (lpm_widths > lpm_widtha+lpm_widthb) ? i_prod_s[lpm_widths-1-i] : i_prod_ab[lpm_widtha+lpm_widthb-1-i]; end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) // clear the pipeline for result to 0 begin for (i = 0; i <= (lpm_pipeline + 1); i = i + 1) result_pipe[i] <= {lpm_widthp{1'b0}}; pipe_ptr <= 0; end else if (i_clken == 1) begin if(i_sclr) begin for (i = 0; i <= (lpm_pipeline + 1); i = i + 1) result_pipe[i] <= {lpm_widthp{1'b0}}; pipe_ptr <= 0; end else begin result_pipe[pipe_ptr] <= i_prod; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end end // CONTINOUS ASSIGNMENT assign dataa_wire = (input_a_is_constant == "FIXED") ? dataa_fixed : dataa; assign datab_wire = (input_b_is_constant == "FIXED") ? datab_fixed : datab; assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : i_prod; endmodule // lpm_mult // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_divide // // Description : Parameterized divider megafunction. This function performs a // divide operation such that denom * quotient + remain = numer // The function allows for all combinations of signed(two's // complement) and unsigned inputs. If any of the inputs is // signed, the output is signed. Otherwise the output is unsigned. // The function also allows the remainder to be specified as // always positive (in which case remain >= 0); otherwise remain // is zero or the same sign as the numerator // (this parameter is ignored in the case of purely unsigned // division). Finally the function is also pipelinable. // // Limitation : n/a // // Results expected: Return quotient and remainder. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_divide ( numer, // The numerator (Required) denom, // The denominator (Required) clock, // Clock input for pipelined usage aclr, // Asynchronous clear signal clken, // Clock enable for pipelined usage. quotient, // Quotient (Required) remain // Remainder (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_widthn = 1; // Width of the numer[] and quotient[] port. (Required) parameter lpm_widthd = 1; // Width of the denom[] and remain[] port. (Required) parameter lpm_nrepresentation = "UNSIGNED"; // The representation of numer parameter lpm_drepresentation = "UNSIGNED"; // The representation of denom parameter lpm_pipeline = 0; // Number of Clock cycles of latency parameter lpm_type = "lpm_divide"; parameter lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE"; // INPUT PORT DECLARATION input [lpm_widthn-1:0] numer; input [lpm_widthd-1:0] denom; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output [lpm_widthn-1:0] quotient; output [lpm_widthd-1:0] remain; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_widthn-1:0] quotient_pipe [lpm_pipeline+1:0]; reg [lpm_widthd-1:0] remain_pipe [lpm_pipeline+1:0]; reg [lpm_widthn-1:0] tmp_quotient; reg [lpm_widthd-1:0] tmp_remain; reg [lpm_widthn-1:0] not_numer; reg [lpm_widthn-1:0] int_numer; reg [lpm_widthd-1:0] not_denom; reg [lpm_widthd-1:0] int_denom; reg [lpm_widthn-1:0] t_numer; reg [lpm_widthn-1:0] t_q; reg [lpm_widthd-1:0] t_denom; reg [lpm_widthd-1:0] t_r; reg sign_q; reg sign_r; reg sign_n; reg sign_d; reg [8*5:1] lpm_remainderpositive; // LOCAL INTEGER DECLARATION integer i; integer rsig; integer pipe_ptr; // INTERNAL TRI DECLARATION tri0 aclr; tri0 clock; tri1 clken; wire i_aclr; wire i_clock; wire i_clken; buf (i_aclr, aclr); buf (i_clock, clock); buf (i_clken, clken); // COMPONENT INSTANTIATIONS LPM_HINT_EVALUATION eva(); // INITIAL CONSTRUCT BLOCK initial begin // check if lpm_widthn > 0 if (lpm_widthn <= 0) begin $display("Error! LPM_WIDTHN must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_widthd > 0 if (lpm_widthd <= 0) begin $display("Error! LPM_WIDTHD must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check for valid lpm_nrepresentation value if ((lpm_nrepresentation != "SIGNED") && (lpm_nrepresentation != "UNSIGNED")) begin $display("Error! LPM_NREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); $display("Time: %0t Instance: %m", $time); $finish; end // check for valid lpm_drepresentation value if ((lpm_drepresentation != "SIGNED") && (lpm_drepresentation != "UNSIGNED")) begin $display("Error! LPM_DREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); $display("Time: %0t Instance: %m", $time); $finish; end // check for valid lpm_remainderpositive value lpm_remainderpositive = eva.GET_PARAMETER_VALUE(lpm_hint, "LPM_REMAINDERPOSITIVE"); if ((lpm_remainderpositive == "TRUE") && (lpm_remainderpositive == "FALSE")) begin $display("Error! LPM_REMAINDERPOSITIVE value must be \"TRUE\" or \"FALSE\"."); $display("Time: %0t Instance: %m", $time); $finish; end for (i = 0; i <= (lpm_pipeline+1); i = i + 1) begin quotient_pipe[i] <= {lpm_widthn{1'b0}}; remain_pipe[i] <= {lpm_widthd{1'b0}}; end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(numer or denom or lpm_remainderpositive) begin sign_q = 1'b0; sign_r = 1'b0; sign_n = 1'b0; sign_d = 1'b0; t_numer = numer; t_denom = denom; if (lpm_nrepresentation == "SIGNED") if (numer[lpm_widthn-1] == 1'b1) begin t_numer = ~numer + 1; // numer is negative number sign_n = 1'b1; end if (lpm_drepresentation == "SIGNED") if (denom[lpm_widthd-1] == 1'b1) begin t_denom = ~denom + 1; // denom is negative numbrt sign_d = 1'b1; end t_q = t_numer / t_denom; // get quotient t_r = t_numer % t_denom; // get remainder sign_q = sign_n ^ sign_d; sign_r = (t_r != {lpm_widthd{1'b0}}) ? sign_n : 1'b0; // Pipeline the result tmp_quotient = (sign_q == 1'b1) ? (~t_q + 1) : t_q; tmp_remain = (sign_r == 1'b1) ? (~t_r + 1) : t_r; // Recalculate the quotient and remainder if remainder is negative number // and LPM_REMAINDERPOSITIVE=TRUE. if ((sign_r) && (lpm_remainderpositive == "TRUE")) begin tmp_quotient = tmp_quotient + ((sign_d == 1'b1) ? 1 : -1 ); tmp_remain = tmp_remain + t_denom; end end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) begin for (i = 0; i <= (lpm_pipeline+1); i = i + 1) begin quotient_pipe[i] <= {lpm_widthn{1'b0}}; remain_pipe[i] <= {lpm_widthd{1'b0}}; end pipe_ptr <= 0; end else if (i_clken) begin quotient_pipe[pipe_ptr] <= tmp_quotient; remain_pipe[pipe_ptr] <= tmp_remain; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end // CONTINOUS ASSIGNMENT assign quotient = (lpm_pipeline > 0) ? quotient_pipe[pipe_ptr] : tmp_quotient; assign remain = (lpm_pipeline > 0) ? remain_pipe[pipe_ptr] : tmp_remain; endmodule // lpm_divide // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_abs // // Description : Parameterized absolute value megafunction. This megafunction // requires the input data to be signed number. // // Limitation : n/a // // Results expected: Return absolute value of data and the overflow status // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_abs ( data, // Signed number (Required) result, // Absolute value of data[]. overflow // High if data = -2 ^ (LPM_WIDTH-1). ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and result[] ports.(Required) parameter lpm_type = "lpm_abs"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; output overflow; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] result_tmp; reg overflow; // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end end // ALWAYS CONSTRUCT BLOCK always @(data) begin result_tmp = (data[lpm_width-1] == 1) ? (~data) + 1 : data; overflow = (data[lpm_width-1] == 1) ? (result_tmp == (1<<(lpm_width-1))) : 0; end // CONTINOUS ASSIGNMENT assign result = result_tmp; endmodule // lpm_abs //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_counter // // Description : Parameterized counter megafunction. The lpm_counter // megafunction is a binary counter that features an up, // down, or up/down counter with optional synchronous or // asynchronous clear, set, and load ports. // // Limitation : n/a // // Results expected: Data output from the counter and carry-out of the MSB. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_counter ( clock, // Positive-edge-triggered clock. (Required) clk_en, // Clock enable input. Enables all synchronous activities. cnt_en, // Count enable input. Disables the count when low (0) without // affecting sload, sset, or sclr. updown, // Controls the direction of the count. High (1) = count up. // Low (0) = count down. aclr, // Asynchronous clear input. aset, // Asynchronous set input. aload, // Asynchronous load input. Asynchronously loads the counter with // the value on the data input. sclr, // Synchronous clear input. Clears the counter on the next active // clock edge. sset, // Synchronous set input. Sets the counter on the next active clock edge. sload, // Synchronous load input. Loads the counter with data[] on the next // active clock edge. data, // Parallel data input to the counter. cin, // Carry-in to the low-order bit. q, // Data output from the counter. cout, // Carry-out of the MSB. eq // Counter decode output. Active high when the counter reaches the specified // count value. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; //The number of bits in the count, or the width of the q[] // and data[] ports, if they are used. (Required) parameter lpm_direction = "UNUSED"; // Direction of the count. parameter lpm_modulus = 0; // The maximum count, plus one. parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge // of clock when sset is high. parameter lpm_pvalue = "UNUSED"; parameter lpm_port_updown = "PORT_CONNECTIVITY"; parameter lpm_type = "lpm_counter"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input clock; input clk_en; input cnt_en; input updown; input aclr; input aset; input aload; input sclr; input sset; input sload; input [lpm_width-1:0] data; input cin; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; output cout; output [15:0] eq; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] tmp_count; reg [lpm_width-1:0] adata; reg use_adata; reg tmp_updown; reg [lpm_width:0] tmp_modulus; reg [lpm_width:0] max_modulus; reg [lpm_width-1:0] svalue; reg [lpm_width-1:0] avalue; reg [lpm_width-1:0] pvalue; // INTERNAL WIRE DECLARATION wire w_updown; wire [lpm_width-1:0] final_count; // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri1 clk_en; tri1 cnt_en; tri0 aclr; tri0 aset; tri0 aload; tri0 sclr; tri0 sset; tri0 sload; tri1 cin; tri1 updown_z; wire i_clk_en; wire i_cnt_en; wire i_aclr; wire i_aset; wire i_aload; wire i_sclr; wire i_sset; wire i_sload; wire i_cin; wire i_updown; buf (i_clk_en, clk_en); buf (i_cnt_en, cnt_en); buf (i_aclr, aclr); buf (i_aset, aset); buf (i_aload, aload); buf (i_sclr, sclr); buf (i_sset, sset); buf (i_sload, sload); buf (i_cin, cin); buf (i_updown, updown_z); // TASK DECLARATION task string_to_reg; input [8*40:1] string_value; output [lpm_width-1:0] value; reg [8*40:1] reg_s; reg [8:1] digit; reg [8:1] tmp; reg [lpm_width-1:0] ivalue; integer m; begin ivalue = {lpm_width{1'b0}}; reg_s = string_value; for (m=1; m<=40; m=m+1) begin tmp = reg_s[320:313]; digit = tmp & 8'b00001111; reg_s = reg_s << 8; ivalue = ivalue * 10 + digit; end value = ivalue; end endtask // INITIAL CONSTRUCT BLOCK initial begin max_modulus = 1 << lpm_width; // check if lpm_width < 0 if (lpm_width <= 0) begin $display("Error! LPM_WIDTH must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_modulus < 0 if (lpm_modulus < 0) begin $display("Error! LPM_MODULUS must be greater or equal to 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_modulus > 1< max_modulus) begin $display("Warning! LPM_MODULUS should be within 1 to 2^LPM_WIDTH. Assuming no modulus input.\n"); $display ("Time: %0t Instance: %m", $time); end // check if lpm_direction valid if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") && (lpm_direction != "UP") && (lpm_direction != "DOWN")) begin $display("Error! LPM_DIRECTION must be \"UP\" or \"DOWN\" if used.\n"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_avalue == "UNUSED") avalue = {lpm_width{1'b1}}; else string_to_reg(lpm_avalue, avalue); if (lpm_svalue == "UNUSED") svalue = {lpm_width{1'b1}}; else string_to_reg(lpm_svalue, svalue); if (lpm_pvalue == "UNUSED") pvalue = {lpm_width{1'b0}}; else string_to_reg(lpm_pvalue, pvalue); tmp_modulus = ((lpm_modulus == 0) || (lpm_modulus > max_modulus)) ? max_modulus : lpm_modulus; tmp_count = pvalue; use_adata = 1'b0; end // NCSIM will only assigns 1'bZ to unconnected port at time 0fs + 1 // verilator lint_off STMTDLY initial #0 // verilator lint_on STMTDLY begin // // check if lpm_direction valid if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") && (updown !== 1'bz) && (lpm_port_updown == "PORT_CONNECTIVITY")) begin $display("Error! LPM_DIRECTION and UPDOWN cannot be used at the same time.\n"); $display("Time: %0t Instance: %m", $time); $finish; end end // ALWAYS CONSTRUCT BLOCK always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock) begin if (i_aclr || i_aset || i_aload) use_adata <= 1'b1; else if ($time > 0) begin if (i_clk_en) begin use_adata <= 1'b0; if (i_sclr) tmp_count <= 0; else if (i_sset) tmp_count <= svalue; else if (i_sload) tmp_count <= data; else if (i_cnt_en && i_cin) begin if (w_updown) tmp_count <= (final_count == tmp_modulus-1) ? 0 : final_count+1; else tmp_count <= (final_count == 0) ? tmp_modulus-1 : final_count-1; end else tmp_count <= final_count; end end end always @(i_aclr or i_aset or i_aload or data or avalue) begin if (i_aclr) begin adata <= 0; end else if (i_aset) begin adata <= avalue; end else if (i_aload) adata <= data; end // CONTINOUS ASSIGNMENT assign q = final_count; assign final_count = (use_adata == 1'b1) ? adata : tmp_count; assign cout = (i_cin && (((w_updown==0) && (final_count==0)) || ((w_updown==1) && ((final_count==tmp_modulus-1) || (final_count=={lpm_width{1'b1}}))) )) ? 1'b1 : 1'b0; assign updown_z = updown; assign w_updown = (lpm_port_updown == "PORT_USED") ? i_updown : (lpm_port_updown == "PORT_UNUSED") ? ((lpm_direction == "DOWN") ? 1'b0 : 1'b1) : ((((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) && (i_updown == 1)) || (lpm_direction == "UP")) ? 1'b1 : 1'b0; assign eq = {16{1'b0}}; endmodule // lpm_counter // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_latch // // Description : Parameterized latch megafunction. // // Limitation : n/a // // Results expected: Data output from the latch. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_latch ( data, // Data input to the latch. gate, // Latch enable input. High = flow-through, low = latch. (Required) aclr, // Asynchronous clear input. aset, // Asynchronous set input. aconst, q // Data output from the latch. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required) parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. parameter lpm_pvalue = "UNUSED"; parameter lpm_type = "lpm_latch"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input gate; input aclr; input aset; input aconst; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] q; reg [lpm_width-1:0] avalue; reg [lpm_width-1:0] pvalue; // INTERNAL TRI DECLARATION tri0 [lpm_width-1:0] data; tri0 aclr; tri0 aset; tri0 aconst; wire i_aclr; wire i_aset; buf (i_aclr, aclr); buf (i_aset, aset); // TASK DECLARATION task string_to_reg; input [8*40:1] string_value; output [lpm_width-1:0] value; reg [8*40:1] reg_s; reg [8:1] digit; reg [8:1] tmp; reg [lpm_width-1:0] ivalue; integer m; begin ivalue = {lpm_width{1'b0}}; reg_s = string_value; for (m=1; m<=40; m=m+1) begin tmp = reg_s[320:313]; digit = tmp & 8'b00001111; reg_s = reg_s << 8; ivalue = ivalue * 10 + digit; end value = ivalue; end endtask // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_pvalue != "UNUSED") begin string_to_reg(lpm_pvalue, pvalue); q = pvalue; end if (lpm_avalue == "UNUSED") avalue = {lpm_width{1'b1}}; else string_to_reg(lpm_avalue, avalue); end // ALWAYS CONSTRUCT BLOCK always @(data or gate or i_aclr or i_aset or avalue) begin if (i_aclr) q <= {lpm_width{1'b0}}; else if (i_aset) q <= avalue; else if (gate) q <= data; end endmodule // lpm_latch //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_ff // // Description : Parameterized flipflop megafunction. The lpm_ff function // contains features that are not available in the DFF, DFFE, // DFFEA, TFF, and TFFE primitives, such as synchronous or // asynchronous set, clear, and load inputs. // // Limitation : n/a // // Results expected: Data output from D or T flipflops. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_ff ( data, // T-type flipflop: Toggle enable // D-type flipflop: Data input clock, // Positive-edge-triggered clock. (Required) enable, // Clock enable input. aclr, // Asynchronous clear input. aset, // Asynchronous set input. aload, // Asynchronous load input. Asynchronously loads the flipflop with // the value on the data input. sclr, // Synchronous clear input. sset, // Synchronous set input. sload, // Synchronous load input. Loads the flipflop with the value on the // data input on the next active clock edge. q // Data output from D or T flipflops. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required) parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge // of clock when sset is high. parameter lpm_pvalue = "UNUSED"; parameter lpm_fftype = "DFF"; // Type of flipflop parameter lpm_type = "lpm_ff"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input clock; input enable; input aclr; input aset; input aload; input sclr; input sset; input sload ; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] tmp_q; reg [lpm_width-1:0] adata; reg use_adata; reg [lpm_width-1:0] svalue; reg [lpm_width-1:0] avalue; reg [lpm_width-1:0] pvalue; // INTERNAL WIRE DECLARATION wire [lpm_width-1:0] final_q; // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri1 [lpm_width-1:0] data; tri1 enable; tri0 sload; tri0 sclr; tri0 sset; tri0 aload; tri0 aclr; tri0 aset; wire i_enable; wire i_sload; wire i_sclr; wire i_sset; wire i_aload; wire i_aclr; wire i_aset; buf (i_enable, enable); buf (i_sload, sload); buf (i_sclr, sclr); buf (i_sset, sset); buf (i_aload, aload); buf (i_aclr, aclr); buf (i_aset, aset); // TASK DECLARATION task string_to_reg; input [8*40:1] string_value; output [lpm_width-1:0] value; reg [8*40:1] reg_s; reg [8:1] digit; reg [8:1] tmp; reg [lpm_width-1:0] ivalue; integer m; begin ivalue = {lpm_width{1'b0}}; reg_s = string_value; for (m=1; m<=40; m=m+1) begin tmp = reg_s[320:313]; digit = tmp & 8'b00001111; reg_s = reg_s << 8; ivalue = ivalue * 10 + digit; end value = ivalue; end endtask // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_fftype != "DFF") && (lpm_fftype != "TFF") && (lpm_fftype != "UNUSED")) // non-LPM 220 standard begin $display("Error! LPM_FFTYPE value must be \"DFF\" or \"TFF\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_avalue == "UNUSED") avalue = {lpm_width{1'b1}}; else string_to_reg(lpm_avalue, avalue); if (lpm_svalue == "UNUSED") svalue = {lpm_width{1'b1}}; else string_to_reg(lpm_svalue, svalue); if (lpm_pvalue == "UNUSED") pvalue = {lpm_width{1'b0}}; else string_to_reg(lpm_pvalue, pvalue); tmp_q = pvalue; use_adata = 1'b0; end // ALWAYS CONSTRUCT BLOCK always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock) begin // Asynchronous process if (i_aclr || i_aset || i_aload) use_adata <= 1'b1; else if ($time > 0) begin // Synchronous process if (i_enable) begin use_adata <= 1'b0; if (i_sclr) tmp_q <= 0; else if (i_sset) tmp_q <= svalue; else if (i_sload) // Load data tmp_q <= data; else begin if (lpm_fftype == "TFF") // toggle begin for (i = 0; i < lpm_width; i=i+1) if (data[i] == 1'b1) tmp_q[i] <= ~final_q[i]; else tmp_q[i] <= final_q[i]; end else // DFF, load data tmp_q <= data; end end end end always @(i_aclr or i_aset or i_aload or data or avalue or pvalue) begin if (i_aclr === 1'b1) adata <= {lpm_width{1'b0}}; else if (i_aclr === 1'bx) adata <= {lpm_width{1'bx}}; else if (i_aset) adata <= avalue; else if (i_aload) adata <= data; else if ((i_aclr === 1'b0) && ($time == 0)) adata <= pvalue; end // CONTINOUS ASSIGNMENT assign q = final_q; assign final_q = (use_adata == 1'b1) ? adata : tmp_q; endmodule // lpm_ff // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_shiftreg // // Description : Parameterized shift register megafunction. // // Limitation : n/a // // Results expected: Data output from the shift register and the Serial shift data output. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_shiftreg ( data, // Data input to the shift register. clock, // Positive-edge-triggered clock. (Required) enable, // Clock enable input shiftin, // Serial shift data input. load, // Synchronous parallel load. High (1): load operation; // low (0): shift operation. aclr, // Asynchronous clear input. aset, // Asynchronous set input. sclr, // Synchronous clear input. sset, // Synchronous set input. q, // Data output from the shift register. shiftout // Serial shift data output. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and q ports. (Required) parameter lpm_direction = "LEFT"; // Values are "LEFT", "RIGHT", and "UNUSED". parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge // of clock when sset is high. parameter lpm_pvalue = "UNUSED"; parameter lpm_type = "lpm_shiftreg"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input clock; input enable; input shiftin; input load; input aclr; input aset; input sclr; input sset; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; output shiftout; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] tmp_q; reg abit; reg [lpm_width-1:0] svalue; reg [lpm_width-1:0] avalue; reg [lpm_width-1:0] pvalue; // LOCAL INTEGER DECLARATION integer i; // INTERNAL WIRE DECLARATION wire tmp_shiftout; // INTERNAL TRI DECLARATION tri1 enable; tri1 shiftin; tri0 load; tri0 aclr; tri0 aset; tri0 sclr; tri0 sset; wire i_enable; wire i_shiftin; wire i_load; wire i_aclr; wire i_aset; wire i_sclr; wire i_sset; buf (i_enable, enable); buf (i_shiftin, shiftin); buf (i_load, load); buf (i_aclr, aclr); buf (i_aset, aset); buf (i_sclr, sclr); buf (i_sset, sset); // TASK DECLARATION task string_to_reg; input [8*40:1] string_value; output [lpm_width-1:0] value; reg [8*40:1] reg_s; reg [8:1] digit; reg [8:1] tmp; reg [lpm_width-1:0] ivalue; integer m; begin ivalue = {lpm_width{1'b0}}; reg_s = string_value; for (m=1; m<=40; m=m+1) begin tmp = reg_s[320:313]; digit = tmp & 8'b00001111; reg_s = reg_s << 8; ivalue = ivalue * 10 + digit; end value = ivalue; end endtask // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_direction != "LEFT") && (lpm_direction != "RIGHT") && (lpm_direction != "UNUSED")) // non-LPM 220 standard begin $display("Error! LPM_DIRECTION value must be \"LEFT\" or \"RIGHT\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_avalue == "UNUSED") avalue = {lpm_width{1'b1}}; else string_to_reg(lpm_avalue, avalue); if (lpm_svalue == "UNUSED") svalue = {lpm_width{1'b1}}; else string_to_reg(lpm_svalue, svalue); if (lpm_pvalue == "UNUSED") pvalue = {lpm_width{1'b0}}; else string_to_reg(lpm_pvalue, pvalue); tmp_q = pvalue; end // ALWAYS CONSTRUCT BLOCK always @(i_aclr or i_aset or avalue) begin if (i_aclr) tmp_q <= {lpm_width{1'b0}}; else if (i_aset) tmp_q <= avalue; end always @(posedge clock) begin if (i_aclr) tmp_q <= (i_aset) ? {lpm_width{1'bx}} : {lpm_width{1'b0}}; else if (i_aset) tmp_q <= avalue; else begin if (i_enable) begin if (i_sclr) tmp_q <= {lpm_width{1'b0}}; else if (i_sset) tmp_q <= svalue; else if (i_load) tmp_q <= data; else if (!i_load) begin if ((lpm_direction == "LEFT") || (lpm_direction == "UNUSED")) {abit,tmp_q} <= {tmp_q,i_shiftin}; else if (lpm_direction == "RIGHT") {tmp_q,abit} <= {i_shiftin,tmp_q}; end end end end // CONTINOUS ASSIGNMENT assign tmp_shiftout = (lpm_direction == "RIGHT") ? tmp_q[0] : tmp_q[lpm_width-1]; assign q = tmp_q; assign shiftout = tmp_shiftout; endmodule // lpm_shiftreg // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_ram_dq // // Description : Parameterized RAM with separate input and output ports megafunction. // lpm_ram_dq implement asynchronous memory or memory with synchronous // inputs and/or outputs. // // Limitation : n/a // // Results expected: Data output from the memory. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_ram_dq ( data, // Data input to the memory. (Required) address, // Address input to the memory. (Required) inclock, // Synchronizes memory loading. outclock, // Synchronizes q outputs from memory. we, // Write enable input. Enables write operations to the memory when high. (Required) q // Data output from the memory. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of data[] and q[] ports. (Required) parameter lpm_widthad = 1; // Width of the address port. (Required) parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory. parameter lpm_indata = "REGISTERED"; // Controls whether the data port is registered. parameter lpm_address_control = "REGISTERED"; // Controls whether the address and we ports are registered. parameter lpm_outdata = "REGISTERED"; // Controls whether the q ports are registered. parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data. parameter use_eab = "ON"; // Specified whether to use the EAB or not. parameter intended_device_family = "Stratix"; parameter lpm_type = "lpm_ram_dq"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input [lpm_widthad-1:0] address; input inclock; input outclock; input we; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] mem_data [lpm_numwords-1:0]; reg [lpm_width-1:0] tmp_q; reg [lpm_width-1:0] pdata; reg [lpm_width-1:0] in_data; reg [lpm_widthad-1:0] paddress; reg pwe; reg [lpm_width-1:0] ZEROS, ONES, UNKNOWN; `ifdef VERILATOR reg [`LPM_MAX_NAME_SZ*8:1] ram_initf; `else reg [8*256:1] ram_initf; `endif // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri0 inclock; tri0 outclock; wire i_inclock; wire i_outclock; buf (i_inclock, inclock); buf (i_outclock, outclock); // COMPONENT INSTANTIATIONS LPM_DEVICE_FAMILIES dev (); LPM_MEMORY_INITIALIZATION mem (); // FUNCTON DECLARATION // Check the validity of the address. function ValidAddress; input [lpm_widthad-1:0] paddress; begin ValidAddress = 1'b0; if (^paddress === {lpm_widthad{1'bx}}) begin $display("%t:Error! Invalid address.\n", $time); $display("Time: %0t Instance: %m", $time); end else if (paddress >= lpm_numwords) begin $display("%t:Error! Address out of bound on RAM.\n", $time); $display("Time: %0t Instance: %m", $time); end else ValidAddress = 1'b1; end endfunction // INITIAL CONSTRUCT BLOCK initial begin // Initialize the internal data register. pdata = {lpm_width{1'b0}}; paddress = {lpm_widthad{1'b0}}; pwe = 1'b0; if (lpm_width <= 0) begin $display("Error! LPM_WIDTH parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthad <= 0) begin $display("Error! LPM_WIDTHAD parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end // check for number of words out of bound if ((lpm_numwords > (1 << lpm_widthad)) || (lpm_numwords <= (1 << (lpm_widthad-1)))) begin $display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED")) begin $display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED")) begin $display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) begin $display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (dev.IS_VALID_FAMILY(intended_device_family) == 0) begin $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); $display("Time: %0t Instance: %m", $time); $finish; end for (i=0; i < lpm_width; i=i+1) begin ZEROS[i] = 1'b0; ONES[i] = 1'b1; UNKNOWN[i] = 1'bX; end for (i = 0; i < lpm_numwords; i=i+1) mem_data[i] = {lpm_width{1'b0}}; // load data to the RAM if (lpm_file != "UNUSED") begin mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf); $readmemh(ram_initf, mem_data); end tmp_q = ZEROS; end // ALWAYS CONSTRUCT BLOCK always @(posedge i_inclock) begin if (lpm_address_control == "REGISTERED") begin if ((we) && (use_eab != "ON") && (lpm_hint != "USE_EAB=ON")) begin if (lpm_indata == "REGISTERED") mem_data[address] <= data; else mem_data[address] <= pdata; end paddress <= address; pwe <= we; end if (lpm_indata == "REGISTERED") pdata <= data; end always @(data) begin if (lpm_indata == "UNREGISTERED") pdata <= data; end always @(address) begin if (lpm_address_control == "UNREGISTERED") paddress <= address; end always @(we) begin if (lpm_address_control == "UNREGISTERED") pwe <= we; end always @(pdata or paddress or pwe) begin :UNREGISTERED_INCLOCK if (ValidAddress(paddress)) begin if ((lpm_address_control == "UNREGISTERED") && (pwe)) mem_data[paddress] <= pdata; end else begin if (lpm_outdata == "UNREGISTERED") tmp_q <= {lpm_width{1'bx}}; end end always @(posedge i_outclock) begin if (lpm_outdata == "REGISTERED") begin if (ValidAddress(paddress)) tmp_q <= mem_data[paddress]; else tmp_q <= {lpm_width{1'bx}}; end end always @(i_inclock or pwe or paddress or pdata) begin if ((lpm_address_control == "REGISTERED") && (pwe)) if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) begin if (i_inclock == 1'b0) mem_data[paddress] = pdata; end end // CONTINOUS ASSIGNMENT assign q = (lpm_outdata == "UNREGISTERED") ? mem_data[paddress] : tmp_q; endmodule // lpm_ram_dq // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_ram_dp // // Description : Parameterized dual-port RAM megafunction. // // Limitation : n/a // // Results expected: Data output from the memory. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_ram_dp ( data, // Data input to the memory. (Required) rdaddress, // Read address input to the memory. (Required) wraddress, // Write address input to the memory. (Required) rdclock, // Positive-edge-triggered clock for read operation. rdclken, // Clock enable for rdclock. wrclock, // Positive-edge-triggered clock for write operation. wrclken, // Clock enable for wrclock. rden, // Read enable input. Disables reading when low (0). wren, // Write enable input. (Required) q // Data output from the memory. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required) parameter lpm_widthad = 1; // Width of the rdaddress[] and wraddress[] ports. (Required) parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory. parameter lpm_indata = "REGISTERED"; // Determines the clock used by the data port. parameter lpm_rdaddress_control = "REGISTERED"; // Determines the clock used by the rdaddress and rden ports. parameter lpm_wraddress_control = "REGISTERED"; // Determines the clock used by the wraddress and wren ports. parameter lpm_outdata = "REGISTERED"; // Determines the clock used by the q[] pxort. parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data. parameter use_eab = "ON"; // Specified whether to use the EAB or not. parameter rden_used = "TRUE"; // Specified whether to use the rden port or not. parameter intended_device_family = "Stratix"; parameter lpm_type = "lpm_ram_dp"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input [lpm_widthad-1:0] rdaddress; input [lpm_widthad-1:0] wraddress; input rdclock; input rdclken; input wrclock; input wrclken; input rden; input wren; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] mem_data [(1<= lpm_numwords) begin $display("%t:Error! Address out of bound on RAM.\n", $time); $display("Time: %0t Instance: %m", $time); end else ValidAddress = 1'b1; end endfunction // INITIAL CONSTRUCT BLOCK initial begin // Check for invalid parameters if (lpm_width < 1) begin $display("Error! lpm_width parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthad < 1) begin $display("Error! lpm_widthad parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED")) begin $display("Error! lpm_indata must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) begin $display("Error! lpm_outdata must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_wraddress_control != "REGISTERED") && (lpm_wraddress_control != "UNREGISTERED")) begin $display("Error! lpm_wraddress_control must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); end if ((lpm_rdaddress_control != "REGISTERED") && (lpm_rdaddress_control != "UNREGISTERED")) begin $display("Error! lpm_rdaddress_control must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (dev.IS_VALID_FAMILY(intended_device_family) == 0) begin $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); $display("Time: %0t Instance: %m", $time); $finish; end // Initialize mem_data i_numwords = (lpm_numwords) ? lpm_numwords : (1< 0)) i_data_reg <= data; if (lpm_wraddress_control == "REGISTERED") if ((i_inclocken == 1'b1) && ($time > 0)) begin i_wraddress_reg <= wraddress; i_wren_reg <= i_wren; end end always @(posedge i_outclock) begin if (lpm_outdata == "REGISTERED") if ((i_outclocken == 1'b1) && ($time > 0)) begin i_q_reg <= i_q_tmp; end if (lpm_rdaddress_control == "REGISTERED") if ((i_outclocken == 1'b1) && ($time > 0)) begin i_rdaddress_reg <= rdaddress; i_rden_reg <= i_rden; end end //========= // Memory //========= always @(i_data_tmp or i_wren_tmp or i_wraddress_tmp or negedge i_inclock) begin if (i_wren_tmp == 1'b1) if (ValidAddress(i_wraddress_tmp)) begin if (((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) && (lpm_wraddress_control == "REGISTERED")) begin if (i_inclock == 1'b0) mem_data[i_wraddress_tmp] <= i_data_tmp; end else mem_data[i_wraddress_tmp] <= i_data_tmp; end end always @(i_rden_tmp or i_rdaddress_tmp or mem_data[i_rdaddress_tmp]) begin if (i_rden_tmp == 1'b1) i_q_tmp = (ValidAddress(i_rdaddress_tmp)) ? mem_data[i_rdaddress_tmp] : {lpm_width{1'bx}}; end //======= // Sync //======= always @(wraddress or i_wraddress_reg) i_wraddress_tmp = (lpm_wraddress_control == "REGISTERED") ? i_wraddress_reg : wraddress; always @(rdaddress or i_rdaddress_reg) i_rdaddress_tmp = (lpm_rdaddress_control == "REGISTERED") ? i_rdaddress_reg : rdaddress; always @(i_wren or i_wren_reg) i_wren_tmp = (lpm_wraddress_control == "REGISTERED") ? i_wren_reg : i_wren; always @(i_rden or i_rden_reg) i_rden_tmp = (lpm_rdaddress_control == "REGISTERED") ? i_rden_reg : i_rden; always @(data or i_data_reg) i_data_tmp = (lpm_indata == "REGISTERED") ? i_data_reg : data; // CONTINOUS ASSIGNMENT assign q = (lpm_outdata == "REGISTERED") ? i_q_reg : i_q_tmp; endmodule // lpm_ram_dp // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_ram_io // // Description : Parameterized RAM with a single I/O port megafunction // // Limitation : This megafunction is provided only for backward // compatibility in Cyclone, Stratix, and Stratix GX designs; // instead, Altera recommends using the altsyncram // megafunction // // Results expected: Output of RAM content at bi-directional DIO. // //END_MODULE_NAME-------------------------------------------------------------- `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_ram_io ( dio, inclock, outclock, we, memenab, outenab, address ); // PARAMETER DECLARATION parameter lpm_type = "lpm_ram_io"; parameter lpm_width = 1; parameter lpm_widthad = 1; parameter lpm_numwords = 1<< lpm_widthad; parameter lpm_indata = "REGISTERED"; parameter lpm_address_control = "REGISTERED"; parameter lpm_outdata = "REGISTERED"; parameter lpm_file = "UNUSED"; parameter lpm_hint = "UNUSED"; parameter use_eab = "ON"; parameter intended_device_family = "UNUSED"; // INPUT PORT DECLARATION input [lpm_widthad-1:0] address; input inclock, outclock, we; input memenab; input outenab; // INPUT/OUTPUT PORT DECLARATION inout [lpm_width-1:0] dio; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] mem_data [lpm_numwords-1:0]; reg [lpm_width-1:0] tmp_io; reg [lpm_width-1:0] tmp_q; reg [lpm_width-1:0] pdio; reg [lpm_widthad-1:0] paddress; reg [lpm_widthad-1:0] paddress_tmp; reg pwe; `ifdef VERILATOR reg [`LPM_MAX_NAME_SZ*8:1] ram_initf; `else reg [8*256:1] ram_initf; `endif // INTERNAL WIRE DECLARATION wire [lpm_width-1:0] read_data; wire i_inclock; wire i_outclock; wire i_memenab; wire i_outenab; // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri0 inclock; tri0 outclock; tri1 memenab; tri1 outenab; // INTERNAL BUF DECLARATION buf (i_inclock, inclock); buf (i_outclock, outclock); buf (i_memenab, memenab); buf (i_outenab, outenab); // FUNCTON DECLARATION function ValidAddress; input [lpm_widthad-1:0] paddress; begin ValidAddress = 1'b0; if (^paddress === {lpm_widthad{1'bx}}) begin $display("%t:Error: Invalid address.", $time); $display("Time: %0t Instance: %m", $time); $finish; end else if (paddress >= lpm_numwords) begin $display("%t:Error: Address out of bound on RAM.", $time); $display("Time: %0t Instance: %m", $time); $finish; end else ValidAddress = 1'b1; end endfunction // COMPONENT INSTANTIATIONS LPM_MEMORY_INITIALIZATION mem (); // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Error! LPM_WIDTH parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthad <= 0) begin $display("Error! LPM_WIDTHAD parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end // check for number of words out of bound if ((lpm_numwords > (1 << lpm_widthad)) ||(lpm_numwords <= (1 << (lpm_widthad-1)))) begin $display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED")) begin $display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED")) begin $display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) begin $display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end for (i = 0; i < lpm_numwords; i=i+1) mem_data[i] = {lpm_width{1'b0}}; // Initialize input/output pwe = 1'b0; pdio = {lpm_width{1'b0}}; paddress = {lpm_widthad{1'b0}}; paddress_tmp = {lpm_widthad{1'b0}}; tmp_io = {lpm_width{1'b0}}; tmp_q = {lpm_width{1'b0}}; // load data to the RAM if (lpm_file != "UNUSED") begin mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf); $readmemh(ram_initf, mem_data); end end // ALWAYS CONSTRUCT BLOCK always @(dio) begin if (lpm_indata == "UNREGISTERED") pdio <= dio; end always @(address) begin if (lpm_address_control == "UNREGISTERED") paddress <= address; end always @(we) begin if (lpm_address_control == "UNREGISTERED") pwe <= we; end always @(posedge i_inclock) begin if (lpm_indata == "REGISTERED") pdio <= dio; if (lpm_address_control == "REGISTERED") begin paddress <= address; pwe <= we; end end always @(pdio or paddress or pwe or i_memenab) begin if (ValidAddress(paddress)) begin paddress_tmp <= paddress; if (lpm_address_control == "UNREGISTERED") if (pwe && i_memenab) mem_data[paddress] <= pdio; end else begin if (lpm_outdata == "UNREGISTERED") tmp_q <= {lpm_width{1'bx}}; end end always @(read_data) begin if (lpm_outdata == "UNREGISTERED") tmp_q <= read_data; end always @(negedge i_inclock or pdio) begin if (lpm_address_control == "REGISTERED") if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) if (pwe && i_memenab && (i_inclock == 1'b0)) mem_data[paddress] = pdio; end always @(posedge i_inclock) begin if (lpm_address_control == "REGISTERED") if ((use_eab == "OFF") && pwe && i_memenab) mem_data[paddress] <= pdio; end always @(posedge i_outclock) begin if (lpm_outdata == "REGISTERED") tmp_q <= mem_data[paddress]; end always @(i_memenab or i_outenab or tmp_q) begin if (i_memenab && i_outenab) tmp_io = tmp_q; else if ((!i_memenab) || (i_memenab && (!i_outenab))) tmp_io = {lpm_width{1'bz}}; end // CONTINOUS ASSIGNMENT assign dio = tmp_io; assign read_data = mem_data[paddress_tmp]; endmodule // lpm_ram_io //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_rom // // Description : Parameterized ROM megafunction. This megafunction is provided // only for backward compatibility in Cyclone, Stratix, and // Stratix GX designs; instead, Altera recommends using the // altsyncram megafunction. // // Limitation : This option is available for all Altera devices supported by // the Quartus II software except MAX 3000 and MAX 7000 devices. // // Results expected: Output of memory. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_rom ( address, // Address input to the memory. (Required) inclock, // Clock for input registers. outclock, // Clock for output registers. memenab, // Memory enable input. q // Output of memory. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the q[] port. (Required) parameter lpm_widthad = 1; // Width of the address[] port. (Required) parameter lpm_numwords = 0; // Number of words stored in memory. parameter lpm_address_control = "REGISTERED"; // Indicates whether the address port is registered. parameter lpm_outdata = "REGISTERED"; // Indicates whether the q and eq ports are registered. parameter lpm_file = ""; // Name of the memory file containing ROM initialization data parameter intended_device_family = "Stratix"; parameter lpm_type = "lpm_rom"; parameter lpm_hint = "UNUSED"; // LOCAL_PARAMETERS_BEGIN parameter NUM_WORDS = (lpm_numwords == 0) ? (1 << lpm_widthad) : lpm_numwords; // LOCAL_PARAMETERS_END // INPUT PORT DECLARATION input [lpm_widthad-1:0] address; input inclock; input outclock; input memenab; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] mem_data [0:NUM_WORDS-1]; reg [lpm_widthad-1:0] address_reg; reg [lpm_width-1:0] tmp_q_reg; `ifdef VERILATOR reg [`LPM_MAX_NAME_SZ*8:1] rom_initf; `else reg [8*256:1] rom_initf; `endif // INTERNAL WIRE DECLARATION wire [lpm_widthad-1:0] w_address; wire [lpm_width-1:0] w_read_data; wire i_inclock; wire i_outclock; wire i_memenab; // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri0 inclock; tri0 outclock; tri1 memenab; buf (i_inclock, inclock); buf (i_outclock, outclock); buf (i_memenab, memenab); // COMPONENT INSTANTIATIONS LPM_DEVICE_FAMILIES dev (); LPM_MEMORY_INITIALIZATION mem (); // FUNCTON DECLARATION // Check the validity of the address. function ValidAddress; input [lpm_widthad-1:0] address; begin ValidAddress = 1'b0; if (^address == {lpm_widthad{1'bx}}) begin $display("%d:Error: Invalid address.", $time); $display("Time: %0t Instance: %m", $time); $finish; end else if (address >= NUM_WORDS) begin $display("%d:Error: Address out of bound on ROM.", $time); $display("Time: %0t Instance: %m", $time); $finish; end else ValidAddress = 1'b1; end endfunction // INITIAL CONSTRUCT BLOCK initial begin // Initialize output tmp_q_reg = {lpm_width{1'b0}}; address_reg = {lpm_widthad{1'b0}}; if (lpm_width <= 0) begin $display("Error! LPM_WIDTH parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthad <= 0) begin $display("Error! LPM_WIDTHAD parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end // check for number of words out of bound if ((NUM_WORDS > (1 << lpm_widthad)) || (NUM_WORDS <= (1 << (lpm_widthad-1)))) begin $display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED")) begin $display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) begin $display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (dev.IS_VALID_FAMILY(intended_device_family) == 0) begin $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); $display("Time: %0t Instance: %m", $time); $finish; end if (dev.FEATURE_FAMILY_MAX(intended_device_family) == 1) begin $display ("Error! LPM_ROM megafunction does not support %s devices.", intended_device_family); $display("Time: %0t Instance: %m", $time); $finish; end for (i = 0; i < NUM_WORDS; i=i+1) mem_data[i] = {lpm_width{1'b0}}; // load data to the ROM if ((lpm_file == "") || (lpm_file == "UNUSED")) begin $display("Warning: LPM_ROM must have data file for initialization.\n"); $display ("Time: %0t Instance: %m", $time); end else begin mem.convert_to_ver_file(lpm_file, lpm_width, rom_initf); $readmemh(rom_initf, mem_data); end end always @(posedge i_inclock) begin if (lpm_address_control == "REGISTERED") address_reg <= address; // address port is registered end always @(w_address or w_read_data) begin if (ValidAddress(w_address)) begin if (lpm_outdata == "UNREGISTERED") // Load the output register with the contents of the memory location // pointed to by address[]. tmp_q_reg <= w_read_data; end else begin if (lpm_outdata == "UNREGISTERED") tmp_q_reg <= {lpm_width{1'bx}}; end end always @(posedge i_outclock) begin if (lpm_outdata == "REGISTERED") begin if (ValidAddress(w_address)) tmp_q_reg <= w_read_data; else tmp_q_reg <= {lpm_width{1'bx}}; end end // CONTINOUS ASSIGNMENT assign w_address = (lpm_address_control == "REGISTERED") ? address_reg : address; assign w_read_data = mem_data[w_address]; assign q = (i_memenab) ? tmp_q_reg : {lpm_width{1'bz}}; endmodule // lpm_rom // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_fifo // // Description : // // Limitation : // // Results expected: // //END_MODULE_NAME-------------------------------------------------------------- `timescale 1 ps / 1 ps module lpm_fifo ( data, clock, wrreq, rdreq, aclr, sclr, q, usedw, full, empty ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; parameter lpm_widthu = 1; parameter lpm_numwords = 2; parameter lpm_showahead = "OFF"; parameter lpm_type = "lpm_fifo"; parameter lpm_hint = ""; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input clock; input wrreq; input rdreq; input aclr; input sclr; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; output [lpm_widthu-1:0] usedw; output full; output empty; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] mem_data [(1< (1 << lpm_widthu))) begin $display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU)."); $display("Time: %0t Instance: %m", $time); $stop; end if (lpm_numwords <= (1 << (lpm_widthu - 1))) begin $display ("Error! LPM_WIDTHU is too big for the specified LPM_NUMWORDS."); $display("Time: %0t Instance: %m", $time); $stop; end overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING"); if(overflow_checking == "") overflow_checking = "ON"; else if ((overflow_checking != "ON") && (overflow_checking != "OFF")) begin $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING"); if(underflow_checking == "") underflow_checking = "ON"; else if ((underflow_checking != "ON") && (underflow_checking != "OFF")) begin $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end allow_rwcycle_when_full = eva.GET_PARAMETER_VALUE(lpm_hint, "ALLOW_RWCYCLE_WHEN_FULL"); if (allow_rwcycle_when_full == "") allow_rwcycle_when_full = "OFF"; else if ((allow_rwcycle_when_full != "ON") && (allow_rwcycle_when_full != "OFF")) begin $display ("Error! ALLOW_RWCYCLE_WHEN_FULL must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY"); if (intended_device_family == "") intended_device_family = "Stratix II"; else if (dev.IS_VALID_FAMILY(intended_device_family) == 0) begin $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); $display("Time: %0t Instance: %m", $time); $stop; end for (i = 0; i < (1<= ((1 << lpm_widthu) - 1)) begin if (lpm_showahead == "ON") tmp_q <= mem_data[0]; else tmp_q <= mem_data[read_id]; read_id <= 0; end else begin if (lpm_showahead == "ON") tmp_q <= mem_data[read_id + 1]; else tmp_q <= mem_data[read_id]; read_id <= read_id + 1; end end // WRITE operation only else if (valid_wreq) begin tmp_data <= data; empty_flag <= 1'b0; write_flag <= 1'b1; if (count_id >= (1 << lpm_widthu) - 1) count_id <= 0; else count_id <= count_id + 1; if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0)) full_flag <= 1'b1; if (lpm_showahead == "ON") tmp_q <= mem_data[read_id]; end // READ operation only else if (valid_rreq) begin full_flag <= 1'b0; if (count_id <= 0) count_id <= {lpm_widthu{1'b1}}; else count_id <= count_id - 1; if ((count_id == 1) && (full_flag == 1'b0)) empty_flag <= 1'b1; if (read_id >= ((1<= ((1 << lpm_widthu) - 1))) write_id <= 0; else write_id <= write_id + 1; end if ((lpm_showahead == "ON") && ($time > 0)) tmp_q <= ((write_flag == 1'b1) && (write_id == read_id)) ? tmp_data : mem_data[read_id]; end // @(negedge clock) // CONTINOUS ASSIGNMENT assign valid_rreq = (underflow_checking == "OFF") ? rdreq : rdreq && ~empty_flag; assign valid_wreq = (overflow_checking == "OFF") ? wrreq : (allow_rwcycle_when_full == "ON") ? wrreq && (!full_flag || rdreq) : wrreq && !full_flag; assign q = tmp_q; assign full = full_flag; assign empty = empty_flag; assign usedw = count_id; endmodule // lpm_fifo // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_fifo_dc_dffpipe // // Description : Dual Clocks FIFO // // Limitation : // // Results expected: // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_fifo_dc_dffpipe (d, clock, aclr, q); // GLOBAL PARAMETER DECLARATION parameter lpm_delay = 1; parameter lpm_width = 64; // INPUT PORT DECLARATION input [lpm_width-1:0] d; input clock; input aclr; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] dffpipe [lpm_delay:0]; reg [lpm_width-1:0] q; // LOCAL INTEGER DECLARATION integer delay; integer i; // INITIAL CONSTRUCT BLOCK initial begin delay <= lpm_delay - 1; for (i = 0; i <= lpm_delay; i = i + 1) dffpipe[i] <= 0; q <= 0; end // ALWAYS CONSTRUCT BLOCK always @(posedge aclr or posedge clock) begin if (aclr) begin for (i = 0; i <= lpm_delay; i = i + 1) dffpipe[i] <= 0; q <= 0; end else if (clock) begin if ((lpm_delay > 0) && ($time > 0)) begin `ifdef VERILATOR if (lpm_delay > 0) `else if (delay > 0) `endif begin `ifdef VERILATOR for (i = lpm_delay-1; i > 0; i = i - 1) `else for (i = delay; i > 0; i = i - 1) `endif dffpipe[i] <= dffpipe[i - 1]; q <= dffpipe[delay - 1]; end else q <= d; dffpipe[0] <= d; end end end // @(posedge aclr or posedge clock) always @(d) begin if (lpm_delay == 0) q <= d; end // @(d) endmodule // lpm_fifo_dc_dffpipe // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_fifo_dc_fefifo // // Description : Dual Clock FIFO // // Limitation : // // Results expected: // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_fifo_dc_fefifo ( usedw_in, wreq, rreq, clock, aclr, empty, full); // GLOBAL PARAMETER DECLARATION parameter lpm_widthad = 1; parameter lpm_numwords = 1; parameter underflow_checking = "ON"; parameter overflow_checking = "ON"; parameter lpm_mode = "READ"; parameter lpm_hint = ""; // INPUT PORT DECLARATION input [lpm_widthad-1:0] usedw_in; input wreq; input rreq; input clock; input aclr; // OUTPUT PORT DECLARATION output empty; output full; // INTERNAL REGISTERS DECLARATION reg [1:0] sm_empty; reg lrreq; reg i_empty; reg i_full; reg [8*5:1] i_overflow_checking; reg [8*5:1] i_underflow_checking; // LOCAL INTEGER DECLARATION integer almostfull; // COMPONENT INSTANTIATIONS LPM_HINT_EVALUATION eva(); // INITIAL CONSTRUCT BLOCK initial begin if ((lpm_mode != "READ") && (lpm_mode != "WRITE")) begin $display ("Error! LPM_MODE must be READ or WRITE."); $display("Time: %0t Instance: %m", $time); $stop; end i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING"); if (i_overflow_checking == "") begin if ((overflow_checking != "ON") && (overflow_checking != "OFF")) begin $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end else i_overflow_checking = overflow_checking; end else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF")) begin $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING"); if(i_underflow_checking == "") begin if ((underflow_checking != "ON") && (underflow_checking != "OFF")) begin $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end else i_underflow_checking = underflow_checking; end else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF")) begin $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end sm_empty <= 2'b00; i_empty <= 1'b1; i_full <= 1'b0; lrreq <= 1'b0; if (lpm_numwords >= 3) almostfull <= lpm_numwords - 3; else almostfull <= 0; end // ALWAYS CONSTRUCT BLOCK always @(posedge aclr) begin sm_empty <= 2'b00; i_empty <= 1'b1; i_full <= 1'b0; lrreq <= 1'b0; end // @(posedge aclr) always @(posedge clock) begin if (i_underflow_checking == "OFF") lrreq <= rreq; else lrreq <= rreq && ~i_empty; if (~aclr && ($time > 0)) begin if (lpm_mode == "READ") begin // verilator lint_off CASEX casex (sm_empty) // verilator lint_on CASEX // state_empty 2'b00: if (usedw_in != 0) sm_empty <= 2'b01; // state_non_empty // verilator lint_off CMPCONST 2'b01: if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq))) sm_empty <= 2'b10; // state_emptywait 2'b10: if (usedw_in > 1) sm_empty <= 2'b01; else sm_empty <= 2'b00; // verilator lint_on CMPCONST default: begin $display ("Error! Invalid sm_empty state in read mode."); $display("Time: %0t Instance: %m", $time); end endcase end // if (lpm_mode == "READ") else if (lpm_mode == "WRITE") begin // verilator lint_off CASEX casex (sm_empty) // verilator lint_on CASEX // state_empty 2'b00: if (wreq) sm_empty <= 2'b01; // state_one 2'b01: if (!wreq) sm_empty <= 2'b11; // state_non_empty 2'b11: if (wreq) sm_empty <= 2'b01; else if (usedw_in == 0) sm_empty <= 2'b00; default: begin $display ("Error! Invalid sm_empty state in write mode."); $display("Time: %0t Instance: %m", $time); end endcase end // if (lpm_mode == "WRITE") if (~aclr && (usedw_in >= almostfull) && ($time > 0)) i_full <= 1'b1; else i_full <= 1'b0; end // if (~aclr && $time > 0) end // @(posedge clock) always @(sm_empty) begin i_empty <= !sm_empty[0]; end // @(sm_empty) // CONTINOUS ASSIGNMENT assign empty = i_empty; assign full = i_full; endmodule // lpm_fifo_dc_fefifo // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_fifo_dc_async // // Description : Asynchronous Dual Clocks FIFO // // Limitation : // // Results expected: // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_fifo_dc_async ( data, rdclk, wrclk, aclr, rdreq, wrreq, rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; parameter lpm_widthu = 1; parameter lpm_numwords = 2; parameter delay_rdusedw = 1; parameter delay_wrusedw = 1; parameter rdsync_delaypipe = 3; parameter wrsync_delaypipe = 3; parameter lpm_showahead = "OFF"; parameter underflow_checking = "ON"; parameter overflow_checking = "ON"; parameter lpm_hint = "INTENDED_DEVICE_FAMILY=Stratix"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input rdclk; input wrclk; input aclr; input wrreq; input rdreq; // OUTPUT PORT DECLARATION output rdfull; output wrfull; output rdempty; output wrempty; output [lpm_widthu-1:0] rdusedw; output [lpm_widthu-1:0] wrusedw; output [lpm_width-1:0] q; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] mem_data [(1< 0)) begin i_data_tmp <= data; i_wrptr_tmp <= i_wrptr; i_wren_tmp <= w_wren; if (w_wren) begin if (~aclr && ((i_wrptr < (1< 0)) begin if (i_wren_tmp) begin mem_data[i_wrptr_tmp] <= i_data_tmp; end if (lpm_showahead == "ON") i_showahead_flag1 <= 1'b1; end end // @(negedge wrclk) always @(posedge rdclk) begin if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) || (use_eab == "OFF"))) begin if (lpm_showahead == "ON") i_q_tmp <= mem_data[0]; else i_q_tmp <= 0; end else if (rdclk && w_rden && ($time > 0)) begin if (~aclr && ((i_rdptr < (1< 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_overcmp.v0000664000177100017500000000527313702133370021533 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dout, // Inputs clk, rstn, dval0, dval1, dbgsel_w ); input clk; input rstn; input [7:0] dval0; input [7:0] dval1; input [7:0] dbgsel_w; output [7:0] dout; wire [7:0] dout = dout0 | dout1; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] dout0; // From sub0 of sub0.v wire [7:0] dout1; // From sub1 of sub1.v // End of automatics initial begin $write("*-* All Finished *-*\n"); $finish; end reg [7:0] dbgsel_msk; always_comb begin reg [7:0] mask; mask = 8'hff; dbgsel_msk = (dbgsel_w & mask); end reg [7:0] dbgsel; always @(posedge clk) begin if ((rstn == 0)) begin dbgsel <= 0; end else begin dbgsel <= dbgsel_msk; end end sub0 sub0 (/*AUTOINST*/ // Outputs .dout0 (dout0[7:0]), // Inputs .rstn (rstn), .clk (clk), .dval1 (dval1[7:0]), .dbgsel (dbgsel[7:0])); sub1 sub1 (/*AUTOINST*/ // Outputs .dout1 (dout1[7:0]), // Inputs .rstn (rstn), .clk (clk), .dval1 (dval1[7:0]), .dbgsel (dbgsel[7:0])); endmodule module sub0 ( /*AUTOARG*/ // Outputs dout0, // Inputs rstn, clk, dval1, dbgsel ); input rstn; input clk; input [7:0] dval1; input [7:0] dbgsel; output reg [7:0] dout0; reg [7:0] dbgsel_d1r; always_comb begin // verilator lint_off WIDTH if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin // verilator lint_on WIDTH dout0 = dval1; end else begin dout0 = 0; end end always @(posedge clk) begin if ((rstn == 0)) begin dbgsel_d1r <= 0; end else begin dbgsel_d1r <= dbgsel; end end endmodule module sub1 ( /*AUTOARG*/ // Outputs dout1, // Inputs rstn, clk, dval1, dbgsel ); input rstn; input clk; input [7:0] dval1; input [7:0] dbgsel; output reg [7:0] dout1; reg [7:0] dbgsel_d1r; always_comb begin // verilator lint_off WIDTH if (((dbgsel_d1r >= 334) && (dbgsel_d1r < 365))) begin // verilator lint_on WIDTH dout1 = dval1; end else begin dout1 = 0; end end always @(posedge clk) begin if ((rstn == 0)) begin dbgsel_d1r <= 0; end else begin dbgsel_d1r <= dbgsel; end end endmodule verilator-4.038/test_regress/t/t_select_little.v0000664000177100017500000000430313702133370022035 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // verilator lint_off LITENDIAN wire [10:41] sel2 = crc[31:0]; wire [10:100] sel3 = {crc[26:0],crc}; wire out20 = sel2[{1'b0,crc[3:0]} + 11]; wire [3:0] out21 = sel2[13 : 16]; wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; wire out30 = sel3[{2'b0,crc[3:0]} + 11]; wire [3:0] out31 = sel3[13 : 16]; wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; // Aggregate outputs into a single result vector wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; reg [19:50] sel1; initial begin // Path clearing // 122333445 // 826048260 sel1 = 32'h12345678; if (sel1 != 32'h12345678) $stop; if (sel1[47 : 50] != 4'h8) $stop; if (sel1[31 : 34] != 4'h4) $stop; if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33); $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h28bf65439eb12c00 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_class_forward.v0000664000177100017500000000164113702133367022042 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package P; typedef class ClsB; class ClsA; int imembera; ClsB b; endclass class ClsB; int imemberb; ClsA a; endclass endpackage module t (/*AUTOARG*/); P::ClsA ca; P::ClsB cb; initial begin // Alternate between two versions to make sure we don't // constant propagate between them. ca = new; cb = new; ca.b = new; cb.a = new; ca.imembera = 100; ca.b.imemberb = 111; cb.imemberb = 200; cb.a.imembera = 202; if (ca.imembera != 100) $stop; if (ca.b.imemberb != 111) $stop; if (cb.imemberb != 200) $stop; if (cb.a.imembera != 202) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_bad2.v0000664000177100017500000000061513702133370021026 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function recurse; input i; recurse = recurse2(i); endfunction function recurse2; input i; recurse2 = recurse(i); endfunction endmodule verilator-4.038/test_regress/t/t_pp_circdef_bad.v0000664000177100017500000000070313702133370022105 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // bug445 `define WIDTH 12 `define SEL_NUM_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS `define SEL_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS `define ADDR_BITS 0 +: `WIDTH-`SEL_NUM_BITS typedef logic [`SEL_NUM_BITS-1:0] d_t; verilator-4.038/test_regress/t/t_assoc_pattern_unsup.pl0000775000177100017500000000107113702133367023456 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_void_bad.out0000664000177100017500000000045713702133370022333 0ustar wsnyderwsnyder%Warning-IGNOREDRETURN: t/t_func_void_bad.v:26:7: Ignoring return value of non-void function (IEEE 1800-2017 13.4.1) 26 | f1(20); | ^~ ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_flag_language.pl0000775000177100017500000000112713702133370022127 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ['--language 1364-2001'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_type_bad2.out0000664000177100017500000000077313702133370022603 0ustar wsnyderwsnyder%Error: t/t_param_type_bad2.v:8:19: Operator VAR 't' expected non-datatype Initial value but 'logic' is a datatype. : ... In instance t 8 | localparam t = logic; | ^~~~~ %Error: t/t_param_type_bad2.v:9:20: Operator VAR 't2' expected non-datatype Initial value but 'real' is a datatype. : ... In instance t 9 | localparam t2 = realtime; | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_numwidth.pl0000775000177100017500000000105713702133370022242 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--max-num-width 131072"], ); ok(1); 1; verilator-4.038/test_regress/t/t_param_type.pl0000775000177100017500000000105313702133370021512 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_sel_range_bad.out0000664000177100017500000000061413702133370023471 0ustar wsnyderwsnyder%Warning-SELRANGE: t/t_param_sel_range.v:43:35: Selection index out of range: 7:7 outside 4:0 : ... In instance t.u2 43 | r_rst[i] <= r_rst[i-1]; | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_unused_bad.v0000664000177100017500000000167113702133370022345 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); sub sub (); endmodule module sub; wire pub /*verilator public*/; // Ignore publics wire [5:0] assunu1 = 0; // Assigned but unused wire [3:0] assunub2 = 0; // Assigned but bit 2 unused wire [15:10] udrb2; // [14:13,11] is undriven assign udrb2[15] = 0; assign udrb2[12] = 0; assign udrb2[10] = 0; wire unu3; // Totally unused wire [3:0] mixed; // [3] unused & undr, [2] unused, [1] undr, [0] ok assign mixed[2] = 0; assign mixed[0] = 0; localparam THREE = 3; initial begin if (0 && assunu1[0] != 0 && udrb2 != 0) begin end if (0 && assunub2[THREE] && assunub2[1:0]!=0) begin end if (0 && mixed[1:0] != 0) begin end end endmodule verilator-4.038/test_regress/t/t_assert_property.pl0000775000177100017500000000113313702133367022623 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert --cc'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_package_dot.pl0000775000177100017500000000105313702133370021612 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_uniqueif_fail2.out0000664000177100017500000000021513702133370022443 0ustar wsnyderwsnyder[10] %Error: t_uniqueif.v:82: Assertion failed in top.t: 'unique if' statement violated %Error: t/t_uniqueif.v:82: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_param_type_collision.pl0000775000177100017500000000117413702133370023571 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_param_type.v"); compile( verilator_flags2 => ["--debug-collision"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_signed4.v0000664000177100017500000001044313702133370021551 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) module t (/*AUTOARG*/); bit fail; localparam signed [3:0] bug737_p1 = 4'b1000; wire [3:0] bug737_a = 4'b1010; reg [5:0] bug737_y; reg signed [3:0] w4_s; reg signed [4:0] w5_s; reg [3:0] w4_u; reg [4:0] w5_u; reg signed [8:0] w9_s; real r; initial begin // verilator lint_off WIDTH bug737_y = bug737_a + (bug737_p1 + 4'sb0); `checkh(bug737_y, 6'b010010); //bug737 // 6u +[6u] 4s +[6s] 6s bug737_y = 6'b001010 + (4'sb1000 + 6'sb0); `checkh(bug737_y, 6'b010010); //bug737, getx 000010 // 6u +[6u] 4s +[6s] 6s bug737_y = 6'b001010 + (4'b1000 + 6'sb0); `checkh(bug737_y, 6'b010010); //ok bug737_y = 6'b001010 + (6'sb111000 + 6'sb0); `checkh(bug737_y, 6'b000010); //ok // v--- sign extends to 6-bits bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0); `checkh(bug737_y, 6'b000010); //ok // From t_math_signed_3 w4_s = 4'sb1111 - 1'b1; `checkh(w4_s,33'he); w4_s = 4'sb1111 - 5'b00001; `checkh(w4_s,33'he); w4_s = 4'sb1111 - 1'sb1; `checkh(w4_s,4'h0); w5_s = 4'sb1111 - 1'sb1; `checkh(w5_s,4'h0); w4_s = 4'sb1111 - 4'sb1111; `checkh(w4_s,4'h0); w5_s = 4'sb1111 - 4'sb1111; `checkh(w5_s,5'h0); // The assign LHS being signed or unsigned does not matter per IEEE // The upper add being signed DOES matter propagating to lower w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add `checkh(w4_s,4'he); w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend `checkh(w4_s,4'h0); w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend `checkh(w4_s,4'he); // BUG, Verilator says 'h0 w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS `checkh(w5_u, 5'b10000); w4_u = 4'b1111 + 4'b0001; // Normal case `checkh(w4_u, 4'b0000); // Another example of promotion, the add is 4 bits wide w4_u = 3'b111 + 3'b010; `checkh(w4_u, 4'b1001); // w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter `checkh(w4_u, 4'sb1111); w4_s = 3'sb111 * 3'sb001; // Signed output `checkh(w4_s, 4'sb1111); w4_s = 3'b111 * 3'sb001; // Unsigned output `checkh(w4_s, 4'b0111); // Conditionals get width from parent; are assignment-like w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11); `checkh(w4_u, 4'b0100); w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000); `checkh(w4_u, 4'b0000); // If RHS is larger, that larger size is used w4_u = 5'b10000 / 5'b00100; `checkh(w4_u, 4'b0100); // bug754 w5_u = 4'sb0010 << -2'sd1; // << 3 `ifdef VCS `checkh(w5_u, 5'b00000); // VCS E-2014.03 bug `else `checkh(w5_u, 5'b10000); // VCS E-2014.03 bug `endif w5_u = 4'sb1000 << 0; // Sign extends `checkh(w5_u, 5'b11000); // Reals do not propagate to children r = 1.0 + ( 1 + (1 / 2)); `checkf(r, 2.0); // Self determined sign extension r = $itor(3'sb111); `checkf(r, -1.0); // If any part of case is real, all is real case (22) 22.0: ; 22.1: $stop; default: $stop; endcase // bug759 w5_u = { -4'sd7 }; `checkh(w5_u, 5'b01001); w5_u = {2{ -2'sd1 }}; `checkh(w5_u, 5'b01111); // Don't break concats.... w5_u = {{0{1'b1}}, -4'sd7 }; `checkh(w5_u, 5'b01001); w9_s = { -4'sd7, -4'sd7 }; `checkh(w9_s, 9'b010011001); {w5_u, {w4_u}} = 9'b10101_1100; `checkh(w5_u, 5'b10101); `checkh(w4_u, 4'b1100); {w4_u} = 4'b1011; `checkh(w4_u, 4'b1011); if (fail) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_case_default_bad.pl0000775000177100017500000000107413702133367022607 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_slice_struct_array_modport.pl0000775000177100017500000000076613702133370025030 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_runflag.pl0000775000177100017500000000202613702133370021010 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( ); execute( all_run_flags => ["+verilator+debug +verilator+debugi+9 +verilator+rand+reset+1"], check_finished => 1, expect => (q{.*Verilated::debug is on.*}), ); execute( all_run_flags => ["+verilator+help"], fails => 1, expect => ( q{.*For help, please see 'verilator --help' .*}), ); execute( all_run_flags => ["+verilator+V"], fails => 1, expect => ( q{.*Version:}), ); execute( all_run_flags => ["+verilator+version"], fails => 1, expect => ( q{.*Version:}), ); ok(1); 1; verilator-4.038/test_regress/t/t_runflag_errorlimit.v0000664000177100017500000000064613702133370023115 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $error("One"); $error("Two"); $error("Three"); $error("Four"); $error("Five"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_for_loop.pl0000775000177100017500000000105313702133370021170 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_under2.pl0000775000177100017500000000105313702133370021563 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_wire_behp1364_bad.out0000664000177100017500000000134113702133370022632 0ustar wsnyderwsnyder%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:23:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' : ... In instance t 23 | w = '0; | ^ %Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 24 | o = '0; | ^ %Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' : ... In instance t 25 | oa = '0; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_display.v0000664000177100017500000002202413702133370020646 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [40:0] quad; initial quad = 41'ha_bbbb_cccc; reg [80:0] wide; initial wide = 81'habc_1234_5678_1234_5678; reg [8:0] nine; initial nine = 12; reg signed [40:0] quads; initial quads = -(41'sha_bbbb_cccc); reg signed [80:0] wides; initial wides = -(81'shabc_1234_5678_1234_5678); reg signed [8:0] nines; initial nines = -12; reg [31:0] str; initial str = "\000\277\021\n"; reg [47:0] str2; initial str2 = "\000what!"; reg [79:0] str3; initial str3 = "\000hmmm!1234"; int n; initial n = 23; reg [7:0] m; initial m = 24; string svs = "sv-str"; reg [31:0] regstr = "meep"; sub sub (); sub2 sub2 (); initial begin $write("[%0t] In %m: Hi\n", $time); sub.write_m; sub2.write_m; // Escapes $display("[%0t] Back \\ Quote \"", $time); // Old bug when \" last on the line. // Display formatting - constants $display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, 9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc), 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, 9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc), -(81'shabc_1234_5678_1234_5678), -(81'shabc_1234_5678_1234_5678)); // Display formatting $display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, nines, nines, quads, quads, wides, wides); $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, nines, nines, quads, quads, wides, wides); // // verilator lint_off WIDTH $display("[%0t] %%C=%C %%0C=%0C", $time, "a"+nine, "a"+nine); $display("[%0t] %%c=%c %%0c=%0c", $time, "a"+nine, "a"+nine); // verilator lint_on WIDTH $display("[%0t] %%v=%v %%0v=%0v %%v=%v %%0v=%0v %%v=%v %%0v=%0v <", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%V=%V %%0V=%0V %%V=%V %%0V=%0V %%V=%V %%0V=%0V <", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%p=%p %%0p=%0p %%p=%p %%0p=%0p %%p=%p %%0p=%0p", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%P=%P %%0P=%0P %%P=%P %%0P=%0P %%P=%P %%0P=%0P", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%P=%P", $time, svs); $display("[%0t] %%u=%u %%0u=%0u", $time, {"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output $display("[%0t] %%U=%U %%0U=%0U", $time, {"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output // %z is tested in t_sys_sformat.v $display("[%0t] %%D=%D %%d=%d %%01d=%01d %%06d=%06d %%6d=%6d", $time, nine, nine, nine, nine, nine); $display("[%0t] %%t=%t %%03t=%03t %%0t=%0t", $time, $time, $time, $time); $display; // Not testing %0s, it does different things in different simulators $display("[%0t] %%s=%s %%s=%s %%s=%s", $time, str2[7:0], str2, str3); $display("[%0t] %%6s=:%6s: %%6s=:%6s: %%6s=:%6s:", $time, str2[7:0], str2, str3); $display("[%0t] %%8s=:%8s:", $time, svs); // Displays without format, must use default $write("d: "); $write(nine); $write(" "); $display(nine); $writeh("h: "); $writeh(nine); $writeh(" "); $displayh(nine); $writeo("o: "); $writeo(nine); $writeo(" "); $displayo(nine); $writeb("b: "); $writeb(nine); $writeb(" "); $displayb(nine); $display("[%0t] %s%s%s", $time, "hel", "lo, fr", "om a very long string. Percent %s are literally substituted in."); $display("hel", "lo, fr", "om a concatenated string."); $write("hel", "lo, fr", "om a concatenated format string [%0t].\n", $time); $display("extra argument: ", $time); $display($time,, ": pre argument",, "after"); $write("[%0t] Embedded tab '\t' and \r return\n", $time); $display("[%0t] Embedded\ multiline", $time); // Str check `ifndef NC // NC-Verilog 5.3 chokes on this test if (str !== 32'h00_bf_11_0a) $stop; `endif // Padding $write("'%0d %2d %8d'\n", 23, 23, 23); $write("'%-0d %-2d %-8d'\n", 23, 23, 23); $write("'%0d %2d %8d'\n", n, n, n); $write("'%-0d %-2d %-8d'\n", n, n, n); $write("'%8d'\n", m); $write("'%-8d'\n", m); $write("'%8t'\n", $time); $write("'%-8t'\n", $time); $write("'%8s'\n", svs); $write("'%-8s'\n", svs); $write("'%8s'\n", regstr); $write("'%-8s'\n", regstr); $write("'%8s'\n", "beep"); $write("'%-8s'\n", "beep"); // $itord conversion bug, note a %d instead of proper float // verilator lint_off REALCVT $display("log10(2) = %d", $log10(100)); // verilator lint_on REALCVT $write("*-* All Finished *-*\n"); $finish; end endmodule module sub; task write_m; begin $write("[%0t] In %m (%l)\n", $time); begin : subblock $write("[%0t] In %M (%L)\n", $time); // Uppercase %M test end end endtask endmodule module sub2; // verilator no_inline_module task write_m; begin $write("[%0t] In %m (%l)\n", $time); begin : subblock2 $write("[%0t] In %m (%L)\n", $time); end end endtask endmodule verilator-4.038/test_regress/t/t_param_up_bad.v0000664000177100017500000000117213702133370021614 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Ian Thompson. // SPDX-License-Identifier: CC0-1.0 //bug1099 typedef struct packed { logic foo; } some_struct_t; module child (); logic a_bad; // bar is in the parent module, but illegal to reference without module name assign a_bad = bar.foo; endmodule module parent #( parameter PARAM = 0 ) ( ); some_struct_t bar; child c (); endmodule module t (); // The parameter must be anything other than the default parent #( 1 ) p (); endmodule verilator-4.038/test_regress/t/t_prot_lib.pl0000775000177100017500000000436013702133370021167 0ustar wsnyderwsnyder#!/usr/bin/env perl # Makes the test run with tracing enabled by default, can be overridden # with --notrace unshift(@ARGV, "--trace"); if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios( vlt => 1, xsim => 1, ); $Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; my $secret_prefix = "secret"; my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; mkdir $secret_dir; while (1) { # Always compile the secret file with Verilator no matter what simulator # we are testing with run(logfile => "$secret_dir/vlt_compile.log", cmd => ["perl", "$ENV{VERILATOR_ROOT}/bin/verilator", "--prefix", "Vt_prot_lib_secret", "-cc", "-Mdir", $secret_dir, "--protect-lib", $secret_prefix, "t/t_prot_lib_secret.v"], verilator_run => 1, ); last if $Self->{errors}; run(logfile => "$secret_dir/secret_gcc.log", cmd=>[$ENV{MAKE}, "-C", $secret_dir, "-f", "Vt_prot_lib_secret.mk"]); last if $Self->{errors}; compile( verilator_flags2 => ["$secret_dir/secret.sv", "-LDFLAGS", "$secret_prefix/libsecret.a"], xsim_flags2 => ["$secret_dir/secret.sv"], ); execute( check_finished => 1, xsim_run_flags2 => ["--sv_lib", "$secret_dir/libsecret", "--dpi_absolute"], ); if ($Self->{vlt} && $Self->{trace}) { # We can see the ports of the secret module file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/); # but we can't see what's inside file_grep_not("$Self->{obj_dir}/simx.vcd", qr/secret_/); } ok(1); last; } 1; verilator-4.038/test_regress/t/t_lint_syncasyncnet_bad.pl0000775000177100017500000000121313702133370023724 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen5_noinl.pl0000775000177100017500000000116013702133370023425 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen5.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_concat.v0000664000177100017500000000325113702133367021310 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input wrclk ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (wrclk) some_other_state <= 0; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( `ifdef BROKEN .wrclk (i_clks[3]) `else .wrclk (i_clk1) `endif ); endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; assign the_clks = {i_clk1, i_clk2, i_clk1, i_clk0}; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( `ifdef ATTRIBUTES input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, `else input clk0, input clk1, input clk2, `endif input data_in ); logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk1), .i_clk2 (clk2), .i_data (data_in) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_case_reducer.pl0000775000177100017500000000105313702133367022003 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_twoedge.pl0000775000177100017500000000105313702133370021645 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_ifbegin.v0000664000177100017500000000216213702133370021463 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; tri pad_io_h; tri pad_io_l; sub sub (.*); endmodule module sub (/*AUTOARG*/ // Inouts pad_io_h, pad_io_l ); parameter USE = 1'b1; parameter DIFFERENTIAL = 1'b1; parameter BIDIR = 1'b1; inout pad_io_h; inout pad_io_l; wire [31:0] dqs_out_dtap_delay; generate if (USE) begin: output_strobe wire aligned_os_oe; wire aligned_strobe; if (BIDIR) begin reg sig_h_r = 1'b0; reg sig_l_r = 1'b0; always @* begin sig_h_r = ~aligned_os_oe ? aligned_strobe : 1'bz; if (DIFFERENTIAL) sig_l_r = ~aligned_os_oe ? ~aligned_strobe : 1'bz; end assign pad_io_h = sig_h_r; if (DIFFERENTIAL) assign pad_io_l = sig_l_r; end end endgenerate endmodule verilator-4.038/test_regress/t/t_interface1.v0000664000177100017500000000152113702133370021221 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing interface ifc; logic [3:0] value; endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc itop(); sub c1 (.isub(itop), .i_value(4'h4)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison if (itop.value != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub ( ifc isub, input logic [3:0] i_value ); always @* begin isub.value = i_value; end endmodule : sub verilator-4.038/test_regress/t/t_func_public.pl0000775000177100017500000000117313702133370021645 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['+define+VERILATOR_PUBLIC_TASKS'], fails => $fail, ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_typedef_unused_bad.pl0000775000177100017500000000114513702133370023204 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--Wpedantic"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_named.pl0000775000177100017500000000105313702133370021615 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_pat_width.pl0000775000177100017500000000105313702133370022740 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_uniqueif_fail3.out0000664000177100017500000000021513702133370022444 0ustar wsnyderwsnyder[10] %Error: t_uniqueif.v:90: Assertion failed in top.t: 'unique if' statement violated %Error: t/t_uniqueif.v:90: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_var_ref_bad2.out0000664000177100017500000000077213702133370022065 0ustar wsnyderwsnyder%Error: t/t_var_ref_bad2.v:13:7: Assigning to const ref variable: 'bad_const_set' : ... In instance t 13 | bad_const_set = 32'h4567; | ^~~~~~~~~~~~~ %Error: t/t_var_ref_bad2.v:23:17: Ref argument requires matching types; port 'int_ref' requires VAR 'int_ref' but connection is VARREF 'bad_non_int'. : ... In instance t 23 | checkset2(bad_non_int); | ^~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface1_modport_noinl.pl0000775000177100017500000000116413702133370024340 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface1_modport.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_synth_full.out0000664000177100017500000000023713702133367023323 0ustar wsnyderwsnyder[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found %Error: t/t_assert_synth.v:31: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_math_imm2.pl0000775000177100017500000000123213702133370021225 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_prot_lib_unpacked_bad.v0000664000177100017500000000073613702133370023501 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module secret_impl ( input unpacked_in [7:0], output unpacked_out [7:0]); genvar i; generate for (i = 0; i < 8; i = i + 1) begin assign unpacked_out[i] = unpacked_in[i]; end endgenerate endmodule verilator-4.038/test_regress/t/t_dpi_accessors.pl0000775000177100017500000000143413702133370022175 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2012 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # 8-Mar-2012: Modifications for this test contributed by Jeremy Bennett and # Jie Xu. scenarios(simulator => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["-Wno-BLKANDNBLK -language 1800-2005 --exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_dup_bad.pl0000775000177100017500000000107413702133367022341 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_cdc_async_debug_bad.out0000664000177100017500000000606313702133367023460 0ustar wsnyderwsnyderEdge Report for Vt_cdc_async_debug_bad t_cdc_async_bad.v: input clk SRC=@(*) DST=@(posedge clk or negedge rst0_n or negedge t.__Vcellinp__flop4__rst_n or negedge t.rst1_n or negedge t.rst2_bad_n or negedge t.rst5_waive_n or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n) t_cdc_async_bad.v: input d SRC=@(*) DST=@(posedge clk or negedge rst0_n or negedge t.__Vcellinp__flop4__rst_n or negedge t.rst1_n or negedge t.rst2_bad_n or negedge t.rst5_waive_n or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n) t_cdc_async_bad.v: input rst0_n SRC=@(*) DST=@(posedge clk or negedge rst0_n or negedge t.rst2_bad_n or negedge t.rst5_waive_n or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n) t_cdc_async_bad.v: output q0 SRC=@(posedge clk or negedge rst0_n) DST= t_cdc_async_bad.v: output q1 SRC=@(posedge clk or negedge t.rst1_n) DST= t_cdc_async_bad.v: output q2 SRC=@(posedge clk or negedge t.rst2_bad_n) DST= t_cdc_async_bad.v: output q3 SRC=@(posedge clk or negedge t.rst2_bad_n) DST= t_cdc_async_bad.v: output q4 SRC=@(posedge clk or negedge t.__Vcellinp__flop4__rst_n) DST= t_cdc_async_bad.v: output q5 SRC=@(posedge clk or negedge t.rst5_waive_n) DST= t_cdc_async_bad.v: output q6a SRC=@(posedge clk or negedge t.rst6a_bad_n) DST= t_cdc_async_bad.v: output q6b SRC=@(posedge clk or negedge t.rst6b_bad_n) DST= t_cdc_async_bad.v: wire t.__Vcellinp__flop4__rst_n SRC=@(posedge clk) DST=@(posedge clk or negedge t.__Vcellinp__flop4__rst_n) t_cdc_async_bad.v: wire t.rst1_n SRC=@(posedge clk) DST=@(posedge clk or negedge t.rst1_n or negedge t.rst2_bad_n or negedge t.rst5_waive_n or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n) t_cdc_async_bad.v: wire t.rst2_bad_n SRC=@(* or posedge clk) DST=@(posedge clk or negedge t.rst2_bad_n) t_cdc_async_bad.v: wire t.rst4_n SRC=@(posedge clk) DST=@(posedge clk or negedge t.__Vcellinp__flop4__rst_n) t_cdc_async_bad.v: wire t.rst5_waive_n SRC=@(* or posedge clk) DST=@(posedge clk or negedge t.rst5_waive_n) t_cdc_async_bad.v: wire t.rst6_bad_n SRC=@(* or posedge clk) DST=@(posedge clk or negedge t.rst6a_bad_n or negedge t.rst6b_bad_n) t_cdc_async_bad.v: wire t.rst6a_bad_n SRC=@(* or posedge clk) DST=@(posedge clk or negedge t.rst6a_bad_n) t_cdc_async_bad.v: wire t.rst6b_bad_n SRC=@(* or posedge clk) DST=@(posedge clk or negedge t.rst6b_bad_n) verilator-4.038/test_regress/t/t_func_v.v0000664000177100017500000000124613702133370020464 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Chandan Egbert. // SPDX-License-Identifier: CC0-1.0 // See bug569 module t(); `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif level1 ul1(); initial ul1.doit(4'b0); endmodule module level1(); `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif level2 ul2(); task doit(input logic [3:0] v); ul2.mem = v; $write("*-* All Finished *-*\n"); $finish; endtask endmodule module level2(); `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif logic [3:0] mem; endmodule verilator-4.038/test_regress/t/t_mod_interface_array1_noinl.pl0000775000177100017500000000116113702133370024626 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_mod_interface_array1.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_undefineall.v0000664000177100017500000000102013702133370023212 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define UDALL `ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif `undefineall `ifdef UDALL `error "undefineall failed" `endif `ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif initial begin $finish; end endmodule verilator-4.038/test_regress/t/t_time_sc_ms.out0000664000177100017500000000022613702133370021665 0ustar wsnyderwsnyder Warning: (W516) default time unit changed to time resolution Time scale of t is 1ms / 1ms [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-4.038/test_regress/t/t_generate_fatal_bad.v0000664000177100017500000000220713702133370022751 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 function integer get_baz(input integer bar); get_baz = bar; $fatal(2, "boom"); endfunction module foo #(parameter BAR = 0); localparam integer BAZ = get_baz(BAR); endmodule module foo2 #(parameter QUX = 0); genvar x; generate for (x = 0; x < 2; x++) begin: foo2_loop foo #(.BAR (QUX + x)) foo_in_foo2_inst(); end endgenerate endmodule module t; genvar i, j; generate for (i = 0; i < 2; i++) begin: genloop foo #(.BAR (i)) foo_inst(); end for (i = 2; i < 4; i++) begin: gen_l1 for (j = 0; j < 2; j++) begin: gen_l2 foo #(.BAR (i + j*2)) foo_inst2(); end end if (1 == 1) begin: cond_true foo #(.BAR (6)) foo_inst3(); end if (1 == 1) begin // unnamed foo #(.BAR (7)) foo_inst4(); end for (i = 8; i < 12; i = i + 2) begin: nested_loop foo2 #(.QUX (i)) foo2_inst(); end endgenerate endmodule verilator-4.038/test_regress/t/t_var_rsvd_bad.out0000664000177100017500000000076413702133370022206 0ustar wsnyderwsnyder%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:12:10: Symbol matches C++ keyword: 'bool' 12 | input bool; | ^~~~ ... Use "/* verilator lint_off SYMRSVDWORD */" and lint_on around source to disable this message. %Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:15:9: Symbol matches C++ keyword: 'switch' : ... In instance t 15 | reg switch /*verilator public*/ ; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_timescale.pl0000775000177100017500000000122513702133370021320 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["--exe $Self->{t_dir}/t_timescale.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dist_manifest.pl0000775000177100017500000000562213702133370022210 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); my $root = ".."; ### Must trim output before and after our file list my %files = %{get_manifest_files($root)}; my $all_files = `cd $root && find . -type f -print`; foreach my $file (split /\s+/,$all_files) { next if $file eq ''; $file =~ s!^\./!!; $files{$file} |= 2; } my %file_regexps; my $skip = file_contents("$root/MANIFEST.SKIP"); foreach my $file (sort keys %files) { foreach my $skip (split /\s+/,$skip) { if ($file =~ /$skip/) { $files{$file} |= 4; $file_regexps{$file} = $skip; } } } # The repo may be a Git worktree my $git_dir = `cd $root ; git rev-parse --git-common-dir`; chomp $git_dir; if (! -d $git_dir) { $git_dir = ".git"; } # Ignore files locally excluded my $git_exclude = `cd $root && git ls-files --others --ignored --exclude-from $git_dir/info/exclude`; foreach my $exclude (split /\s+/, $git_exclude) { if (exists $files{$exclude}) { $files{$exclude} |= 8; } } my %warns; foreach my $file (sort keys %files) { my $tar = $files{$file}&1; my $dir = $files{$file}&2; my $skip = $files{$file}&4; my $exclude = $files{$file}&8; print +(($tar ? "TAR ":" ") .($dir ? "DIR ":" ") .($skip ? "SKIP ":" ") .($exclude ? "EXCL ":" ") ." $file\n") if $Self->{verbose}; if ($dir && !$tar && !$skip && !$exclude) { $warns{$file} = "File not in manifest or MANIFEST.SKIP: $file"; } elsif (!$dir && $tar && !$skip) { $warns{$file} = "File in manifest, but not directory: $file"; } elsif ($dir && $tar && $skip) { $warns{$file} = "File in manifest and also MANIFEST.SKIP, too general skip regexp '$file_regexps{$file}'?: $file"; } } if (keys %warns) { # First warning lists everything as that's shown in the driver summary error("Files mismatch with manifest: ",join(' ',sort keys %warns)); foreach my $file (sort keys %warns) { error($warns{$file}); } } ok(1); 1; sub get_manifest_files { my $root = shift; `cd $root && $ENV{MAKE} dist-file-list`; my $manifest_files = `cd $root && $ENV{MAKE} dist-file-list`; $manifest_files =~ s!.*begin-dist-file-list:!!sg; $manifest_files =~ s!end-dist-file-list:.*$!!sg; print "MF $manifest_files\n" if $Self->{verbose}; my %files; foreach my $file (split /\s+/,$manifest_files) { next if $file eq ''; $files{$file} |= 1; } return \%files; } verilator-4.038/test_regress/t/t_array_unpacked_public.pl0000775000177100017500000000113113702133367023702 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--public-flat-rw"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_package_ddecl.pl0000775000177100017500000000105313702133370022077 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_timescale.out0000664000177100017500000000006213702133370022500 0ustar wsnyderwsnyderTime scale of t is 1ms / 1us *-* All Finished *-* verilator-4.038/test_regress/t/t_tri_gate_nmos.pl0000775000177100017500000000141513702133370022205 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_tri_gate.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ['+define+T_NMOS',], make_flags => 'CPPFLAGS_ADD=-DT_NMOS', verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unroll_genf.pl0000775000177100017500000000105313702133370021663 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_svl.v0000664000177100017500000000742113702133370021022 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [15:0] l; reg [49:0] q; reg [79:0] w; reg [4:0] lc; reg lo; reg l0; reg [5:0] qc; reg qo; reg q0; reg [6:0] wc; reg wo; reg w0; always @* begin lc = $countones(l); lo = $onehot(l); l0 = $onehot0(l); wc = $countones(w); wo = $onehot(w); w0 = $onehot0(w); qc = $countones(q); qo = $onehot(q); q0 = $onehot0(q); end integer cyc; initial cyc=1; integer cyc_com; always_comb begin cyc_com = cyc; end integer cyc_d1; always_ff @ (posedge clk) begin cyc_d1 <= cyc_com; end initial begin // Constification check if ($countones(32'b11001011101) != 7) $stop; if ($countones(32'b0) != 0) $stop; if ($isunknown(32'b11101x11111) != 1) $stop; if ($isunknown(32'b11101011111) != 0) $stop; if ($isunknown(32'b10zzzzzzzzz) != 1) $stop; if ($bits(0) != 32'd32) $stop; if ($bits(lc) != 5) $stop; if ($onehot(32'b00000001000000) != 1'b1) $stop; if ($onehot(32'b00001001000000) != 1'b0) $stop; if ($onehot(32'b0) != 1'b0) $stop; if ($onehot0(32'b00000001000000) != 1'b1) $stop; if ($onehot0(32'b00001001000000) != 1'b0) $stop; if ($onehot0(32'b0) != 1'b1) $stop; end always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n", // cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0); if (cyc_com != cyc_com) $stop; if (cyc_d1 != cyc-1) $stop; if (cyc==1) begin l <= 16'b0; q <= 50'h0; w <= 80'h0; end if (cyc==2) begin l <= ~16'b0; q <= ~50'h0; w <= ~80'h0; // if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop; if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop; if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop; end if (cyc==3) begin l <= 16'b0010110010110111; q <= 50'h01_1111_0001; w <= 80'h0100_0000_0f00_00f0_0000; // if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop; if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop; if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop; end if (cyc==4) begin l <= 16'b0000010000000000; q <= 50'h1_0000_0000; w <= 80'h010_00000000_00000000; // if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop; if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop; if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop; end if (cyc==5) begin l <= 16'b0000000100000000; q <= 50'h8000_0000_0000; w <= 80'h10_00000000_00000000; // if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop; if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop; if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop; end if (cyc==6) begin l <= 16'b0000100100000000; q <= 50'h01_00000100; w <= 80'h01_00000100_00000000; // if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop; if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop; if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop; end if (cyc==7) begin // if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop; if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop; if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop; end if (cyc==8) begin end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end initial begin if ($isunknown(4'b000x) !== 1'b1) $stop; if ($isunknown(4'b000z) !== 1'b1) $stop; if ($isunknown(4'b00xz) !== 1'b1) $stop; if ($isunknown(4'b0000) !== 1'b0) $stop; end final begin $write("Goodbye world, at cycle %0d\n", cyc); end endmodule verilator-4.038/test_regress/t/t_flag_errorlimit_bad.pl0000775000177100017500000000117613702133370023346 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["-Wall -Wno-DECLFILENAME --error-limit 2"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_alw_split.v0000664000177100017500000000442613702133367021213 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [15:0] m_din; // We expect all these blocks should split; // blocks that don't split should go in t_alw_nosplit.v reg [15:0] a_split_1, a_split_2; always @ (/*AS*/m_din) begin a_split_1 = m_din; a_split_2 = m_din; end reg [15:0] d_split_1, d_split_2; always @ (posedge clk) begin d_split_1 <= m_din; d_split_2 <= d_split_1; d_split_1 <= ~m_din; end reg [15:0] h_split_1; reg [15:0] h_split_2; always @ (posedge clk) begin // $write(" cyc = %x m_din = %x\n", cyc, m_din); if (cyc > 2) begin if (m_din == 16'h0) begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end else begin h_split_1 <= m_din; h_split_2 <= ~m_din; end end else begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end end // (The checker block is an exception, it won't split.) always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==1) begin m_din <= 16'hfeed; end if (cyc==3) begin end if (cyc==4) begin m_din <= 16'he11e; //$write(" A %x %x\n", a_split_1, a_split_2); if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; end if (cyc==5) begin m_din <= 16'he22e; if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; end if (cyc==6) begin m_din <= 16'he33e; if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop; if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop; end if (cyc==7) begin $write("*-* All Finished *-*\n"); $finish; end end end // always @ (posedge clk) endmodule verilator-4.038/test_regress/t/t_lint_blksync_bad.pl0000775000177100017500000000120213702133370022646 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_module.pl0000775000177100017500000000105313702133367022031 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_dtree_inlac.pl0000775000177100017500000000125113702133370022657 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_A +define+INLINE_C'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_first_bad.out0000664000177100017500000000051113702133367022334 0ustar wsnyderwsnyder%Warning-DEPRECATED: t/t_clk_first_deprecated.v:12:14: sc_clock is deprecated and will be removed 12 | input clk /*verilator sc_clock*/ ; | ^~~~~~~~~~~~~~~~~~~~~~ ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_math_sign_extend.pl0000775000177100017500000000105313702133370022671 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_always_comb_iface.pl0000775000177100017500000000076613702133370024040 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_a4_examples.pl0000775000177100017500000000125513702133367021565 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); $Self->{clean_command} = 'rm -rf ../examples/*/build ../examples/*/obj*'; my @examples = sort(glob("../examples/*")); for my $example (@examples) { run(cmd=>["$ENV{MAKE} -C $example"]); } ok(1); 1; verilator-4.038/test_regress/t/t_func_noinl.pl0000775000177100017500000000105313702133370021503 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_signed6.v0000664000177100017500000000171113702133370021551 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) module t (/*AUTOARG*/); // signed source logic signed [8-1:0] src; // destination structure struct packed { logic signed [16-1:0] s; logic unsigned [16-1:0] u; } dst; initial begin // bug882 // verilator lint_off WIDTH src = 8'sh05; dst = '{s: src, u: src}; `checkh (dst.s, 16'h0005); `checkh (dst.u, 16'h0005); src = 8'shf5; dst = '{s: src, u: src}; `checkh (dst.s, 16'hfff5); `checkh (dst.u, 16'hfff5); // verilator lint_on WIDTH $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_restore_bad.v0000664000177100017500000000066413702133370022526 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); reg [3:0] four; reg [4:0] five; // verilator lint_save // verilator lint_off WIDTH initial four = 64'h1; // verilator lint_restore initial five = 64'h1; initial $stop; endmodule verilator-4.038/test_regress/t/t_unconnected_bad.out0000664000177100017500000000062513702133370022661 0ustar wsnyderwsnyder%Error: t/t_unconnected_bad.v:7:1: Bad `unconnected_drive syntax 7 | `unconnected_drive | ^~~~~~~~~~~~~~~~~~ %Error: t/t_unconnected_bad.v:9:1: Bad `unconnected_drive syntax 9 | `unconnected_drive pull2 | ^~~~~~~~~~~~~~~~~~ %Error: t/t_unconnected_bad.v:9:20: syntax error, unexpected IDENTIFIER 9 | `unconnected_drive pull2 | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_flag_off.pl0000775000177100017500000000120113702133370022265 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test that without --trace we get a message when turning on traces scenarios(vlt => 1); compile( ); execute( expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_nest.pl0000775000177100017500000000105313702133367021323 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_enabled_bad.pl0000775000177100017500000000121513702133367023140 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_on.v"); compile( verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], ); execute( fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_cover.v0000664000177100017500000000714713702133367021717 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; integer cyc; initial cyc=1; Test test (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle), .cyc (cyc[31:0])); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; toggle <= !cyc[0]; if (cyc==9) begin end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test ( input clk, input toggle, input [31:0] cyc ); // Simple cover cover property (@(posedge clk) cyc==3); // With statement, in generate generate if (1) begin cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4"); end endgenerate // Labeled cover cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); // Using default clock default clocking @(posedge clk); endclocking cover property (cyc==6) $display("*COVER: Cyc==6"); // Disable statement // Note () after disable are required cover property (@(posedge clk) disable iff (toggle) cyc==8) $display("*COVER: Cyc==8"); cover property (@(posedge clk) disable iff (!toggle) cyc==8) $stop; always_ff @ (posedge clk) begin labeled_icov: cover (cyc==3 || cyc==4); end // Immediate cover labeled_imm0: cover #0 (cyc == 0); labeled_immf: cover final (cyc == 0); // Immediate assert labeled_imas: assert #0 (1); assert final (1); //============================================================ // Using a macro and generate wire reset = (cyc < 2); `define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn)) genvar i; generate for (i=0; i<32; i=i+1) begin: cycval CycCover_i: `covclk( cyc[i] ); end endgenerate `ifndef verilator // Unsupported //============================================================ // Using a more complicated property property C1; @(posedge clk) disable iff (!toggle) cyc==5; endproperty cover property (C1) $display("*COVER: Cyc==5"); // Using covergroup // Note a covergroup is really inheritance of a special system "covergroup" class. covergroup counter1 @ (posedge cyc); // Automatic methods: stop(), start(), sample(), set_inst_name() // Each bin value must be <= 32 bits. Strange. cyc_value : coverpoint cyc { } cyc_bined : coverpoint cyc { bins zero = {0}; bins low = {1,5}; // Note 5 is also in the bin above. Only the first bin matching is counted. bins mid = {[5:$]}; // illegal_bins // Has precidence over "first matching bin", creates assertion // ignore_bins // Not counted, and not part of total } toggle : coverpoint (toggle) { bins off = {0}; bins on = {1}; } cyc5 : coverpoint (cyc==5) { bins five = {1}; } // option.at_least = {number}; // Default 1 - Hits to be considered covered // option.auto_bin_max = {number}; // Default 64 // option.comment = {string} // option.goal = {number}; // Default 90% // option.name = {string} // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) // option.weight = {number}; // Default 1 // CROSS value_and_toggle: // else default is ___X__ cross cyc_value, toggle; endgroup counter1 c1 = new(); `endif endmodule verilator-4.038/test_regress/t/t_order_comboclkloop.pl0000775000177100017500000000106013702133370023225 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_anon.v0000664000177100017500000000113013702133370021533 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Anonymous struct packed { logic [31:0] val1; logic [31:0] val2; } struct1; struct packed { logic [31:0] val3; logic [31:0] val4; } struct2; module t ( output logic [63:0] s1, output logic [63:0] s2 ); initial struct1 = 64'h123456789_abcdef0; always_comb s1 = struct1; initial struct2 = 64'h123456789_abcdef0; always_comb s2 = struct2; endmodule verilator-4.038/test_regress/t/t_trace_abort_fst.pl0000775000177100017500000000126513702133370022517 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_trace_abort.v"); compile( verilator_flags2 => ['--cc --trace-fst'], ); execute( fails => 1, ); fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_delay.v0000664000177100017500000000214513702133370020301 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; input clk; integer cyc=1; reg [31:0] dly0; wire [31:0] dly1; wire [31:0] dly2 = dly1 + 32'h1; typedef struct packed { int dly; } dly_s_t; dly_s_t dly_s; assign #(1.2000000000000000) dly1 = dly0 + 32'h1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin dly0 <= #0 32'h11; end else if (cyc == 2) begin dly0 <= #0.12 dly0 + 32'h12; end else if (cyc == 3) begin if (dly0 !== 32'h23) $stop; if (dly2 !== 32'h25) $stop; end else if (cyc == 4) begin dly_s.dly = 55; dly0 <= #(dly_s.dly) 32'h55; //dly0 <= # dly_s.dly 32'h55; // Unsupported, issue-2410 end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); #100 $finish; end end endmodule verilator-4.038/test_regress/t/t_assert_cover.pl0000775000177100017500000000313513702133367022061 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_cover.v"); compile( verilator_flags2 => ['--assert --cc --coverage-user'], nc_flags2 => ["+nccovoverwrite +nccoverage+all +nccovtest+$Self->{name}"] ); execute( check_finished => 1, ); if ($Self->{nc}) { my $name = $Self->{name}; my $cf = "$Self->{obj_dir}/${name}__nccover.cf"; { my $fh = IO::File->new(">$cf") or die "%Error: $! writing $cf,"; $fh->printf("report_summary -module *\n"); $fh->printf("report_detail -both -instance *\n"); $fh->printf("report_html -both -instance * > $Self->{obj_dir}/${name}__nccover.html\n"); $fh->close; } run(logfile => "$Self->{obj_dir}/${name}__nccover.log", tee => 0, cmd => [($ENV{VERILATOR_ICCR}||'iccr'), "-test ${name} ${cf}"]); } file_grep($Self->{run_log_filename}, qr/COVER: Cyc==4/); file_grep($Self->{run_log_filename}, qr/COVER: Cyc==5/); file_grep($Self->{run_log_filename}, qr/COVER: Cyc==6/); # Allow old Perl format dump, or new binary dump file_grep($Self->{coverage_filename}, qr/(cyc_eq_5.*,c=>[^0]|cyc_eq_5.* [1-9][0-9]*\n)/); ok(1); 1; verilator-4.038/test_regress/t/t_lint_comb_bad.v0000664000177100017500000000051713702133370021760 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always_comb @(*) begin $stop; end endmodule verilator-4.038/test_regress/t/t_dist_tabs.pl0000775000177100017500000000711613702133370021333 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); my $root = ".."; my $Tabs_Exempt_Re = qr!(\.out$)|(/gtkwave)|(Makefile)|(\.mk$)|(nodist/fastcov.py)!; my $Wide_Exempt_Re = qr!(\.l$)|(\.y$)!; if (!-r "$root/.git") { skip("Not in a git repository"); } else { ### Must trim output before and after our file list my %warns; my $prefix; my $summary = ""; { my $diff = `cd $root && git diff HEAD`; #print "DS $diff\n" if $Debug; my $file; my $atab; my $btab; my $lineno = 0; foreach my $line ((split /\n/, $diff), "+++ b/_the_end") { if ($line =~ m!^\+\+\+ b/(.*)!) { if ($file && !$atab && $btab && $file !~ $Tabs_Exempt_Re) { $summary = "File modifications adds new tabs (please untabify the patch):"; $warns{$file} = "File modification adds new tabs (please untabify the patch): $file"; } # Next $file = $1; $atab = 0; $btab = 0; print " File $file\n" if $Self->{verbose}; } elsif ($line =~ m!^@@ -?[0-9]+,?[0-9]* \+?([0-9]+)!) { $lineno = $1 - 1; } elsif ($line =~ m!^ !) { ++$lineno; if ($line =~ m!^[- ].*\t!) { print " Had tabs\n" if $Self->{verbose} && !$atab; $atab = 1; } } elsif ($line =~ m!^-.*\t!) { print " Had tabs\n" if $Self->{verbose} && !$atab; $atab = 1; } elsif ($line =~ m!^\+.*\t!) { ++$lineno; print " Inserts tabs\n" if $Self->{verbose} && !$btab; $btab = 1; } elsif ($line =~ m!^\+(.*)!) { ++$lineno; if ($line =~ /\r/) { $summary = "File modification adds carriage return (remove them):" if !$summary; $warns{$file} = "File modification adds carriage return (remove them): $file:$lineno"; } my $len = length($1); if ($len >= 100 && $file !~ $Tabs_Exempt_Re && $file !~ $Wide_Exempt_Re) { print" Wide $line\n" if $Self->{verbose}; $summary = "File modification adds a new >100 column line:" if !$summary; $warns{$file} = "File modification adds a new >100 column line: $file:$lineno"; } } } } if (keys %warns) { # First warning lists everything as that's shown in the driver summary error($summary." ",join(' ',sort keys %warns)); foreach my $file (sort keys %warns) { error($warns{$file}); } } } sub _has_tabs { my $filename = shift; my $contents = file_contents($filename); if ($filename =~ /\.out$/) { # Ignore golden files } elsif ($contents =~ /[\001\002\003\004\005\006]/) { # Ignore binrary files } elsif ($contents =~ /\t/) { return 1; } return 0; } ok(1); 1; verilator-4.038/test_regress/t/t_func_sum.v0000664000177100017500000000371013702133370021021 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008-2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; wire [9:0] I1 = crc[9:0]; wire [9:0] I2 = crc[19:10]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [9:0] S; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .S (S[9:0]), // Inputs .I1 (I1[9:0]), .I2 (I2[9:0])); wire [63:0] result = {32'h0, 22'h0, S}; `define EXPECTED_SUM 64'h24c38b77b0fcc2e7 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs S, // Inputs I1, I2 ); input [9:0] I1/*verilator public*/; input [9:0] I2/*verilator public*/; output reg [9:0] S/*verilator public*/; always @(I1 or I2) t2(I1,I2,S); task t1; input In1,In2; output Sum; Sum = In1 ^ In2; endtask task t2; input[9:0] In1,In2; output [9:0] Sum; integer I; begin for (I=0;I<10;I=I+1) t1(In1[I],In2[I],Sum[I]); end endtask endmodule verilator-4.038/test_regress/t/t_mem_iforder.pl0000775000177100017500000000106013702133370021637 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_time.v0000664000177100017500000000241513702133370021666 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin if ($time >= 10) begin // Display formatting $write; // Check missing arguments work $write("default: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 0, "", 0); $write("-9,0,,0: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 0, "", 10); $write("-9,0,,10: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 0, "ns", 5); $write("-9,0,ns,5: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 3, "ns", 8); $write("-9,3,ns,8: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $write("\n"); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_select_set.pl0000775000177100017500000000105313702133370021503 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unopt_converge_run_bad.pl0000775000177100017500000000131013702133370024074 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2007 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_unopt_converge.v"); compile( v_flags2 => ['+define+ALLOW_UNOPT --output-split 0'], ); execute( fails => 1, expect_filename => $Self->{golden_filename}, ) if $Self->{vlt_all}; ok(1); 1; verilator-4.038/test_regress/t/t_var_overwidth_bad.v0000664000177100017500000000077613702133370022704 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_multidriven_bad.pl0000775000177100017500000000107413702133370023552 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_notunsized.v0000664000177100017500000000466613702133370022454 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [71:0] muxed; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .muxed (muxed[71:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {muxed[63:0]}; wire [5:0] width_check = cyc[5:0] + 1; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h20050a66e7b253d1 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs muxed, // Inputs clk, in ); input clk; input [31:0] in; output [71:0] muxed; wire [71:0] a = {in[7:0],~in[31:0],in[31:0]}; wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]}; /*AUTOWIRE*/ Muxer muxer ( .sa (0), .sb (in[0]), /*AUTOINST*/ // Outputs .muxed (muxed[71:0]), // Inputs .a (a[71:0]), .b (b[71:0])); endmodule module Muxer (/*AUTOARG*/ // Outputs muxed, // Inputs sa, sb, a, b ); input sa; input sb; output wire [71:0] muxed; input [71:0] a; input [71:0] b; // Constification wasn't sizing with inlining and gave // unsized error on below // v assign muxed = (({72{sa}} & a) | ({72{sb}} & b)); endmodule verilator-4.038/test_regress/t/t_flag_werror_bad1.pl0000775000177100017500000000113513702133370022552 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_werror.v"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_prot_lib_inout_bad.pl0000775000177100017500000000143613702133370023214 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile ( verilator_flags2 => ["--protect-lib", "secret"], verilator_make_gcc => 0, fails => 1, expect_filename => $Self->{golden_filename}, ); #run(cmd=>["make", # "-C", # "$Self->{obj_dir}", # "-f", # "V$Self->{name}.mk"]); ok(1); 1; verilator-4.038/test_regress/t/t_mem_multiwire.pl0000775000177100017500000000105313702133370022230 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_query.pl0000775000177100017500000000105313702133367021722 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_finish_c.cpp0000664000177100017500000000146613702133370022165 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include "svdpi.h" #include "vpi_user.h" //====================================================================== extern "C" { extern void dpii_test(); } //====================================================================== void dpii_test() { vpi_control(vpiFinish); } verilator-4.038/test_regress/t/t_func_const_packed_array_bad.pl0000775000177100017500000000107313702133370025027 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2017 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_pattern_bad.v0000664000177100017500000000075013702133367022672 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug1364 module t (/*AUTOARG*/ // Inputs clk, res ); input clk; input res; typedef struct packed { logic [3:0] port_num; } info_t; info_t myinfo; always_comb myinfo = '{default: '0, valids: '1}; endmodule verilator-4.038/test_regress/t/t_clk_latch_edgestyle.pl0000775000177100017500000000130213702133367023345 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_clk_latch.v"); my $fail = $Self->{vlt_all}; compile( v_flags2 => ['+define+EDGE_DETECT_STYLE'], fails => $fail, ); execute( check_finished => !$fail, ) if !$fail; ok(1); 1; verilator-4.038/test_regress/t/t_bitsel_wire_array_bad.v0000664000177100017500000000102513702133367023521 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test of select from constant // // This tests issue 509, bit select of constant fails // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // a and b are arrays of length 1. wire a[0:0]; // Array of nets wire b[0:0]; assign a = 1'b0; // Only net assignment allowed assign b = a[0]; // Only net assignment allowed endmodule verilator-4.038/test_regress/t/t_time_passed.out0000664000177100017500000000021613702133370022037 0ustar wsnyderwsnydertop.t.ps: Input time 5432109.877000ns 5432109877 top.t.ns: Input time 5432109877.000000ns 5432109877 *-* All Finished *-* verilator-4.038/test_regress/t/t_interface_wrong_bad.v0000664000177100017500000000132713702133370023166 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Using the wrong kind of interface in a portmap // should cause an error // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic [7:0] a; endinterface interface bar_intf; logic [7:0] a; endinterface module foo_mod (foo_intf foo_port); // initial begin // $display("a = %0d", foo_port.a); // end endmodule module t (/*AUTOARG*/); foo_intf foo (); bar_intf bar (); // assign foo.a = 8'd1; // assign bar.a = 8'd2; foo_mod foo_mod ( .foo_port (bar) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_flag_topmodule_bad2.out0000664000177100017500000000013213702133341023426 0ustar wsnyderwsnyder%Error: Specified --top-module 'notfound' was not found in design. %Error: Exiting due to verilator-4.038/test_regress/t/t_cover_line_trace.out0000664000177100017500000004513713702133370023060 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sun May 31 15:48:42 2020 $end $timescale 1ps $end $scope module top $end $var wire 1 W clk $end $scope module t $end $var wire 1 W clk $end $var wire 32 & cyc [31:0] $end $var wire 8 ' cyc_copy [7:0] $end $var wire 1 % toggle $end $var wire 32 ; vlCoverageLineTrace_t_cover_line__102_elsif [31:0] $end $var wire 32 : vlCoverageLineTrace_t_cover_line__105_elsif [31:0] $end $var wire 32 9 vlCoverageLineTrace_t_cover_line__112_else [31:0] $end $var wire 32 8 vlCoverageLineTrace_t_cover_line__112_if [31:0] $end $var wire 32 X vlCoverageLineTrace_t_cover_line__119_block [31:0] $end $var wire 32 # vlCoverageLineTrace_t_cover_line__15_block [31:0] $end $var wire 32 $ vlCoverageLineTrace_t_cover_line__18_block [31:0] $end $var wire 32 > vlCoverageLineTrace_t_cover_line__47_block [31:0] $end $var wire 32 = vlCoverageLineTrace_t_cover_line__48_else [31:0] $end $var wire 32 < vlCoverageLineTrace_t_cover_line__48_if [31:0] $end $var wire 32 ) vlCoverageLineTrace_t_cover_line__52_else [31:0] $end $var wire 32 ( vlCoverageLineTrace_t_cover_line__52_if [31:0] $end $var wire 32 + vlCoverageLineTrace_t_cover_line__53_else [31:0] $end $var wire 32 * vlCoverageLineTrace_t_cover_line__53_if [31:0] $end $var wire 32 - vlCoverageLineTrace_t_cover_line__58_else [31:0] $end $var wire 32 , vlCoverageLineTrace_t_cover_line__58_if [31:0] $end $var wire 32 / vlCoverageLineTrace_t_cover_line__59_else [31:0] $end $var wire 32 . vlCoverageLineTrace_t_cover_line__59_if [31:0] $end $var wire 32 1 vlCoverageLineTrace_t_cover_line__65_else [31:0] $end $var wire 32 0 vlCoverageLineTrace_t_cover_line__65_if [31:0] $end $var wire 32 3 vlCoverageLineTrace_t_cover_line__66_else [31:0] $end $var wire 32 2 vlCoverageLineTrace_t_cover_line__66_if [31:0] $end $var wire 32 7 vlCoverageLineTrace_t_cover_line__75_elsif [31:0] $end $var wire 32 6 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end $var wire 32 5 vlCoverageLineTrace_t_cover_line__83_else [31:0] $end $var wire 32 4 vlCoverageLineTrace_t_cover_line__83_if [31:0] $end $var wire 32 ] vlCoverageLineTrace_t_cover_line__92_block [31:0] $end $var wire 32 ^ vlCoverageLineTrace_t_cover_line__93_block [31:0] $end $var wire 32 _ vlCoverageLineTrace_t_cover_line__96_block [31:0] $end $var wire 32 ` vlCoverageLineTrace_t_cover_line__97_block [31:0] $end $scope module a1 $end $var wire 1 W clk $end $var wire 1 % toggle $end $var wire 32 B vlCoverageLineTrace_t_cover_line__132_block [31:0] $end $var wire 32 @ vlCoverageLineTrace_t_cover_line__133_else [31:0] $end $var wire 32 ? vlCoverageLineTrace_t_cover_line__133_if [31:0] $end $var wire 32 A vlCoverageLineTrace_t_cover_line__137_else [31:0] $end $upscope $end $scope module a2 $end $var wire 1 W clk $end $var wire 1 % toggle $end $var wire 32 F vlCoverageLineTrace_t_cover_line__132_block [31:0] $end $var wire 32 D vlCoverageLineTrace_t_cover_line__133_else [31:0] $end $var wire 32 C vlCoverageLineTrace_t_cover_line__133_if [31:0] $end $var wire 32 E vlCoverageLineTrace_t_cover_line__137_else [31:0] $end $upscope $end $scope module b1 $end $var wire 1 W clk $end $var wire 1 % toggle $end $var wire 32 O vlCoverageLineTrace_t_cover_line__156_block [31:0] $end $var wire 32 K vlCoverageLineTrace_t_cover_line__158_else [31:0] $end $var wire 32 b vlCoverageLineTrace_t_cover_line__158_if [31:0] $end $var wire 32 M vlCoverageLineTrace_t_cover_line__162_else [31:0] $end $var wire 32 L vlCoverageLineTrace_t_cover_line__162_if [31:0] $end $var wire 32 N vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $upscope $end $scope module b2 $end $var wire 1 W clk $end $var wire 1 % toggle $end $var wire 32 T vlCoverageLineTrace_t_cover_line__156_block [31:0] $end $var wire 32 P vlCoverageLineTrace_t_cover_line__158_else [31:0] $end $var wire 32 c vlCoverageLineTrace_t_cover_line__158_if [31:0] $end $var wire 32 R vlCoverageLineTrace_t_cover_line__162_else [31:0] $end $var wire 32 Q vlCoverageLineTrace_t_cover_line__162_if [31:0] $end $var wire 32 S vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $upscope $end $scope module o1 $end $var wire 1 W clk $end $var wire 1 % toggle $end $var wire 32 J vlCoverageLineTrace_t_cover_line__220_block [31:0] $end $var wire 32 I vlCoverageLineTrace_t_cover_line__221_else [31:0] $end $var wire 32 H vlCoverageLineTrace_t_cover_line__221_if [31:0] $end $var wire 32 G vlCoverageLineTrace_t_cover_line__224_else [31:0] $end $var wire 32 a vlCoverageLineTrace_t_cover_line__224_if [31:0] $end $upscope $end $scope module t1 $end $var wire 1 W clk $end $var wire 1 % toggle $end $var wire 32 U vlCoverageLineTrace_t_cover_line__187_block [31:0] $end $var wire 32 \ vlCoverageLineTrace_t_cover_line__191_block [31:0] $end $var wire 32 Z vlCoverageLineTrace_t_cover_line__194_else [31:0] $end $var wire 32 Y vlCoverageLineTrace_t_cover_line__194_if [31:0] $end $var wire 32 V vlCoverageLineTrace_t_cover_line__197_else [31:0] $end $var wire 32 [ vlCoverageLineTrace_t_cover_line__197_if [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # b00000000000000000000000000000001 $ 0% b00000000000000000000000000000001 & b00000001 ' b00000000000000000000000000000000 ( b00000000000000000000000000000000 ) b00000000000000000000000000000000 * b00000000000000000000000000000000 + b00000000000000000000000000000000 , b00000000000000000000000000000000 - b00000000000000000000000000000000 . b00000000000000000000000000000000 / b00000000000000000000000000000000 0 b00000000000000000000000000000000 1 b00000000000000000000000000000000 2 b00000000000000000000000000000000 3 b00000000000000000000000000000000 4 b00000000000000000000000000000000 5 b00000000000000000000000000000000 6 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 b00000000000000000000000000000000 9 b00000000000000000000000000000000 : b00000000000000000000000000000000 ; b00000000000000000000000000000000 < b00000000000000000000000000000000 = b00000000000000000000000000000000 > b00000000000000000000000000000000 ? b00000000000000000000000000000000 @ b00000000000000000000000000000000 A b00000000000000000000000000000000 B b00000000000000000000000000000000 C b00000000000000000000000000000000 D b00000000000000000000000000000000 E b00000000000000000000000000000000 F b00000000000000000000000000000000 G b00000000000000000000000000000000 H b00000000000000000000000000000000 I b00000000000000000000000000000000 J b00000000000000000000000000000000 K b00000000000000000000000000000000 L b00000000000000000000000000000000 M b00000000000000000000000000000000 N b00000000000000000000000000000000 O b00000000000000000000000000000000 P b00000000000000000000000000000000 Q b00000000000000000000000000000000 R b00000000000000000000000000000000 S b00000000000000000000000000000000 T b00000000000000000000000000000000 U b00000000000000000000000000000000 V 0W b00000000000000000000000000000000 X b00000000000000000000000000000000 Y b00000000000000000000000000000000 Z b00000000000000000000000000000000 [ b00000000000000000000000000000000 \ b00000000000000000000000000000000 ] b00000000000000000000000000000000 ^ b00000000000000000000000000000000 _ b00000000000000000000000000000000 ` b00000000000000000000000000000000 a b00000000000000000000000000000000 b b00000000000000000000000000000000 c #10 b00000000000000000000000000000010 & b00000010 ' b00000000000000000000000000000001 ) b00000000000000000000000000000001 + b00000000000000000000000000000001 - b00000000000000000000000000000001 / b00000000000000000000000000000001 1 b00000000000000000000000000000001 3 b00000000000000000000000000000001 5 b00000000000000000000000000000001 9 b00000000000000000000000000000001 < b00000000000000000000000000000001 > b00000000000000000000000000000001 @ b00000000000000000000000000000001 A b00000000000000000000000000000001 B b00000000000000000000000000000001 D b00000000000000000000000000000001 E b00000000000000000000000000000001 F b00000000000000000000000000000001 I b00000000000000000000000000000001 J b00000000000000000000000000000001 K b00000000000000000000000000000001 M b00000000000000000000000000000001 N b00000000000000000000000000000001 O b00000000000000000000000000000001 P b00000000000000000000000000000001 R b00000000000000000000000000000001 S b00000000000000000000000000000001 T b00000000000000000000000000000001 U b00000000000000000000000000000001 V 1W b00000000000000000000000000000001 Z b00000000000000000000000000000001 \ #15 0W #20 b00000000000000000000000000000011 & b00000011 ' b00000000000000000000000000000010 ) b00000000000000000000000000000010 + b00000000000000000000000000000010 - b00000000000000000000000000000010 / b00000000000000000000000000000010 1 b00000000000000000000000000000010 3 b00000000000000000000000000000010 5 b00000000000000000000000000000010 9 b00000000000000000000000000000010 < b00000000000000000000000000000010 > b00000000000000000000000000000010 @ b00000000000000000000000000000010 A b00000000000000000000000000000010 B b00000000000000000000000000000010 D b00000000000000000000000000000010 E b00000000000000000000000000000010 F b00000000000000000000000000000010 I b00000000000000000000000000000010 J b00000000000000000000000000000010 K b00000000000000000000000000000010 M b00000000000000000000000000000010 N b00000000000000000000000000000010 O b00000000000000000000000000000010 P b00000000000000000000000000000010 R b00000000000000000000000000000010 S b00000000000000000000000000000010 T b00000000000000000000000000000010 U b00000000000000000000000000000010 V 1W b00000000000000000000000000000010 Z b00000000000000000000000000000010 \ #25 0W #30 1% b00000000000000000000000000000100 & b00000100 ' b00000000000000000000000000000001 ( b00000000000000000000000000000001 * b00000000000000000000000000000001 , b00000000000000000000000000000001 . b00000000000000000000000000000001 0 b00000000000000000000000000000001 2 b00000000000000000000000000000001 7 b00000000000000000000000000000001 ; b00000000000000000000000000000011 < b00000000000000000000000000000011 > b00000000000000000000000000000011 @ b00000000000000000000000000000011 A b00000000000000000000000000000011 B b00000000000000000000000000000011 D b00000000000000000000000000000011 E b00000000000000000000000000000011 F b00000000000000000000000000000011 I b00000000000000000000000000000011 J b00000000000000000000000000000011 K b00000000000000000000000000000011 M b00000000000000000000000000000011 N b00000000000000000000000000000011 O b00000000000000000000000000000011 P b00000000000000000000000000000011 R b00000000000000000000000000000011 S b00000000000000000000000000000011 T b00000000000000000000000000000011 U b00000000000000000000000000000011 V 1W b00000000000000000000000000000011 Z b00000000000000000000000000000011 \ #35 0W #40 0% b00000000000000000000000000000101 & b00000101 ' b00000000000000000000000000000011 ) b00000000000000000000000000000011 + b00000000000000000000000000000011 - b00000000000000000000000000000011 / b00000000000000000000000000000011 1 b00000000000000000000000000000011 3 b00000000000000000000000000000001 6 b00000000000000000000000000000011 9 b00000000000000000000000000000100 < b00000000000000000000000000000100 > b00000000000000000000000000000001 ? b00000000000000000000000000000100 B b00000000000000000000000000000001 C b00000000000000000000000000000100 F b00000000000000000000000000000001 G b00000000000000000000000000000001 H b00000000000000000000000000000100 J b00000000000000000000000000000100 K b00000000000000000000000000000001 L b00000000000000000000000000000100 O b00000000000000000000000000000100 P b00000000000000000000000000000001 Q b00000000000000000000000000000100 T b00000000000000000000000000000100 U b00000000000000000000000000000100 V 1W b00000000000000000000000000000001 Y b00000000000000000000000000000100 \ #45 0W #50 b00000000000000000000000000000110 & b00000110 ' b00000000000000000000000000000100 ) b00000000000000000000000000000100 + b00000000000000000000000000000100 - b00000000000000000000000000000100 / b00000000000000000000000000000100 1 b00000000000000000000000000000100 3 b00000000000000000000000000000001 4 b00000000000000000000000000000001 : b00000000000000000000000000000101 < b00000000000000000000000000000101 > b00000000000000000000000000000100 @ b00000000000000000000000000000100 A b00000000000000000000000000000101 B b00000000000000000000000000000100 D b00000000000000000000000000000100 E b00000000000000000000000000000101 F b00000000000000000000000000000100 I b00000000000000000000000000000101 J b00000000000000000000000000000101 K b00000000000000000000000000000100 M b00000000000000000000000000000100 N b00000000000000000000000000000101 O b00000000000000000000000000000101 P b00000000000000000000000000000100 R b00000000000000000000000000000100 S b00000000000000000000000000000101 T b00000000000000000000000000000101 U b00000000000000000000000000000101 V 1W b00000000000000000000000000000001 X b00000000000000000000000000000101 Z b00000000000000000000000000000001 [ b00000000000000000000000000000110 \ #55 0W #60 b00000000000000000000000000000111 & b00000111 ' b00000000000000000000000000000101 ) b00000000000000000000000000000101 + b00000000000000000000000000000101 - b00000000000000000000000000000101 / b00000000000000000000000000000101 1 b00000000000000000000000000000101 3 b00000000000000000000000000000011 5 b00000000000000000000000000000100 9 b00000000000000000000000000000110 < b00000000000000000000000000000110 > b00000000000000000000000000000101 @ b00000000000000000000000000000101 A b00000000000000000000000000000110 B b00000000000000000000000000000101 D b00000000000000000000000000000101 E b00000000000000000000000000000110 F b00000000000000000000000000000101 I b00000000000000000000000000000110 J b00000000000000000000000000000110 K b00000000000000000000000000000101 M b00000000000000000000000000000101 N b00000000000000000000000000000110 O b00000000000000000000000000000110 P b00000000000000000000000000000101 R b00000000000000000000000000000101 S b00000000000000000000000000000110 T b00000000000000000000000000000110 U b00000000000000000000000000000110 V 1W b00000000000000000000000000000110 Z b00000000000000000000000000000111 \ #65 0W #70 b00000000000000000000000000001000 & b00001000 ' b00000000000000000000000000000110 ) b00000000000000000000000000000110 + b00000000000000000000000000000110 - b00000000000000000000000000000110 / b00000000000000000000000000000110 1 b00000000000000000000000000000110 3 b00000000000000000000000000000100 5 b00000000000000000000000000000101 9 b00000000000000000000000000000111 < b00000000000000000000000000000111 > b00000000000000000000000000000110 @ b00000000000000000000000000000110 A b00000000000000000000000000000111 B b00000000000000000000000000000110 D b00000000000000000000000000000110 E b00000000000000000000000000000111 F b00000000000000000000000000000110 I b00000000000000000000000000000111 J b00000000000000000000000000000111 K b00000000000000000000000000000110 M b00000000000000000000000000000110 N b00000000000000000000000000000111 O b00000000000000000000000000000111 P b00000000000000000000000000000110 R b00000000000000000000000000000110 S b00000000000000000000000000000111 T b00000000000000000000000000000111 U b00000000000000000000000000000111 V 1W b00000000000000000000000000000111 Z b00000000000000000000000000001000 \ #75 0W #80 b00000000000000000000000000001001 & b00001001 ' b00000000000000000000000000000111 ) b00000000000000000000000000000111 + b00000000000000000000000000000111 - b00000000000000000000000000000111 / b00000000000000000000000000000111 1 b00000000000000000000000000000111 3 b00000000000000000000000000000101 5 b00000000000000000000000000000110 9 b00000000000000000000000000001000 < b00000000000000000000000000001000 > b00000000000000000000000000000111 @ b00000000000000000000000000000111 A b00000000000000000000000000001000 B b00000000000000000000000000000111 D b00000000000000000000000000000111 E b00000000000000000000000000001000 F b00000000000000000000000000000111 I b00000000000000000000000000001000 J b00000000000000000000000000001000 K b00000000000000000000000000000111 M b00000000000000000000000000000111 N b00000000000000000000000000001000 O b00000000000000000000000000001000 P b00000000000000000000000000000111 R b00000000000000000000000000000111 S b00000000000000000000000000001000 T b00000000000000000000000000001000 U b00000000000000000000000000001000 V 1W b00000000000000000000000000001000 Z b00000000000000000000000000001001 \ #85 0W #90 b00000000000000000000000000001010 & b00001010 ' b00000000000000000000000000001000 ) b00000000000000000000000000001000 + b00000000000000000000000000001000 - b00000000000000000000000000001000 / b00000000000000000000000000001000 1 b00000000000000000000000000001000 3 b00000000000000000000000000000110 5 b00000000000000000000000000000111 9 b00000000000000000000000000001001 < b00000000000000000000000000001001 > b00000000000000000000000000001000 @ b00000000000000000000000000001000 A b00000000000000000000000000001001 B b00000000000000000000000000001000 D b00000000000000000000000000001000 E b00000000000000000000000000001001 F b00000000000000000000000000001000 I b00000000000000000000000000001001 J b00000000000000000000000000001001 K b00000000000000000000000000001000 M b00000000000000000000000000001000 N b00000000000000000000000000001001 O b00000000000000000000000000001001 P b00000000000000000000000000001000 R b00000000000000000000000000001000 S b00000000000000000000000000001001 T b00000000000000000000000000001001 U b00000000000000000000000000001001 V 1W b00000000000000000000000000001001 Z b00000000000000000000000000001010 \ #95 0W #100 b00000000000000000000000000001011 & b00001011 ' b00000000000000000000000000001001 ) b00000000000000000000000000001001 + b00000000000000000000000000001001 - b00000000000000000000000000001001 / b00000000000000000000000000001001 1 b00000000000000000000000000001001 3 b00000000000000000000000000000111 5 b00000000000000000000000000000001 8 b00000000000000000000000000001010 < b00000000000000000000000000001010 > b00000000000000000000000000001001 @ b00000000000000000000000000001001 A b00000000000000000000000000001010 B b00000000000000000000000000001001 D b00000000000000000000000000001001 E b00000000000000000000000000001010 F b00000000000000000000000000001001 I b00000000000000000000000000001010 J b00000000000000000000000000001010 K b00000000000000000000000000001001 M b00000000000000000000000000001001 N b00000000000000000000000000001010 O b00000000000000000000000000001010 P b00000000000000000000000000001001 R b00000000000000000000000000001001 S b00000000000000000000000000001010 T b00000000000000000000000000001010 U b00000000000000000000000000001010 V 1W b00000000000000000000000000001010 Z b00000000000000000000000000001011 \ verilator-4.038/test_regress/t/t_interface_gen4.pl0000775000177100017500000000106013702133370022224 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unpacked_array_order.pl0000775000177100017500000000105313702133370023534 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_packed_bad.out0000664000177100017500000000031713702133370022437 0ustar wsnyderwsnyder%Error: t/t_mem_packed_bad.v:27:32: CONST '28'h0' unexpected in assignment to unpacked array 27 | ch04 <= 56'd0; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_enum_type_methods_bad.v0000664000177100017500000000112713702133370023540 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, increment ); input clk; input [1:0] increment; typedef enum [3:0] { E01 = 1, E03 = 3, E04 = 4, E05 = 5 } my_t; my_t e; always @ (posedge clk) begin e.next(increment); $finish; end endmodule verilator-4.038/test_regress/t/t_vlcov_nfound_bad.out0000664000177100017500000000004113702133370023046 0ustar wsnyderwsnyder%Error: Can't read t/t_NOT_FOUND verilator-4.038/test_regress/t/t_class_name.out0000664000177100017500000000035313702133367021657 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_name.v:12:16: Unsupported: 'static' class method : ... In instance t 12 | static task static_name; | ^~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_class2.v0000664000177100017500000000174613702133367020406 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; typedef enum { ENUMP_VAL = 33 } enump_t; endpackage module t (/*AUTOARG*/); class Cls; int imembera; int imemberb; typedef enum { ENUM_VAL = 22 } enum_t; endclass : Cls Cls c; Cls d; initial begin // Alternate between two versions to make sure we don't // constant propagate between them. c = new; d = new; c.imembera = 10; d.imembera = 11; c.imemberb = 20; d.imemberb = 21; if (c.imembera != 10) $stop; if (d.imembera != 11) $stop; if (c.imemberb != 20) $stop; if (d.imemberb != 21) $stop; if (Pkg::ENUMP_VAL != 33) $stop; if (Cls::ENUM_VAL != 22) $stop; if (c.ENUM_VAL != 22) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_preproc_inc_recurse_bad.v0000664000177100017500000000037513702133370024047 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_preproc_inc_recurse_bad.v" verilator-4.038/test_regress/t/t_alias2_unsup.pl0000775000177100017500000000111313702133367021761 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_debug_sigsegv_bad.pl0000775000177100017500000000135513702133370023001 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB"); lint( v_flags => ["--debug-sigsegv"], fails => 1, expect => '%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt %Error: Command Failed.*', ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_modport_inl.pl0000775000177100017500000000130313702133370023715 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_modport.v"); compile( # Avoid inlining so we find bugs in the non-inliner connection code verilator_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_plus_mul_pow2.v0000664000177100017500000000241113702133370023345 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Conor McCullough. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [63:0] from = 64'h0706050403020100; reg [7:0] to; reg [2:0] bitn; reg [7:0] cyc; initial cyc=0; always @* begin to = from[bitn * 8 +: 8]; end always @ (posedge clk) begin cyc <= cyc + 8'd1; case (cyc) 8'd00: begin bitn<=3'd0; end 8'd01: begin bitn<=3'd1; end 8'd02: begin bitn<=3'd2; end 8'd03: begin bitn<=3'd3; end 8'd04: begin bitn<=3'd4; end 8'd05: begin bitn<=3'd5; end 8'd06: begin bitn<=3'd6; end 8'd07: begin bitn<=3'd7; end 8'd08: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase case (cyc) 8'd00: ; 8'd01: begin if (to !== 8'h00) $stop; end 8'd02: begin if (to !== 8'h01) $stop; end 8'd03: begin if (to !== 8'h02) $stop; end 8'd04: begin if (to !== 8'h03) $stop; end 8'd05: begin if (to !== 8'h04) $stop; end 8'd06: begin if (to !== 8'h05) $stop; end 8'd07: begin if (to !== 8'h06) $stop; end 8'd08: begin if (to !== 8'h07) $stop; end default: $stop; endcase end endmodule verilator-4.038/test_regress/t/t_dpi_imp_gen.pl0000775000177100017500000000112613702133370021624 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2011 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["t/t_dpi_imp_gen_c.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlt_syntax_bad.out0000664000177100017500000000052213702133370022563 0ustar wsnyderwsnyder%Error: t/t_vlt_syntax_bad.vlt:9:20: sensitivity not expected for attribute 9 | public -module "t" @(posedge clk) | ^ %Error: t/t_vlt_syntax_bad.vlt:10:1: isolate_assignments only applies to signals or functions/tasks 10 | isolate_assignments -module "t" | ^~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_inst_array_bad.v0000664000177100017500000000121113702133370022155 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [7:0] bitout; reg [7:0] allbits; reg [7:0] onebit; reg [8:0] onebitbad; // Wrongly sized sub sub [7:0] (allbits, onebitbad, bitout); // This is ok. wire [9:8] b; wire [1:0] c; sub sub2 [9:8] (allbits,b,c); endmodule module sub (input [7:0] allbits, input onebit, output bitout); assign bitout = onebit ^ (^ allbits); endmodule verilator-4.038/test_regress/t/t_trace_cat_renew_0000.out0000664000177100017500000000533213702133370023332 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Thu Aug 30 16:11:06 2018 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # 1$ #1 0$ #2 b00000000000000000000000000000001 # 1$ #3 0$ #4 b00000000000000000000000000000010 # 1$ #5 0$ #6 b00000000000000000000000000000011 # 1$ #7 0$ #8 b00000000000000000000000000000100 # 1$ #9 0$ #10 b00000000000000000000000000000101 # 1$ #11 0$ #12 b00000000000000000000000000000110 # 1$ #13 0$ #14 b00000000000000000000000000000111 # 1$ #15 0$ #16 b00000000000000000000000000001000 # 1$ #17 0$ #18 b00000000000000000000000000001001 # 1$ #19 0$ #20 b00000000000000000000000000001010 # 1$ #21 0$ #22 b00000000000000000000000000001011 # 1$ #23 0$ #24 b00000000000000000000000000001100 # 1$ #25 0$ #26 b00000000000000000000000000001101 # 1$ #27 0$ #28 b00000000000000000000000000001110 # 1$ #29 0$ #30 b00000000000000000000000000001111 # 1$ #31 0$ #32 b00000000000000000000000000010000 # 1$ #33 0$ #34 b00000000000000000000000000010001 # 1$ #35 0$ #36 b00000000000000000000000000010010 # 1$ #37 0$ #38 b00000000000000000000000000010011 # 1$ #39 0$ #40 b00000000000000000000000000010100 # 1$ #41 0$ #42 b00000000000000000000000000010101 # 1$ #43 0$ #44 b00000000000000000000000000010110 # 1$ #45 0$ #46 b00000000000000000000000000010111 # 1$ #47 0$ #48 b00000000000000000000000000011000 # 1$ #49 0$ #50 b00000000000000000000000000011001 # 1$ #51 0$ #52 b00000000000000000000000000011010 # 1$ #53 0$ #54 b00000000000000000000000000011011 # 1$ #55 0$ #56 b00000000000000000000000000011100 # 1$ #57 0$ #58 b00000000000000000000000000011101 # 1$ #59 0$ #60 b00000000000000000000000000011110 # 1$ #61 0$ #62 b00000000000000000000000000011111 # 1$ #63 0$ #64 b00000000000000000000000000100000 # 1$ #65 0$ #66 b00000000000000000000000000100001 # 1$ #67 0$ #68 b00000000000000000000000000100010 # 1$ #69 0$ #70 b00000000000000000000000000100011 # 1$ #71 0$ #72 b00000000000000000000000000100100 # 1$ #73 0$ #74 b00000000000000000000000000100101 # 1$ #75 0$ #76 b00000000000000000000000000100110 # 1$ #77 0$ #78 b00000000000000000000000000100111 # 1$ #79 0$ #80 b00000000000000000000000000101000 # 1$ #81 0$ #82 b00000000000000000000000000101001 # 1$ #83 0$ #84 b00000000000000000000000000101010 # 1$ #85 0$ #86 b00000000000000000000000000101011 # 1$ #87 0$ #88 b00000000000000000000000000101100 # 1$ #89 0$ #90 b00000000000000000000000000101101 # 1$ #91 0$ #92 b00000000000000000000000000101110 # 1$ #93 0$ #94 b00000000000000000000000000101111 # 1$ #95 0$ #96 b00000000000000000000000000110000 # 1$ #97 0$ #98 b00000000000000000000000000110001 # 1$ #99 0$ verilator-4.038/test_regress/t/t_class_virtual_pure.out0000664000177100017500000000046413702133367023463 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_virtual_pure.v:8:22: Unsupported: 'virtual' class method 8 | pure virtual task hello(); | ^~~~~ %Error-UNSUPPORTED: t/t_class_virtual_pure.v:7:9: Unsupported: virtual class 7 | virtual class VC; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_case_string.pl0000775000177100017500000000105313702133367021660 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_future_bad.out0000664000177100017500000000107313702133370022655 0ustar wsnyderwsnyder%Error: t/t_flag_future.v:8:7: Unknown verilator lint message code: 'FUTURE1', in '/*verilator lint_off FUTURE1*/' 8 | /*verilator lint_off FUTURE1*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_flag_future.v:11:7: Unknown verilator comment: '/*verilator FUTURE2*/' 11 | /*verilator FUTURE2*/ | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_flag_future.v:12:7: Unknown verilator comment: '/*verilator FUTURE2 blah blah*/' 12 | /*verilator FUTURE2 blah blah*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_typedef_circ_bad.v0000664000177100017500000000040513702133370022446 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef a_t; typedef a_t b_t; typedef b_t a_t; verilator-4.038/test_regress/t/t_select_bad_tri.v0000664000177100017500000000053513702133370022147 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg [72:1] in; initial begin if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; end endmodule verilator-4.038/test_regress/t/t_enum_x_bad.pl0000775000177100017500000000107413702133370021455 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_array.v0000664000177100017500000000423013702133370021476 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); typedef enum int { PADTYPE_DEFAULT = 32'd0, PADTYPE_GPIO, PADTYPE_VDD, PADTYPE_GND } t_padtype; localparam int STR_PINID [0:15] = '{ "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" }; typedef struct packed { t_padtype padtype; int aux; } t_pin_descriptor; localparam t_pin_descriptor PINOUT[ 1: 6] = '{ '{default:0, padtype:PADTYPE_GPIO, aux:1}, '{default:0, padtype:PADTYPE_GPIO}, '{default:0, padtype:PADTYPE_GPIO}, '{default:0, padtype:PADTYPE_GPIO}, '{default:0, padtype:PADTYPE_VDD}, '{default:0, padtype:PADTYPE_GND} }; localparam int PINOUT_SIZE = 6; localparam int PINOUT_WA[1:PINOUT_SIZE][3] = '{ '{0, PADTYPE_GPIO, 0}, '{1, PADTYPE_GPIO, 0}, '{2, PADTYPE_GPIO, 0}, '{5, PADTYPE_GPIO, 0}, '{6, PADTYPE_VDD, 0}, '{8, PADTYPE_GND , 0} }; const int pinout_static_const[1:PINOUT_SIZE][3] = '{ '{0, PADTYPE_GPIO, 0}, '{1, PADTYPE_GPIO, 0}, '{2, PADTYPE_GPIO, 0}, '{5, PADTYPE_GPIO, 0}, '{6, PADTYPE_VDD, 0}, '{8, PADTYPE_GND , 0} }; // Make sure consants propagate checkstr #(.PINID(STR_PINID[1]), .EXP("ERR")) substr1 (); checkstr #(.PINID(STR_PINID[8]), .EXP("PA0")) substr8 (); initial begin $display("PINID1 %s", STR_PINID[1]); $display("PINID8 %s", STR_PINID[8]); if (STR_PINID[1] != "ERR") $stop; if (STR_PINID[8] != "PA0") $stop; if (pinout_static_const[1][0] != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module checkstr; parameter int PINID = " "; parameter int EXP = " "; initial begin $display("PID %s EXP %s", PINID, EXP); if (EXP != "ERR" && EXP != "PA0") $stop; if (PINID != EXP) $stop; end endmodule verilator-4.038/test_regress/t/t_math_width.pl0000775000177100017500000000105313702133370021501 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_port_bad.out0000664000177100017500000000023313702133370022203 0ustar wsnyderwsnyder%Error: t/t_var_port_bad.v:16:13: Input/output/inout does not appear in port list: 'b' 16 | input a, b; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_void_bad.v0000664000177100017500000000132713702133370021766 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; int side_effect; function int f1; input int in; f1 = in + 1; side_effect += in + 1; endfunction initial begin int got; side_effect = 1; // got = f1(10); if (got != 11) $stop; if (side_effect != 12) $stop; // f1(20); if (side_effect != 33) $stop; // // void'f1(30); // if (side_effect != 64) $stop; // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_if_blk.pl0000775000177100017500000000105313702133370021757 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_kwd.pl0000775000177100017500000000105313702133370021670 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_slice.pl0000775000177100017500000000105313702133370021505 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_array_inl0.pl0000775000177100017500000000117613702133370022454 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_array.v"); compile( v_flags2 => ['+define+NOUSE_INLINE',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_unpacked.v0000664000177100017500000000106713702133370022403 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module x; // verilator lint_off UNPACKED typedef struct { int a; } notpacked_t; // verilator lint_on UNPACKED typedef struct packed { notpacked_t b; } ispacked_t; ispacked_t p; initial begin p.b = 1; if (p.b != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_inst_misarray2_bad.out0000664000177100017500000000052013702133370023314 0ustar wsnyderwsnyder%Error: t/t_inst_misarray2_bad.v:10:17: Illegal input port connection 'i_data', mismatch between port which is not an array, and expression which is an array. (IEEE 1800-2017 7.6) : ... In instance t 10 | .i_data(fft_oQ[6:0]) | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_extend_class_c.h0000664000177100017500000000101713702133370022140 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006-2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class t_extend_class_c { public: // CONSTRUCTORS t_extend_class_c() {} ~t_extend_class_c() {} // METHODS // This function will be called from a instance created in Verilog inline vluint32_t my_math(vluint32_t in) { return in + 1; } }; verilator-4.038/test_regress/t/t_leak.v0000664000177100017500000000103013702133370020107 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); sub sub (); input clk; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==2) begin // Not $finish; as we don't want a message to scroll by $c("Verilated::gotFinish(true);"); end end endmodule module sub; /* verilator public_module */ endmodule verilator-4.038/test_regress/t/t_func_crc.pl0000775000177100017500000000120413702133370021131 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_for_break.pl0000775000177100017500000000105313702133370021303 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_shortreal_unsup_bad.pl0000775000177100017500000000107413702133370024430 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_mod_paren_bad.out0000664000177100017500000000021013702133370023334 0ustar wsnyderwsnyder%Error: t/t_lint_mod_paren_bad.v:13:6: syntax error, unexpected '(', expecting ';' 13 | ) ( | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_wire_behp1800_bad.out0000664000177100017500000000134113702133370022625 0ustar wsnyderwsnyder%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' : ... In instance t 23 | w = '0; | ^ %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 24 | o = '0; | ^ %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' : ... In instance t 25 | oa = '0; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_dpi_export_bad.pl0000775000177100017500000000107113702133370022334 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_init.pl0000775000177100017500000000105313702133370021164 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_typedef_circ_bad.out0000664000177100017500000000021013702133370023002 0ustar wsnyderwsnyder%Error: t/t_typedef_circ_bad.v:8:9: Typedef's type is circular: a_t 8 | typedef a_t b_t; | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_unopt_converge_unopt_bad.out0000664000177100017500000000075113702133370024636 0ustar wsnyderwsnyder%Warning-UNOPT: t/t_unopt_converge.v:19:11: Signal unoptimizable: Feedback to public clock or circular logic: 'x' 19 | output x; | ^ ... Use "/* verilator lint_off UNOPT */" and lint_on around source to disable this message. t/t_unopt_converge.v:19:11: Example path: x t/t_unopt_converge.v:22:4: Example path: ALWAYS t/t_unopt_converge.v:19:11: Example path: x %Error: Exiting due to verilator-4.038/test_regress/t/t_tri_array.pl0000775000177100017500000000127413702133370021352 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # When fix, update ifdefs in t_sv_cpu files; search for t_tri_array $Self->{vlt_all} and unsupported("Verilator unsupported, tristate arrays"); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_backw_index_bad.pl0000775000177100017500000000107413702133367023644 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_outoforder.pl0000775000177100017500000000105313702133370022411 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_yosys.v0000664000177100017500000000514313702133370021403 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Claire Wolf. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] y1; // From d1 of demo_001.v wire [7:0] y2; // From d1 of demo_001.v wire [7:0] y3; // From d1 of demo_001.v wire [7:0] y4; // From d1 of demo_001.v wire [31:0] z0; // From d2 of demo_002.v wire [31:0] z1; // From d2 of demo_002.v wire [31:0] z2; // From d2 of demo_002.v wire [31:0] z3; // From d2 of demo_002.v // End of automatics demo_001 d1(/*AUTOINST*/ // Outputs .y1 (y1[7:0]), .y2 (y2[7:0]), .y3 (y3[7:0]), .y4 (y4[7:0])); demo_002 d2(/*AUTOINST*/ // Outputs .z0 (z0[31:0]), .z1 (z1[31:0]), .z2 (z2[31:0]), .z3 (z3[31:0])); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (y1 !== 8'h7b) $stop; if (y2 !== 8'h7c) $stop; if (y3 !== 8'h7b) $stop; if (y4 !== 8'h7c) $stop; if (z0 !== 32'h00000000) $stop; if (z1 !== 32'hffffffff) $stop; if (z2 !== 32'hffffffff) $stop; if (z3 !== 32'hffffffff) $stop; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module demo_001(y1, y2, y3, y4); output [7:0] y1, y2, y3, y4; // verilator lint_off REALCVT localparam [7:0] p1 = 123.45; localparam real p2 = 123.45; localparam real p3 = 123; localparam p4 = 123.45; // verilator lint_off WIDTH assign y1 = p1 + 0.2; assign y2 = p2 + 0.2; assign y3 = p3 + 0.2; assign y4 = p4 + 0.2; // verilator lint_on WIDTH endmodule module demo_002(z0, z1, z2, z3); output [31:0] z0, z1, z2, z3; // verilator lint_off WIDTH assign z0 = 1'bx >= (-1 * -1.17); // verilator lint_on WIDTH assign z1 = 1 ? 1 ? -1 : 'd0 : 0.0; assign z2 = 1 ? -1 : 1 ? 'd0 : 0.0; assign z3 = 1 ? -1 : 'd0; endmodule verilator-4.038/test_regress/t/t_trace_public_sig.pl0000775000177100017500000000165013702133370022652 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_trace_public.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["-DATTRIBUTES --trace --exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", "t/t_trace_public.out"); # vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" file_grep("$Self->{obj_dir}/simx.vcd", qr/module glbl/i); ok(1); 1; verilator-4.038/test_regress/t/t_math_signed_wire.v0000664000177100017500000000207013702133370022510 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug511 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [7:0] au; wire [7:0] as; Test1 test1 (.au); Test2 test2 (.as); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] result=%x %x\n",$time, au, as); `endif if (au != 'h12) $stop; if (as != 'h02) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test1 (output [7:0] au); wire [7:0] b; wire signed [3:0] c; // verilator lint_off WIDTH assign c=-1; // 'hf assign b=3; // 'h3 assign au=b+c; // 'h12 // verilator lint_on WIDTH endmodule module Test2 (output [7:0] as); wire signed [7:0] b; wire signed [3:0] c; // verilator lint_off WIDTH assign c=-1; // 'hf assign b=3; // 'h3 assign as=b+c; // 'h12 // verilator lint_on WIDTH endmodule verilator-4.038/test_regress/t/t_lint_importstar_bad.out0000664000177100017500000000044713702133370023610 0ustar wsnyderwsnyder%Warning-IMPORTSTAR: t/t_lint_importstar_bad.v:11:12: Import::* in $unit scope may pollute global namespace 11 | import defs::*; | ^~ ... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_clk_latch.v0000664000177100017500000000626113702133367021140 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs fastclk, clk ); `ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge `define posstyle posedge `define negstyle negedge `else `define posstyle `define negstyle `endif input fastclk; input clk; reg [7:0] data; reg [7:0] data_a; reg [7:0] data_a_a; reg [7:0] data_a_b; reg [7:0] data_b; reg [7:0] data_b_a; reg [7:0] data_b_b; reg [8*6-1:0] check [100:0]; wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b}; initial begin check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; end // verilator lint_off COMBDLY always @ (`posstyle clk /*AS*/ or data) begin if (clk) begin data_a <= data + 8'd1; end end always @ (`posstyle clk /*AS*/ or data_a) begin if (clk) begin data_a_a <= data_a + 8'd1; end end always @ (`posstyle clk /*AS*/ or data_b) begin if (clk) begin data_b_a <= data_b + 8'd1; end end always @ (`negstyle clk /*AS*/ or data or data_a) begin if (~clk) begin data_b <= data + 8'd1; data_a_b <= data_a + 8'd1; data_b_b <= data_b + 8'd1; end end integer cyc; initial cyc=0; always @ (posedge fastclk) begin cyc <= cyc+1; `ifdef TEST_VERBOSE $write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b); `endif if (cyc>=19 && cyc<36) begin if (compare !== check[cyc]) begin $write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]); $stop; end end if (cyc == 10) begin data <= 8'd12; end if (cyc == 20) begin data <= 8'd20; end if (cyc == 30) begin data <= 8'd30; end if (cyc == 40) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_gen_forif.v0000664000177100017500000000451113702133370021140 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; wire [3:0] Value = crc[3:0]; wire [3:0] Result; wire [3:0] Result2; Testit testit (/*AUTOINST*/ // Outputs .Result (Result[3:0]), .Result2 (Result2[3:0]), // Inputs .clk (clk), .Value (Value[3:0])); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= {56'h0, Result, Result2} ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== 64'h4af37965592f64f9) $stop; $finish; end end endmodule module Test (clk, Value, Result); input clk; input Value; output Result; reg Internal; assign Result = Internal ^ clk; always @(posedge clk) Internal <= #1 Value; endmodule module Test_wrap1 (clk, Value, Result); input clk; input Value; output Result; Test t (clk, Value, Result); endmodule module Test_wrap2 (clk, Value, Result); input clk; input Value; output Result; Test t (clk, Value, Result); endmodule module Testit (clk, Value, Result, Result2); input clk; input [3:0] Value; output [3:0] Result; output [3:0] Result2; genvar i; generate for (i = 0; i < 4; i = i + 1) begin : a if ((i == 0) || (i == 2)) begin : gblk Test_wrap1 test (clk, Value[i] , Result[i]); end else begin : gblk Test_wrap2 test (clk, Value[i], Result[i]); end end endgenerate assign Result2[0] = a[0].gblk.test.t.Internal; assign Result2[1] = a[1].gblk.test.t.Internal; assign Result2[2] = a[2].gblk.test.t.Internal; assign Result2[3] = a[3].gblk.test.t.Internal; endmodule verilator-4.038/test_regress/t/t_mem_banks.v0000664000177100017500000000346413702133370021144 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg [5:0] addr; parameter BANKS = 6; parameter ROWS = 8; wire [2:0] bank; wire [2:0] row; integer a; integer used[BANKS][ROWS]; // Test loop initial begin for (a = 0; a < BANKS*ROWS; ++a) begin addr[5:0] = a[5:0]; hash (addr, bank, row); used [bank][row] ++; if (used [bank][row] > 1) begin $write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row); end end $write("*-* All Finished *-*\n"); $finish; end task hash (input [5:0] addr, output [2:0] bank, output [2:0] row); reg [1:0] third; reg [1:0] fourth; third = {addr[5], addr[4]}; fourth = {addr[3] ^ addr[1], addr[2] ^ addr[0]}; case (third) 2'h0: case (fourth) 2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end 2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end 2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end 2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end endcase 2'h1: case (fourth) 2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end 2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end 2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end 2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end endcase 2'h2: case (fourth) 2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end 2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end 2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end 2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end endcase 2'h3: $stop; endcase endtask endmodule verilator-4.038/test_regress/t/t_sys_readmem_assoc_bad.v0000664000177100017500000000071313702133370023510 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [5:0] assoc_bad_key[real]; real assoc_bad_value[int]; initial begin $readmemb("not", assoc_bad_key); $readmemb("not", assoc_bad_value); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_ceil.pl0000775000177100017500000000105313702133370021445 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_zero_time_cb.cpp0000664000177100017500000001252013702133370023035 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #else #include "Vt_vpi_zero_time_cb.h" #include "verilated.h" #include "svdpi.h" #include #include "Vt_vpi_zero_time_cb__Dpi.h" #include "verilated_vpi.h" #include "verilated_vcd_c.h" #endif #include #include #include #include #include "TestSimulator.h" #include "TestVpi.h" #define TEST_MSG \ if (0) printf unsigned int main_time = 0; unsigned int callback_count_zero_time = 0; unsigned int callback_count_start_of_sim = 0; //====================================================================== #define CHECK_RESULT_VH(got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d: GOT = %p EXP = %p\n", __FILE__, __LINE__, (got), (exp)); \ return __LINE__; \ } #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", __FILE__, __LINE__); \ return __LINE__; \ } // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_HEX(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << hex \ << ": GOT = " << (got) << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", __FILE__, __LINE__, \ (got) ? (got) : "", (exp) ? (exp) : ""); \ return __LINE__; \ } #define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp) //====================================================================== #ifdef IS_VPI static int _zero_time_cb(p_cb_data cb_data) { callback_count_zero_time++; return 0; } static int _start_of_sim_cb(p_cb_data cb_data) { t_cb_data cb_data_n; bzero(&cb_data_n, sizeof(cb_data_n)); s_vpi_time t; cb_data_n.reason = cbAfterDelay; t.type = vpiSimTime; t.high = 0; t.low = 0; cb_data_n.time = &t; cb_data_n.cb_rtn = _zero_time_cb; vpi_register_cb(&cb_data_n); callback_count_start_of_sim++; return 0; } static int _end_of_sim_cb(p_cb_data cb_data) { CHECK_RESULT(callback_count_start_of_sim, 1); CHECK_RESULT(callback_count_zero_time, 1); fprintf(stdout, "*-* All Finished *-*\n"); return 0; } // cver entry #ifdef __cplusplus extern "C" #endif void vpi_compat_bootstrap(void) { t_cb_data cb_data; bzero(&cb_data, sizeof(cb_data)); // VL_PRINTF("register start-of-sim callback\n"); cb_data.reason = cbStartOfSimulation; cb_data.time = 0; cb_data.cb_rtn = _start_of_sim_cb; vpi_register_cb(&cb_data); cb_data.reason = cbEndOfSimulation; cb_data.time = 0; cb_data.cb_rtn = _end_of_sim_cb; vpi_register_cb(&cb_data); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out #ifdef VERILATOR # ifdef TEST_VERBOSE Verilated::scopesDump(); # endif #endif #if VM_TRACE Verilated::traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif // Load and initialize the PLI application { const char* filenamep = VL_STRINGIFY(TEST_OBJ_DIR) "/libvpi.so"; void* lib = dlopen(filenamep, RTLD_LAZY); void* bootstrap = dlsym(lib, "vpi_compat_bootstrap"); if (!bootstrap) { std::string msg = std::string("%Error: Could not dlopen ") + filenamep; vl_fatal(__FILE__, __LINE__, "main", msg.c_str()); } ((void (*)(void))bootstrap)(); } VerilatedVpi::callCbs(cbStartOfSimulation); topp->eval(); topp->clk = 0; main_time += 1; while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += 1; topp->eval(); VerilatedVpi::callValueCbs(); VerilatedVpi::callTimedCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } VerilatedVpi::callCbs(cbEndOfSimulation); if (!Verilated::gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete topp, topp); exit(0L); } #endif verilator-4.038/test_regress/t/t_past_unsup_bad.pl0000775000177100017500000000107113702133370022360 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_chg_first.v0000664000177100017500000000337413702133367021166 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, fastclk ); input clk; input fastclk; // surefire lint_off_line UDDIXN integer _mode; initial _mode=0; reg [31:0] ord1; initial ord1 = 32'h1111; wire [31:0] ord2; reg [31:0] ord3; wire [31:0] ord4; wire [31:0] ord5; wire [31:0] ord6; wire [31:0] ord7; // verilator lint_off UNOPT t_chg_a a ( .a(ord1), .a_p1(ord2), .b(ord4), .b_p1(ord5), .c(ord3), .c_p1(ord4), .d(ord6), .d_p1(ord7) ); // surefire lint_off ASWEMB assign ord6 = ord5 + 1; // verilator lint_on UNOPT always @ (/*AS*/ord2) ord3 = ord2 + 1; always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR if (_mode==1) begin //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n",$time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); //if (ord2 == 2 && ord7 != 7) $stop; end end always @ (posedge clk) begin if (_mode==0) begin $write("[%0t] t_chg: Running\n", $time); _mode<=1; ord1 <= 1; end else if (_mode==1) begin _mode<=2; if (ord7 !== 7) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_chg_a (/*AUTOARG*/ // Outputs a_p1, b_p1, c_p1, d_p1, // Inputs a, b, c, d ); input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1; input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1; input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1; input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1; endmodule verilator-4.038/test_regress/t/t_time_vpi.v0000664000177100017500000000323713702133370021022 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale `time_scale_units / `time_scale_prec import "DPI-C" function void dpii_check(); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; // verilator lint_off REALCVT time digits = 5432109876.543210ns; // Will round to time units realtime rdigits = 5432109876.543210ns; // Will round to time precision // verilator lint_on REALCVT always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("- [%0t] tick\n", $time); `endif if ($time >= 60) begin $write(":: In %m\n"); $printtimescale; $write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123); $write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits); $write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits); $timeformat(-9, 6, "ns", 16); $write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123); $write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits); $write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits); $write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n", $time, $stime, $stime, $stime); // verilator lint_off REALCVT $write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n", $time, $realtime, $realtime, $realtime); // verilator lint_on REALCVT dpii_check(); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_interface_down_inlab.pl0000775000177100017500000000125513702133370023511 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_A +define+INLINE_B'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_concat.vlt0000664000177100017500000000044313702133367021650 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config clocker -module "t" -var "clk*" no_clocker -module "t" -var "data_in" verilator-4.038/test_regress/t/t_lint_unused_iface.pl0000775000177100017500000000107113702133370023031 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_inherit.pl0000775000177100017500000000100113702133370022032 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_display_merge.out0000664000177100017500000000046013702133370022367 0ustar wsnyderwsnyderMerge: This should merge f a=top.t b=top.t pre t=0 t2=0 post t3=0 t4=0 t5=0 0 m t=0 t2=0 t3=0 t4=0 t5=0 t=0 t2=0 t3=0 t4=0 t5=0 mm f a=top.t b=top.t pre t=0 t2=0 post t3=0 t4=0 t5=0 0m t=0 t2=0 t3=0 t4=0 t5=0 t=0 t2=0 t3=0 t4=0 t5=0mm *-* All Finished *-* verilator-4.038/test_regress/t/t_pp_circdef_bad.pl0000775000177100017500000000117213702216710022257 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, # EOF result varies with Bison version, so can't use .out expect => qr/define or other nested inclusion/, ); ok(1); 1; verilator-4.038/test_regress/t/t_cdc_async_bad.pl0000775000177100017500000000135213702133367022115 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( v_flags => ['--cdc'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, fails => 1, expect_filename => $Self->{golden_filename}, ); file_grep("$Self->{obj_dir}/V$Self->{name}__cdc.txt", qr/CDC Report/); ok(1); 1; verilator-4.038/test_regress/t/t_flag_xinitial_unique.pl0000775000177100017500000000125113702133370023551 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( verilator_flags2 => ["--x-initial unique"], ); execute( check_finished => 1, ); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}__Slow.cpp", qr/VL_RAND_RESET/); ok(1); 1; verilator-4.038/test_regress/t/t_flag_build_bad.pl0000775000177100017500000000136213702133370022252 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ["--build --make gmake"], fails => 1, expect_filename => $Self->{golden_filename}, ); compile( verilator_flags2 => ["--build --make cmake"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_concat2.v0000664000177100017500000000340313702133367021371 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input wrclk ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (wrclk) some_other_state <= 0; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( `ifdef BROKEN .wrclk (i_clks[3]) `else .wrclk (i_clk1) `endif ); endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; assign the_clks[3] = i_clk1; assign the_clks[2] = i_clk2; assign the_clks[1] = i_clk1; assign the_clks[0] = i_clk0; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( /*AUTOARG*/ // Inputs clk /*verilator clocker*/, input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); input clk; logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk), .i_clk2 (clk2), .i_data (data_in) ); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_imm.pl0000775000177100017500000000120413702133370021142 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_udp_noname.out0000664000177100017500000000023613702133370021671 0ustar wsnyderwsnyder%Error: t/t_udp_noname.v:15:8: syntax error, unexpected '(', expecting IDENTIFIER or randomize 15 | udp (o, a); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_class_null_bad.out0000664000177100017500000000010713702133367022514 0ustar wsnyderwsnyder%Error: t/t_class_null_bad.v:15: Null pointer dereferenced Aborting... verilator-4.038/test_regress/t/t_var_notfound_bad.out0000664000177100017500000000233013702133370023053 0ustar wsnyderwsnyder%Error: t/t_var_notfound_bad.v:18:7: Can't find definition of variable: 'nf' 18 | nf = 0; | ^~ %Error: t/t_var_notfound_bad.v:19:11: Can't find definition of 'subsubz' in dotted scope/variable: 'sub.subsubz' 19 | sub.subsubz.inss = 0; | ^~~~~~~ ... Known scopes under 'sub': subsub %Error: t/t_var_notfound_bad.v:20:11: Can't find definition of task/function: 'nofunc' : ... Suggested alternative: 'notfunc' 20 | i = nofunc(); | ^~~~~~ %Error: t/t_var_notfound_bad.v:21:15: Can't find definition of 'nofuncs' in dotted task/function: 'sub.nofuncs' : ... Suggested alternative: 'notfuncs' 21 | i = sub.nofuncs(); | ^~~~~~~ ... Known scopes under 'nofuncs': sub %Error: t/t_var_notfound_bad.v:22:7: Can't find definition of task/function: 'notask' : ... Suggested alternative: 'nottask' 22 | notask(); | ^~~~~~ %Error: t/t_var_notfound_bad.v:23:7: Found definition of 'a_var' as a VAR but expected a task/function 23 | a_var(); | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_noinl.v0000664000177100017500000000506213702133370021336 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; wire [31:0] inp = crc[31:0]; wire reset = (cyc < 5); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] outp; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .outp (outp[31:0]), // Inputs .reset (reset), .clk (clk), .inp (inp[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, outp}; // What checksum will we end up with `define EXPECTED_SUM 64'ha7f0a34f9cf56ccb // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs outp, // Inputs reset, clk, inp ); input reset; input clk; input [31:0] inp; output [31:0] outp; function [31:0] no_inline_function; input [31:0] var1; input [31:0] var2; /*verilator no_inline_task*/ reg [31*2:0] product1 ; reg [31*2:0] product2 ; integer i; reg [31:0] tmp; begin product2 = {(31*2+1){1'b0}}; for (i = 0; i < 32; i = i + 1) if (var2[i]) begin product1 = { {31*2+1-32{1'b0}}, var1} << i; product2 = product2 ^ product1; end no_inline_function = 0; for (i= 0; i < 31; i = i + 1 ) no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i]; end endfunction reg [31:0] outp; reg [31:0] inp_d; always @( posedge clk ) begin if( reset ) begin outp <= 0; end else begin inp_d <= inp; outp <= no_inline_function(inp, inp_d); end end endmodule verilator-4.038/test_regress/t/t_param_bracket.v0000664000177100017500000000065613702133370022003 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder; // SPDX-License-Identifier: CC0-1.0 module t #(parameter WIDTH = 8) (/*AUTOARG*/ // Outputs o ); output [WIDTH-1:0] o; localparam DEPTH = $clog2(5); // Note single bracket below reg [WIDTH-1:0] arid [1< 1); # This is a compile only test. compile( v_flags2 => ["+1364-2005ext+v"], ); ok(1); 1; verilator-4.038/test_regress/t/t_var_local.v0000664000177100017500000000177513702133370021155 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer top; integer top_assign=1; task automatic tsk; integer task_assign = 1; if (task_assign != 1) $stop; task_assign = 2; if (task_assign != 2) $stop; endtask initial begin begin : a integer lower; integer lower_assign=1; lower = 1; top = 1; if (lower != 1) $stop; if (lower_assign != 1) $stop; begin : aa integer lev2; lev2 = 1; lower = 2; lower_assign = 2; top = 2; end if (lower != 2) $stop; if (lower_assign != 2) $stop; end begin : b integer lower; lower = 1; top = 2; begin : empty begin : empty end end end tsk; tsk; // Second time to ensure we reinit the initial value $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_preproc_ttempty.out0000664000177100017500000000002113555673107023011 0ustar wsnyderwsnyder `TARGET_PACKAGE verilator-4.038/test_regress/t/t_struct_unaligned.v0000664000177100017500000000136513702133370022560 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: // Test an error where a shift amount was out of bounds and the compiler treats the // value as undefined (Issue #803) // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jeff Bush. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; struct packed { logic flag; logic [130:0] data; } foo[1]; integer cyc=0; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; foo[0].data <= 0; foo[0].flag <= !foo[0].flag; if (cyc==10) begin if (foo[0].data != 0) begin $display("bad data value %x", foo[0].data); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_struct_init_trace.pl0000775000177100017500000000117613702133370023104 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_struct_init.v"); compile( verilator_flags2 => ['--cc --trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_begin2.v0000664000177100017500000000156513702133370021371 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module init; task t1; reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; reg ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz; reg da,db,dc,dd,de,df,dg,dh,di,dj,dk,dl,dm,dn, dp,dq,dr,ds,dt,du,dv,dw,dx,dy,dz; begin : READER $display ("Time: %0t Instance: %m", $time); end endtask task t2; reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; begin : READER $display ("Time: %0t Instance: %m", $time); end endtask endmodule module test(); init u_ram1(); init u_ram2(); endmodule verilator-4.038/test_regress/t/t_vlt_syntax_bad.vlt0000664000177100017500000000045313702133370022564 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config public -module "t" @(posedge clk) isolate_assignments -module "t" verilator-4.038/test_regress/t/t_dpi_export_context_bad.pl0000775000177100017500000000125613702133370024105 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["--exe $Self->{t_dir}/t_dpi_export_context_bad.cpp"], make_main => 0, ); execute( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_long_bad.pl0000775000177100017500000000311313702133370022152 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use strict; use vars qw($Self); scenarios(vlt => 1); my $length = 200; my $long = "long_" x (($length + 4) / 5); sub gen_top { my $filename = shift; my $fh = IO::File->new(">$filename") or $Self->error("Can't write $filename"); $fh->print("// Generated by t_inst_long.pl\n"); $fh->print("module t;\n"); $fh->print("\n"); $fh->print(" ${long} inst ();\n"); $fh->print("\n"); $fh->print("endmodule\n"); $fh->close; } sub gen_sub { my $filename = shift; my $fh = IO::File->new(">$filename") or $Self->error("Can't write $filename"); $fh->print("// Generated by t_inst_long.pl\n"); $fh->print("module ${long};\n"); $fh->print("\n"); $fh->print(" initial begin\n"); $fh->print(" \$write(\"*-* All Finished *-*\\n\");\n"); $fh->print(" \$finish;\n"); $fh->print(" end\n"); $fh->print("endmodule\n"); $fh->close; } top_filename("$Self->{obj_dir}/t_inst_long.v", $long); gen_top($Self->{top_filename}); gen_sub("$Self->{obj_dir}/${long}.v"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_inconly.v0000664000177100017500000000077513702133370021700 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; task main; integer varintask; varintask = 0; while (varintask < 4) begin varintask = varintask + 1; end if (varintask != 4) $stop; endtask initial begin main; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_package_export.pl0000775000177100017500000000121313702133370022343 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vcs} and unsupported("VCS unsupported"); compile( v_flags2 => ['+define+T_PACKAGE_EXPORT',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dynarray_bad.out0000664000177100017500000000106413702133370022203 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_dynarray_bad.v:15:11: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits. : ... In instance t 15 | a = new [s]; | ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Internal Error: t/t_dynarray_bad.v:15:16: ../V3Number.cpp:#: Number operation called with non-logic (double or string) argument: '"str"" 15 | a = new [s]; | ^ verilator-4.038/test_regress/t/t_initial.v0000664000177100017500000000163513702133370020637 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; `include "t_initial_inc.vh" // surefire lint_off STMINI initial assign user_loaded_value = 1; initial _ranit = 0; always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; // Test $time // surefire lint_off CWECBB if ($time<20) $write("time<20\n"); // surefire lint_on CWECBB // Test $write $write ("[%0t] %m: User loaded ", $time); $display ("%b", user_loaded_value); if (user_loaded_value!=1) $stop; // Test $c `ifdef VERILATOR $c ("VL_PRINTF(\"Hi From C++\\n\");"); `endif user_loaded_value <= 2; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_genfor_hier.v0000664000177100017500000000117313702133370021472 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Demonstrate deferred linking across module // bondaries // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module m1(); logic v1; endmodule module t (/*AUTOARG*/); for (genvar the_genvar = 0; the_genvar < 4; the_genvar++) begin : m1_b m1 m1_inst(); end for (genvar the_other_genvar = 0; the_other_genvar < 4; the_other_genvar++) begin always_comb m1_b[the_other_genvar].m1_inst.v1 = 1'b0; end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_unopt_array_csplit.pl0000775000177100017500000000124113702133370023271 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_unopt_array.v"); compile( v_flags2 => ["--trace --output-split 1 --output-split-cfuncs 1 -Wno-UNOPTFLAT"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_const_overflow_bad.pl0000775000177100017500000000110113702133367023230 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_class1.v0000664000177100017500000000142213702133367020374 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Cls; int imembera; int imemberb; endclass : Cls module t (/*AUTOARG*/); initial begin Cls c; if (c != null) $stop; $display("Display: null = \"%p\"", c); // null c = new; $display("Display: newed = \"%p\"", c); // '{imembera:0, imemberb:0} c.imembera = 10; c.imemberb = 20; $display("Display: set = \"%p\"", c); // '{imembera:10, imemberb:20} if (c.imembera != 10) $stop; if (c.imemberb != 20) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_multitop_sig.pl0000775000177100017500000000174613702133370022101 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["-Wno-MULTITOP --exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); file_grep($Self->{run_log_filename}, qr!In 'a'!); file_grep($Self->{run_log_filename}, qr!In 'a.sub'!); file_grep($Self->{run_log_filename}, qr!In 'b'!); file_grep($Self->{run_log_filename}, qr!In 'b.sub'!); file_grep($Self->{run_log_filename}, qr!In 'c'!); file_grep($Self->{run_log_filename}, qr!In 'c.sub'!); ok(1); 1; verilator-4.038/test_regress/t/t_gate_tree.pl0000775000177100017500000001026613702133370021316 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; #use Data::Dumper; use strict; use vars qw($Self); scenarios(simulator => 1); my $width = 64*($ENV{VERILATOR_TEST_WIDTH}||4); my $vars = 64; $Self->{cycles} = ($Self->{benchmark} ? 1_000_000 : 100); $Self->{sim_time} = $Self->{cycles} * 10 + 1000; sub gen { my $filename = shift; my $fh = IO::File->new(">$filename"); $fh->print("// Generated by t_gate_tree.pl\n"); $fh->print("module t (clk);\n"); $fh->print(" input clk;\n"); $fh->print("\n"); $fh->print(" integer cyc=0;\n"); $fh->print(" reg reset;\n"); $fh->print("\n"); my %tree; my $fanin = 8; my $stages = int(log($vars)/log($fanin)+0.99999)+1; my $result = 0; for (my $n=0; $n<$vars; $n++) { $result += ($n||1); $tree{0}{$n}{$n} = 1; my $nl = $n; for (my $stage=1; $stage<$stages; $stage++) { my $lastn = $nl; $nl = int($nl/$fanin); $tree{$stage}{$nl}{$lastn} = 1; } } #print Dumper(\%tree); $fh->print("\n"); my $workingset = 0; foreach my $stage (sort {$a<=>$b} keys %tree) { foreach my $n (sort {$a<=>$b} keys %{$tree{$stage}}) { $fh->print( " reg [".($width-1).":0] v${stage}_${n};\n"); $workingset += int($width/8 + 7); } } $fh->print("\n"); $fh->print(" always @ (posedge clk) begin\n"); $fh->print(" cyc <= cyc + 1;\n"); $fh->print("`ifdef TEST_VERBOSE\n"); $fh->print(" \$write(\"[%0t] rst=%0x v0_0=%0x v1_0=%0x result=%0x\\n\"" .", \$time, reset, v0_0, v1_0, v".($stages-1)."_0);\n"); $fh->print("`endif\n"); $fh->print(" if (cyc==0) begin\n"); $fh->print(" reset <= 1;\n"); $fh->print(" end\n"); $fh->print(" else if (cyc==10) begin\n"); $fh->print(" reset <= 0;\n"); $fh->print(" end\n"); $fh->print("`ifndef SIM_CYCLES\n"); $fh->print(" `define SIM_CYCLES 99\n"); $fh->print("`endif\n"); $fh->print(" else if (cyc==`SIM_CYCLES) begin\n"); $fh->print(" if (v".($stages-1)."_0 != ${width}'d${result}) \$stop;\n"); $fh->print(" \$write(\"VARS=${vars} WIDTH=${width}" ." WORKINGSET=".(int($workingset/1024))."KB\\n\");\n"); $fh->print(' $write("*-* All Finished *-*\n");',"\n"); $fh->print(' $finish;',"\n"); $fh->print(" end\n"); $fh->print(" end\n"); $fh->print("\n"); for (my $n=0; $n<$vars; $n++) { $fh->print(" always @ (posedge clk)" ." v0_${n} <= reset ? ${width}'d".(${n}||1)." : v0_" .((int($n/$fanin)*$fanin) + (($n+1) % $fanin)).";\n"); } foreach my $stage (sort {$a<=>$b} keys %tree) { next if $stage == 0; $fh->print("\n"); foreach my $n (sort {$a<=>$b} keys %{$tree{$stage}}) { $fh->print(" always @ (posedge clk)" ." v${stage}_${n} <="); my $op = ""; foreach my $ni (sort {$a<=>$b} keys %{$tree{$stage}{$n}}) { $fh->print($op." v".(${stage}-1)."_${ni}"); $op = " +"; } $fh->print(";\n"); } } $fh->print("endmodule\n"); } top_filename("$Self->{obj_dir}/t_gate_tree.v"); gen($Self->{top_filename}); compile( v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",], verilator_flags2=>["--stats --x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS"], ); execute( all_run_flags => ["+verilator+prof+threads+start+100", " +verilator+prof+threads+window+2", " +verilator+prof+threads+file+$Self->{obj_dir}/profile_threads.dat", ], check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_select.v0000664000177100017500000000214613702133370021341 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 `define WIDTH 2 module top ( input OE1, input OE2, input [`WIDTH-1:0] A1, input [`WIDTH-1:0] A2, output [`WIDTH-1:0] Y1, output [`WIDTH-1:0] Y2, output [`WIDTH-1:0] Y3, output [`WIDTH**2-1:0] W); assign W[A1] = (OE2) ? A2[0] : 1'bz; assign W[A2] = (OE1) ? A2[1] : 1'bz; // have 2 different 'chips' drive the PAD to act like a bi-directional bus wire [`WIDTH-1:0] PAD; io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD)); io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD)); assign Y3 = PAD; pullup p1(PAD); // pulldown p1(PAD); wire [5:0] fill = { 4'b0, A1 }; endmodule module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD); io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD)); endmodule module io (input OE, input I, output O, inout PAD); assign O = PAD; assign PAD = OE ? I : 1'bz; endmodule verilator-4.038/test_regress/t/t_tri_pullup.cpp0000664000177100017500000000267413702133370021726 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_pullup.h" Vt_tri_pullup* tb = NULL; double sc_time_stamp() { return 0; } bool check() { bool pass; int Z, Y, X; if (tb->OE) { Z = tb->A; Y = tb->A; X = tb->A; } else { Z = 1; Y = 0; X = 1; } #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif if (tb->Z == Z && tb->Y == Y && tb->X == X) { if (verbose) printf("PASS: "); pass = true; } else { printf("%%E-FAIL: "); verbose = true; pass = false; } if (verbose) printf("OE=%d A=%d X=%d xexp=%d Y=%d yexp=%d Z=%d zexp=%d\n", tb->OE, tb->A, tb->X, X, tb->Y, Y, tb->Z, Z); return pass; } int main() { bool pass = true; Verilated::debug(0); tb = new Vt_tri_pullup("tb"); // loop through every possibility and check the result for (tb->OE = 0; tb->OE < 2; tb->OE++) { for (tb->A = 0; tb->A < 2; tb->A++) { tb->eval(); if (!check()) { pass = false; } } } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from pullup test\n"); } return 0; } verilator-4.038/test_regress/t/t_event_control_unsup.v0000664000177100017500000000072313702133370023316 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; initial begin; @(clk); $write("[%0t] Got\n", $time); @(clk); $write("[%0t] Got\n", $time); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_string_type_methods_bad.out0000664000177100017500000000133713702133370024447 0ustar wsnyderwsnyder%Error: t/t_string_type_methods_bad.v:15:13: The 1 arguments passed to .len method does not match its requiring 0 arguments : ... In instance t 15 | i = s.len(0); | ^~~ %Error: t/t_string_type_methods_bad.v:16:9: The 0 arguments passed to .itoa method does not match its requiring 1 arguments : ... In instance t 16 | s.itoa; | ^~~~ %Error: t/t_string_type_methods_bad.v:17:9: The 3 arguments passed to .itoa method does not match its requiring 1 arguments : ... In instance t 17 | s.itoa(1,2,3); | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_order_loop_bad.pl0000775000177100017500000000144713702133370022332 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, # Can't use expect_filename here as unstable output expect => '%Error: Circular logic when ordering code .* *t/t_order_loop_bad.v:\d+:\d+: + Example path: ALWAYS *t/t_order_loop_bad.v:\d+:\d+: + Example path: t.ready *t/t_order_loop_bad.v:\d+:\d+: + Example path: ACTIVE .*', ); ok(1); 1; verilator-4.038/test_regress/t/t_param_long.pl0000775000177100017500000000105313702133370021470 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_dup2_bad.out0000664000177100017500000000117713702133370022101 0ustar wsnyderwsnyder%Error: t/t_var_dup2_bad.v:13:9: Duplicate declaration of signal: 'bad_o_w' : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2) 13 | wire bad_o_w; | ^~~~~~~ t/t_var_dup2_bad.v:10:11: ... Location of original declaration 10 | output bad_o_w, | ^~~~~~~ %Error: t/t_var_dup2_bad.v:14:9: Duplicate declaration of signal: 'bad_o_r' 14 | reg bad_o_r; | ^~~~~~~ t/t_var_dup2_bad.v:11:11: ... Location of original declaration 11 | output bad_o_r); | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_c_api.cpp0000664000177100017500000000116413702133370021751 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include VM_PREFIX_INCLUDE extern void vcdTestMain(const char* filenamep); int main(int argc, char** argv, char** env) { const char* filenamep = VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"; printf("Writing %s\n", filenamep); vcdTestMain(filenamep); printf("*-* All Finished *-*\n"); return 0; } verilator-4.038/test_regress/t/t_vlt_warn_bad.out0000664000177100017500000000117013702133370022204 0ustar wsnyderwsnyder%Warning-DEPRECATED: t/t_vlt_warn_bad.vlt:12:10: Deprecated -msg in configuration files, use -rule instead. 12 | lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 19-19 | ^~~~ ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_vlt_warn.v:21:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits. : ... In instance t 21 | reg width_warn3_var_line20 = 2'b11; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_package_abs.pl0000775000177100017500000000105313702133370021571 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_bad_sameas.v0000664000177100017500000000121213702133370022124 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer varfirst; sub varfirst (); // Error: Cell hits var task varfirst; begin end endtask // Error: Task hits var sub cellfirst (); integer cellfirst; // Error: Var hits cell task cellfirst; begin end endtask // Error: Task hits cell task taskfirst; begin end endtask integer taskfirst; // Error: Var hits task sub taskfirst (); // Error: Cell hits task endmodule module sub; endmodule verilator-4.038/test_regress/t/t_interface_gen7.v0000664000177100017500000000302013702133370022054 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); logic val; function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t(); intf #(.PARAM(1)) my_intf [1:0] (); generate genvar the_genvar; begin : ia for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf begin assign my_intf[the_genvar].val = '1; t1 t (.mod_intf(my_intf[the_genvar])); end end end endgenerate generate genvar the_second_genvar; begin : ib intf #(.PARAM(1)) my_intf [1:0] (); for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf begin assign my_intf[the_second_genvar].val = '1; t1 t (.mod_intf(my_intf[the_second_genvar])); end end end endgenerate generate genvar the_third_genvar; begin : ic for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf begin intf #(.PARAM(1)) my_intf [1:0] (); assign my_intf[the_third_genvar].val = '1; t1 t (.mod_intf(my_intf[the_third_genvar])); end end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_modport_dir_bad.out0000664000177100017500000000064613702133370024721 0ustar wsnyderwsnyderExpecting something along the line of: %Error: t/t_interface_modport_dir_bad.v:36: Attempt to drive input-only modport: 'data' : ... In instance t.source_i.source_i ctrl.data <= ~ctrl.data; ^~~~ %Error: Exiting due to 1 error(s) %Error: t/t_interface_modport_dir_bad.v:37: Attempt to drive input-only modport: 'valid' : ... In instance t.source_i.source_i ctrl.valid<= ~ctrl.valid; ^~~~ %Error: Exiting due to 1 error(s) verilator-4.038/test_regress/t/t_flag_getenv.v0000664000177100017500000000034613702133370021465 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define EMPTY 1 verilator-4.038/test_regress/t/t_mem_multidim.pl0000775000177100017500000000105313702133370022033 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_mda.v0000664000177100017500000000350313702133367021147 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // msg2946 int A [7][1], B [8][1]; int a [1], b [1]; always_ff @(posedge clk) begin a <= A[crc[2:0]]; b <= B[crc[2:0]]; end wire [63:0] result = {a[0], b[0]}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; A[0][0] <= 32'h1_0; A[1][0] <= 32'h1_1; A[2][0] <= 32'h1_2; A[3][0] <= 32'h1_3; A[4][0] <= 32'h1_4; A[5][0] <= 32'h1_5; A[6][0] <= 32'h1_6; B[0][0] <= 32'h2_0; B[1][0] <= 32'h2_1; B[2][0] <= 32'h2_2; B[3][0] <= 32'h2_3; B[4][0] <= 32'h2_4; B[5][0] <= 32'h2_5; B[6][0] <= 32'h2_6; B[7][0] <= 32'h2_7; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h619f75c3a6d948bd if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_lint_unused.pl0000775000177100017500000000112113702133370021676 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME"], ); ok(1); 1; verilator-4.038/test_regress/t/t_class_local.pl0000775000177100017500000000105313702133367021636 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_const_part.pl0000775000177100017500000000105313702133370022705 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_blocking.pl0000775000177100017500000000105313702133367021147 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_vpi_1ns1ns.pl0000775000177100017500000000161413702133370022373 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator_st => 1); top_filename("t/t_time_vpi.v"); $Self->{main_time_multiplier} = 1e-9 / 1e-9; compile( v_flags2 => ['+define+time_scale_units=1ns +define+time_scale_prec=1ns', 't/t_time_vpi_c.cpp'], verilator_flags2 => ['--vpi --trace'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); file_grep("$Self->{obj_dir}/simx.vcd", qr!timescale +1ns!); ok(1); 1; verilator-4.038/test_regress/t/t_order_multidriven.v0000664000177100017500000001106013702133370022734 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Ted Campbell. // SPDX-License-Identifier: CC0-1.0 //With MULTI_CLK defined shows bug, without it is hidden `define MULTI_CLK //bug634 module t ( input i_clk_wr, input i_clk_rd ); wire wr$wen; wire [7:0] wr$addr; wire [7:0] wr$wdata; wire [7:0] wr$rdata; wire rd$wen; wire [7:0] rd$addr; wire [7:0] rd$wdata; wire [7:0] rd$rdata; wire clk_wr; wire clk_rd; `ifdef MULTI_CLK assign clk_wr = i_clk_wr; assign clk_rd = i_clk_rd; `else assign clk_wr = i_clk_wr; assign clk_rd = i_clk_wr; `endif FooWr u_wr ( .i_clk ( clk_wr ), .o_wen ( wr$wen ), .o_addr ( wr$addr ), .o_wdata ( wr$wdata ), .i_rdata ( wr$rdata ) ); FooRd u_rd ( .i_clk ( clk_rd ), .o_wen ( rd$wen ), .o_addr ( rd$addr ), .o_wdata ( rd$wdata ), .i_rdata ( rd$rdata ) ); FooMem u_mem ( .iv_clk ( {clk_wr, clk_rd } ), .iv_wen ( {wr$wen, rd$wen } ), .iv_addr ( {wr$addr, rd$addr } ), .iv_wdata ( {wr$wdata,rd$wdata} ), .ov_rdata ( {wr$rdata,rd$rdata} ) ); endmodule // Memory Writer module FooWr( input i_clk, output o_wen, output [7:0] o_addr, output [7:0] o_wdata, input [7:0] i_rdata ); reg [7:0] cnt = 0; // Count [0,200] always @( posedge i_clk ) if ( cnt < 8'd50 ) cnt <= cnt + 8'd1; // Write addr in (10,30) if even assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 ); assign o_addr = cnt; assign o_wdata = cnt; endmodule // Memory Reader module FooRd( input i_clk, output o_wen, output [7:0] o_addr, output [7:0] o_wdata, input [7:0] i_rdata ); reg [7:0] cnt = 0; reg [7:0] addr_r; reg en_r; // Count [0,200] always @( posedge i_clk ) if ( cnt < 8'd200 ) cnt <= cnt + 8'd1; // Read data assign o_wen = 0; assign o_addr = cnt - 8'd100; // Track issued read always @( posedge i_clk ) begin addr_r <= o_addr; en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 ); end // Display to console 100 cycles after writer always @( negedge i_clk ) if ( en_r ) begin `ifdef TEST_VERBOSE $display( "MEM[%x] == %x", addr_r, i_rdata ); `endif if (addr_r != i_rdata) $stop; end endmodule // Multi-port memory abstraction module FooMem( input [2 -1:0] iv_clk, input [2 -1:0] iv_wen, input [2*8-1:0] iv_addr, input [2*8-1:0] iv_wdata, output [2*8-1:0] ov_rdata ); FooMemImpl u_impl ( .a_clk ( iv_clk [0*1+:1] ), .a_wen ( iv_wen [0*1+:1] ), .a_addr ( iv_addr [0*8+:8] ), .a_wdata ( iv_wdata[0*8+:8] ), .a_rdata ( ov_rdata[0*8+:8] ), .b_clk ( iv_clk [1*1+:1] ), .b_wen ( iv_wen [1*1+:1] ), .b_addr ( iv_addr [1*8+:8] ), .b_wdata ( iv_wdata[1*8+:8] ), .b_rdata ( ov_rdata[1*8+:8] ) ); endmodule // Dual-Port L1 Memory Implementation module FooMemImpl( input a_clk, input a_wen, input [7:0] a_addr, input [7:0] a_wdata, output reg [7:0] a_rdata, input b_clk, input b_wen, input [7:0] b_addr, input [7:0] b_wdata, output reg [7:0] b_rdata ); /* verilator lint_off MULTIDRIVEN */ reg [7:0] mem[0:255]; /* verilator lint_on MULTIDRIVEN */ always @( posedge a_clk ) if ( a_wen ) mem[a_addr] <= a_wdata; always @( posedge b_clk ) if ( b_wen ) mem[b_addr] <= b_wdata; always @( posedge a_clk ) a_rdata <= mem[a_addr]; always @( posedge b_clk ) b_rdata <= mem[b_addr]; endmodule verilator-4.038/test_regress/t/t_waiveroutput_allgood.out0000664000177100017500000000054313702133370024024 0ustar wsnyderwsnyder// DESCRIPTION: Verilator output: Waivers generated with --waiver-output `verilator_config // Below you find suggested waivers. You have three options: // 1. Fix the reason for the linter warning // 2. Keep the waiver permanently if you are sure this is okay // 3. Keep the waiver temporarily to suppress the output // No waivers needed - great! verilator-4.038/test_regress/t/t_packed_concat_bad.out0000664000177100017500000000213513702133370023130 0ustar wsnyderwsnyder%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:17:47: Unsized numbers/parameters not allowed in replications. : ... In instance t 17 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; | ^~~~~ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:46: Unsized numbers/parameters not allowed in concatenations. : ... In instance t 18 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; | ^~~~~ %Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:60: Unsized numbers/parameters not allowed in replications. : ... In instance t 18 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_reloop_cam.v0000664000177100017500000001225713702133370021330 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; reg rst; // Two phases, random so nothing optimizes away, and focused so get hits logic inval; wire [30:0] wdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); wire [30:0] cdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); wire wdat_val = 1'b1; wire camen = crc[32]; wire ren = crc[33]; wire wen = crc[34]; wire [7:0] rwidx = (cyc < 50 ? crc[63:56] : {6'h0, crc[57:56]}); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic hit_d2r; // From cam of cam.v logic [7:0] hitidx_d1r; // From cam of cam.v logic [255:0] hitvec_d1r; // From cam of cam.v logic [30:0] rdat_d2r; // From cam of cam.v logic rdat_val_d2r; // From cam of cam.v // End of automatics cam cam (/*AUTOINST*/ // Outputs .hitvec_d1r (hitvec_d1r[255:0]), .hitidx_d1r (hitidx_d1r[7:0]), .hit_d2r (hit_d2r), .rdat_d2r (rdat_d2r[30:0]), .rdat_val_d2r (rdat_val_d2r), // Inputs .clk (clk), .rst (rst), .camen (camen), .inval (inval), .cdat (cdat[30:0]), .ren (ren), .wen (wen), .wdat (wdat[30:0]), .wdat_val (wdat_val), .rwidx (rwidx[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {hitvec_d1r[15:0], 15'h0, hit_d2r, rdat_val_d2r, rdat_d2r}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; rst <= 1'b1; end else if (cyc<10) begin sum <= '0; rst <= 1'b0; end else if (cyc==70) begin inval <= 1'b1; end else if (cyc==71) begin inval <= 1'b0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h5182640870b07199 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module cam ( input clk, input rst, input camen, input inval, input [30:0] cdat, output logic [255:0] hitvec_d1r, output logic [7:0] hitidx_d1r, output logic hit_d2r, input ren, input wen, input [30:0] wdat, input wdat_val, input [7:0] rwidx, output logic [30:0] rdat_d2r, output logic rdat_val_d2r ); logic camen_d1r; logic inval_d1r; logic ren_d1r; logic wen_d1r; logic [7:0] rwidx_d1r; logic [30:0] cdat_d1r; logic [30:0] wdat_d1r; logic wdat_val_d1r; always_ff @(posedge clk) begin camen_d1r <= camen; inval_d1r <= inval; ren_d1r <= ren; wen_d1r <= wen; cdat_d1r <= cdat; rwidx_d1r <= rwidx; wdat_d1r <= wdat; wdat_val_d1r <= wdat_val; end typedef struct packed { logic [30:0] data; logic valid; } entry_t; entry_t [255:0] entries; always_ff @(posedge clk) begin if (camen_d1r) begin for (int i = 0; i < 256; i = i + 1) begin hitvec_d1r[i] <= entries[i].valid & (entries[i].data == cdat_d1r); end end end always_ff @(posedge clk) begin hit_d2r <= | hitvec_d1r; end always_ff @(posedge clk) begin if (rst) begin for (int i = 0; i < 256; i = i + 1) begin entries[i] <= '0; end end else if (wen_d1r) begin entries[rwidx_d1r] <= '{valid:wdat_val_d1r, data:wdat_d1r}; end else if (inval_d1r) begin for (int i = 0; i < 256; i = i + 1) begin entries[i] <= '{valid:'0, data:entries[i].data}; end end end always_ff @(posedge clk) begin if (ren_d1r) begin rdat_d2r <= entries[rwidx_d1r].data; rdat_val_d2r <= entries[rwidx_d1r].valid; end end endmodule verilator-4.038/test_regress/t/t_display_merge.pl0000775000177100017500000000137413702133370022203 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2=>["--stats"], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}__stats.txt", qr/Node count, DISPLAY \s+ 32 \s+ 25 \s+ 25 \s+ 25/); ok(1); 1; verilator-4.038/test_regress/t/t_flag_nofile_bad.out0000664000177100017500000000015613702133370022620 0ustar wsnyderwsnyder%Error: verilator: No Input Verilog file specified on command line, see verilator --help for more information verilator-4.038/test_regress/t/t_var_dotted_dup_bad.pl0000775000177100017500000000107113702133370023162 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2005 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_order_clkinst.pl0000775000177100017500000000152213702133370022214 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # On Verilator, we expect this to pass. # # TBD: Will event-based simulators match Verilator's behavior # closely enough to pass the same test? # If not -- probably we should switch this to be vlt-only. compile(verilator_flags2 => ["--trace"]); execute(check_finished => 1); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_assert_synth.pl0000775000177100017500000000116413702133367022110 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_name.v0000664000177100017500000000147013702133367021316 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 task unit_name; $write("unit_name = '%m'\n"); endtask class Cls; static task static_name; $write("static_name = '%m'\n"); endtask task nonstatic_name; $write("nonstatic_name = '%m'\n"); endtask endclass : Cls module t (/*AUTOARG*/); initial begin Cls c; c = new; $write("t = '%m'\n"); unit_name(); $write("Below results vary with simulator.\n"); // E.g. '$unit.\Cls::static_name ' // E.g. '$unit_x.Cls.static_name' c.static_name(); c.nonstatic_name(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_shiftrs.v0000664000177100017500000000235213702133370021676 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg signed [64+15:0] data; integer i; integer b; reg signed [64+15:0] srs; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==2) begin data <= 80'h0; data[75] <= 1'b1; data[10] <= 1'b1; end if (cyc==3) begin for (i=0; i<85; i=i+1) begin srs = data>>>i; //$write (" %x >>> %d == %x\n",data,i,srs); for (b=0; b<80; b=b+1) begin if (srs[b] != (b==(75-i) || b==(10-i))) $stop; end end end if (cyc==10) begin data <= 80'h0; data[79] <= 1'b1; data[10] <= 1'b1; end if (cyc==12) begin for (i=0; i<85; i=i+1) begin srs = data>>>i; //$write (" %x >>> %d == %x\n",data,i,srs); for (b=0; b<80; b=b+1) begin if (srs[b] != (b>=(79-i) || b==(10-i))) $stop; end end end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_assert_inside_cond.pl0000775000177100017500000000114113702133367023214 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"], ); execute( ); ok(1); 1; verilator-4.038/test_regress/t/t_xml_first.pl0000775000177100017500000000134713702133370021366 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2012 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( verilator_flags2 => ['--xml-only'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); files_identical("$out_filename", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_wire_types.v0000664000177100017500000000321713702133370021376 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%g exp=%g\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); // IEEE: integer_atom_type wire byte w_byte; wire shortint w_shortint; wire int w_int; wire longint w_longint; wire integer w_integer; // IEEE: integer_atom_type wire bit w_bit; wire logic w_logic; wire bit [1:0] w_bit2; wire logic [1:0] w_logic2; // IEEE: non_integer_type //UNSUP shortreal w_shortreal; wire real w_real; assign w_byte = 8'h12; assign w_shortint = 16'h1234; assign w_int = -123456; assign w_longint = -1234567; assign w_integer = -123456; assign w_bit = 1'b1; assign w_logic = 1'b1; assign w_bit2 = 2'b10; assign w_logic2 = 2'b10; assign w_real = 3.14; always @ (posedge clk) begin `checkh(w_byte, 8'h12); `checkh(w_shortint, 16'h1234); `checkh(w_int, -123456); `checkh(w_longint, -1234567); `checkh(w_integer, -123456); `checkh(w_bit, 1'b1); `checkh(w_logic, 1'b1); `checkh(w_bit2, 2'b10); `checkh(w_logic2, 2'b10); `checkr(w_real, 3.14); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_select_bad_range.out0000664000177100017500000000110013702133370022774 0ustar wsnyderwsnyder%Warning-SELRANGE: t/t_select_bad_range.v:16:15: Selection index out of range: 44:44 outside 43:0 : ... In instance t 16 | sel = mi[44]; | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range.v:17:16: Selection index out of range: 44:41 outside 43:0 : ... In instance t 17 | sel2 = mi[44:41]; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_notfound_bad.pl0000775000177100017500000000107413702133370022666 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_multi_io.pl0000775000177100017500000000125013702133370022027 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( # Disable inlining, this test is trivial without it verilator_flags2 => ["-Oi --trace"], verilator_flags3 => [], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_array_bad.out0000664000177100017500000000074613702133370023516 0ustar wsnyderwsnyder%Error: t/t_interface_array_bad.v:23:16: Expecting expression to be constant, but variable isn't const: 'bar' : ... In instance t 23 | assign foos[bar].a = 1'b1; | ^~~ %Error: t/t_interface_array_bad.v:23:15: Could not expand constant selection inside dotted reference: 'bar' : ... In instance t 23 | assign foos[bar].a = 1'b1; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_case_nest.v0000664000177100017500000000722113702133367021155 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; reg [63:0] sum; reg out1; sub sub (.in(crc[23:0]), .out1(out1)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1}; if (cyc==1) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==90) begin if (sum !== 64'h2e5cb972eb02b8a0) $stop; end else if (cyc==91) begin end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, // Inputs in ); input [23:0] in; output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101; always @* begin casez (in[17:16]) 2'b00: casez (in[2:0]) 3'h0: out1[0] = in[0]^RANDOM[0]; 3'h1: out1[0] = in[0]^RANDOM[1]; 3'h2: out1[0] = in[0]^RANDOM[2]; 3'h3: out1[0] = in[0]^RANDOM[3]; 3'h4: out1[0] = in[0]^RANDOM[4]; 3'h5: out1[0] = in[0]^RANDOM[5]; 3'h6: out1[0] = in[0]^RANDOM[6]; 3'h7: out1[0] = in[0]^RANDOM[7]; endcase 2'b01: casez (in[2:0]) 3'h0: out1[0] = RANDOM[10]; 3'h1: out1[0] = RANDOM[11]; 3'h2: out1[0] = RANDOM[12]; 3'h3: out1[0] = RANDOM[13]; 3'h4: out1[0] = RANDOM[14]; 3'h5: out1[0] = RANDOM[15]; 3'h6: out1[0] = RANDOM[16]; 3'h7: out1[0] = RANDOM[17]; endcase 2'b1?: casez (in[4]) 1'b1: casez (in[2:0]) 3'h0: out1[0] = RANDOM[20]; 3'h1: out1[0] = RANDOM[21]; 3'h2: out1[0] = RANDOM[22]; 3'h3: out1[0] = RANDOM[23]; 3'h4: out1[0] = RANDOM[24]; 3'h5: out1[0] = RANDOM[25]; 3'h6: out1[0] = RANDOM[26]; 3'h7: out1[0] = RANDOM[27]; endcase 1'b0: casez (in[2:0]) 3'h0: out1[0] = RANDOM[30]; 3'h1: out1[0] = RANDOM[31]; 3'h2: out1[0] = RANDOM[32]; 3'h3: out1[0] = RANDOM[33]; 3'h4: out1[0] = RANDOM[34]; 3'h5: out1[0] = RANDOM[35]; 3'h6: out1[0] = RANDOM[36]; 3'h7: out1[0] = RANDOM[37]; endcase endcase endcase end endmodule verilator-4.038/test_regress/t/t_select_param.pl0000775000177100017500000000105313702133370022010 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_const_packed_struct_bad2.v0000664000177100017500000000225313702133370025147 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { logic [ 31 : 0 ] b; logic [ 7 : 0 ] bar; } sub_params_t; typedef struct packed { logic [ 31 : 0 ] a; logic [ 5 : 0 ] foo; sub_params_t sub_params; } params_t; localparam P24 = f_add2(7, 8, 9); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end function integer f_add(input params_t [ 1 : 0 ] params); f_add = params[0].a+params[1].sub_params.b; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); params_t [ 1 : 0 ] params; sub_params_t sp0; sub_params_t sp1; sp0 = '{b:55, bar:111}; params[0] = '{a:a, foo:11, sub_params:sp0}; sp1 = '{b:b, bar:112}; params[1] = '{a:12345, foo:12, sub_params:sp1}; f_add2 = f_add(params)+c; endfunction endmodule verilator-4.038/test_regress/t/t_sys_file_basic.v0000664000177100017500000002102213702133370022154 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "verilated.v" `define STRINGIFY(x) `"x`" `define ratio_error(a,b) (((a)>(b) ? ((a)-(b)) : ((b)-(a))) /(a)) `define checkr(gotv,expv) do if (`ratio_error((gotv),(expv))>0.0001) begin $write("%%Error: %s:%0d: got=%g exp=%g\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t; integer file; integer chars; reg [1*8:1] letterl; reg [8*8:1] letterq; reg [16*8:1] letterw; reg [16*8:1] letterz; real r; string s; integer i; reg [7:0] v_a,v_b,v_c,v_d; reg [31:0] v_worda; reg [31:0] v_wordb; integer v_length, v_off; `ifdef TEST_VERBOSE `define verbose 1'b1 `else `define verbose 1'b0 `endif initial begin // Display formatting `ifdef verilator if (file != 0) $stop; $fwrite(file, "Never printed, file closed\n"); if (!$feof(file)) $stop; `endif `ifdef AUTOFLUSH // The "w" is required so we get a FD not a MFD file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_autoflush.log"},"w"); `else // The "w" is required so we get a FD not a MFD file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_basic_test.log"},"w"); `endif if ($feof(file)) $stop; $fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667); $fwrite(file, "[%0t] %s\n", $time, "Hello2"); i = 12; $fwrite(file, "d: "); $fwrite(file, i); $fwrite(file, " "); $fdisplay(file, i); $fwriteh(file, "h: "); $fwriteh(file, i); $fwriteh(file, " "); $fdisplayh(file, i); $fwriteo(file, "o: "); $fwriteo(file, i); $fwriteo(file, " "); $fdisplayo(file, i); $fwriteb(file, "b: "); $fwriteb(file, i); $fwriteb(file, " "); $fdisplayb(file, i); $fflush(file); $fflush(); $fflush; $fclose(file); `ifdef verilator if (file != 0) $stop(1); // Also test arguments to stop $fwrite(file, "Never printed, file closed\n"); `endif begin // Check for opening errors // The "r" is required so we get a FD not a MFD file = $fopen("DOES_NOT_EXIST","r"); if (|file) $stop; // Should not exist, IE must return 0 // Check error function s = ""; i = $ferror(file, s); `checkh(i, 2); `checks(s, "No such file or directory"); end begin // Check quadword access; a little strange, but it's legal to open "." file = $fopen(".","r"); $fclose(file); end begin // Check read functions w/string s = "t/t_sys_file_basic_input.dat"; file = $fopen(s,"r"); if ($feof(file)) $stop; $fclose(file); end begin // Check read functions file = $fopen("t/t_sys_file_basic_input.dat","r"); if ($feof(file)) $stop; // $fgetc if ($fgetc(file) != "h") $stop; if ($fgetc(file) != "i") $stop; if ($fgetc(file) != "\n") $stop; // $ungetc if ($ungetc("x", file) != 0) $stop; if ($fgetc(file) != "x") $stop; // $fgets chars = $fgets(letterl, file); if (`verbose) $write("c=%0d l=%s\n", chars, letterl); if (chars != 1) $stop; if (letterl != "l") $stop; chars = $fgets(letterq, file); if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline if (chars != 5) $stop; if (letterq != "\0\0\0quad\n") $stop; letterw = "5432109876543210"; chars = $fgets(letterw, file); if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline if (chars != 10) $stop; if (letterw != "\0\0\0\0\0\0widestuff\n") $stop; // $sscanf if ($sscanf("x","")!=0) $stop; if ($sscanf("z","z")!=0) $stop; chars = $sscanf("blabcdefghijklmnop", "%s", letterq); if (`verbose) $write("c=%0d sa=%s\n", chars, letterq); if (chars != 1) $stop; if (letterq != "ijklmnop") $stop; chars = $sscanf("xa=1f ign=22 xb=12898971238912389712783490823_abcdef689_02348923", "xa=%x ign=%*d xb=%x", letterq, letterw); if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw); if (chars != 2) $stop; if (letterq != 64'h1f) $stop; if (letterw != 128'h389712783490823_abcdef689_02348923) $stop; chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ", "ba=%b bb=%b%s", letterq, letterw, letterz); if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz); if (chars != 3) $stop; if (letterq != 64'h2) $stop; if (letterw != 128'hd2a55) $stop; if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop; chars = $sscanf("oa=23 oi=11 ob=125634123615234123681236", "oa=%o oi=%*o ob=%o", letterq, letterw); if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw); if (chars != 2) $stop; if (letterq != 64'h13) $stop; if (letterw != 128'h55ce14f1a9c29e) $stop; chars = $sscanf("r=0.1 d=-236123", "r=%g d=%d", r, letterq); if (`verbose) $write("c=%0d d=%d\n", chars, letterq); if (chars != 2) $stop; `checkr(r, 0.1); if (letterq != 64'hfffffffffffc65a5) $stop; // Cover quad and %e/%f chars = $sscanf("r=0.2", "r=%e", r); if (`verbose) $write("c=%0d r=%e\n", chars, r); `checkr(r, 0.2); chars = $sscanf("r=0.3", "r=%f", r); if (`verbose) $write("c=%0d r=%f\n", chars, r); `checkr(r, 0.3); s = "r=0.2 d=-236124"; chars = $sscanf(s, "r=%g d=%d", r, letterq); if (`verbose) $write("c=%0d d=%d\n", chars, letterq); if (chars != 2) $stop; `checkr(r, 0.2); if (letterq != 64'hfffffffffffc65a4) $stop; // $fscanf if ($fscanf(file,"")!=0) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw); if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw); if (chars != 2) $stop; if (letterq != 64'h1f) $stop; if (letterw != 128'h23790468902348923) $stop; if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz); if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz); if (chars != 3) $stop; if (letterq != 64'h2) $stop; if (letterw != 128'hd2a55) $stop; if (letterz != "\0\0\0\0note_the_two") $stop; if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw); if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw); if (chars != 2) $stop; if (letterq != 64'h13) $stop; if (letterw != 128'h1573) $stop; if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "d=%d", letterq); if (`verbose) $write("c=%0d d=%0x\n", chars, letterq); if (chars != 1) $stop; if (letterq != 64'hfffffffffffc65a5) $stop; if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "%c%s", letterl, letterw); if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw); if (chars != 2) $stop; if (letterl != "f") $stop; if (letterw != "\0\0\0\0\0redfishblah") $stop; chars = $fscanf(file, "%c", letterl); if (`verbose) $write("c=%0d l=%x\n", chars, letterl); if (chars != 1) $stop; if (letterl != "\n") $stop; // msg1229 v_a = $fgetc(file); v_b = $fgetc(file); v_c = $fgetc(file); v_d = $fgetc(file); v_worda = { v_d, v_c, v_b, v_a }; if (v_worda != "4321") $stop; v_wordb[7:0] = $fgetc(file); v_wordb[15:8] = $fgetc(file); v_wordb[23:16] = $fgetc(file); v_wordb[31:24] = $fgetc(file); if (v_wordb != "9876") $stop; if ($fgetc(file) != "\n") $stop; v_length = $ftell(file); $frewind(file); v_off = $ftell(file); if (v_off != 0) $stop; $fseek(file, 10, 0); v_off = $ftell(file); if (v_off != 10) $stop; $fseek(file, 1, 1); v_off = $ftell(file); if (v_off != 11) $stop; $fseek(file, -1, 1); v_off = $ftell(file); if (v_off != 10) $stop; $fseek(file, v_length, 0); v_off = $ftell(file); if (v_off != v_length) $stop; if ($fseek(file, 0, 2) != 0) $stop; v_off = $ftell(file); if (v_off < v_length) $stop; if ($rewind(file) != 0) $stop; v_off = $ftell(file); if (v_off != 0) $stop; $fclose(file); end $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end function sync; input [7:0] cexp; reg [7:0] cgot; begin cgot = $fgetc(file); if (`verbose) $write("sync=%x='%c'\n", cgot,cgot); sync = (cgot == cexp); end endfunction endmodule verilator-4.038/test_regress/t/t_randomize.pl0000775000177100017500000000107113702133370021341 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_outoforder.v0000664000177100017500000000246113702133370022244 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [125:0] a; wire q; sub sub ( .q (q), .a (a), .clk (clk)); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 126'b1000; end if (cyc==2) begin a <= 126'h1001; end if (cyc==3) begin a <= 126'h1010; end if (cyc==4) begin a <= 126'h1111; if (q !== 1'b0) $stop; end if (cyc==5) begin if (q !== 1'b1) $stop; end if (cyc==6) begin if (q !== 1'b0) $stop; end if (cyc==7) begin if (q !== 1'b0) $stop; end if (cyc==8) begin if (q !== 1'b0) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module sub ( input clk, input [125:0] a, output reg q ); // verilator public_module reg [125:0] g_r; wire [127:0] g_extend = { g_r, 1'b1, 1'b0 }; reg [6:0] sel; wire g_sel = g_extend[sel]; always @ (posedge clk) begin g_r <= a; sel <= a[6:0]; q <= g_sel; end endmodule verilator-4.038/test_regress/t/t_queue_unsup_bad.pl0000775000177100017500000000107413702133370022540 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_always_comb_bad.pl0000775000177100017500000000107413702133370023510 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_topmodule_bad2.pl0000775000177100017500000000130113702133370023236 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_topmodule.v"); lint( fails => 1, v_flags2 => ["--top-module notfound"], nc => 0, # Need to get it not to give the prompt expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_intdot.v0000664000177100017500000000423713702133370021341 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; wire out; reg in; Genit g (.clk(clk), .value(in), .result(out)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out); cyc <= cyc + 1; if (cyc==0) begin // Setup in <= 1'b1; end else if (cyc==1) begin in <= 1'b0; end else if (cyc==2) begin if (out != 1'b1) $stop; end else if (cyc==3) begin if (out != 1'b0) $stop; end else if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end //`define WAVES `ifdef WAVES initial begin $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"}); $dumpvars(12, t); end `endif endmodule module Generate (clk, value, result); input clk; input value; output result; reg Internal; assign result = Internal ^ clk; always @(posedge clk) Internal <= #1 value; endmodule module Checker (clk, value); input clk, value; always @(posedge clk) begin $write ("[%0t] value=%h\n", $time, value); end endmodule module Test (clk, value, result); input clk; input value; output result; Generate gen (clk, value, result); Checker chk (clk, gen.Internal); endmodule module Genit (clk, value, result); input clk; input value; output result; `ifndef ATSIM // else unsupported `ifndef NC // else unsupported `define WITH_FOR_GENVAR `endif `endif `define WITH_GENERATE `ifdef WITH_GENERATE `ifndef WITH_FOR_GENVAR genvar i; `endif generate for ( `ifdef WITH_FOR_GENVAR genvar `endif i = 0; i < 1; i = i + 1) begin : foo Test tt (clk, value, result); end endgenerate `else Test tt (clk, value, result); `endif wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change! always @ (posedge clk) begin $write("[%0t] Result2 = %x\n", $time, Result2); end endmodule verilator-4.038/test_regress/t/t_interface2_noinl.pl0000775000177100017500000000120313702133370022567 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface2.v"); compile( verilator_flags2 => ["--top-module t -Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_inl.pl0000775000177100017500000000127313702133370022157 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface.v"); compile( # Avoid inlining so we find bugs in the non-inliner connection code verilator_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dist_fixme.pl0000775000177100017500000000215213702133370021505 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; scenarios(dist => 1); my $root = ".."; my $Debug; if (!-r "$root/.git") { skip("Not in a git repository"); } else { ### Must trim output before and after our file list my $files = `cd $root && git ls-files --exclude-standard`; print "ST $files\n" if $Debug; $files =~ s/\s+/ /g; my $cmd = "cd $root && grep -n -P '(FIX"."ME|BO"."ZO)' $files | sort"; my $grep = `$cmd`; print "$grep\n"; if ($grep ne "") { my %names; foreach my $line (split /\n/, $grep) { $names{$1} = 1 if $line =~ /^([^:]+)/; } error("Files with FIX"."MEs: ",join(' ',sort keys %names)); } } ok(1); 1; verilator-4.038/test_regress/t/t_var_bad_sameas.pl0000775000177100017500000000107413702133370022303 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_alias2_unsup.out0000664000177100017500000000023113702133367022152 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_alias2_unsup.v:39:4: Unsupported: alias statements 39 | alias b = {a[3:0],a[7:4]}; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_process.out0000664000177100017500000000222313702133370021220 0ustar wsnyderwsnyder%Error: t/t_process.v:22:4: Can't find typedef: 'process' 22 | process p; | ^~~~~~~ %Error: t/t_process.v:26:20: Can't find definition of task/function: 'self' 26 | p = process::self(); | ^~~~ %Error: t/t_process.v:27:34: Can't find definition of variable: 'RUNNING' 27 | if (p.status() != process::RUNNING) $stop; | ^~~~~~~ %Error: t/t_process.v:28:34: Can't find definition of variable: 'WAITING' 28 | if (p.status() == process::WAITING) $stop; | ^~~~~~~ %Error: t/t_process.v:29:34: Can't find definition of variable: 'SUSPENDED' 29 | if (p.status() == process::SUSPENDED) $stop; | ^~~~~~~~~ %Error: t/t_process.v:30:34: Can't find definition of variable: 'KILLED' 30 | if (p.status() == process::KILLED) $stop; | ^~~~~~ %Error: t/t_process.v:31:34: Can't find definition of variable: 'FINISHED' 31 | if (p.status() == process::FINISHED) $stop; | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_array_nocolon.pl0000775000177100017500000000105313702133370024236 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_dup_bad.v0000664000177100017500000000174213702133370021453 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Outputs o, oi, og, org, // Inputs i, oi ); reg a; reg a; integer l; integer l; bit b; bit b; output o; output o; input i; input i; output oi; input oi; output og; reg og; reg og; output reg org; output reg org; sub0 sub0(.*); sub1 sub1(.*); sub2 sub2(.*); sub3 sub3(.*); endmodule module sub0 ( bad_duport, bad_duport ); output bad_duport; endmodule module sub1 ( bad_mixport, output bad_mixport ); endmodule module sub2 ( output bad_reout_port ); output bad_reout_port; endmodule module sub3 (output wire bad_rewire, output reg bad_rereg ); wire bad_rewire; reg bad_rereg; endmodule verilator-4.038/test_regress/t/t_inst_darray.v0000664000177100017500000000306013702133370021517 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by John Stevenson. // SPDX-License-Identifier: CC0-1.0 typedef logic [63:0] uid_t; typedef logic [31:0] value_t; interface the_intf #(parameter M = 5); logic valid; uid_t uid; value_t [M-1:0] values; modport i( output valid, output uid, output values ); modport t( input valid, input uid, input values ); endinterface module Contemplator #( parameter IMPL = 0, parameter M = 5, parameter N = 1 ) ( input logic clk, the_intf.i out [N-1:0] ); the_intf #(.M(M)) inp[N-1:0] (); DeepThought #( .N ( N )) ultimateAnswerer( .src ( inp ), .dst ( out )); endmodule module DeepThought #( parameter N = 1 ) ( the_intf.t src[N-1:0], the_intf.i dst[N-1:0] ); endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam M = 5; localparam N = 1; the_intf #(.M(M)) out0 [N-1:0] (); the_intf #(.M(M)) out1 [N-1:0] (); Contemplator #( .IMPL ( 0 ), .M ( M ), .N ( N )) contemplatorOfTheZerothKind( .clk ( clk ), .out ( out0 )); Contemplator #( .IMPL ( 1 ), .M ( M ), .N ( N )) contemplatorOfTheFirstKind( .clk ( clk ), .out ( out1 )); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_enum_recurse_bad2.pl0000775000177100017500000000107413702133370022740 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_split_var_1_bad.pl0000775000177100017500000000113513702133370022403 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, verilator_flags2 => ['--stats'], expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_cdc_async_debug_bad.pl0000775000177100017500000000145213702133367023264 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_cdc_async_bad.v"); compile( # --debug so we get code coverage of Cdc v_flags => ['--cdc --debug'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, fails => 1, ); files_identical("$Self->{obj_dir}/V$Self->{name}__cdc_edges.txt", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_var_overwidth_bad.cpp0000664000177100017500000000204613702133370023211 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "Vt_var_overwidth_bad.h" #include "verilated.h" //====================================================================== double main_time; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { Verilated::debug(0); VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out main_time = 0; topp->clk = 0; topp->eval(); main_time += 10; topp->clk = 0x2; // ILLEGAL topp->eval(); topp->final(); VL_DO_DANGLING(delete topp, topp); exit(0L); } verilator-4.038/test_regress/t/t_lint_modport_dir_bad.out0000664000177100017500000000037713702133370023730 0ustar wsnyderwsnyder%Error: t/t_lint_modport_dir_bad.v:26:20: Attempt to drive input-only modport: 'signal' : ... In instance t.sub 26 | assign dummy_in.signal = signal_i; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_gate_lvalue_const.pl0000775000177100017500000000105313702133370023047 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_context_bad.out0000664000177100017500000000073313702133370023031 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. : ... In instance t ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_flag_context_bad.v:9:15: Signal is not used: 'foo' : ... In instance t %Error: Exiting due to verilator-4.038/test_regress/t/t_fork_func_bad.out0000664000177100017500000000024513702133370022326 0ustar wsnyderwsnyder%Error: t/t_fork_func_bad.v:11:10: Return isn't legal under fork (IEEE 1800-2017 9.2.3) 11 | return 0; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_dpi_export_context_bad.v0000664000177100017500000000071313702133370023731 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; export "DPI-C" task dpix_task; task dpix_task(); $write("Hello in %m\n"); endtask endmodule verilator-4.038/test_regress/t/t_math_shift.v0000664000177100017500000001032113702133370021324 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs ign, ign2, ign3, ign4, ign4s, // Inputs clk ); input clk; output [31:0] ign; output [3:0] ign2; output [11:0] ign3; parameter [95:0] P6 = 6; localparam P64 = (1 << P6); // verilator lint_off WIDTH localparam [4:0] PBIG23 = 1'b1 << ~73'b0; localparam [3:0] PBIG29 = 4'b1 << 33'h100000000; // verilator lint_on WIDTH reg [31:0] right; reg [31:0] left; reg [P64-1:0] qright; reg [P64-1:0] qleft; reg [31:0] amt; assign ign = {31'h0, clk} >>> 4'bx; // bug760 assign ign2 = {amt[1:0] >> {22{amt[5:2]}}, amt[1:0] << (0 <<< amt[5:2])}; // bug1174 assign ign3 = {amt[1:0] >> {22{amt[5:2]}}, amt[1:0] >> {11{amt[5:2]}}, $signed(amt[1:0]) >>> {22{amt[5:2]}}, $signed(amt[1:0]) >>> {11{amt[5:2]}}, amt[1:0] << {22{amt[5:2]}}, amt[1:0] << {11{amt[5:2]}}}; wire [95:0] wamt = {amt,amt,amt}; output wire [95:0] ign4 = wamt >> {11{amt[5:2]}}; output wire signed [95:0] ign4s = $signed(wamt) >>> {11{amt[5:2]}}; always @* begin right = 32'h819b018a >> amt; left = 32'h819b018a << amt; qright = 64'hf784bf8f_12734089 >> amt; qleft = 64'hf784bf8f_12734089 >> amt; end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%d %x %x %x %x\n", cyc, left, right, qleft, qright); `endif if (cyc==1) begin amt <= 32'd0; if (P64 != 64) $stop; if (5'b10110>>2 != 5'b00101) $stop; if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness if (5'b10110<<2 != 5'b11000) $stop; if (5'b10110<<<2 != 5'b11000) $stop; if (5'sb10110>>2 != 5'sb00101) $stop; if (5'sb10110>>>2 != 5'sb11101) $stop; if (5'sb10110<<2 != 5'sb11000) $stop; if (5'sb10110<<<2 != 5'sb11000) $stop; // Allow >64 bit shifts if the shift amount is a constant if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; end if (cyc==2) begin amt <= 32'd28; if (left != 32'h819b018a) $stop; if (right != 32'h819b018a) $stop; if (qleft != 64'hf784bf8f_12734089) $stop; if (qright != 64'hf784bf8f_12734089) $stop; end if (cyc==3) begin amt <= 32'd31; if (left != 32'ha0000000) $stop; if (right != 32'h8) $stop; if (qleft != 64'h0000000f784bf8f1) $stop; if (qright != 64'h0000000f784bf8f1) $stop; end if (cyc==4) begin amt <= 32'd32; if (left != 32'h0) $stop; if (right != 32'h1) $stop; if (qleft != 64'h00000001ef097f1e) $stop; if (qright != 64'h00000001ef097f1e) $stop; end if (cyc==5) begin amt <= 32'd33; if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h00000000f784bf8f) $stop; if (qright != 64'h00000000f784bf8f) $stop; end if (cyc==6) begin amt <= 32'd64; if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h000000007bc25fc7) $stop; if (qright != 64'h000000007bc25fc7) $stop; end if (cyc==7) begin amt <= 32'd128; if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h0) $stop; if (qright != 64'h0) $stop; end if (cyc==8) begin if (left != 32'h0) $stop; if (right != 32'h0) $stop; if (qleft != 64'h0) $stop; if (qright != 64'h0) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_a1_first_cc.v0000664000177100017500000000061713702133367021370 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Test loop always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_fork_func2_bad.out0000664000177100017500000000033313702133370022406 0ustar wsnyderwsnyder%Error: t/t_fork_func2_bad.v:10:7: Only fork .. join_none is legal in functions. (IEEE 1800-2017 13.4.4) : ... In instance t 10 | fork | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_ref_bad1.v0000664000177100017500000000070113702133370021512 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH module t(/*AUTOARG*/); bit bad_parent; sub sub (.bad_sub_ref(bad_parent)); // Type mismatch endmodule module sub(ref real bad_sub_ref); endmodule verilator-4.038/test_regress/t/t_assert_enabled_off.pl0000775000177100017500000000120313702133367023161 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_assert_on.v"); compile( verilator_flags2 => ["--assert"], ); execute( all_run_flags => ["+verilator+noassert"], ); ok(1); 1; verilator-4.038/test_regress/t/t_langext_4.pl0000775000177100017500000000114713702133370021242 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_langext_2.v"); # This is a compile only test. compile( v_flags2 => ["+1800-2009ext+v"], ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_param.pl0000775000177100017500000000105313702133370022055 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_increment_bad.v0000664000177100017500000000057713702133370022004 0ustar wsnyderwsnydermodule t (/*AUTOARG*/ // Inputs clk ); input clk; int pos; int a; int b; int array[2][2] = '{ '{0, 1}, '{2, 3}}; string test_string = "abcd"; initial begin if (0 && test_string[pos++] != "e"); if (1 || pos-- != 1); if (a <-> --b); if (0 -> ++b); pos = (a > 0) ? a++ : --b; pos = array[0][0]++; end endmodule verilator-4.038/test_regress/t/t_sys_time.v0000664000177100017500000000122713702133370021037 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] time64; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin end else if (cyc<10) begin end else if (cyc<90) begin time64 = $time; if ($stime != time64[31:0]) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_interface_gen9.v0000664000177100017500000000125713702133370022070 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 module t1(input logic foo); initial begin $display("%m %d", foo); end endmodule module t(); logic [1:0] my_foo; generate genvar the_genvar; for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf //logic tmp_foo; //assign tmp_foo = my_foo[the_genvar]; t1 t (.foo(my_foo[the_genvar])); //t1 t (.foo(tmp_foo)); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_dpi_imp_gen_c.cpp0000664000177100017500000000215313702133370022273 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_imp_gen__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { extern void dpi_genvarTest(); } #endif //====================================================================== // Called from our Verilog code to run the tests void dpi_genvarTest() { const char* scopeName = svGetNameFromScope(svGetScope()); printf("scope name : %s\n", scopeName); } verilator-4.038/test_regress/t/t_preproc_inc_bad.out0000664000177100017500000000040213702133370022650 0ustar wsnyderwsnyder%Error: t/t_preproc_inc_inc_bad.vh:11:1: syntax error, unexpected endmodule, expecting IDENTIFIER or randomize 11 | endmodule | ^~~~~~~~~ t/t_preproc_inc_bad.v:10:1: ... note: In file included from t_preproc_inc_bad.v %Error: Exiting due to verilator-4.038/test_regress/t/t_time_print.v0000664000177100017500000000201213702133370021346 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; timeunit 1ns; timeprecision 1ps; time t; initial begin t = 10ns; $write("[%0t] In %m: Hi\n", $time); $printtimescale; $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-3, 0, "-my-ms", 8); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-3, 1, "-my-ms", 10); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-6, 2, "-my-us", 12); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-9, 3, "-my-ns", 13); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-12, 3, "-my-ps", 13); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-15, 4, "-my-fs", 14); $write("Time: '%t' 10ns=%0t\n", $time, t); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_colonplus_bad.v0000664000177100017500000000051213702133370023051 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs z ); reg [3:0] r = 4'b1010; output [2:1] z = r[2 :+ 1]; endmodule verilator-4.038/test_regress/t/t_lint_once_bad.pl0000775000177100017500000000117013702133370022131 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wwarn-UNUSED"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_default_bad.v0000664000177100017500000000046013702133370022613 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m #(parameter int Foo); endmodule module t (/*AUTOARG*/); m foo(); endmodule verilator-4.038/test_regress/t/t_param_real2.v0000664000177100017500000000157313702133370021374 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module foo #( parameter real bar = 2.0) (); endmodule module t(); genvar m, r; generate for (m = 10; m <= 20; m+=10) begin : gen_m for (r = 0; r <= 1; r++) begin : gen_r localparam real lparam = m + (r + 0.5); initial begin if (lparam != foo_inst.bar) begin $display("%m: lparam != foo_inst.bar (%f, %f)", lparam, foo_inst.bar); $stop(); end end foo #(.bar (lparam)) foo_inst (); end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_preproc_def09.v0000664000177100017500000000347713702133370021655 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `undefineall // Definitions as speced // Note there are trailing spaces, which spec doesn't show properly `define D(x,y) initial $display("start", x , y, "end"); '`D( "msg1" , "msg2" )' 'initial $display("start", "msg1" , "msg2" , "end");' '`D( " msg1", )' 'initial $display("start", " msg1" , , "end");' '`D(, "msg2 ")' 'initial $display("start", , "msg2 ", "end");' '`D(,)' 'initial $display("start", , , "end");' '`D( , )' 'initial $display("start", , , "end");' //`D("msg1") // ILLEGAL: only one argument //`D() // ILLEGAL: only one empty argument //`D(,,) // ILLEGAL: more actual than formal arguments // Defaults: `define MACRO1(a=5,b="B",c) $display(a,,b,,c); '`MACRO1 ( , 2, 3 )' '$display(5,,2,,3);' '`MACRO1 ( 1 , , 3 )' '$display(1 ,,"B",,3 );' '`MACRO1 ( , 2, )' '$display(5,,2,,);' //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c `define MACRO2(a=5, b, c="C") $display(a,,b,,c); '`MACRO2 (1, , 3)' '$display(5,,,,"C");' '`MACRO2 (, 2, )' '$display(5,,2,,"C");' '`MACRO2 (, 2)' '$display(5,,2,,"C");' `define MACRO3(a=5, b=0, c="C") $display(a,,b,,c); '`MACRO3 ( 1 )' '$display(1 ,,0,,"C");' '`MACRO3 ( )' '$display(5,,0,,"C");' //`MACRO3 // ILLEGAL: parentheses required `define DTOP(a,b) a + b '`DTOP( `DTOP(b,1), `DTOP(42,a) )' 'b + 1 + 42 + a' // Local tests `define MACROQUOTE(a="==)",b="((((",c=() ) 'a b c' `MACROQUOTE(); '"==)" "((((" () '; // Also check our line counting doesn't go bad `define MACROPAREN(a=(6), b=(eq=al), c) 'a b c' `MACROPAREN( ,, ZOT) HERE-`__LINE__ - Line71 //====================================================================== verilator-4.038/test_regress/t/t_stream.pl0000775000177100017500000000105313702133370020644 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_optm_redor.pl0000775000177100017500000000127613702133370021532 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", qr/rstn_r/); file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}__Slow.cpp", qr/rstn_r/); ok(1); 1; verilator-4.038/test_regress/t/t_flag_ldflags.pl0000775000177100017500000000337513702133370021767 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); run(cmd => ["cd $Self->{obj_dir}" ." && $ENV{CXX} -c ../../t/t_flag_ldflags_a.cpp" ." && ar -cr t_flag_ldflags_a.a t_flag_ldflags_a.o" ." && ranlib t_flag_ldflags_a.a "], check_finished => 0); run(cmd => ["cd $Self->{obj_dir}" ." && $ENV{CXX} -fPIC -c ../../t/t_flag_ldflags_so.cpp" ." && $ENV{CXX} -shared -o t_flag_ldflags_so.so -lc t_flag_ldflags_so.o"], check_finished => 0); compile( # Pass multiple -D's so we check quoting works properly v_flags2 => ["-CFLAGS '-DCFLAGS_FROM_CMDLINE -DCFLAGS2_FROM_CMDLINE' ", "t/t_flag_ldflags_c.cpp", "t_flag_ldflags_a.a", "t_flag_ldflags_so.so",], ); # On OS X, LD_LIBRARY_PATH is ignored, so set rpath of the exe to find the .so if ($^O eq "darwin") { run(cmd => ["cd $Self->{obj_dir}" ." && install_name_tool -add_rpath \@executable_path/." ." $Self->{VM_PREFIX}"], check_finished => 0); run(cmd => ["cd $Self->{obj_dir}" ." && install_name_tool -change t_flag_ldflags_so.so" ." \@rpath/t_flag_ldflags_so.so $Self->{VM_PREFIX}"], check_finished => 0); } execute( check_finished => 1, run_env => "LD_LIBRARY_PATH=$Self->{obj_dir}", ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_bad_digit.pl0000775000177100017500000000114213702133370023646 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_modport_export.v0000664000177100017500000000237713702133370024317 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test of the export parameter used with modport // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 interface test_if; // Pre-declare function extern function myfunc (input logic val); // Interface variable logic data; // Modport modport mp_e( export myfunc, output data ); // Modport modport mp_i( import myfunc, output data ); endinterface // test_if module t (/*AUTOARG*/ // Inputs clk ); input clk; test_if i (); testmod_callee testmod_callee_i (.ie (i.mp_e)); testmod_caller testmod_caller_i (.clk (clk), .ii (i.mp_i)); endmodule module testmod_callee ( test_if.mp_e ie ); function automatic logic ie.myfunc (input logic val); begin myfunc = (val == 1'b0); end endfunction endmodule // testmod_caller module testmod_caller ( input clk, test_if.mp_i ii ); always @(posedge clk) begin ii.data = 1'b0; if (ii.myfunc (1'b0)) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-4.038/test_regress/t/t_altera_lpm_xor.pl0000775000177100017500000000120613702133367022367 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/tsub/0000775000177100017500000000000013702335701017446 5ustar wsnyderwsnyderverilator-4.038/test_regress/t/tsub/t_flag_f_tsub_inc.v0000664000177100017500000000010113343101620023244 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module `define GOT_DEF5 verilator-4.038/test_regress/t/tsub/t_flag_f_tsub.vc0000664000177100017500000000013513343101620022565 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module +define+GOT_DEF4=1 +incdir+. t_flag_f_tsub.v verilator-4.038/test_regress/t/tsub/t_flag_f_tsub.v0000664000177100017500000000010113343101620022413 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module `define GOT_DEF6 verilator-4.038/test_regress/t/t_func_const_packed_array_bad.v0000664000177100017500000000162313702133370024657 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; localparam [ 1 : 0 ] [ 31 : 0 ] P = {32'd5, 32'd1}; localparam P6 = f_add(P); localparam P14 = f_add2(2, 3, f_add(P)); localparam P24 = f_add2(7, 8, 9); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end function integer f_add(input [ 1 : 0 ] [ 31 : 0 ] params); f_add = params[0]+params[1]; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); logic [ 1 : 0 ] [ 31 : 0 ] params; params[0] = a; params[1] = b; f_add2 = f_add(params)+c; endfunction endmodule verilator-4.038/test_regress/t/t_multitop_sig.cpp0000664000177100017500000000235413702133370022241 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include "Vt_multitop_sig.h" // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } int main(int argc, char* argv[]) { Vt_multitop_sig* topp = new Vt_multitop_sig(""); Verilated::debug(0); { topp->a__02Ein = 0; topp->b__02Ein = 0; topp->uniq_in = 0; topp->eval(); CHECK_RESULT(topp->a__02Eout, 1); CHECK_RESULT(topp->b__02Eout, 0); CHECK_RESULT(topp->uniq_out, 1); topp->a__02Ein = 1; topp->b__02Ein = 1; topp->uniq_in = 1; topp->eval(); CHECK_RESULT(topp->a__02Eout, 0); CHECK_RESULT(topp->b__02Eout, 1); CHECK_RESULT(topp->uniq_out, 0); } printf("*-* All Finished *-*\n"); } verilator-4.038/test_regress/t/t_flag_werror.v0000664000177100017500000000045513702133370021516 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); // Width error below wire [3:0] foo = 6'h2e; endmodule verilator-4.038/test_regress/t/t_interface_modport_import.pl0000775000177100017500000000105313702133370024447 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_bad_hide.out0000664000177100017500000000132513702133370022133 0ustar wsnyderwsnyder%Warning-VARHIDDEN: t/t_var_bad_hide.v:16:14: Declaration of signal hides declaration in upper scope: 'top' 16 | output top; | ^~~ t/t_var_bad_hide.v:13:12: ... Location of original declaration 13 | integer top; | ^~~ ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Warning-VARHIDDEN: t/t_var_bad_hide.v:22:18: Declaration of signal hides declaration in upper scope: 'top' 22 | integer top; | ^~~ t/t_var_bad_hide.v:13:12: ... Location of original declaration 13 | integer top; | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_order_wireloop.pl0000775000177100017500000000160213702133370022404 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2005 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. # However we no longer gate optimize this # Can't use expect_filename here as unstable output expect => '%Warning-UNOPT: t/t_order_wireloop.v:\d+:\d+: Signal unoptimizable: Feedback to public clock or circular logic: \'bar\' ', ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_hdr_cc.out0000664000177100017500000000371013702133370023035 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sat Feb 29 09:09:40 2020 $end $timescale 1ps $end $scope module topa $end $var wire 1 3 clk $end $scope module t $end $var wire 32 + c_trace_on [31:0] $end $var wire 1 3 clk $end $var wire 32 # cyc [31:0] $end $scope module sub $end $var wire 32 ; inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $var wire 1 N clk $end $scope module t $end $var wire 32 ^ c_trace_on [31:0] $end $var wire 1 N clk $end $var wire 32 V cyc [31:0] $end $var real 64 > r $end $scope module sub $end $var wire 32 f inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # b00000000000000000000000000000000 + 03 b00000000000000000000000000000001 ; r0 > 0N b00000000000000000000000000000001 V b00000000000000000000000000000000 ^ b00000000000000000000000000000010 f #10 b00000000000000000000000000000010 # b00000000000000000000000000000011 + 13 r0.1 > 1N #15 03 0N #20 b00000000000000000000000000000011 # b00000000000000000000000000000100 + 13 r0.2 > 1N #25 03 0N #30 b00000000000000000000000000000100 # b00000000000000000000000000000101 + 13 r0.3 > 1N #35 03 0N #40 b00000000000000000000000000000101 # b00000000000000000000000000000110 + 13 r0.4 > 1N #45 03 0N #50 b00000000000000000000000000000110 # b00000000000000000000000000000111 + 13 r0.5 > 1N #55 03 0N #60 b00000000000000000000000000000111 # b00000000000000000000000000001000 + 13 r0.6 > 1N #65 03 0N #70 b00000000000000000000000000001000 # b00000000000000000000000000001001 + 13 r0.7 > 1N #75 03 0N #80 b00000000000000000000000000001001 # b00000000000000000000000000001010 + 13 r0.7999999999999999 > 1N #85 03 0N #90 b00000000000000000000000000001010 # b00000000000000000000000000001011 + 13 r0.8999999999999999 > 1N #95 03 0N #100 b00000000000000000000000000001011 # b00000000000000000000000000001100 + 13 r0.9999999999999999 > 1N verilator-4.038/test_regress/t/t_prot_lib.v0000664000177100017500000001220113702133370021007 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 `define DRIVE(sig) \ /* Just throw a bunch of bits at the input */ \ /* verilator lint_off WIDTH */ \ sig``_in <= {8{crc}}; \ /* verilator lint_on WIDTH */ `define CHECK(sig) \ if (cyc > 0 && sig``_in != sig``_out) begin \ $display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \ sig``_in, sig``_out); \ $stop; \ end module t #(parameter GATED_CLK = 0) (/*AUTOARG*/ // Inputs clk ); input clk; localparam last_cyc = `ifdef TEST_BENCHMARK `TEST_BENCHMARK; `else 10; `endif genvar x; generate for (x = 0; x < 2; x = x + 1) begin: gen_loop integer cyc = 0; reg [63:0] crc = 64'h5aef0c8d_d70a4497; logic [31:0] accum_in; logic [31:0] accum_out; logic accum_bypass; logic [31:0] accum_bypass_out; logic [31:0] accum_out_expect; logic [31:0] accum_bypass_out_expect; logic s1_in; logic s1_out; logic [1:0] s2_in; logic [1:0] s2_out; logic [7:0] s8_in; logic [7:0] s8_out; logic [32:0] s33_in; logic [32:0] s33_out; logic [63:0] s64_in; logic [63:0] s64_out; logic [64:0] s65_in; logic [64:0] s65_out; logic [128:0] s129_in; logic [128:0] s129_out; logic [3:0] [31:0] s4x32_in; logic [3:0] [31:0] s4x32_out; wire clk_en = crc[0]; secret secret ( .accum_in, .accum_out, .accum_bypass, .accum_bypass_out, .s1_in, .s1_out, .s2_in, .s2_out, .s8_in, .s8_out, .s33_in, .s33_out, .s64_in, .s64_out, .s65_in, .s65_out, .s129_in, .s129_out, .s4x32_in, .s4x32_out, .clk_en, .clk); always @(posedge clk) begin `ifdef TEST_VERBOSE $display("[%0t] x=%0d, cyc=%0d accum_in=%0d accum_out=%0d accum_bypass_out=%0d", $time, x, cyc, accum_in, accum_out, accum_bypass_out); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; accum_in <= accum_in + 5; `DRIVE(s1) `DRIVE(s2) `DRIVE(s8) `DRIVE(s33) `DRIVE(s64) `DRIVE(s65) `DRIVE(s129) `DRIVE(s4x32) if (cyc == 0) begin accum_in <= x*100; accum_bypass <= '0; end else if (cyc > 0) begin if (accum_out_expect != accum_out) begin $display("%%Error: (%m) accum_out expected %0d got %0d", accum_out_expect, accum_out); $stop; end if (accum_bypass_out_expect != accum_bypass_out) begin $display("%%Error: (%m) accum_bypass_out expected %0d got %0d", accum_bypass_out_expect, accum_bypass_out); $stop; end end if (cyc == 5) accum_bypass <= '1; if (x == 0 && cyc == last_cyc) begin $display("final cycle = %0d", cyc); $write("*-* All Finished *-*\n"); $finish; end end logic possibly_gated_clk; if (GATED_CLK != 0) begin: yes_gated_clock logic clk_en_latch /*verilator clock_enable*/; /* verilator lint_off COMBDLY */ always_comb if (clk == '0) clk_en_latch <= clk_en; /* verilator lint_on COMBDLY */ assign possibly_gated_clk = clk & clk_en_latch; end else begin: no_gated_clock assign possibly_gated_clk = clk; end always @(posedge possibly_gated_clk) begin // 7 is the secret_value inside the secret module accum_out_expect <= accum_in + accum_out_expect + 7; end always @(*) begin // XSim (and maybe all event simulators?) sees the moment where // s1_in has not yet propagated to s1_out, however, they do always // both change at the same time /* verilator lint_off STMTDLY */ #1; /* verilator lint_on STMTDLY */ `CHECK(s1) `CHECK(s2) `CHECK(s8) `CHECK(s33) `CHECK(s64) `CHECK(s65) `CHECK(s129) `CHECK(s4x32) end assign accum_bypass_out_expect = accum_bypass ? accum_in : accum_out_expect; end endgenerate endmodule verilator-4.038/test_regress/t/t_flag_wpedantic_bad.out0000664000177100017500000000021213702133370023313 0ustar wsnyderwsnyder%Error: t/t_flag_wpedantic_bad.v:8:8: syntax error, unexpected global 8 | reg global; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_math_tri.v0000664000177100017500000000112213702133370021004 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg [3:0] a; reg [99:0] x; initial begin a = 4'b010x; if (a[3:2] !== 2'b01) $stop; if (|a !== 1'b1) $stop; if (&a !== 1'b0) $stop; x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_flag_timescale_override.out0000664000177100017500000000006213702133370024377 0ustar wsnyderwsnyderTime scale of t is 1ms / 1us *-* All Finished *-* verilator-4.038/test_regress/t/t_select_lhs_oob.pl0000775000177100017500000000105313702133370022335 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_stop_bad.pl0000775000177100017500000000115513702133370021147 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( fails => 1, check_finished => 0, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_names.pl0000775000177100017500000000117113702133370021446 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ["--mod-prefix modPrefix --top-module t --l2-name l2Name"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_local.pl0000775000177100017500000000105313702133370021313 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_default.v0000664000177100017500000000064013702133370022005 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m #(parameter int Foo); endmodule module t (/*AUTOARG*/); m #(10) foo(); initial begin if (foo.Foo != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_unconnected.v0000664000177100017500000000166213702133370021513 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; wire o_n; wire o_0; wire o_1; // verilator lint_off PINMISSING sub_0 sub_0(.o_0); sub_1 sub_1(.o_1); sub_n sub_n(.o_n); // verilator lint_on PINMISSING always @ (posedge clk) begin if (o_0 !== 1'b0) $stop; if (o_1 !== 1'b1) $stop; //4-state if (o_n !== 1'bz) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule `unconnected_drive pull0 module sub_0 (input i, output wire o_0); assign o_0 = i; endmodule `unconnected_drive pull1 module sub_1 (input i, output wire o_1); assign o_1 = i; endmodule `nounconnected_drive module sub_n (input i, output wire o_n); assign o_n = i; endmodule verilator-4.038/test_regress/t/t_x_assign_0.pl0000775000177100017500000000131213702133370021401 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_x_assign.v"); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--x-assign 0 --exe $Self->{t_dir}/t_x_assign.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_inp_init.cpp0000664000177100017500000000253013702133367022166 0ustar wsnyderwsnyder// This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Test defines // Generated header #include "Vt_clk_inp_init.h" // General headers #include "verilated.h" Vt_clk_inp_init* topp; vluint64_t main_time; double sc_time_stamp() { return main_time; } void oneTest(int seed) { double sim_time = 1000; #ifdef TEST_VERBOSE VL_PRINTF("== Seed=%d\n", seed); #endif // Randomise initial state srand48(seed); srand48(5); Verilated::randReset(123); topp = new Vt_clk_inp_init("top"); // Start not in reset topp->rst_n = 1; topp->clk = 0; topp->eval(); // Tick for a little bit while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { topp->clk = 0; topp->eval(); main_time += 5; topp->clk = 1; topp->eval(); main_time += 5; } if (!Verilated::gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); VL_DO_DANGLING(delete topp, topp); } int main(int argc, char** argv, char** env) { Verilated::commandArgs(argc, argv); #if VL_DEBUG // Verilated::debug(1); #endif for (int seed = 123; seed < 133; ++seed) { oneTest(seed); } return 0; } verilator-4.038/test_regress/t/t_pp_resetall_bad.v0000664000177100017500000000043613702133370022324 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `resetall // Ok module t; `resetall // Bad endmodule `resetall // Ok verilator-4.038/test_regress/t/t_param_default_bad.out0000664000177100017500000000043113702133370023153 0ustar wsnyderwsnyder%Error: t/t_param_default_bad.v:7:26: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'Foo' : ... In instance t.foo 7 | module m #(parameter int Foo); | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_suggest_bad.v0000664000177100017500000000052213702133370022337 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg foobar; task boobar; endtask initial begin if (foobat) $stop; boobat; end endmodule verilator-4.038/test_regress/t/t_inst_dtree_inld.pl0000775000177100017500000000123013702133370022514 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_D'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_dup_ign.pl0000775000177100017500000000076313702133370021644 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_param_mem_attr.pl0000775000177100017500000000102613702133370022341 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Compile only test. compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen2.v0000664000177100017500000000321413702133370022054 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc #(2) itopa(); ifc #(4) itopb(); sub ca (.isub(itopa), .clk); sub cb (.isub(itopb), .clk); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo); `endif cyc <= cyc + 1; itopa.valuei <= cyc[1:0]; itopb.valuei <= cyc[3:0]; if (cyc==1) begin if (itopa.WIDTH != 2) $stop; if (itopb.WIDTH != 4) $stop; if ($bits(itopa.valueo) != 2) $stop; if ($bits(itopb.valueo) != 4) $stop; if ($bits(itopa.out_modport.valueo) != 2) $stop; if ($bits(itopb.out_modport.valueo) != 4) $stop; end if (cyc==4) begin if (itopa.valueo != 2'b11) $stop; if (itopb.valueo != 4'b0011) $stop; end if (cyc==5) begin if (itopa.valueo != 2'b00) $stop; if (itopb.valueo != 4'b0100) $stop; end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule interface ifc #(parameter WIDTH = 1); // verilator lint_off MULTIDRIVEN logic [WIDTH-1:0] valuei; logic [WIDTH-1:0] valueo; // verilator lint_on MULTIDRIVEN modport out_modport (input valuei, output valueo); endinterface // Note not parameterized module sub ( ifc.out_modport isub, input clk ); always @(posedge clk) isub.valueo <= isub.valuei + 1; endmodule verilator-4.038/test_regress/t/t_math_imm2.cpp0000664000177100017500000000317013702133370021374 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include "Vt_math_imm2.h" QData MaskVal(int lbit, int hbit) { QData val; for (val = 0; lbit <= hbit; lbit++) val |= (1ULL << lbit); return val; } int main(int argc, char* argv[]) { Verilated::debug(0); Vt_math_imm2* sim = new Vt_math_imm2; int lbit, hbit; int errs = 0; for (lbit = 0; lbit < 32; lbit++) { for (hbit = lbit; hbit < 32; hbit++) { QData expected; sim->LowMaskSel_Bot = lbit; sim->LowMaskSel_Top = lbit; sim->HighMaskSel_Bot = hbit; sim->HighMaskSel_Top = hbit; sim->eval(); expected = ((MaskVal(sim->LowMaskSel_Top, sim->HighMaskSel_Top) << 32ULL) | MaskVal(sim->LowMaskSel_Bot, sim->HighMaskSel_Bot)); if (sim->LogicImm != expected) { printf("%%Error: %d.%d,%d.%d -> %016" VL_PRI64 "x/%016" VL_PRI64 "x -> %016" VL_PRI64 "x (expected %016" VL_PRI64 "x)\n", sim->LowMaskSel_Top, sim->HighMaskSel_Top, sim->LowMaskSel_Bot, sim->HighMaskSel_Bot, sim->LowLogicImm, sim->HighLogicImm, sim->LogicImm, expected); errs=1; } } } if (errs) { vl_stop(__FILE__, __LINE__, "TOP-cpp"); exit(10); } else { printf("*-* All Finished *-*\n"); exit(0); } } verilator-4.038/test_regress/t/t_mem_slice_bad.out0000664000177100017500000000365713702133370022321 0ustar wsnyderwsnyder%Error: t/t_mem_slice_bad.v:39:31: Slice selection index '[2:0]' outside data type's '[1:0]' : ... In instance t 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ %Error: t/t_mem_slice_bad.v:39:36: Slice selection index '[3:0]' outside data type's '[2:0]' : ... In instance t 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ %Error: t/t_mem_slice_bad.v:39:72: Slice selection index '[2:0]' outside data type's '[1:0]' : ... In instance t 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ %Error: t/t_mem_slice_bad.v:39:77: Slice selection index '[3:0]' outside data type's '[2:0]' : ... In instance t 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ %Error: t/t_mem_slice_bad.v:39:105: Slice selection index '[3:0]' outside data type's '[1:0]' : ... In instance t 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ %Error: t/t_mem_slice_bad.v:51:41: Slice selection index '[8:0]' outside data type's '[7:0]' : ... In instance t 51 | active_command4[7:0] <= command_A4[8:0]; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_array_pattern_bad.out0000664000177100017500000000036113702133367023232 0ustar wsnyderwsnyder%Error: t/t_array_pattern_bad.v:24:18: Assignment pattern key 'valids' not found as member : ... In instance t 24 | valids: '1}; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_gen_cond_bitrange.pl0000775000177100017500000000105313702133370023000 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_gen.pl0000775000177100017500000000105313702133370021135 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_param.v0000664000177100017500000000264613702133370021167 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function integer mon_check(); `endif module t #( parameter int WIDTH /* verilator public_flat_rd */ = 32 ) (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; localparam int DEPTH /* verilator public_flat_rd */ = 16; localparam longint PARAM_LONG /* verilator public_flat_rd */ = 64'hFEDCBA9876543210; localparam string PARAM_STR /* verilator public_flat_rd */ = "'some string value'"; reg [WIDTH-1:0] mem0 [DEPTH:1] /*verilator public_flat_rw @(posedge clk) */; integer i, status; // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_param.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-4.038/test_regress/t/t_unopt_converge_initial.v0000664000177100017500000000074213702133370023752 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs x, // Inputs clk ); `ifdef ALLOW_UNOPT /*verilator lint_off UNOPTFLAT*/ `endif input clk; output [31:0] x; // Avoid eliminating x reg [31:0] x; always @* begin x = x ^ $random; end endmodule verilator-4.038/test_regress/t/t_typedef_signed.v0000664000177100017500000000377113702133370022202 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug456 typedef logic signed [34:0] rc_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [34:0] rc = crc[34:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic o; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .o (o), // Inputs .rc (rc), .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, o}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h7211d24a17b25ec9 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test( output logic o, input rc_t rc, input logic clk); localparam RATIO = 2; rc_t rc_d[RATIO:1]; always_ff @(posedge clk) begin integer k; rc_d[1] <= rc; for( k=2; k 1); run(cmd => ["../bin/verilator_coverage", '--invalid-dash'], logfile => $Self->{run_log_filename}, fails => 1, expect_filename => $Self->{golden_filename}, verilator_run => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_shift.v0000664000177100017500000000241613702133370021157 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; integer i; reg [63:0] mem [7:0]; always @ (posedge clk) begin if (cyc==1) begin for (i=0; i<8; i=i+1) begin mem[i] <= 64'h0; end end else begin mem[0] <= crc; for (i=1; i<8; i=i+1) begin mem[i] <= mem[i-1]; end end end wire [63:0] outData = mem[7]; always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData); cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc==90) begin if (outData != 64'h1265e3bddcd9bc27) $stop; end else if (cyc==91) begin if (outData != 64'h24cbc77bb9b3784e) $stop; end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_lint_ifdepth_bad.pl0000775000177100017500000000121413702133370022627 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); lint( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_restore_bad.out0000664000177100017500000000062013702133370023060 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_lint_restore_bad.v:19:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... In instance t 19 | initial five = 64'h1; | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_preproc_def09.out0000664000177100017500000000255413702133370022212 0ustar wsnyderwsnyder`line 1 "t/t_preproc_def09.v" 1 `line 3 "t/t_preproc_def09.v" 0 `line 9 "t/t_preproc_def09.v" 0 'initial $display("start", "msg1" , "msg2", "end");' 'initial $display("start", "msg1" , "msg2" , "end");' 'initial $display("start", " msg1" , , "end");' 'initial $display("start", " msg1" , , "end");' 'initial $display("start", , "msg2 ", "end");' 'initial $display("start", , "msg2 ", "end");' 'initial $display("start", , , "end");' 'initial $display("start", , , "end");' 'initial $display("start", , , "end");' 'initial $display("start", , , "end");' `line 26 "t/t_preproc_def09.v" 0 '$display(5,,2,,3);' '$display(5,,2,,3);' '$display(1,,"B",,3);' '$display(1 ,,"B",,3 );' '$display(5,,2,,);' '$display(5,,2,,);' `line 36 "t/t_preproc_def09.v" 0 '$display(1,,,,3);' '$display(5,,,,"C");' '$display(5,,2,,"C");' '$display(5,,2,,"C");' '$display(5,,2,,"C");' '$display(5,,2,,"C");' `line 44 "t/t_preproc_def09.v" 0 '$display(1,,0,,"C");' '$display(1 ,,0,,"C");' '$display(5,,0,,"C");' '$display(5,,0,,"C");' `line 51 "t/t_preproc_def09.v" 0 'b + 1 + 42 + a' 'b + 1 + 42 + a' `line 55 "t/t_preproc_def09.v" 0 '"==)" "((((" () '; '"==)" "((((" () '; `line 60 "t/t_preproc_def09.v" 0 `line 71 "t/t_preproc_def09.v" 0 '(6) (eq=al) ZOT' HERE-72 - Line71 `line 74 "t/t_preproc_def09.v" 0 `line 76 "t/t_preproc_def09.v" 2 verilator-4.038/test_regress/t/t_time_vpi_100s10ms.out0000664000177100017500000000120513702133370022621 0ustar wsnyderwsnyder:: In top.t Time scale of t is 100s / 10ms [100000000] time%0d=10000 123%0t=1230000 dig%0t=0 dig%0d=0 rdig%0t=543 rdig%0f=0.054321 [0.000000ns] time%0d=10000 123%0t=12300000000000.000000ns dig%0t=0.000000ns dig%0d=0 rdig%0t=5432109876.543210ns rdig%0f=0.054321 [0.000000ns] stime%0t=0.000000ns stime%0d=10000 stime%0f=10000.000000 [0.000000ns] rtime%0t=0.000000ns rtime%0d=10000 rtime%0f=10000.000000 global vpiSimTime = 0,100000000 vpiScaledRealTime = 1e+08 global vpiTimeUnit = -2 vpiTimePrecision = -2 top.t vpiSimTime = 0,100000000 vpiScaledRealTime = 10000 top.t vpiTimeUnit = 2 vpiTimePrecision = -2 *-* All Finished *-* verilator-4.038/test_regress/t/t_sys_file_basic_mcd_test2_0.dat0000664000177100017500000000020213702133370024637 0ustar wsnyderwsnyderScotland is the greatest country. All other countries are inferior. Woe betide those to stand against the mighty Scottish nation. verilator-4.038/test_regress/t/t_lint_import_name_bad.v0000664000177100017500000000044413702133370023351 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package defs; int sig; endpackage import defs::sigs; module t; endmodule verilator-4.038/test_regress/t/t_interface_array.pl0000775000177100017500000000105313702133370022507 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_verilate.pl0000775000177100017500000000422513702133370022161 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_flag_make_cmake.v"); # We expect below that Vt_flag_verilate.mk and others are not in the build # tree already when doing --no-verilate, so we must remove them when # re-running the test. clean_objs(); compile( # Don't call cmake nor gmake from driver.pl. Nothing should be done here. verilator_make_cmake => 0, verilator_make_gmake => 0, verilator_flags2 => ['--exe --cc --no-verilate', '../' . $Self->{main_filename}] ); # --no-verilate should skip verilation if ( -e $Self->{obj_dir} . '/Vt_flag_verilate.mk' ) { $Self->error('Vt_flag_verilate.mk is unexpectedly created'); } # --verilate this time compile( # Don't call cmake nor gmake from driver.pl. Just verilate here. verilator_make_cmake => 0, verilator_make_gmake => 0, verilator_flags2 => ['--exe --cc --verilate', '../' . $Self->{main_filename}] ); # must be verilated this time if ( ! -e $Self->{obj_dir} . '/Vt_flag_verilate.mk' ) { $Self->error('Vt_flag_verilate.mk does not exist'); } # Just build, no verilation. .tree must not be saved even with --dump-tree option. compile( # Don't call cmake nor gmake from driver.pl. Just build here verilator_make_cmake => 0, verilator_make_gmake => 0, verilator_flags2 => ['--exe --cc --build --no-verilate', '../' . $Self->{main_filename}, '--debugi 1 --dump-tree --dump-tree-addrids'], ); # The previous run must not verilated, only build is expected. if ( -e $Self->{obj_dir} . '/Vt_flag_verilate_990_final.tree' ) { $Self->error('Unexpectedly verilated.'); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_huge_sub3.v0000664000177100017500000003146713702133367022101 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub3 (/*AUTOARG*/ // Outputs outr, // Inputs clk, index ); input clk; input [9:0] index; output [3:0] outr; // ============================= /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [3:0] outr; // End of automatics // ============================= // Created from perl //for $i (0..255) { $r=rand(4); printf "\t8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end\n", $i, //rand(256); }; // Reset cheating initial outr = 4'b0; always @(posedge clk) begin case (index[7:0]) 8'h00: begin outr <= 4'h0; end 8'h01: begin /*No Change*/ end 8'h02: begin outr <= outr^index[8:5]^4'ha; end 8'h03: begin outr <= outr^index[8:5]^4'h4; end 8'h04: begin outr <= outr^index[8:5]^4'hd; end 8'h05: begin outr <= outr^index[8:5]^4'h1; end 8'h06: begin outr <= outr^index[8:5]^4'hf; end 8'h07: begin outr <= outr^index[8:5]^4'he; end 8'h08: begin outr <= outr^index[8:5]^4'h0; end 8'h09: begin outr <= outr^index[8:5]^4'h4; end 8'h0a: begin outr <= outr^index[8:5]^4'h5; end 8'h0b: begin outr <= outr^index[8:5]^4'ha; end 8'h0c: begin outr <= outr^index[8:5]^4'h2; end 8'h0d: begin outr <= outr^index[8:5]^4'hf; end 8'h0e: begin outr <= outr^index[8:5]^4'h5; end 8'h0f: begin outr <= outr^index[8:5]^4'h0; end 8'h10: begin outr <= outr^index[8:5]^4'h3; end 8'h11: begin outr <= outr^index[8:5]^4'hb; end 8'h12: begin outr <= outr^index[8:5]^4'h0; end 8'h13: begin outr <= outr^index[8:5]^4'hf; end 8'h14: begin outr <= outr^index[8:5]^4'h3; end 8'h15: begin outr <= outr^index[8:5]^4'h5; end 8'h16: begin outr <= outr^index[8:5]^4'h7; end 8'h17: begin outr <= outr^index[8:5]^4'h2; end 8'h18: begin outr <= outr^index[8:5]^4'h3; end 8'h19: begin outr <= outr^index[8:5]^4'hb; end 8'h1a: begin outr <= outr^index[8:5]^4'h5; end 8'h1b: begin outr <= outr^index[8:5]^4'h4; end 8'h1c: begin outr <= outr^index[8:5]^4'h2; end 8'h1d: begin outr <= outr^index[8:5]^4'hf; end 8'h1e: begin outr <= outr^index[8:5]^4'h0; end 8'h1f: begin outr <= outr^index[8:5]^4'h4; end 8'h20: begin outr <= outr^index[8:5]^4'h6; end 8'h21: begin outr <= outr^index[8:5]^4'ha; end 8'h22: begin outr <= outr^index[8:5]^4'h6; end 8'h23: begin outr <= outr^index[8:5]^4'hb; end 8'h24: begin outr <= outr^index[8:5]^4'ha; end 8'h25: begin outr <= outr^index[8:5]^4'he; end 8'h26: begin outr <= outr^index[8:5]^4'h7; end 8'h27: begin outr <= outr^index[8:5]^4'ha; end 8'h28: begin outr <= outr^index[8:5]^4'h3; end 8'h29: begin outr <= outr^index[8:5]^4'h8; end 8'h2a: begin outr <= outr^index[8:5]^4'h1; end 8'h2b: begin outr <= outr^index[8:5]^4'h8; end 8'h2c: begin outr <= outr^index[8:5]^4'h4; end 8'h2d: begin outr <= outr^index[8:5]^4'h4; end 8'h2e: begin outr <= outr^index[8:5]^4'he; end 8'h2f: begin outr <= outr^index[8:5]^4'h8; end 8'h30: begin outr <= outr^index[8:5]^4'ha; end 8'h31: begin outr <= outr^index[8:5]^4'h7; end 8'h32: begin outr <= outr^index[8:5]^4'h0; end 8'h33: begin outr <= outr^index[8:5]^4'h3; end 8'h34: begin outr <= outr^index[8:5]^4'h1; end 8'h35: begin outr <= outr^index[8:5]^4'h3; end 8'h36: begin outr <= outr^index[8:5]^4'h4; end 8'h37: begin outr <= outr^index[8:5]^4'h6; end 8'h38: begin outr <= outr^index[8:5]^4'h4; end 8'h39: begin outr <= outr^index[8:5]^4'hb; end 8'h3a: begin outr <= outr^index[8:5]^4'h7; end 8'h3b: begin outr <= outr^index[8:5]^4'h1; end 8'h3c: begin outr <= outr^index[8:5]^4'h2; end 8'h3d: begin outr <= outr^index[8:5]^4'h0; end 8'h3e: begin outr <= outr^index[8:5]^4'h2; end 8'h3f: begin outr <= outr^index[8:5]^4'ha; end 8'h40: begin outr <= outr^index[8:5]^4'h7; end 8'h41: begin outr <= outr^index[8:5]^4'h5; end 8'h42: begin outr <= outr^index[8:5]^4'h5; end 8'h43: begin outr <= outr^index[8:5]^4'h4; end 8'h44: begin outr <= outr^index[8:5]^4'h8; end 8'h45: begin outr <= outr^index[8:5]^4'h5; end 8'h46: begin outr <= outr^index[8:5]^4'hf; end 8'h47: begin outr <= outr^index[8:5]^4'h6; end 8'h48: begin outr <= outr^index[8:5]^4'h7; end 8'h49: begin outr <= outr^index[8:5]^4'h4; end 8'h4a: begin outr <= outr^index[8:5]^4'ha; end 8'h4b: begin outr <= outr^index[8:5]^4'hd; end 8'h4c: begin outr <= outr^index[8:5]^4'hb; end 8'h4d: begin outr <= outr^index[8:5]^4'hf; end 8'h4e: begin outr <= outr^index[8:5]^4'hd; end 8'h4f: begin outr <= outr^index[8:5]^4'h7; end 8'h50: begin outr <= outr^index[8:5]^4'h9; end 8'h51: begin outr <= outr^index[8:5]^4'ha; end 8'h52: begin outr <= outr^index[8:5]^4'hf; end 8'h53: begin outr <= outr^index[8:5]^4'h3; end 8'h54: begin outr <= outr^index[8:5]^4'h1; end 8'h55: begin outr <= outr^index[8:5]^4'h0; end 8'h56: begin outr <= outr^index[8:5]^4'h2; end 8'h57: begin outr <= outr^index[8:5]^4'h9; end 8'h58: begin outr <= outr^index[8:5]^4'h2; end 8'h59: begin outr <= outr^index[8:5]^4'h4; end 8'h5a: begin outr <= outr^index[8:5]^4'hc; end 8'h5b: begin outr <= outr^index[8:5]^4'hd; end 8'h5c: begin outr <= outr^index[8:5]^4'h3; end 8'h5d: begin outr <= outr^index[8:5]^4'hb; end 8'h5e: begin outr <= outr^index[8:5]^4'hd; end 8'h5f: begin outr <= outr^index[8:5]^4'h7; end 8'h60: begin outr <= outr^index[8:5]^4'h7; end 8'h61: begin outr <= outr^index[8:5]^4'h3; end 8'h62: begin outr <= outr^index[8:5]^4'h3; end 8'h63: begin outr <= outr^index[8:5]^4'hb; end 8'h64: begin outr <= outr^index[8:5]^4'h9; end 8'h65: begin outr <= outr^index[8:5]^4'h4; end 8'h66: begin outr <= outr^index[8:5]^4'h3; end 8'h67: begin outr <= outr^index[8:5]^4'h6; end 8'h68: begin outr <= outr^index[8:5]^4'h7; end 8'h69: begin outr <= outr^index[8:5]^4'h7; end 8'h6a: begin outr <= outr^index[8:5]^4'hf; end 8'h6b: begin outr <= outr^index[8:5]^4'h6; end 8'h6c: begin outr <= outr^index[8:5]^4'h8; end 8'h6d: begin outr <= outr^index[8:5]^4'he; end 8'h6e: begin outr <= outr^index[8:5]^4'h4; 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end 8'hc7: begin outr <= outr^index[8:5]^4'h6; end 8'hc8: begin outr <= outr^index[8:5]^4'ha; end 8'hc9: begin outr <= outr^index[8:5]^4'hf; end 8'hca: begin outr <= outr^index[8:5]^4'h3; end 8'hcb: begin outr <= outr^index[8:5]^4'hb; end 8'hcc: begin outr <= outr^index[8:5]^4'he; end 8'hcd: begin outr <= outr^index[8:5]^4'h2; end 8'hce: begin outr <= outr^index[8:5]^4'h5; end 8'hcf: begin outr <= outr^index[8:5]^4'hf; end 8'hd0: begin outr <= outr^index[8:5]^4'h2; end 8'hd1: begin outr <= outr^index[8:5]^4'h9; end 8'hd2: begin outr <= outr^index[8:5]^4'hb; end 8'hd3: begin outr <= outr^index[8:5]^4'h8; end 8'hd4: begin outr <= outr^index[8:5]^4'h0; end 8'hd5: begin outr <= outr^index[8:5]^4'h2; end 8'hd6: begin outr <= outr^index[8:5]^4'hb; end 8'hd7: begin outr <= outr^index[8:5]^4'h2; end 8'hd8: begin outr <= outr^index[8:5]^4'ha; end 8'hd9: begin outr <= outr^index[8:5]^4'hf; end 8'hda: begin outr <= outr^index[8:5]^4'h8; end 8'hdb: begin outr <= outr^index[8:5]^4'h4; end 8'hdc: begin outr <= outr^index[8:5]^4'he; end 8'hdd: begin outr <= outr^index[8:5]^4'h6; end 8'hde: begin outr <= outr^index[8:5]^4'h9; end 8'hdf: begin outr <= outr^index[8:5]^4'h9; end 8'he0: begin outr <= outr^index[8:5]^4'h7; end 8'he1: begin outr <= outr^index[8:5]^4'h0; end 8'he2: begin outr <= outr^index[8:5]^4'h9; end 8'he3: begin outr <= outr^index[8:5]^4'h3; end 8'he4: begin outr <= outr^index[8:5]^4'h2; end 8'he5: begin outr <= outr^index[8:5]^4'h4; end 8'he6: begin outr <= outr^index[8:5]^4'h5; end 8'he7: begin outr <= outr^index[8:5]^4'h5; end 8'he8: begin outr <= outr^index[8:5]^4'hf; end 8'he9: begin outr <= outr^index[8:5]^4'ha; end 8'hea: begin outr <= outr^index[8:5]^4'hc; end 8'heb: begin outr <= outr^index[8:5]^4'hd; end 8'hec: begin outr <= outr^index[8:5]^4'h1; end 8'hed: begin outr <= outr^index[8:5]^4'h5; end 8'hee: begin outr <= outr^index[8:5]^4'h9; end 8'hef: begin outr <= outr^index[8:5]^4'h0; end 8'hf0: begin outr <= outr^index[8:5]^4'hd; end 8'hf1: begin outr <= outr^index[8:5]^4'hf; end 8'hf2: begin outr <= outr^index[8:5]^4'h4; end 8'hf3: begin outr <= outr^index[8:5]^4'ha; end 8'hf4: begin outr <= outr^index[8:5]^4'h8; end 8'hf5: begin outr <= outr^index[8:5]^4'he; end 8'hf6: begin outr <= outr^index[8:5]^4'he; end 8'hf7: begin outr <= outr^index[8:5]^4'h1; end 8'hf8: begin outr <= outr^index[8:5]^4'h6; end 8'hf9: begin outr <= outr^index[8:5]^4'h0; end 8'hfa: begin outr <= outr^index[8:5]^4'h5; end 8'hfb: begin outr <= outr^index[8:5]^4'h1; end 8'hfc: begin outr <= outr^index[8:5]^4'h8; end 8'hfd: begin outr <= outr^index[8:5]^4'h6; end 8'hfe: begin outr <= outr^index[8:5]^4'h1; end default: begin outr <= outr^index[8:5]^4'h6; end endcase end endmodule verilator-4.038/test_regress/t/t_func_regfirst.pl0000775000177100017500000000105313702133370022211 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_countbits_bad.out0000775000177100017500000000040513702133370023376 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_math_countbits_bad.v:14:54: Unsupported: $countbits with more than 3 control fields 14 | assign count = $countbits(32'h123456, '0, '1, 'x, 'z); | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_unused_iface_bad.out0000664000177100017500000000105713702133370024034 0ustar wsnyderwsnyder%Warning-UNDRIVEN: t/t_lint_unused_iface_bad.v:8:10: Signal is not driven: 'sig_udrv' : ... In instance t.sub 8 | logic sig_udrv; | ^~~~~~~~ ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_lint_unused_iface_bad.v:9:10: Signal is not used: 'sig_uusd' : ... In instance t.sub 9 | logic sig_uusd; | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_initial_inc.vh0000664000177100017500000000053113702133370021632 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define foo bar `ifdef foo `ifdef baz `else // Test file to make sure includes work; integer user_loaded_value; `endif `endif verilator-4.038/test_regress/t/t_dpi_dup_bad.pl0000775000177100017500000000111313702133370021600 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_parameter_hier.v0000664000177100017500000000304513702133370023163 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; u u (); tx x (); parameter PARAM = 0; parameter HIER = 0; initial begin $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG `check(PARAM, 0); `elsif NC `check(PARAM, 0); `elsif VCS `check(PARAM, 10); `else `check(PARAM, 10); `endif `check(HIER, 0); end always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module u; ux x(); endmodule module ux; parameter PARAM = 0; parameter HIER = 0; initial begin $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG `check(PARAM, 0); `elsif NC `check(PARAM, 0); `elsif VCS `check(PARAM, 10); `else `check(PARAM, 0); `endif `check(HIER, 0); end endmodule module tx; parameter PARAM = 0; parameter HIER = 0; initial begin $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG `check(PARAM, 0); `elsif NC `check(PARAM, 10); `elsif VCS `check(PARAM, 10); `else `check(PARAM, 0); `endif `ifdef NC `check(HIER, 20); `else `check(HIER, 0); `endif end endmodule verilator-4.038/test_regress/t/t_fork_bbox.pl0000775000177100017500000000105613702133370021327 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ['--lint-only --bbox-unsup'], ); ok(1); 1; verilator-4.038/test_regress/t/t_select_bad_tri.pl0000775000177100017500000000111313702133370022311 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_public_func.cpp0000664000177100017500000000234513702133370023171 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include VM_PREFIX_INCLUDE #ifdef T_TRACE_PUBLIC_FUNC_VLT # include "Vt_trace_public_func_vlt_t.h" # include "Vt_trace_public_func_vlt_glbl.h" #else # include "Vt_trace_public_func_t.h" # include "Vt_trace_public_func_glbl.h" #endif unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const unsigned long long dt_2 = 3; int main(int argc, char** argv, char** env) { VM_PREFIX* top = new VM_PREFIX("top"); Verilated::debug(0); Verilated::traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; top->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); while (main_time <= 20) { top->CLK = (main_time / dt_2) % 2; top->eval(); top->t->glbl->setGSR(main_time < 7); tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); printf("*-* All Finished *-*\n"); return 0; } verilator-4.038/test_regress/t/t_typedef_port.pl0000775000177100017500000000105313702133370022055 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_fork_bbox.v0000664000177100017500000000062513702133370021157 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); initial begin fork : fblk begin $write("*-* All Finished *-*\n"); $finish; end join : fblk end endmodule verilator-4.038/test_regress/t/t_lint_implicit_port.v0000664000177100017500000000115113702133370023103 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic oe; read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) ); sets s (.clk(clk), .enable(implicit_write)); read u (.clk(clk), .data(~implicit_also)); endmodule module sets ( input clk, output enable ); assign enable = 1'b0; endmodule module read ( input clk, input data ); endmodule verilator-4.038/test_regress/t/t_array_mda.pl0000775000177100017500000000105313702133367021316 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mailbox.out0000664000177100017500000000017213702133370021176 0ustar wsnyderwsnyder%Error: t/t_mailbox.v:20:4: Can't find typedef: 'mailbox' 20 | mailbox m; | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface1_modport_nansi.pl0000775000177100017500000000117613702133370024334 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface1_modport.v"); compile( v_flags2 => ['+define+NANSI'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_redef.v0000664000177100017500000000113313702133370021277 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 function automatic integer min(input integer a, input integer b); return (a < b) ? a : b; endfunction module t #(parameter A=16, parameter B=8) (/*AUTOARG*/ // Outputs c, // Inputs a, b ); input [A-1:0] a; input [B-1:0] b; output logic [min(A,B)-1:0] c; always_comb for (int i = 0; i < min(A,B); i++) assign c[i] = a[i] | b[i]; endmodule verilator-4.038/test_regress/t/t_mem_slot.cpp0000664000177100017500000000265713702133370021347 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include "Vt_mem_slot.h" unsigned int Array[3]; unsigned int StepSim(Vt_mem_slot* sim, unsigned int slot, unsigned int bit, unsigned int val, unsigned int rslot) { #ifdef TEST_VERBOSE printf("StepSim: slot=%u bit=%u val=%u rslot=%u\n", slot, bit, val, rslot); #endif sim->SlotIdx = slot; sim->BitToChange = bit; sim->BitVal = val; sim->SlotToReturn = rslot; sim->Clk = 0; sim->eval(); sim->Clk = 1; sim->eval(); if (sim->OutputVal != Array[rslot]) { printf("%%Error: got %x - expected %x\n", sim->OutputVal, Array[rslot]); exit(1); } if (val) Array[slot] |= (1 << bit); else Array[slot] &= ~(1 << bit); return sim->OutputVal; } int main(int argc, char* argv[]) { Vt_mem_slot* sim = new Vt_mem_slot; int slot, bit, i; Verilated::debug(0); /* clear all bits in the array */ for (slot = 0; slot < 3; slot++) for (bit = 0; bit < 2; bit++) StepSim(sim, slot, bit, 0, 0); printf("\nTesting\n"); for (i = 0; i < 100; i++) StepSim(sim, random() % 3, random() % 2, random() % 2, random() % 3); printf("*-* All Finished *-*\n"); } verilator-4.038/test_regress/t/t_struct_packed_sysfunct.v0000664000177100017500000000306713702133370024000 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // packed structures struct packed { logic e0; logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; } struct_bg; // big endian structure /* verilator lint_off LITENDIAN */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; } struct_lt; // little endian structure /* verilator lint_on LITENDIAN */ integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if (cnt==2) begin $write("*-* All Finished *-*\n"); $finish; end always @ (posedge clk) if (cnt==1) begin // big endian if ($bits (struct_bg ) != 15) $stop; if ($bits (struct_bg.e0) != 1) $stop; if ($bits (struct_bg.e1) != 2) $stop; if ($bits (struct_bg.e2) != 4) $stop; if ($bits (struct_bg.e3) != 8) $stop; if ($increment (struct_bg, 1) != 1) $stop; // little endian if ($bits (struct_lt ) != 15) $stop; if ($bits (struct_lt.e0) != 1) $stop; if ($bits (struct_lt.e1) != 2) $stop; if ($bits (struct_lt.e2) != 4) $stop; if ($bits (struct_lt.e3) != 8) $stop; if ($increment (struct_lt, 1) != 1) $stop; // Structure itself always big numbered end endmodule verilator-4.038/test_regress/t/t_unpacked_array_order.v0000664000177100017500000000160313702133370023364 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Duraid Madina. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter logic [1:0] t0 [ 2][ 2] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; parameter logic [1:0] t1 [0:1][0:1] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; parameter logic [1:0] t2 [1:0][1:0] = '{'{2'd3, 2'd2}, '{2'd1, 2'd0}}; always @ (posedge clk) begin if (t0[0][0] != t1[0][0]) $stop; if (t0[0][1] != t1[0][1]) $stop; if (t0[1][0] != t1[1][0]) $stop; if (t0[1][1] != t1[1][1]) $stop; if (t0[0][0] != t2[0][0]) $stop; if (t0[0][1] != t2[0][1]) $stop; if (t0[1][0] != t2[1][0]) $stop; if (t0[1][1] != t2[1][1]) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_flag_relinc.v0000664000177100017500000000060713702133370021451 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; t_flag_relinc_sub sub (); endmodule verilator-4.038/test_regress/t/t_preproc_inc_bad.pl0000775000177100017500000000115313702133370022463 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, # The .vh file has the error, not the .v file expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_qw_c.cpp0000664000177100017500000000227313702133370021307 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include #include #include "svdpi.h" //====================================================================== #include "Vt_dpi_qw__Dpi.h" //====================================================================== // Called from our Verilog code to run the tests void poke_value(int i) { printf("poke_value(%d)\n", i); #ifdef VERILATOR static int didDump = 0; if (didDump++ == 0) { # ifdef TEST_VERBOSE Verilated::scopesDump(); # endif } #endif svScope scope = svGetScopeFromName("top.t.a"); if (scope == NULL) { printf("%%Error: null scope for top.t.a\n"); return; } svSetScope(scope); svBitVecVal val[2]; val[0] = i; val[1] = 0; set_value(val); } verilator-4.038/test_regress/t/t_wire_beh1364_bad.v0000664000177100017500000000145713702133370022120 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, oa, ro, roa, wo, woa ); wire w; reg r; output o; output [1:0] oa; output reg ro; output reg [1:0] roa; output wire wo; output wire [1:0] woa; //1800 only: //output var vo; //output var [1:0] voa; initial begin w = '0; // Error o = '0; // Error oa = '0; // Error wo = '0; // Error woa = '0; // Error r = '0; // Not an error ro = '0; // Not an error roa = '0; // Not an error //vo = '0; // Not an error //voa = '0; // Not an error end endmodule verilator-4.038/test_regress/t/t_class_method_bad.v0000664000177100017500000000064613702133367022470 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base1; task meth1; endtask endclass class Cls2 extends Base1; task meth2; endtask endclass module t (/*AUTOARG*/); initial begin Cls2 c; c.meth3(); // Not found end endmodule verilator-4.038/test_regress/t/t_pp_resetall_bad.out0000664000177100017500000000020513702133370022660 0ustar wsnyderwsnyder%Error: t/t_pp_resetall_bad.v:9:1: syntax error, unexpected `resetall 9 | `resetall | ^~~~~~~~~ %Error: Cannot continue verilator-4.038/test_regress/t/t_fuzz_eof_bad.v0000664000177100017500000000005713702133370021640 0ustar wsnyderwsnydermodule a; initial $lay(*Hello!=n"); endmodule verilator-4.038/test_regress/t/t_struct_packed_value_list.v0000664000177100017500000001200513702133370024261 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam NO = 7; // number of access events // packed structures struct packed { logic e0; logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; } struct_bg; // big endian structure /* verilator lint_off LITENDIAN */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; } struct_lt; // little endian structure /* verilator lint_on LITENDIAN */ localparam WS = 15; // $bits(struct_bg) integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin $write("*-* All Finished *-*\n"); $finish; end // big endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]==0) struct_bg <= '0; else if (cnt[30:2]==1) struct_bg <= '0; else if (cnt[30:2]==2) struct_bg <= '0; else if (cnt[30:2]==3) struct_bg <= '0; else if (cnt[30:2]==4) struct_bg <= '0; else if (cnt[30:2]==5) struct_bg <= '0; else if (cnt[30:2]==6) struct_bg <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) struct_bg <= '{0 ,1 , 2, 3}; else if (cnt[30:2]==2) struct_bg <= '{e0:1, e1:2, e2:3, e3:4}; else if (cnt[30:2]==3) struct_bg <= '{e3:6, e2:4, e1:2, e0:0}; // verilator lint_off WIDTH else if (cnt[30:2]==4) struct_bg <= '{default:13}; else if (cnt[30:2]==5) struct_bg <= '{e2:8'haa, default:1}; else if (cnt[30:2]==6) struct_bg <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; // verilator lint_on WIDTH end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]==0) begin if (struct_bg !== 15'b0_00_0000_00000000) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==1) begin if (struct_bg !== 15'b0_01_0010_00000011) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1_10_0011_00000100) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==3) begin if (struct_bg !== 15'b0_10_0100_00000110) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==4) begin if (struct_bg !== 15'b1_01_1101_00001101) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==5) begin if (struct_bg !== 15'b1_01_1010_00000001) begin $display("%b", struct_bg); $stop(); end end else if (cnt[30:2]==6) begin if (struct_bg !== 15'b1_10_1011_00011100) begin $display("%b", struct_bg); $stop(); end end end // little endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]==0) struct_lt <= '0; else if (cnt[30:2]==1) struct_lt <= '0; else if (cnt[30:2]==2) struct_lt <= '0; else if (cnt[30:2]==3) struct_lt <= '0; else if (cnt[30:2]==4) struct_lt <= '0; else if (cnt[30:2]==5) struct_lt <= '0; else if (cnt[30:2]==6) struct_lt <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) struct_lt <= '{0 ,1 , 2, 3}; else if (cnt[30:2]==2) struct_lt <= '{e0:1, e1:2, e2:3, e3:4}; else if (cnt[30:2]==3) struct_lt <= '{e3:6, e2:4, e1:2, e0:0}; // verilator lint_off WIDTH else if (cnt[30:2]==4) struct_lt <= '{default:13}; else if (cnt[30:2]==5) struct_lt <= '{e2:8'haa, default:1}; else if (cnt[30:2]==6) struct_lt <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; // verilator lint_on WIDTH end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]==0) begin if (struct_lt !== 15'b0_00_0000_00000000) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==1) begin if (struct_lt !== 15'b0_01_0010_00000011) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1_10_0011_00000100) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==3) begin if (struct_lt !== 15'b0_10_0100_00000110) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==4) begin if (struct_lt !== 15'b1_01_1101_00001101) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==5) begin if (struct_lt !== 15'b1_01_1010_00000001) begin $display("%b", struct_lt); $stop(); end end else if (cnt[30:2]==6) begin if (struct_lt !== 15'b1_10_1011_00011100) begin $display("%b", struct_lt); $stop(); end end end endmodule verilator-4.038/test_regress/t/t_flag_quiet_exit.pl0000775000177100017500000000147113702133370022526 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_file_does_not_exist.v"); # Tests for the error message and then the absence of the # "Command Failed" line compile( v_flags2 => ["--quiet-exit"], fails => 1, ); file_grep_not("$Self->{obj_dir}/vlt_compile.log", qr/Exiting due to/); file_grep_not("$Self->{obj_dir}/vlt_compile.log", qr/Command Failed/); ok(1); 1; verilator-4.038/test_regress/t/t_interface_down_inla.pl0000775000177100017500000000123413702133370023344 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_A'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_dangle.v0000664000177100017500000000112513702133370021310 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inouts AVDD, AVSS ); inout AVDD; inout AVSS; sub sub (/*AUTOINST*/ // Inouts .AVDD (AVDD), .AVSS (AVSS)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (/*AUTOARG*/ // Inouts AVDD, AVSS ); // verilator no_inline_module inout AVDD; inout AVSS; endmodule verilator-4.038/test_regress/t/t_math_red.pl0000775000177100017500000000105313702133370021134 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_sc.pl0000775000177100017500000000130513702133370020634 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( # Must not make shell/main or hides bug make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe --vpi --sc $Self->{t_dir}/t_vpi_sc.cpp"], ); execute( check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_math_clog2.v0000664000177100017500000000522513702133370021224 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef verilator `define CLOG2 $clog2 `else `define CLOG2 clog2_emulate `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Need temp wires as function has different width rules than $clog2 wire [127:0] pows = 128'h1<> 1); end endfunction endmodule verilator-4.038/test_regress/t/t_altera_lpm_decode.pl0000775000177100017500000000120613702133367023002 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_inc_recurse_bad.out0000664000177100017500000000033413702133370024404 0ustar wsnyderwsnyder%Error: t/t_preproc_inc_recurse_bad.v:7:10: Recursive inclusion of file: t/t_preproc_inc_recurse_bad.v 7 | `include "t_preproc_inc_recurse_bad.v" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_math_countbits_bad.v0000664000177100017500000000054613702133370023037 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Yossi Nivin. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer count; assign count = $countbits(32'h123456, '0, '1, 'x, 'z); endmodule verilator-4.038/test_regress/t/t_for_break.v0000664000177100017500000000725413702133370021143 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] l_stop = crc[3:0]; wire [3:0] l_break = crc[7:4]; wire [3:0] l_continue = crc[11:8]; /*AUTOWIRE*/ wire [15:0] out0 = Test0(l_stop, l_break, l_continue); wire [15:0] out1 = Test1(l_stop, l_break, l_continue); wire [15:0] out2 = Test2(l_stop, l_break, l_continue); wire [15:0] out3 = Test3(l_stop, l_break, l_continue); // Aggregate outputs into a single result vector wire [63:0] result = {out3,out2,out1,out0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin if (out0!==out1) $stop; if (out0!==out2) $stop; if (out0!==out3) $stop; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h293e9f9798e97da0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end function [15:0] Test0; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; reg broken; Test0 = 0; broken = 0; begin for (i=1; i<20; i=i+1) begin if (!broken) begin Test0 = Test0 + 1; if (i[3:0] != loop_continue) begin // continue if (i[3:0] == loop_break) begin broken = 1'b1; end if (!broken) begin Test0 = Test0 + i[15:0]; end end end end end endfunction function [15:0] Test1; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; Test1 = 0; begin : outer_block for (i=1; i<20; i=i+1) begin : inner_block Test1 = Test1 + 1; // continue, IE jump to end-of-inner_block. Must be inside inner_block. if (i[3:0] == loop_continue) disable inner_block; // break, IE jump to end-of-outer_block. Must be inside outer_block. if (i[3:0] == loop_break) disable outer_block; Test1 = Test1 + i[15:0]; end : inner_block end : outer_block endfunction function [15:0] Test2; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; Test2 = 0; begin for (i=1; i<20; i=i+1) begin Test2 = Test2 + 1; if (i[3:0] == loop_continue) continue; if (i[3:0] == loop_break) break; Test2 = Test2 + i[15:0]; end end endfunction function [15:0] Test3; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; Test3 = 0; begin for (i=1; i<20; i=i+1) begin Test3 = Test3 + 1; if (i[3:0] == loop_continue) continue; // return, IE jump to end-of-function optionally setting return value if (i[3:0] == loop_break) return Test3; Test3 = Test3 + i[15:0]; end end endfunction endmodule verilator-4.038/test_regress/t/t_clk_inp_init.pl0000775000177100017500000000117413702133367022025 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2018 by Argon Design. This program is free software; you # can redistribute it and/or modify it under the terms of either the # GNU Lesser General Public License Version 3 or the Perl Artistic # License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile(make_main => 0, verilator_flags2 => ["-CFLAGS -g3 --exe $Self->{t_dir}/$Self->{name}.cpp"]); execute(check_finished => 1); ok(1); 1; verilator-4.038/test_regress/t/t_cover_line_cc_vlt.pl0000775000177100017500000000177313702133367023047 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_cover_line.v"); compile( verilator_flags2 => ['--cc', '--coverage-line', "t/t_cover_line.vlt"], ); execute( check_finished => 1, ); # Read the input .v file and do any CHECK_COVER requests inline_checks(); run(cmd => ["../bin/verilator_coverage", "--annotate", "$Self->{obj_dir}/annotated", "$Self->{obj_dir}/coverage.dat", ], verilator_run => 1, ); files_identical("$Self->{obj_dir}/annotated/t_cover_line.v", "t/t_cover_line.out"); ok(1); 1; verilator-4.038/test_regress/t/t_struct_portsel.v0000664000177100017500000000433713702133370022304 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [19:0] in = crc[19:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [19:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[19:0]), // Inputs .in (in[19:0])); // Aggregate outputs into a single result vector wire [63:0] result = {44'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hdb7bc61592f31b99 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule typedef struct packed { logic [7:0] cn; logic vbfval; logic vabval; } rel_t; module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [19:0] in; output [19:0] out; rel_t [1:0] i; // From ifb0 of ifb.v, ... rel_t [1:0] o; // From ifb0 of ifb.v, ... assign i = in; assign out = o; sub sub ( .i (i[1:0]), .o (o[1:0])); endmodule module sub (/*AUTOARG*/ // Outputs o, // Inputs i ); input rel_t [1:0] i; output rel_t [1:0] o; assign o = i; endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-4.038/test_regress/t/t_gen_defparam_unsup_bad.pl0000775000177100017500000000107113702133370024021 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_first_deprecated.pl0000775000177100017500000000106413702133367023521 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only", "-Wno-DEPRECATED"], ); ok(1); 1; verilator-4.038/test_regress/t/t_var_set_link.pl0000775000177100017500000000105313702133370022031 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_ifdef.pl0000775000177100017500000000105313702133370022160 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_copy.v0000664000177100017500000000156713702133367021357 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int imembera; function int inc_methoda; imembera += 1; return imembera; endfunction endclass module t (/*AUTOARG*/); initial begin Cls c1; Cls c2; Cls c3; c1 = new; c1.imembera = 10; if (c1.inc_methoda() != 11) $stop; // Assignment c2 = c1; if (c1.inc_methoda() != 12) $stop; if (c2.inc_methoda() != 13) $stop; if (c1.inc_methoda() != 14) $stop; // Shallow copy c3 = new c1; if (c1.inc_methoda() != 15) $stop; if (c3.inc_methoda() != 15) $stop; if (c1.inc_methoda() != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_div.pl0000775000177100017500000000105313702133370021144 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_fifo.v0000664000177100017500000000536213702133370020770 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; wire [65:0] outData; // From fifo of fifo.v wire [15:0] inData = crc[15:0]; wire [1:0] inWordPtr = crc[17:16]; wire wrEn = crc[20]; wire [1:0] wrPtr = crc[33:32]; wire [1:0] rdPtr = crc[34:33]; fifo fifo ( // Outputs .outData (outData[65:0]), // Inputs .clk (clk), .inWordPtr (inWordPtr[1:0]), .inData (inData[15:0]), .rdPtr (rdPtr), .wrPtr (wrPtr), .wrEn (wrEn)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData); cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc==90) begin if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop; end else if (cyc==91) begin if (outData[63:0] != 64'hef77cd9b13a866f0) $stop; end else if (cyc==92) begin if (outData[63:0] != 64'h2750cd9b13a866f0) $stop; end else if (cyc==93) begin if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop; end else if (cyc==94) begin if (outData[63:0] != 64'h9d41bc276f0984ea) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module fifo (/*AUTOARG*/ // Outputs outData, // Inputs clk, inWordPtr, inData, wrPtr, rdPtr, wrEn ); parameter fifoDepthLog2 = 1; parameter fifoDepth = 1< 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_parameter.v0000664000177100017500000000617613702133370022164 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // Special cases of "string parameters" : // This table compares obtain results from big-3 simulators to Verilator // expected behavior. Base specified integer literals are also included as // string detection may impact results for such cases. // // | Option/Param file | simulator 1 | simulator 2 | simulator 3 | verilator | // |---------------------|-------------|-------------|-------------|-------------| // | -gC0='"AB CD"' | AB CD | UNSUPPORTED | AB CD | AB CD | // | -gC1=\"AB\ CD\" | AB CD | UNSUPPORTED | UNSUPPORTED | AB CD | // | -gC2="\"AB CD\"" | AB CD | AB CD | AB CD | AB CD | // | -gC3="\"AB\ CD\"" | AB CD | AB\\ CD | AB CD | AB CD | // | -gC4=32'h600D600D | UNSUPPORTED | 32'h600D600D| 32'h600D600D| 32'h600D600D| // | -gC5=32\'h600D600D | 32'h600D600D| UNSUPPORTED | UNSUPPORTED | 32'h600D600D| // | -gC6="32'h600D600D" | 32'h600D600D| 32'h600D600D| UNSUPPORTED | 32'h600D600D| // | -gC7='AB CD' | AB CD | UNSUPPORTED | UNSUPPORTED | UNSUPPORTED | `define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); $stop; end while(0); module t; parameter string1 = "Original String"; parameter string2 = "Original String"; parameter string11 = "Original String"; parameter string12 = "Original String"; parameter string21 = "Original String"; parameter string22 = "Original String"; parameter real11 = 0.1; parameter real12 = 0.1; parameter real21 = 0.1; parameter real22 = 0.1; parameter real31 = 0.1; parameter real32 = 0.1; parameter real41 = 0.1; parameter real42 = 0.1; parameter real51 = 0.1; parameter real52 = 0.1; parameter int11 = 1; parameter int12 = 1; parameter int21 = 1; parameter int22 = 1; parameter int31 = 1; parameter int32 = 1; parameter int41 = 1; parameter int42 = 1; parameter int51 = 1; parameter int52 = 1; parameter int61 = 1; parameter int62 = 1; initial begin `check(string1,"New String"); `check(string2,"New String"); `check(string11,"New String"); `check(string12,"New String"); `check(string21,"New String"); `check(string22,"New String"); `check(real11,0.2); `check(real12,0.2); `check(real21,400); `check(real22,400); `check(real31,20); `check(real32,20); `check(real41,582.5); `check(real42,582.5); `check(real51,145.5); `check(real52,145.5); `check(int11,16); `check(int12,16); `check(int21,16); `check(int22,16); `check(int31,123); `check(int32,123); `check(int41,32'hdeadbeef); `check(int42,32'hdeadbeef); `check(int51,32'hdeadbeef); `check(int52,32'hdeadbeef); `check(int61,32'hdeadbeef); `check(int62,32'hdeadbeef); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_dpi_arg_inout_type.v0000664000177100017500000012664313702133370023101 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `define NO_INTEGER `define NO_SHORTREAL `endif `ifdef MS `endif `ifdef VERILATOR `define NO_SHORTREAL `define NULL 64'd0 `else `define NULL null `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef VERILATOR wire _unused = &{1'b0, clk}; `endif // Legal inout argument types for DPI functions //====================================================================== // Type definitions //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 typedef byte byte_t; typedef byte unsigned byte_unsigned_t; typedef shortint shortint_t; typedef shortint unsigned shortint_unsigned_t; typedef int int_t; typedef int unsigned int_unsigned_t; typedef longint longint_t; typedef longint unsigned longint_unsigned_t; `ifndef NO_TIME typedef time time_t; `endif `ifndef NO_INTEGER typedef integer integer_t; `endif typedef real real_t; `ifndef NO_SHORTREAL typedef shortreal shortreal_t; `endif typedef chandle chandle_t; typedef string string_t; typedef bit bit_t; typedef logic logic_t; // 2-state packed structures typedef struct packed { bit x; } struct_2_state_1; typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; // 2-state packed unions typedef union packed { bit x; bit y; } union_2_state_1; typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; // 4-state packed structures typedef struct packed { logic x; } struct_4_state_1; typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; // 4-state packed unions typedef union packed { logic x; bit y; } union_4_state_1; typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; //====================================================================== // Imports //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 import "DPI-C" function void i_byte (inout byte x); import "DPI-C" function void i_byte_unsigned (inout byte unsigned x); import "DPI-C" function void i_shortint (inout shortint x); import "DPI-C" function void i_shortint_unsigned (inout shortint unsigned x); import "DPI-C" function void i_int (inout int x); import "DPI-C" function void i_int_unsigned (inout int unsigned x); import "DPI-C" function void i_longint (inout longint x); import "DPI-C" function void i_longint_unsigned (inout longint unsigned x); `ifndef NO_TIME import "DPI-C" function void i_time (inout time x); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer (inout integer x); `endif import "DPI-C" function void i_real (inout real x); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal (inout shortreal x); `endif import "DPI-C" function void i_chandle (inout chandle x); import "DPI-C" function void i_string (inout string x); import "DPI-C" function void i_bit (inout bit x); import "DPI-C" function void i_logic (inout logic x); // Basic types via typedef import "DPI-C" function void i_byte_t (inout byte_t x); import "DPI-C" function void i_byte_unsigned_t (inout byte_unsigned_t x); import "DPI-C" function void i_shortint_t (inout shortint_t x); import "DPI-C" function void i_shortint_unsigned_t (inout shortint_unsigned_t x); import "DPI-C" function void i_int_t (inout int_t x); import "DPI-C" function void i_int_unsigned_t (inout int_unsigned_t x); import "DPI-C" function void i_longint_t (inout longint_t x); import "DPI-C" function void i_longint_unsigned_t (inout longint_unsigned_t x); `ifndef NO_TIME import "DPI-C" function void i_time_t (inout time_t x); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer_t (inout integer_t x); `endif import "DPI-C" function void i_real_t (inout real_t x); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal_t (inout shortreal_t x); `endif import "DPI-C" function void i_chandle_t (inout chandle_t x); import "DPI-C" function void i_string_t (inout string_t x); import "DPI-C" function void i_bit_t (inout bit_t x); import "DPI-C" function void i_logic_t (inout logic_t x); // 2-state packed arrays import "DPI-C" function void i_array_2_state_1 (inout bit [ 0:0] x); import "DPI-C" function void i_array_2_state_32 (inout bit [ 31:0] x); import "DPI-C" function void i_array_2_state_33 (inout bit [ 32:0] x); import "DPI-C" function void i_array_2_state_64 (inout bit [ 63:0] x); import "DPI-C" function void i_array_2_state_65 (inout bit [ 64:0] x); import "DPI-C" function void i_array_2_state_128(inout bit [127:0] x); // 2-state packed structures import "DPI-C" function void i_struct_2_state_1 (inout struct_2_state_1 x); import "DPI-C" function void i_struct_2_state_32 (inout struct_2_state_32 x); import "DPI-C" function void i_struct_2_state_33 (inout struct_2_state_33 x); import "DPI-C" function void i_struct_2_state_64 (inout struct_2_state_64 x); import "DPI-C" function void i_struct_2_state_65 (inout struct_2_state_65 x); import "DPI-C" function void i_struct_2_state_128 (inout struct_2_state_128 x); // 2-state packed unions import "DPI-C" function void i_union_2_state_1 (inout union_2_state_1 x); import "DPI-C" function void i_union_2_state_32 (inout union_2_state_32 x); import "DPI-C" function void i_union_2_state_33 (inout union_2_state_33 x); import "DPI-C" function void i_union_2_state_64 (inout union_2_state_64 x); import "DPI-C" function void i_union_2_state_65 (inout union_2_state_65 x); import "DPI-C" function void i_union_2_state_128 (inout union_2_state_128 x); // 4-state packed arrays import "DPI-C" function void i_array_4_state_1 (inout logic [ 0:0] x); import "DPI-C" function void i_array_4_state_32 (inout logic [ 31:0] x); import "DPI-C" function void i_array_4_state_33 (inout logic [ 32:0] x); import "DPI-C" function void i_array_4_state_64 (inout logic [ 63:0] x); import "DPI-C" function void i_array_4_state_65 (inout logic [ 64:0] x); import "DPI-C" function void i_array_4_state_128(inout logic [127:0] x); // 4-state packed structures import "DPI-C" function void i_struct_4_state_1 (inout struct_4_state_1 x); import "DPI-C" function void i_struct_4_state_32 (inout struct_4_state_32 x); import "DPI-C" function void i_struct_4_state_33 (inout struct_4_state_33 x); import "DPI-C" function void i_struct_4_state_64 (inout struct_4_state_64 x); import "DPI-C" function void i_struct_4_state_65 (inout struct_4_state_65 x); import "DPI-C" function void i_struct_4_state_128 (inout struct_4_state_128 x); // 4-state packed unions import "DPI-C" function void i_union_4_state_1 (inout union_4_state_1 x); import "DPI-C" function void i_union_4_state_32 (inout union_4_state_32 x); import "DPI-C" function void i_union_4_state_33 (inout union_4_state_33 x); import "DPI-C" function void i_union_4_state_64 (inout union_4_state_64 x); import "DPI-C" function void i_union_4_state_65 (inout union_4_state_65 x); import "DPI-C" function void i_union_4_state_128 (inout union_4_state_128 x); //====================================================================== // Exports //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 export "DPI-C" function e_byte; export "DPI-C" function e_byte_unsigned; export "DPI-C" function e_shortint; export "DPI-C" function e_shortint_unsigned; export "DPI-C" function e_int; export "DPI-C" function e_int_unsigned; export "DPI-C" function e_longint; export "DPI-C" function e_longint_unsigned; `ifndef NO_TIME export "DPI-C" function e_time; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer; `endif export "DPI-C" function e_real; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal; `endif export "DPI-C" function e_chandle; export "DPI-C" function e_string; export "DPI-C" function e_bit; export "DPI-C" function e_logic; // Basic types via typedef export "DPI-C" function e_byte_t; export "DPI-C" function e_byte_unsigned_t; export "DPI-C" function e_shortint_t; export "DPI-C" function e_shortint_unsigned_t; export "DPI-C" function e_int_t; export "DPI-C" function e_int_unsigned_t; export "DPI-C" function e_longint_t; export "DPI-C" function e_longint_unsigned_t; `ifndef NO_TIME export "DPI-C" function e_time_t; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer_t; `endif export "DPI-C" function e_real_t; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_t; `endif export "DPI-C" function e_chandle_t; export "DPI-C" function e_string_t; export "DPI-C" function e_bit_t; export "DPI-C" function e_logic_t; // 2-state packed arrays export "DPI-C" function e_array_2_state_1; export "DPI-C" function e_array_2_state_32; export "DPI-C" function e_array_2_state_33; export "DPI-C" function e_array_2_state_64; export "DPI-C" function e_array_2_state_65; export "DPI-C" function e_array_2_state_128; // 2-state packed structures export "DPI-C" function e_struct_2_state_1; export "DPI-C" function e_struct_2_state_32; export "DPI-C" function e_struct_2_state_33; export "DPI-C" function e_struct_2_state_64; export "DPI-C" function e_struct_2_state_65; export "DPI-C" function e_struct_2_state_128; // 2-state packed unions export "DPI-C" function e_union_2_state_1; export "DPI-C" function e_union_2_state_32; export "DPI-C" function e_union_2_state_33; export "DPI-C" function e_union_2_state_64; export "DPI-C" function e_union_2_state_65; export "DPI-C" function e_union_2_state_128; // 4-state packed arrays export "DPI-C" function e_array_4_state_1; export "DPI-C" function e_array_4_state_32; export "DPI-C" function e_array_4_state_33; export "DPI-C" function e_array_4_state_64; export "DPI-C" function e_array_4_state_65; export "DPI-C" function e_array_4_state_128; // 4-state packed structures export "DPI-C" function e_struct_4_state_1; export "DPI-C" function e_struct_4_state_32; export "DPI-C" function e_struct_4_state_33; export "DPI-C" function e_struct_4_state_64; export "DPI-C" function e_struct_4_state_65; export "DPI-C" function e_struct_4_state_128; // 4-state packed unions export "DPI-C" function e_union_4_state_1; export "DPI-C" function e_union_4_state_32; export "DPI-C" function e_union_4_state_33; export "DPI-C" function e_union_4_state_64; export "DPI-C" function e_union_4_state_65; export "DPI-C" function e_union_4_state_128; //====================================================================== // Definitions of exported functions //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 byte n_byte = 0; function void e_byte(inout byte x); if (x !== 8'd10 + n_byte) $stop; x += 8'd100; n_byte++; endfunction byte n_byte_unsigned = 0; function void e_byte_unsigned(inout byte unsigned x); if (x !== 8'd20 + n_byte_unsigned) $stop; x += 8'd200; n_byte_unsigned++; endfunction shortint n_shortint = 0; function void e_shortint(inout shortint x); if (x !== 16'd30 + n_shortint) $stop; x += 16'd300; n_shortint++; endfunction shortint n_shortint_unsigned = 0; function void e_shortint_unsigned(inout shortint unsigned x); if (x !== 16'd40 + n_shortint_unsigned) $stop; x += 16'd400; n_shortint_unsigned++; endfunction int n_int = 0; function void e_int(inout int x); if (x !== 32'd50 + n_int) $stop; x += 32'd500; n_int++; endfunction int n_int_unsigned = 0; function void e_int_unsigned(inout int unsigned x); if (x !== 32'd60 + n_int_unsigned) $stop; x += 32'd600; n_int_unsigned++; endfunction longint n_longint = 0; function void e_longint(inout longint x); if (x !== 64'd70 + n_longint) $stop; x += 64'd700; n_longint++; endfunction longint n_longint_unsigned = 0; function void e_longint_unsigned(inout longint unsigned x); if (x !== 64'd80 + n_longint_unsigned) $stop; x += 64'd800; n_longint_unsigned++; endfunction `ifndef NO_TIME longint n_time = 0; function void e_time(inout time x); if (x !== 64'd90 + n_time) $stop; x += 64'd900; n_time++; endfunction `endif `ifndef NO_INTEGER int n_integer = 0; function void e_integer(inout integer x); if (x !== 32'd100 + n_integer) $stop; x += 32'd1000; n_integer++; endfunction `endif int n_real = 0; function void e_real(inout real x); if (x != real'(2*n_real + 1) / 2.0) $stop; x += 100.0; n_real++; endfunction `ifndef NO_SHORTREAL int n_shortreal = 0; function void e_shortreal(inout shortreal x); if (x != shortreal'(4*n_shortreal + 1)/ 4.0) $stop; x += 200.0; n_shortreal++; endfunction `endif int n_chandle = 0; function void e_chandle(inout chandle x); $display("e_chandle %1d", n_chandle); if (!n_chandle[0]) begin if (x === `NULL) $stop; end else begin if (x !== `NULL) $stop; end x = `NULL; n_chandle++; endfunction int n_string = 0; function void e_string(inout string x); $display("e_string %1d", n_string); if (!n_string[0]) begin if (x != "Good") $stop; x = "Hello"; end else begin if (x != "Bye") $stop; x = "World"; end n_string++; endfunction int n_bit = 0; function void e_bit(inout bit x); $display("e_bit %1d", n_bit); if (x !== n_bit[0]) $stop; x = ~x; n_bit++; endfunction int n_logic = 0; function void e_logic(inout logic x); $display("e_logic %1d", n_logic); if (x !== ~n_logic[0]) $stop; x = ~x; n_logic++; endfunction // Basic types via typedefs byte_t n_byte_t = 0; function void e_byte_t(inout byte_t x); if (x !== 8'd10 + n_byte_t) $stop; x += 8'd101; n_byte_t += 2; endfunction byte n_byte_unsigned_t = 0; function void e_byte_unsigned_t(inout byte_unsigned_t x); if (x !== 8'd20 + n_byte_unsigned_t) $stop; x += 8'd202; n_byte_unsigned_t += 2; endfunction shortint_t n_shortint_t = 0; function void e_shortint_t(inout shortint_t x); if (x !== 16'd30 + n_shortint_t) $stop; x += 16'd303; n_shortint_t += 2; endfunction shortint n_shortint_unsigned_t = 0; function void e_shortint_unsigned_t(inout shortint_unsigned_t x); if (x !== 16'd40 + n_shortint_unsigned_t) $stop; x += 16'd404; n_shortint_unsigned_t += 2; endfunction int_t n_int_t = 0; function void e_int_t(inout int_t x); if (x !== 32'd50 + n_int_t) $stop; x += 32'd505; n_int_t += 2; endfunction int n_int_unsigned_t = 0; function void e_int_unsigned_t(inout int_unsigned_t x); if (x !== 32'd60 + n_int_unsigned_t) $stop; x += 32'd606; n_int_unsigned_t += 2; endfunction longint_t n_longint_t = 0; function void e_longint_t(inout longint_t x); if (x !== 64'd70 + n_longint_t) $stop; x += 64'd707; n_longint_t += 2; endfunction longint n_longint_unsigned_t = 0; function void e_longint_unsigned_t(inout longint_unsigned_t x); if (x !== 64'd80 + n_longint_unsigned_t) $stop; x += 64'd808; n_longint_unsigned_t += 2; endfunction `ifndef NO_TIME longint n_time_t = 0; function void e_time_t(inout time_t x); if (x !== 64'd90 + n_time_t) $stop; x += 64'd909; n_time_t += 2; endfunction `endif `ifndef NO_INTEGER int n_integer_t = 0; function void e_integer_t(inout integer_t x); if (x !== 32'd100 + n_integer_t) $stop; x += 32'd1001; n_integer_t += 2; endfunction `endif int n_real_t = 0; function void e_real_t(inout real_t x); if (x != real'(2*n_real_t + 1) / 2.0) $stop; x += 111.0; n_real_t += 2; endfunction `ifndef NO_SHORTREAL int n_shortreal_t = 0; function void e_shortreal_t(inout shortreal_t x); if (x != shortreal'(4*n_shortreal_t + 1)/ 4.0) $stop; x += 222.0; n_shortreal_t += 2; endfunction `endif int n_chandle_t = 0; function void e_chandle_t(inout chandle_t x); $display("e_chandle_t %1d", n_chandle_t); if (!n_chandle_t[0]) begin if (x !== `NULL) $stop; end else begin if (x === `NULL) $stop; end x = `NULL; n_chandle_t++; endfunction int n_string_t = 0; function void e_string_t(inout string_t x); $display("e_string_t %1d", n_string_t); if (!n_string_t[0]) begin if (x != "Bye") $stop; x = "World"; end else begin if (x != "Good") $stop; x = "Hello"; end n_string_t++; endfunction int n_bit_t = 0; function void e_bit_t(inout bit_t x); $display("e_bit_t %1d", n_bit_t); if (x !== n_bit_t[0]) $stop; x = ~x; n_bit_t++; endfunction int n_logic_t = 0; function void e_logic_t(inout logic_t x); $display("e_logic_t %1d", n_logic_t); if (x !== ~n_logic_t[0]) $stop; x = ~x; n_logic_t++; endfunction // 2-state packed arrays int n_array_2_state_1 = 0; function void e_array_2_state_1(inout bit [ 0:0] x); $display("e_array_2_state_1 %1d", n_array_2_state_1); if (x !== n_array_2_state_1[0]) $stop; x = ~x; n_array_2_state_1++; endfunction int n_array_2_state_32 = 0; function void e_array_2_state_32(inout bit [31:0] x); $display("e_array_2_state_32 %1d", n_array_2_state_32); if (x !== ~32'd0 >> n_array_2_state_32) $stop; x <<= n_array_2_state_32; n_array_2_state_32++; endfunction int n_array_2_state_33 = 0; function void e_array_2_state_33(inout bit [32:0] x); $display("e_array_2_state_33 %1d", n_array_2_state_33); if (x !== ~33'd0 >> n_array_2_state_33) $stop; x <<= n_array_2_state_33; n_array_2_state_33++; endfunction int n_array_2_state_64 = 0; function void e_array_2_state_64(inout bit [63:0] x); $display("e_array_2_state_64 %1d", n_array_2_state_64); if (x !== ~64'd0 >> n_array_2_state_64) $stop; x <<= n_array_2_state_64; n_array_2_state_64++; endfunction int n_array_2_state_65 = 0; function void e_array_2_state_65(inout bit [64:0] x); $display("e_array_2_state_65 %1d", n_array_2_state_65); if (x !== ~65'd0 >> n_array_2_state_65) $stop; x <<= n_array_2_state_65; n_array_2_state_65++; endfunction int n_array_2_state_128 = 0; function void e_array_2_state_128(inout bit [127:0] x); $display("e_array_2_state_128 %1d", n_array_2_state_128); if (x !== ~128'd0 >> n_array_2_state_128) $stop; x <<= n_array_2_state_128; n_array_2_state_128++; endfunction // 2-state packed structures int n_struct_2_state_1 = 0; function void e_struct_2_state_1(inout struct_2_state_1 x); $display("e_struct_2_state_1 %1d", n_struct_2_state_1); if (x !== n_struct_2_state_1[0]) $stop; x = ~x; n_struct_2_state_1++; endfunction int n_struct_2_state_32 = 0; function void e_struct_2_state_32(inout struct_2_state_32 x); $display("e_struct_2_state_32 %1d", n_struct_2_state_32); if (x !== ~32'd0 >> n_struct_2_state_32) $stop; x <<= n_struct_2_state_32; n_struct_2_state_32++; endfunction int n_struct_2_state_33 = 0; function void e_struct_2_state_33(inout struct_2_state_33 x); $display("e_struct_2_state_33 %1d", n_struct_2_state_33); if (x !== ~33'd0 >> n_struct_2_state_33) $stop; x <<= n_struct_2_state_33; n_struct_2_state_33++; endfunction int n_struct_2_state_64 = 0; function void e_struct_2_state_64(inout struct_2_state_64 x); $display("e_struct_2_state_64 %1d", n_struct_2_state_64); if (x !== ~64'd0 >> n_struct_2_state_64) $stop; x <<= n_struct_2_state_64; n_struct_2_state_64++; endfunction int n_struct_2_state_65 = 0; function void e_struct_2_state_65(inout struct_2_state_65 x); $display("e_struct_2_state_65 %1d", n_struct_2_state_65); if (x !== ~65'd0 >> n_struct_2_state_65) $stop; x <<= n_struct_2_state_65; n_struct_2_state_65++; endfunction int n_struct_2_state_128 = 0; function void e_struct_2_state_128(inout struct_2_state_128 x); $display("e_struct_2_state_128 %1d", n_struct_2_state_128); if (x !== ~128'd0 >> n_struct_2_state_128) $stop; x <<= n_struct_2_state_128; n_struct_2_state_128++; endfunction // 2-state packed unions int n_union_2_state_1 = 0; function void e_union_2_state_1(inout union_2_state_1 x); $display("e_union_2_state_1 %1d", n_union_2_state_1); if (x !== n_union_2_state_1[0]) $stop; x = ~x; n_union_2_state_1++; endfunction int n_union_2_state_32 = 0; function void e_union_2_state_32(inout union_2_state_32 x); $display("e_union_2_state_32 %1d", n_union_2_state_32); if (x !== ~32'd0 >> n_union_2_state_32) $stop; x <<= n_union_2_state_32; n_union_2_state_32++; endfunction int n_union_2_state_33 = 0; function void e_union_2_state_33(inout union_2_state_33 x); $display("e_union_2_state_33 %1d", n_union_2_state_33); if (x !== ~33'd0 >> n_union_2_state_33) $stop; x <<= n_union_2_state_33; n_union_2_state_33++; endfunction int n_union_2_state_64 = 0; function void e_union_2_state_64(inout union_2_state_64 x); $display("e_union_2_state_64 %1d", n_union_2_state_64); if (x !== ~64'd0 >> n_union_2_state_64) $stop; x <<= n_union_2_state_64; n_union_2_state_64++; endfunction int n_union_2_state_65 = 0; function void e_union_2_state_65(inout union_2_state_65 x); $display("e_union_2_state_65 %1d", n_union_2_state_65); if (x !== ~65'd0 >> n_union_2_state_65) $stop; x <<= n_union_2_state_65; n_union_2_state_65++; endfunction int n_union_2_state_128 = 0; function void e_union_2_state_128(inout union_2_state_128 x); $display("e_union_2_state_128 %1d", n_union_2_state_128); if (x !== ~128'd0 >> n_union_2_state_128) $stop; x <<= n_union_2_state_128; n_union_2_state_128++; endfunction // 4-state packed arrays int n_array_4_state_1 = 0; function void e_array_4_state_1(inout logic [ 0:0] x); $display("e_array_4_state_1 %1d", n_array_4_state_1); if (x !== n_array_4_state_1[0]) $stop; x = ~x; n_array_4_state_1++; endfunction int n_array_4_state_32 = 0; function void e_array_4_state_32(inout logic [31:0] x); $display("e_array_4_state_32 %1d", n_array_4_state_32); if (x !== ~32'd0 >> n_array_4_state_32) $stop; x <<= n_array_4_state_32; n_array_4_state_32++; endfunction int n_array_4_state_33 = 0; function void e_array_4_state_33(inout logic [32:0] x); $display("e_array_4_state_33 %1d", n_array_4_state_33); if (x !== ~33'd0 >> n_array_4_state_33) $stop; x <<= n_array_4_state_33; n_array_4_state_33++; endfunction int n_array_4_state_64 = 0; function void e_array_4_state_64(inout logic [63:0] x); $display("e_array_4_state_64 %1d", n_array_4_state_64); if (x !== ~64'd0 >> n_array_4_state_64) $stop; x <<= n_array_4_state_64; n_array_4_state_64++; endfunction int n_array_4_state_65 = 0; function void e_array_4_state_65(inout logic [64:0] x); $display("e_array_4_state_65 %1d", n_array_4_state_65); if (x !== ~65'd0 >> n_array_4_state_65) $stop; x <<= n_array_4_state_65; n_array_4_state_65++; endfunction int n_array_4_state_128 = 0; function void e_array_4_state_128(inout logic [127:0] x); $display("e_array_4_state_128 %1d", n_array_4_state_128); if (x !== ~128'd0 >> n_array_4_state_128) $stop; x <<= n_array_4_state_128; n_array_4_state_128++; endfunction // 4-state packed structures int n_struct_4_state_1 = 0; function void e_struct_4_state_1(inout struct_4_state_1 x); $display("e_struct_4_state_1 %1d", n_struct_4_state_1); if (x !== n_struct_4_state_1[0]) $stop; x = ~x; n_struct_4_state_1++; endfunction int n_struct_4_state_32 = 0; function void e_struct_4_state_32(inout struct_4_state_32 x); $display("e_struct_4_state_32 %1d", n_struct_4_state_32); if (x !== ~32'd0 >> n_struct_4_state_32) $stop; x <<= n_struct_4_state_32; n_struct_4_state_32++; endfunction int n_struct_4_state_33 = 0; function void e_struct_4_state_33(inout struct_4_state_33 x); $display("e_struct_4_state_33 %1d", n_struct_4_state_33); if (x !== ~33'd0 >> n_struct_4_state_33) $stop; x <<= n_struct_4_state_33; n_struct_4_state_33++; endfunction int n_struct_4_state_64 = 0; function void e_struct_4_state_64(inout struct_4_state_64 x); $display("e_struct_4_state_64 %1d", n_struct_4_state_64); if (x !== ~64'd0 >> n_struct_4_state_64) $stop; x <<= n_struct_4_state_64; n_struct_4_state_64++; endfunction int n_struct_4_state_65 = 0; function void e_struct_4_state_65(inout struct_4_state_65 x); $display("e_struct_4_state_65 %1d", n_struct_4_state_65); if (x !== ~65'd0 >> n_struct_4_state_65) $stop; x <<= n_struct_4_state_65; n_struct_4_state_65++; endfunction int n_struct_4_state_128 = 0; function void e_struct_4_state_128(inout struct_4_state_128 x); $display("e_struct_4_state_128 %1d", n_struct_4_state_128); if (x !== ~128'd0 >> n_struct_4_state_128) $stop; x <<= n_struct_4_state_128; n_struct_4_state_128++; endfunction // 4-state packed unions int n_union_4_state_1 = 0; function void e_union_4_state_1(inout union_4_state_1 x); $display("e_union_4_state_1 %1d", n_union_4_state_1); if (x !== n_union_4_state_1[0]) $stop; x = ~x; n_union_4_state_1++; endfunction int n_union_4_state_32 = 0; function void e_union_4_state_32(inout union_4_state_32 x); $display("e_union_4_state_32 %1d", n_union_4_state_32); if (x !== ~32'd0 >> n_union_4_state_32) $stop; x <<= n_union_4_state_32; n_union_4_state_32++; endfunction int n_union_4_state_33 = 0; function void e_union_4_state_33(inout union_4_state_33 x); $display("e_union_4_state_33 %1d", n_union_4_state_33); if (x !== ~33'd0 >> n_union_4_state_33) $stop; x <<= n_union_4_state_33; n_union_4_state_33++; endfunction int n_union_4_state_64 = 0; function void e_union_4_state_64(inout union_4_state_64 x); $display("e_union_4_state_64 %1d", n_union_4_state_64); if (x !== ~64'd0 >> n_union_4_state_64) $stop; x <<= n_union_4_state_64; n_union_4_state_64++; endfunction int n_union_4_state_65 = 0; function void e_union_4_state_65(inout union_4_state_65 x); $display("e_union_4_state_65 %1d", n_union_4_state_65); if (x !== ~65'd0 >> n_union_4_state_65) $stop; x <<= n_union_4_state_65; n_union_4_state_65++; endfunction int n_union_4_state_128 = 0; function void e_union_4_state_128(inout union_4_state_128 x); $display("e_union_4_state_128 %1d", n_union_4_state_128); if (x !== ~128'd0 >> n_union_4_state_128) $stop; x <<= n_union_4_state_128; n_union_4_state_128++; endfunction //====================================================================== // Invoke all functions 3 times (they have side effects) //====================================================================== import "DPI-C" context function void check_exports(); initial begin for (int i = 0 ; i < 3; i++) begin // Check the imports byte x_byte; byte unsigned x_byte_unsigned; shortint x_shortint; shortint unsigned x_shortint_unsigned; int x_int; int unsigned x_int_unsigned; longint x_longint; longint unsigned x_longint_unsigned; `ifndef NO_TIME time x_time; `endif `ifndef NO_INTEGER integer x_integer; `endif real x_real; `ifndef NO_SHORTREAL shortreal x_shortreal; `endif chandle x_chandle; string x_string; bit x_bit; logic x_logic; byte_t x_byte_t; byte_unsigned_t x_byte_unsigned_t; shortint_t x_shortint_t; shortint_unsigned_t x_shortint_unsigned_t; int_t x_int_t; int_unsigned_t x_int_unsigned_t; longint_t x_longint_t; longint_unsigned_t x_longint_unsigned_t; `ifndef NO_TIME time_t x_time_t; `endif `ifndef NO_INTEGER integer_t x_integer_t; `endif real_t x_real_t; `ifndef NO_SHORTREAL shortreal_t x_shortreal_t; `endif chandle_t x_chandle_t; string_t x_string_t; bit_t x_bit_t; logic_t x_logic_t; bit [ 0:0] x_bit_1; bit [ 31:0] x_bit_32; bit [ 32:0] x_bit_33; bit [ 63:0] x_bit_64; bit [ 64:0] x_bit_65; bit [127:0] x_bit_128; struct_2_state_1 x_struct_2_state_1; struct_2_state_32 x_struct_2_state_32; struct_2_state_33 x_struct_2_state_33; struct_2_state_64 x_struct_2_state_64; struct_2_state_65 x_struct_2_state_65; struct_2_state_128 x_struct_2_state_128; union_2_state_1 x_union_2_state_1; union_2_state_32 x_union_2_state_32; union_2_state_33 x_union_2_state_33; union_2_state_64 x_union_2_state_64; union_2_state_65 x_union_2_state_65; union_2_state_128 x_union_2_state_128; logic [ 0:0] x_logic_1; logic [ 31:0] x_logic_32; logic [ 32:0] x_logic_33; logic [ 63:0] x_logic_64; logic [ 64:0] x_logic_65; logic [127:0] x_logic_128; struct_4_state_1 x_struct_4_state_1; struct_4_state_32 x_struct_4_state_32; struct_4_state_33 x_struct_4_state_33; struct_4_state_64 x_struct_4_state_64; struct_4_state_65 x_struct_4_state_65; struct_4_state_128 x_struct_4_state_128; union_4_state_1 x_union_4_state_1; union_4_state_32 x_union_4_state_32; union_4_state_33 x_union_4_state_33; union_4_state_64 x_union_4_state_64; union_4_state_65 x_union_4_state_65; union_4_state_128 x_union_4_state_128; // Basic types as per IEEE 1800-2017 35.5.6 x_byte = 8'd10 - 8'(i); i_byte(x_byte); if (x_byte !== 8'd110 - 8'(i)) $stop; x_byte_unsigned = 8'd20 - 8'(i); i_byte_unsigned(x_byte_unsigned); if (x_byte_unsigned !== 8'd220 - 8'(i)) $stop; x_shortint = 16'd30 - 16'(i); i_shortint(x_shortint); if (x_shortint !== 16'd330 - 16'(i)) $stop; x_shortint_unsigned = 16'd40 - 16'(i); i_shortint_unsigned(x_shortint_unsigned); if (x_shortint_unsigned !== 16'd440 - 16'(i)) $stop; x_int = 32'd50 - 32'(i); i_int(x_int); if (x_int !== 32'd550 - 32'(i)) $stop; x_int_unsigned = 32'd60 - 32'(i); i_int_unsigned(x_int_unsigned); if (x_int_unsigned !== 32'd660 - 32'(i)) $stop; x_longint = 64'd70 - 64'(i); i_longint(x_longint); if (x_longint !== 64'd770 - 64'(i)) $stop; x_longint_unsigned = 64'd80 - 64'(i); i_longint_unsigned(x_longint_unsigned); if (x_longint_unsigned !== 64'd880 - 64'(i)) $stop; `ifndef NO_TIME x_time = 64'd90 - 64'(i); i_time(x_time); if (x_time !== 64'd990 - 64'(i)) $stop; `endif `ifndef NO_INTEGER x_integer = 32'd100- 32'(i); i_integer(x_integer); if (x_integer !== 32'd1100- 32'(i)) $stop; `endif x_real = -1.0*i - 0.50; i_real(x_real); if (x_real != -100.0 + -1.0*i - 0.50) $stop; `ifndef NO_SHORTREAL x_shortreal = -1.0*i - 0.25; i_shortreal(x_shortreal); if (x_shortreal != -200.0 + -1.0*i - 0.25) $stop; `endif if (~i[0]) begin x_chandle = `NULL; i_chandle(x_chandle); if (x_chandle !== `NULL) $stop; x_string = "Hello"; i_string(x_string); if (x_string != "Good") $stop; end else begin x_chandle = `NULL; i_chandle(x_chandle); if (x_chandle === `NULL) $stop; x_string = "World"; i_string(x_string); if (x_string != "Bye" ) $stop; end x_bit = ~i[0]; i_bit(x_bit); if (x_bit !== i[0]) $stop; x_logic = i[0]; i_logic(x_logic); if (x_logic !== ~i[0]) $stop; // Basic types via typedefs x_byte_t = 8'd10 - 8'(2*i); i_byte_t(x_byte_t); if (x_byte_t !== 8'd111 - 8'(2*i)) $stop; x_byte_unsigned_t = 8'd20 - 8'(2*i); i_byte_unsigned_t(x_byte_unsigned_t); if (x_byte_unsigned_t !== 8'd222 - 8'(2*i)) $stop; x_shortint_t = 16'd30 - 16'(2*i); i_shortint_t(x_shortint_t); if (x_shortint_t !== 16'd333 - 16'(2*i)) $stop; x_shortint_unsigned_t = 16'd40 - 16'(2*i); i_shortint_unsigned_t(x_shortint_unsigned_t); if (x_shortint_unsigned_t !== 16'd444 - 16'(2*i)) $stop; x_int_t = 32'd50 - 32'(2*i); i_int_t(x_int_t); if (x_int_t !== 32'd555 - 32'(2*i)) $stop; x_int_unsigned_t = 32'd60 - 32'(2*i); i_int_unsigned_t(x_int_unsigned_t); if (x_int_unsigned_t !== 32'd666 - 32'(2*i)) $stop; x_longint_t = 64'd70 - 64'(2*i); i_longint_t(x_longint_t); if (x_longint_t !== 64'd777 - 64'(2*i)) $stop; x_longint_unsigned_t = 64'd80 - 64'(2*i); i_longint_unsigned_t(x_longint_unsigned_t); if (x_longint_unsigned_t !== 64'd888 - 64'(2*i)) $stop; `ifndef NO_TIME x_time_t = 64'd90 - 64'(2*i); i_time_t(x_time_t); if (x_time_t !== 64'd999 - 64'(2*i)) $stop; `endif `ifndef NO_INTEGER x_integer_t = 32'd100- 32'(2*i); i_integer_t(x_integer_t); if (x_integer_t !== 32'd1101- 32'(2*i)) $stop; `endif x_real_t = -1.0*(2*i) - 0.50; i_real_t(x_real_t); if (x_real_t != -111.0 + -1.0*(2*i) - 0.50) $stop; `ifndef NO_SHORTREAL x_shortreal_t = -1.0*(2*i) - 0.25; i_shortreal_t(x_shortreal_t); if (x_shortreal_t != -222.0 + -1.0*(2*i) - 0.25) $stop; `endif if (~i[0]) begin x_chandle_t = `NULL; i_chandle_t(x_chandle_t); if (x_chandle_t === `NULL) $stop; x_string_t = "World"; i_string_t(x_string_t); if (x_string_t != "Bye") $stop; end else begin x_chandle_t = `NULL; i_chandle_t(x_chandle_t); if (x_chandle_t !== `NULL) $stop; x_string_t = "Hello"; i_string_t(x_string_t); if (x_string_t != "Good") $stop; end x_bit_t = ~i[0]; i_bit_t(x_bit_t); if (x_bit_t !== i[0]) $stop; x_logic_t = i[0]; i_logic_t(x_logic_t); if (x_logic_t !== ~i[0]) $stop; // 2-state packed arrays x_bit_1 = ~i[0]; i_array_2_state_1(x_bit_1); if (x_bit_1 !== i[0] ) $stop; x_bit_32 = ~32'd0 << i; i_array_2_state_32(x_bit_32); if (x_bit_32 !== ~32'd0 >> i) $stop; x_bit_33 = ~33'd0 << i; i_array_2_state_33(x_bit_33); if (x_bit_33 !== ~33'd0 >> i) begin $display("%d %x %0x", i, x_bit_33, ~33'd0 >> i); $stop; end x_bit_64 = ~64'd0 << i; i_array_2_state_64(x_bit_64); if (x_bit_64 !== ~64'd0 >> i) $stop; x_bit_65 = ~65'd0 << i; i_array_2_state_65(x_bit_65); if (x_bit_65 !== ~65'd0 >> i) $stop; x_bit_128 = ~128'd0<< i; i_array_2_state_128(x_bit_128); if (x_bit_128 !== ~128'd0>> i) $stop; // 2-state packed structures x_struct_2_state_1 = ~i[0]; i_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1 !== i[0] ) $stop; x_struct_2_state_32 = ~32'd0 << i; i_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32 !== ~32'd0 >> i) $stop; x_struct_2_state_33 = ~33'd0 << i; i_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33 !== ~33'd0 >> i) $stop; x_struct_2_state_64 = ~64'd0 << i; i_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64 !== ~64'd0 >> i) $stop; x_struct_2_state_65 = ~65'd0 << i; i_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65 !== ~65'd0 >> i) $stop; x_struct_2_state_128= ~128'd0<< i; i_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128!== ~128'd0>> i) $stop; // 2-state packed unions x_union_2_state_1 = ~i[0]; i_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1 !== i[0] ) $stop; x_union_2_state_32 = ~32'd0 << i; i_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32 !== ~32'd0 >> i) $stop; x_union_2_state_33 = ~33'd0 << i; i_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33 !== ~33'd0 >> i) $stop; x_union_2_state_64 = ~64'd0 << i; i_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64 !== ~64'd0 >> i) $stop; x_union_2_state_65 = ~65'd0 << i; i_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65 !== ~65'd0 >> i) $stop; x_union_2_state_128 = ~128'd0<< i; i_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128 !== ~128'd0>> i) $stop; // 4-state packed arrays x_logic_1 = ~i[0]; i_array_4_state_1(x_logic_1); if (x_logic_1 !== i[0] ) $stop; x_logic_32 = ~32'd0 << i; i_array_4_state_32(x_logic_32); if (x_logic_32 !== ~32'd0 >> i) $stop; x_logic_33 = ~33'd0 << i; i_array_4_state_33(x_logic_33); if (x_logic_33 !== ~33'd0 >> i) $stop; x_logic_64 = ~64'd0 << i; i_array_4_state_64(x_logic_64); if (x_logic_64 !== ~64'd0 >> i) $stop; x_logic_65 = ~65'd0 << i; i_array_4_state_65(x_logic_65); if (x_logic_65 !== ~65'd0 >> i) $stop; x_logic_128 = ~128'd0<< i; i_array_4_state_128(x_logic_128); if (x_logic_128 !== ~128'd0>> i) $stop; // 4-state packed structures x_struct_4_state_1 = ~i[0]; i_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1 !== i[0] ) $stop; x_struct_4_state_32 = ~32'd0 << i; i_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32 !== ~32'd0 >> i) $stop; x_struct_4_state_33 = ~33'd0 << i; i_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33 !== ~33'd0 >> i) $stop; x_struct_4_state_64 = ~64'd0 << i; i_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64 !== ~64'd0 >> i) $stop; x_struct_4_state_65 = ~65'd0 << i; i_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65 !== ~65'd0 >> i) $stop; x_struct_4_state_128= ~128'd0<< i; i_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128!== ~128'd0>> i) $stop; // 4-state packed unions x_union_4_state_1 = ~i[0]; i_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1 !== i[0] ) $stop; x_union_4_state_32 = ~32'd0 << i; i_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32 !== ~32'd0 >> i) $stop; x_union_4_state_33 = ~33'd0 << i; i_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33 !== ~33'd0 >> i) $stop; x_union_4_state_64 = ~64'd0 << i; i_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64 !== ~64'd0 >> i) $stop; x_union_4_state_65 = ~65'd0 << i; i_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65 !== ~65'd0 >> i) $stop; x_union_4_state_128 = ~128'd0<< i; i_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128 !== ~128'd0>> i) $stop; // Check the exports check_exports(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_clk_condflop_nord.pl0000775000177100017500000000114013702133367023033 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2=>["-no-order-clock-delay"], ); execute( check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_system.v0000664000177100017500000000133113702133370021421 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer i; initial begin `ifndef VERILATOR `ifndef VCS `ifndef NC $system(); // Legal per spec, but not supported everywhere and nonsensical `endif `endif `endif $system("exit 0"); $system("echo hello"); `ifndef VCS i = $system("exit 0"); if (i!==0) $stop; i = $system("exit 10"); if (i!==10) $stop; i = $system("exit 20"); // Wide if (i!==20) $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_cat_renew.pl0000775000177100017500000000157413702133370022506 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_trace_cat.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_cat.cpp"], ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simpart_0000.vcd", "t/$Self->{name}_0000.out"); vcd_identical("$Self->{obj_dir}/simpart_0100.vcd", "t/$Self->{name}_0100.out"); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_portfst_cc.pl0000775000177100017500000000226013702133370023567 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); top_filename("t_trace_two_a.v"); compile( make_main => 0, verilator_make_gmake => 0, top_filename => 't_trace_two_b.v', VM_PREFIX => 'Vt_trace_two_b', verilator_flags2 => ['--trace-fst --trace-threads 1'], ); compile( make_main => 0, top_filename => 't_trace_two_a.v', verilator_flags2 => ['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', "$Self->{t_dir}/t_trace_two_cc.cpp"], v_flags2 => ['+define+TEST_DUMPPORTS'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { fst_identical($Self->trace_filename, $Self->{golden_filename}); } ok(1); 1; verilator-4.038/test_regress/t/t_concat_large_bad.out0000664000177100017500000000062213702133367023000 0ustar wsnyderwsnyder%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:9:29: More than a 8k bit replication is probably wrong: 32768 : ... In instance t 9 | wire [32767:0] a = {32768{1'b1}}; | ^ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_inst_dtree.v0000664000177100017500000000267513702133370021353 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef INLINE_A //verilator inline_module `else //verilator no_inline_module `endif bmod bsub3 (.clk, .n(3)); bmod bsub2 (.clk, .n(2)); bmod bsub1 (.clk, .n(1)); bmod bsub0 (.clk, .n(0)); endmodule module bmod (input clk, input [31:0] n); `ifdef INLINE_B //verilator inline_module `else //verilator no_inline_module `endif cmod csub (.clk, .n); endmodule module cmod (input clk, input [31:0] n); `ifdef INLINE_C //verilator inline_module `else //verilator no_inline_module `endif reg [31:0] clocal; always @ (posedge clk) clocal <= n; dmod dsub (.clk, .n); endmodule module dmod (input clk, input [31:0] n); `ifdef INLINE_D //verilator inline_module `else //verilator no_inline_module `endif reg [31:0] dlocal; always @ (posedge clk) dlocal <= n; int cyc; always @(posedge clk) begin cyc <= cyc+1; end always @(posedge clk) begin if (cyc>10) begin `ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif if (csub.clocal !== n) $stop; if (dlocal !== n) $stop; end if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_param_width_loc_bad.out0000664000177100017500000000175413702133370023514 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_param_width_loc_bad.v:22: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits. : ... In instance t.test_i parameter logic param = 1'b0 ^~~~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to # I believe this warning message should be pointing to line 12 instead, i.e., wherever the wrongly sized parameter is given as an input rather than the parameter definition. # It would be more informative if it looked like this: %Warning-WIDTH: t/t_param_width_loc_bad.v:12: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits. test #(.param(32'd0)) test_i; ^~~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_bitsel_struct2.pl0000775000177100017500000000105313702133367022327 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_const_dec_mixed_bad.pl0000775000177100017500000000110113702133367023306 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_cmtend_bad.v0000664000177100017500000000034213702133370023012 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 /*Blah blah verilator-4.038/test_regress/t/t_func_dotted_inl1.vlt0000664000177100017500000000041513702133370022762 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config inline -module "global_mod" inline -module "m*" verilator-4.038/test_regress/t/t_flag_build.pl0000775000177100017500000000212213702133370021437 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_flag_make_cmake.v"); compile( # Don't call cmake nor gmake from driver.pl verilator_make_cmake => 0, verilator_make_gmake => 0, verilator_flags2 => ['--exe --cc --build -j 2', '../' . $Self->{main_filename}, '-MAKEFLAGS -p --trace'], ); execute( check_finished => 1, ); # If '-MAKEFLAGS --trace' is not properly processed, # the log will not contain 'CMAKE_BUILD_TYPE:STRING=Debug'. file_grep($Self->{obj_dir} . '/vlt_compile.log', /^Vt_flag_build_make.mk:\d+: update target \'(\w+)\' due to:/, 'Vt_flag_build'); ok(1); 1; verilator-4.038/test_regress/t/t_flag_relinc.pl0000775000177100017500000000117313702133370021621 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( v_flags2 => ["--relative-includes", "--lint-only $Self->{t_dir}/t_flag_relinc_dir/chip/t_flag_relinc_sub.v"], ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_if.v0000664000177100017500000000217413702133370020434 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // simplistic example, should choose 1st conditional generate and assign straight through // the tool also compiles the special case and determines an error (replication value is 0) // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps module t(data_i, data_o, single); parameter op_bits = 32; input [op_bits -1:0] data_i; output [31:0] data_o; input single; //simplistic example, should choose 1st conditional generate and assign straight through //the tool also compiles the special case and determines an error (replication value is 0 generate if (op_bits == 32) begin : general_case assign data_o = data_i; // Test implicit signals /* verilator lint_off IMPLICIT */ assign imp = single; /* verilator lint_on IMPLICIT */ end else begin : special_case assign data_o = {{(32 -op_bits){1'b0}},data_i}; /* verilator lint_off IMPLICIT */ assign imp = single; /* verilator lint_on IMPLICIT */ end endgenerate endmodule verilator-4.038/test_regress/t/t_alw_combdly.pl0000775000177100017500000000105313702133367021653 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_werror_bad2.pl0000775000177100017500000000121513702133370022552 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_werror.v"); lint( fails => 1, verilator_flags => [qw(-cc -Werror-WIDTH)], expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_outfirst.pl0000775000177100017500000000105313702133370022243 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_bitsel_wire_array_bad.out0000664000177100017500000000035013702133367024063 0ustar wsnyderwsnyder%Error: t/t_bitsel_wire_array_bad.v:21:16: Illegal assignment of constant to unpacked array : ... In instance t 21 | assign b = a[0]; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_array_type_methods.v0000664000177100017500000000165613702133367023121 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [3:0] foo [1:0]; initial begin foo[0] = 4'b0101; foo[1] = 4'b0011; `checkh(foo.or, 4'b0111); `checkh(foo.and, 4'b0001); `checkh(foo.xor, 4'b0110); `checkh(foo.sum, 4'b1000); `checkh(foo.product, 4'b1111); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_gen_for1.v0000664000177100017500000000305313702133370020702 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire b; reg reset; integer cyc=0; Testit testit (/*AUTOINST*/ // Outputs .b (b), // Inputs .clk (clk), .reset (reset)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin reset <= 1'b0; end else if (cyc<10) begin reset <= 1'b1; end else if (cyc<90) begin reset <= 1'b0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Testit (clk, reset, b); input clk; input reset; output b; wire [0:0] c; wire my_sig; wire [0:0] d; genvar i; generate for(i = 0; i >= 0; i = i-1) begin: fnxtclk1 fnxtclk fnxtclk1 (.u(c[i]), .reset(reset), .clk(clk), .w(d[i]) ); end endgenerate assign b = d[0]; assign c[0] = my_sig; assign my_sig = 1'b1; endmodule module fnxtclk (u, reset, clk, w ); input u; input reset; input clk; output reg w; always @ (posedge clk or posedge reset) begin if (reset == 1'b1) begin w <= 1'b0; end else begin w <= u; end end endmodule verilator-4.038/test_regress/t/t_gate_chained.pl0000775000177100017500000000333413702133370021750 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; scenarios(simulator => 1); sub gen { my $filename = shift; my $fh = IO::File->new(">$filename"); $fh->print("// Generated by t_gate_chained.pl\n"); $fh->print("module t (clk,i,sel,o);\n"); $fh->print(" input clk;\n"); $fh->print(" input [63:0] i;\n"); $fh->print(" input [15:0] sel;\n"); $fh->print(" output [63:0] o;\n"); $fh->print("\n"); my $prev = "i"; my $n = 9000; for (my $i=1; $i<$n; ++$i) { $fh->printf(" wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : $prev;\n", $i, $i); $prev = sprintf("ass%04x", $i); } $fh->print("\n"); $fh->print(" wire [63:0] o = $prev;\n"); $fh->print("\n"); $fh->print(" always @ (posedge clk) begin\n"); $fh->print(' $write("*-* All Finished *-*\n");',"\n"); $fh->print(' $finish;',"\n"); $fh->print(" end\n"); $fh->print("endmodule\n"); } top_filename("$Self->{obj_dir}/t_gate_chained.v"); gen($Self->{top_filename}); compile( verilator_flags2=>["--stats --x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS"], ); execute( check_finished => 1, ); # Must be <<9000 above to prove this worked file_grep($Self->{stats}, qr/Optimizations, Gate sigs deleted\s+(\d+)/i, 8575); ok(1); 1; verilator-4.038/test_regress/t/t_var_dup3.v0000664000177100017500000000105513702133370020725 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Legal with Verilog 1995 style ports module t (/*AUTOARG*/ // Outputs ok_o_w, ok_o_r, ok_o_ra, ok_or, ok_ow, ok_owa ); output ok_o_w; wire ok_o_w; output ok_o_r; reg ok_o_r; output [1:0] ok_o_ra; reg [1:0] ok_o_ra; output reg ok_or; output wire ok_ow; output wire [1:0] ok_owa; endmodule verilator-4.038/test_regress/t/t_sys_readmem_h.mem0000664000177100017500000000104713702133370022333 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 4004_37654321_27654321_17654321_07654321_abcdef10 @a 400a_37654321_27654321_17654321_07654321_abcdef11 400b_37654321_27654321_17654321_07654321_abcdef12 400c_37654321_27654321_17654321_07654321_abcdef13 verilator-4.038/test_regress/t/t_stream3.v0000664000177100017500000000447613702133370020572 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ generate for (genvar width=1; width<=16; width++) begin for (genvar amt=1; amt<=width; amt++) begin Test #(.WIDTH(width), .AMT(amt)) test (.ins(crc[width-1:0])); end end endgenerate // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Inputs ins ); parameter WIDTH = 1; parameter AMT = 1; input [WIDTH-1:0] ins; reg [WIDTH-1:0] got; reg [WIDTH-1:0] expec; int istart; int bitn; int ostart; always @* begin got = { << AMT {ins}}; // Note always starts with right-most bit expec = 0; for (istart=0; istart= 0 && (ostart+bitn) < WIDTH && (ostart+bitn) >= 0) begin expec[ostart+bitn] = ins[istart+bitn]; end end end `ifdef TEST_VERBOSE $write("[%0t] exp %0d'b%b got %0d'b%b = { << %0d { %0d'b%b }}\n", $time, WIDTH, expec, WIDTH, got, AMT, WIDTH, ins); `endif `checkh(got, expec); end endmodule verilator-4.038/test_regress/t/t_math_arith.pl0000775000177100017500000000105313702133370021471 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_literal_bad.out0000664000177100017500000000046613702133370023041 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256 10 | localparam the_localparam = 8'd256; | ^~~~~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_assert_disable_iff.pl0000775000177100017500000000115313702133367023170 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert --cc --coverage-user'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_enabled_on_bad.pl0000775000177100017500000000115113702133367023633 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_assert_on.v"); compile( verilator_flags2 => ["--assert"], ); execute( fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_pindup_bad.pl0000775000177100017500000000107413702133370022507 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_uniqueif_fail4.out0000664000177100017500000000021713702133370022447 0ustar wsnyderwsnyder[10] %Error: t_uniqueif.v:102: Assertion failed in top.t: 'unique if' statement violated %Error: t/t_uniqueif.v:102: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_assert_synth_parallel_vlt.pl0000775000177100017500000000147013702133367024651 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_synth.v"); compile( v_flags2 => ['+define+FAILING_PARALLEL', "t/t_assert_synth_parallel.vlt"], verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], ); execute( check_finished => 0, fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_number_bad.out0000664000177100017500000000250213702133370021640 0ustar wsnyderwsnyder%Error: t/t_number_bad.v:9:29: Number is missing value digits: 32'd 9 | parameter integer FOO2 = 32'd-6; | ^~~~ %Error: t/t_number_bad.v:10:29: Number is missing value digits: 32'd 10 | parameter integer FOO3 = 32'd; | ^~~~ %Error: t/t_number_bad.v:11:29: Number is missing value digits: 32'h 11 | parameter integer FOO4 = 32'h; | ^~~~ %Error: t/t_number_bad.v:13:29: Illegal character in binary constant: 2 13 | parameter integer FOO5 = 32'b2; | ^~~~~ %Error: t/t_number_bad.v:14:29: Illegal character in octal constant 14 | parameter integer FOO6 = 32'o8; | ^~~~~ %Error: t/t_number_bad.v:17:33: Illegal character in binary constant: 4 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; | ^~~~~~ %Error: t/t_number_bad.v:17:33: Too many digits for 1 bit number: 1'b1?4 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; | ^~~~~~ %Error: t/t_number_bad.v:17:39: syntax error, unexpected INTEGER NUMBER, expecting ';' 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_gen7_noinl.pl0000775000177100017500000000116013702133370023427 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen7.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_return.pl0000775000177100017500000000105313702133370021703 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_ref_trace.pl0000775000177100017500000000126413702133370023327 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--trace-structs --trace'], ); execute( check_finished => 1, ); vcd_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_assert_inside_cond_bad.pl0000775000177100017500000000131313702133367024023 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_assert_inside_cond.v"); compile( verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"], ); execute( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_bad_sameas.out0000664000177100017500000000275413702133370022502 0ustar wsnyderwsnyder%Error: t/t_var_bad_sameas.v:10:8: Unsupported in C: Cell has the same name as variable: 'varfirst' 10 | sub varfirst (); | ^~~~~~~~ t/t_var_bad_sameas.v:9:12: ... Location of original declaration 9 | integer varfirst; | ^~~~~~~~ %Error: t/t_var_bad_sameas.v:11:9: Unsupported in C: Task has the same name as cell: 'varfirst' 11 | task varfirst; begin end endtask | ^~~~~~~~ t/t_var_bad_sameas.v:10:8: ... Location of original declaration 10 | sub varfirst (); | ^~~~~~~~ %Error: t/t_var_bad_sameas.v:14:12: Unsupported in C: Variable has same name as cell: 'cellfirst' 14 | integer cellfirst; | ^~~~~~~~~ %Error: t/t_var_bad_sameas.v:15:9: Unsupported in C: Task has the same name as cell: 'cellfirst' 15 | task cellfirst; begin end endtask | ^~~~~~~~~ t/t_var_bad_sameas.v:13:8: ... Location of original declaration 13 | sub cellfirst (); | ^~~~~~~~~ %Error: t/t_var_bad_sameas.v:18:12: Unsupported in C: Variable has same name as task: 'taskfirst' 18 | integer taskfirst; | ^~~~~~~~~ %Error: t/t_var_bad_sameas.v:19:8: Unsupported in C: Cell has the same name as task: 'taskfirst' 19 | sub taskfirst (); | ^~~~~~~~~ t/t_var_bad_sameas.v:17:9: ... Location of original declaration 17 | task taskfirst; begin end endtask | ^~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_unicode.pl0000775000177100017500000000272013702133370021001 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; #use Data::Dumper; use strict; use vars qw($Self); scenarios(simulator => 1); sub gen { my $filename = shift; my $fh = IO::File->new(">$filename"); $fh->print(chr(0xEF).chr(0xBB).chr(0xBF)); # BOM $fh->print("// Bom\n"); $fh->print("// Generated by t_unicode.pl\n"); $fh->print("module t;\n"); $fh->print(" // Chinese " .chr(0xe8).chr(0xaf).chr(0x84).chr(0xe8).chr(0xae).chr(0xba) # Comment ."\n"); $fh->print(" initial begin\n"); $fh->print(" \$write(\"Hello " .chr(0xe4).chr(0xb8).chr(0x96).chr(0xe7).chr(0x95).chr(0x8c) # World ."\\n\");\n"); $fh->print(" \$write(\"*-* All Finished *-*\\n\");\n"); $fh->print(" \$finish;\n"); $fh->print(" end\n"); $fh->print("endmodule\n"); } top_filename("$Self->{obj_dir}/t_unicode.v"); gen($Self->{top_filename}); compile( ); execute( check_finished => 1, expect => q{Hello \344\270\226\347\225\214.*}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_const_struct_bad.pl0000775000177100017500000000107313702133370023726 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2017 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_concat6.pl0000775000177100017500000000106013702133367021543 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_file_scan_input.dat0000664000177100017500000000000613343101620023532 0ustar wsnyderwsnyder1 2 3 verilator-4.038/test_regress/t/t_lint_multidriven_bad.out0000664000177100017500000000166513702133370023751 0ustar wsnyderwsnyder%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:21:22: Signal has multiple driving blocks with different clocking: 't.mem' t/t_lint_multidriven_bad.v:27:7: ... Location of first driving block 27 | mem[a0] <= d1; | ^~~ t/t_lint_multidriven_bad.v:24:7: ... Location of other driving block 24 | mem[a0] <= d0; | ^~~ ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:22: Signal has multiple driving blocks with different clocking: 'out2' t/t_lint_multidriven_bad.v:35:7: ... Location of first driving block 35 | out2[15:8] <= d0; | ^~~~ t/t_lint_multidriven_bad.v:32:7: ... Location of other driving block 32 | out2[7:0] <= d0; | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_tri_inout2.pl0000775000177100017500000000105313702133370021447 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gate_ormux.pl0000775000177100017500000000134613702133370021530 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{cycles} = ($Self->{benchmark} ? 100_000_000 : 100); $Self->{sim_time} = $Self->{cycles} * 10 + 1000; compile( v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",], verilator_flags2=>["-Wno-UNOPTTHREADS"], ); execute( ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_colonplus_bad.out0000664000177100017500000000046613702133370023423 0ustar wsnyderwsnyder%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:13:25: Perhaps instead of ':+' the intent was '+:'? 13 | output [2:1] z = r[2 :+ 1]; | ^~ ... Use "/* verilator lint_off COLONPLUS */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_ref_trace.out0000664000177100017500000004200713702133370023520 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Wed Dec 4 07:47:51 2019 $end $timescale 1ps $end $scope module top $end $var wire 1 0 clk $end $scope module t $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $scope module a $end $scope module ac1 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $scope module the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $scope module the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module intf_in_sub_all $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $scope module the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end $upscope $end $upscope $end $scope module intf_one $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $upscope $end $scope module intf_two $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end $scope module ac1 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end $scope module the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end $scope module the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module intf_in_sub_all $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end $scope module the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end $upscope $end $upscope $end $scope module intf_one $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $upscope $end $scope module intf_two $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c1 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c2 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module intf_1 $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $upscope $end $scope module intf_2 $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $upscope $end $scope module s1 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope module s2 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b00000000000000000000000000000001 $ b00000000000000000000000001100101 % b00000000000000000000000011001001 & b00000000000000000000000000000010 ' b00000000000000000000000001100110 ( b00000000000000000000000011001010 ) b00000000000000000000001111101001 * b00000000000000000000010001001101 + b00000000000000000000010010110001 , b00000000000000000000001111101010 - b00000000000000000000010001001110 . b00000000000000000000010010110010 / 00 #10 b00000000000000000000000000000001 # b00000000000000000000000000000010 $ b00000000000000000000000001100110 % b00000000000000000000000011001010 & b00000000000000000000000000000011 ' b00000000000000000000000001100111 ( b00000000000000000000000011001011 ) b00000000000000000000001111101010 * b00000000000000000000010001001110 + b00000000000000000000010010110010 , b00000000000000000000001111101011 - b00000000000000000000010001001111 . b00000000000000000000010010110011 / 10 #15 00 #20 b00000000000000000000000000000010 # b00000000000000000000000000000011 $ b00000000000000000000000001100111 % b00000000000000000000000011001011 & b00000000000000000000000000000100 ' b00000000000000000000000001101000 ( b00000000000000000000000011001100 ) b00000000000000000000001111101011 * b00000000000000000000010001001111 + b00000000000000000000010010110011 , b00000000000000000000001111101100 - b00000000000000000000010001010000 . b00000000000000000000010010110100 / 10 #25 00 #30 b00000000000000000000000000000011 # b00000000000000000000000000000100 $ b00000000000000000000000001101000 % b00000000000000000000000011001100 & b00000000000000000000000000000101 ' b00000000000000000000000001101001 ( b00000000000000000000000011001101 ) b00000000000000000000001111101100 * b00000000000000000000010001010000 + b00000000000000000000010010110100 , b00000000000000000000001111101101 - b00000000000000000000010001010001 . b00000000000000000000010010110101 / 10 #35 00 #40 b00000000000000000000000000000100 # b00000000000000000000000000000101 $ b00000000000000000000000001101001 % b00000000000000000000000011001101 & b00000000000000000000000000000110 ' b00000000000000000000000001101010 ( b00000000000000000000000011001110 ) b00000000000000000000001111101101 * b00000000000000000000010001010001 + b00000000000000000000010010110101 , b00000000000000000000001111101110 - b00000000000000000000010001010010 . b00000000000000000000010010110110 / 10 #45 00 #50 b00000000000000000000000000000101 # b00000000000000000000000000000110 $ b00000000000000000000000001101010 % b00000000000000000000000011001110 & b00000000000000000000000000000111 ' b00000000000000000000000001101011 ( b00000000000000000000000011001111 ) b00000000000000000000001111101110 * b00000000000000000000010001010010 + b00000000000000000000010010110110 , b00000000000000000000001111101111 - b00000000000000000000010001010011 . b00000000000000000000010010110111 / 10 #55 00 #60 b00000000000000000000000000000110 # b00000000000000000000000000000111 $ b00000000000000000000000001101011 % b00000000000000000000000011001111 & b00000000000000000000000000001000 ' b00000000000000000000000001101100 ( b00000000000000000000000011010000 ) b00000000000000000000001111101111 * b00000000000000000000010001010011 + b00000000000000000000010010110111 , b00000000000000000000001111110000 - b00000000000000000000010001010100 . b00000000000000000000010010111000 / 10 #65 00 #70 b00000000000000000000000000000111 # b00000000000000000000000000001000 $ b00000000000000000000000001101100 % b00000000000000000000000011010000 & b00000000000000000000000000001001 ' b00000000000000000000000001101101 ( b00000000000000000000000011010001 ) b00000000000000000000001111110000 * b00000000000000000000010001010100 + b00000000000000000000010010111000 , b00000000000000000000001111110001 - b00000000000000000000010001010101 . b00000000000000000000010010111001 / 10 #75 00 #80 b00000000000000000000000000001000 # b00000000000000000000000000001001 $ b00000000000000000000000001101101 % b00000000000000000000000011010001 & b00000000000000000000000000001010 ' b00000000000000000000000001101110 ( b00000000000000000000000011010010 ) b00000000000000000000001111110001 * b00000000000000000000010001010101 + b00000000000000000000010010111001 , b00000000000000000000001111110010 - b00000000000000000000010001010110 . b00000000000000000000010010111010 / 10 #85 00 #90 b00000000000000000000000000001001 # b00000000000000000000000000001010 $ b00000000000000000000000001101110 % b00000000000000000000000011010010 & b00000000000000000000000000001011 ' b00000000000000000000000001101111 ( b00000000000000000000000011010011 ) b00000000000000000000001111110010 * b00000000000000000000010001010110 + b00000000000000000000010010111010 , b00000000000000000000001111110011 - b00000000000000000000010001010111 . b00000000000000000000010010111011 / 10 #95 00 #100 b00000000000000000000000000001010 # b00000000000000000000000000001011 $ b00000000000000000000000001101111 % b00000000000000000000000011010011 & b00000000000000000000000000001100 ' b00000000000000000000000001110000 ( b00000000000000000000000011010100 ) b00000000000000000000001111110011 * b00000000000000000000010001010111 + b00000000000000000000010010111011 , b00000000000000000000001111110100 - b00000000000000000000010001011000 . b00000000000000000000010010111100 / 10 #105 00 #110 b00000000000000000000000000001011 # b00000000000000000000000000001100 $ b00000000000000000000000001110000 % b00000000000000000000000011010100 & b00000000000000000000000000001101 ' b00000000000000000000000001110001 ( b00000000000000000000000011010101 ) b00000000000000000000001111110100 * b00000000000000000000010001011000 + b00000000000000000000010010111100 , b00000000000000000000001111110101 - b00000000000000000000010001011001 . b00000000000000000000010010111101 / 10 #115 00 #120 b00000000000000000000000000001100 # b00000000000000000000000000001101 $ b00000000000000000000000001110001 % b00000000000000000000000011010101 & b00000000000000000000000000001110 ' b00000000000000000000000001110010 ( b00000000000000000000000011010110 ) b00000000000000000000001111110101 * b00000000000000000000010001011001 + b00000000000000000000010010111101 , b00000000000000000000001111110110 - b00000000000000000000010001011010 . b00000000000000000000010010111110 / 10 #125 00 #130 b00000000000000000000000000001101 # b00000000000000000000000000001110 $ b00000000000000000000000001110010 % b00000000000000000000000011010110 & b00000000000000000000000000001111 ' b00000000000000000000000001110011 ( b00000000000000000000000011010111 ) b00000000000000000000001111110110 * b00000000000000000000010001011010 + b00000000000000000000010010111110 , b00000000000000000000001111110111 - b00000000000000000000010001011011 . b00000000000000000000010010111111 / 10 #135 00 #140 b00000000000000000000000000001110 # b00000000000000000000000000001111 $ b00000000000000000000000001110011 % b00000000000000000000000011010111 & b00000000000000000000000000010000 ' b00000000000000000000000001110100 ( b00000000000000000000000011011000 ) b00000000000000000000001111110111 * b00000000000000000000010001011011 + b00000000000000000000010010111111 , b00000000000000000000001111111000 - b00000000000000000000010001011100 . b00000000000000000000010011000000 / 10 #145 00 #150 b00000000000000000000000000001111 # b00000000000000000000000000010000 $ b00000000000000000000000001110100 % b00000000000000000000000011011000 & b00000000000000000000000000010001 ' b00000000000000000000000001110101 ( b00000000000000000000000011011001 ) b00000000000000000000001111111000 * b00000000000000000000010001011100 + b00000000000000000000010011000000 , b00000000000000000000001111111001 - b00000000000000000000010001011101 . b00000000000000000000010011000001 / 10 #155 00 #160 b00000000000000000000000000010000 # b00000000000000000000000000010001 $ b00000000000000000000000001110101 % b00000000000000000000000011011001 & b00000000000000000000000000010010 ' b00000000000000000000000001110110 ( b00000000000000000000000011011010 ) b00000000000000000000001111111001 * b00000000000000000000010001011101 + b00000000000000000000010011000001 , b00000000000000000000001111111010 - b00000000000000000000010001011110 . b00000000000000000000010011000010 / 10 #165 00 #170 b00000000000000000000000000010001 # b00000000000000000000000000010010 $ b00000000000000000000000001110110 % b00000000000000000000000011011010 & b00000000000000000000000000010011 ' b00000000000000000000000001110111 ( b00000000000000000000000011011011 ) b00000000000000000000001111111010 * b00000000000000000000010001011110 + b00000000000000000000010011000010 , b00000000000000000000001111111011 - b00000000000000000000010001011111 . b00000000000000000000010011000011 / 10 #175 00 #180 b00000000000000000000000000010010 # b00000000000000000000000000010011 $ b00000000000000000000000001110111 % b00000000000000000000000011011011 & b00000000000000000000000000010100 ' b00000000000000000000000001111000 ( b00000000000000000000000011011100 ) b00000000000000000000001111111011 * b00000000000000000000010001011111 + b00000000000000000000010011000011 , b00000000000000000000001111111100 - b00000000000000000000010001100000 . b00000000000000000000010011000100 / 10 #185 00 #190 b00000000000000000000000000010011 # b00000000000000000000000000010100 $ b00000000000000000000000001111000 % b00000000000000000000000011011100 & b00000000000000000000000000010101 ' b00000000000000000000000001111001 ( b00000000000000000000000011011101 ) b00000000000000000000001111111100 * b00000000000000000000010001100000 + b00000000000000000000010011000100 , b00000000000000000000001111111101 - b00000000000000000000010001100001 . b00000000000000000000010011000101 / 10 #195 00 #200 b00000000000000000000000000010100 # b00000000000000000000000000010101 $ b00000000000000000000000001111001 % b00000000000000000000000011011101 & b00000000000000000000000000010110 ' b00000000000000000000000001111010 ( b00000000000000000000000011011110 ) b00000000000000000000001111111101 * b00000000000000000000010001100001 + b00000000000000000000010011000101 , b00000000000000000000001111111110 - b00000000000000000000010001100010 . b00000000000000000000010011000110 / 10 #205 00 #210 b00000000000000000000000000010101 # b00000000000000000000000000010110 $ b00000000000000000000000001111010 % b00000000000000000000000011011110 & b00000000000000000000000000010111 ' b00000000000000000000000001111011 ( b00000000000000000000000011011111 ) b00000000000000000000001111111110 * b00000000000000000000010001100010 + b00000000000000000000010011000110 , b00000000000000000000001111111111 - b00000000000000000000010001100011 . b00000000000000000000010011000111 / 10 verilator-4.038/test_regress/t/t_order_first.pl0000775000177100017500000000105313702133370021673 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_randomize_bbox.pl0000775000177100017500000000112313702133370022351 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_randomize.v"); lint( verilator_flags => ["--bbox-unsup"], fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_inconly.pl0000775000177100017500000000105313702133370022037 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_concat4.pl0000775000177100017500000000106013702133367021541 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_const_packed_struct_bad.v0000664000177100017500000000160613702133370025066 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { logic [ 31 : 0 ] a; logic [ 31 : 0 ] b; } params_t; localparam P24 = f_add2(7, 8, 9); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end function integer f_add(input params_t [ 1 : 0 ] params); f_add = params[0].a+params[1].b; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); params_t [ 1 : 0 ] params; params[0] = '{a:a, b:555}; params[1] = '{a:12345, b:b}; f_add2 = f_add(params)+c; endfunction endmodule verilator-4.038/test_regress/t/t_var_in_assign.v0000664000177100017500000000261413702133370022026 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; integer v; reg i; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire oa; // From a of a.v wire oz; // From z of z.v // End of automatics a a (.*); z z (.*); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz); `endif cyc <= cyc + 1; i <= cyc[0]; if (cyc==0) begin v = 3; if (v !== 3) $stop; if (assignin(v) !== 2) $stop; if (v !== 3) $stop; // Make sure V didn't get changed end else if (cyc<10) begin if (cyc==11 && oz!==1'b0) $stop; if (cyc==12 && oz!==1'b1) $stop; if (cyc==12 && oa!==1'b1) $stop; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end function integer assignin(input integer i); i = 2; assignin = i; endfunction endmodule module a (input i, output oa); // verilator lint_off ASSIGNIN assign i = 1'b1; assign oa = i; endmodule module z (input i, output oz); assign oz = i; endmodule verilator-4.038/test_regress/t/t_altera_lpm_ram_dq.pl0000775000177100017500000000120613702133367023022 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_first_b.v0000664000177100017500000000156513702133370021675 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_inst_first_b (/*AUTOARG*/ // Outputs o_seq_d1r, o_com, o2_com, // Inputs clk, i_seq, i_com, i2_com, wide_for_trace, wide_for_trace_2 ); // verilator inline_module input clk; input i_seq; output o_seq_d1r; input i_com; output o_com; input [1:0] i2_com; output [1:0] o2_com; input [127:0] wide_for_trace; input [127:0] wide_for_trace_2; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) // End of automatics reg o_seq_d1r; always @ (posedge clk) begin o_seq_d1r <= ~i_seq; end wire [1:0] o2_com = ~i2_com; wire o_com = ~i_com; endmodule verilator-4.038/test_regress/t/t_flag_f__2.vc0000664000177100017500000000012413666032701021144 0ustar wsnyderwsnyder +define+GOT_DEF1 // -DNON_DEF /* +define+NON_DEF */ +define+GOT_DEF2=1 verilator-4.038/test_regress/t/t_gen_cond_bitrange_bad.v0000664000177100017500000000501713702133370023441 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if" // that should not work. // // The given generate loops should attempt to access invalid bits of mask and // trigger errors. // is defined by SIZE. However since the loop range is larger, this only works // if short-circuited evaluation of the generate loop is in place. // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 3 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Set the parameters, so that we use a size less than MAX_SIZE test_gen #(.SIZE (2), .MASK (2'b11)) i_test_gen (.clk (clk)); // This is only a compilation test, so we can immediately finish always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule // t module test_gen #( parameter SIZE = `MAX_SIZE, MASK = `MAX_SIZE'b0) (/*AUTOARG*/ // Inputs clk ); input clk; // Generate blocks that all have errors in applying short-circuting to // generate "if" conditionals. // Attempt to access invalid bits of MASK in different ways generate genvar g; for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ((g < (SIZE + 1)) && MASK[g]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ((g < SIZE) && MASK[g + 1]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif end end end endgenerate // Attempt to short-circuit bitwise AND generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ((g < (SIZE)) & MASK[g]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif end end end endgenerate // Attempt to short-circuit bitwise OR generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g >= SIZE) | ~MASK[g])) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]); `endif end end end endgenerate endmodule verilator-4.038/test_regress/t/t_enum_overlap_bad.v0000664000177100017500000000055413702133370022507 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); enum { e0, e1, e2, e1b=1 } BAD1; initial begin $stop; end endmodule verilator-4.038/test_regress/t/t_assert_disable_iff.v0000664000177100017500000000247513702133367023027 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Peter Monsson. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; Test test (/*AUTOINST*/ // Inputs .clk (clk)); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test ( input clk ); `ifdef FAIL_ASSERT_1 assert property ( @(posedge clk) disable iff (0) 0 ) else $display("wrong disable"); `endif assert property ( @(posedge clk) disable iff (1) 0 ); assert property ( @(posedge clk) disable iff (1) 1 ); assert property ( @(posedge clk) disable iff (0) 1 ); // // Cover properties behave differently // cover property ( @(posedge clk) disable iff (1) 1 ) $stop; cover property ( @(posedge clk) disable iff (1) 0 ) $stop; cover property ( @(posedge clk) disable iff (0) 1 ) $display("*COVER: ok"); cover property ( @(posedge clk) disable iff (0) 0 ) $stop; endmodule verilator-4.038/test_regress/t/t_assert_cover_off.pl0000775000177100017500000000115113702133367022707 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_cover.v"); compile( v_flags2 => [], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_werror_bad3.out0000664000177100017500000000007513702133370022747 0ustar wsnyderwsnyder%Error: Unknown warning specified: -Werror-NOSUCHERRORASTHIS verilator-4.038/test_regress/t/t_trace_cat_renew.out0000664000177100017500000001745013702133370022677 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sat Feb 23 20:18:07 2013 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # 1$ #1 0$ #2 b00000000000000000000000000000010 # 1$ #3 0$ #4 b00000000000000000000000000000011 # 1$ #5 0$ #6 b00000000000000000000000000000100 # 1$ #7 0$ #8 b00000000000000000000000000000101 # 1$ #9 0$ #10 b00000000000000000000000000000110 # 1$ #11 0$ #12 b00000000000000000000000000000111 # 1$ #13 0$ #14 b00000000000000000000000000001000 # 1$ #15 0$ #16 b00000000000000000000000000001001 # 1$ #17 0$ #18 b00000000000000000000000000001010 # 1$ #19 0$ #20 b00000000000000000000000000001011 # 1$ #21 0$ #22 b00000000000000000000000000001100 # 1$ #23 0$ #24 b00000000000000000000000000001101 # 1$ #25 0$ #26 b00000000000000000000000000001110 # 1$ #27 0$ #28 b00000000000000000000000000001111 # 1$ #29 0$ #30 b00000000000000000000000000010000 # 1$ #31 0$ #32 b00000000000000000000000000010001 # 1$ #33 0$ #34 b00000000000000000000000000010010 # 1$ #35 0$ #36 b00000000000000000000000000010011 # 1$ #37 0$ #38 b00000000000000000000000000010100 # 1$ #39 0$ #40 b00000000000000000000000000010101 # 1$ #41 0$ #42 b00000000000000000000000000010110 # 1$ #43 0$ #44 b00000000000000000000000000010111 # 1$ #45 0$ #46 b00000000000000000000000000011000 # 1$ #47 0$ #48 b00000000000000000000000000011001 # 1$ #49 0$ #50 b00000000000000000000000000011010 # 1$ #51 0$ #52 b00000000000000000000000000011011 # 1$ #53 0$ #54 b00000000000000000000000000011100 # 1$ #55 0$ #56 b00000000000000000000000000011101 # 1$ #57 0$ #58 b00000000000000000000000000011110 # 1$ #59 0$ #60 b00000000000000000000000000011111 # 1$ #61 0$ #62 b00000000000000000000000000100000 # 1$ #63 0$ #64 b00000000000000000000000000100001 # 1$ #65 0$ #66 b00000000000000000000000000100010 # 1$ #67 0$ #68 b00000000000000000000000000100011 # 1$ #69 0$ #70 b00000000000000000000000000100100 # 1$ #71 0$ #72 b00000000000000000000000000100101 # 1$ #73 0$ #74 b00000000000000000000000000100110 # 1$ #75 0$ #76 b00000000000000000000000000100111 # 1$ #77 0$ #78 b00000000000000000000000000101000 # 1$ #79 0$ #80 b00000000000000000000000000101001 # 1$ #81 0$ #82 b00000000000000000000000000101010 # 1$ #83 0$ #84 b00000000000000000000000000101011 # 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1$ #125 0$ #126 b00000000000000000000000001000000 # 1$ #127 0$ #128 b00000000000000000000000001000001 # 1$ #129 0$ #130 b00000000000000000000000001000010 # 1$ #131 0$ #132 b00000000000000000000000001000011 # 1$ #133 0$ #134 b00000000000000000000000001000100 # 1$ #135 0$ #136 b00000000000000000000000001000101 # 1$ #137 0$ #138 b00000000000000000000000001000110 # 1$ #139 0$ #140 b00000000000000000000000001000111 # 1$ #141 0$ #142 b00000000000000000000000001001000 # 1$ #143 0$ #144 b00000000000000000000000001001001 # 1$ #145 0$ #146 b00000000000000000000000001001010 # 1$ #147 0$ #148 b00000000000000000000000001001011 # 1$ #149 0$ #150 b00000000000000000000000001001100 # 1$ #151 0$ #152 b00000000000000000000000001001101 # 1$ #153 0$ #154 b00000000000000000000000001001110 # 1$ #155 0$ #156 b00000000000000000000000001001111 # 1$ #157 0$ #158 b00000000000000000000000001010000 # 1$ #159 0$ #160 b00000000000000000000000001010001 # 1$ #161 0$ #162 b00000000000000000000000001010010 # 1$ #163 0$ #164 b00000000000000000000000001010011 # 1$ #165 0$ #166 b00000000000000000000000001010100 # 1$ #167 0$ #168 b00000000000000000000000001010101 # 1$ #169 0$ #170 b00000000000000000000000001010110 # 1$ #171 0$ #172 b00000000000000000000000001010111 # 1$ #173 0$ #174 b00000000000000000000000001011000 # 1$ #175 0$ #176 b00000000000000000000000001011001 # 1$ #177 0$ #178 b00000000000000000000000001011010 # 1$ #179 0$ #180 b00000000000000000000000001011011 # 1$ #181 0$ #182 b00000000000000000000000001011100 # 1$ #183 0$ #184 b00000000000000000000000001011101 # 1$ #185 0$ #186 b00000000000000000000000001011110 # 1$ #187 0$ #188 b00000000000000000000000001011111 # 1$ #189 0$ #190 b00000000000000000000000001100000 # 1$ #191 0$ #192 b00000000000000000000000001100001 # 1$ #193 0$ #194 b00000000000000000000000001100010 # 1$ #195 0$ #196 b00000000000000000000000001100011 # 1$ #197 0$ #198 b00000000000000000000000001100100 # 1$ #199 0$ #200 b00000000000000000000000001100101 # 1$ #201 0$ #202 b00000000000000000000000001100110 # 1$ #203 0$ #204 b00000000000000000000000001100111 # 1$ #205 0$ #206 b00000000000000000000000001101000 # 1$ #207 0$ #208 b00000000000000000000000001101001 # 1$ #209 0$ #210 b00000000000000000000000001101010 # 1$ #211 0$ #212 b00000000000000000000000001101011 # 1$ #213 0$ #214 b00000000000000000000000001101100 # 1$ #215 0$ #216 b00000000000000000000000001101101 # 1$ #217 0$ #218 b00000000000000000000000001101110 # 1$ #219 0$ #220 b00000000000000000000000001101111 # 1$ #221 0$ #222 b00000000000000000000000001110000 # 1$ #223 0$ #224 b00000000000000000000000001110001 # 1$ #225 0$ #226 b00000000000000000000000001110010 # 1$ #227 0$ #228 b00000000000000000000000001110011 # 1$ #229 0$ #230 b00000000000000000000000001110100 # 1$ #231 0$ #232 b00000000000000000000000001110101 # 1$ #233 0$ #234 b00000000000000000000000001110110 # 1$ #235 0$ #236 b00000000000000000000000001110111 # 1$ #237 0$ #238 b00000000000000000000000001111000 # 1$ #239 0$ #240 b00000000000000000000000001111001 # 1$ #241 0$ #242 b00000000000000000000000001111010 # 1$ #243 0$ #244 b00000000000000000000000001111011 # 1$ #245 0$ #246 b00000000000000000000000001111100 # 1$ #247 0$ #248 b00000000000000000000000001111101 # 1$ #249 0$ #250 b00000000000000000000000001111110 # 1$ #251 0$ #252 b00000000000000000000000001111111 # 1$ #253 0$ #254 b00000000000000000000000010000000 # 1$ #255 0$ #256 b00000000000000000000000010000001 # 1$ #257 0$ #258 b00000000000000000000000010000010 # 1$ #259 0$ #260 b00000000000000000000000010000011 # 1$ #261 0$ #262 b00000000000000000000000010000100 # 1$ #263 0$ #264 b00000000000000000000000010000101 # 1$ #265 0$ #266 b00000000000000000000000010000110 # 1$ #267 0$ #268 b00000000000000000000000010000111 # 1$ #269 0$ #270 b00000000000000000000000010001000 # 1$ #271 0$ #272 b00000000000000000000000010001001 # 1$ #273 0$ #274 b00000000000000000000000010001010 # 1$ #275 0$ #276 b00000000000000000000000010001011 # 1$ #277 0$ #278 b00000000000000000000000010001100 # 1$ #279 0$ #280 b00000000000000000000000010001101 # 1$ #281 0$ #282 b00000000000000000000000010001110 # 1$ #283 0$ #284 b00000000000000000000000010001111 # 1$ #285 0$ #286 b00000000000000000000000010010000 # 1$ #287 0$ #288 b00000000000000000000000010010001 # 1$ #289 0$ #290 b00000000000000000000000010010010 # 1$ #291 0$ #292 b00000000000000000000000010010011 # 1$ #293 0$ #294 b00000000000000000000000010010100 # 1$ #295 0$ #296 b00000000000000000000000010010101 # 1$ #297 0$ #298 b00000000000000000000000010010110 # 1$ #299 0$ verilator-4.038/test_regress/t/t_time_vpi_10ms10ns.pl0000775000177100017500000000151313702133370022530 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator_st => 1); top_filename("t/t_time_vpi.v"); $Self->{main_time_multiplier} = 10e-3 / 10e-9; compile( v_flags2 => ['+define+time_scale_units=10ms +define+time_scale_prec=10ns', 't/t_time_vpi_c.cpp'], verilator_flags2 => ['--vpi'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_dtree_inla.pl0000775000177100017500000000123013702133370022511 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_A'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_wide.pl0000775000177100017500000000105313702133370021314 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_shortcircuit.pl0000775000177100017500000000144213702133370022731 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug413 short circuit"); compile( # Amazingly VCS, NC and Verilator all just accept the C file here! v_flags2 => ["t/t_dpi_shortcircuit_c.cpp"], verilator_flags2 => ["-Wno-DECLFILENAME"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_castdyn.pl0000775000177100017500000000130613702133367021025 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); # #file_grep_not("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/Dead/x); ok(1); 1; verilator-4.038/test_regress/t/t_math_concat0.pl0000775000177100017500000000105313702133370021711 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_order_quad.v0000664000177100017500000000077213702133370021334 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug 762 module t(a0, y); input [3:0] a0; output [44:0] y; assign y[40] = 0; assign y[30] = 0; // verilator lint_off UNOPTFLAT assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 }; endmodule verilator-4.038/test_regress/t/t_array_interface.pl0000775000177100017500000000105313702133367022515 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_setout_bad.v0000664000177100017500000000120513702133370022356 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire reset_l, input wire clk ); sub sub_I ( .clk(clk), .reset_l(reset_l), .cpu_if_timeout(1'b0) ); endmodule module sub ( input wire clk, reset_l, output reg cpu_if_timeout ); always @(posedge clk) begin if (!reset_l) begin cpu_if_timeout <= 1'b0; end else begin cpu_if_timeout <= 1'b0; end end endmodule verilator-4.038/test_regress/t/t_param_concat.v0000664000177100017500000000120213702133370021623 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter UNSIZED = 10; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_var_dup3.pl0000775000177100017500000000077313702133370021104 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( ); ok(1); 1; verilator-4.038/test_regress/t/t_math_trig.pl0000775000177100017500000000105313702133370021327 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_timescale.cpp0000664000177100017500000000367213702133370021474 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } #include #define FILENM "t_timescale.cpp" #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } int main(int argc, char** argv, char** env) { VM_PREFIX* top = new VM_PREFIX("top"); CHECK_RESULT(VL_TIME_STR_CONVERT("100s"), 2); CHECK_RESULT(VL_TIME_STR_CONVERT("10s"), 1); CHECK_RESULT(VL_TIME_STR_CONVERT("1s"), 0); CHECK_RESULT(VL_TIME_STR_CONVERT("100ms"), -1); CHECK_RESULT(VL_TIME_STR_CONVERT("10ms"), -2); CHECK_RESULT(VL_TIME_STR_CONVERT("1ms"), -3); CHECK_RESULT(VL_TIME_STR_CONVERT("100us"), -4); CHECK_RESULT(VL_TIME_STR_CONVERT("10us"), -5); CHECK_RESULT(VL_TIME_STR_CONVERT("1us"), -6); CHECK_RESULT(VL_TIME_STR_CONVERT("100ns"), -7); CHECK_RESULT(VL_TIME_STR_CONVERT("10ns"), -8); CHECK_RESULT(VL_TIME_STR_CONVERT("1ns"), -9); CHECK_RESULT(VL_TIME_STR_CONVERT("100ps"), -10); CHECK_RESULT(VL_TIME_STR_CONVERT("10ps"), -11); CHECK_RESULT(VL_TIME_STR_CONVERT("1ps"), -12); CHECK_RESULT(VL_TIME_STR_CONVERT("100fs"), -13); CHECK_RESULT(VL_TIME_STR_CONVERT("10fs"), -14); CHECK_RESULT(VL_TIME_STR_CONVERT("1fs"), -15); CHECK_RESULT(VL_TIME_STR_CONVERT("1.5s"), 0); CHECK_RESULT(VL_TIME_STR_CONVERT("1s "), 0); CHECK_RESULT(VL_TIME_STR_CONVERT("1ss"), 0); CHECK_RESULT(VL_TIME_STR_CONVERT("s"), 0); CHECK_RESULT(VL_TIME_STR_CONVERT(0), 0); top->final(); printf("*-* All Finished *-*\n"); return 0; } verilator-4.038/test_regress/t/t_param_shift.pl0000775000177100017500000000105313702133370021646 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_synth_full.vlt0000664000177100017500000000041413702133367023316 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config full_case -file "t/t_assert_synth.v" -lines 32 verilator-4.038/test_regress/t/t_inside.v0000664000177100017500000000530313702133370020455 0ustar wsnyderwsnyder// DESCRIPTION::Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); typedef enum logic [1:0] { ZERO = 2'd0, ONE = 2'd1, TWO = 2'd2, THREE = 2'd3, XXX = 2'dx } num_t; function automatic logic is_odd; input en; input num_t number; case (en) 1'b1: begin unique if (number inside {ONE, THREE}) is_odd = 1'b1; else if (number inside {ZERO, TWO}) is_odd = 1'b0; else is_odd = 1'bx; end 1'b0: is_odd = 1'bx; default: is_odd = 1'bx; endcase endfunction function automatic bit is_00_to_04 (input byte value); return value inside { [ 8'h0 : 8'h04 ] }; endfunction function automatic bit is_fe_to_ff (input byte value); return value inside { [ 8'hfe : 8'hff ] }; endfunction initial begin `checkh ((4'd4 inside {4'd1,4'd5}), 1'b0); `checkh ((4'd4 inside {4'd1,4'd4}), 1'b1); // `checkh ((4'b1011 inside {4'b1001}), 1'b0); `checkh ((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==? `checkh ((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==? `checkh ((4'b1001 inside {4'b1??1}), 1'b1); `ifndef VERILATOR `checkh ((4'b1z11 inside {4'b11?1, 4'b1011}),1'bx); `endif // Range `checkh ((4'd4 inside {[4'd5:4'd3], [4'd10:4'd8]}), 1'b0); // If left of colon < never matches `checkh ((4'd3 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); `checkh ((4'd4 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); `checkh ((4'd5 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); // // Unsupported $ bound // // Unsupported if unpacked array, elements tranversed //int unpackedarray [$] = '{8,9}; //( expr inside {2, 3, unpackedarray}) // { 2,3,8,9} // `checkh (is_odd(1'b1, ZERO), 1'd0); `checkh (is_odd(1'b1, ONE), 1'd1); `checkh (is_odd(1'b1, TWO), 1'd0); `checkh (is_odd(1'b1, THREE),1'd1); `ifndef VERILATOR `checkh (is_odd(1'b1, XXX), 1'dx); `endif // // Should not give UNSIGNED/CMPCONST warnings // (Verilator converts to 8'h00 >= 8'h00 which is always true) `checkh(is_00_to_04(8'h00), 1'b1); `checkh(is_00_to_04(8'h04), 1'b1); `checkh(is_00_to_04(8'h05), 1'b0); `checkh(is_fe_to_ff(8'hfd), 1'b0); `checkh(is_fe_to_ff(8'hfe), 1'b1); `checkh(is_fe_to_ff(8'hff), 1'b1); // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_gen12.pl0000775000177100017500000000106013702133370022303 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_merge_cond.v0000664000177100017500000001522313702133370021306 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); $stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc= 64'h5aef0c8d_d70a4497; reg [63:0] prev_crc; always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; prev_crc <= crc; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end wire cond2 = &crc[1:0]; wire cond3 = &crc[2:0]; reg shuf_q [63:0]; always @(posedge clk) begin reg bits [63:0]; reg shuf_a [63:0]; reg shuf_b [63:0]; reg shuf_c [63:0]; reg shuf_d [63:0]; reg shuf_e [63:0]; // Unpack these to test core algorithm for (int i = 0; i < 64; i = i + 1) begin bits[i] = crc[i]; end for (int i = 0; i < 64; i = i + 1) begin shuf_a[i] = cyc[0] ? bits[i] : bits[63-i]; end if (cyc[1]) begin for (int i = 0; i < 64; i = i + 1) begin shuf_b[i] = cyc[0] ? bits[i] : bits[63-i]; end end else begin for (int i = 0; i < 64; i = i + 1) begin shuf_b[i] = cyc[0] ? bits[63-i] : bits[i]; end end // Also test merge under clean/bit extract for (int i = 0; i < 64; i = i + 1) begin shuf_c[i] = cyc[0] ? crc[i] : crc[63-i]; end // Merge with 'cond & value', 'value & cond', or 'cond' shuf_d[0] = cond2 ? bits[0] : bits[63]; for (int i = 1; i < 32; i = i + 2) begin shuf_d[i] = cond2 & bits[i]; end for (int i = 2; i < 32; i = i + 2) begin shuf_d[i] = bits[i] & cond2; end for (int i = 32; i < 64; i = i + 1) begin shuf_d[i] = cond2; end // Merge with an '&' also used for masking of LSB. shuf_e[0] = cond3 ? bits[0] : bits[63]; for (int i = 1; i < 64; i = i + 1) begin shuf_e[i] = cond3 & crc[0]; end // Also delayed.. for (int i = 0; i < 64; i = i + 1) begin shuf_q[i] <= cyc[0] ? crc[i] : crc[63-i]; end // Check results if (cyc[0]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[63-i]); end if (cyc[0] ~^ cyc[1]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[63-i]); end if (cyc[0]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[63-i]); end if (cond2) begin `check(shuf_d[0], crc[0]); for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], crc[i]); for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd1); end else begin `check(shuf_d[0], crc[63]); for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], 1'b0); for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd0); end if (cond3) begin `check(shuf_e[0], crc[0]); for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], crc[0]); end else begin `check(shuf_e[0], crc[63]); for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], 1'b0); end if (cyc > 0) begin if (~cyc[0]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[63-i]); end if (((cyc - 1) >> 1) % 2 == 1) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[63-i]); end end if (cyc[2]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[63-i]); end end // Generated always reg shuf_g [63:0]; generate for (genvar i = 0 ; i < 64; i = i + 1) always @(posedge clk) begin shuf_g[i] <= cyc[1] ? crc[i] : crc[63-i]; end endgenerate // Generated assign wire shuf_w [63:0]; generate for (genvar i = 0 ; i < 64; i = i + 1) assign shuf_w[i] = cyc[2] ? crc[i] : crc[63-i]; endgenerate // Things not to merge always @(posedge clk) begin reg bits [63:0]; reg x; reg y; reg z; reg w; // Unpack these to test core algorithm for (int i = 0; i < 64; i = i + 1) begin bits[i] = crc[i]; end // Do not merge if condition appears in an LVALUE x = bits[0]; y = x ? bits[2] : bits[1]; x = x ? bits[3] : bits[4]; x = x ? bits[5] : bits[6]; `check(x, (bits[0] ? bits[3] : bits[4]) ? bits[5] : bits[6]); `check(y, bits[0] ? bits[2] : bits[1]); // However do merge when starting a new list in the same block with the // previous condition variable, but without the condition being an LVALUE x = cond2 ? bits[0] : bits[1]; y = cond2 & bits[2]; z = cond2 & bits[3]; w = cond2 & bits[4]; `check(x, cond2 ? bits[0] : bits[1]); `check(y, cond2 & bits[2]); `check(z, cond2 & bits[3]); `check(w, cond2 & bits[4]); // Do not merge if condition is not a pure expression $c("int _cnt = 0;"); x = $c("_cnt++") ? bits[0] : bits[1]; y = $c("_cnt++") ? bits[2] : bits[3]; z = $c("_cnt++") ? bits[4] : bits[5]; w = $c("_cnt++") ? bits[6] : bits[7]; $c("if (_cnt != 4) abort();"); `check(x, bits[1]); `check(y, bits[2]); `check(z, bits[4]); `check(w, bits[6]); // Do not merge with assignment under other statement x = cond2 ? bits[0] : bits[1]; if (bits[1]) begin y = cond2 ? bits[2] : bits[3]; end `check(x, cond2 ? bits[0] : bits[1]); if (bits[1]) begin `check(y, cond2 ? bits[2] : bits[3]); end // Do not merge with assignment under other statement x = cond2 ? bits[0] : bits[1]; if (bits[1]) begin y = cond2 & bits[2]; end `check(x, cond2 ? bits[0] : bits[1]); if (bits[1]) begin `check(y, cond2 & bits[2]); end end endmodule verilator-4.038/test_regress/t/t_func_void.v0000664000177100017500000000143713702133370021162 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; int side_effect; function int f1; input int in; f1 = in + 1; side_effect += in + 1; endfunction initial begin int got; side_effect = 1; // got = f1(10); if (got != 11) $stop; if (side_effect != 12) $stop; // verilator lint_off IGNOREDRETURN f1(20); // verilator lint_on IGNOREDRETURN if (side_effect != 33) $stop; // void'(f1(30)); if (side_effect != 64) $stop; // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_langext_order.v0000664000177100017500000000057613702133370022046 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD module t(input do); t_langext_order_sub sub (.do(do)); endmodule verilator-4.038/test_regress/t/t_gated_clk_1.v0000664000177100017500000000275713702133370021351 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test of gated clock detection // // The code as shown generates a result by a delayed assignment from PC. The // creation of the result is from a clock gated from the clock that sets // PC. Howevever since they are essentially the same clock, the result should // be delayed by one cycle. // // Standard Verilator treats them as different clocks, so the result stays in // step with the PC. An event drive simulator always allows the clock to win. // // The problem is caused by the extra loop added by Verilator to the // evaluation of all internally generated clocks (effectively removed by // marking the clock enable). // // This test is added to facilitate experiments with solutions. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett . // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg gated_clk_en = 1'b0 ; reg [1:0] pc = 2'b0; reg [1:0] res = 2'b0; wire gated_clk = gated_clk_en & clk; always @(posedge clk) begin pc <= pc + 1; gated_clk_en <= 1'b1; end always @(posedge gated_clk) begin res <= pc; end always @(posedge clk) begin if (pc == 2'b11) begin // Correct behaviour is that res should be lagging pc in the count // by one cycle if (res == 2'b10) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end end endmodule verilator-4.038/test_regress/t/t_var_port2_bad.out0000664000177100017500000000052113702133370022265 0ustar wsnyderwsnyder%Error: t/t_var_port2_bad.v:7:11: Input/output/inout declaration not found for port: 'portwithoin' 7 | module t (portwithoin); | ^~~~~~~~~~~ %Error: t/t_var_port2_bad.v:8:10: Input/output/inout does not appear in port list: 'portwithin' 8 | input portwithin; | ^~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_sys_plusargs.v0000664000177100017500000000570213702133370021743 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer p_i; // signal type IData reg [15:0] p_s; // signal type SData reg [7:0] p_c; // signal type CData real p_r; // signal type double reg [7*8:1] p_str; string sv_str; reg [7*8:1] p_in; string sv_in; initial begin if ($test$plusargs("PLUS")!==1) $stop; if ($test$plusargs("PLUSNOT")!==0) $stop; if ($test$plusargs("PL")!==1) $stop; //if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer if ($test$plusargs("NOTTHERE")!==0) $stop; p_i = 10; if ($value$plusargs("NOTTHERE%d", p_i)!==0) $stop; if (p_i !== 10) $stop; p_i = 0; if ($value$plusargs("INT=%d", p_i)!==1) $stop; if (p_i !== 32'd1234) $stop; p_i = 0; if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also if (p_i !== 32'h1234) $stop; p_i = 0; // Check octal and WIDTH if (!$value$plusargs("INT=%o", p_i)) $stop; if (p_i !== 32'o1234) $stop; // Check handling of 'SData' type signals (Issue #1592) p_s = 0; if (!$value$plusargs("INT=%d", p_s)) $stop; if (p_s !== 16'd1234) $stop; // Check handling of 'CData' type signals (Issue #1592) p_c = 0; if (!$value$plusargs("INT=%d", p_c)) $stop; if (p_c !== 8'd210) $stop; // Check handling of 'double' type signals (Issue #1619) p_r = 0; if (!$value$plusargs("REAL=%e", p_r)) $stop; $display("r='%e'", p_r); if (p_r !== 1.2345) $stop; p_r = 0; if (!$value$plusargs("REAL=%f", p_r)) $stop; $display("r='%f'", p_r); if (p_r !== 1.2345) $stop; p_r = 0; if (!$value$plusargs("REAL=%g", p_r)) $stop; $display("r='%g'", p_r); if (p_r !== 1.2345) $stop; p_str = "none"; if ($value$plusargs("IN%s", p_str)!==1) $stop; $display("str='%s'",p_str); if (p_str !== "T=1234") $stop; sv_str = "none"; if ($value$plusargs("IN%s", sv_str)!==1) $stop; $display("str='%s'",sv_str); if (sv_str != "T=1234") $stop; sv_str = "none"; $value$plusargs("IN%s", sv_str); $display("str='%s'",sv_str); if (sv_str != "T=1234") $stop; p_in = "IN%s"; `ifdef VERILATOR p_in = $c(p_in); // Prevent constant propagation `endif sv_str = "none"; if ($value$plusargs(p_in, sv_str)!==1) $stop; $display("str='%s'",sv_str); if (sv_str != "T=1234") $stop; sv_in = "INT=%d"; `ifdef VERILATOR if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation `endif p_i = 0; if ($value$plusargs(sv_in, p_i)!==1) $stop; $display("i='%d'",p_i); if (p_i !== 32'd1234) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_rnd.pl0000775000177100017500000000105313702133370020134 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_auto1.pl0000775000177100017500000000105313702133367021403 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dos.v0000775000177100017500000000075413702133370017777 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // This file has DOS carrage returns in it! module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule // This file has DOS carrage returns in it! verilator-4.038/test_regress/t/t_altera_lpm_or.pl0000775000177100017500000000120613702133367022177 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_primitive_fst.pl0000775000177100017500000000117113702133370023414 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_primitive.v"); compile( v_flags2 => ["--trace-fst"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_ref_bad2.v0000664000177100017500000000114313702133370021514 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH module t(/*AUTOARG*/); task checkset(const ref int bad_const_set); bad_const_set = 32'h4567; // Bad setting const endtask task checkset2(ref int int_ref); endtask initial begin int i; byte bad_non_int; checkset(i); checkset2(bad_non_int); // Type mismatch end endmodule verilator-4.038/test_regress/t/t_dedupe_clk_gate.v0000664000177100017500000000260413702133370022302 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Dedupe optimization test. // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Varun Koyyalagunta, Centaur Technology. module t(res,d,clk,en); output res; input d,en,clk; wire q0,q1,q2,q3; flop_gated_latch f0(q0,d,clk,en); flop_gated_latch f1(q1,d,clk,en); flop_gated_flop f2(q2,d,clk,en); flop_gated_flop f3(q3,d,clk,en); assign res = (q0 + q1) * (q2 - q3); endmodule module flop_gated_latch(q,d,clk,en); input d, clk, en; output reg q; wire gated_clock; clock_gate_latch clock_gate(gated_clock, clk, en); always @(posedge gated_clock) begin q <= d; end endmodule module flop_gated_flop(q,d,clk,en); input d, clk, en; output reg q; wire gated_clock; clock_gate_flop clock_gate(gated_clock, clk, en); always @(posedge gated_clock) begin q <= d; end endmodule module clock_gate_latch (gated_clk, clk, clken); output gated_clk; input clk, clken; reg clken_latched; assign gated_clk = clk & clken_latched ; wire clkb = ~clk; always @(clkb or clken) if(clkb) clken_latched = clken; endmodule module clock_gate_flop (gated_clk, clk, clken); output gated_clk; input clk, clken; reg clken_r /*verilator clock_enable*/; assign gated_clk = clk & clken_r ; always @(negedge clk) clken_r <= clken; endmodule verilator-4.038/test_regress/t/t_pp_misdef_bad.out0000664000177100017500000000063713702133370022325 0ustar wsnyderwsnyder%Error: t/t_pp_misdef_bad.v:11:4: Define or directive not defined: '`NDEFINED' : ... Suggested alternative: '`DEFINED' 11 | `NDEFINED | ^~~~~~~~~ %Error: t/t_pp_misdef_bad.v:14:6: Define or directive not defined: '`imescale' : ... Suggested alternative: '`timescale' 14 | `imescale | ^~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_iff.out0000664000177100017500000000053113702133370020306 0ustar wsnyderwsnyder%Error: t/t_iff.v:64:15: syntax error, unexpected iff, expecting ')' or ',' or or 64 | always @(d iff enable == 1) begin | ^~~ %Error: t/t_iff.v:69:35: syntax error, unexpected iff, expecting ')' 69 | assert property (@(posedge clk iff enable) | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_dpi_string.pl0000775000177100017500000000112513702133370021513 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["t/t_dpi_string_c.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_for_count.v0000664000177100017500000000466213702133370021207 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; integer j; reg [63:0] cam_lookup_hit_vector; integer hit_count; always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin hit_count = 0; for (j=0; j < 64; j=j+1) begin hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]}; end end integer hit_count2; always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin hit_count2 = 0; for (j=63; j >= 0; j=j-1) begin hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]}; end end integer hit_count3; always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin hit_count3 = 0; for (j=63; j > 0; j=j-1) begin if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1; end end reg [127:0] wide_for_index; reg [31:0] wide_for_count; always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin wide_for_count = 0; for (wide_for_index = 128'hff_00000000_00000000; wide_for_index < 128'hff_00000000_00000100; wide_for_index = wide_for_index + 2) begin wide_for_count = wide_for_count+32'h1; end end // While loop integer w; initial begin while (w<10) w=w+1; if (w!=10) $stop; while (w<20) begin w=w+2; end while (w<20) begin w=w+99999; end // NEVER if (w!=20) $stop; end // Do-While loop integer dw; initial begin do dw=dw+1; while (dw<10); if (dw!=10) $stop; do dw=dw+2; while (dw<20); if (dw!=20) $stop; do dw=dw+5; while (dw<20); // Once if (dw!=25) $stop; end always @ (posedge clk) begin cam_lookup_hit_vector <= 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin cam_lookup_hit_vector <= 64'h00010000_00010000; end if (cyc==2) begin if (hit_count != 32'd2) $stop; if (hit_count2 != 32'd2) $stop; if (hit_count3 != 32'd2) $stop; cam_lookup_hit_vector <= 64'h01010010_00010001; end if (cyc==3) begin if (hit_count != 32'd5) $stop; if (hit_count2 != 32'd5) $stop; if (hit_count3 != 32'd4) $stop; if (wide_for_count != 32'h80) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_func_const3_bad.pl0000775000177100017500000000113113702133370022400 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2017 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( v_flags2 => ["--lint-only"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_topmodule.pl0000775000177100017500000000111213702133370022346 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( v_flags2 => ["--top-module b "], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_width_genfor.v0000664000177100017500000000143213702133370022706 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs rc, rg, ri, rp ); parameter P = 15; output reg [3:0] rc; output reg [3:0] rg; output reg [3:0] ri; output reg [3:0] rp; for (genvar g=0; g < 15; ++g) begin // bug1487 // This isn't a width violation, as genvars are generally 32 bits initial begin rg = g; rp = P; rc = 1; end end initial begin for (integer i=0; i < 15; ++i) begin /* verilator lint_off WIDTH */ ri = i; /* verilator lint_on WIDTH */ end end endmodule verilator-4.038/test_regress/t/t_interface_down_inlbd.pl0000775000177100017500000000125513702133370023514 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_B +define+INLINE_D'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_declfilename.v0000664000177100017500000000046013702133370022637 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; t_lint_declfilename sub (); endmodule module t_lint_declfilename; endmodule verilator-4.038/test_regress/t/t_altera_lpm_counter.pl0000775000177100017500000000120613702133367023236 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_prot_lib_unpacked_bad.out0000664000177100017500000000071713702133370024042 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_prot_lib_unpacked_bad.v:7:28: Unsupported: unpacked arrays with protect-lib on 'unpacked_in' 7 | input unpacked_in [7:0], | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_prot_lib_unpacked_bad.v:8:28: Unsupported: unpacked arrays with protect-lib on 'unpacked_out' 8 | output unpacked_out [7:0]); | ^~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_restore_prag_bad.out0000664000177100017500000000027713702133370024101 0ustar wsnyderwsnyder%Error: t/t_lint_restore_prag_bad.v:10:4: /*verilator lint_restore*/ without matching save 10 | /*verilator lint_restore*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_array_pattern_packed.pl0000775000177100017500000000105313702133367023541 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clocker.out0000664000177100017500000000401313702133367021171 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Fri Jun 22 19:23:24 2018 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $var wire 1 % res $end $var wire 16 ' res16 [15:0] $end $var wire 8 & res8 [7:0] $end $scope module $unit $end $var wire 32 + ID_MSB [31:0] $end $upscope $end $scope module t $end $var wire 1 $ clk $end $var wire 8 ( clkSet [7:0] $end $var wire 1 $ clk_1 $end $var wire 3 ) clk_3 [2:0] $end $var wire 4 * clk_4 [3:0] $end $var wire 1 $ clk_final $end $var wire 8 # count [7:0] $end $var wire 1 % res $end $var wire 16 ' res16 [15:0] $end $var wire 8 & res8 [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000 # 0$ 0% b00000000 & b0000000000000000 ' b00000000 ( b000 ) b0000 * b00000000000000000000000000000001 + #10 b00000001 # 1$ 1% b11101111 & b0000000111111111 ' b11111111 ( b111 ) b1111 * #15 b00000010 # 0$ 0% b00000000 & b0000001000000000 ' b00000000 ( b000 ) b0000 * #20 b00000011 # 1$ 1% b11101111 & b0000001111111111 ' b11111111 ( b111 ) b1111 * #25 b00000100 # 0$ 0% b00000000 & b0000010000000000 ' b00000000 ( b000 ) b0000 * #30 b00000101 # 1$ 1% b11101111 & b0000010111111111 ' b11111111 ( b111 ) b1111 * #35 b00000110 # 0$ 0% b00000000 & b0000011000000000 ' b00000000 ( b000 ) b0000 * #40 b00000111 # 1$ 1% b11101111 & b0000011111111111 ' b11111111 ( b111 ) b1111 * #45 b00001000 # 0$ 0% b00000000 & b0000100000000000 ' b00000000 ( b000 ) b0000 * #50 b00001001 # 1$ 1% b11101111 & b0000100111111111 ' b11111111 ( b111 ) b1111 * #55 b00001010 # 0$ 0% b00000000 & b0000101000000000 ' b00000000 ( b000 ) b0000 * #60 b00001011 # 1$ 1% b11101111 & b0000101111111111 ' b11111111 ( b111 ) b1111 * #65 b00001100 # 0$ 0% b00000000 & b0000110000000000 ' b00000000 ( b000 ) b0000 * #70 b00001101 # 1$ 1% b11101111 & b0000110111111111 ' b11111111 ( b111 ) b1111 * #75 b00001110 # 0$ 0% b00000000 & b0000111000000000 ' b00000000 ( b000 ) b0000 * #80 b00001111 # 1$ 1% b11101111 & b0000111111111111 ' b11111111 ( b111 ) b1111 * verilator-4.038/test_regress/t/t_mod_interface_array3.pl0000775000177100017500000000110213702133370023424 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlt_syntax_bad.v0000664000177100017500000000002413702133370022216 0ustar wsnyderwsnydermodule t; endmodule verilator-4.038/test_regress/t/t_vgen.pl0000775000177100017500000000144513702133370020315 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if (eval "use Bit::Vector; return 2;" != 2) { skip("Vgen test requires Bit::Vector"); } else { top_filename("$Self->{obj_dir}/vgen.v"); run(cmd => ["./vgen.pl", "-o $Self->{top_filename}", #"--seed 0", ]); compile( ); execute( check_finished => 1, ); } ok(1); 1; verilator-4.038/test_regress/t/t_alw_splitord.v0000664000177100017500000000766213702133367021725 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [15:0] m_din; // OK reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5; always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops c_split_1 <= 16'h0; c_split_2 <= 16'h0; c_split_3 <= 16'h0; c_split_4 <= 0; c_split_5 <= 0; // End of automatics end else begin c_split_1 <= m_din; c_split_2 <= c_split_1; c_split_3 <= c_split_2 & {16{(cyc!=0)}}; if (cyc==1) begin c_split_4 <= 16'h4; c_split_5 <= 16'h5; end else begin c_split_4 <= c_split_3; c_split_5 <= c_split_4; end end end // OK reg [15:0] d_split_1, d_split_2; always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops d_split_1 <= 16'h0; d_split_2 <= 16'h0; // End of automatics end else begin d_split_1 <= m_din; d_split_2 <= d_split_1; d_split_1 <= ~m_din; end end // Not OK always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops // End of automatics end else begin $write(" foo %x", m_din); $write(" bar %x\n", m_din); end end // Not OK reg [15:0] e_split_1, e_split_2; always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops e_split_1 = 16'h0; e_split_2 = 16'h0; // End of automatics end else begin e_split_1 = m_din; e_split_2 = e_split_1; end end // Not OK reg [15:0] f_split_1, f_split_2; always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops f_split_1 = 16'h0; f_split_2 = 16'h0; // End of automatics end else begin f_split_2 = f_split_1; f_split_1 = m_din; end end always @ (posedge clk) begin if (cyc!=0) begin //$write(" C %d %x %x\n", cyc, c_split_1, c_split_2); cyc<=cyc+1; if (cyc==1) begin m_din <= 16'hfeed; end if (cyc==3) begin end if (cyc==4) begin m_din <= 16'he11e; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; end if (cyc==5) begin m_din <= 16'he22e; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; end if (cyc==6) begin m_din <= 16'he33e; if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop; if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; end if (cyc==7) begin m_din <= 16'he44e; if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop; end if (cyc==8) begin m_din <= 16'he55e; if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e && c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_sys_readmem_bad_digit.mem0000664000177100017500000000053413702133370024012 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 a0 verilator-4.038/test_regress/t/t_pp_pragma_bad.pl0000775000177100017500000000114713702133370022131 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["-E -Wpedantic"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_recurse_bad2.v0000664000177100017500000000040613702133370022565 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum foo_t { A = 'b0, B = 'b1 } foo_t; verilator-4.038/test_regress/t/t_inst_signed.v0000664000177100017500000000320713702133370021511 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; wire signed [7:0] sgn_wide; wire [7:0] unsgn_wide; // The instantiation will Z extend, not sign extend // verilator lint_off WIDTH sub sub (.clk, .sgn(sgn_wide), .unsgn(unsgn_wide), .iss(3'sh7), .isu(3'h7), .ius(3'sh7), .iuu(3'h7)); // verilator lint_on WIDTH always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide); `endif if (sgn_wide[2:0] != 3'sh7) $stop; if (unsgn_wide[2:0] != 3'h7) $stop; // Simulators differ here. if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC && sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS if (unsgn_wide !== 8'sbzzzzz111 && unsgn_wide!== 8'sb00000111) $stop; cyc <= cyc + 1; if (cyc==3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub ( input clk, output wire signed [2:0] sgn, output wire [2:0] unsgn, input signed [7:0] iss, input signed [7:0] isu, input [7:0] ius, input [7:0] iuu); assign sgn = 3'sh7; assign unsgn = 3'h7; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("in: %x %x %x %x\n", iss, isu, ius, iuu); if (iss != 8'hff) $stop; if (isu != 8'h07) $stop; if (ius != 8'hff) $stop; if (iuu != 8'h07) $stop; `endif end endmodule verilator-4.038/test_regress/t/t_var_set_link.v0000664000177100017500000000107013702133370021657 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs state, // Inputs clk ); input clk; // Gave "Internal Error: V3Broken.cpp:: Broken link in node" output [1:0] state; reg [1:0] state = 2'b11; always @ (posedge clk) begin state <= state; end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_array_rev.v0000664000177100017500000000231313702133367021200 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Geoff Barrett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; // verilator lint_off LITENDIAN logic arrd [0:1] = '{ 1'b1, 1'b0 }; // verilator lint_on LITENDIAN logic y0, y1; logic localbkw [1:0]; arr_rev arr_rev_u ( .arrbkw (arrd), .y0(y0), .y1(y1) ); always @ (posedge clk) begin if (arrd[0] != 1'b1) $stop; if (arrd[1] != 1'b0) $stop; localbkw = arrd; `ifdef TEST_VERBOSE $write("localbkw[0]=%b\n", localbkw[0]); $write("localbkw[1]=%b\n", localbkw[1]); `endif if (localbkw[0] != 1'b0) $stop; if (localbkw[1] != 1'b1) $stop; `ifdef TEST_VERBOSE $write("y0=%b\n", y0); $write("y1=%b\n", y1); `endif if (y0 != 1'b0) $stop; if (y1 != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module arr_rev ( input var logic arrbkw [1:0], output var logic y0, output var logic y1 ); always_comb y0 = arrbkw[0]; always_comb y1 = arrbkw[1]; endmodule verilator-4.038/test_regress/t/t_tri_public.v0000664000177100017500000000334213702133370021337 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Unsupported tristate construct error // // This is a compile only regression test of tristate handling for bug514 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Rob Stoddard. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs out, // Inputs data, up_down, clk, reset ); //----------Output Ports-------------- output [7:0] out; //------------Input Ports-------------- //input [7:0] data ; input [7:0] data; input up_down, clk, reset; //------------Internal Variables-------- reg [7:0] out; logic [7:0] q_out; //-------------Code Starts Here------- always @(posedge clk) if (reset) begin // active high reset out <= 8'b0 ; end else if (up_down) begin out <= out + 1; end else begin out <= q_out; end // verilator lint_off PINMISSING sub_mod sub_mod ( .clk(clk), .data(data), .reset(reset), .q(q_out) ); // verilator lint_on PINMISSING endmodule module sub_mod (/*AUTOARG*/ // Outputs q, test_out, // Inouts test_inout, // Inputs data, clk, reset ); //-----------Input Ports--------------- input [7:0] data /*verilator public*/; input clk, reset; inout test_inout; // Get rid of this, the problem goes away. //-----------Output Ports--------------- output [7:0] q; output test_out; // Not assigned, no problem. logic [7:0] que; // Uncomment this line, the error goes away. //assign test_inout = que; assign q = que; always @ ( posedge clk) if (~reset) begin que <= 8'b0; end else begin que <= data; end endmodule verilator-4.038/test_regress/t/t_display_signed_noopt.pl0000775000177100017500000000136013702133370023567 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_display_signed.v"); $Self->{golden_filename} = "t/t_display_signed.out"; # Match unopt version compile( verilator_flags2 => ["-O0"], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_unpacked.pl0000775000177100017500000000105313702133370022547 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_new_bad.v0000664000177100017500000000131713702133367021775 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsNoArg; int imembera; function new(); imembera = 5; endfunction endclass class ClsNoNew; int imembera; endclass class ClsArg; int imembera; function new(int i); imembera = i + 1; endfunction endclass module t (/*AUTOARG*/); initial begin ClsNoArg c1; ClsNoNew c2; ClsArg c3; c1 = new(3); // Bad, called with arg c2 = new(3); // Bad, called with arg c3 = new(); // Bad, called without arg $stop; end endmodule verilator-4.038/test_regress/t/t_func_const_packed_struct_bad2.out0000664000177100017500000000200613702133370025505 0ustar wsnyderwsnyder%Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_struct_bad2.v:20:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t t/t_func_const_packed_struct_bad2.v:31:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_packed_struct_bad2.v:43:16: ... Called from f_add() with parameters: params = [0 = '{a: 32'h7, foo: 6'hb, sub_params: '{b: 32'h37, bar: 8'h6f}}, 1 = '{a: 32'h3039, foo: 6'hc, sub_params: '{b: 32'h8, bar: 8'h70}}] t/t_func_const_packed_struct_bad2.v:20:21: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 20 | localparam P24 = f_add2(7, 8, 9); | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_case_huge_prof.pl0000775000177100017500000000314413702133367022333 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_case_huge.v"); if ($ENV{VERILATOR_TEST_NO_GPROF}) { skip("Skipping due to VERILATOR_TEST_NO_GPROF"); } else { dotest(); } ok(1); sub dotest { compile( verilator_flags2 => ["--stats --prof-cfuncs -CFLAGS '-pg' -LDFLAGS '-pg'"], ); file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10); file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 10); unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); setenv('GMON_OUT_PREFIX', "$Self->{obj_dir}/gmon.out"); execute( check_finished => 1, ); my $gmon_path; $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); $gmon_path or error("Profiler did not create a gmon.out"); (my $gmon_base = $gmon_path) =~ s!.*[/\\]!!; run(cmd => ["cd $Self->{obj_dir} && gprof $Self->{VM_PREFIX} $gmon_base > gprof.out"], check_finished => 0); run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_profcfunc gprof.out > cfuncs.out"], check_finished => 0); file_grep("$Self->{obj_dir}/cfuncs.out", qr/Overall summary by/); } 1; verilator-4.038/test_regress/t/t_math_signed7.pl0000775000177100017500000000105313702133370021722 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_bad_range3.v0000664000177100017500000000100513702133370022521 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs outwires, // Inputs inwires ); input [7:0] inwires [12:10]; output wire [7:0] outwires [12:10]; assign outwires[10] = inwires[11]; assign outwires[11] = inwires[12]; assign outwires[12] = inwires[13]; // must be an error here endmodule verilator-4.038/test_regress/t/t_const_overflow_bad.out0000664000177100017500000000224613702133367023434 0ustar wsnyderwsnyder%Error: t/t_const_overflow_bad.v:9:34: Too many digits for 94 bit number: 94'd123456789012345678901234567890 9 | parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_const_overflow_bad.v:11:31: Too many digits for 8 bit number: 8'habc 11 | parameter [200:0] SMALLH = 8'habc; | ^~~~~~ %Error: t/t_const_overflow_bad.v:12:31: Too many digits for 6 bit number: 6'o1234 12 | parameter [200:0] SMALLO = 6'o1234; | ^~~~~~~ %Error: t/t_const_overflow_bad.v:13:31: Too many digits for 3 bit number: 3'b1111 13 | parameter [200:0] SMALLB = 3'b1111; | ^~~~~~~ %Error: t/t_const_overflow_bad.v:19:35: Too many digits for 129 bit number: 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d 19 | parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_gen8.v0000664000177100017500000000223313702133370022062 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); logic val; function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t(); //intf #(.PARAM(1)) my_intf [1:0] (); intf #(.PARAM(1)) my_intf (); generate genvar the_genvar; for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf //assign my_intf[the_genvar].val = '1; //t1 t (.mod_intf(my_intf[the_genvar])); t1 t (.mod_intf(my_intf)); end endgenerate // t1 t (.mod_intf(my_intf[1])); // generate // begin : TestIf // assign my_intf[1].val = '1; // t1 t (.mod_intf(my_intf[1])); // end // endgenerate // generate // begin // assign my_intf[0].val = '1; // t1 t (.mod_intf(my_intf[0])); // end // endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_case_write1.pl0000775000177100017500000000130213702133367021562 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats --O3 -x-assign fast"], ); execute( check_finished => 1, ); files_identical("$Self->{obj_dir}/$Self->{name}_logger.log", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_param_local.v0000664000177100017500000000105713702133370021456 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs a, y ); input [1:0] a; output [3:0] y; Test #(.C(2)) test (.*); endmodule module Test #(C = 3, localparam O = 1 << C) (input [C-1:0] a, output reg [O-1:0] y); initial begin if (O != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_for_init_bug.v0000664000177100017500000000146113702133370021651 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs priority_mask, // Inputs muxed_requests ); parameter ARW = 7; // verilator lint_off UNOPTFLAT integer i,j; output reg [ARW-1:0] priority_mask; input [ARW-1:0] muxed_requests; always @* begin for (i=ARW-1;i>0;i=i-1) begin priority_mask[i]=1'b0; // vvvv=== note j=j not j=i; was bug for( j=j;j>=0;j=j-1) priority_mask[i]=priority_mask[j] | muxed_requests[j]; end //Bit zero is always enabled priority_mask[0]=1'b0; end endmodule // Local Variables: // verilog-auto-inst-param-value: t // End: verilator-4.038/test_regress/t/t_bitsel_const_bad.v0000664000177100017500000000077513702133367022516 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test of select from constant // // This tests issue 508, bit select of constant fails // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Note that if we declare "wire [0:0] b", this works just fine. wire a; wire b; assign b = 1'b0; assign a = b[0]; // IEEE illegal can't extract scalar endmodule verilator-4.038/test_regress/t/t_dpi_result_type.pl0000775000177100017500000000255013702133370022567 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if ($Self->{nc}) { # For NC, compile twice, first just to generate DPI headers compile( nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] ); } compile( v_flags2 => ["t/t_dpi_result_type.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], # NC: Gdd the obj_dir to the C include path nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", "-ccflags -I$Self->{obj_dir}"], ); if ($Self->{vlt_all}) { files_identical( "$Self->{obj_dir}/Vt_dpi_result_type__Dpi.h", "t/t_dpi_result_type__Dpi.out" ); } execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ms_pli => 0 ); ok(1); 1; verilator-4.038/test_regress/t/t_math_pow5.v0000664000177100017500000000330413702133370021104 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [67:0] q; reg signed [67:0] qs; initial begin q = 68'he_12345678_9abcdef0 ** 68'h3; if (q != 68'hcee3cb96ce96cf000) $stop; // q = 68'he_12345678_9abcdef0 ** 68'h5_6789abcd_ef012345; if (q != 68'h0) $stop; // qs = 68'she_12345678_9abcdef0 ** 68'sh3; if (qs != 68'shcee3cb96ce96cf000) $stop; // qs = 68'she_12345678_9abcdef0 ** 68'sh5_6789abcd_ef012345; if (qs != 68'h0) $stop; end reg [67:0] left; reg [67:0] right; wire [67:0] outu = left ** right; wire signed [67:0] outs = $signed(left) ** $signed(right); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%d %x %x %x %x\n", cyc, left, right, outu, outs); `endif if (cyc==1) begin left <= 68'h1; right <= '0; end if (cyc==2) begin if (outu != 68'h1) $stop; if (outs != 68'h1) $stop; end if (cyc==3) begin left <= 68'he_12345678_9abcdef0; right <= 68'h3; end if (cyc==4) begin if (outu != 68'hcee3cb96ce96cf000) $stop; if (outs != 68'hcee3cb96ce96cf000) $stop; end if (cyc==5) begin left <= 68'he_12345678_9abcdef0; right <= 68'h5_6789abcd_ef012345; end if (cyc==6) begin if (outu != 68'h0) $stop; if (outs != 68'h0) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_trace_dumporder_bad.out0000664000177100017500000000011613702133370023526 0ustar wsnyderwsnyder%Warning: $dumpvar ignored as not proceeded by $dumpfile *-* All Finished *-* verilator-4.038/test_regress/t/t_func_const_bad.out0000664000177100017500000000644213702133370022520 0ustar wsnyderwsnyder%Error: t/t_func_const_bad.v:12:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_output' : ... In instance t t/t_func_const_bad.v:13:64: ... Location of non-constant VAR 'o': Language violation: Outputs/refs not allowed in constant functions 12 | localparam B1 = f_bad_output(1,2); | ^~~~~~~~~~~~ %Error: t/t_func_const_bad.v:21:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_dotted' : ... In instance t t/t_func_const_bad.v:23:24: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions t/t_func_const_bad.v:21:20: ... Called from f_bad_dotted() with parameters: a = ?32?h2 21 | localparam B2 = f_bad_dotted(2); | ^~~~~~~~~~~~ %Error: t/t_func_const_bad.v:28:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_nonparam' : ... In instance t t/t_func_const_bad.v:30:24: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable t/t_func_const_bad.v:28:20: ... Called from f_bad_nonparam() with parameters: a = ?32?h3 28 | localparam B3 = f_bad_nonparam(3); | ^~~~~~~~~~~~~~ %Error: t/t_func_const_bad.v:36:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_infinite' : ... In instance t t/t_func_const_bad.v:38:7: ... Location of non-constant WHILE: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024 t/t_func_const_bad.v:36:20: ... Called from f_bad_infinite() with parameters: a = ?32?h3 36 | localparam B4 = f_bad_infinite(3); | ^~~~~~~~~~~~~~ %Error: t/t_func_const_bad.v:44:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_stop' : ... In instance t t/t_func_const_bad.v:46:7: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_bad.v:44:23: ... Called from f_bad_stop() with parameters: a = ?32?h3 44 | localparam BSTOP = f_bad_stop(3); | ^~~~~~~~~~ -Info: "Printing in loop: 0" -Info: "Printing in loop: 1" -Info: "Printing in loop: 2" %Warning-USERFATAL: "Fatal Error" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_bad.v:50:24: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal' : ... In instance t t/t_func_const_bad.v:55:7: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_bad.v:50:24: ... Called from f_bad_fatal() with parameters: a = ?32?h3 50 | localparam BFATAL = f_bad_fatal(3); | ^~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_inst_tree_inl0_pub0.vlt0000664000177100017500000000036413702133370023410 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config no_inline -module "l*" verilator-4.038/test_regress/t/t_display_real_noopt.pl0000775000177100017500000000135413702133370023244 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_display_real.v"); $Self->{golden_filename} = "t/t_display_real.out"; # Match unopt version compile( verilator_flags2 => ["-O0"], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_write1.out0000664000177100017500000001674713343101620021762 0ustar wsnyderwsnyder[2] crc=0000000000000097 1410 [3] crc=000000000000012e 1410 [4] crc=000000000000025d 1410 [5] crc=00000000000004ba 1410 [6] crc=0000000000000974 1410 [7] crc=00000000000012e9 1410 [8] crc=00000000000025d3 1410 [9] crc=0000000000004ba7 1410 [10] crc=000000000000974e 1410 [11] crc=0000000000012e9d 1410 [12] crc=0000000000025d3a 1410 [13] crc=000000000004ba74 1410 [14] crc=00000000000974e9 1410 [15] crc=000000000012e9d3 1410 [16] crc=000000000025d3a7 1410 [17] crc=00000000004ba74e 1410 [18] crc=0000000000974e9d 1410 [19] crc=00000000012e9d3a 1410 [20] crc=00000000025d3a74 1410 [21] crc=0000000004ba74e9 1410 [22] crc=000000000974e9d3 1304a:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002031303039;17 1304b:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002031303039203233 1304c:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020313030392032332031333033;4 1304d:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002031303039203233203133303320313338 1304e:203130303920323320313330332031333820202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020 1304: 1009 23 1303 138 [23] crc=0000000012e9d3a7 1313: 1009 46 1309 1311 143 1312 [24] crc=0000000025d3a74e 1129: 1009 172 407 175 408 409 410 1106 [25] crc=000000004ba74e9d 1017: 1009 223 1014 880 885 1015 1016 1007 [26] crc=00000000974e9d3a 1231: 1229 967 1230 718 [27] crc=000000012e9d3a74 1410 [28] crc=000000025d3a74e9 1370: 1009 58 1369 19 [29] crc=00000004ba74e9d3 1036: 1009 194 1033 1034 1008 1035 880 [30] crc=0000000974e9d3a7 1409:i [31] crc=00000012e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [32] crc=00000025d3a74e9d 1383:§ [33] crc=0000004ba74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [34] crc=000000974e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [35] crc=0000012e9d3a74e9 1231: 1228 979 1230 713 [36] crc=0000025d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [37] crc=000004ba74e9d3a7 1409:i [38] crc=00000974e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [39] crc=000012e9d3a74e9d 1383:§ [40] crc=000025d3a74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [41] crc=00004ba74e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [42] crc=0000974e9d3a74e9 1231: 1228 979 1230 713 [43] crc=00012e9d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [44] crc=00025d3a74e9d3a7 1409:i [45] crc=0004ba74e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [46] crc=000974e9d3a74e9d 1383:§ [47] crc=0012e9d3a74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [48] crc=0025d3a74e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [49] crc=004ba74e9d3a74e9 1231: 1228 979 1230 713 [50] crc=00974e9d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [51] crc=012e9d3a74e9d3a7 1409:i [52] crc=025d3a74e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [53] crc=04ba74e9d3a74e9d 1383:§ [54] crc=0974e9d3a74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [55] crc=12e9d3a74e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [56] crc=25d3a74e9d3a74e9 1231: 1228 979 1230 713 [57] crc=4ba74e9d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [58] crc=974e9d3a74e9d3a7 1409:i [59] crc=2e9d3a74e9d3a74f 1321: 1009 29 1320 137 144 141 138 149 [60] crc=5d3a74e9d3a74e9e 1383:§ [61] crc=ba74e9d3a74e9d3d 1021: 1009 216 1018 882 884 1019 1020 1007 [62] crc=74e9d3a74e9d3a7b 1017: 1009 197 1014 882 883 1015 1016 1008 [63] crc=e9d3a74e9d3a74f7 1231: 1228 979 1230 713 [64] crc=d3a74e9d3a74e9ef 1013: 1009 194 1011 1006 1008 1012 880 [65] crc=a74e9d3a74e9d3df 1409:i [66] crc=4e9d3a74e9d3a7bf 1321: 1009 29 1320 137 144 141 145 149 [67] crc=9d3a74e9d3a74f7e 1383:§ [68] crc=3a74e9d3a74e9efc 1021: 1009 216 1018 882 884 1019 1020 1007 [69] crc=74e9d3a74e9d3df9 1017: 1009 197 1014 882 883 1015 1016 1008 [70] crc=e9d3a74e9d3a7bf3 1231: 1228 979 1230 713 [71] crc=d3a74e9d3a74f7e6 1013: 1009 194 1011 1006 1008 1012 880 [72] crc=a74e9d3a74e9efcc 1409:i [73] crc=4e9d3a74e9d3df98 1321: 1009 29 1320 137 147 149 143 142 [74] crc=9d3a74e9d3a7bf30 1383:§ [75] crc=3a74e9d3a74f7e61 1021: 1009 216 1018 882 885 1019 1020 1007 [76] crc=74e9d3a74e9efcc3 1017: 1009 197 1014 882 884 1015 1016 1008 [77] crc=e9d3a74e9d3df987 1231: 1228 982 1230 713 [78] crc=d3a74e9d3a7bf30f 1013: 1009 194 1011 1006 1008 1012 881 885 [79] crc=a74e9d3a74f7e61f 1409:w [80] crc=4e9d3a74e9efcc3f 1321: 1009 30 1320 149 146 146 137 149 [81] crc=9d3a74e9d3df987e 1383:ß [82] crc=3a74e9d3a7bf30fc 1021: 1009 225 1018 882 885 1019 1020 1008 [83] crc=74e9d3a74f7e61f9 1017: 1009 218 1014 882 884 1015 1016 1008 [84] crc=e9d3a74e9efcc3f3 1231: 1228 981 1230 708 [85] crc=d3a74e9d3df987e6 1013: 1009 232 1011 1005 1008 1012 881 883 [86] crc=a74e9d3a7bf30fcc 1409:s [87] crc=4e9d3a74f7e61f98 1262: 1009 1006 1258 846 1259 1006 1260 833 1261 [88] crc=9d3a74e9efcc3f30 1321: 1009 124 1320 146 137 149 137 134 [89] crc=3a74e9d3df987e61 1383:˜ [90] crc=74e9d3a7bf30fcc3 1036: 1009 215 1033 1034 1008 1035 879 verilator-4.038/test_regress/t/t_typedef_array.pl0000775000177100017500000000105313702133370022207 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_interface_noinl.pl0000775000177100017500000000115413702133367023716 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_array_interface.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_signed.pl0000775000177100017500000000105313702133370021633 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_extern.out0000664000177100017500000000027213702133367022244 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_extern.v:11:15: Unsupported: Out of class block function declaration 11 | function void Cls::extfunc(); | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_pkg_colon_bad.pl0000775000177100017500000000107413702133370023163 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_cond_const.v0000664000177100017500000000251613702133370022167 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test for generate IF constants // // The given generate loop should have a constant expression as argument. This // test checks it really does evaluate as constant. // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 4 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Set the parameters, so that we use a size less than MAX_SIZE test_gen #(.SIZE (2), .MASK (4'b1111)) i_test_gen (.clk (clk)); // This is only a compilation test, but for good measure we do one clock // cycle. integer count; initial begin count = 0; end always @(posedge clk) begin if (count == 1) begin $write("*-* All Finished *-*\n"); $finish; end else begin count = count + 1; end end endmodule // t module test_gen #( parameter SIZE = `MAX_SIZE, MASK = `MAX_SIZE'b0) (/*AUTOARG*/ // Inputs clk ); input clk; // Generate blocks that rely on short-circuiting of the logic to avoid // errors. generate if ((SIZE < 8'h04) && MASK[0]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Generate IF MASK[0] = %d\n", MASK[0]); `endif end end endgenerate endmodule verilator-4.038/test_regress/t/t_gen_lsb.v0000664000177100017500000000413013702133370020610 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] datai = crc[3:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [3:0] datao; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .datao (datao[3:0]), // Inputs .clk (clk), .datai (datai[3:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, datao}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3db7bc8bfe61f983 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input logic clk, input logic [3:0] datai, output logic [3:0] datao ); genvar i; parameter SIZE = 4; logic [SIZE:1][3:0] delay; always_ff @(posedge clk) begin delay[1][3:0] <= datai; end generate for (i = 2; i < (SIZE+1); i++) begin always_ff @(posedge clk) begin delay[i][3:0] <= delay[i-1][3:0]; end end endgenerate always_comb datao = delay[SIZE][3:0]; endmodule verilator-4.038/test_regress/t/t_mem_multi_io3.v0000664000177100017500000000317713702133370021753 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. // SPDX-License-Identifier: CC0-1.0 module t ( input logic clk, input logic daten, input logic [8:0] datval, output logic signed [3:0][3:0][35:0] datao ); logic signed [3:0][3:0][3:0][8:0] datat; genvar i; generate for (i=0; i<4; i++)begin testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i])); end endgenerate genvar j; generate for (i=0; i<4; i++) begin for (j=0; j<4; j++) begin always_comb datat[i][j][0] = daten ? 9'h0 : datval; always_comb datat[i][j][1] = daten ? 9'h1 : datval; always_comb datat[i][j][2] = daten ? 9'h2 : datval; always_comb datat[i][j][3] = daten ? 9'h3 : datval; end end endgenerate endmodule module testio ( input clk, input logic signed [3:0] [3:0] [8:0] arr3d_in, output logic signed [3:0] [35:0] arr2d_out ); logic signed [3:0] [35:0] ar2d_out_pre; always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; always_ff @(posedge clk) begin if (clk) arr2d_out <= ar2d_out_pre; end endmodule verilator-4.038/test_regress/t/t_clk_first.v0000664000177100017500000001107613702133367021174 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, fastclk ); input clk; input fastclk; reg reset_l; int cyc; initial reset_l = 0; always @ (posedge clk) begin if (cyc==0) reset_l <= 1'b1; else if (cyc==1) reset_l <= 1'b0; else if (cyc==10) reset_l <= 1'b1; end t_clk t (/*AUTOINST*/ // Inputs .clk (clk), .fastclk (fastclk), .reset_l (reset_l)); endmodule module t_clk (/*AUTOARG*/ // Inputs clk, fastclk, reset_l ); input clk; input fastclk; input reset_l; // surefire lint_off STMINI // surefire lint_off CWECSB // surefire lint_off NBAJAM reg _ranit; initial _ranit=0; // surefire lint_off UDDSMX reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT wire [7:0] clk_clocks_d1r; wire [7:0] clk_clocks_d1sr; wire [7:0] clk_clocks_cp2_d1r; wire [7:0] clk_clocks_cp2_d1sr; // verilator lint_off MULTIDRIVEN reg [7:0] int_clocks; initial int_clocks = 0; // verilator lint_on MULTIDRIVEN reg [7:0] int_clocks_copy; // verilator lint_off GENCLK reg internal_clk; initial internal_clk = 0; reg reset_int_; // verilator lint_on GENCLK always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] CLK1 %x\n", $time, reset_l); `endif if (!reset_l) begin clk_clocks <= 0; int_clocks <= 0; internal_clk <= 1'b1; reset_int_ <= 0; end else begin internal_clk <= ~internal_clk; if (!_ranit) begin _ranit <= 1; `ifdef TEST_VERBOSE $write("[%0t] t_clk: Running\n",$time); `endif reset_int_ <= 1; end end end reg [7:0] sig_rst; always @ (posedge clk or negedge reset_l) begin `ifdef TEST_VERBOSE $write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst); `endif if (!reset_l) begin sig_rst <= 0; end else begin sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB end end always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst); `endif if (!reset_l) begin clk_clocks <= 0; end else begin clk_clocks <= clk_clocks + 8'd1; if (clk_clocks == 4) begin if (sig_rst !== 4) $stop; if (clk_clocks_d1r !== 3) $stop; if (int_clocks !== 2) $stop; if (int_clocks_copy !== 2) $stop; if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop; if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop; $write("*-* All Finished *-*\n"); $finish; end end end reg [7:0] resetted; always @ (posedge clk or negedge reset_int_) begin `ifdef TEST_VERBOSE $write("[%0t] CLK4 %x\n", $time, reset_l); `endif if (!reset_int_) begin resetted <= 0; end else begin resetted <= resetted + 8'd1; end end always @ (int_clocks) begin int_clocks_copy = int_clocks; end always @ (negedge internal_clk) begin int_clocks <= int_clocks + 8'd1; end t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks), .q(clk_clocks_d1r), .q2(clk_clocks_d1sr)); t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks), .q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr)); t_clk_two two (/*AUTOINST*/ // Inputs .fastclk (fastclk), .reset_l (reset_l)); endmodule module t_clk_flop (/*AUTOARG*/ // Outputs q, q2, // Inputs clk, clk2, a ); parameter WIDTH=8; input clk; input clk2; input [(WIDTH-1):0] a; output [(WIDTH-1):0] q; output [(WIDTH-1):0] q2; reg [(WIDTH-1):0] q; reg [(WIDTH-1):0] q2; always @ (posedge clk) q<=a; always @ (posedge clk2) q2<=a; endmodule module t_clk_two (/*AUTOARG*/ // Inputs fastclk, reset_l ); input fastclk; input reset_l; // verilator lint_off GENCLK reg clk2; // verilator lint_on GENCLK reg [31:0] count; t_clk_twob tb (.*); wire reset_h = ~reset_l; always @ (posedge fastclk) begin if (reset_h) clk2 <= 0; else clk2 <= ~clk2; end always @ (posedge clk2) begin if (reset_h) count <= 0; else count <= count + 1; end endmodule module t_clk_twob (/*AUTOARG*/ // Inputs fastclk, reset_l ); input fastclk; input reset_l; always @ (posedge fastclk) begin // Extra line coverage point, just to make sure coverage // hierarchy under inlining lands properly if (reset_l) ; end endmodule verilator-4.038/test_regress/t/t_sys_readmem_assoc.v0000664000177100017500000000156013702133370022703 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; reg [5:0] assoc_c[int]; reg [95:0] assoc_w[int]; initial begin assoc_c[300] = 10; // See if clearing must happen first $readmemb("t/t_sys_readmem_b.mem", assoc_c); $display("assoc_c=%p", assoc_c); $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_c_b.mem"}, assoc_c); $readmemb("t/t_sys_readmem_b.mem", assoc_w); // Not conditional with TEST_VERBOSE as found bug with wide display $display("assoc_w=%p", assoc_w); $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_w_h.mem"}, assoc_w); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_dpi_display.pl0000775000177100017500000000120713702133370021653 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["t/t_dpi_display_c.cpp"], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_package_param.pl0000775000177100017500000000105313702133370022124 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen8_noinl.pl0000775000177100017500000000116013702133370023430 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen8.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_queue_bounded.v0000664000177100017500000000167113702133370022032 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); int q[$ : 2]; // Shall not go higher than [2], i.e. size 3 initial begin q.push_front(3); if (q.size() != 1) $stop; q.push_front(2); if (q.size() != 2) $stop; q.push_front(1); if (q.size() != 3) $stop; q.push_front(0); if (q.size() != 3) $stop; if (q[0] != 0) $stop; if (q[1] != 1) $stop; if (q[2] != 2) $stop; q.delete(); q.push_back(0); q.push_back(1); q.push_back(2); if (q.size() != 3) $stop; q.push_back(3); if (q.size() != 3) $stop; if (q[0] != 0) $stop; if (q[1] != 1) $stop; if (q[2] != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_v.pl0000775000177100017500000000105313702133370020631 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_wide.out0000664000177100017500000000753313702133370022230 0ustar wsnyderwsnyder[1000] cyc==99 crc=2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1ba7ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc [1000] cyc==99 crc=001010010110000110010010011011101101110111100011111001011100011000000001100010111110100101110000110011011011111100110010011110110111001010110101111100111100010111101010101101000010100110010101100010010001000000000101111011101100100001110110011111100101111111011111000000110000010100011110110110111110100111010010001000101110111001110101011011101110001101001101100011010110110010000011111011101000011101111010101011010110010111000100100001110001010000001010110010000111110100100110110001100011011010100110011000100001010010110100101001101001101011001010110110010010010011000101011010001100110010001110100011000111100111111001011111010000011110100110111011101101111110010001000000010001100100011001110100001110001111001101110110100101001000010101111011100101100011001001010000101111011011000100110111101010010010001011001111110011100010101011110001110111101111110100011111100100111101101101011010101000010110011111110011000101101101011101010001101110110010011101001011110110101001011011111101111011100101111000101100011011101001111100101000010101110100000111000100111010001011101011000001101010110111100001010101110000110001001110001110100001001011011011011010000111011000100101111011101111100011011111111010111100101101000000100101011010101101001011110111111111111001111001110000010010100110001111011000001001001100000111101001011110111101110111001110100110010000110010101110000101010111100011111001010100110111101011100010001100101000110100001010111111010110100111111111101100110001011111001011110011111000010110010110100101100111001101101110010001011110010111000110001010001011010001000111001001110101010101111100010100110101101001111101000000101100000001111001000001111111001011011100110011010110101000100001110010101001101011101001111000011101101110110001101000010011010110101000111010111100001011100000101010101000110001110011001010011011100010011000110100000010100010010110001001110011110111101111111000100001101111101010101000110100100011100001000100010110010110110111000111000100100011001111000111000000100101110001010010010100001010100101101000101101110111000010101011011100101101101110010000101100000011110110001100000001000101111110111000100001001000000101011001110111110101010001001010001110100011101111110000011000110010011010011011111000001010101000010001110101010101000001111111010111001000101100110010100010110111011000001010011011011111100111100011111110111110001001110110111110101010110110001110101011011110111000010010011001000100001110101101001111111001100111010101100101011011000100101101000010101110010100010100101100100000011010010011001010011000101001011000011001000010101000000111011100011000111110011010101101111110101010001100011001100101011101011111011111111000110100001110001110111010011101111101100110010010001000110101101100111101010110100100111000000001010110100111111111111001101110010111101010001100010011110100100011101011110110111111110000100011011001011110011010111100101001001101110100111011101001101011111111000111111010000101000011110111110010001110001010000100001011000111000101111010000111011000010110101001011101111010000000110011111101010110010011111100 *-* All Finished *-* verilator-4.038/test_regress/t/t_sys_plusargs.pl0000775000177100017500000000122713702133370022112 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ['-v', 't/t_flag_libinc.v'], ); execute( check_finished => 1, all_run_flags => ['+PLUS +INT=1234 +STRSTR +REAL=1.2345'], ); ok(1); 1; verilator-4.038/test_regress/t/t_class_virtual_pure.pl0000775000177100017500000000107113702133367023265 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_multi_io2_sc.pl0000775000177100017500000000132013702133370022574 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_mem_multi_io2.v"); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io2.cpp --sc -Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_clog2.pl0000775000177100017500000000105313702133370021370 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_version.pl0000775000177100017500000000254313702133370022034 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); foreach my $prog ( # See also t_flag_help.pl "../bin/verilator", "../bin/verilator_coverage", #"../bin/verilator_difftree", #"../bin/verilator_gantt", #"../bin/verilator_profcfunc", ) { run(fails => 0, cmd => ["perl", $prog, "--version"], tee => $self->{verbose}, logfile => "$Self->{obj_dir}/t_help.log", expect => qr/^Verilator/, verilator_run => 1, ); run(fails => 0, cmd => ["perl", $prog, "-V"], tee => $self->{verbose}, logfile => "$Self->{obj_dir}/t_help.log", expect => qr/^Verilator/, verilator_run => 1, ); run(fails => 0, cmd => ["perl", $prog, "-V"], logfile => "$Self->{obj_dir}/t_help.log", expect => qr/^Verilator/, verilator_run => 1, ); } ok(1); 1; verilator-4.038/test_regress/t/t_sv_cpu.pl0000775000177100017500000000337513702133370020661 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett, # Embecosm. compile( # Taken from the original VCS command line. v_flags2 => ["t/t_sv_cpu_code/timescale.sv", "t/t_sv_cpu_code/program_h.sv", "t/t_sv_cpu_code/pads_h.sv", "t/t_sv_cpu_code/ports_h.sv", "t/t_sv_cpu_code/pinout_h.sv", "t/t_sv_cpu_code/genbus_if.sv", "t/t_sv_cpu_code/pads_if.sv", "t/t_sv_cpu_code/adrdec.sv", "t/t_sv_cpu_code/pad_gpio.sv", "t/t_sv_cpu_code/pad_vdd.sv", "t/t_sv_cpu_code/pad_gnd.sv", "t/t_sv_cpu_code/pads.sv", "t/t_sv_cpu_code/ports.sv", "t/t_sv_cpu_code/ac_dig.sv", "t/t_sv_cpu_code/ac_ana.sv", "t/t_sv_cpu_code/ac.sv", "t/t_sv_cpu_code/cpu.sv", "t/t_sv_cpu_code/chip.sv"], vcs_flags2 => ["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"], verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t"], iv_flags2 => ["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_precedence.pl0000775000177100017500000000115713702133370022464 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); #!$Self->{vcs} or unsupported("VCS does ** wrong, fixed in 2014"); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_leak.pl0000775000177100017500000000150013702133370020262 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 if ($Self->{vltmt} && exists $ENV{TRAVIS_DIST} && $ENV{TRAVIS_DIST} eq "trusty") { skip("Multithreaded test does not work under Travis w/ Ubuntu Trusty"); } scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_named_2.pl0000775000177100017500000000105313702133370022036 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_threads.v0000664000177100017500000000401713702133370021471 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2018 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" dpii_sys_task = function void \$dpii_sys (); import "DPI-C" dpii_failure = function int \$dpii_failure (); module t (clk); input clk; integer cyc; integer failure; initial cyc = 0; `ifndef verilator `error "Only Verilator supports PLI-ish DPI calls." `endif always @ (posedge clk) begin if (cyc == 2) begin failure = $dpii_failure(); $write("* failure = %0d\n", failure); if (failure > 0) begin $stop; end $write("*-* All Finished *-*\n"); $finish; end cyc <= cyc + 1; end // The purpose of this test is to confirm that the DPI-call serialization // code in V3Partition does ensure that these DPI calls do not run // concurrently. // // Alternatively, the test may be run with "--threads-dpi all" in which case // it should confirm that the calls do run concurrently and do detect a // collision (they should, if the test is set up right.) This is // t_dpi_threads_collide.pl. // // Q) Is it a risk that the partitioner will merge or serialize these always // blocks, just by luck, even if the DPI-call serialization code fails? // // A) Yes, that's why t_dpi_threads_collide.pl also passes // --no-threads-do-coaren to disable MTask coarsening. This ensures that // the MTask graph at the end of FixDataHazards (where we resolve DPI // hazards) is basically the final MTasks graph, and that data hazards // which persist beyond FixDataHazards should persist in the final // generated C code. always @ (posedge clk) begin $dpii_sys(); end always @ (posedge clk) begin $dpii_sys(); end endmodule verilator-4.038/test_regress/t/t_func_first.v0000664000177100017500000000132413702133370021343 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc=0; reg set_in_task; always @ (posedge clk) begin if (cyc == 8'd0) begin cyc <= 8'd1; set_in_task <= 0; end if (cyc == 8'd1) begin cyc <= 8'h2; ttask; end if (cyc == 8'd2) begin if (!set_in_task) $stop; cyc <= 8'hf; $write("*-* All Finished *-*\n"); $finish; end end task ttask; begin set_in_task <= 1'b1; end endtask endmodule verilator-4.038/test_regress/t/t_dpi_accessors_inc.vh0000664000177100017500000000332613702133370023027 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Accessor definitions for test of DPI accessors // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by Jeremy Bennett and Jie Xu // See t_dpi_accessors.v for details of the test. This file should be included // by the top level module to define all the accessors needed. // Use the macros to provide the desire access to our data. First simple // access to the registers, array elements and wires. For consistency with // simulators, we do not attempt to write wires. `RW_ACCESS([0:0], a, {t.i_test_sub.a}); `RW_ACCESS([7:0], b, {t.i_test_sub.b}); `RW_ACCESS([7:0], mem32, {t.i_test_sub.mem[32]}); `R_ACCESS ([0:0], c, {t.i_test_sub.c}); `R_ACCESS ([7:0], d, {t.i_test_sub.d}); `RW_ACCESS([7:0], e, {t.i_test_sub.e}); `RW_ACCESS([7:0], f, {t.i_test_sub.f}); // Slices of vectors and array elements. For consistency with simulators, // we do not attempt to write wire slices. `RW_ACCESS([3:0], b_slice, {t.i_test_sub.b[3:0]}); `RW_ACCESS([4:0], mem32_slice, {t.i_test_sub.mem[32][7:6], t.i_test_sub.mem[32][2:0]}); `R_ACCESS([5:0], d_slice, {t.i_test_sub.d[6:1]}); // Complex registers, one with distinct read and write. We avoid use of // wires for consistency with simulators. `RW_ACCESS([14:0], l1, {t.i_test_sub.b[3:0], t.i_test_sub.mem[32][7:6], t.i_test_sub.e[6:1], t.i_test_sub.mem[32][2:0]}); `R_ACCESS([7:0], l2, {t.i_test_sub.e[7:4], t.i_test_sub.f[3:0]}); `W_ACCESS([7:0], l2, {t.i_test_sub.e[5:2], t.i_test_sub.f[5:2]}); verilator-4.038/test_regress/t/t_sys_writemem.pl0000775000177100017500000000250713702133370022105 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_sys_readmem.v"); # Use random reset to ensure we're fully initializing arrays before # $writememh, to avoid miscompares with X's on 4-state simulators. $Self->{verilated_randReset} = 2; # 2 == truly random compile(v_flags2 => [ "+define+WRITEMEM_READ_BACK=1", "+define+OUT_TMP1=\\\"$Self->{obj_dir}/tmp1.mem\\\"", "+define+OUT_TMP2=\\\"$Self->{obj_dir}/tmp2.mem\\\"", "+define+OUT_TMP3=\\\"$Self->{obj_dir}/tmp3.mem\\\"", "+define+OUT_TMP4=\\\"$Self->{obj_dir}/tmp4.mem\\\"", "+define+OUT_TMP5=\\\"$Self->{obj_dir}/tmp5.mem\\\"", ]); execute( check_finished => 1, ); for (my $i = 1; $i <= 5; $i++) { my $gold = "$Self->{t_dir}/t_sys_writemem.gold${i}.mem"; my $out = "$Self->{obj_dir}/tmp${i}.mem"; files_identical($out, $gold); } ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen4.v0000664000177100017500000000216613702133370022063 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug789 generates module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc #(1) itopa(); ifc #(2) itopb(); sub #(1) ca (.isub(itopa), .i_value(4)); sub #(2) cb (.isub(itopb), .i_value(5)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin if (itopa.MODE != 1) $stop; if (itopb.MODE != 2) $stop; end if (cyc==20) begin if (itopa.i != 4) $stop; if (itopb.i != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub #(parameter MODE = 0) ( ifc isub, input integer i_value ); // Commercial unsupported Xmrs into scopes within interfaces generate always_comb isub.i = i_value; endgenerate endmodule interface ifc; parameter MODE = 0; // Commercial unsupported Xmrs into scopes within interfaces generate integer i; endgenerate endinterface verilator-4.038/test_regress/t/t_sys_writemem.gold1.mem0000664000177100017500000000005213631173020023240 0ustar wsnyderwsnyder02 03 04 05 06 07 10 00 00 00 14 15 00 00 verilator-4.038/test_regress/t/t_lint_unsup_mixed.pl0000775000177100017500000000105613702133370022742 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only --bbox-unsup"], ); ok(1); 1; verilator-4.038/test_regress/t/t_unopt_bound.pl0000775000177100017500000000105313702133370021705 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_mp_func.v0000664000177100017500000000157613702133370022661 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface pads_if(); modport mp_dig( import fIn, import fOut ); integer exists[8]; function automatic integer fIn (integer i); fIn = exists[i]; endfunction task automatic fOut (integer i); exists[i] = 33; endtask endinterface module t(); pads_if padsif[1:0](); pads_if padsif_arr[1:0](); initial begin padsif[0].fOut(3); if (padsif[0].fIn(3) != 33) $stop; padsif_arr[0].fOut(3); if (padsif_arr[0].fIn(3) != 33) $stop; padsif_arr[1].fOut(3); if (padsif_arr[1].fIn(3) != 33) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_select_bad_msb.pl0000775000177100017500000000107113702133370022277 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlcov_data_a.dat0000664000177100017500000000026713366724403022144 0ustar wsnyderwsnyder# SystemC::Coverage-3 C 'CoverPoint0ffile1.sphl159' 0 C 'CoverPoint1ffile1.sphl159' 1 C 'CoverPoint2ffile1.sphl159' 10 C 'CoverPoint3ffile1.sphl159' 0 verilator-4.038/test_regress/t/t_lint_modport_dir_bad.pl0000775000177100017500000000116713702133370023535 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_bound_bad.pl0000775000177100017500000000120013702133370022116 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, bug528"); scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_fuzz_eqne_bad.v0000664000177100017500000000045713702133370022023 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1587 module t; reg a[0]; reg b; reg c; initial c = (a != &b); endmodule verilator-4.038/test_regress/t/t_flag_parameter_hier.pl0000775000177100017500000000233313702133370023333 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( # For Verilator, all PARAMs at all levels are overwridden # Error if parameter not found #verilator_flags2 => ['-GPARAM=10 -Gtop.t.x.HIER=20'], # HIER would error verilator_flags2 => ['-GPARAM=10'], # For NC, always implies a hierarchy, only HIER will be set # Warns if sets nothing nc_flags2 => ['+defparam+PARAM=10 +defparam+top.t.x.HIER=20'], # For VCS, all PARAMs at all levels are overridden. Hierarchy not allowed. # Informational on all overrides vcs_flags2 => ['-pvalue+PARAM=10 -px.HIER=20'], # For icarus -P without hierarchy does nothing, only can ref into top iv_flags2 => ['-PPARAM=10', '-Ptop.HIER=30', '-Ptop.t.x.HIER=20'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_cmp.pl0000775000177100017500000000105313702133370021141 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unopt_array.pl0000775000177100017500000000112513702133370021714 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2=>["-Wno-UNOPTFLAT"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_unconn.v0000664000177100017500000001060413702133370021360 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; wire one = '1; wire z0 = 'z; wire z1 = 'z; wire z2 = 'z; wire z3 = 'z; wire tog = cyc[0]; // verilator lint_off PINMISSING t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn()); t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0)); t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn()); t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1)); t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn()); t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2)); t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn()); t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3)); t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); // verilator lint_on PINMISSING // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_tri0 (line, expval, tn); input integer line; input expval; input tn; // Illegal to be inout; spec requires net connection to any inout tri0 tn; wire clk = t.clk; always @(posedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule module t_tri1 (line, expval, tn); input integer line; input expval; input tn; tri1 tn; wire clk = t.clk; always @(posedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule module t_tri2 (line, expval, tn); input integer line; input expval; input tn; pulldown(tn); wire clk = t.clk; always @(posedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule module t_tri3 (line, expval, tn); input integer line; input expval; input tn; pullup(tn); wire clk = t.clk; always @(negedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule verilator-4.038/test_regress/t/t_time_print.pl0000775000177100017500000000113513702133370021524 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_vams.cpp0000664000177100017500000000233513702133370021323 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include "Vt_dpi_vams.h" //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_vams__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { extern void dpii_call(double in, double* outp); } #endif void dpii_call(double in, double* outp) { *outp = in + 0.1; } //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = NULL; int main(int argc, char* argv[]) { topp = new VM_PREFIX; Verilated::debug(0); topp->in = 1.1; topp->eval(); if (topp->out != 1.2) { VL_PRINTF("*-* All Finished *-*\n"); topp->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results\n"); } return 0; } verilator-4.038/test_regress/t/t_bitsel_struct.pl0000775000177100017500000000105313702133367022245 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_index.v0000664000177100017500000000266613702133370021153 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test generate index usage. // // The code illustrates a problem in Verilator's handling of constant // expressions inside generate indexes. // // This is a regression test against issue 517. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 `define START 8 `define SIZE 4 `define END (`START + `SIZE) module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [`END-1:0] y; wire [`END-1:0] x; foo foo_i (.y (y), .x (x), .clk (clk)); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule // t module foo(output wire [`END-1:0] y, input wire [`END-1:0] x, input wire clk); function peek_bar; peek_bar = bar_inst[`START].i_bar.r; // this is ok peek_bar = bar_inst[`START + 1].i_bar.r; // this fails, should not. endfunction genvar g; generate for (g = `START; g < `END; g = g + 1) begin: bar_inst bar i_bar(.x (x[g]), .y (y[g]), .clk (clk)); end endgenerate endmodule : foo module bar(output wire y, input wire x, input wire clk); reg r = 0; assign y = r; always @(posedge clk) begin r = x ? ~x : y; end endmodule : bar verilator-4.038/test_regress/t/t_enum_int.pl0000775000177100017500000000105313702133370021167 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/.gitattributes0000664000177100017500000000002613702133341021356 0ustar wsnyderwsnydert_dos*.pl -crlf verilator-4.038/test_regress/t/t_param_default_presv_bad.out0000664000177100017500000000031313702133370024371 0ustar wsnyderwsnyder%Error: t/t_param_default_bad.v:7:26: Parameter requires default value, or use IEEE 1800-2009 or later. 7 | module m #(parameter int Foo); | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_gen9_noinl.pl0000775000177100017500000000116013702133370023431 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen9.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_hierarchy_identifier_bad.v0000664000177100017500000000214413702133370024170 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter SIZE = 8; integer cnt = 0; logic [SIZE-1:0] vld_for; logic vld_if = 1'b0; logic vld_else = 1'b0; genvar i; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if (cnt==SIZE) begin : if_cnt_finish $write("*-* All Finished *-*\n"); $finish; end : if_cnt_finish_bad generate for (i=0; i0) begin : generate_if_if always @ (posedge clk) vld_if <= 1'b1; end : generate_if_if_bad else begin : generate_if_else always @ (posedge clk) vld_else <= 1'b1; end : generate_if_else_bad endgenerate endmodule : t_bad verilator-4.038/test_regress/t/t_dist_inctree.pl0000775000177100017500000000534713702133370022037 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use strict; scenarios(dist => 1); my $root = ".."; my $Debug; my %Files; if (!-r "$root/.git") { skip("Not in a git repository"); } else { print "-Test is only for occasional cleanup, never completely clean\n"; #inctree(); } ok(1); sub inctree { # Note do not do test_regress, as VPI files need to compile without verilatedos.h my $files = "src/*.c* src/*.h include/*.c* include/*.h"; my $cmd = "cd $root && grep -n -P '^(# *include)' $files | sort"; print "C $cmd\n"; my $grep = `$cmd`; foreach my $line (split /\n/, $grep) { if ($line =~ /^(\S+):(\d+):#\s*include\s*(\S+)/) { my $filename = $1; my $line = $2+0; my $inc = $3; (my $base = $filename) =~ s!.*/(.*?)!$1!; $inc =~ s/[<>"]//g; $Files{$base}{filename} = $filename; $Files{$base}{incs}{$inc} = $line; #print "I $fileline $base $inc\n"; } else { warn "%Warning: Strange line: $line\n"; } } foreach my $base (keys %Files) { _inctree_recurse($base); } #use Data::Dumper; print Dumper(\%Files); foreach my $base (sort keys %Files) { my $fileref = $Files{$base}; foreach my $subinc (sort keys %{$fileref->{incs}}) { my $subline = $fileref->{incs}{$subinc}; if (my $subsubinfo = $fileref->{subincs}{$subinc}) { if ($subsubinfo->{line} < $subline) { error("$fileref->{filename}:$subline: Include of $subinc is also included by earlier include ($subsubinfo->{name})"); } } } } } sub _inctree_recurse { my $basename = shift; my $fileref = $Files{$basename}; return if $fileref->{subincs}; $fileref->{subincs} = {}; foreach my $subinc (keys %{$fileref->{incs}}) { _inctree_recurse($subinc); } foreach my $subinc (keys %{$fileref->{incs}}) { my $subline = $fileref->{incs}{$subinc}; foreach my $subsubinc (keys %{$Files{$subinc}{incs}}) { if (!$fileref->{subincs}{$subsubinc} || $fileref->{subincs}{$subsubinc}{line} < $subline) { $fileref->{subincs}{$subsubinc} = {line => $subline, name => $subinc, }; } } } } 1; verilator-4.038/test_regress/t/t_flag_parameter_bad.pl0000775000177100017500000000131613702133370023132 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_parameter.v"); lint( fails => 1, # It is not possible to put them into the options file v_flags2 => ['-GPARAM_THAT_DOES_NON_EXIST=1'], expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_bad_msb.out0000664000177100017500000000107213702133370022471 0ustar wsnyderwsnyder%Warning-LITENDIAN: t/t_select_bad_msb.v:12:8: Little bit endian vector: MSB < LSB of bit range: 0:22 : ... In instance t 12 | reg [0:22] backwd; | ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Error: t/t_select_bad_msb.v:16:16: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1] : ... In instance t 16 | sel2 = mi[1:4]; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_vpi_time_cb.pl0000775000177100017500000000173313702133370021636 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1, iv => 1); compile( make_top_shell => 0, make_main => 0, make_pli => 1, sim_time => 2100, iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"], v_flags2 => ["+define+USE_VPI_NOT_DPI"], verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_time_cb.cpp -LDFLAGS '-ldl -rdynamic'"], ); execute( iv_pli => 1, ms_pli => 1, check_finished => 1, all_run_flags => ['+PLUS +INT=1234 +STRSTR'] ); ok(1); 1; verilator-4.038/test_regress/t/t_time_literals.pl0000775000177100017500000000106013702133370022204 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_eq.pl0000775000177100017500000000105313702133370020767 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_implicit_def_bad.v0000664000177100017500000000104313702133370023463 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (a,z); input a; output z; sub sub (); assign imp_warn = 1'b1; // verilator lint_off IMPLICIT assign imp_ok = 1'b1; `default_nettype none assign imp_err = 1'b1; `default_nettype wire assign imp_ok2 = 1'b1; endmodule `default_nettype none `resetall module sub; assign imp_ok3 = 1'b1; endmodule verilator-4.038/test_regress/t/t_castdyn.out0000664000177100017500000000063513702133367021222 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_castdyn.v:12:11: Unsupported: $cast. Suggest try static cast. : ... In instance t 12 | i = $cast(a, b); | ^~~~~ %Error-UNSUPPORTED: t/t_castdyn.v:14:7: Unsupported: $cast. Suggest try static cast. : ... In instance t 14 | $cast(a, b); | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_in_inc_bad.v0000664000177100017500000000037013702133370022274 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_lint_in_inc_bad_1.vh" verilator-4.038/test_regress/t/t_var_vec_sel.v0000664000177100017500000000125613702133370021475 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug601 module t ( input clk, input [3:0] in3, // worky input [0:0] in2 [3:0], // worky input in1 [3:0], // no worky input [1:0] sel, output reg out1, output reg out2, output reg out3 ); always @(posedge clk) begin out3 <= in3[sel] ? in3[sel] : out3; out2 <= in2[sel] ? in2[sel] : out2; out1 <= in1[sel] ? in1[sel] : out1; // breaks $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_unopt_converge_run_bad.out0000664000177100017500000000042013702133370024266 0ustar wsnyderwsnyder-V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_unopt_converge_run_bad::_change_request -V{t#,#} CHANGE: t/t_unopt_converge.v:19: x %Error: t/t_unopt_converge.v:7: Verilated model didn't converge Aborting... verilator-4.038/test_regress/t/t_gen_var_bad.v0000664000177100017500000000053213702133370021430 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer i; generate for (i=0; i<3; i=i+1) begin // Bad: i is not a genvar end endgenerate endmodule verilator-4.038/test_regress/t/t_typedef_circ_bad.pl0000775000177100017500000000111313702133370022614 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_assoc_c_b.out0000664000177100017500000000005113702133370024042 0ustar wsnyderwsnyder02 03 04 05 06 07 @8 10 @c 14 15 @12c 0a verilator-4.038/test_regress/t/t_var_pins_sc_biguint.pl0000775000177100017500000000471713702133370023412 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_var_pinsizes.v"); compile( verilator_flags2 => ["-sc --pins-sc-biguint --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], make_main => 0, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i128;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i513;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o128;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o513;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16;/x); } execute(); ok(1); 1; verilator-4.038/test_regress/t/t_math_svl.pl0000775000177100017500000000124613702133370021172 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2005 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, # Make sure we get the finish statement called expect => '\*-\* All Finished \*-\* Goodbye world, at cycle \d+.*', ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_inside_cond.v0000664000177100017500000000155413702133367023053 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs hit, // Inputs clk ); input clk; output logic hit; logic [31:0] addr; int cyc; initial addr = 32'h380; always @ (posedge clk) begin cyc <= cyc + 1; `ifdef T_ASSERT_INSIDE_COND addr <= 32'h380; `elsif T_ASSERT_INSIDE_COND_BAD addr <= 32'h389; `else `error "Bad test define" `endif if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end end always_comb begin hit = 0; unique case (addr[11:0]) inside [12'h380 : 12'h388]: begin hit = 1; end endcase end endmodule verilator-4.038/test_regress/t/t_var_dup2.pl0000775000177100017500000000077313702133370021103 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_tree_inl1_pub1.pl0000775000177100017500000000254613702133370023227 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_tree.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( v_flags2 => ["t/$Self->{name}.vlt", $Self->wno_unopthreads_for_few_cores()] ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, expect => '\] (%m|.*t\.ps): Clocked ', ); ok(1); 1; verilator-4.038/test_regress/t/t_time_stamp64.v0000664000177100017500000000103013702133370021507 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin $write("[%0t] In %m: Hi\n", $time); $printtimescale; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_lint_vcmarker_bad.out0000664000177100017500000000061213702133370023210 0ustar wsnyderwsnyder%Error: t/t_lint_vcmarker_bad.v:9:1: version control conflict marker in file 9 | <<<<<<< HEAD | ^~~~~~~~~~~~~~~ %Error: t/t_lint_vcmarker_bad.v:11:1: version control conflict marker in file 11 | ======= | ^~~~~~~~~~~ %Error: t/t_lint_vcmarker_bad.v:13:1: version control conflict marker in file 13 | >>>>>>> MERGE | ^~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_dedupe_seq_logic.pl0000775000177100017500000000122213702133370022642 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats"], ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 6); } ok(1); 1; verilator-4.038/test_regress/t/t_case_write2.out0000664000177100017500000001155713343101620021755 0ustar wsnyderwsnyder[2] crc=0000000000000097 1009 1410 [3] crc=000000000000012e 1009 1410 [4] crc=000000000000025d 1009 1410 [5] crc=00000000000004ba 1009 1410 [6] crc=0000000000000974 1009 1410 [7] crc=00000000000012e9 1009 1410 [8] crc=00000000000025d3 1009 1410 [9] crc=0000000000004ba7 1009 1410 [10] crc=000000000000974e 1009 1410 [11] crc=0000000000012e9d 1009 1410 [12] crc=0000000000025d3a 1009 1410 [13] crc=000000000004ba74 1009 1410 [14] crc=00000000000974e9 1009 1410 [15] crc=000000000012e9d3 1009 1410 [16] crc=000000000025d3a7 1009 1410 [17] crc=00000000004ba74e 1009 1410 [18] crc=0000000000974e9d 1009 1410 [19] crc=00000000012e9d3a 1009 1410 [20] crc=00000000025d3a74 1009 1410 [21] crc=0000000004ba74e9 1009 1410 [22] crc=000000000974e9d3 1009 23 1303 138 dude 1304 [23] crc=0000000012e9d3a7 1009 46 1309 1311 143 1312 dude 1313 [24] crc=0000000025d3a74e 1009 172 407 175 408 409 410 1106 dude 1129 [25] crc=000000004ba74e9d 1009 223 1014 880 885 1015 1016:0 1007 dude 1017 [26] crc=00000000974e9d3a 1009 1229 967 1230 718 dude 1231 [27] crc=000000012e9d3a74 1009 1410 [28] crc=000000025d3a74e9 1009 58 1369 19 dude 1370 [29] crc=00000004ba74e9d3 1009 194 1033 1034 1008 1035 880 dude 1036 [30] crc=0000000974e9d3a7 1009 1409:69 [31] crc=00000012e9d3a74e 1009 29 1320 137 144 141 138 148 dude 1321 [32] crc=00000025d3a74e9d 1009 1383:3a7 [33] crc=0000004ba74e9d3a 1009 216 1018 882 884 1019 1020 1007 dude 1021 [34] crc=000000974e9d3a74 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [35] crc=0000012e9d3a74e9 1009 1228 979 1230 713 dude 1231 [36] crc=0000025d3a74e9d3 1009 194 1011 1006 1008 1012 880 dude 1013 [37] crc=000004ba74e9d3a7 1009 1409:69 [38] crc=00000974e9d3a74e 1009 29 1320 137 144 141 138 148 dude 1321 [39] crc=000012e9d3a74e9d 1009 1383:3a7 [40] crc=000025d3a74e9d3a 1009 216 1018 882 884 1019 1020 1007 dude 1021 [41] crc=00004ba74e9d3a74 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [42] crc=0000974e9d3a74e9 1009 1228 979 1230 713 dude 1231 [43] crc=00012e9d3a74e9d3 1009 194 1011 1006 1008 1012 880 dude 1013 [44] crc=00025d3a74e9d3a7 1009 1409:69 [45] crc=0004ba74e9d3a74e 1009 29 1320 137 144 141 138 148 dude 1321 [46] crc=000974e9d3a74e9d 1009 1383:3a7 [47] crc=0012e9d3a74e9d3a 1009 216 1018 882 884 1019 1020 1007 dude 1021 [48] crc=0025d3a74e9d3a74 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [49] crc=004ba74e9d3a74e9 1009 1228 979 1230 713 dude 1231 [50] crc=00974e9d3a74e9d3 1009 194 1011 1006 1008 1012 880 dude 1013 [51] crc=012e9d3a74e9d3a7 1009 1409:69 [52] crc=025d3a74e9d3a74e 1009 29 1320 137 144 141 138 148 dude 1321 [53] crc=04ba74e9d3a74e9d 1009 1383:3a7 [54] crc=0974e9d3a74e9d3a 1009 216 1018 882 884 1019 1020 1007 dude 1021 [55] crc=12e9d3a74e9d3a74 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [56] crc=25d3a74e9d3a74e9 1009 1228 979 1230 713 dude 1231 [57] crc=4ba74e9d3a74e9d3 1009 194 1011 1006 1008 1012 880 dude 1013 [58] crc=974e9d3a74e9d3a7 1009 1409:69 [59] crc=2e9d3a74e9d3a74f 1009 29 1320 137 144 141 138 149 dude 1321 [60] crc=5d3a74e9d3a74e9e 1009 1383:3a7 [61] crc=ba74e9d3a74e9d3d 1009 216 1018 882 884 1019 1020 1007 dude 1021 [62] crc=74e9d3a74e9d3a7b 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [63] crc=e9d3a74e9d3a74f7 1009 1228 979 1230 713 dude 1231 [64] crc=d3a74e9d3a74e9ef 1009 194 1011 1006 1008 1012 880 dude 1013 [65] crc=a74e9d3a74e9d3df 1009 1409:69 [66] crc=4e9d3a74e9d3a7bf 1009 29 1320 137 144 141 145 149 dude 1321 [67] crc=9d3a74e9d3a74f7e 1009 1383:3a7 [68] crc=3a74e9d3a74e9efc 1009 216 1018 882 884 1019 1020 1007 dude 1021 [69] crc=74e9d3a74e9d3df9 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [70] crc=e9d3a74e9d3a7bf3 1009 1228 979 1230 713 dude 1231 [71] crc=d3a74e9d3a74f7e6 1009 194 1011 1006 1008 1012 880 dude 1013 [72] crc=a74e9d3a74e9efcc 1009 1409:69 [73] crc=4e9d3a74e9d3df98 1009 29 1320 137 147 149 143 142 dude 1321 [74] crc=9d3a74e9d3a7bf30 1009 1383:3a7 [75] crc=3a74e9d3a74f7e61 1009 216 1018 882 885 1019 1020 1007 dude 1021 [76] crc=74e9d3a74e9efcc3 1009 197 1014 882 884 1015 1016:1 1008 dude 1017 [77] crc=e9d3a74e9d3df987 1009 1228 982 1230 713 dude 1231 [78] crc=d3a74e9d3a7bf30f 1009 194 1011 1006 1008 1012 881 885 dude 1013 [79] crc=a74e9d3a74f7e61f 1009 1409:77 [80] crc=4e9d3a74e9efcc3f 1009 30 1320 149 146 146 137 149 dude 1321 [81] crc=9d3a74e9d3df987e 1009 1383:3df [82] crc=3a74e9d3a7bf30fc 1009 225 1018 882 885 1019 1020 1008 dude 1021 [83] crc=74e9d3a74f7e61f9 1009 218 1014 882 884 1015 1016:1 1008 dude 1017 [84] crc=e9d3a74e9efcc3f3 1009 1228 981 1230 708 dude 1231 [85] crc=d3a74e9d3df987e6 1009 232 1011 1005 1008 1012 881 883 dude 1013 [86] crc=a74e9d3a7bf30fcc 1009 1409:73 [87] crc=4e9d3a74f7e61f98 1009 1006 1258 846 1259 1006 1260 833 1261 dude 1262 [88] crc=9d3a74e9efcc3f30 1009 124 1320 146 137 149 137 134 dude 1321 [89] crc=3a74e9d3df987e61 1009 1383:f98 [90] crc=74e9d3a7bf30fcc3 1009 215 1033 1034 1008 1035 879 dude 1036 verilator-4.038/test_regress/t/t_func_bad2.out0000664000177100017500000000034313702133370021366 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_func_bad2.v:8:13: Unsupported: Recursive function or task call : ... In instance t 8 | function recurse; | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_time_sc_ms.pl0000775000177100017500000000141313702133370021473 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_time_sc.v"); $Self->{sc_time_resolution} = 'SC_MS'; compile( verilator_flags2 => ['-sc', '-timescale 1ms/1ms', '+define+TEST_EXPECT=20ms'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_dup_bad.out0000664000177100017500000000137113702133370022002 0ustar wsnyderwsnyder%Warning-MODDUP: t/t_mod_dup_bad.v:14:8: Duplicate declaration of module: 'a' 14 | module a(); | ^ t/t_mod_dup_bad.v:7:8: ... Location of original declaration 7 | module a(); | ^ ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. %Warning-MULTITOP: t/t_mod_dup_bad.v:17:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. : ... Top module 'test' 10 | module test(); | ^~~~ : ... Top module 'b' 17 | module b(); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_bitsel_slice.v0000664000177100017500000000353213702133367021653 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; logic [2:0] [1:0] in; always @* in = crc[5:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [1:0] [1:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out/*[1:0][1:0]*/), // Inputs .clk (clk), .in (in/*[2:0][1:0]*/)); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out[1],out[0]}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hdc21e42d85441511 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); //bug717 input clk; input logic [2:0][1:0] in; output logic [1:0][1:0] out; always @(posedge clk) begin out <= in[2 -: 2]; end endmodule verilator-4.038/test_regress/t/t_xml_tag.pl0000775000177100017500000000134713702133370021012 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2012 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( verilator_flags2 => ['--xml-only'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); files_identical("$out_filename", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_param_circ_bad.v0000664000177100017500000000051413702133370022107 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); sub sub (); endmodule module sub #(parameter WIDTH=X, parameter X=WIDTH) (); endmodule verilator-4.038/test_regress/t/t_concat_link_bad.pl0000775000177100017500000000107413702133367022454 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_concat5.v0000664000177100017500000000343713702133367021403 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input [3:0] i_clks ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge i_clks[3]) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (i_clks[3]) some_other_state <= 0; $write("*-* All Finished *-*\n"); $finish; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( .i_clks (i_clks) ); endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; assign the_clks[3] = i_clk1; assign the_clks[2] = i_clk2; assign the_clks[1] = i_clk1; assign the_clks[0] = i_clk0; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( /*AUTOARG*/ // Inputs clk /*verilator clocker*/, input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); input clk; logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk), .i_clk2 (clk2), .i_data (data_in) ); // initial begin // $write("*-* All Finished *-*\n"); // $finish; // end endmodule verilator-4.038/test_regress/t/t_type_param_collision.pl0000775000177100017500000000117313702133370023570 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_type_param.v"); compile( verilator_flags2 => ["--debug-collision"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_cover_line.out0000664000177100017500000001606613702133367021707 0ustar wsnyderwsnyder // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; %000002 initial toggle=0; integer cyc; %000002 initial cyc=1; wire [7:0] cyc_copy = cyc[7:0]; alpha a1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); alpha a2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); beta b2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); tsk t1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); 000020 always @ (posedge clk) begin 000020 if (cyc!=0) begin %000000 verilator_coverage: (next point on previous line) 000010 cyc <= cyc + 1; 000010 toggle <= '0; // Single and multiline if %000002 if (cyc==3) $write(""); %000009 verilator_coverage: (next point on previous line) %000002 if (cyc==3) %000009 verilator_coverage: (next point on previous line) %000001 begin %000001 $write(""); end // Single and multiline else %000002 if (cyc==3) ; else $write(""); %000018 verilator_coverage: (next point on previous line) %000002 if (cyc==3) ; %000009 verilator_coverage: (next point on previous line) else %000009 begin %000009 $write(""); end // Single and multiline if else %000002 if (cyc==3) $write(""); else $write(""); %000018 verilator_coverage: (next point on previous line) %000002 if (cyc==3) %000009 verilator_coverage: (next point on previous line) %000001 begin %000001 $write(""); end else %000009 begin %000009 $write(""); end // multiline elseif %000002 if (cyc==3) %000001 begin %000001 $write(""); end %000002 else if (cyc==4) %000001 begin %000001 $write(""); end %000002 else if (cyc==5) %000007 verilator_coverage: (next point on previous line) %000001 begin %000001 $write(""); end else %000007 begin %000007 $write(""); end // Single and multiline while %000000 while (0); %000000 while (0) begin %000000 $write(""); end %000000 do ; while (0); 000010 do begin %000000 verilator_coverage: (next point on previous line) 000010 $write(""); %000000 verilator_coverage: (next point on previous line) %000000 end while (0); //=== // Task and complicated %000002 if (cyc==3) begin %000001 toggle <= '1; end %000002 else if (cyc==5) begin `ifdef VERILATOR %000001 $c("call_task();"); `else call_task(); `endif end %000002 else if (cyc==10) begin %000007 verilator_coverage: (next point on previous line) %000001 $write("*-* All Finished *-*\n"); %000001 $finish; end end end %000002 task call_task; /* verilator public */ %000001 t1.center_task(1'b1); endtask endmodule module alpha (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; 000040 always @ (posedge clk) begin %000004 if (toggle) begin // CHECK_COVER(0,"top.t.a*",2) 000018 verilator_coverage: (next point on previous line) %000002 $write(""); // t.a1 and t.a2 collapse to a count of 2 end 000018 if (toggle) begin $write(""); // CHECK_COVER_MISSING(0) // This doesn't even get added `ifdef ATTRIBUTE // verilator coverage_block_off `endif end end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ 000040 always @ (posedge clk) begin 000020 $write(""); // Always covered %000000 if (0) begin // CHECK_COVER(0,"top.t.b*",0) 000020 verilator_coverage: (next point on previous line) // Make sure that we don't optimize away zero buckets %000000 $write(""); end %000004 if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) 000018 verilator_coverage: (next point on previous line) // t.b1 and t.b2 collapse to a count of 2 %000002 $write(""); end 000018 if (toggle) begin : block // This doesn't `ifdef ATTRIBUTE // verilator coverage_block_off `endif begin end // Needed for .vlt to attach coverage_block_off if (1) begin end // CHECK_COVER_MISSING(0) $write(""); // CHECK_COVER_MISSING(0) end end endmodule module tsk (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ 000020 always @ (posedge clk) begin 000010 center_task(1'b0); end 000022 task center_task; input external; 000011 begin %000002 if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) 000010 verilator_coverage: (next point on previous line) %000001 $write(""); end %000002 if (external) begin // CHECK_COVER(0,"top.t.t1",1) 000010 verilator_coverage: (next point on previous line) %000001 $write("[%0t] Got external pulse\n", $time); end end endtask endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; // verilator coverage_off always @ (posedge clk) begin if (toggle) begin $write(""); // CHECK_COVER_MISSING(0) // because under coverage_module_off end end // verilator coverage_on 000020 always @ (posedge clk) begin %000002 if (toggle) begin %000009 verilator_coverage: (next point on previous line) // because under coverage_module_off %000001 $write(""); %000000 if (0) ; // CHECK_COVER(0,"top.t.o1",1) %000001 verilator_coverage: (next point on previous line) end end endmodule verilator-4.038/test_regress/t/t_lint_ifdepth_bad.out0000664000177100017500000000057713702133370023033 0ustar wsnyderwsnyder%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:22:12: Deep 'if' statement; suggest unique/priority to avoid slow logic : ... In instance t 22 | else if (value==11) begin end | ^~ ... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_var_suggest_bad.pl0000775000177100017500000000111313702133370022505 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_persist.pl0000775000177100017500000000173613702133370022604 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2017 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; compile( # Override default flags v_flags => [''], v_other_filenames => ["t_preproc_persist2.v"], verilator_flags => ["-E -P +incdir+t -Mdir $Self->{obj_dir}", ], verilator_flags2 => ['',], verilator_flags3 => ['',], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, stdout_filename => $stdout_filename, ); files_identical($stdout_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_func_numones.pl0000775000177100017500000000105313702133370022050 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_casez.pl0000775000177100017500000000112613702133367022046 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gate_basic.pl0000775000177100017500000000105313702133370021432 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_f.v0000664000177100017500000000150113702133370020414 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_flag_f_tsub_inc.v" module t; initial begin `ifndef GOT_DEF1 $write("%%Error: NO GOT_DEF1\n"); $stop; `endif `ifndef GOT_DEF2 $write("%%Error: NO GOT_DEF2\n"); $stop; `endif `ifndef GOT_DEF3 $write("%%Error: NO GOT_DEF3\n"); $stop; `endif `ifndef GOT_DEF4 $write("%%Error: NO GOT_DEF4\n"); $stop; `endif `ifndef GOT_DEF5 $write("%%Error: NO GOT_DEF5\n"); $stop; `endif `ifndef GOT_DEF6 $write("%%Error: NO GOT_DEF6\n"); $stop; `endif `ifdef NON_DEF $write("%%Error: NON_DEF\n"); $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_time_stamp_double.pl0000775000177100017500000000133713702133370023052 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename('t/t_time_stamp64.v'); # Verilator before 4.033 had 'double sc_time_stamp()', make sure this still compiles $self->{vl_time_stamp64} = 0; compile( verilator_flags2 => [], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_file_basic_input.dat0000664000177100017500000000021613343101620023672 0ustar wsnyderwsnyderhi lquad widestuff *xa=1f xb=237904689_02348923 *ba=10 bb=11010010101001010101 note_the_two *oa=23 ob=12563 *d=-236123 *fredfishblah 12346789 verilator-4.038/test_regress/t/t_gen_if.pl0000775000177100017500000000077713702133370020614 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_wpedantic_bad.pl0000775000177100017500000000114113702133370023124 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["-Wpedantic"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_scope_bad.out0000664000177100017500000000054513702133367022325 0ustar wsnyderwsnyder%Warning-CLKDATA: t/t_clk_scope_bad.v:36:12: Clock used as data (on rhs of assignment) in sequential block 'clk' : ... In instance t.p2 36 | q <= d; | ^ ... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_display_real.v0000664000177100017500000000371013702133370021652 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; real n0; initial n0 = 0.0; real n1; initial n1 = 1.0; real n2; initial n2 = 0.1; real n3; initial n3 = 1.2345e-15; real n4; initial n4 = 2.579e+15; reg [7:0] r8; initial r8 = 3; initial begin // Display formatting $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n0,n0,n0,n0,n0); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n0,n0,n0,n0,n0); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n0,n0,n0,n0,n0); $display; $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n1,n1,n1,n1,n1); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n1,n1,n1,n1,n1); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n1,n1,n1,n1,n1); $display; $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n2,n2,n2,n2,n2); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n2,n2,n2,n2,n2); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n2,n2,n2,n2,n2); $display; $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n3,n3,n3,n3,n3); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n3,n3,n3,n3,n3); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n3,n3,n3,n3,n3); $display; $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n4,n4,n4,n4,n4); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n4,n4,n4,n4,n4); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n4,n4,n4,n4,n4); $display; $display("r8=%d n1=%g n2=%g", r8, n1, n2); $display("n1=%g n2=%g r8=%d", n1, n2, r8); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_div.v0000664000177100017500000000666713702133370021013 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [255:0] a; reg [60:0] divisor; reg [60:0] qq; reg [60:0] rq; reg [60:0] qq4; reg [60:0] rq4; reg [60:0] qq5; reg [60:0] rq5; reg signed [60:0] qqs; reg signed [60:0] rqs; always @* begin qq = a[60:0] / divisor; rq = a[60:0] % divisor; qq4 = a[60:0] / 4; // Check power-of-two constification rq4 = a[60:0] % 4; qq5 = a[60:0] / 5; // Non power-of-two rq5 = a[60:0] % 5; qqs = $signed(a[60:0]) / $signed(divisor); rqs = $signed(a[60:0]) % $signed(divisor); end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs); if (cyc==1) begin a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; divisor <= 61'h12371; a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned end if (cyc > 1) begin if (qq4 != {2'b0, a[60:2]}) $stop; if (rq4 != {59'h0, a[1:0]}) $stop; end if (cyc==2) begin a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; divisor <= 61'h1238123771; a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned if (qq!==61'h00000403ad81c0da) $stop; if (rq!==61'h00000000000090ec) $stop; if (qqs!==61'h00000403ad81c0da) $stop; if (rqs!==61'h00000000000090ec) $stop; if (qq4 != 61'h01247cf6851f9fc9) $stop; if (rq4 != 61'h0000000000000002) $stop; end if (cyc==3) begin a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8; divisor <= 61'hf1b; a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed if (qq!==61'h000000000090832e) $stop; if (rq!==61'h0000000334becc6a) $stop; if (qqs!==61'h000000000090832e) $stop; if (rqs!==61'h0000000334becc6a) $stop; if (qq4 != 61'h0292380e727ce56e) $stop; if (rq4 != 61'h0000000000000000) $stop; end if (cyc==4) begin a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed if (qq!==61'h0001eda37cca1be8) $stop; if (rq!==61'h0000000000000c40) $stop; if (qqs!==61'h1fffcf5187c76510) $stop; if (rqs!==61'h1ffffffffffffd08) $stop; if (qq4 != 61'h07482923803ce56e) $stop; if (rq4 != 61'h0000000000000000) $stop; end if (cyc==5) begin a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed if (qq!==61'h0000000000000000) $stop; if (rq!==61'h0d20a48e00f395b8) $stop; if (qqs!==61'h0000000000000000) $stop; if (rqs!==61'h0d20a48e00f395b8) $stop; end if (cyc==6) begin if (qq!==61'h0000000000000001) $stop; if (rq!==61'h0d20a48e00f3869d) $stop; if (qqs!==61'h0000000000000000) $stop; if (rqs!==61'h1d20a48e00f395b8) $stop; end // Div by zero if (cyc==9) begin divisor <= 61'd0; end if (cyc==10) begin `ifdef verilator if (qq !== {61{1'b0}}) $stop; if (rq !== {61{1'b0}}) $stop; `else if (qq !== {61{1'bx}}) $stop; if (rq !== {61{1'bx}}) $stop; `endif if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors end if (cyc==19) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_debug_fatalsrc_bt_bad.pl0000775000177100017500000000144613702133370023617 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB"); lint( verilator_flags2 => ["--lint-only --debug --gdbbt --debug-fatalsrc"], fails => 1, expect => '%Error: Internal Error: .*: --debug-fatal-src .*See the manual and .* .*in V3Options::.* .*%Error: Command Failed.*', ); ok(1); 1; verilator-4.038/test_regress/t/t_func_return_bad.pl0000775000177100017500000000107413702133370022514 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2011 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_recurse_bad.pl0000775000177100017500000000107413702133370022656 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_rsvd_bad.pl0000775000177100017500000000116113702133370022005 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_var_rsvd_port.v"); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_concat_sel_bad.pl0000775000177100017500000000101313702133370023276 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_context_bad.pl0000775000177100017500000000117313702133370022637 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["-Wall -Wno-DECLFILENAME -Wno-context"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_packed_concat_bad.v0000664000177100017500000000131013702133370022560 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; initial begin if (count_bits[0] != 16) $stop; if (count_bits[1] != 16) $stop; if (count_bitsc[0] != 16) $stop; if (count_bitsc[1] != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_class_class.pl0000775000177100017500000000112113702133367021645 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_bad_range3.pl0000775000177100017500000000111313702133370022672 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_signed.pl0000775000177100017500000000105313702133370021657 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_noopt.pl0000775000177100017500000000134313702133370022237 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_display.v"); $Self->{golden_filename} = "t/t_display.out"; # Match unopt version compile( verilator_flags2 => ["-O0"], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_arraymux.v0000664000177100017500000000505013702133370023071 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by John Stevenson. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef logic [31:0] unique_id_t; typedef struct packed { unique_id_t foo; } inner_thing_t; typedef struct packed { inner_thing_t bar; inner_thing_t baz; } outer_thing_t; endpackage import pkg::*; interface the_intf #(parameter M=5); outer_thing_t [M-1:0] things; logic valid; modport i ( output things, output valid); modport t ( input things, input valid); endinterface module ThingMuxOH #( parameter NTHINGS = 1, parameter M = 5 ) ( input logic [NTHINGS-1:0] select_oh, the_intf.t things_in [NTHINGS-1:0], the_intf.i thing_out ); endmodule module Thinker #( parameter M = 5, parameter N = 2) ( input logic clk, input logic reset, input unique_id_t uids[0:N-1], the_intf.t thing_inp, the_intf.i thing_out ); the_intf #(.M(M)) curr_things [N-1:0] (); the_intf #(.M(M)) prev_things [N-1:0] (); the_intf #(.M(M)) curr_thing (); the_intf #(.M(M)) prev_thing (); logic [N-1:0] select_oh; // 1st mux: ThingMuxOH #( .NTHINGS ( N ), .M ( M )) curr_thing_mux( .select_oh( select_oh ), .things_in( curr_things ), .thing_out( curr_thing )); // 2nd mux, comment this out and no problem: ThingMuxOH #( .NTHINGS ( N ), .M ( M )) prev_thing_mux( .select_oh( select_oh ), .things_in( prev_things ), .thing_out( prev_thing )); endmodule module t ( input logic clk, input logic reset ); localparam M = 5; localparam N = 2; unique_id_t uids[0:N-1]; the_intf #(.M(M)) thing_inp(); the_intf #(.M(M)) thing_out(); Thinker #( .M ( M ), .N ( N )) thinker( .clk ( clk ), .reset ( reset ), .uids ( uids ), .thing_inp( thing_inp ), .thing_out( thing_out )); // Previously there was a problem in V3Inst if non-default parameters was used localparam K = 2; the_intf #(.M(K)) thing_inp2(); the_intf #(.M(K)) thing_out2(); Thinker #( .M ( K ), .N ( N )) thinker2( .clk ( clk ), .reset ( reset ), .uids ( uids ), .thing_inp( thing_inp2 ), .thing_out( thing_out2 )); endmodule verilator-4.038/test_regress/t/t_tri_array_bufif.pl0000775000177100017500000000105313702133370022520 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_export_bad.v0000664000177100017500000000062313702133370022165 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; export "DPI-C" task dpix_bad_missing; endmodule verilator-4.038/test_regress/t/t_cover_line_sc.pl0000775000177100017500000000134213702133367022172 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_cover_line.v"); compile( verilator_flags2 => ['--sc --coverage-line +define+ATTRIBUTE'], ); execute( check_finished => 1, ); # Read the input .v file and do any CHECK_COVER requests inline_checks(); ok(1); 1; verilator-4.038/test_regress/t/t_case_reducer.v0000664000177100017500000002553313702133367021643 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] operand_a = crc[7:0]; wire [7:0] operand_b = crc[15:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [6:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[6:0]), // Inputs .clk (clk), .operand_a (operand_a[7:0]), .operand_b (operand_b[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h8a78c2ec4946ac38 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( // Inputs input wire clk, input wire [7:0] operand_a, // operand a input wire [7:0] operand_b, // operand b // Outputs output wire [6:0] out ); wire [6:0] clz_a; wire [6:0] clz_b; clz u_clz_a ( // Inputs .data_i (operand_a), .out (clz_a)); clz u_clz_b ( // Inputs .data_i (operand_b), .out (clz_b)); assign out = clz_a - clz_b; `ifdef TEST_VERBOSE always @(posedge clk) $display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b); `endif endmodule `define def_0000_001x 8'b0000_0010, 8'b0000_0011 `define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111 `define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011 `define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111 `define def_0000_1xxx `def_0000_10xx, `def_0000_11xx `define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011 `define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111 `define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011 `define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111 `define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011 `define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111 `define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011 `define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111 `define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011 `define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111 `define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011 `define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111 `define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011 `define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111 `define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011 `define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111 `define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011 `define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111 `define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011 `define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111 `define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011 `define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111 `define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011 `define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111 `define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011 `define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111 `define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011 `define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111 `define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011 `define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111 `define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011 `define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111 `define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011 `define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111 `define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011 `define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111 `define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011 `define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111 `define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011 `define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111 `define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011 `define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111 `define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011 `define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111 `define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011 `define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111 `define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011 `define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111 `define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011 `define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111 `define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011 `define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111 `define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011 `define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111 `define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011 `define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111 `define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011 `define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111 `define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011 `define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111 `define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx `define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx `define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx `define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx `define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx `define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx `define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx `define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx `define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx `define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx `define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx `define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx `define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx `define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx `define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx `define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \ `def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx `define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx `define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx module clz( input wire [7:0] data_i, output wire [6:0] out ); // ----------------------------- // Reg declarations // ----------------------------- reg [2:0] clz_byte0; reg [2:0] clz_byte1; reg [2:0] clz_byte2; reg [2:0] clz_byte3; always @* case (data_i) `def_1xxx_xxxx : clz_byte0 = 3'b000; `def_01xx_xxxx : clz_byte0 = 3'b001; `def_001x_xxxx : clz_byte0 = 3'b010; `def_0001_xxxx : clz_byte0 = 3'b011; `def_0000_1xxx : clz_byte0 = 3'b100; `def_0000_01xx : clz_byte0 = 3'b101; `def_0000_001x : clz_byte0 = 3'b110; 8'b0000_0001 : clz_byte0 = 3'b111; 8'b0000_0000 : clz_byte0 = 3'b111; default : clz_byte0 = 3'bxxx; endcase always @* case (data_i) `def_1xxx_xxxx : clz_byte1 = 3'b000; `def_01xx_xxxx : clz_byte1 = 3'b001; `def_001x_xxxx : clz_byte1 = 3'b010; `def_0001_xxxx : clz_byte1 = 3'b011; `def_0000_1xxx : clz_byte1 = 3'b100; `def_0000_01xx : clz_byte1 = 3'b101; `def_0000_001x : clz_byte1 = 3'b110; 8'b0000_0001 : clz_byte1 = 3'b111; 8'b0000_0000 : clz_byte1 = 3'b111; default : clz_byte1 = 3'bxxx; endcase always @* case (data_i) `def_1xxx_xxxx : clz_byte2 = 3'b000; `def_01xx_xxxx : clz_byte2 = 3'b001; `def_001x_xxxx : clz_byte2 = 3'b010; `def_0001_xxxx : clz_byte2 = 3'b011; `def_0000_1xxx : clz_byte2 = 3'b100; `def_0000_01xx : clz_byte2 = 3'b101; `def_0000_001x : clz_byte2 = 3'b110; 8'b0000_0001 : clz_byte2 = 3'b111; 8'b0000_0000 : clz_byte2 = 3'b111; default : clz_byte2 = 3'bxxx; endcase always @* case (data_i) `def_1xxx_xxxx : clz_byte3 = 3'b000; `def_01xx_xxxx : clz_byte3 = 3'b001; `def_001x_xxxx : clz_byte3 = 3'b010; `def_0001_xxxx : clz_byte3 = 3'b011; `def_0000_1xxx : clz_byte3 = 3'b100; `def_0000_01xx : clz_byte3 = 3'b101; `def_0000_001x : clz_byte3 = 3'b110; 8'b0000_0001 : clz_byte3 = 3'b111; 8'b0000_0000 : clz_byte3 = 3'b111; default : clz_byte3 = 3'bxxx; endcase assign out = {4'b0000, clz_byte1}; endmodule // clz verilator-4.038/test_regress/t/t_assert_on.v0000664000177100017500000000055113702133367021205 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin assert (0); $finish; end endmodule verilator-4.038/test_regress/t/t_flag_bboxsys.pl0000775000177100017500000000111513702133370022032 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ["--bbox-sys"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_misdef_bad.v0000664000177100017500000000061613702133370021760 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define DEFINED // NDEFINED isn't defined here: `NDEFINED // Botched directive (`timescale) `imescale initial $stop; // Should have failed endmodule verilator-4.038/test_regress/t/t_param_array4.v0000664000177100017500000000236013702133370021564 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter int SIZES [3:1] = '{10,20,30}; parameter int SUMS3 = SIZES[3]; parameter int SUMS2 = SIZES[2]; parameter int SUMS1 = SIZES[1]; parameter int LE_SIZES [1:3] = '{10,20,30}; parameter int LE_SUMS3 = LE_SIZES[3]; parameter int LE_SUMS2 = LE_SIZES[2]; parameter int LE_SUMS1 = LE_SIZES[1]; function int from_array(int index); if (index != 0); return SIZES[index]; endfunction function int from_array_le(int index); if (index != 0); return LE_SIZES[index]; endfunction initial begin if (SUMS1 != 30) $stop; if (SUMS2 != 20) $stop; if (SUMS3 != 10) $stop; if (LE_SUMS1 != 10) $stop; if (LE_SUMS2 != 20) $stop; if (LE_SUMS3 != 30) $stop; if (from_array(1) != 30) $stop; if (from_array(2) != 20) $stop; if (from_array(3) != 10) $stop; if (from_array_le(1) != 10) $stop; if (from_array_le(2) != 20) $stop; if (from_array_le(3) != 30) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_named.v0000664000177100017500000000162213702133370021301 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); function int f( int j = 1, int s = 0 ); return (j<<16) | s; endfunction `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); initial begin `checkh( f(.j(2), .s(1)) , 32'h2_0001 ); `checkh( f(.s(1)) , 32'h1_0001 ); `checkh( f(, 1) , 32'h1_0001 ); `checkh( f(.j(2)) , 32'h2_0000 ); `checkh( f(.s(1), .j(2)) , 32'h2_0001 ); `checkh( f(.s(), .j()) , 32'h1_0000 ); `checkh( f(2) , 32'h2_0000 ); `checkh( f() , 32'h1_0000 ); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_package.v0000664000177100017500000000264213702133370020600 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef int unit_type_t; function [3:0] unit_plusone(input [3:0] i); unit_plusone = i+1; endfunction package p; typedef int package_type_t; integer pi = 123; function [3:0] plusone(input [3:0] i); plusone = i+1; endfunction endpackage package p2; typedef int package2_type_t; function [3:0] plustwo(input [3:0] i); plustwo = i+2; endfunction endpackage module t (/*AUTOARG*/ // Inputs clk ); input clk; unit_type_t vu; $unit::unit_type_t vdu; p::package_type_t vp; t2 t2 (); initial begin if (unit_plusone(1) !== 2) $stop; if ($unit::unit_plusone(1) !== 2) $stop; if (p::plusone(1) !== 2) $stop; p::pi = 124; if (p::pi !== 124) $stop; $write("*-* All Finished *-*\n"); $finish; end always @ (posedge clk) begin p::pi += 1; if (p::pi < 124) $stop; end endmodule module t2; import p::*; import p2::plustwo; import p2::package2_type_t; package_type_t vp; package2_type_t vp2; initial begin if (plusone(1) !== 2) $stop; if (plustwo(1) !== 3) $stop; if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value end endmodule verilator-4.038/test_regress/t/t_interface_gen3.v0000664000177100017500000000324413702133370022060 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc #(2) itopa(); ifc #(4) itopb(); sub ca (.isub(itopa.out_modport), .clk); sub cb (.isub(itopb.out_modport), .clk); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo); `endif cyc <= cyc + 1; itopa.valuei <= cyc[1:0]; itopb.valuei <= cyc[3:0]; if (cyc==1) begin if (itopa.WIDTH != 2) $stop; if (itopb.WIDTH != 4) $stop; if ($bits(itopa.valueo) != 2) $stop; if ($bits(itopb.valueo) != 4) $stop; if ($bits(itopa.out_modport.valueo) != 2) $stop; if ($bits(itopb.out_modport.valueo) != 4) $stop; end if (cyc==4) begin if (itopa.valueo != 2'b11) $stop; if (itopb.valueo != 4'b0011) $stop; end if (cyc==5) begin if (itopa.valueo != 2'b00) $stop; if (itopb.valueo != 4'b0100) $stop; end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule interface ifc #(parameter WIDTH = 1); // verilator lint_off MULTIDRIVEN logic [WIDTH-1:0] valuei; logic [WIDTH-1:0] valueo; // verilator lint_on MULTIDRIVEN modport out_modport (input valuei, output valueo); endinterface // Note not parameterized module sub ( ifc.out_modport isub, input clk ); always @(posedge clk) isub.valueo <= isub.valuei + 1; endmodule verilator-4.038/test_regress/t/t_case_zx_bad.pl0000775000177100017500000000110113702133367021613 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_vecgen2.pl0000775000177100017500000000116513702133367021545 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_clk_vecgen1.v"); compile( v_flags2 => ['+define+T_TEST2',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_order_a.v0000664000177100017500000000321413702133370020614 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_order_a (/*AUTOARG*/ // Outputs m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12, // Inputs clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one ); input clk; input [7:0] a_to_clk_levm3; input [7:0] b_to_clk_levm1; input [7:0] c_com_levs10; input [7:0] d_to_clk_levm2; input [7:0] one; output [7:0] m_from_clk_lev1_r; output [7:0] n_from_clk_lev2; output [7:0] o_from_com_levs11; output [7:0] o_from_comandclk_levs12; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [7:0] m_from_clk_lev1_r; // End of automatics // surefire lint_off ASWEBB // surefire lint_off ASWEMB wire [7:0] a_to_clk_levm1; wire [7:0] a_to_clk_levm2; wire [7:0] c_com_levs11; reg [7:0] o_from_comandclk_levs12; wire [7:0] n_from_clk_lev2; wire [7:0] n_from_clk_lev3; assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2; assign a_to_clk_levm2 = a_to_clk_levm3 + 0; always @ (posedge clk) begin m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1; end assign c_com_levs11 = c_com_levs10 + one; always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3; assign n_from_clk_lev2 = m_from_clk_lev1_r; assign n_from_clk_lev3 = n_from_clk_lev2; wire [7:0] o_from_com_levs11 = c_com_levs10 + 1; endmodule verilator-4.038/test_regress/t/t_lint_in_inc_bad_2.vh0000664000177100017500000000041213702133370022662 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module x; // Syntax error if if if; endmodule verilator-4.038/test_regress/t/t_trace_cat.v0000664000177100017500000000055013702133370021126 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire clk ); integer cyc; initial cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; end endmodule verilator-4.038/test_regress/t/t_unopt_converge.v0000664000177100017500000000071413702133370022240 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs x, // Inputs clk ); `ifdef ALLOW_UNOPT /*verilator lint_off UNOPTFLAT*/ `endif input clk; output x; // Avoid eliminating x reg x; always @* begin x = ~x; end endmodule verilator-4.038/test_regress/t/t_display_real.pl0000775000177100017500000000113413702133370022021 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_no_parentheses.v0000664000177100017500000000274713702133370023410 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // This is a copy of t_param.v with the parentheses around the module parameters // removed. module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; m1 #PAR m1(); m3 #PAR m3(); mnooverride #10 mno(); input clk; integer cyc=1; reg [4:0] bitsel; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin bitsel = 0; if (PAR[bitsel]!==1'b1) $stop; bitsel = 1; if (PAR[bitsel]!==1'b1) $stop; bitsel = 2; if (PAR[bitsel]!==1'b0) $stop; end if (cyc==1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module m1; localparam PAR1MINUS1 = PAR1DUP-2-1; localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly parameter PAR1 = 0; m2 #PAR1MINUS1 m2 (); endmodule module m2; parameter PAR2 = 10; initial begin $display("%x",PAR2); if (PAR2 !== 2) $stop; end endmodule module m3; localparam LOC = 13; parameter PAR = 10; initial begin $display("%x %x",LOC,PAR); if (LOC !== 13) $stop; if (PAR !== 3) $stop; end endmodule module mnooverride; localparam LOC = 13; parameter PAR = 10; initial begin $display("%x %x",LOC,PAR); if (LOC !== 13) $stop; if (PAR !== 10) $stop; end endmodule verilator-4.038/test_regress/t/t_chg_first.pl0000775000177100017500000000105313702133367021327 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_local.pl0000775000177100017500000000105313702133370021623 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_bitsel_struct2.v0000664000177100017500000000303513702133367022160 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); typedef struct packed { logic [3:2] a; logic [5:4][3:2] b; } ab_t; typedef ab_t [7:6] c_t; // array of structs typedef struct packed { c_t [17:16] d; } e_t; `define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); initial begin e_t e; `checkh($bits(ab_t),6); `checkh($bits(c_t),12); `checkh($bits(e_t),24); `checkh($bits(e), 24); `checkh($bits(e.d[17]),12); `checkh($bits(e.d[16][6]),6); `checkh($bits(e.d[16][6].b[5]),2); `checkh($bits(e.d[16][6].b[5][2]), 1); // e = 24'b101101010111010110101010; `checkb(e, 24'b101101010111010110101010); e.d[17] = 12'b111110011011; `checkb(e, 24'b111110011011010110101010); e.d[16][6] = 6'b010101; `checkb(e, 24'b111110011011010110010101); e.d[16][6].b[5] = 2'b10; `checkb(e, 24'b111110011011010110011001); e.d[16][6].b[5][2] = 1'b1; // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_initial_edge.pl0000775000177100017500000000113013702133370021762 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--x-initial-edge"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_qw.pl0000775000177100017500000000122113702133370020631 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2011 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["t/t_dpi_qw_c.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME -no-l2name"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_modport_import.v0000664000177100017500000000166413702133370024306 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test of the import parameter used with modport // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 interface test_if; // Interface variable logic data; // Modport modport mp( import myfunc, output data ); function automatic logic myfunc (input logic val); begin myfunc = (val == 1'b0); end endfunction endinterface // test_if module t (/*AUTOARG*/ // Inputs clk ); input clk; test_if i (); testmod testmod_i (.clk (clk), .i (i.mp)); endmodule module testmod ( input clk, test_if.mp i ); always @(posedge clk) begin i.data = 1'b0; if (i.myfunc (1'b0)) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-4.038/test_regress/t/t_param.pl0000775000177100017500000000105313702133370020451 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_l.pl0000775000177100017500000000105313702133370021331 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_comp.v0000664000177100017500000000073513702133367021533 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); if (0) begin $info("User compile-time info"); $warning("User compile-time warning"); $error("User compile-time error"); end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_life.pl0000775000177100017500000000143213702133370021141 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats"], ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Lifetime assign deletions\s+(\d+)/i, 4); file_grep($Self->{stats}, qr/Optimizations, Lifetime constant prop\s+(\d+)/i, 2); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_defaults.v0000664000177100017500000000124013702133370022020 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed // default function argument // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 parameter logic Bar = 1'b1; function automatic logic calc_y; return 1'b1; endfunction function automatic logic [1:0] foo ( input logic x = Bar, input logic y = calc_y() ); return x + y; endfunction module t (/*AUTOARG*/); logic [1:0] foo_val; initial begin foo_val = foo(); if (foo_val != 2'b10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_grey.v0000664000177100017500000000302213702133370021157 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // surefire lint_off _NETNM // surefire lint_off STMINI input clk; integer _mode; initial _mode = 0; wire [2:0] b3; reg [2:0] g3; wire [5:0] b6; reg [5:0] g6; t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3)); t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6)); always @ (posedge clk) begin if (_mode==0) begin _mode <= 1; g3 <= 3'b101; g6 <= 6'b110101; end else if (_mode==1) begin if (b3 !== 3'b110) $stop; if (b6 !== 6'b100110) $stop; _mode <= 2; $write("*-* All Finished *-*\n"); $finish; end end endmodule // Module gray2bin // convert an arbitrary width gray coded number to binary. The conversion // of a 4 bit gray (represented as "g") to binary ("b") would go as follows: // b[3] = ^g[3] = g[3] // b[2] = ^g[3:2] // b[1] = ^g[3:1] // b[0] = ^g[3:[SZ-1:0] cur0] module t_func_grey2bin (/*AUTOARG*/ // Outputs b, // Inputs g ); // surefire lint_off STMFOR parameter SZ = 5; output [SZ-1:0] b; input [SZ-1:0] g; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [SZ-1:0] b; // End of automatics integer i; always @(/*AUTOSENSE*/g) for (i=0; i> i); // surefire lint_off_line LATASS endmodule verilator-4.038/test_regress/t/t_tri_pull2_bad.pl0000775000177100017500000000111313702133370022070 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_language.v0000664000177100017500000000061213702133370021754 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); // See also t_preproc_kwd.v integer bit; initial bit = 1; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_mismodport_bad.pl0000775000177100017500000000107413702133370024377 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_while.pl0000775000177100017500000000104613702133370021476 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--trace"], ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_missing.pl0000775000177100017500000000110213702133370022052 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only --Wall -Wno-DECLFILENAME"], ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_mod_paren_bad.pl0000775000177100017500000000116413702133370023154 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_type_pins.v0000664000177100017500000000620513702133370022242 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: System Verilog test of enumerated type methods // // This code exercises the various enumeration methods // // This file ONLY is placed into the Public Domain, for any use, without // warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. // **** Pin Identifiers **** typedef enum int { PINID_A0 = 32'd0, // MUST BE ZERO! // - Standard Ports - PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7, PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7, PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7, PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7, PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7, PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7, PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7, PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7, // PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1 PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7, PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7, PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7, PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7, PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7, // PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0 PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7, PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7, PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7, // - AUX Port (Custom) - PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7, // - PDI Port - PINID_D2W_DAT, PINID_D2W_CLK, // - Power Pins - PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3, PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3, // - Maximum number of pins - PINID_MAX } t_pinid; module t (/*AUTOARG*/ // Inputs clk ); input clk; wire a = clk; wire b = 1'b0; reg c; test test_i (/*AUTOINST*/ // Inputs .clk (clk)); // This is a compile time only test. Immediately finish always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module test (/*AUTOARG*/ // Inputs clk ); input clk; // Use the enumeration size to initialize a dynamic array t_pinid e; int myarray1 [] = new [e.num]; always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Enumeration has %d members\n", e.num); `endif e = e.first; forever begin myarray1[e] <= e.prev; `ifdef TEST_VERBOSE $write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]); `endif if (e == e.last) begin break; end else begin e = e.next; end end end endmodule verilator-4.038/test_regress/t/t_inst_dtree_inlbc.pl0000775000177100017500000000125113702133370022660 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_B +define+INLINE_C'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_width_genfor.pl0000775000177100017500000000101613702133370023055 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all}; scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_lint_import_name2_bad.v0000664000177100017500000000040013702133370023423 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 import missing::sigs; import missing::*; verilator-4.038/test_regress/t/t_func_v_noinl.pl0000775000177100017500000000116713702133370022036 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_func_v.v"); compile( v_flags2 => ['+define+T_FUNC_V_NOINL',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_typedef_port.v0000664000177100017500000000446113702133370021712 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef reg [2:0] threeansi_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef reg [2:0] three_t; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = crc[2:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) threeansi_t outa; // From testa of TestAnsi.v three_t outna; // From test of TestNonAnsi.v // End of automatics TestNonAnsi test (// Outputs .out (outna), /*AUTOINST*/ // Inputs .clk (clk), .in (in)); TestAnsi testa (// Outputs .out (outa), /*AUTOINST*/ // Inputs .clk (clk), .in (in)); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, outna, 1'b0, outa}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h018decfea0a8828a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module TestNonAnsi (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); typedef reg [2:0] three_t; input clk; input three_t in; output three_t out; always @(posedge clk) begin out <= ~in; end endmodule module TestAnsi ( input clk, input threeansi_t in, output threeansi_t out ); always @(posedge clk) begin out <= ~in; end endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-4.038/test_regress/t/t_metacmt_onoff.out0000664000177100017500000000153413702133370022367 0ustar wsnyderwsnyder%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:8: Little bit endian vector: MSB < LSB of bit range: 0:1 : ... In instance t 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; | ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-LITENDIAN: t/t_metacmt_onoff.v:8:109: Little bit endian vector: MSB < LSB of bit range: 0:3 : ... In instance t 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_inst_mism.pl0000775000177100017500000000105313702133370021353 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_vpi_1ps1fs.pl0000775000177100017500000000151213702133370022362 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator_st => 1); top_filename("t/t_time_vpi.v"); $Self->{main_time_multiplier} = 1e-12 / 10e-15; compile( v_flags2 => ['+define+time_scale_units=1ps +define+time_scale_prec=1fs', 't/t_time_vpi_c.cpp'], verilator_flags2 => ['--vpi'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_tree_inl1_pub0.vlt0000664000177100017500000000036113702133370023406 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config inline -module "l*" verilator-4.038/test_regress/t/t_math_shortreal.pl0000775000177100017500000000105313702133370022365 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_typedef_package.v0000664000177100017500000000075313702133370022321 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 package pkg1; typedef logic [7:0] uint8_t; endpackage package pkg2; typedef enum pkg1::uint8_t { a = 8'd1, b = 8'd2 } opts; endpackage module t (/*AUTOARG*/); initial begin $display("%d", pkg2::a); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_select_plus.pl0000775000177100017500000000105313702133370021673 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_altera_lpm_latch.pl0000775000177100017500000000120613702133367022652 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_size_bad.pl0000775000177100017500000000107413702133370023154 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_dotted1_inl0.pl0000775000177100017500000000117713702133370022516 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_var_dotted1.v"); compile( v_flags2 => ['+define+NOUSE_INLINE',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_parameter_bad.out0000664000177100017500000000017013702133370023320 0ustar wsnyderwsnyder%Error: Parameters from the command line were not found in the design: PARAM_THAT_DOES_NON_EXIST %Error: Exiting due to verilator-4.038/test_regress/t/t_math_strwidth.v0000664000177100017500000000075013702133370022064 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008-2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg [4*8:1] strg; initial begin strg = "CHK"; if (strg != "CHK") $stop; if (strg == "JOE") $stop; $write("String = %s = %x\n", strg, strg); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_mem_twoedge.v0000664000177100017500000000521213702133370021475 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // verilator lint_off MULTIDRIVEN /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v wire [15:0] out2; // From test of Test.v // End of automatics // verilator lint_on MULTIDRIVEN Test test ( .en (crc[21:20]), .a1 (crc[19:18]), .a0 (crc[17:16]), .d1 (crc[15:8]), .d0 (crc[7:0]), /*AUTOINST*/ // Outputs .out (out[31:0]), .out2 (out2[15:0]), // Inputs .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {out2, 16'h0, out}; // Test loop `ifdef TEST_VERBOSE always @ (negedge clk) begin $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); end `endif always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; test.clear(); end else if (cyc<10) begin sum <= 64'h0; test.clear(); end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc68a94a34ec970aa if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, out2, // Inputs clk, en, a0, a1, d0, d1 ); input clk; input [1:0] en; input [1:0] a0; input [1:0] a1; input [7:0] d0; input [7:0] d1; output reg [31:0] out; output reg [15:0] out2; // verilator lint_off MULTIDRIVEN reg [7:0] mem [4]; // verilator lint_on MULTIDRIVEN task clear(); for (int i=0; i<4; ++i) mem[i] = 0; endtask always @(posedge clk) begin if (en[0]) begin mem[a0] <= d0; out2[7:0] <= d0; end end always @(negedge clk) begin if (en[1]) begin mem[a1] <= d1; out2[15:8] <= d0; end end assign out = {mem[3],mem[2],mem[1],mem[0]}; endmodule verilator-4.038/test_regress/t/t_lint_defparam_bad.pl0000775000177100017500000000124713702133370022771 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_lint_defparam.v"); lint( verilator_flags2 => ["--lint-only -Wwarn-style -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vams_wreal.v0000664000177100017500000000541613702133370021347 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" module t (/*autoarg*/ // Inputs clk, in ); input clk; input [15:0] in; wreal aout; integer cyc=0; real vin; wreal vpass; through through (.vin, .vpass); real gnd; wire out; within_range within_range (/*AUTOINST*/ // Interfaces .vpass (vpass), .gnd (gnd), // Outputs .out (out)); // wreal bus declaration wreal vin_upper_bus[1:0]; // wreal nets declaration wreal vout_split_0; wreal vout_split_1; wreal_bus wreal_bus( .vin_bus(vin_upper_bus[1:0]), .vout_split_0(vout_split_0), .vout_split_1(vout_split_1)); // implicit declaration of wreal `ifdef VERILATOR wreal wreal_implicit_net; // implicit declaration of wreal not supported yet `endif // verilator lint_off IMPLICIT first_level first_level(.in(cyc[0]), .out(wreal_implicit_net)); // verilator lint_on IMPLICIT parameter real lsb = 1; // verilator lint_off WIDTH assign aout = $itor(in) * lsb; // verilator lint_on WIDTH always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n",$time, cyc, out, vin, gnd, within_range.in_int); `endif if (cyc==0) begin // Setup gnd = 0.0; vin = 0.2; end else if (cyc==2) begin if (out != 0) $stop; end else if (cyc==3) begin gnd = 0.0; vin = 0.6; end else if (cyc==4) begin if (out != 1) $stop; end else if (cyc==5) begin gnd = 0.6; vin = 0.8; end else if (cyc==6) begin if (out != 0) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module through (input wreal vin, output wreal vpass); assign vpass = vin; endmodule module within_range (input wreal vpass, input wreal gnd, output out); parameter real V_MIN = 0.5; parameter real V_MAX = 10; wreal in_int = vpass - gnd; assign out = (V_MIN <= in_int && in_int <= V_MAX); endmodule module wreal_bus (input wreal vin_bus [1:0], output wreal vout_split_0, output wreal vout_split_1); assign vout_split_0 = vin_bus[0]; assign vout_split_1 = vin_bus[1]; endmodule module first_level (input in, `ifdef VERILATOR output wreal out `else output out // Implicity becomes real `endif ); second_level second_level(.in(in), .out(out)); endmodule module second_level(in, out); input in; output out; wreal out; assign out = in ? 1.23456: 7.8910; endmodule verilator-4.038/test_regress/t/t_trace_two_hdr_sc.pl0000775000177100017500000000245313702133370022667 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if (!$Self->have_sc) { skip("No SystemC installed"); } else { top_filename("t_trace_two_a.v"); compile( make_main => 0, verilator_make_gmake => 0, top_filename => 't_trace_two_b.v', VM_PREFIX => 'Vt_trace_two_b', verilator_flags2 => ['-sc -trace'], ); compile( make_main => 0, top_filename => 't_trace_two_a.v', make_flags => 'CPPFLAGS_ADD=-DTEST_HDR_TRACE', verilator_flags2 => ['-sc', '-exe', '-trace', "$Self->{t_dir}/t_trace_two_sc.cpp"], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } } ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_input_type.v0000664000177100017500000010126713702133370023075 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `define NO_INTEGER `define NO_SHORTREAL `endif `ifdef MS `endif `ifdef VERILATOR `define NO_SHORTREAL `define NULL 64'd0 `else `define NULL null `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef VERILATOR wire _unused = &{1'b0, clk}; `endif // Legal input argument types for DPI functions //====================================================================== // Type definitions //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 typedef byte byte_t; typedef byte unsigned byte_unsigned_t; typedef shortint shortint_t; typedef shortint unsigned shortint_unsigned_t; typedef int int_t; typedef int unsigned int_unsigned_t; typedef longint longint_t; typedef longint unsigned longint_unsigned_t; `ifndef NO_TIME typedef time time_t; `endif `ifndef NO_INTEGER typedef integer integer_t; `endif typedef real real_t; `ifndef NO_SHORTREAL typedef shortreal shortreal_t; `endif typedef chandle chandle_t; typedef string string_t; typedef bit bit_t; typedef logic logic_t; // 2-state packed structures typedef struct packed { bit x; } struct_2_state_1; typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; // 2-state packed unions typedef union packed { bit x; bit y; } union_2_state_1; typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; // 4-state packed structures typedef struct packed { logic x; } struct_4_state_1; typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; // 4-state packed unions typedef union packed { logic x; bit y; } union_4_state_1; typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; //====================================================================== // Imports //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 import "DPI-C" function void i_byte (input byte i); import "DPI-C" function void i_byte_unsigned (input byte unsigned i); import "DPI-C" function void i_shortint (input shortint i); import "DPI-C" function void i_shortint_unsigned (input shortint unsigned i); import "DPI-C" function void i_int (input int i); import "DPI-C" function void i_int_unsigned (input int unsigned i); import "DPI-C" function void i_longint (input longint i); import "DPI-C" function void i_longint_unsigned (input longint unsigned i); `ifndef NO_TIME import "DPI-C" function void i_time (input time i); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer (input integer i); `endif import "DPI-C" function void i_real (input real i); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal (input shortreal i); `endif import "DPI-C" function void i_chandle (input chandle i); import "DPI-C" function void i_string (input string i); import "DPI-C" function void i_bit (input bit i); import "DPI-C" function void i_logic (input logic i); // Basic types via typedef import "DPI-C" function void i_byte_t (input byte_t i); import "DPI-C" function void i_byte_unsigned_t (input byte_unsigned_t i); import "DPI-C" function void i_shortint_t (input shortint_t i); import "DPI-C" function void i_shortint_unsigned_t (input shortint_unsigned_t i); import "DPI-C" function void i_int_t (input int_t i); import "DPI-C" function void i_int_unsigned_t (input int_unsigned_t i); import "DPI-C" function void i_longint_t (input longint_t i); import "DPI-C" function void i_longint_unsigned_t (input longint_unsigned_t i); `ifndef NO_TIME import "DPI-C" function void i_time_t (input time_t i); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer_t (input integer_t i); `endif import "DPI-C" function void i_real_t (input real_t i); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal_t (input shortreal_t i); `endif import "DPI-C" function void i_chandle_t (input chandle_t i); import "DPI-C" function void i_string_t (input string_t i); import "DPI-C" function void i_bit_t (input bit_t i); import "DPI-C" function void i_logic_t (input logic_t i); // 2-state packed arrays import "DPI-C" function void i_array_2_state_1 (input bit [ 0:0] i); import "DPI-C" function void i_array_2_state_32 (input bit [ 31:0] i); import "DPI-C" function void i_array_2_state_33 (input bit [ 32:0] i); import "DPI-C" function void i_array_2_state_64 (input bit [ 63:0] i); import "DPI-C" function void i_array_2_state_65 (input bit [ 64:0] i); import "DPI-C" function void i_array_2_state_128(input bit [127:0] i); // 2-state packed structures import "DPI-C" function void i_struct_2_state_1 (input struct_2_state_1 i); import "DPI-C" function void i_struct_2_state_32 (input struct_2_state_32 i); import "DPI-C" function void i_struct_2_state_33 (input struct_2_state_33 i); import "DPI-C" function void i_struct_2_state_64 (input struct_2_state_64 i); import "DPI-C" function void i_struct_2_state_65 (input struct_2_state_65 i); import "DPI-C" function void i_struct_2_state_128 (input struct_2_state_128 i); // 2-state packed unions import "DPI-C" function void i_union_2_state_1 (input union_2_state_1 i); import "DPI-C" function void i_union_2_state_32 (input union_2_state_32 i); import "DPI-C" function void i_union_2_state_33 (input union_2_state_33 i); import "DPI-C" function void i_union_2_state_64 (input union_2_state_64 i); import "DPI-C" function void i_union_2_state_65 (input union_2_state_65 i); import "DPI-C" function void i_union_2_state_128(input union_2_state_128 i); // 4-state packed arrays import "DPI-C" function void i_array_4_state_1 (input logic [ 0:0] i); import "DPI-C" function void i_array_4_state_32 (input logic [ 31:0] i); import "DPI-C" function void i_array_4_state_33 (input logic [ 32:0] i); import "DPI-C" function void i_array_4_state_64 (input logic [ 63:0] i); import "DPI-C" function void i_array_4_state_65 (input logic [ 64:0] i); import "DPI-C" function void i_array_4_state_128(input logic [127:0] i); // 4-state packed structures import "DPI-C" function void i_struct_4_state_1 (input struct_4_state_1 i); import "DPI-C" function void i_struct_4_state_32 (input struct_4_state_32 i); import "DPI-C" function void i_struct_4_state_33 (input struct_4_state_33 i); import "DPI-C" function void i_struct_4_state_64 (input struct_4_state_64 i); import "DPI-C" function void i_struct_4_state_65 (input struct_4_state_65 i); import "DPI-C" function void i_struct_4_state_128 (input struct_4_state_128 i); // 4-state packed unions import "DPI-C" function void i_union_4_state_1 (input union_4_state_1 i); import "DPI-C" function void i_union_4_state_32 (input union_4_state_32 i); import "DPI-C" function void i_union_4_state_33 (input union_4_state_33 i); import "DPI-C" function void i_union_4_state_64 (input union_4_state_64 i); import "DPI-C" function void i_union_4_state_65 (input union_4_state_65 i); import "DPI-C" function void i_union_4_state_128(input union_4_state_128 i); //====================================================================== // Exports //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 export "DPI-C" function e_byte; export "DPI-C" function e_byte_unsigned; export "DPI-C" function e_shortint; export "DPI-C" function e_shortint_unsigned; export "DPI-C" function e_int; export "DPI-C" function e_int_unsigned; export "DPI-C" function e_longint; export "DPI-C" function e_longint_unsigned; `ifndef NO_TIME export "DPI-C" function e_time; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer; `endif export "DPI-C" function e_real; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal; `endif export "DPI-C" function e_chandle; export "DPI-C" function e_string; export "DPI-C" function e_bit; export "DPI-C" function e_logic; // Basic types via typedef export "DPI-C" function e_byte_t; export "DPI-C" function e_byte_unsigned_t; export "DPI-C" function e_shortint_t; export "DPI-C" function e_shortint_unsigned_t; export "DPI-C" function e_int_t; export "DPI-C" function e_int_unsigned_t; export "DPI-C" function e_longint_t; export "DPI-C" function e_longint_unsigned_t; `ifndef NO_TIME export "DPI-C" function e_time_t; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer_t; `endif export "DPI-C" function e_real_t; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_t; `endif export "DPI-C" function e_chandle_t; export "DPI-C" function e_string_t; export "DPI-C" function e_bit_t; export "DPI-C" function e_logic_t; // 2-state packed arrays export "DPI-C" function e_array_2_state_1; export "DPI-C" function e_array_2_state_32; export "DPI-C" function e_array_2_state_33; export "DPI-C" function e_array_2_state_64; export "DPI-C" function e_array_2_state_65; export "DPI-C" function e_array_2_state_128; // 2-state packed structures export "DPI-C" function e_struct_2_state_1; export "DPI-C" function e_struct_2_state_32; export "DPI-C" function e_struct_2_state_33; export "DPI-C" function e_struct_2_state_64; export "DPI-C" function e_struct_2_state_65; export "DPI-C" function e_struct_2_state_128; // 2-state packed unions export "DPI-C" function e_union_2_state_1; export "DPI-C" function e_union_2_state_32; export "DPI-C" function e_union_2_state_33; export "DPI-C" function e_union_2_state_64; export "DPI-C" function e_union_2_state_65; export "DPI-C" function e_union_2_state_128; // 4-state packed arrays export "DPI-C" function e_array_4_state_1; export "DPI-C" function e_array_4_state_32; export "DPI-C" function e_array_4_state_33; export "DPI-C" function e_array_4_state_64; export "DPI-C" function e_array_4_state_65; export "DPI-C" function e_array_4_state_128; // 4-state packed structures export "DPI-C" function e_struct_4_state_1; export "DPI-C" function e_struct_4_state_32; export "DPI-C" function e_struct_4_state_33; export "DPI-C" function e_struct_4_state_64; export "DPI-C" function e_struct_4_state_65; export "DPI-C" function e_struct_4_state_128; // 4-state packed unions export "DPI-C" function e_union_4_state_1; export "DPI-C" function e_union_4_state_32; export "DPI-C" function e_union_4_state_33; export "DPI-C" function e_union_4_state_64; export "DPI-C" function e_union_4_state_65; export "DPI-C" function e_union_4_state_128; //====================================================================== // Definitions of exported functions //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 byte n_byte = 0; function void e_byte(input byte i); if (i !== 8'd10 + n_byte) $stop; n_byte++; endfunction byte n_byte_unsigned = 0; function void e_byte_unsigned(input byte unsigned i); if (i !== 8'd20 + n_byte_unsigned) $stop; n_byte_unsigned++; endfunction shortint n_shortint = 0; function void e_shortint(input shortint i); if (i !== 16'd30 + n_shortint) $stop; n_shortint++; endfunction shortint n_shortint_unsigned = 0; function void e_shortint_unsigned(input shortint unsigned i); if (i !== 16'd40 + n_shortint_unsigned) $stop; n_shortint_unsigned++; endfunction int n_int = 0; function void e_int(input int i); if (i !== 32'd50 + n_int) $stop; n_int++; endfunction int n_int_unsigned = 0; function void e_int_unsigned(input int unsigned i); if (i !== 32'd60 + n_int_unsigned) $stop; n_int_unsigned++; endfunction longint n_longint = 0; function void e_longint(input longint i); if (i !== 64'd70 + n_longint) $stop; n_longint++; endfunction longint n_longint_unsigned = 0; function void e_longint_unsigned(input longint unsigned i); if (i !== 64'd80 + n_longint_unsigned) $stop; n_longint_unsigned++; endfunction `ifndef NO_TIME longint n_time = 0; function void e_time(input time i); if (i !== 64'd90 + n_time) $stop; n_time++; endfunction `endif `ifndef NO_INTEGER int n_integer = 0; function void e_integer(input integer i); if (i !== 32'd100 + n_integer) $stop; n_integer++; endfunction `endif int n_real = 0; function void e_real(input real i); if (i != real'(2*n_real + 1) / 2.0) $stop; n_real++; endfunction `ifndef NO_SHORTREAL int n_shortreal = 0; function void e_shortreal(input shortreal i); if (i != shortreal'(4*n_shortreal + 1)/ 4.0) $stop; n_shortreal++; endfunction `endif int n_chandle = 0; function void e_chandle(input chandle i); $display("e_chandle %1d", n_chandle); if (!n_chandle[0]) begin if (i !== `NULL) $stop; end else begin if (i === `NULL) $stop; end n_chandle++; endfunction int n_string = 0; function void e_string(input string i); $display("e_string %1d", n_string); if (!n_string[0]) begin if (i != "Hello") $stop; end else begin if (i != "World") $stop; end n_string++; endfunction int n_bit = 0; function void e_bit(input bit i); $display("e_bit %1d", n_bit); if (i !== n_bit[0]) $stop; n_bit++; endfunction int n_logic = 0; function void e_logic(input logic i); $display("e_logic %1d", n_logic); if (i !== ~n_logic[0]) $stop; n_logic++; endfunction // Basic types via typedefs byte_t n_byte_t = 0; function void e_byte_t(input byte_t i); if (i !== 8'd10 + n_byte_t) $stop; n_byte_t += 2; endfunction byte n_byte_unsigned_t = 0; function void e_byte_unsigned_t(input byte_unsigned_t i); if (i !== 8'd20 + n_byte_unsigned_t) $stop; n_byte_unsigned_t += 2; endfunction shortint_t n_shortint_t = 0; function void e_shortint_t(input shortint_t i); if (i !== 16'd30 + n_shortint_t) $stop; n_shortint_t += 2; endfunction shortint n_shortint_unsigned_t = 0; function void e_shortint_unsigned_t(input shortint_unsigned_t i); if (i !== 16'd40 + n_shortint_unsigned_t) $stop; n_shortint_unsigned_t += 2; endfunction int_t n_int_t = 0; function void e_int_t(input int_t i); if (i !== 32'd50 + n_int_t) $stop; n_int_t += 2; endfunction int n_int_unsigned_t = 0; function void e_int_unsigned_t(input int_unsigned_t i); if (i !== 32'd60 + n_int_unsigned_t) $stop; n_int_unsigned_t += 2; endfunction longint_t n_longint_t = 0; function void e_longint_t(input longint_t i); if (i !== 64'd70 + n_longint_t) $stop; n_longint_t += 2; endfunction longint n_longint_unsigned_t = 0; function void e_longint_unsigned_t(input longint_unsigned_t i); if (i !== 64'd80 + n_longint_unsigned_t) $stop; n_longint_unsigned_t += 2; endfunction `ifndef NO_TIME longint n_time_t = 0; function void e_time_t(input time_t i); if (i !== 64'd90 + n_time_t) $stop; n_time_t += 2; endfunction `endif `ifndef NO_INTEGER int n_integer_t = 0; function void e_integer_t(input integer_t i); if (i !== 32'd100 + n_integer_t) $stop; n_integer_t += 2; endfunction `endif int n_real_t = 0; function void e_real_t(input real_t i); if (i != real'(2*n_real_t + 1) / 2.0) $stop; n_real_t += 2; endfunction `ifndef NO_SHORTREAL int n_shortreal_t = 0; function void e_shortreal_t(input shortreal_t i); if (i != shortreal'(4*n_shortreal_t + 1)/ 4.0) $stop; n_shortreal_t += 2; endfunction `endif int n_chandle_t = 0; function void e_chandle_t(input chandle_t i); $display("e_chandle_t %1d", n_chandle_t); if (!n_chandle_t[0]) begin if (i === `NULL) $stop; end else begin if (i !== `NULL) $stop; end n_chandle_t++; endfunction int n_string_t = 0; function void e_string_t(input string_t i); $display("e_string_t %1d", n_string_t); if (!n_string_t[0]) begin if (i != "World") $stop; end else begin if (i != "Hello") $stop; end n_string_t++; endfunction int n_bit_t = 0; function void e_bit_t(input bit_t i); $display("e_bit_t %1d", n_bit_t); if (i !== n_bit_t[0]) $stop; n_bit_t++; endfunction int n_logic_t = 0; function void e_logic_t(input logic_t i); $display("e_logic_t %1d", n_logic_t); if (i !== ~n_logic_t[0]) $stop; n_logic_t++; endfunction // 2-state packed arrays int n_array_2_state_1 = 0; function void e_array_2_state_1(input bit [ 0:0] i); $display("e_array_2_state_1 %1d", n_array_2_state_1); if (i !== n_array_2_state_1[0]) $stop; n_array_2_state_1++; endfunction int n_array_2_state_32 = 0; function void e_array_2_state_32(input bit [31:0] i); $display("e_array_2_state_32 %1d", n_array_2_state_32); if (i !== ~32'd0 >> n_array_2_state_32) $stop; n_array_2_state_32++; endfunction int n_array_2_state_33 = 0; function void e_array_2_state_33(input bit [32:0] i); $display("e_array_2_state_33 %1d", n_array_2_state_33); if (i !== ~33'd0 >> n_array_2_state_33) $stop; n_array_2_state_33++; endfunction int n_array_2_state_64 = 0; function void e_array_2_state_64(input bit [63:0] i); $display("e_array_2_state_64 %1d", n_array_2_state_64); if (i !== ~64'd0 >> n_array_2_state_64) $stop; n_array_2_state_64++; endfunction int n_array_2_state_65 = 0; function void e_array_2_state_65(input bit [64:0] i); $display("e_array_2_state_65 %1d", n_array_2_state_65); if (i !== ~65'd0 >> n_array_2_state_65) $stop; n_array_2_state_65++; endfunction int n_array_2_state_128 = 0; function void e_array_2_state_128(input bit [127:0] i); $display("e_array_2_state_128 %1d", n_array_2_state_128); if (i !== ~128'd0 >> n_array_2_state_128) $stop; n_array_2_state_128++; endfunction // 2-state packed structures int n_struct_2_state_1 = 0; function void e_struct_2_state_1(input struct_2_state_1 i); $display("e_struct_2_state_1 %1d", n_struct_2_state_1); if (i !== n_struct_2_state_1[0]) $stop; n_struct_2_state_1++; endfunction int n_struct_2_state_32 = 0; function void e_struct_2_state_32(input struct_2_state_32 i); $display("e_struct_2_state_32 %1d", n_struct_2_state_32); if (i !== ~32'd0 >> n_struct_2_state_32) $stop; n_struct_2_state_32++; endfunction int n_struct_2_state_33 = 0; function void e_struct_2_state_33(input struct_2_state_33 i); $display("e_struct_2_state_33 %1d", n_struct_2_state_33); if (i !== ~33'd0 >> n_struct_2_state_33) $stop; n_struct_2_state_33++; endfunction int n_struct_2_state_64 = 0; function void e_struct_2_state_64(input struct_2_state_64 i); $display("e_struct_2_state_64 %1d", n_struct_2_state_64); if (i !== ~64'd0 >> n_struct_2_state_64) $stop; n_struct_2_state_64++; endfunction int n_struct_2_state_65 = 0; function void e_struct_2_state_65(input struct_2_state_65 i); $display("e_struct_2_state_65 %1d", n_struct_2_state_65); if (i !== ~65'd0 >> n_struct_2_state_65) $stop; n_struct_2_state_65++; endfunction int n_struct_2_state_128 = 0; function void e_struct_2_state_128(input struct_2_state_128 i); $display("e_struct_2_state_128 %1d", n_struct_2_state_128); if (i !== ~128'd0 >> n_struct_2_state_128) $stop; n_struct_2_state_128++; endfunction // 2-state packed unions int n_union_2_state_1 = 0; function void e_union_2_state_1(input union_2_state_1 i); $display("e_union_2_state_1 %1d", n_union_2_state_1); if (i !== n_union_2_state_1[0]) $stop; n_union_2_state_1++; endfunction int n_union_2_state_32 = 0; function void e_union_2_state_32(input union_2_state_32 i); $display("e_union_2_state_32 %1d", n_union_2_state_32); if (i !== ~32'd0 >> n_union_2_state_32) $stop; n_union_2_state_32++; endfunction int n_union_2_state_33 = 0; function void e_union_2_state_33(input union_2_state_33 i); $display("e_union_2_state_33 %1d", n_union_2_state_33); if (i !== ~33'd0 >> n_union_2_state_33) $stop; n_union_2_state_33++; endfunction int n_union_2_state_64 = 0; function void e_union_2_state_64(input union_2_state_64 i); $display("e_union_2_state_64 %1d", n_union_2_state_64); if (i !== ~64'd0 >> n_union_2_state_64) $stop; n_union_2_state_64++; endfunction int n_union_2_state_65 = 0; function void e_union_2_state_65(input union_2_state_65 i); $display("e_union_2_state_65 %1d", n_union_2_state_65); if (i !== ~65'd0 >> n_union_2_state_65) $stop; n_union_2_state_65++; endfunction int n_union_2_state_128 = 0; function void e_union_2_state_128(input union_2_state_128 i); $display("e_union_2_state_128 %1d", n_union_2_state_128); if (i !== ~128'd0 >> n_union_2_state_128) $stop; n_union_2_state_128++; endfunction // 4-state packed arrays int n_array_4_state_1 = 0; function void e_array_4_state_1(input logic [ 0:0] i); $display("e_array_4_state_1 %1d", n_array_4_state_1); if (i !== n_array_4_state_1[0]) $stop; n_array_4_state_1++; endfunction int n_array_4_state_32 = 0; function void e_array_4_state_32(input logic [31:0] i); $display("e_array_4_state_32 %1d", n_array_4_state_32); if (i !== ~32'd0 >> n_array_4_state_32) $stop; n_array_4_state_32++; endfunction int n_array_4_state_33 = 0; function void e_array_4_state_33(input logic [32:0] i); $display("e_array_4_state_33 %1d", n_array_4_state_33); if (i !== ~33'd0 >> n_array_4_state_33) $stop; n_array_4_state_33++; endfunction int n_array_4_state_64 = 0; function void e_array_4_state_64(input logic [63:0] i); $display("e_array_4_state_64 %1d", n_array_4_state_64); if (i !== ~64'd0 >> n_array_4_state_64) $stop; n_array_4_state_64++; endfunction int n_array_4_state_65 = 0; function void e_array_4_state_65(input logic [64:0] i); $display("e_array_4_state_65 %1d", n_array_4_state_65); if (i !== ~65'd0 >> n_array_4_state_65) $stop; n_array_4_state_65++; endfunction int n_array_4_state_128 = 0; function void e_array_4_state_128(input logic [127:0] i); $display("e_array_4_state_128 %1d", n_array_4_state_128); if (i !== ~128'd0 >> n_array_4_state_128) $stop; n_array_4_state_128++; endfunction // 4-state packed structures int n_struct_4_state_1 = 0; function void e_struct_4_state_1(input struct_4_state_1 i); $display("e_struct_4_state_1 %1d", n_struct_4_state_1); if (i !== n_struct_4_state_1[0]) $stop; n_struct_4_state_1++; endfunction int n_struct_4_state_32 = 0; function void e_struct_4_state_32(input struct_4_state_32 i); $display("e_struct_4_state_32 %1d", n_struct_4_state_32); if (i !== ~32'd0 >> n_struct_4_state_32) $stop; n_struct_4_state_32++; endfunction int n_struct_4_state_33 = 0; function void e_struct_4_state_33(input struct_4_state_33 i); $display("e_struct_4_state_33 %1d", n_struct_4_state_33); if (i !== ~33'd0 >> n_struct_4_state_33) $stop; n_struct_4_state_33++; endfunction int n_struct_4_state_64 = 0; function void e_struct_4_state_64(input struct_4_state_64 i); $display("e_struct_4_state_64 %1d", n_struct_4_state_64); if (i !== ~64'd0 >> n_struct_4_state_64) $stop; n_struct_4_state_64++; endfunction int n_struct_4_state_65 = 0; function void e_struct_4_state_65(input struct_4_state_65 i); $display("e_struct_4_state_65 %1d", n_struct_4_state_65); if (i !== ~65'd0 >> n_struct_4_state_65) $stop; n_struct_4_state_65++; endfunction int n_struct_4_state_128 = 0; function void e_struct_4_state_128(input struct_4_state_128 i); $display("e_struct_4_state_128 %1d", n_struct_4_state_128); if (i !== ~128'd0 >> n_struct_4_state_128) $stop; n_struct_4_state_128++; endfunction // 4-state packed unions int n_union_4_state_1 = 0; function void e_union_4_state_1(input union_4_state_1 i); $display("e_union_4_state_1 %1d", n_union_4_state_1); if (i !== n_union_4_state_1[0]) $stop; n_union_4_state_1++; endfunction int n_union_4_state_32 = 0; function void e_union_4_state_32(input union_4_state_32 i); $display("e_union_4_state_32 %1d", n_union_4_state_32); if (i !== ~32'd0 >> n_union_4_state_32) $stop; n_union_4_state_32++; endfunction int n_union_4_state_33 = 0; function void e_union_4_state_33(input union_4_state_33 i); $display("e_union_4_state_33 %1d", n_union_4_state_33); if (i !== ~33'd0 >> n_union_4_state_33) $stop; n_union_4_state_33++; endfunction int n_union_4_state_64 = 0; function void e_union_4_state_64(input union_4_state_64 i); $display("e_union_4_state_64 %1d", n_union_4_state_64); if (i !== ~64'd0 >> n_union_4_state_64) $stop; n_union_4_state_64++; endfunction int n_union_4_state_65 = 0; function void e_union_4_state_65(input union_4_state_65 i); $display("e_union_4_state_65 %1d", n_union_4_state_65); if (i !== ~65'd0 >> n_union_4_state_65) $stop; n_union_4_state_65++; endfunction int n_union_4_state_128 = 0; function void e_union_4_state_128(input union_4_state_128 i); $display("e_union_4_state_128 %1d", n_union_4_state_128); if (i !== ~128'd0 >> n_union_4_state_128) $stop; n_union_4_state_128++; endfunction //====================================================================== // Invoke all functions 3 times (they have side effects) //====================================================================== import "DPI-C" context function void check_exports(); initial begin for (int i = 0 ; i < 3; i++) begin // Check the imports // Basic types as per IEEE 1800-2017 35.5.6 i_byte( 8'd10 - 8'(i)); i_byte_unsigned( 8'd20 - 8'(i)); i_shortint( 16'd30 - 16'(i)); i_shortint_unsigned( 16'd40 - 16'(i)); i_int( 32'd50 - 32'(i)); i_int_unsigned( 32'd60 - 32'(i)); i_longint( 64'd70 - 64'(i)); i_longint_unsigned( 64'd80 - 64'(i)); `ifndef NO_TIME i_time( 64'd90 - 64'(i)); `endif `ifndef NO_INTEGER i_integer( 32'd100- 32'(i)); `endif i_real( -1.0*i - 0.50); `ifndef NO_SHORTREAL i_shortreal( -1.0*i - 0.25); `endif if (~i[0]) begin i_chandle(`NULL); i_string("World"); end else begin i_chandle(`NULL); i_string("Hello"); end i_bit(~i[0]); i_logic(i[0]); // Basic types via typedefs i_byte_t( 8'd10 - 8'(2*i)); i_byte_unsigned_t( 8'd20 - 8'(2*i)); i_shortint_t( 16'd30 - 16'(2*i)); i_shortint_unsigned_t( 16'd40 - 16'(2*i)); i_int_t( 32'd50 - 32'(2*i)); i_int_unsigned_t( 32'd60 - 32'(2*i)); i_longint_t( 64'd70 - 64'(2*i)); i_longint_unsigned_t( 64'd80 - 64'(2*i)); `ifndef NO_TIME i_time_t( 64'd90 - 64'(2*i)); `endif `ifndef NO_INTEGER i_integer_t( 32'd100- 32'(2*i)); `endif i_real_t( -1.0*(2*i) - 0.50); `ifndef NO_SHORTREAL i_shortreal_t( -1.0*(2*i) - 0.25); `endif if (~i[0]) begin i_chandle_t(`NULL); i_string_t("World"); end else begin i_chandle_t(`NULL); i_string_t("Hello"); end i_bit_t(~i[0]); i_logic_t(i[0]); // 2-state packed arrays i_array_2_state_1(~i[0]); i_array_2_state_32(~32'd0 << i); i_array_2_state_33(~33'd0 << i); i_array_2_state_64(~64'd0 << i); i_array_2_state_65(~65'd0 << i); i_array_2_state_128(~128'd0 << i); // 2-state packed structures i_struct_2_state_1(~i[0]); i_struct_2_state_32(~32'd0 << i); i_struct_2_state_33(~33'd0 << i); i_struct_2_state_64(~64'd0 << i); i_struct_2_state_65(~65'd0 << i); i_struct_2_state_128(~128'd0 << i); // 2-state packed unions i_union_2_state_1(~i[0]); i_union_2_state_32(~32'd0 << i); i_union_2_state_33(~33'd0 << i); i_union_2_state_64(~64'd0 << i); i_union_2_state_65(~65'd0 << i); i_union_2_state_128(~128'd0 << i); // 4-state packed arrays i_array_4_state_1(~i[0]); i_array_4_state_32(~32'd0 << i); i_array_4_state_33(~33'd0 << i); i_array_4_state_64(~64'd0 << i); i_array_4_state_65(~65'd0 << i); i_array_4_state_128(~128'd0 << i); // 4-state packed structures i_struct_4_state_1(~i[0]); i_struct_4_state_32(~32'd0 << i); i_struct_4_state_33(~33'd0 << i); i_struct_4_state_64(~64'd0 << i); i_struct_4_state_65(~65'd0 << i); i_struct_4_state_128(~128'd0 << i); // 4-state packed unions i_union_4_state_1(~i[0]); i_union_4_state_32(~32'd0 << i); i_union_4_state_33(~33'd0 << i); i_union_4_state_64(~64'd0 << i); i_union_4_state_65(~65'd0 << i); i_union_4_state_128(~128'd0 << i); // Check the exports check_exports(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_tri_gate_notif1.pl0000775000177100017500000000142113702133370022426 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_tri_gate.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ['+define+T_NOTIF1',], make_flags => 'CPPFLAGS_ADD=-DT_NOTIF1', verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_attr_parenstar.pl0000775000177100017500000000105313702133367022410 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_dos.pl0000775000177100017500000000215413702133370021673 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2006-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("$Self->{obj_dir}/$Self->{name}.v"); $Self->{golden_filename} = "$Self->{obj_dir}/$Self->{name}.out"; # Rather then having to maintain a new .v and .out, simply add returns # to all lines of the existing t_preproc test. { my $wholefile = file_contents("$Self->{t_dir}/t_preproc.v"); $wholefile =~ s/\n/\r\n/og; write_wholefile("$Self->{obj_dir}/$Self->{name}.v", $wholefile); } { my $wholefile = file_contents("$Self->{t_dir}/t_preproc.out"); $wholefile =~ s!t/t_preproc.v!$Self->{obj_dir}/t_preproc_dos.v!og; # Fix `line's write_wholefile($Self->{golden_filename}, $wholefile); } do 't/t_preproc.pl'; 1; verilator-4.038/test_regress/t/t_display_string.pl0000775000177100017500000000110313702133370022400 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_var_bad.pl0000775000177100017500000000107413702133370021603 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_gater.pl0000775000177100017500000000143213702133367021313 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats", $Self->wno_unopthreads_for_few_cores()] ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { #Optimization is disabled #file_grep ($Self->{stats}, qr/Optimizations, Gaters inserted\s+(\d+)/i, 3); } ok(1); 1; verilator-4.038/test_regress/t/t_case_deep.v0000664000177100017500000004421713702133367021127 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [33:0] in = crc[33:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] code; // From test of Test.v wire [4:0] len; // From test of Test.v wire next; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .next (next), .code (code[31:0]), .len (len[4:0]), // Inputs .clk (clk), .in (in[33:0])); // Aggregate outputs into a single result vector wire [63:0] result = {26'h0, next, len, code}; // What checksum will we end up with `define EXPECTED_SUM 64'h5537fa30d49bf865 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs next, code, len, // Inputs clk, in ); input clk; input [33:0] in; output next; output [31:0] code; output [4:0] len; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [31:0] code; reg [4:0] len; reg next; // End of automatics /* #!/usr/bin/env perl use warnings; srand(5); my @used; pat: for (my $pat=0; 1; ) { last if $pat > 196; my $len = int($pat / (6 + $pat/50)) + 4; $len=20 if $len>20; my ($try, $val, $mask); try: for ($try=0; ; $try++) { next pat if $try>50; $val = 0; for (my $bit=23; $bit>(23-$len); $bit--) { my $b = int(rand()*2); $val |= (1<<$bit) if $b; } $mask = (1<<(23-$len+1))-1; for (my $testval = $val; $testval <= ($val + $mask); $testval ++) { next try if $used[$testval]; } last; } my $bits = ""; my $val2 = 0; for (my $bit=23; $bit>(23-$len); $bit--) { my $b = ($val & (1<<$bit)); $bits .= $b?'1':'0'; } for (my $testval = $val; $testval <= ($val + $mask); $testval++) { $used[$testval]= 1; #printf "U%08x\n", $testval; } if ($try<90) { printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n" ,$bits.("?"x(24-$len)), 31-$len, $len, $pat); $pat++; } } */ always @* begin next = 1'b0; code = 32'd0; len = 5'b11111; casez (in[31:8]) 24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000}; 24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001}; 24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002}; 24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003}; 24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004}; 24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005}; 24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006}; 24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007}; 24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008}; 24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009}; 24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010}; 24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011}; 24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012}; 24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013}; 24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014}; 24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015}; 24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016}; 24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017}; 24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018}; 24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020}; 24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021}; 24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022}; 24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023}; 24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024}; 24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025}; 24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026}; 24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027}; 24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028}; 24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029}; 24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030}; 24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031}; 24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032}; 24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033}; 24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034}; 24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035}; 24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036}; 24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037}; 24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038}; 24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039}; 24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040}; 24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041}; 24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042}; 24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043}; 24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044}; 24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045}; 24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046}; 24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047}; 24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048}; 24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049}; 24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050}; 24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051}; 24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052}; 24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053}; 24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054}; 24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055}; 24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056}; 24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057}; 24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058}; 24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059}; 24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060}; 24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061}; 24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062}; 24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063}; 24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064}; 24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065}; 24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066}; 24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067}; 24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068}; 24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069}; 24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070}; 24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071}; 24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072}; 24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073}; 24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074}; 24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075}; 24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076}; 24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077}; 24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078}; 24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079}; 24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080}; 24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081}; 24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082}; 24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083}; 24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084}; 24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085}; 24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086}; 24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087}; 24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088}; 24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089}; 24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090}; 24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091}; 24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092}; 24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093}; 24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094}; 24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095}; 24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096}; 24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097}; 24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098}; 24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099}; 24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100}; 24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101}; 24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102}; 24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103}; 24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104}; 24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105}; 24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106}; 24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107}; 24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108}; 24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109}; 24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110}; 24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111}; 24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112}; 24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113}; 24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114}; 24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115}; 24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116}; 24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117}; 24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118}; 24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119}; 24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120}; 24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121}; 24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122}; 24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123}; 24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124}; 24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125}; 24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126}; 24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127}; 24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128}; 24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129}; 24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130}; 24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131}; 24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132}; 24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133}; 24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134}; 24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135}; 24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136}; 24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137}; 24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138}; 24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139}; 24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140}; 24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141}; 24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142}; 24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143}; 24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144}; 24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145}; 24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146}; 24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147}; 24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148}; 24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149}; 24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150}; 24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151}; 24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152}; 24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153}; 24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154}; 24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155}; 24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156}; 24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157}; 24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158}; 24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159}; 24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160}; 24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161}; 24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162}; 24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163}; 24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164}; 24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165}; 24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166}; 24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167}; 24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168}; 24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169}; 24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170}; 24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171}; 24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172}; 24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173}; 24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174}; 24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175}; 24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176}; 24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177}; 24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178}; 24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179}; 24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180}; 24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181}; 24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182}; 24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183}; 24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184}; 24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185}; 24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186}; 24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187}; 24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188}; 24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189}; 24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190}; 24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191}; 24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192}; 24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193}; 24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194}; 24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195}; 24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196}; 24'b000000??????????????????: begin casez (in[33:32]) 2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197}; 2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198}; 2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199}; default: ; endcase end default: ; endcase end endmodule verilator-4.038/test_regress/t/t_concat_link_bad.v0000664000177100017500000000045713702133367022307 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); typedef logic [3:0] foo_t; foo_t foo_s; assign bar_s = {foo_s, foo_s}.f1; endmodule verilator-4.038/test_regress/t/t_dpi_var_vlt.pl0000775000177100017500000000275413702133370021673 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_dpi_var.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe --no-l2name $Self->{t_dir}/t_dpi_var.vlt $Self->{t_dir}/t_dpi_var.cpp"], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_multi_ref_bad.v0000664000177100017500000000157513702133370022643 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg dimn; reg [1:0] dim0; reg [1:0] dim1 [1:0]; reg [1:0] dim2 [1:0][1:0]; reg dim0nv[1:0]; initial begin dimn[1:0] = 0; // Bad: Not ranged dim0[1][1] = 0; // Bad: Not arrayed dim1[1][1][1] = 0; // Bad: Not arrayed to right depth dim2[1][1][1] = 0; // OK dim2[0 +: 1][1] = 0; // Bad: Range on non-bits dim2[1 : 0][1] = 0; // Bad: Range on non-bits dim2[1][1:0] = 0; // Bad: Bitsel too soon dim0nv[1:0] = 0; // Bad: Not vectored dim0nv[1][1] = 0; // Bad: Not arrayed to right depth end endmodule verilator-4.038/test_regress/t/t_func_const3_bad.v0000664000177100017500000000113013702133370022226 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module c9 #(parameter A = 1, parameter B = 1); localparam BITS = A*B; localparam SOMEP = {BITS{1'b0}}; endmodule module b9 #(parameter A = 1); c9 #(.A (A), .B (9)) c9; endmodule module t; b9 b9; b9 #(.A (100)) b900; b9 #(.A (1000)) b9k; initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_sys_file_basic_mcd.pl0000775000177100017500000000205013702133370023150 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); unlink("$Self->{obj_dir}/t_sys_file_basic_mcd.log"); compile(); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test2_0.dat", "$Self->{t_dir}/t_sys_file_basic_mcd_test2_0.dat"); files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test2_1.dat", "$Self->{t_dir}/t_sys_file_basic_mcd_test2_1.dat"); files_identical("$Self->{obj_dir}/t_sys_file_basic_mcd_test2_2.dat", "$Self->{t_dir}/t_sys_file_basic_mcd_test2_2.dat"); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_inc4.vh0000664000177100017500000000036613702133370021745 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define T_PREPROC_INC4 verilator-4.038/test_regress/t/t_lint_unused_iface_bad.v0000664000177100017500000000076413702133370023476 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic sig_udrv; logic sig_uusd; endinterface: dummy_if module sub ( dummy_if dummy ); assign dummy.sig_uusd = 1'b0 | dummy.sig_udrv; endmodule module t (/*AUTOARG*/); dummy_if dummy (); sub sub (.dummy(dummy) ); endmodule verilator-4.038/test_regress/t/t_dpi_display.v0000664000177100017500000000224113702133370021501 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); `ifndef VERILATOR `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." `endif import "DPI-C" context dpii_display_call = function void \$dpii_display (input string formatted /*verilator sformat*/ ); integer a; initial begin // Check variable width constant string conversions $dpii_display(""); $dpii_display("c"); $dpii_display("co"); $dpii_display("cons"); $dpii_display("constant"); $dpii_display("constant_value"); a = $c("10"); // Don't optimize away "a" $display ("one10=%x",a); // Check single arg $dpii_display("one10=%x",a); $display ("Mod=%m 16=%d 10=%x",a,a); // Check multiarg $dpii_display("Mod=%m 16=%d 10=%x",a,a); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_dpi_logic_bad.out0000664000177100017500000000044513702133370022305 0ustar wsnyderwsnyder%Error: t/t_dpi_logic_bad.v:12:54: DPI function may not return type BASICDTYPE 'logic' (IEEE 1800-2017 35.5.5) 12 | import "DPI-C" dpii_fa_bit = function logic [2:0] oth_f_int1(input time i); | ^~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_dist_whitespace.pl0000775000177100017500000000651613702133370022541 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); my $root = ".."; my $Debug; ### Must trim output before and after our file list my %files = %{get_manifest_files($root)}; foreach my $file (sort keys %files) { my $filename = "$root/$file"; my $contents = file_contents($filename); if ($file =~ /\.out$/) { # Ignore golden files next; } elsif ($contents =~ /[\001\002\003\004\005\006]/) { # Ignore binary files next; } if ($contents !~ /\n$/s && $contents ne "") { $warns{$file} = "Missing trailing newline in $file"; } if ($contents =~ /[ \t]\n/ || $contents =~ m/\n\n+$/) { # Regexp repeated below my $eol_ws_exempt = ($file =~ /(\.txt|\.html)$/ || $file =~ m!^README$! || $file =~ m!/gtkwave/!); next if $eol_ws_exempt; if ($ENV{HARNESS_UPDATE_GOLDEN}) { my $changes = undef; $changes = 1 if ($contents =~ s/[ \t]+\n/\n/g); $changes = 1 if (!$eol_ws_exempt && $contents =~ s/\n\n+$/\n/g); next if (!$changes); $warns{$file} = "Updated whitespace at $file"; write_wholefile($filename, $contents); next; } my @lines = split(/\n/, $contents); my $line_no = 0; foreach my $line (@lines) { $line_no++; # Trim trailing carriage-return (ascii 0xd) and form feed (0xc), # as we expect a few of those $line =~ s/[\x{d}\x{c}]//g; if ($line =~ /\s$/) { $warns{$file} = "Trailing whitespace at $file:$line_no"; $warns{$file} .= " (last character is ASCII " . ord(substr($line, -1, 1)) . ")"; } } if ($contents =~ m/\n\n+$/ && !$eol_ws_exempt) { # Regexp repeated above $warns{$file} = "Trailing newlines at EOF in $file"; } } } if (keys %warns) { # First warning lists everything as that's shown in the driver summary if ($ENV{HARNESS_UPDATE_GOLDEN}) { error("Updated files with whitespace errors: ",join(' ',sort keys %warns)); error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden"); } else { error("Files have whitespace errors: ",join(' ',sort keys %warns)); error("To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden"); } foreach my $file (sort keys %warns) { error($warns{$file}); } } ok(1); 1; sub get_manifest_files { my $root = shift; `cd $root && $ENV{MAKE} dist-file-list`; my $manifest_files = `cd $root && $ENV{MAKE} dist-file-list`; $manifest_files =~ s!.*begin-dist-file-list:!!sg; $manifest_files =~ s!end-dist-file-list:.*$!!sg; print "MF $manifest_files\n" if $Self->{verbose}; my %files; foreach my $file (split /\s+/,$manifest_files) { next if $file eq ''; $files{$file} |= 1; } return \%files; } verilator-4.038/test_regress/t/t_param_public.v0000664000177100017500000000146513702133370021645 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug505 module t (/*AUTOARG*/ // Inputs clk ); input clk; a #(1) a1 (); b #(2) b2 (); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module a; parameter ONE /*verilator public*/ = 22; initial if (ONE != 1) $stop; `ifdef VERILATOR initial if ($c32("ONE") != 1) $stop; `endif endmodule module b #( parameter TWO /*verilator public*/ = 22 ); initial if (TWO != 2) $stop; `ifdef VERILATOR initial if ($c32("TWO") != 2) $stop; `endif endmodule //bug804 package p; localparam INPACK /*verilator public*/ = 6; endpackage verilator-4.038/test_regress/t/t_math_divw.pl0000775000177100017500000000105313702133370021333 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_mul.pl0000775000177100017500000000105313702133370021157 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_order_clkinst_bad.out0000664000177100017500000000262113702133370023214 0ustar wsnyderwsnyder%Warning-IMPERFECTSCH: t/t_order_clkinst.v:18:16: Imperfect scheduling of variable: 't.c1_start' 18 | reg c1_start; initial c1_start = 0; | ^~~~~~~~ ... Use "/* verilator lint_off IMPERFECTSCH */" and lint_on around source to disable this message. %Warning-IMPERFECTSCH: t/t_order_clkinst.v:19:16: Imperfect scheduling of variable: 't.c1_count' 19 | wire [31:0] c1_count; | ^~~~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:23:16: Imperfect scheduling of variable: 't.s2_count' 23 | wire [31:0] s2_count; | ^~~~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:27:16: Imperfect scheduling of variable: 't.c3_count' 27 | wire [31:0] c3_count; | ^~~~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:71:28: Imperfect scheduling of variable: 't.c1.runner' 71 | reg [31:0] runnerm1, runner; initial runner = 0; | ^~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:100:28: Imperfect scheduling of variable: 't.s2.runner' 100 | reg [31:0] runnerm1, runner; initial runner = 0; | ^~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:71:28: Imperfect scheduling of variable: 't.c3.runner' 71 | reg [31:0] runnerm1, runner; initial runner = 0; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_case_string.v0000664000177100017500000000177713702133367021524 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; string mystr; reg [2:0] cyc; initial cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) if (mystr != "case-1") $stop; if (cyc == 4) if (mystr != "case-4") $stop; if (cyc == 6) if (mystr != "bad-default") $stop; if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end always @ (cyc) begin // verilator lint_off CASEINCOMPLETE case (cyc) 3'b000: mystr = "case-0"; 3'b001: mystr = "case-1"; 3'b010: mystr = "case-2"; 3'b100: mystr = "case-4"; 3'b101: mystr = "case-5"; default: mystr = "bad-default"; endcase //$display("with_case: %d = %s", cyc, mystr); end endmodule verilator-4.038/test_regress/t/t_trace_decoration.pl0000775000177100017500000000126113702133370022657 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--cc --trace --no-decoration'], ); execute( check_finished => 1, ); file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr!// Body!x); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_stop_bad_c.cpp0000664000177100017500000000146413702133370022476 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include "svdpi.h" #include "vpi_user.h" //====================================================================== extern "C" { extern void dpii_test(); } //====================================================================== void dpii_test() { vpi_control(vpiStop); } verilator-4.038/test_regress/t/t_x_assign_unique_0.pl0000775000177100017500000000131713702133370022774 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_x_assign.v"); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--x-assign unique --exe $Self->{t_dir}/t_x_assign.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_array_bad.out0000664000177100017500000000054313702133370022526 0ustar wsnyderwsnyder%Error: t/t_inst_array_bad.v:19:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. : ... In instance t 19 | sub sub [7:0] (allbits, onebitbad, bitout); | ^~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_dotted_inl0_vlt.pl0000775000177100017500000000222313702133370023456 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_func_dotted.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( v_flags2 => ["$Self->{t_dir}/t_func_dotted_inl0.vlt"], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_multitop_sig_bad.pl0000775000177100017500000000114613702133370022701 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_multitop_sig.v"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_package_twodeep.pl0000775000177100017500000000105313702133370022473 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_waiveroutput.pl0000775000177100017500000000161513702133370022133 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2012 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.vlt"; my $waiver_filename = "$Self->{obj_dir}/$Self->{name}_waiver.vlt"; compile( v_flags2 => ['--waiver-output', $out_filename], fails => 1, ); files_identical("$out_filename", $Self->{golden_filename}); run(cmd=>["sed 's/\\/\\/ lint_off/lint_off/g' $out_filename > $waiver_filename"]); compile( v_flags2 => [$waiver_filename], ); ok(1); 1; verilator-4.038/test_regress/t/t_wire_beh1800_bad.v0000664000177100017500000000146013702133370022105 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, oa, ro, roa, wo, woa, vo, voa ); wire w; reg r; output o; output [1:0] oa; output reg ro; output reg [1:0] roa; output wire wo; output wire [1:0] woa; // 1800 only output var vo; output var [1:0] voa; initial begin w = '0; // Error o = '0; // Error oa = '0; // Error wo = '0; // Error woa = '0; // Error r = '0; // Not an error ro = '0; // Not an error roa = '0; // Not an error vo = '0; // Not an error voa = '0; // Not an error end endmodule verilator-4.038/test_regress/t/t_case_deep.pl0000775000177100017500000000120413702133367021265 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_div0.v0000664000177100017500000000156313702326127021065 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs y, d2, m2, d3, m3 ); output [3:0] y; output [31:0] d2; output [31:0] m2; output [63:0] d3; output [63:0] m3; // bug775 // verilator lint_off WIDTH assign y = ((0/0) ? 1 : 2) % 0; // bug2460 reg [31:0] b; assign d2 = $signed(32'h80000000) / $signed(b); assign m2 = $signed(32'h80000000) % $signed(b); reg [63:0] b3; assign d3 = $signed(64'h80000000_00000000) / $signed(b3); assign m3 = $signed(64'h80000000_00000000) % $signed(b3); initial begin b = 32'hffffffff; b3 = 64'hffffffff_ffffffff; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_display_realtime.pl0000775000177100017500000000105413702133370022701 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clocker.v0000664000177100017500000000272013702133367020632 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Simple test of CLkDATA // // Trigger the CLKDATA detection // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; module t (/*AUTOARG*/ // Inputs clk, res, res8, res16 ); input clk; output reg res; output reg [7:0] res8; output reg [15:0] res16; wire [7:0] clkSet; wire clk_1; wire [2:0] clk_3; wire [3:0] clk_4; wire clk_final; reg [7:0] count; assign clkSet = {8{clk}}; assign clk_4 = clkSet[7:4]; assign clk_1 = clk_4[0];; // arraysel assign clk_3 = {3{clk_1}}; assign clk_final = clk_3[0]; // the following two assignment triggers the CLKDATA warning // because on LHS there are a mix of signals both CLOCK and // DATA /* verilator lint_off CLKDATA */ assign res8 = {clk_3, 1'b0, clk_4}; assign res16 = {count, clk_3, clk_1, clk_4}; /* verilator lint_on CLKDATA */ initial count = 0; always @(posedge clk_final or negedge clk_final) begin count = count + 1; // the following assignment should trigger the CLKDATA warning // because CLOCK signal is used as DATA in sequential block /* verilator lint_off CLKDATA */ res <= clk_final; /* verilator lint_on CLKDATA */ if ( count == 8'hf) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_param_ddeep_width.pl0000775000177100017500000000076613702133370023023 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_pp_pragmas.v0000664000177100017500000000250113702133370021330 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/10ps `verilog `suppress_faults `nosuppress_faults `enable_portfaults `disable_portfaults `delay_mode_distributed `delay_mode_path `delay_mode_unit `delay_mode_zero `default_decay_time 1 `default_decay_time 1.0 `default_decay_time infinite // unsupported (recommended not to): `default_trireg_strength 10 `default_nettype wire // unsupported: `default_nettype tri // unsupported: `default_nettype tri0 // unsupported: `default_nettype wand // unsupported: `default_nettype triand // unsupported: `default_nettype wor // unsupported: `default_nettype trior // unsupported: `default_nettype trireg `default_nettype none `autoexpand_vectornets `accelerate `noaccelerate `expand_vectornets `noexpand_vectornets `remove_gatenames `noremove_gatenames `remove_netnames `noremove_netnames `resetall // unsupported: `unconnected_drive pull1 // unsupported: `unconnected_drive pull0 `nounconnected_drive `line 100 "hallo.v" 0 // unsupported: `uselib file=../moto_lib.v // unsupported: `uselib dir=../lib.dir libext=.v module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_sys_readmem_bad_addr.v0000664000177100017500000000061313702133370023311 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; initial begin $readmemh("t/t_sys_readmem_bad_addr.mem", hex); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_timing_reentry.pl0000775000177100017500000000152313702133370022412 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( #verilator_flags2 => ['--exe --build --main --timing'], # Unsupported verilator_flags2 => ['--exe --build --main --bbox-unsup -Wno-STMTDLY -Wno-INITIALDLY'], verilator_make_cmake => 0, verilator_make_gmake => 0, make_main => 0, make_top => 1, ); # Will fail, unsupported #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_order_loop_bad.v0000664000177100017500000000162013702133370022152 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Non-cutable edge in loop // // This code (stripped down from a much larger application) has a loop between // the use of ready in the first two always blocks. However it should // trivially trigger the $write on the first clk posedge. // // This is a regression test against issue 513. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg ready; initial begin ready = 1'b0; end always @(posedge ready) begin if ((ready === 1'b1)) begin $write("*-* All Finished *-*\n"); $finish; end end always @(posedge ready) begin if ((ready === 1'b0)) begin ready = 1'b1 ; end end always @(posedge clk) begin ready = 1'b1; end endmodule verilator-4.038/test_regress/t/t_dpi_result_type.v0000664000177100017500000004216413702133370022423 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_REAL_EXPORT `endif `ifdef NC `define NO_STRUCT_OR_UNION `define NO_SHORTREAL `endif `ifdef MS `define NO_STRUCT_OR_UNION `define NO_ARRAY `endif `ifdef VERILATOR `define NO_SHORTREAL `define NULL 64'd0 `else `define NULL null `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef VERILATOR wire _unused = &{1'b0, clk}; `endif // Legal result types for DPI functions //====================================================================== // Type definitions //====================================================================== // Basic types as per IEEE 1800-2017 35.5.5 typedef byte byte_t; typedef byte unsigned byte_unsigned_t; typedef shortint shortint_t; typedef shortint unsigned shortint_unsigned_t; typedef int int_t; typedef int unsigned int_unsigned_t; typedef longint longint_t; typedef longint unsigned longint_unsigned_t; typedef real real_t; `ifndef NO_SHORTREAL typedef shortreal shortreal_t; `endif typedef chandle chandle_t; typedef string string_t; typedef bit bit_t; typedef logic logic_t; // 2-state packed structures of width <= 32 typedef struct packed { bit x; } struct_2_state_1; typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; // 2-state packed unions of width <= 32 typedef union packed { bit x; bit y; } union_2_state_1; typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; //====================================================================== // Imports //====================================================================== // Basic types as per IEEE 1800-2017 35.5.5 import "DPI-C" function void i_void (); import "DPI-C" function byte i_byte (); import "DPI-C" function byte unsigned i_byte_unsigned (); import "DPI-C" function shortint i_shortint (); import "DPI-C" function shortint unsigned i_shortint_unsigned (); import "DPI-C" function int i_int (); import "DPI-C" function int unsigned i_int_unsigned (); import "DPI-C" function longint i_longint (); import "DPI-C" function longint unsigned i_longint_unsigned (); import "DPI-C" function real i_real (); `ifndef NO_SHORTREAL import "DPI-C" function shortreal i_shortreal (); `endif import "DPI-C" function chandle i_chandle (); import "DPI-C" function string i_string (); import "DPI-C" function bit i_bit (); import "DPI-C" function logic i_logic (); // Basic types via typedef import "DPI-C" function byte_t i_byte_t (); import "DPI-C" function byte_unsigned_t i_byte_unsigned_t (); import "DPI-C" function shortint_t i_shortint_t (); import "DPI-C" function shortint_unsigned_t i_shortint_unsigned_t (); import "DPI-C" function int_t i_int_t (); import "DPI-C" function int_unsigned_t i_int_unsigned_t (); import "DPI-C" function longint_t i_longint_t (); import "DPI-C" function longint_unsigned_t i_longint_unsigned_t (); import "DPI-C" function real_t i_real_t (); `ifndef NO_SHORTREAL import "DPI-C" function shortreal_t i_shortreal_t (); `endif import "DPI-C" function chandle_t i_chandle_t (); import "DPI-C" function string_t i_string_t (); import "DPI-C" function bit_t i_bit_t (); import "DPI-C" function logic_t i_logic_t (); `ifndef NO_ARRAY // 2-state packed arrays of width <= 32 import "DPI-C" function bit [ 0:0] i_array_2_state_1 (); import "DPI-C" function bit [31:0] i_array_2_state_32 (); `endif `ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 import "DPI-C" function struct_2_state_1 i_struct_2_state_1 (); import "DPI-C" function struct_2_state_32 i_struct_2_state_32(); // 2-state packed unions of width <= 32 import "DPI-C" function union_2_state_1 i_union_2_state_1 (); import "DPI-C" function union_2_state_32 i_union_2_state_32(); `endif //====================================================================== // Exports //====================================================================== // Basic types as per IEEE 1800-2017 35.5.5 export "DPI-C" function e_void; export "DPI-C" function e_byte; export "DPI-C" function e_byte_unsigned; export "DPI-C" function e_shortint; export "DPI-C" function e_shortint_unsigned; export "DPI-C" function e_int; export "DPI-C" function e_int_unsigned; export "DPI-C" function e_longint; export "DPI-C" function e_longint_unsigned; `ifndef NO_REAL_EXPORT export "DPI-C" function e_real; `endif `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal; `endif export "DPI-C" function e_chandle; export "DPI-C" function e_string; export "DPI-C" function e_bit; export "DPI-C" function e_logic; // Basic types via typedef export "DPI-C" function e_byte_t; export "DPI-C" function e_byte_unsigned_t; export "DPI-C" function e_shortint_t; export "DPI-C" function e_shortint_unsigned_t; export "DPI-C" function e_int_t; export "DPI-C" function e_int_unsigned_t; export "DPI-C" function e_longint_t; export "DPI-C" function e_longint_unsigned_t; `ifndef NO_REAL_EXPORT export "DPI-C" function e_real_t; `endif `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_t; `endif export "DPI-C" function e_chandle_t; export "DPI-C" function e_string_t; export "DPI-C" function e_bit_t; export "DPI-C" function e_logic_t; `ifndef NO_ARRAY // 2-state packed arrays of width <= 32 export "DPI-C" function e_array_2_state_1; export "DPI-C" function e_array_2_state_32; `endif `ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 export "DPI-C" function e_struct_2_state_1; export "DPI-C" function e_struct_2_state_32; // 2-state packed unions of width <= 32 export "DPI-C" function e_union_2_state_1; export "DPI-C" function e_union_2_state_32; `endif //====================================================================== // Definitions of exported functions //====================================================================== // Static variables (Note: Verilator strangely assumes everything inside // a function is automatic, which is exactly the opposite of the standard // see IEEE 1800-2017 13.3.1 and 13.4.2 // Basic types as per IEEE 1800-2017 35.5.5 int n_void = 0; function void e_void(); $display("e_void %1d", n_void); n_void++; endfunction byte n_byte = 0; function byte e_byte(); e_byte = 8'd10 + n_byte; n_byte++; endfunction byte n_byte_unsigned = 0; function byte unsigned e_byte_unsigned(); e_byte_unsigned = 8'd20 + n_byte_unsigned; n_byte_unsigned++; endfunction shortint n_shortint = 0; function shortint e_shortint(); e_shortint = 16'd30 + n_shortint; n_shortint++; endfunction shortint n_shortint_unsigned = 0; function shortint unsigned e_shortint_unsigned(); e_shortint_unsigned = 16'd40 + n_shortint_unsigned; n_shortint_unsigned++; endfunction int n_int = 0; function int e_int(); e_int = 32'd50 + n_int; n_int++; endfunction int n_int_unsigned = 0; function int unsigned e_int_unsigned(); e_int_unsigned = 32'd60 + n_int_unsigned; n_int_unsigned++; endfunction longint n_longint = 0; function longint e_longint(); e_longint = 64'd70 + n_longint; n_longint++; endfunction longint n_longint_unsigned = 0; function longint unsigned e_longint_unsigned(); e_longint_unsigned = 64'd80 + n_longint_unsigned; n_longint_unsigned++; endfunction `ifndef NO_REAL_EXPORT int n_real = 0; function real e_real(); e_real = real'(2*n_real + 1) / 2.0; n_real++; endfunction `endif `ifndef NO_SHORTREAL int n_shortreal = 0; function shortreal e_shortreal(); e_shortreal = shortreal'(4*n_shortreal + 1)/ 4.0; n_shortreal++; endfunction `endif int n_chandle = 0; function chandle e_chandle(); $display("e_chandle %1d", n_chandle); e_chandle = `NULL; n_chandle++; endfunction int n_string = 0; function string e_string(); $display("e_string %1d", n_string); e_string = n_string[0] ? "World" : "Hello"; n_string++; endfunction int n_bit = 0; function bit e_bit(); $display("e_bit %1d", n_bit); e_bit = n_bit[0]; n_bit++; endfunction int n_logic = 0; function logic e_logic(); $display("e_logic %1d", n_logic); e_logic = ~n_logic[0]; n_logic++; endfunction // Basic types via typedefs byte_t n_byte_t = 0; function byte_t e_byte_t(); e_byte_t = 8'd10 + n_byte_t; n_byte_t += 2; endfunction byte n_byte_unsigned_t = 0; function byte_unsigned_t e_byte_unsigned_t(); e_byte_unsigned_t = 8'd20 + n_byte_unsigned_t; n_byte_unsigned_t += 2; endfunction shortint_t n_shortint_t = 0; function shortint_t e_shortint_t(); e_shortint_t = 16'd30 + n_shortint_t; n_shortint_t += 2; endfunction shortint n_shortint_unsigned_t = 0; function shortint_unsigned_t e_shortint_unsigned_t(); e_shortint_unsigned_t = 16'd40 + n_shortint_unsigned_t; n_shortint_unsigned_t += 2; endfunction int_t n_int_t = 0; function int_t e_int_t(); e_int_t = 32'd50 + n_int_t; n_int_t += 2; endfunction int n_int_unsigned_t = 0; function int_unsigned_t e_int_unsigned_t(); e_int_unsigned_t = 32'd60 + n_int_unsigned_t; n_int_unsigned_t += 2; endfunction longint_t n_longint_t = 0; function longint_t e_longint_t(); e_longint_t = 64'd70 + n_longint_t; n_longint_t += 2; endfunction longint n_longint_unsigned_t = 0; function longint_unsigned_t e_longint_unsigned_t(); e_longint_unsigned_t = 64'd80 + n_longint_unsigned_t; n_longint_unsigned_t += 2; endfunction `ifndef NO_REAL_EXPORT int n_real_t = 0; function real_t e_real_t(); e_real_t = real'(2*n_real_t + 1) / 2.0; n_real_t += 2; endfunction `endif `ifndef NO_SHORTREAL int n_shortreal_t = 0; function shortreal_t e_shortreal_t(); e_shortreal_t = shortreal'(4*n_shortreal_t + 1)/ 4.0; n_shortreal_t += 2; endfunction `endif int n_chandle_t = 0; function chandle_t e_chandle_t(); $display("e_chandle_t %1d", n_chandle_t); e_chandle_t = `NULL; n_chandle_t++; endfunction int n_string_t = 0; function string_t e_string_t(); $display("e_string_t %1d", n_string_t); e_string_t = n_string_t[0] ? "World" : "Hello"; n_string_t++; endfunction int n_bit_t = 0; function bit_t e_bit_t(); $display("e_bit_t %1d", n_bit_t); e_bit_t = n_bit_t[0]; n_bit_t++; endfunction int n_logic_t = 0; function logic_t e_logic_t(); $display("e_logic_t %1d", n_logic_t); e_logic_t = ~n_logic_t[0]; n_logic_t++; endfunction `ifndef NO_ARRAY // 2-state packed arrays of width <= 32 int n_array_2_state_1 = 0; function bit [ 0:0] e_array_2_state_1(); $display("e_array_2_state_1 %1d", n_array_2_state_1); e_array_2_state_1 = n_array_2_state_1[0]; n_array_2_state_1++; endfunction int n_array_2_state_32 = 0; function bit [31:0] e_array_2_state_32(); $display("e_array_2_state_32 %1d", n_array_2_state_32); e_array_2_state_32 = ~32'd0 >> n_array_2_state_32; n_array_2_state_32++; endfunction `endif `ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 int n_struct_2_state_1 = 0; function struct_2_state_1 e_struct_2_state_1(); $display("e_struct_2_state_1 %1d", n_struct_2_state_1); e_struct_2_state_1 = n_struct_2_state_1[0]; n_struct_2_state_1++; endfunction int n_struct_2_state_32 = 0; function struct_2_state_32 e_struct_2_state_32(); $display("e_struct_2_state_32 %1d", n_struct_2_state_32); e_struct_2_state_32 = ~32'd0 >> n_struct_2_state_32; n_struct_2_state_32++; endfunction // 2-state packed unions of width <= 32 int n_union_2_state_1 = 0; function union_2_state_1 e_union_2_state_1(); $display("e_union_2_state_1 %1d", n_union_2_state_1); e_union_2_state_1 = n_union_2_state_1[0]; n_union_2_state_1++; endfunction int n_union_2_state_32 = 0; function union_2_state_32 e_union_2_state_32(); $display("e_union_2_state_32 %1d", n_union_2_state_32); e_union_2_state_32 = ~32'd0 >> n_union_2_state_32; n_union_2_state_32++; endfunction `endif //====================================================================== // Invoke all functions 3 times (they have side effects) //====================================================================== import "DPI-C" context function void check_exports(); initial begin for (int i = 0 ; i < 3; i++) begin // Check the imports // Basic types as per IEEE 1800-2017 35.5.5 i_void(); if (i_byte() !== 8'd10 - 8'(i)) $stop; if (i_byte_unsigned() !== 8'd20 - 8'(i)) $stop; if (i_shortint() !== 16'd30 - 16'(i)) $stop; if (i_shortint_unsigned() !== 16'd40 - 16'(i)) $stop; if (i_int() !== 32'd50 - 32'(i)) $stop; if (i_int_unsigned() !== 32'd60 - 32'(i)) $stop; if (i_longint() !== 64'd70 - 64'(i)) $stop; if (i_longint_unsigned() !== 64'd80 - 64'(i)) $stop; if (i_real() != -1.0*i - 0.5 ) $stop; `ifndef NO_SHORTREAL if (i_shortreal() != -1.0*i - 0.25) $stop; `endif if (~i[0]) begin if (i_chandle() !== `NULL) $stop; if (i_string() != "World") $stop; end else begin if (i_chandle() === `NULL) $stop; if (i_string() != "Hello") $stop; end if (i_bit() !== ~i[0]) $stop; if (i_logic() !== i[0]) $stop; // Basic types via typedefs if (i_byte_t() !== 8'd10 - 8'(2*i)) $stop; if (i_byte_unsigned_t() !== 8'd20 - 8'(2*i)) $stop; if (i_shortint_t() !== 16'd30 - 16'(2*i)) $stop; if (i_shortint_unsigned_t() !== 16'd40 - 16'(2*i)) $stop; if (i_int_t() !== 32'd50 - 32'(2*i)) $stop; if (i_int_unsigned_t() !== 32'd60 - 32'(2*i)) $stop; if (i_longint_t() !== 64'd70 - 64'(2*i)) $stop; if (i_longint_unsigned_t() !== 64'd80 - 64'(2*i)) $stop; if (i_real_t() != -1.0*(2*i) - 0.5 ) $stop; `ifndef NO_SHORTREAL if (i_shortreal_t() != -1.0*(2*i) - 0.25) $stop; `endif if (~i[0]) begin if (i_chandle_t() !== `NULL) $stop; if (i_string_t() != "World") $stop; end else begin if (i_chandle_t() === `NULL) $stop; if (i_string_t() != "Hello") $stop; end if (i_bit_t() !== ~i[0]) $stop; if (i_logic_t() !== i[0]) $stop; `ifndef NO_ARRAY // 2-state packed arrays of width <= 32 if (i_array_2_state_1() !== ~i[0] ) $stop; if (i_array_2_state_32() !== ~32'd0 << i) $stop; `endif `ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 if (i_struct_2_state_1() !== ~i[0] ) $stop; if (i_struct_2_state_32() !== ~32'd0 << i) $stop; // 2-state packed unions of width <= 32 if (i_union_2_state_1() !== ~i[0] ) $stop; if (i_union_2_state_32() !== ~32'd0 << i) $stop; `endif // Check the exports check_exports(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_mlog2.v0000664000177100017500000000243313702133370021236 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer cyc; initial cyc=1; integer sum; integer cpre; always @ (posedge clk) begin if (cyc!=0) begin cpre = cyc; cyc <= cyc + 1; if (cyc==1) begin if (mlog2(32'd0) != 32'd0) $stop; if (mlog2(32'd1) != 32'd0) $stop; if (mlog2(32'd3) != 32'd2) $stop; sum <= 32'd0; end else if (cyc<90) begin // (cyc) so if we trash the variable things will get upset. sum <= mlog2(cyc) + sum * 32'd42; if (cpre != cyc) $stop; end else if (cyc==90) begin if (sum !== 32'h0f12bb51) $stop; $write("*-* All Finished *-*\n"); $finish; end end end function integer mlog2; input [31:0] value; integer i; begin if(value < 32'd1) begin mlog2 = 0; end else begin value = value - 32'd1; mlog2 = 0; for(i=0;i<32;i=i+1) begin if(value > 32'd0) begin mlog2 = mlog2 + 1; end value = value >> 1; end end end endfunction endmodule verilator-4.038/test_regress/t/t_assert_dup_bad.v0000664000177100017500000000071713702133367022173 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; covlabel: cover property (@(posedge clk) cyc==5); covlabel: // Error: Duplicate block_identifier cover property (@(posedge clk) cyc==5); endmodule verilator-4.038/test_regress/t/t_preproc_inc_bad.v0000664000177100017500000000043513702133370022314 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //See bug289 `include "t_preproc_inc_inc_bad.vh" module t; endmodule verilator-4.038/test_regress/t/t_class_extends.pl0000775000177100017500000000117613702133367022224 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_inout_type.out0000664000177100017500000001206113702133370023427 0ustar wsnyderwsnyderi_chandle 0 i_string 0 i_bit 0 i_logic 0 i_chandle_t 0 i_string_t 0 i_bit_t 0 i_logic_t 0 i_array_2_state_1 0 i_array_2_state_32 0 i_array_2_state_33 0 i_array_2_state_64 0 i_array_2_state_65 0 i_array_2_state_128 0 i_struct_2_state_1 0 i_struct_2_state_32 0 i_struct_2_state_33 0 i_struct_2_state_64 0 i_struct_2_state_65 0 i_struct_2_state_128 0 i_union_2_state_1 0 i_union_2_state_32 0 i_union_2_state_33 0 i_union_2_state_64 0 i_union_2_state_65 0 i_union_2_state_128 0 i_array_4_state_1 0 i_array_4_state_32 0 i_array_4_state_33 0 i_array_4_state_64 0 i_array_4_state_65 0 i_array_4_state_128 0 i_struct_4_state_1 0 i_struct_4_state_32 0 i_struct_4_state_33 0 i_struct_4_state_64 0 i_struct_4_state_65 0 i_struct_4_state_128 0 i_union_4_state_1 0 i_union_4_state_32 0 i_union_4_state_33 0 i_union_4_state_64 0 i_union_4_state_65 0 i_union_4_state_128 0 e_chandle 0 e_string 0 e_bit 0 e_logic 0 e_chandle_t 0 e_string_t 0 e_bit_t 0 e_logic_t 0 e_array_2_state_1 0 e_array_2_state_32 0 e_array_2_state_33 0 e_array_2_state_64 0 e_array_2_state_65 0 e_array_2_state_128 0 e_struct_2_state_1 0 e_struct_2_state_32 0 e_struct_2_state_33 0 e_struct_2_state_64 0 e_struct_2_state_65 0 e_struct_2_state_128 0 e_union_2_state_1 0 e_union_2_state_32 0 e_union_2_state_33 0 e_union_2_state_64 0 e_union_2_state_65 0 e_union_2_state_128 0 e_array_4_state_1 0 e_array_4_state_32 0 e_array_4_state_33 0 e_array_4_state_64 0 e_array_4_state_65 0 e_array_4_state_128 0 e_struct_4_state_1 0 e_struct_4_state_32 0 e_struct_4_state_33 0 e_struct_4_state_64 0 e_struct_4_state_65 0 e_struct_4_state_128 0 e_union_4_state_1 0 e_union_4_state_32 0 e_union_4_state_33 0 e_union_4_state_64 0 e_union_4_state_65 0 e_union_4_state_128 0 i_chandle 1 i_string 1 i_bit 1 i_logic 1 i_chandle_t 1 i_string_t 1 i_bit_t 1 i_logic_t 1 i_array_2_state_1 1 i_array_2_state_32 1 i_array_2_state_33 1 i_array_2_state_64 1 i_array_2_state_65 1 i_array_2_state_128 1 i_struct_2_state_1 1 i_struct_2_state_32 1 i_struct_2_state_33 1 i_struct_2_state_64 1 i_struct_2_state_65 1 i_struct_2_state_128 1 i_union_2_state_1 1 i_union_2_state_32 1 i_union_2_state_33 1 i_union_2_state_64 1 i_union_2_state_65 1 i_union_2_state_128 1 i_array_4_state_1 1 i_array_4_state_32 1 i_array_4_state_33 1 i_array_4_state_64 1 i_array_4_state_65 1 i_array_4_state_128 1 i_struct_4_state_1 1 i_struct_4_state_32 1 i_struct_4_state_33 1 i_struct_4_state_64 1 i_struct_4_state_65 1 i_struct_4_state_128 1 i_union_4_state_1 1 i_union_4_state_32 1 i_union_4_state_33 1 i_union_4_state_64 1 i_union_4_state_65 1 i_union_4_state_128 1 e_chandle 1 e_string 1 e_bit 1 e_logic 1 e_chandle_t 1 e_string_t 1 e_bit_t 1 e_logic_t 1 e_array_2_state_1 1 e_array_2_state_32 1 e_array_2_state_33 1 e_array_2_state_64 1 e_array_2_state_65 1 e_array_2_state_128 1 e_struct_2_state_1 1 e_struct_2_state_32 1 e_struct_2_state_33 1 e_struct_2_state_64 1 e_struct_2_state_65 1 e_struct_2_state_128 1 e_union_2_state_1 1 e_union_2_state_32 1 e_union_2_state_33 1 e_union_2_state_64 1 e_union_2_state_65 1 e_union_2_state_128 1 e_array_4_state_1 1 e_array_4_state_32 1 e_array_4_state_33 1 e_array_4_state_64 1 e_array_4_state_65 1 e_array_4_state_128 1 e_struct_4_state_1 1 e_struct_4_state_32 1 e_struct_4_state_33 1 e_struct_4_state_64 1 e_struct_4_state_65 1 e_struct_4_state_128 1 e_union_4_state_1 1 e_union_4_state_32 1 e_union_4_state_33 1 e_union_4_state_64 1 e_union_4_state_65 1 e_union_4_state_128 1 i_chandle 2 i_string 2 i_bit 2 i_logic 2 i_chandle_t 2 i_string_t 2 i_bit_t 2 i_logic_t 2 i_array_2_state_1 2 i_array_2_state_32 2 i_array_2_state_33 2 i_array_2_state_64 2 i_array_2_state_65 2 i_array_2_state_128 2 i_struct_2_state_1 2 i_struct_2_state_32 2 i_struct_2_state_33 2 i_struct_2_state_64 2 i_struct_2_state_65 2 i_struct_2_state_128 2 i_union_2_state_1 2 i_union_2_state_32 2 i_union_2_state_33 2 i_union_2_state_64 2 i_union_2_state_65 2 i_union_2_state_128 2 i_array_4_state_1 2 i_array_4_state_32 2 i_array_4_state_33 2 i_array_4_state_64 2 i_array_4_state_65 2 i_array_4_state_128 2 i_struct_4_state_1 2 i_struct_4_state_32 2 i_struct_4_state_33 2 i_struct_4_state_64 2 i_struct_4_state_65 2 i_struct_4_state_128 2 i_union_4_state_1 2 i_union_4_state_32 2 i_union_4_state_33 2 i_union_4_state_64 2 i_union_4_state_65 2 i_union_4_state_128 2 e_chandle 2 e_string 2 e_bit 2 e_logic 2 e_chandle_t 2 e_string_t 2 e_bit_t 2 e_logic_t 2 e_array_2_state_1 2 e_array_2_state_32 2 e_array_2_state_33 2 e_array_2_state_64 2 e_array_2_state_65 2 e_array_2_state_128 2 e_struct_2_state_1 2 e_struct_2_state_32 2 e_struct_2_state_33 2 e_struct_2_state_64 2 e_struct_2_state_65 2 e_struct_2_state_128 2 e_union_2_state_1 2 e_union_2_state_32 2 e_union_2_state_33 2 e_union_2_state_64 2 e_union_2_state_65 2 e_union_2_state_128 2 e_array_4_state_1 2 e_array_4_state_32 2 e_array_4_state_33 2 e_array_4_state_64 2 e_array_4_state_65 2 e_array_4_state_128 2 e_struct_4_state_1 2 e_struct_4_state_32 2 e_struct_4_state_33 2 e_struct_4_state_64 2 e_struct_4_state_65 2 e_struct_4_state_128 2 e_union_4_state_1 2 e_union_4_state_32 2 e_union_4_state_33 2 e_union_4_state_64 2 e_union_4_state_65 2 e_union_4_state_128 2 *-* All Finished *-* verilator-4.038/test_regress/t/t_gen_defparam_unsup_bad.v0000664000177100017500000000054213702133370023652 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); a a (); defparam a.b.W = 3; endmodule module a; b b(); endmodule module b; parameter W = 0; endmodule verilator-4.038/test_regress/t/t_preproc_ttempty.pl0000775000177100017500000000165313702133370022617 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2017 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; compile( # Override default flags v_flags => [''], verilator_flags => ["-E -P +incdir+t -Mdir $Self->{obj_dir}", ], verilator_flags2 => ['',], verilator_flags3 => ['',], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, stdout_filename => $stdout_filename, ); files_identical($stdout_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_genvar_for_bad.pl0000775000177100017500000000107413702133370022312 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_woff.pl0000775000177100017500000000105413702133370021304 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wno-WIDTH"], ); ok(1); 1; verilator-4.038/test_regress/t/t_scope_map.pl0000775000177100017500000000123113702133370021315 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2015 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["--trace --exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_ena_cc.pl0000775000177100017500000000203413702133370021737 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_ena.v"); compile( verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/c_trace_on\"/x); file_grep_not ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/_trace_off\"/x); file_grep ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); file_grep_not ("$Self->{obj_dir}/simx.vcd", qr/inside_sub/x); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } ok(1); 1; verilator-4.038/test_regress/t/t_for_funcbound.v0000664000177100017500000000271513702133370022037 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer j; integer hit_count; reg [63:0] cam_lookup_hit_vector; strings strings (); task show; input [8*8-1:0] str; reg [7:0] char; integer loc; begin $write("[%0t] ",$time); strings.stringStart(8*8-1); for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin $write("%c",char); end $write("\n"); end endtask integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin show("hello\000xx"); end if (cyc==2) begin show("world\000xx"); end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module strings; // **NOT** reentrant, just a test! integer index; task stringStart; input [31:0] bits; begin index = (bits-1)/8; end endtask function isNull; input [7:0] chr; isNull = (chr == 8'h0); endfunction function [7:0] stringByte; input [8*8-1:0] str; begin if (index<=0) stringByte=8'h0; else stringByte = str[index*8 +: 8]; index = index - 1; end endfunction endmodule verilator-4.038/test_regress/t/t_pp_misdef_bad.pl0000775000177100017500000000107113702133370022125 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_modport_dir_bad.v0000664000177100017500000000154513702133370023364 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic signal; modport slave (output signal); modport master (input signal); endinterface: dummy_if module sub ( input wire signal_i, output wire signal_o, dummy_if.master dummy_in, dummy_if.slave dummy_out ); assign dummy_in.signal = signal_i; assign signal_o = dummy_out.signal; endmodule module t (/*AUTOARG*/ // Outputs signal_o, // Inputs signal_i ); input signal_i; output signal_o; dummy_if dummy_if (); sub sub ( .signal_i(signal_i), .signal_o(signal_o), .dummy_in(dummy_if), .dummy_out(dummy_if) ); endmodule verilator-4.038/test_regress/t/t_lint_unsup_mixed.v0000664000177100017500000000105413702133370022567 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire clk, input wire a, input wire b ); integer q; // bug1120 always @ (a or posedge clk) begin if (a) q = 0; else q = q + 1; end // bug934 integer qb; always @((a && b) or posedge clk) begin if (a) qb = 0; else qb = qb + 1; end endmodule verilator-4.038/test_regress/t/t_gen_genblk_noinl.pl0000775000177100017500000000117113702133370022644 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 top_filename("t_gen_genblk.v"); scenarios(simulator => 1); compile( v_flags2 => ["-Oi"], ); execute( expect_filename => "t/t_gen_genblk.out", ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_result_type_bad.pl0000775000177100017500000000115313702133370023373 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, verilator_flags2 => ["-Wall --error-limit 0"], ); ok(1); 1; verilator-4.038/test_regress/t/t_bind.pl0000775000177100017500000000105313702133367020273 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_infinite.v0000664000177100017500000000056513702133370022042 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); initial begin forever begin end // verilator lint_off UNSIGNED for (reg [31:0] i=0; i>=0; i=i+1) begin end end endmodule verilator-4.038/test_regress/t/t_unroll_signed.v0000664000177100017500000000625013702133370022050 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Check empty blocks task EmptyFor; /* verilator public */ integer i; begin for (i = 0; i < 2; i = i+1) begin end end endtask // Check look unroller reg signed signed_tests_only = 1'sb1; integer total; integer i; reg [31:0] iu; reg [31:0] dly_to_ensure_was_unrolled [1:0]; reg [2:0] i3; integer cyc; initial cyc=0; always @ (posedge clk) begin cyc <= cyc + 1; case (cyc) 1: begin // >= signed total = 0; for (i=5; i>=0; i=i-1) begin total = total - i -1; dly_to_ensure_was_unrolled[i] <= i; end if (total != -21) $stop; end 2: begin // > signed total = 0; for (i=5; i>0; i=i-1) begin total = total - i -1; dly_to_ensure_was_unrolled[i] <= i; end if (total != -20) $stop; end 3: begin // < signed total = 0; for (i=1; i<5; i=i+1) begin total = total - i -1; dly_to_ensure_was_unrolled[i] <= i; end if (total != -14) $stop; end 4: begin // <= signed total = 0; for (i=1; i<=5; i=i+1) begin total = total - i -1; dly_to_ensure_was_unrolled[i] <= i; end if (total != -20) $stop; end // UNSIGNED 5: begin // >= unsigned total = 0; for (iu=5; iu>=1; iu=iu-1) begin total = total - iu -1; dly_to_ensure_was_unrolled[iu] <= iu; end if (total != -20) $stop; end 6: begin // > unsigned total = 0; for (iu=5; iu>1; iu=iu-1) begin total = total - iu -1; dly_to_ensure_was_unrolled[iu] <= iu; end if (total != -18) $stop; end 7: begin // < unsigned total = 0; for (iu=1; iu<5; iu=iu+1) begin total = total - iu -1; dly_to_ensure_was_unrolled[iu] <= iu; end if (total != -14) $stop; end 8: begin // <= unsigned total = 0; for (iu=1; iu<=5; iu=iu+1) begin total = total - iu -1; dly_to_ensure_was_unrolled[iu] <= iu; end if (total != -20) $stop; end //=== 9: begin // mostly cover a small index total = 0; for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin total = total - {29'd0,i3} -1; dly_to_ensure_was_unrolled[i3[0]] <= 0; end if (total != -28) $stop; end //=== 10: begin // mostly cover a small index total = 0; for (i3=0; i3<3'd7; i3=i3+3'd1) begin total = total - {29'd0,i3} -1; dly_to_ensure_was_unrolled[i3[0]] <= 0; end if (total != -28) $stop; end //=== 11: begin // width violation on <, causes extend total = 0; for (i3=3'd0; i3<7; i3=i3+1) begin total = total - {29'd0,i3} -1; dly_to_ensure_was_unrolled[i3[0]] <= 0; end if (total != -28) $stop; end //=== // width violation on <, causes extend signed // Unsupported as yet //=== 19: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase end endmodule verilator-4.038/test_regress/t/t_time_vpi_1s10ns.out0000664000177100017500000000127313702133370022467 0ustar wsnyderwsnyder:: In top.t Time scale of t is 1s / 10ns [6000000000] time%0d=60 123%0t=12300000000 dig%0t=500000000 dig%0d=5 rdig%0t=543210987 rdig%0f=5.432110 [60000000000.000000ns] time%0d=60 123%0t=123000000000.000000ns dig%0t=5000000000.000000ns dig%0d=5 rdig%0t=5432109876.543210ns rdig%0f=5.432110 [60000000000.000000ns] stime%0t=60000000000.000000ns stime%0d=60 stime%0f=60.000000 [60000000000.000000ns] rtime%0t=60000000000.000000ns rtime%0d=60 rtime%0f=60.000000 global vpiSimTime = 1,1705032704 vpiScaledRealTime = 6e+09 global vpiTimeUnit = 0 vpiTimePrecision = -8 top.t vpiSimTime = 1,1705032704 vpiScaledRealTime = 60 top.t vpiTimeUnit = 0 vpiTimePrecision = -8 *-* All Finished *-* verilator-4.038/test_regress/t/t_dpi_import.v0000664000177100017500000002402613702133370021353 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_SHORTREAL `define NO_TIME `endif `ifdef NC `define NO_SHORTREAL `define NO_TIME `endif `ifdef VERILATOR // Unsupported `define NO_SHORTREAL `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { bit [47:0] lo; bit [47:0] hi; } str_t; typedef struct packed { int a; int b; } substr_t; // Allowed import return types: // void, byte, shortint, int, longint, real, shortreal, chandle, and string // Scalar bit and logic // // Allowed argument types: // Same as above plus packed arrays import "DPI-C" pure function bit dpii_f_bit (input bit i); import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i); import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i); import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i); import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i); import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i); // Illegal to return > 32 bits, so we use longint import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i); import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i); import "DPI-C" pure function int dpii_f_int (input int i); import "DPI-C" pure function byte dpii_f_byte (input byte i); import "DPI-C" pure function shortint dpii_f_shortint (input shortint i); import "DPI-C" pure function longint dpii_f_longint (input longint i); import "DPI-C" pure function chandle dpii_f_chandle (input chandle i); import "DPI-C" pure function string dpii_f_string (input string i); import "DPI-C" pure function real dpii_f_real (input real i); `ifndef NO_SHORTREAL import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i); `endif import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o); import "DPI-C" pure function void dpii_v_int (input int i, output int o); import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o); import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o); import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o); import "DPI-C" pure function void dpii_v_struct (input str_t i, output str_t o); import "DPI-C" pure function void dpii_v_substruct(input substr_t i, output int o); import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o); import "DPI-C" pure function void dpii_v_string (input string i, inout string o); import "DPI-C" pure function void dpii_v_real (input real i, output real o); import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o); import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o); import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o); `ifndef NO_SHORTREAL import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o); `endif import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o); import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o); import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o); import "DPI-C" pure function void dpii_v_reg (input reg i, output reg o); import "DPI-C" pure function void dpii_v_reg15 (input reg [14:0] i, output reg [14:0] o); import "DPI-C" pure function void dpii_v_reg95 (input reg [94:0] i, output reg [94:0] o); import "DPI-C" pure function void dpii_v_integer (input integer i, output integer o); `ifndef NO_TIME import "DPI-C" pure function void dpii_v_time (input time i, output time o); `endif import "DPI-C" pure function int dpii_f_strlen (input string i); import "DPI-C" function void dpii_f_void (); // Try a task import "DPI-C" task dpii_t_void (); import "DPI-C" context task dpii_t_void_context (); import "DPI-C" task dpii_t_int (input int i, output int o); // Try non-pure, aliasing with name import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i); bit i_b, o_b; bit [7:0] i_b8; bit [8:0] i_b9; bit [15:0] i_b16; bit [16:0] i_b17; bit [31:0] i_b32; bit [32:0] i_b33, o_b33; bit [63:0] i_b64, o_b64; bit [94:0] i_b95, o_b95; bit [95:0] i_b96, o_b96; int i_i, o_i; byte i_y, o_y; shortint i_s, o_s; longint i_l, o_l; str_t i_t, o_t; substr_t i_ss; int o_ss; int unsigned i_iu, o_iu; shortint unsigned i_su, o_su; longint unsigned i_lu, o_lu; // verilator lint_off UNDRIVEN chandle i_c, o_c; string i_n, o_n; // verilator lint_on UNDRIVEN real i_d, o_d; `ifndef NO_SHORTREAL shortreal i_f, o_f; `endif reg i_r, o_r; reg [14:0] i_r15, o_r15; reg [94:0] i_r95, o_r95; integer i_in, o_in; time i_tm, o_tm; bit [94:0] wide; bit [6*8:1] string6; initial begin wide = 95'h15caff7a73c48afee4ffcb57; i_b = 1'b1; i_b8 = {1'b1,wide[8-2:0]}; i_b9 = {1'b1,wide[9-2:0]}; i_b16 = {1'b1,wide[16-2:0]}; i_b17 = {1'b1,wide[17-2:0]}; i_b32 = {1'b1,wide[32-2:0]}; i_b33 = {1'b1,wide[33-2:0]}; i_b64 = {1'b1,wide[64-2:0]}; i_b95 = {1'b1,wide[95-2:0]}; i_b96 = {1'b1,wide[96-2:0]}; i_i = {1'b1,wide[32-2:0]}; i_iu= {1'b1,wide[32-2:0]}; i_y = {1'b1,wide[8-2:0]}; i_s = {1'b1,wide[16-2:0]}; i_su= {1'b1,wide[16-2:0]}; i_l = {1'b1,wide[64-2:0]}; i_lu= {1'b1,wide[64-2:0]}; i_t = {1'b1,wide[95-1:0]}; i_d = 32.1; i_ss.a = 32'h054321ab; i_ss.b = 32'h05a43b21; `ifndef NO_SHORTREAL i_f = 30.2; `endif i_r = '0; i_r15 = wide[14:0]; i_r95 = wide[94:0]; i_in = -1234; i_tm = 62; if (dpii_f_bit (i_b) !== ~i_b) $stop; if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop; if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop; if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop; if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop; if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop; // These return different sizes, so we need to truncate // verilator lint_off WIDTH o_b33 = dpii_f_bit33 (i_b33); o_b64 = dpii_f_bit64 (i_b64); // verilator lint_on WIDTH if (o_b33 !== ~i_b33) $stop; if (o_b64 !== ~i_b64) $stop; if (dpii_f_bit (i_b) !== ~i_b) $stop; if (dpii_f_int (i_i) !== ~i_i) $stop; if (dpii_f_byte (i_y) !== ~i_y) $stop; if (dpii_f_shortint (i_s) !== ~i_s) $stop; if (dpii_f_longint (i_l) !== ~i_l) $stop; if (dpii_f_chandle (i_c) !== i_c) $stop; if (dpii_f_string (i_n) != i_n) $stop; if (dpii_f_real (i_d) != i_d+1.5) $stop; `ifndef NO_SHORTREAL if (dpii_f_shortreal(i_f) != i_f+1.5) $stop; `endif dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop; dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop; dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop; dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop; dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop; dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop; dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop; dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop; dpii_v_struct (i_t,o_t); if (o_t !== ~i_t) $stop; dpii_v_substruct(i_ss,o_ss); if (o_ss !== i_ss.a - i_ss.b) $stop; dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop; dpii_v_string (i_n,o_n); if (o_n != i_n) $stop; dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop; `ifndef NO_SHORTREAL dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop; `endif dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop; dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop; dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop; dpii_v_reg (i_r,o_r); if (o_r !== ~i_r) $stop; dpii_v_reg15 (i_r15,o_r15); if (o_r15 !== ~i_r15) $stop; dpii_v_reg95 (i_r95,o_r95); if (o_r95 !== ~i_r95) $stop; dpii_v_integer (i_in,o_in); if (o_in != ~i_in) $stop; `ifndef NO_TIME dpii_v_time (i_tm,o_tm); if (o_tm != ~i_tm) $stop; `endif if (dpii_f_strlen ("")!=0) $stop; if (dpii_f_strlen ("s")!=1) $stop; if (dpii_f_strlen ("st")!=2) $stop; if (dpii_f_strlen ("str")!=3) $stop; if (dpii_f_strlen ("stri")!=4) $stop; if (dpii_f_strlen ("string_l")!=8) $stop; if (dpii_f_strlen ("string_len")!=10) $stop; string6 = "hello6"; `ifdef VERILATOR string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function `endif if (dpii_f_strlen (string6) != 6) $stop; dpii_f_void(); dpii_t_void(); dpii_t_void_context(); i_i = 32'h456789ab; dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop; // Check alias if (oth_f_int1(32'd123) !== ~32'd123) $stop; if (oth_f_int2(32'd124) !== ~32'd124) $stop; $write("*-* All Finished *-*\n"); $finish; end always @ (posedge clk) begin i_b <= ~i_b; // This once mis-threw a BLKSEQ warning dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop; end endmodule verilator-4.038/test_regress/t/t_lint_import_name2_bad.pl0000775000177100017500000000117213702133370023603 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_gate_pmos.pl0000775000177100017500000000141513702133370022207 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_tri_gate.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ['+define+T_PMOS',], make_flags => 'CPPFLAGS_ADD=-DT_PMOS', verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_slice_dtype_bad.out0000664000177100017500000000033613702133370023515 0ustar wsnyderwsnyder%Error: t/t_mem_slice_dtype_bad.v:23:45: ADD unexpected in assignment to unpacked array 23 | completed_cnt[id] <= completed_cnt_dp + 1; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_unpacked_concat_bad.out0000664000177100017500000000334613702133370023500 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_unpacked_concat_bad.v:17:46: Unsupported: Replication to form 'bit[31:0]$[1:0]' data type : ... In instance t 17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; | ^ %Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:17:47: Unsized numbers/parameters not allowed in replications. : ... In instance t 17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; | ^~~~~ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error-UNSUPPORTED: t/t_unpacked_concat_bad.v:18:45: Unsupported: Replication to form 'bit[31:0]$[1:0]' data type : ... In instance t 18 | localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; | ^ %Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:18:46: Unsized numbers/parameters not allowed in concatenations. : ... In instance t 18 | localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; | ^~~~~ %Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:18:60: Unsized numbers/parameters not allowed in replications. : ... In instance t 18 | localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_dpi_export_c.cpp0000664000177100017500000001612113702133370022176 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include "svdpi.h" #ifdef _WIN32 # define T_PRI64 "I64" #else // Linux or compliant Unix flavors # define T_PRI64 "ll" #endif //====================================================================== #if defined(VERILATOR) # ifdef T_DPI_EXPORT_NOOPT # include "Vt_dpi_export_noopt__Dpi.h" # else # include "Vt_dpi_export__Dpi.h" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { extern int dpix_run_tests(); extern int dpix_t_int(int i, int* o); extern int dpix_t_renamed(int i, int* o); extern int dpix_int123(); extern unsigned char dpix_f_bit(unsigned char i); extern svBitVecVal dpix_f_bit15(const svBitVecVal* i); extern svBitVecVal dpix_f_bit48(const svBitVecVal* i); extern int dpix_f_int(int i); extern char dpix_f_byte(char i); extern short int dpix_f_shortint(short int i); extern long long dpix_f_longint(long long i); extern void* dpix_f_chandle(void* i); extern int dpix_sub_inst(int i); extern void dpix_t_reg(svLogic i, svLogic* o); extern void dpix_t_reg15(const svLogicVecVal* i, svLogicVecVal* o); extern void dpix_t_reg95(const svLogicVecVal* i, svLogicVecVal* o); extern void dpix_t_integer(const svLogicVecVal* i, svLogicVecVal* o); extern void dpix_t_time(const svLogicVecVal* i, svLogicVecVal* o); } #endif //====================================================================== #define CHECK_RESULT(type, got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d:", __FILE__, __LINE__); \ union { type a; long long l; } u; \ u.l = 0; u.a = got; if (u.a) {/*used*/} \ printf(" GOT = %" T_PRI64 "x", u.l); \ u.l = 0; u.a = exp; if (u.a) {/*used*/} \ printf(" EXP = %" T_PRI64 "x\n", u.l); \ return __LINE__; \ } #define CHECK_RESULT_NNULL(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = %p EXP = !NULL\n", __FILE__, __LINE__, (got)); \ return __LINE__; \ } static int check_sub(const char* name, int i) { svScope scope = svGetScopeFromName(name); #ifdef TEST_VERBOSE printf("svGetScopeFromName(\"%s\") -> %p\n", name, scope); #endif CHECK_RESULT_NNULL(scope); svScope prev = svGetScope(); svScope sout = svSetScope(scope); CHECK_RESULT(svScope, sout, prev); CHECK_RESULT(svScope, svGetScope(), scope); #ifndef T_DPI_EXPORT_NOOPT int out = dpix_sub_inst(100 * i); CHECK_RESULT(int, out, 100 * i + i); #endif return 0; // OK } // Called from our Verilog code to run the tests int dpix_run_tests() { printf("dpix_run_tests:\n"); #ifdef VERILATOR static int didDump = 0; if (didDump++ == 0) { # ifdef TEST_VERBOSE Verilated::internalsDump(); # endif } #endif #ifndef CADENCE // Unimplemented; how hard is it? printf("svDpiVersion: %s\n", svDpiVersion()); CHECK_RESULT(bool, strcmp(svDpiVersion(), "1800-2005")==0 || strcmp(svDpiVersion(), "P1800-2005")==0 , 1); #endif CHECK_RESULT(int, dpix_int123(), 0x123); #ifndef CADENCE // No export calls from an import int o; dpix_t_int(0x456, &o); CHECK_RESULT(unsigned long, o, ~0x456UL); dpix_t_renamed(0x456, &o); CHECK_RESULT(int, o, 0x458UL); #endif svBitVecVal vec10[1] = {0x10}; CHECK_RESULT(int, dpix_f_bit(1), 0x0); CHECK_RESULT(int, dpix_f_bit(0), 0x1); CHECK_RESULT(int, dpix_f_bit15(vec10) & 0x7fUL, 0x6f); // Simulators disagree over the next three's sign extension unless we mask the upper bits CHECK_RESULT(int, dpix_f_int(1) & 0xffffffffUL, 0xfffffffeUL); CHECK_RESULT(int, dpix_f_byte(1) & 0xffUL, 0xfe); CHECK_RESULT(int, dpix_f_shortint(1) & 0xffffUL, 0xfffeUL); CHECK_RESULT(unsigned long long, dpix_f_longint(1), 0xfffffffffffffffeULL); CHECK_RESULT(void*, dpix_f_chandle((void*)(12345)), (void*)(12345)); { svBitVecVal i_vec48[2] = {0xab782a12, 0x8a413bd9}; svBitVecVal o_vec48[2] = {0, 0}; dpix_t_bit48(i_vec48, o_vec48); CHECK_RESULT(int, o_vec48[0], ~i_vec48[0]); #ifdef VCS // VCS has bug where doesn't clean input CHECK_RESULT(int, o_vec48[1], (~i_vec48[1])); #else CHECK_RESULT(int, o_vec48[1], (~i_vec48[1]) & 0x0000ffffUL); #endif } { svBitVecVal i_vec95[3] = {0x72912312, 0xab782a12, 0x8a413bd9}; svBitVecVal o_vec95[3] = {0, 0, 0}; dpix_t_bit95(i_vec95, o_vec95); CHECK_RESULT(int, o_vec95[0], ~i_vec95[0]); CHECK_RESULT(int, o_vec95[1], ~i_vec95[1]); CHECK_RESULT(int, o_vec95[2], (~i_vec95[2]) & 0x7fffffffUL); } { svBitVecVal i_vec96[3] = {0xf2912312, 0xab782a12, 0x8a413bd9}; svBitVecVal o_vec96[3] = {0, 0, 0}; dpix_t_bit96(i_vec96, o_vec96); CHECK_RESULT(int, o_vec96[0], ~i_vec96[0]); CHECK_RESULT(int, o_vec96[1], ~i_vec96[1]); CHECK_RESULT(int, o_vec96[2], ~i_vec96[2]); } extern void dpix_t_reg(svLogic i, svLogic* o); { svLogic i = 0; svLogic o; dpix_t_reg(i, &o); CHECK_RESULT(svLogic, o, 1); i = 1; dpix_t_reg(i, &o); CHECK_RESULT(svLogic, o, 0); } { svLogicVecVal i[1]; i[0].aval = 0x12; i[0].bval = 0; svLogicVecVal o[1]; dpix_t_reg15(i, o); CHECK_RESULT(int, o[0].aval, (~i[0].aval) & 0x7fff); CHECK_RESULT(int, o[0].bval, 0); } { svLogicVecVal i[3]; i[0].aval = 0x72912312; i[0].bval = 0; i[1].aval = 0xab782a12; i[1].bval = 0; i[2].aval = 0x8a413bd9; i[2].bval = 0; svLogicVecVal o[3]; dpix_t_reg95(i, o); CHECK_RESULT(int, o[0].aval, ~i[0].aval); CHECK_RESULT(int, o[1].aval, ~i[1].aval); CHECK_RESULT(int, o[2].aval, (~i[2].aval) & 0x7fffffffUL); CHECK_RESULT(int, o[0].bval, 0); CHECK_RESULT(int, o[1].bval, 0); CHECK_RESULT(int, o[2].bval, 0); } #if !defined(VCS) && !defined(CADENCE) { svLogicVecVal i[2]; i[0].aval = 0x72912312; i[0].bval = 0; i[1].aval = 0xab782a12; i[1].bval = 0; svLogicVecVal o[2]; dpix_t_time(i, o); CHECK_RESULT(int, o[0].aval, ~i[0].aval); CHECK_RESULT(int, o[1].aval, ~i[1].aval); CHECK_RESULT(int, o[0].bval, 0); CHECK_RESULT(int, o[1].bval, 0); } #endif if (int bad = check_sub("top.t.a", 1)) return bad; if (int bad = check_sub("top.t.b", 2)) return bad; return -1; // OK status } verilator-4.038/test_regress/t/t_enum_recurse_bad2.out0000664000177100017500000000027413702133370023132 0ustar wsnyderwsnyder%Error: t/t_enum_recurse_bad2.v:7:14: Self-referential enumerated type definition 7 | typedef enum foo_t { A = 'b0, B = 'b1 } foo_t; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_genvar_misuse_bad.pl0000775000177100017500000000117713702133370023035 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug408"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_timescale_default.out0000664000177100017500000000006213702133370023213 0ustar wsnyderwsnyderTime scale of t is 1ps / 1ps *-* All Finished *-* verilator-4.038/test_regress/t/t_sys_file_basic_uz.dat0000664000177100017500000003600013702133370023177 0ustar wsnyderwsnyder  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ¡¢£¤¥¦§¨©ª«¬­®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ  !!""##$$%%&&''(())**++,,--..//00112233445566778899::;;<<==>>??@@AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPPQQRRSSTTUUVVWWXXYYZZ[[\\]]^^__``aabbccddeeffgghhiijjkkllmmnnooppqqrrssttuuvvwwxxyyzz{{||}}~~€€‚‚ƒƒ„„……††‡‡ˆˆ‰‰ŠŠ‹‹ŒŒŽŽ‘‘’’““””••––——˜˜™™šš››œœžžŸŸ  ¡¡¢¢££¤¤¥¥¦¦§§¨¨©©ªª««¬¬­­®®¯¯°°±±²²³³´´µµ¶¶··¸¸¹¹ºº»»¼¼½½¾¾¿¿ÀÀÁÁÂÂÃÃÄÄÅÅÆÆÇÇÈÈÉÉÊÊËËÌÌÍÍÎÎÏÏÐÐÑÑÒÒÓÓÔÔÕÕÖÖ××ØØÙÙÚÚÛÛÜÜÝÝÞÞßßààááââããääååææççèèééêêëëììííîîïïððññòòóóôôõõöö÷÷øøùùúúûûüüýýþþÿÿ       ! !" !"#!"#$"#$%#$%&$%&'%&'(&'()'()*()*+)*+,*+,-+,-.,-./-./0./01/0120123123423453456456756786789789:89:;9:;<:;<=;<=><=>?=>?@>?@A?@AB@ABCABCDBCDECDEFDEFGEFGHFGHIGHIJHIJKIJKLJKLMKLMNLMNOMNOPNOPQOPQRPQRSQRSTRSTUSTUVTUVWUVWXVWXYWXYZXYZ[YZ[\Z[\][\]^\]^_]^_`^_`a_`ab`abcabcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopqopqrpqrsqrstrstustuvtuvwuvwxvwxywxyzxyz{yz{|z{|}{|}~|}~}~€~€€‚€‚ƒ‚ƒ„‚ƒ„…ƒ„…†„…†‡…†‡ˆ†‡ˆ‰‡ˆ‰Šˆ‰Š‹‰Š‹ŒŠ‹Œ‹ŒŽŒŽŽŽ‘‘’‘’“‘’“”’“”•“”•–”•–—•–—˜–—˜™—˜™š˜™š›™š›œš›œ›œžœžŸžŸ žŸ ¡Ÿ ¡¢ ¡¢£¡¢£¤¢£¤¥£¤¥¦¤¥¦§¥¦§¨¦§¨©§¨©ª¨©ª«©ª«¬ª«¬­«¬­®¬­®¯­®¯°®¯°±¯°±²°±²³±²³´²³´µ³´µ¶´µ¶·µ¶·¸¶·¸¹·¸¹º¸¹º»¹º»¼º»¼½»¼½¾¼½¾¿½¾¿À¾¿ÀÁ¿ÀÁÂÀÁÂÃÁÂÃÄÂÃÄÅÃÄÅÆÄÅÆÇÅÆÇÈÆÇÈÉÇÈÉÊÈÉÊËÉÊËÌÊËÌÍËÌÍÎÌÍÎÏÍÎÏÐÎÏÐÑÏÐÑÒÐÑÒÓÑÒÓÔÒÓÔÕÓÔÕÖÔÕÖ×ÕÖ×ØÖ×ØÙ×ØÙÚØÙÚÛÙÚÛÜÚÛÜÝÛÜÝÞÜÝÞßÝÞßàÞßàáßàáâàáâãáâãäâãäåãäåæäåæçåæçèæçèéçèéêèéêëéêëìêëìíëìíîìíîïíîïðîïðñïðñòðñòóñòóôòóôõóôõöôõö÷õö÷øö÷øù÷øùúøùúûùúûüúûüýûüýþüýþÿýþÿþÿÿ              ! !" !"# !"#$ !"#$% !"#$%& !"#$%&'!"#$%&'("#$%&'()#$%&'()*$%&'()*+%&'()*+,&'()*+,-'()*+,-.()*+,-./)*+,-./0*+,-./01+,-./012,-./0123-./01234./012345/01234560123456712345678234567893456789:456789:;56789:;<6789:;<=789:;<=>89:;<=>?9:;<=>?@:;<=>?@A;<=>?@AB<=>?@ABC=>?@ABCD>?@ABCDE?@ABCDEF@ABCDEFGABCDEFGHBCDEFGHICDEFGHIJDEFGHIJKEFGHIJKLFGHIJKLMGHIJKLMNHIJKLMNOIJKLMNOPJKLMNOPQKLMNOPQRLMNOPQRSMNOPQRSTNOPQRSTUOPQRSTUVPQRSTUVWQRSTUVWXRSTUVWXYSTUVWXYZTUVWXYZ[UVWXYZ[\VWXYZ[\]WXYZ[\]^XYZ[\]^_YZ[\]^_`Z[\]^_`a[\]^_`ab\]^_`abc]^_`abcd^_`abcde_`abcdef`abcdefgabcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstuopqrstuvpqrstuvwqrstuvwxrstuvwxystuvwxyztuvwxyz{uvwxyz{|vwxyz{|}wxyz{|}~xyz{|}~yz{|}~€z{|}~€{|}~€‚|}~€‚ƒ}~€‚ƒ„~€‚ƒ„…€‚ƒ„…†€‚ƒ„…†‡‚ƒ„…†‡ˆ‚ƒ„…†‡ˆ‰ƒ„…†‡ˆ‰Š„…†‡ˆ‰Š‹…†‡ˆ‰Š‹Œ†‡ˆ‰Š‹Œ‡ˆ‰Š‹ŒŽˆ‰Š‹ŒŽ‰Š‹ŒŽŠ‹ŒŽ‘‹ŒŽ‘’ŒŽ‘’“Ž‘’“”Ž‘’“”•‘’“”•–‘’“”•–—‘’“”•–—˜’“”•–—˜™“”•–—˜™š”•–—˜™š›•–—˜™š›œ–—˜™š›œ—˜™š›œž˜™š›œžŸ™š›œžŸ š›œžŸ ¡›œžŸ ¡¢œžŸ ¡¢£žŸ ¡¢£¤žŸ ¡¢£¤¥Ÿ ¡¢£¤¥¦ ¡¢£¤¥¦§¡¢£¤¥¦§¨¢£¤¥¦§¨©£¤¥¦§¨©ª¤¥¦§¨©ª«¥¦§¨©ª«¬¦§¨©ª«¬­§¨©ª«¬­®¨©ª«¬­®¯©ª«¬­®¯°ª«¬­®¯°±«¬­®¯°±²¬­®¯°±²³­®¯°±²³´®¯°±²³´µ¯°±²³´µ¶°±²³´µ¶·±²³´µ¶·¸²³´µ¶·¸¹³´µ¶·¸¹º´µ¶·¸¹º»µ¶·¸¹º»¼¶·¸¹º»¼½·¸¹º»¼½¾¸¹º»¼½¾¿¹º»¼½¾¿Àº»¼½¾¿ÀÁ»¼½¾¿ÀÁ¼½¾¿ÀÁÂý¾¿ÀÁÂÃľ¿ÀÁÂÃÄÅ¿ÀÁÂÃÄÅÆÀÁÂÃÄÅÆÇÁÂÃÄÅÆÇÈÂÃÄÅÆÇÈÉÃÄÅÆÇÈÉÊÄÅÆÇÈÉÊËÅÆÇÈÉÊËÌÆÇÈÉÊËÌÍÇÈÉÊËÌÍÎÈÉÊËÌÍÎÏÉÊËÌÍÎÏÐÊËÌÍÎÏÐÑËÌÍÎÏÐÑÒÌÍÎÏÐÑÒÓÍÎÏÐÑÒÓÔÎÏÐÑÒÓÔÕÏÐÑÒÓÔÕÖÐÑÒÓÔÕÖ×ÑÒÓÔÕÖ×ØÒÓÔÕÖ×ØÙÓÔÕÖ×ØÙÚÔÕÖ×ØÙÚÛÕÖ×ØÙÚÛÜÖ×ØÙÚÛÜÝ×ØÙÚÛÜÝÞØÙÚÛÜÝÞßÙÚÛÜÝÞßàÚÛÜÝÞßàáÛÜÝÞßàáâÜÝÞßàáâãÝÞßàáâãäÞßàáâãäåßàáâãäåæàáâãäåæçáâãäåæçèâãäåæçèéãäåæçèéêäåæçèéêëåæçèéêëìæçèéêëìíçèéêëìíîèéêëìíîïéêëìíîïðêëìíîïðñëìíîïðñòìíîïðñòóíîïðñòóôîïðñòóôõïðñòóôõöðñòóôõö÷ñòóôõö÷øòóôõö÷øùóôõö÷øùúôõö÷øùúûõö÷øùúûüö÷øùúûüý÷øùúûüýþøùúûüýþÿùúûüýþÿúûüýþÿûüýþÿüýþÿýþÿþÿÿ  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ¡¢£¤¥¦§¨©ª«¬­®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ  !!""##$$%%&&''(())**++,,--..//00112233445566778899::;;<<==>>??@@AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPPQQRRSSTTUUVVWWXXYYZZ[[\\]]^^__``aabbccddeeffgghhiijjkkllmmnnooppqqrrssttuuvvwwxxyyzz{{||}}~~€€‚‚ƒƒ„„……††‡‡ˆˆ‰‰ŠŠ‹‹ŒŒŽŽ‘‘’’““””••––——˜˜™™šš››œœžžŸŸ  ¡¡¢¢££¤¤¥¥¦¦§§¨¨©©ªª««¬¬­­®®¯¯°°±±²²³³´´µµ¶¶··¸¸¹¹ºº»»¼¼½½¾¾¿¿ÀÀÁÁÂÂÃÃÄÄÅÅÆÆÇÇÈÈÉÉÊÊËËÌÌÍÍÎÎÏÏÐÐÑÑÒÒÓÓÔÔÕÕÖÖ××ØØÙÙÚÚÛÛÜÜÝÝÞÞßßààááââããääååææççèèééêêëëììííîîïïððññòòóóôôõõöö÷÷øøùùúúûûüüýýþþÿÿ       ! !" !"#!"#$"#$%#$%&$%&'%&'(&'()'()*()*+)*+,*+,-+,-.,-./-./0./01/0120123123423453456456756786789789:89:;9:;<:;<=;<=><=>?=>?@>?@A?@AB@ABCABCDBCDECDEFDEFGEFGHFGHIGHIJHIJKIJKLJKLMKLMNLMNOMNOPNOPQOPQRPQRSQRSTRSTUSTUVTUVWUVWXVWXYWXYZXYZ[YZ[\Z[\][\]^\]^_]^_`^_`a_`ab`abcabcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopqopqrpqrsqrstrstustuvtuvwuvwxvwxywxyzxyz{yz{|z{|}{|}~|}~}~€~€€‚€‚ƒ‚ƒ„‚ƒ„…ƒ„…†„…†‡…†‡ˆ†‡ˆ‰‡ˆ‰Šˆ‰Š‹‰Š‹ŒŠ‹Œ‹ŒŽŒŽŽŽ‘‘’‘’“‘’“”’“”•“”•–”•–—•–—˜–—˜™—˜™š˜™š›™š›œš›œ›œžœžŸžŸ žŸ ¡Ÿ ¡¢ ¡¢£¡¢£¤¢£¤¥£¤¥¦¤¥¦§¥¦§¨¦§¨©§¨©ª¨©ª«©ª«¬ª«¬­«¬­®¬­®¯­®¯°®¯°±¯°±²°±²³±²³´²³´µ³´µ¶´µ¶·µ¶·¸¶·¸¹·¸¹º¸¹º»¹º»¼º»¼½»¼½¾¼½¾¿½¾¿À¾¿ÀÁ¿ÀÁÂÀÁÂÃÁÂÃÄÂÃÄÅÃÄÅÆÄÅÆÇÅÆÇÈÆÇÈÉÇÈÉÊÈÉÊËÉÊËÌÊËÌÍËÌÍÎÌÍÎÏÍÎÏÐÎÏÐÑÏÐÑÒÐÑÒÓÑÒÓÔÒÓÔÕÓÔÕÖÔÕÖ×ÕÖ×ØÖ×ØÙ×ØÙÚØÙÚÛÙÚÛÜÚÛÜÝÛÜÝÞÜÝÞßÝÞßàÞßàáßàáâàáâãáâãäâãäåãäåæäåæçåæçèæçèéçèéêèéêëéêëìêëìíëìíîìíîïíîïðîïðñïðñòðñòóñòóôòóôõóôõöôõö÷õö÷øö÷øù÷øùúøùúûùúûüúûüýûüýþüýþÿýþÿþÿÿ              ! !" !"# !"#$ !"#$% !"#$%& !"#$%&'!"#$%&'("#$%&'()#$%&'()*$%&'()*+%&'()*+,&'()*+,-'()*+,-.()*+,-./)*+,-./0*+,-./01+,-./012,-./0123-./01234./012345/01234560123456712345678234567893456789:456789:;56789:;<6789:;<=789:;<=>89:;<=>?9:;<=>?@:;<=>?@A;<=>?@AB<=>?@ABC=>?@ABCD>?@ABCDE?@ABCDEF@ABCDEFGABCDEFGHBCDEFGHICDEFGHIJDEFGHIJKEFGHIJKLFGHIJKLMGHIJKLMNHIJKLMNOIJKLMNOPJKLMNOPQKLMNOPQRLMNOPQRSMNOPQRSTNOPQRSTUOPQRSTUVPQRSTUVWQRSTUVWXRSTUVWXYSTUVWXYZTUVWXYZ[UVWXYZ[\VWXYZ[\]WXYZ[\]^XYZ[\]^_YZ[\]^_`Z[\]^_`a[\]^_`ab\]^_`abc]^_`abcd^_`abcde_`abcdef`abcdefgabcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstuopqrstuvpqrstuvwqrstuvwxrstuvwxystuvwxyztuvwxyz{uvwxyz{|vwxyz{|}wxyz{|}~xyz{|}~yz{|}~€z{|}~€{|}~€‚|}~€‚ƒ}~€‚ƒ„~€‚ƒ„…€‚ƒ„…†€‚ƒ„…†‡‚ƒ„…†‡ˆ‚ƒ„…†‡ˆ‰ƒ„…†‡ˆ‰Š„…†‡ˆ‰Š‹…†‡ˆ‰Š‹Œ†‡ˆ‰Š‹Œ‡ˆ‰Š‹ŒŽˆ‰Š‹ŒŽ‰Š‹ŒŽŠ‹ŒŽ‘‹ŒŽ‘’ŒŽ‘’“Ž‘’“”Ž‘’“”•‘’“”•–‘’“”•–—‘’“”•–—˜’“”•–—˜™“”•–—˜™š”•–—˜™š›•–—˜™š›œ–—˜™š›œ—˜™š›œž˜™š›œžŸ™š›œžŸ š›œžŸ ¡›œžŸ ¡¢œžŸ ¡¢£žŸ ¡¢£¤žŸ ¡¢£¤¥Ÿ ¡¢£¤¥¦ ¡¢£¤¥¦§¡¢£¤¥¦§¨¢£¤¥¦§¨©£¤¥¦§¨©ª¤¥¦§¨©ª«¥¦§¨©ª«¬¦§¨©ª«¬­§¨©ª«¬­®¨©ª«¬­®¯©ª«¬­®¯°ª«¬­®¯°±«¬­®¯°±²¬­®¯°±²³­®¯°±²³´®¯°±²³´µ¯°±²³´µ¶°±²³´µ¶·±²³´µ¶·¸²³´µ¶·¸¹³´µ¶·¸¹º´µ¶·¸¹º»µ¶·¸¹º»¼¶·¸¹º»¼½·¸¹º»¼½¾¸¹º»¼½¾¿¹º»¼½¾¿Àº»¼½¾¿ÀÁ»¼½¾¿ÀÁ¼½¾¿ÀÁÂý¾¿ÀÁÂÃľ¿ÀÁÂÃÄÅ¿ÀÁÂÃÄÅÆÀÁÂÃÄÅÆÇÁÂÃÄÅÆÇÈÂÃÄÅÆÇÈÉÃÄÅÆÇÈÉÊÄÅÆÇÈÉÊËÅÆÇÈÉÊËÌÆÇÈÉÊËÌÍÇÈÉÊËÌÍÎÈÉÊËÌÍÎÏÉÊËÌÍÎÏÐÊËÌÍÎÏÐÑËÌÍÎÏÐÑÒÌÍÎÏÐÑÒÓÍÎÏÐÑÒÓÔÎÏÐÑÒÓÔÕÏÐÑÒÓÔÕÖÐÑÒÓÔÕÖ×ÑÒÓÔÕÖ×ØÒÓÔÕÖ×ØÙÓÔÕÖ×ØÙÚÔÕÖ×ØÙÚÛÕÖ×ØÙÚÛÜÖ×ØÙÚÛÜÝ×ØÙÚÛÜÝÞØÙÚÛÜÝÞßÙÚÛÜÝÞßàÚÛÜÝÞßàáÛÜÝÞßàáâÜÝÞßàáâãÝÞßàáâãäÞßàáâãäåßàáâãäåæàáâãäåæçáâãäåæçèâãäåæçèéãäåæçèéêäåæçèéêëåæçèéêëìæçèéêëìíçèéêëìíîèéêëìíîïéêëìíîïðêëìíîïðñëìíîïðñòìíîïðñòóíîïðñòóôîïðñòóôõïðñòóôõöðñòóôõö÷ñòóôõö÷øòóôõö÷øùóôõö÷øùúôõö÷øùúûõö÷øùúûüö÷øùúûüý÷øùúûüýþøùúûüýþÿùúûüýþÿúûüýþÿûüýþÿüýþÿýþÿþÿÿverilator-4.038/test_regress/t/t_tri_gen.pl0000775000177100017500000000105313702133370021000 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_initial_dlyass.v0000664000177100017500000000115413702133370022212 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; integer a; integer b; initial begin a <= 22; b <= 33; end always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin if (a != 22) $stop; if (b != 33) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_select_bound1.v0000664000177100017500000000426713702133370021741 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug823 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = crc[2:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] mask; // From test of Test.v wire [3:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[3:0]), .mask (mask[3:0]), // Inputs .clk (clk), .in (in[2:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out & mask}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'ha9d3a7a69d2bea75 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, mask, // Inputs clk, in ); input clk; input [2:0] in; output reg [3:0] out; output reg [3:0] mask; localparam [15:5] p = 11'h1ac; always @(posedge clk) begin // verilator lint_off WIDTH out <= p[15 + in -: 5]; // verilator lint_on WIDTH mask[3] <= ((15 + in - 5) < 12); mask[2] <= ((15 + in - 5) < 13); mask[1] <= ((15 + in - 5) < 14); mask[0] <= ((15 + in - 5) < 15); end endmodule verilator-4.038/test_regress/t/t_clk_condflop.pl0000775000177100017500000000105713702133367022020 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_prot_lib_secret.pl0000775000177100017500000000157613702133370022542 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile ( verilator_flags2 => ["--protect-lib", "secret", "--protect-key", "SECRET_FAKE_KEY"], verilator_make_gcc => 0, verilator_make_gmake => 0, make_main => 0, make_top_shell => 0, ); run(cmd=>[$ENV{MAKE}, "-C", "$Self->{obj_dir}", "-f", "V$Self->{name}.mk"]); ok(1); 1; verilator-4.038/test_regress/t/t_tri_unconn.pl0000775000177100017500000000105313702133370021527 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_intdot2.v0000664000177100017500000001045013702133370021415 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg check; initial check = 1'b0; Genit g (.clk(clk), .check(check)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out); cyc <= cyc + 1; if (cyc==0) begin // Setup check <= 1'b0; end else if (cyc==1) begin check <= 1'b1; end else if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end //`define WAVES `ifdef WAVES initial begin $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"}); $dumpvars(12, t); end `endif endmodule module One; wire one = 1'b1; endmodule module Genit ( input clk, input check); // ARRAY One cellarray1[1:0] (); //cellarray[0..1][0..1] always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop; always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop; // IF generate // genblk1 refers to the if's name, not the "generate" itself. if (1'b1) // IMPLIED begin: genblk1 One ifcell1(); // genblk1.ifcell1 else One ifcell1(); // genblk1.ifcell1 endgenerate // On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc `ifdef verilator always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop; //`else // NOT SUPPORTED accoring to spec - generic block references `endif generate begin : namedif2 if (1'b1) One ifcell2(); // namedif2.genblk1.ifcell2 end endgenerate `ifdef verilator always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop; //`else // NOT SUPPORTED accoring to spec - generic block references `endif generate if (1'b1) begin : namedif3 One ifcell3(); // namedif3.ifcell3 end endgenerate always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop; // CASE generate case (1'b1) 1'b1 : One casecell10(); // genblk3.casecell10 endcase endgenerate `ifdef verilator always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop; //`else // NOT SUPPORTED accoring to spec - generic block references `endif generate case (1'b1) 1'b1 : begin : namedcase11 One casecell11(); end endcase endgenerate always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop; genvar i; genvar j; // IF generate for (i = 0; i < 2; i = i + 1) One cellfor20 (); // genblk4[0..1].cellfor20 endgenerate `ifdef verilator always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop; always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop; //`else // NOT SUPPORTED accoring to spec - generic block references `endif // COMBO generate for (i = 0; i < 2; i = i + 1) begin : namedfor21 One cellfor21 (); // namedfor21[0..1].cellfor21 end endgenerate always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop; generate for (i = 0; i < 2; i = i + 1) begin : namedfor30 for (j = 0; j < 2; j = j + 1) begin : forb30 if (j == 0) begin : forif30 One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a end else `ifdef verilator begin : forif30b `else begin : forif30 // forif30 seems to work on some simulators, not verilator yet `endif One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b end end end endgenerate always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; `ifdef verilator always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; `else always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; `endif endmodule verilator-4.038/test_regress/t/t_tri_select.pl0000775000177100017500000000123713702133370021512 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_pullvec_bad.pl0000775000177100017500000000111013702133370022501 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_compare.v0000664000177100017500000000301413702133367022031 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Andrew Bardsley. // SPDX-License-Identifier: CC0-1.0 // bug1071 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] array_1 [2:0]; reg [3:0] array_2 [2:0]; reg [3:0] array_3 [3:1]; reg [3:0] elem; reg array_1_ne_array_2; reg array_1_eq_array_2; reg array_1_ne_array_3; reg array_1_eq_array_3; initial begin array_1[0] = 4'b1000; array_1[1] = 4'b1000; array_1[2] = 4'b1000; array_2[0] = 4'b1000; array_2[1] = 4'b1000; array_2[2] = 4'b1000; array_3[1] = 4'b1000; array_3[2] = 4'b0100; array_3[3] = 4'b0100; array_1_ne_array_2 = array_1 != array_2; // 0 array_1_eq_array_2 = array_1 == array_2; // 0 array_1_ne_array_3 = array_1 != array_3; // 1 array_1_eq_array_3 = array_1 == array_3; // 1 //Not legal: array_rxor = ^ array_1; //Not legal: array_rxnor = ^~ array_1; //Not legal: array_ror = | array_1; //Not legal: array_rand = & array_1; `ifdef TEST_VERBOSE $write("array_1_ne_array2==%0d\n", array_1_ne_array_2); $write("array_1_ne_array3==%0d\n", array_1_ne_array_3); `endif if (array_1_ne_array_2 !== 0) $stop; if (array_1_eq_array_2 !== 1) $stop; if (array_1_ne_array_3 !== 1) $stop; if (array_1_eq_array_3 !== 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_inst_array_connect.v0000664000177100017500000000353013702133370023066 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module for Issue#1631 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Julien Margetts. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; localparam N = 4; wire [7:0] cval1[0:N-1]; wire [7:0] cval2[N-1:0]; wire [7:0] cval3[0:N-1]; wire [7:0] cval4[N-1:0]; wire [3:0] inc; assign inc = 4'b0001; // verilator lint_off LITENDIAN COUNTER UCOUNTER1[N-1:0] ( .clk (clk), .inc (inc), .o (cval1) // Twisted ); COUNTER UCOUNTER2[N-1:0] ( .clk (clk), .inc (inc), .o (cval2) // Matches ); COUNTER UCOUNTER3[0:N-1] ( .clk (clk), .inc (inc), .o (cval3) // Matches ); COUNTER UCOUNTER4[0:N-1] ( .clk (clk), .inc (inc), .o (cval4) // Twisted ); always @(posedge clk) begin if ((cval1[3] != cval2[0]) || (cval3[3] != cval4[0])) $stop; if ((cval1[0] + cval1[1] + cval1[2] + cval2[1] + cval2[2] + cval2[3] + cval3[0] + cval3[1] + cval3[2] + cval4[1] + cval4[2] + cval4[3]) != 0) $stop; `ifdef TEST_VERBOSE $display("%d %d %d %d", cval1[0], cval1[1], cval1[2], cval1[3]); $display("%d %d %d %d", cval2[0], cval2[1], cval2[2], cval2[3]); $display("%d %d %d %d", cval3[0], cval3[1], cval3[2], cval3[3]); $display("%d %d %d %d", cval4[0], cval4[1], cval4[2], cval4[3]); `endif if (cval1[0] + cval1[3] > 3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module COUNTER ( input clk, input inc, output reg [7:0] o ); initial o = 8'd0; // No reset input always @(posedge clk) if (inc) o <= o + 1; endmodule verilator-4.038/test_regress/t/t_param_in_func_bad.out0000664000177100017500000000051413702133370023152 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_param_in_func_bad.v:24:26: Unsupported: Parameters in functions 24 | localparam logic[7:0] digits[10] | ^~~~~~ %Error: t/t_param_in_func_bad.v:28:11: Can't find definition of variable: 'digits' 28 | return digits[d]; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_comb_use.v0000664000177100017500000000121213702133370022017 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs hval, // Inputs sel ); input logic [2:0] sel; output logic [3:0] hval; /*AUTOINPUT*/ /*AUTOOUTPUT*/ always_comb begin unique case (sel) 3'h0: hval = 4'hd; 3'h1: hval = 4'hc; 3'h7: hval = 4'hf; default: begin $ignore ("ERROR : %s [%m]", $sformatf ("Illegal sel = %x", sel)); hval = 4'bx; end endcase end endmodule verilator-4.038/test_regress/t/t_threads_counter.v0000664000177100017500000000077413702133370022402 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc!=0) begin if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_display_time.out0000664000177100017500000000063213702133370022227 0ustar wsnyderwsnyderdefault: [10] 0t time [ 10] No0 time p= 10 0p='ha -9,0,,0: [10] 0t time [10] No0 time p= 10 0p='ha -9,0,,10: [10] 0t time [ 10] No0 time p= 10 0p='ha -9,0,ns,5: [10ns] 0t time [ 10ns] No0 time p= 10 0p='ha -9,3,ns,8: [10.000ns] 0t time [10.000ns] No0 time p= 10 0p='ha *-* All Finished *-* verilator-4.038/test_regress/t/t_var_dotted2_inl1.pl0000775000177100017500000000117513702133370022516 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_var_dotted2.v"); compile( v_flags2 => ['+define+USE_INLINE',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_latchgate.pl0000775000177100017500000000105313702133367022144 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_for_count.pl0000775000177100017500000000105313702133370021347 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_extends_this.v0000664000177100017500000000152613702133367023101 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Base; int value = 1; function void test; if (value != 1) $stop; if (this.value != 1) $stop; endfunction endclass class Cls extends Base; int value = 2; function void test; if (value != 2) $stop; if (this.value != 2) $stop; if (super.value != 1) $stop; super.test(); super.value = 10; this.value = 20; if (super.value != 10) $stop; if (value != 20) $stop;; endfunction endclass module t (/*AUTOARG*/); initial begin Cls c; c = new; c.test(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_preproc_inc3.vh0000664000177100017500000000077113702133370021744 0ustar wsnyderwsnyder`line 2 "inc3_a_filename_from_line_directive" 0 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef _EXAMPLE_INC2_V_ `define _EXAMPLE_INC2_V_ 1 `define _EMPTY // FOO At file `__FILE__ line `__LINE__ `else `error "INC2 File already included once" `endif // guard `ifdef not_defined `include "NotToBeInced.vh" `endif verilator-4.038/test_regress/t/t_select_bad_range.v0000664000177100017500000000072013702133370022441 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [43:0] mi; reg sel; reg [3:0] sel2; always @ (posedge clk) begin mi = 44'h123; sel = mi[44]; sel2 = mi[44:41]; $write ("Bad select %x %x\n", sel, sel2); end endmodule verilator-4.038/test_regress/t/t_var_tieout.v0000664000177100017500000000213513702133370021363 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug291 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer out18; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire out1; // From test of Test.v wire out19; // From test of Test.v wire out1b; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out1 (out1), .out18 (out18), .out1b (out1b), .out19 (out19)); // Test loop always @ (posedge clk) begin if (out1 !== 1'b1) $stop; if (out18 !== 32'h18) $stop; if (out1b !== 1'b1) $stop; if (out19 !== 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test ( output wire out1 = 1'b1, output integer out18 = 32'h18, output var out1b = 1'b1, output var logic out19 = 1'b1 ); endmodule verilator-4.038/test_regress/t/t_fuzz_always_bad.out0000664000177100017500000000071213702133370022727 0ustar wsnyderwsnyder%Error: t/t_fuzz_always_bad.v:10:15: Can't find definition of 'a' in dotted variable: 'c.a' 10 | always @ c.a c:h; | ^ %Error: t/t_fuzz_always_bad.v:10:19: Can't find definition of task/function: 'h' 10 | always @ c.a c:h; | ^ %Error-UNSUPPORTED: t/t_fuzz_always_bad.v:10:14: Unsupported: Complex statement in sensitivity list 10 | always @ c.a c:h; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_param_real.pl0000775000177100017500000000105313702133370021454 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_print.out0000664000177100017500000000052313702133370021715 0ustar wsnyderwsnyder[0] In top.t: Hi Time scale of t is 1ns / 1ps Time: ' 0' 10ns=10000 Time: ' 0-my-ms' 10ns=0-my-ms Time: ' 0.0-my-ms' 10ns=0.0-my-ms Time: ' 0.00-my-us' 10ns=0.01-my-us Time: ' 0.000-my-ns' 10ns=10.000-my-ns Time: ' 0.000-my-ps' 10ns=10000.000-my-ps Time: ' 0.0000-my-fs' 10ns=10000000.0000-my-fs *-* All Finished *-* verilator-4.038/test_regress/t/t_flag_nomod_bad.pl0000775000177100017500000000107113702133370022264 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_wire_behp1800_bad.pl0000775000177100017500000000116713702133370022442 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only --language 1800-2017"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_pattern_unpacked.v0000664000177100017500000000451413702133367023740 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); logic [3:0] array_simp [1:0] [3:0]; // big endian array int irep[1:2][1:6]; initial begin array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop; // verilator lint_off WIDTH array_simp[0] = '{ 3 ,2 ,1, 0 }; // verilator lint_on WIDTH if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop; // Doesn't seem to work for unpacked arrays in other simulators //array_simp[0] = '{ 1:4'd3, default:13 }; //if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop; array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_1234) $stop; // Doesn't seem to work for unpacked arrays in other simulators array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_3210) $stop; array_simp = '{2{ '{4{ 4'd3 }} }}; if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3333_3333) $stop; // Not legal in other simulators - replication doesn't match // However IEEE suggests this is legal. //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} // Replication irep = '{2{ '{3 {4, 5}}}}; if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]} != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]} != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_mem_packed_bad.v0000664000177100017500000000206113702133370022073 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; logic [1:0][27:0] ch01; logic [1:0][27:0] ch02; logic [1:0][27:0] ch03; logic [27:0] ch04[1:0]; /* verilator lint_off WIDTH */ always @ (posedge clk) begin // LHS is a 2D packed array, RHS is 1D packed or Const. Allowed now. ch01 <= {{2{28'd4}}}; ch02 <= {{2{cyc}}}; ch03 <= 56'd0; // LHS is 1D packed, 1D unpacked, this should never work. ch04 <= 56'd0; $display("ch01: %0x %0x", ch01[0], ch01[1]); $display("ch01: %0x %0x", ch02[0], ch02[1]); $display("ch01: %0x %0x", ch03[0], ch03[1]); $display("ch01: %0x %0x", ch04[0], ch04[1]); end /* verilator lint_on WIDTH */ endmodule verilator-4.038/test_regress/t/t_fuzz_always_bad.v0000664000177100017500000000041213702133370022362 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1577 module t; always @ c.a c:h; endmodule verilator-4.038/test_regress/t/t_math_signed7.v0000664000177100017500000000207113702133370021552 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; reg alu_ltu, alu_lts; logic [3:0] in_op1; logic [3:0] in_op2; reg aaa_ltu, aaa_lts; always @(posedge clk) begin in_op1 = 4'sb1110; in_op2 = 4'b0010; aaa_ltu = in_op1 < in_op2; // bug999 aaa_lts = $signed(in_op1) < $signed(in_op2); `checkh (aaa_ltu, 1'b0); `checkh (aaa_lts, 1'b1); end generate if (1) begin always @(posedge clk) begin in_op1 = 4'sb1110; in_op2 = 4'b0010; alu_ltu = in_op1 < in_op2; // bug999 alu_lts = $signed(in_op1) < $signed(in_op2); `checkh (alu_ltu, 1'b0); `checkh (alu_lts, 1'b1); $write("*-* All Finished *-*\n"); $finish; end end endgenerate endmodule verilator-4.038/test_regress/t/t_func_const2_bad.pl0000775000177100017500000000107313702133370022404 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2017 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_cat.pl0000775000177100017500000000156713702133370021310 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_cat.cpp"], ); execute( check_finished => 1, ); system("cat $Self->{obj_dir}/simpart_0000.vcd " ." $Self->{obj_dir}/simpart_0000_cat*.vcd > $Self->{obj_dir}/simall.vcd"); vcd_identical("$Self->{obj_dir}/simall.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_mod_nomod.pl0000775000177100017500000000077713702133370021340 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_param_sel_range_bad.pl0000775000177100017500000000114413702133370023277 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_param_sel_range.v"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_var.cpp0000664000177100017500000005007513702133370021173 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #else #include "Vt_vpi_var.h" #include "verilated.h" #include "svdpi.h" #include "Vt_vpi_var__Dpi.h" #include "verilated_vpi.h" #include "verilated_vcd_c.h" #endif #include #include #include #include #include "TestSimulator.h" #include "TestVpi.h" // __FILE__ is too long #define FILENM "t_vpi_var.cpp" #define TEST_MSG \ if (0) printf unsigned int main_time = 0; unsigned int callback_count = 0; unsigned int callback_count_half = 0; unsigned int callback_count_quad = 0; unsigned int callback_count_strs = 0; unsigned int callback_count_strs_max = 500; //====================================================================== #define CHECK_RESULT_VH(got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d: GOT = %p EXP = %p\n", FILENM, __LINE__, (got), (exp)); \ return __LINE__; \ } #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ return __LINE__; \ } // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_HEX(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << std::hex \ << ": GOT = " << (got) << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ ((got) != NULL) ? (got) : "", ((exp) != NULL) ? (exp) : ""); \ return __LINE__; \ } #define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp) // We cannot replace those with VL_STRINGIFY, not available when PLI is build #define STRINGIFY(x) STRINGIFY2(x) #define STRINGIFY2(x) #x int _mon_check_mcd() { PLI_INT32 status; PLI_UINT32 mcd; PLI_BYTE8* filename = (PLI_BYTE8*)(STRINGIFY(TEST_OBJ_DIR) "/mcd_open.tmp"); mcd = vpi_mcd_open(filename); CHECK_RESULT_NZ(mcd); { // Check it got written FILE* fp = fopen(filename, "r"); CHECK_RESULT_NZ(fp); fclose(fp); } status = vpi_mcd_printf(mcd, (PLI_BYTE8*)"hello %s", "vpi_mcd_printf"); CHECK_RESULT(status, strlen("hello vpi_mcd_printf")); status = vpi_mcd_flush(mcd); CHECK_RESULT(status, 0); status = vpi_mcd_close(mcd); // Icarus says 'error' on ones we're not using, so check only used ones return 0. CHECK_RESULT(status & mcd, 0); status = vpi_flush(); CHECK_RESULT(status, 0); return 0; } int _mon_check_callbacks_error(p_cb_data cb_data) { vpi_printf((PLI_BYTE8*)"%%Error: callback should not be executed\n"); return 1; } int _mon_check_callbacks() { t_cb_data cb_data; cb_data.reason = cbEndOfSimulation; cb_data.cb_rtn = _mon_check_callbacks_error; cb_data.user_data = 0; cb_data.value = NULL; cb_data.time = NULL; vpiHandle vh = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(vh); PLI_INT32 status = vpi_remove_cb(vh); CHECK_RESULT_NZ(status); return 0; } int _value_callback(p_cb_data cb_data) { if (TestSimulator::is_verilator()) { // this check only makes sense in Verilator CHECK_RESULT(cb_data->value->value.integer + 10, main_time); } callback_count++; return 0; } int _value_callback_half(p_cb_data cb_data) { if (TestSimulator::is_verilator()) { // this check only makes sense in Verilator CHECK_RESULT(cb_data->value->value.integer * 2 + 10, main_time); } callback_count_half++; return 0; } int _value_callback_quad(p_cb_data cb_data) { for (int index = 0; index < 2; index++) { CHECK_RESULT_HEX(cb_data->value->value.vector[1].aval, (unsigned long)((index == 2) ? 0x1c77bb9bUL : 0x12819213UL)); CHECK_RESULT_HEX(cb_data->value->value.vector[0].aval, (unsigned long)((index == 2) ? 0x3784ea09UL : 0xabd31a1cUL)); } callback_count_quad++; return 0; } int _mon_check_value_callbacks() { vpiHandle vh1 = VPI_HANDLE("count"); CHECK_RESULT_NZ(vh1); s_vpi_value v; v.format = vpiIntVal; vpi_get_value(vh1, &v); t_cb_data cb_data; cb_data.reason = cbValueChange; cb_data.cb_rtn = _value_callback; cb_data.obj = vh1; cb_data.value = &v; cb_data.time = NULL; vpiHandle vh = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(vh); vh1 = VPI_HANDLE("half_count"); CHECK_RESULT_NZ(vh1); cb_data.obj = vh1; cb_data.cb_rtn = _value_callback_half; vh = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(vh); vh1 = VPI_HANDLE("quads"); CHECK_RESULT_NZ(vh1); v.format = vpiVectorVal; cb_data.obj = vh1; cb_data.cb_rtn = _value_callback_quad; vh = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(vh); vh1 = vpi_handle_by_index(vh1, 2); CHECK_RESULT_NZ(vh1); cb_data.obj = vh1; cb_data.cb_rtn = _value_callback_quad; vh = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(vh); return 0; } int _mon_check_var() { TestVpiHandle vh1 = VPI_HANDLE("onebit"); CHECK_RESULT_NZ(vh1); TestVpiHandle vh2 = vpi_handle_by_name((PLI_BYTE8*)TestSimulator::top(), NULL); CHECK_RESULT_NZ(vh2); // scope attributes const char* p; p = vpi_get_str(vpiName, vh2); CHECK_RESULT_CSTR(p, "t"); p = vpi_get_str(vpiFullName, vh2); CHECK_RESULT_CSTR(p, TestSimulator::top()); p = vpi_get_str(vpiType, vh2); CHECK_RESULT_CSTR(p, "vpiModule"); TestVpiHandle vh3 = vpi_handle_by_name((PLI_BYTE8*)"onebit", vh2); CHECK_RESULT_NZ(vh3); // onebit attributes PLI_INT32 d; d = vpi_get(vpiType, vh3); CHECK_RESULT(d, vpiReg); if (TestSimulator::has_get_scalar()) { d = vpi_get(vpiVector, vh3); CHECK_RESULT(d, 0); } p = vpi_get_str(vpiName, vh3); CHECK_RESULT_CSTR(p, "onebit"); p = vpi_get_str(vpiFullName, vh3); CHECK_RESULT_CSTR(p, TestSimulator::rooted("onebit")); p = vpi_get_str(vpiType, vh3); CHECK_RESULT_CSTR(p, "vpiReg"); // array attributes TestVpiHandle vh4 = VPI_HANDLE("fourthreetwoone"); CHECK_RESULT_NZ(vh4); if (TestSimulator::has_get_scalar()) { d = vpi_get(vpiVector, vh4); CHECK_RESULT(d, 1); p = vpi_get_str(vpiType, vh4); CHECK_RESULT_CSTR(p, "vpiMemory"); } t_vpi_value tmpValue; tmpValue.format = vpiIntVal; { TestVpiHandle vh10 = vpi_handle(vpiLeftRange, vh4); CHECK_RESULT_NZ(vh10); vpi_get_value(vh10, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 4); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiConstant"); } { TestVpiHandle vh10 = vpi_handle(vpiRightRange, vh4); CHECK_RESULT_NZ(vh10); vpi_get_value(vh10, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 3); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiConstant"); } { TestVpiHandle vh10 = vpi_iterate(vpiMemoryWord, vh4); CHECK_RESULT_NZ(vh10); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiIterator"); TestVpiHandle vh11 = vpi_scan(vh10); CHECK_RESULT_NZ(vh11); p = vpi_get_str(vpiType, vh11); CHECK_RESULT_CSTR(p, "vpiMemoryWord"); TestVpiHandle vh12 = vpi_handle(vpiLeftRange, vh11); CHECK_RESULT_NZ(vh12); vpi_get_value(vh12, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 2); p = vpi_get_str(vpiType, vh12); CHECK_RESULT_CSTR(p, "vpiConstant"); TestVpiHandle vh13 = vpi_handle(vpiRightRange, vh11); CHECK_RESULT_NZ(vh13); vpi_get_value(vh13, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 1); p = vpi_get_str(vpiType, vh13); CHECK_RESULT_CSTR(p, "vpiConstant"); } return 0; } int _mon_check_varlist() { const char* p; TestVpiHandle vh2 = VPI_HANDLE("sub"); CHECK_RESULT_NZ(vh2); TestVpiHandle vh10 = vpi_iterate(vpiReg, vh2); CHECK_RESULT_NZ(vh10.nofree()); TestVpiHandle vh11 = vpi_scan(vh10); CHECK_RESULT_NZ(vh11); p = vpi_get_str(vpiFullName, vh11); CHECK_RESULT_CSTR(p, TestSimulator::rooted("sub.subsig1")); TestVpiHandle vh12 = vpi_scan(vh10); CHECK_RESULT_NZ(vh12); p = vpi_get_str(vpiFullName, vh12); CHECK_RESULT_CSTR(p, TestSimulator::rooted("sub.subsig2")); TestVpiHandle vh13 = vpi_scan(vh10); CHECK_RESULT(vh13, 0); return 0; } int _mon_check_getput() { TestVpiHandle vh2 = VPI_HANDLE("onebit"); CHECK_RESULT_NZ(vh2); s_vpi_value v; v.format = vpiIntVal; vpi_get_value(vh2, &v); CHECK_RESULT(v.value.integer, 0); s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; v.value.integer = 1; vpi_put_value(vh2, &v, &t, vpiNoDelay); vpi_get_value(vh2, &v); CHECK_RESULT(v.value.integer, 1); return 0; } int _mon_check_quad() { TestVpiHandle vh2 = VPI_HANDLE("quads"); CHECK_RESULT_NZ(vh2); s_vpi_value v; t_vpi_vecval vv[2]; bzero(&vv, sizeof(vv)); s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; TestVpiHandle vhidx2 = vpi_handle_by_index(vh2, 2); CHECK_RESULT_NZ(vhidx2); TestVpiHandle vhidx3 = vpi_handle_by_index(vh2, 3); CHECK_RESULT_NZ(vhidx2); v.format = vpiVectorVal; v.value.vector = vv; v.value.vector[1].aval = 0x12819213UL; v.value.vector[0].aval = 0xabd31a1cUL; vpi_put_value(vhidx2, &v, &t, vpiNoDelay); v.format = vpiVectorVal; v.value.vector = vv; v.value.vector[1].aval = 0x1c77bb9bUL; v.value.vector[0].aval = 0x3784ea09UL; vpi_put_value(vhidx3, &v, &t, vpiNoDelay); vpi_get_value(vhidx2, &v); CHECK_RESULT(v.value.vector[1].aval, 0x12819213UL); CHECK_RESULT(v.value.vector[1].bval, 0); vpi_get_value(vhidx3, &v); CHECK_RESULT(v.value.vector[1].aval, 0x1c77bb9bUL); CHECK_RESULT(v.value.vector[1].bval, 0); return 0; } int _mon_check_string() { static struct { const char* name; const char* initial; const char* value; } text_test_obs[] = { {"text_byte", "B", "xxA"}, // x's dropped {"text_half", "Hf", "xxT2"}, // x's dropped {"text_word", "Word", "Tree"}, {"text_long", "Long64b", "44Four44"}, {"text", "Verilog Test module", "lorem ipsum"}, }; for (int i = 0; i < 5; i++) { TestVpiHandle vh1 = VPI_HANDLE(text_test_obs[i].name); CHECK_RESULT_NZ(vh1); s_vpi_value v; s_vpi_time t = {vpiSimTime, 0, 0, 0.0}; s_vpi_error_info e; v.format = vpiStringVal; vpi_get_value(vh1, &v); if (vpi_chk_error(&e)) { printf("%%vpi_chk_error : %s\n", e.message); } CHECK_RESULT_CSTR_STRIP(v.value.str, text_test_obs[i].initial); v.value.str = (PLI_BYTE8*)text_test_obs[i].value; vpi_put_value(vh1, &v, &t, vpiNoDelay); } return 0; } int _mon_check_putget_str(p_cb_data cb_data) { static TestVpiHandle cb; static struct { TestVpiHandle scope, sig, rfr, check, verbose; char str[128 + 1]; // char per bit plus null terminator int type; // value type in .str union { PLI_INT32 integer; s_vpi_vecval vector[4]; } value; // reference } data[129]; if (cb_data) { // this is the callback static unsigned int seed = 1; s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; for (int i = 2; i <= 128; i++) { static s_vpi_value v; int words = (i + 31) >> 5; TEST_MSG("========== %d ==========\n", i); if (callback_count_strs) { // check persistance if (data[i].type) { v.format = data[i].type; } else { static PLI_INT32 vals[] = {vpiBinStrVal, vpiOctStrVal, vpiHexStrVal, vpiDecStrVal}; v.format = vals[rand_r(&seed) % ((words > 2) ? 3 : 4)]; TEST_MSG("new format %d\n", v.format); } vpi_get_value(data[i].sig, &v); TEST_MSG("%s\n", v.value.str); if (data[i].type) { CHECK_RESULT_CSTR(v.value.str, data[i].str); } else { data[i].type = v.format; strcpy(data[i].str, v.value.str); } } // check for corruption v.format = (words == 1) ? vpiIntVal : vpiVectorVal; vpi_get_value(data[i].sig, &v); if (v.format == vpiIntVal) { TEST_MSG("%08x %08x\n", v.value.integer, data[i].value.integer); CHECK_RESULT(v.value.integer, data[i].value.integer); } else { for (int k = 0; k < words; k++) { TEST_MSG("%d %08x %08x\n", k, v.value.vector[k].aval, data[i].value.vector[k].aval); CHECK_RESULT_HEX(v.value.vector[k].aval, data[i].value.vector[k].aval); } } if (callback_count_strs & 7) { // put same value back - checking encoding/decoding equivalent v.format = data[i].type; v.value.str = data[i].str; vpi_put_value(data[i].sig, &v, &t, vpiNoDelay); v.format = vpiIntVal; v.value.integer = 1; // vpi_put_value(data[i].verbose, &v, &t, vpiNoDelay); vpi_put_value(data[i].check, &v, &t, vpiNoDelay); } else { // stick a new random value in unsigned int mask = ((i & 31) ? (1 << (i & 31)) : 0) - 1; if (words == 1) { v.value.integer = rand_r(&seed); data[i].value.integer = v.value.integer &= mask; v.format = vpiIntVal; TEST_MSG("new value %08x\n", data[i].value.integer); } else { TEST_MSG("new value\n"); for (int j = 0; j < 4; j++) { data[i].value.vector[j].aval = rand_r(&seed); if (j == (words - 1)) { data[i].value.vector[j].aval &= mask; } TEST_MSG(" %08x\n", data[i].value.vector[j].aval); } v.value.vector = data[i].value.vector; v.format = vpiVectorVal; } vpi_put_value(data[i].sig, &v, &t, vpiNoDelay); vpi_put_value(data[i].rfr, &v, &t, vpiNoDelay); } if ((callback_count_strs & 1) == 0) data[i].type = 0; } if (++callback_count_strs == callback_count_strs_max) { int success = vpi_remove_cb(cb); CHECK_RESULT_NZ(success); }; } else { // setup and install for (int i = 1; i <= 128; i++) { char buf[32]; snprintf(buf, sizeof(buf), TestSimulator::rooted("arr[%d].arr"), i); CHECK_RESULT_NZ(data[i].scope = vpi_handle_by_name((PLI_BYTE8*)buf, NULL)); CHECK_RESULT_NZ(data[i].sig = vpi_handle_by_name((PLI_BYTE8*)"sig", data[i].scope)); CHECK_RESULT_NZ(data[i].rfr = vpi_handle_by_name((PLI_BYTE8*)"rfr", data[i].scope)); CHECK_RESULT_NZ(data[i].check = vpi_handle_by_name((PLI_BYTE8*)"check", data[i].scope)); CHECK_RESULT_NZ(data[i].verbose = vpi_handle_by_name((PLI_BYTE8*)"verbose", data[i].scope)); } static t_cb_data cb_data; static s_vpi_value v; static TestVpiHandle count_h = VPI_HANDLE("count"); cb_data.reason = cbValueChange; cb_data.cb_rtn = _mon_check_putget_str; // this function cb_data.obj = count_h; cb_data.value = &v; cb_data.time = NULL; v.format = vpiIntVal; cb = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(cb); } return 0; } int _mon_check_vlog_info() { s_vpi_vlog_info vlog_info; PLI_INT32 rtn = vpi_get_vlog_info(&vlog_info); CHECK_RESULT(rtn, 1); CHECK_RESULT(vlog_info.argc, 4); CHECK_RESULT_CSTR(vlog_info.argv[1], "+PLUS"); CHECK_RESULT_CSTR(vlog_info.argv[2], "+INT=1234"); CHECK_RESULT_CSTR(vlog_info.argv[3], "+STRSTR"); if (TestSimulator::is_verilator()) { CHECK_RESULT_CSTR(vlog_info.product, "Verilator"); CHECK_RESULT(strlen(vlog_info.version) > 0, 1); } return 0; } int mon_check() { // Callback from initial block in monitor if (int status = _mon_check_mcd()) return status; if (int status = _mon_check_callbacks()) return status; if (int status = _mon_check_value_callbacks()) return status; if (int status = _mon_check_var()) return status; if (int status = _mon_check_varlist()) return status; if (int status = _mon_check_getput()) return status; if (int status = _mon_check_quad()) return status; if (int status = _mon_check_string()) return status; if (int status = _mon_check_putget_str(NULL)) return status; if (int status = _mon_check_vlog_info()) return status; #ifndef IS_VPI VerilatedVpi::selfTest(); #endif return 0; // Ok } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { vpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out #ifdef VERILATOR #ifdef TEST_VERBOSE Verilated::scopesDump(); #endif #endif #if VM_TRACE Verilated::traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; main_time += 10; while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += 1; topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } CHECK_RESULT(callback_count, 501); CHECK_RESULT(callback_count_half, 250); CHECK_RESULT(callback_count_quad, 2); CHECK_RESULT(callback_count_strs, callback_count_strs_max); if (!Verilated::gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete topp, topp); exit(0L); } #endif verilator-4.038/test_regress/t/t_clk_inp_init.v0000664000177100017500000000426613702133367021661 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Check initialisation of cloned clock variables // // This tests issue 1327 (Strange initialisation behaviour with // "VinpClk" cloned clock variables) // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Rupert Swarbrick (Argon Design). // SPDX-License-Identifier: CC0-1.0 // bug1327 // This models some device under test with an asynchronous reset pin // which counts to 15. module dut (input wire clk, input wire rst_n, output wire done); reg [3:0] counter; always @(posedge clk or negedge rst_n) begin if (rst_n & ! clk) begin $display("[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.", $time, clk, rst_n); $stop; end if (! rst_n) begin counter <= 4'd0; end else begin counter <= counter < 4'd15 ? counter + 4'd1 : counter; end end assign done = rst_n & (counter == 4'd15); endmodule module t(input wire clk, input wire rst_n); wire dut_done; // A small FSM for driving the test // // This is just designed to be enough to force Verilator to make a // "VinpClk" variant of dut_rst_n. // Possible states: // // 0: Device in reset // 1: Device running // 2: Device finished reg [1:0] state; always @(posedge clk or negedge rst_n) begin if (! rst_n) begin state <= 0; end else begin if (state == 2'd0) begin // One clock after resetting the device, we switch to running // it. state <= 2'd1; end else if (state == 2'd1) begin // If the device is running, we switch to finished when its // done signal goes high. state <= dut_done ? 2'd2 : 2'd1; end else begin // If the dut has finished, the test is done. $write("*-* All Finished *-*\n"); $finish; end end end wire dut_rst_n = rst_n & (state != 0); wire done; dut dut_i (.clk (clk), .rst_n (dut_rst_n), .done (dut_done)); endmodule verilator-4.038/test_regress/t/t_preproc_def09.pl0000775000177100017500000000142613702133370022016 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; compile( verilator_flags2 => ['-E'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, stdout_filename => $stdout_filename, ); files_identical($stdout_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_sys_writemem.gold4.mem0000664000177100017500000000142013631173020023243 0ustar wsnyderwsnyder000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 7755400437654321276543211765432107654321abcdef10 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 7755400a37654321276543211765432107654321abcdef11 7755400b37654321276543211765432107654321abcdef12 7755400c37654321276543211765432107654321abcdef13 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 verilator-4.038/test_regress/t/t_unopt_converge_ndbg_bad.pl0000775000177100017500000000134413702133370024211 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2007 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_unopt_converge.v"); compile( v_flags2 => ['+define+ALLOW_UNOPT'], make_flags => 'CPPFLAGS_ADD=-UVL_DEBUG', ); execute( fails => 1, expect_filename => $Self->{golden_filename}, ) if $Self->{vlt_all}; ok(1); 1; verilator-4.038/test_regress/t/t_flag_parameter.pl0000775000177100017500000000121613702133370022323 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( # It is not possible to put them into the options file v_flags2 => ['-f t/t_flag_parameter.vc'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlcov_rewrite.pl0000775000177100017500000000167513702133370022255 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); foreach my $basename ("t_vlcov_data_a.dat", "t_vlcov_data_b.dat", "t_vlcov_data_c.dat", "t_vlcov_data_d.dat", ) { run(cmd => ["../bin/verilator_coverage", "t/${basename}", "--write", "$Self->{obj_dir}/${basename}" ], tee => 0, verilator_run => 1, ); files_identical("$Self->{obj_dir}/${basename}", "t/${basename}"); } ok(1); 1; verilator-4.038/test_regress/t/t_order_doubleloop.v0000664000177100017500000000465013702133370022545 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT // verilator lint_off MULTIDRIVEN // verilator lint_off BLKANDNBLK reg [31:0] comcnt; reg [31:0] dlycnt; initial dlycnt=0; reg [31:0] lastdlycnt; initial lastdlycnt = 0; reg [31:0] comrun; initial comrun = 0; reg [31:0] comrunm1; reg [31:0] dlyrun; initial dlyrun = 0; reg [31:0] dlyrunm1; always @ (posedge clk) begin $write("[%0t] cyc %d\n",$time,cyc); cyc <= cyc + 1; if (cyc==2) begin // Test # of iters lastdlycnt = 0; comcnt = 0; dlycnt <= 0; end if (cyc==3) begin dlyrun <= 5; dlycnt <= 0; end if (cyc==4) begin comrun = 4; end end always @ (negedge clk) begin if (cyc==5) begin $display("%d %d\n", dlycnt, comcnt); if (dlycnt != 32'd5) $stop; if (comcnt != 32'd19) $stop; $write("*-* All Finished *-*\n"); $finish; end end // This forms a "loop" where we keep going through the always till comrun=0 reg runclk; initial runclk = 1'b0; always @ (/*AS*/comrunm1 or dlycnt) begin if (lastdlycnt != dlycnt) begin comrun = 3; $write ("[%0t] comrun=%0d start\n", $time, comrun); end else if (comrun > 0) begin comrun = comrunm1; if (comrunm1==1) begin runclk = 1; $write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun); end else $write ("[%0t] comrun=%0d\n", $time, comrun); end lastdlycnt = dlycnt; end always @ (/*AS*/comrun) begin if (comrun!=0) begin comrunm1 = comrun - 32'd1; comcnt = comcnt + 32'd1; $write("[%0t] comcnt=%0d\n",$time,comcnt); end end // This forms a "loop" where we keep going through the always till dlyrun=0 reg runclkrst; always @ (posedge runclk) begin runclkrst <= 1; $write ("[%0t] runclk\n", $time); if (dlyrun > 0) begin dlyrun <= dlyrun - 32'd1; dlycnt <= dlycnt + 32'd1; $write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1); end end always @* begin if (runclkrst) begin $write ("[%0t] runclk reset\n", $time); runclkrst = 0; runclk = 0; end end endmodule verilator-4.038/test_regress/t/t_flag_topmod2_bad.out0000664000177100017500000000016213702133341022723 0ustar wsnyderwsnyder%Error: Specified --top-module 'a' isn't at the top level, it's under another cell 'a_top' %Error: Exiting due to verilator-4.038/test_regress/t/t_tri_eqcase.pl0000775000177100017500000000105313702133370021470 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_missing_bad.pl0000775000177100017500000000120313702133370022662 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only --Wall -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_index2.pl0000775000177100017500000000076613702133370022113 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_export_context_bad.cpp0000664000177100017500000000176013702133370024251 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_export_context_bad__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { extern void dpix_task(); } #endif //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = NULL; int main(int argc, char* argv[]) { topp = new VM_PREFIX; Verilated::debug(0); topp->eval(); dpix_task(); // Missing svSetScope return 1; } verilator-4.038/test_regress/t/t_clk_vecgen1.v0000664000177100017500000000546513702133367021402 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; wire [1:0] clkvec = crc[1:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [1:0] count; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .count (count[1:0]), // Inputs .clkvec (clkvec[1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {62'h0, count}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'hfe8bac0bb1a0e53b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule `ifdef T_TEST1 module Test ( input wire [1:0] clkvec, // verilator lint_off MULTIDRIVEN output reg [1:0] count // verilator lint_on MULTIDRIVEN ); genvar igen; generate for (igen=0; igen<2; igen=igen+1) begin : code_gen initial count[igen] = 1'b0; always @ (posedge clkvec[igen]) count[igen] <= count[igen] + 1; end endgenerate always @ (count) begin $write("hi\n"); end endmodule `endif `ifdef T_TEST2 module Test ( input wire [1:0] clkvec, // verilator lint_off MULTIDRIVEN output reg [1:0] count // verilator lint_on MULTIDRIVEN ); genvar igen; generate for (igen=0; igen<2; igen=igen+1) begin : code_gen wire clk_tmp = clkvec[igen]; // Unsupported: Count is multidriven, though if we did better analysis it wouldn't // need to be. initial count[igen] = 1'b0; always @ (posedge clk_tmp) count[igen] <= count[igen] + 1; end endgenerate endmodule `endif `ifdef T_TEST3 module Test ( input wire [1:0] clkvec, output wire [1:0] count ); genvar igen; generate for (igen=0; igen<2; igen=igen+1) begin : code_gen wire clk_tmp = clkvec[igen]; reg tmp_count = 1'b0; always @ (posedge clk_tmp) begin tmp_count <= tmp_count + 1; end assign count[igen] = tmp_count; end endgenerate endmodule `endif verilator-4.038/test_regress/t/t_sys_writemem_b.gold3.mem0000664000177100017500000000542013702133370023552 0ustar wsnyderwsnyder00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 01000000000001000011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 01000000000010100011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010001 01000000000010110011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010010 01000000000011000011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010011 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 verilator-4.038/test_regress/t/t_alw_dly.pl0000775000177100017500000000112513702133367021012 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-Wno-CLKDATA"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_protect_ids_bad.out0000664000177100017500000000100313702133370022662 0ustar wsnyderwsnyder%Error-UNSUPPORTED: Unsupported: Using --protect-ids with --public ... Suggest remove --public. %Warning-INSECURE: Using --protect-ids with --trace may expose private design details ... Suggest remove --trace. ... Use "/* verilator lint_off INSECURE */" and lint_on around source to disable this message. %Warning-INSECURE: Using --protect-ids with --vpi may expose private design details ... Suggest remove --vpi. %Error: Exiting due to verilator-4.038/test_regress/t/t_class_unsup_bad.out0000664000177100017500000000117513702133367022722 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_unsup_bad.v:7:1: Unsupported: virtual interface 7 | virtual interface vi_t vi; | ^~~~~~~ %Error-UNSUPPORTED: t/t_class_unsup_bad.v:8:1: Unsupported: virtual data type 8 | virtual vi_t vi2; | ^~~~~~~ %Error-UNSUPPORTED: t/t_class_unsup_bad.v:14:26: Unsupported: class parameters 14 | localparam LOCPAR = 10; | ^ %Error: t/t_class_unsup_bad.v:29:24: Syntax error: 'const'/'rand'/'randc' not allowed before function/task declaration 29 | const function void func_const; endfunction | ^~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_pipe_filter.out0000664000177100017500000000202613702133370022045 0ustar wsnyderwsnyder`line 1 "t/t_pipe_filter.v" 1 `line 3 "t/t_pipe_filter.v" 0 `line 7 "t/t_pipe_filter.v" 0 `line 11 "t/t_pipe_filter.v" 0 example line 10; example line 11; `line 14 "t/t_pipe_filter.v" 0 `line 14 "t/t_pipe_filter.v" 0 `line 1 "t/t_pipe_filter_inc.vh" 1 int lint_off_line_8 = 1; `line 2 "t/t_pipe_filter_inc.vh" 0 int lint_off_line_9 = 1; `line 5 "t/t_pipe_filter_inc.vh" 0 `line 9 "t/t_pipe_filter_inc.vh" 0 inc line 6; inc line 7; inc line 8; inc line 9; `line 14 "t/t_pipe_filter_inc.vh" 2 `line 14 "t/t_pipe_filter.v" 0 `line 15 "t/t_pipe_filter.v" 0 `line 16 "t/t_pipe_filter.v" 0 `line 1 "t/t_pipe_filter_inc.vh" 1 int lint_off_line_8 = 1; `line 2 "t/t_pipe_filter_inc.vh" 0 int lint_off_line_9 = 1; `line 5 "t/t_pipe_filter_inc.vh" 0 `line 9 "t/t_pipe_filter_inc.vh" 0 inc line 6; inc line 7; inc line 8; inc line 9; `line 14 "t/t_pipe_filter_inc.vh" 2 `line 16 "t/t_pipe_filter.v" 0 `line 18 "t/t_pipe_filter.v" 0 example line 15; example line 16; `line 21 "t/t_pipe_filter.v" 2 verilator-4.038/test_regress/t/t_clk_gate_ext.pl0000775000177100017500000000105313702133367022010 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_for_shuffle.pl0000775000177100017500000000105313702133370022504 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_fork_disable.out0000664000177100017500000000110313702133370022162 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_fork_disable.v:12:7: Unsupported: fork statements : ... In instance t 12 | fork | ^~~~ %Error-UNSUPPORTED: t/t_fork_disable.v:16:7: Unsupported: disable fork statements : ... In instance t 16 | disable fork; | ^~~~~~~ %Error-UNSUPPORTED: t/t_fork_disable.v:17:7: Unsupported: wait fork statements : ... In instance t 17 | wait fork; | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_port_bad.v0000664000177100017500000000057713702133370021654 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; subok subok (.a(1'b1), .b(1'b0)); sub sub (.a(1'b1), .b(1'b0)); endmodule module subok (input a,b); endmodule module sub (a); input a, b; endmodule verilator-4.038/test_regress/t/t_uniqueif.v0000664000177100017500000000446313702133370021035 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; integer a, b, c, d, e, f, g, h, i, j, k, l; always @ (posedge clk) begin cyc <= cyc + 1; //==================== // Positive test cases //==================== // Single if, which is untrue sometimes unique0 if (cyc > 5) a <= 17; // single if with else unique0 if (cyc < 3) b <= 17; else b <= 19; // multi if, some cases may not be true unique0 if (cyc < 3) c <= 17; else if (cyc > 3) c <= 19; // multi if with else, else clause hit in some cases unique0 if (cyc < 3) d <= 17; else if (cyc > 3) d <= 19; else d <= 21; // single if with else unique if (cyc < 3) f <= 17; else f <= 19; // multi if unique if (cyc < 3) g <= 17; else if (cyc >= 3) g <= 19; // multi if with else, else clause hit in some cases unique if (cyc < 3) h <= 17; else if (cyc > 3) h <= 19; else h <= 21; //==================== // Negative test cases //==================== `ifdef FAILING_ASSERTION1 $display("testing fail 1: %d", cyc); // multi if, multiple cases true unique0 if (cyc < 3) i <= 17; else if (cyc < 5) i <= 19; `endif `ifdef FAILING_ASSERTION2 // multi if, multiple cases true unique if (cyc < 3) j <= 17; else if (cyc < 5) j <= 19; `endif `ifdef FAILING_ASSERTION3 // multi if, no cases true unique if (cyc > 1000) k <= 17; else if (cyc > 2000) k <= 19; `endif `ifdef FAILING_ASSERTION4 // Single if, which is untrue sometimes. // The LRM states: "A software tool shall also issue an error if it determines that no condition' // is true, or it is possible that no condition is true, and the final if does not have a // corresponding else." In this case, the final if is the only if, but I think the clause // still applies. unique if (cyc > 5) l <= 17; `endif if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_case_genx_bad.pl0000775000177100017500000000110113702133367022113 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_f.pl0000775000177100017500000000111313702133370020564 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( v_flags2 => ["-f t/t_flag_f.vc"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mailbox.v0000664000177100017500000000403713702133370020640 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // class mailbox #(type T = dynamic_singular_type) ; // function new(int bound = 0); // function int num(); // task put( T message); // function int try_put( T message); // task get( ref T message ); // function int try_get( ref T message ); // task peek( ref T message ); // function int try_peek( ref T message ); // endclass module t(/*AUTOARG*/); mailbox m; int msg; int out; initial begin m = new(4); if (m.num() != 0) $stop; if (m.try_get(msg) > 0) $stop; msg = 123; m.put(msg); msg = 0; if (m.num() != 1) $stop; if (m.try_peek(out) <= 0) $stop; if (out != 123) $stop; if (m.num() != 0) $stop; out = 0; if (m.try_peek(out) <= 0) $stop; if (out != 123) $stop; out = 0; if (m.try_get(out) <= 0) $stop; if (out != 123) $stop; if (m.num() != 0) $stop; msg = 124; m.put(msg); out = 0; m.get(out); if (out != 124) $stop; msg = 125; m.put(msg); m.put(msg); m.try_put(msg); m.try_put(msg); if (m.num() != 4) $stop; if (m.try_put(msg) != 0) $stop; if (m.num() != 4) $stop; m.get(out); m.get(out); m.get(out); m.get(out); if (m.num() != 0) $stop; fork begin #10; // So later then get() starts below msg = 130; m.put(msg); msg = 131; m.put(msg); end begin if (m.try_get(msg) != 0) $stop; out = 0; m.get(out); // Blocks until put if (out != 130) $stop; out = 0; m.get(out); if (out != 131) $stop; end join $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_timescale_lint_bad.v0000664000177100017500000000055613702133370023011 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module pre_no_ts; endmodule `timescale 1ns/1ns module t; pre_no_ts pre_no_ts(); post_no_ts pst_no_ts(); endmodule module post_no_ts; endmodule verilator-4.038/test_regress/t/t_param_value.pl0000775000177100017500000000105313702133370021645 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_timing_reentry.v0000664000177100017500000000157313702133370022246 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); event a, b; int order = 0; initial begin order++; if (order != 1) $stop; #10; $display("[%0t]%0d -> a", $time, order); order++; if (order != 2) $stop; -> a; #10; $display("[%0t]%0d -> b", $time, order); order++; if (order != 4) $stop; -> b; #100; order++; if (order != 6) $stop; $write("*-* All Finished *-*\n"); $finish; end always @ (a or b) begin $display("[%0t]%0d entering", $time, order); order++; if (order != 3) $stop; #15; $display("[%0t]%0d 15 later", $time, order); order++; if (order != 5) $stop; end endmodule verilator-4.038/test_regress/t/t_func_wide_out_bad.v0000664000177100017500000000154513702133370022646 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); parameter MSG_PORT_WIDTH = 4350; localparam PAYLOAD_MAX_BITS = 4352; reg [MSG_PORT_WIDTH-1:0] msg; initial begin // Operator TASKREF 'func' expects 4352 bits on the Function Argument, but Function Argument's VARREF 'msg' generates 4350 bits. // verilator lint_off WIDTH func(msg); // verilator lint_on WIDTH if (msg !== {MSG_PORT_WIDTH{1'b1}}) $stop; $write("*-* All Finished *-*\n"); $finish; end function integer func (output bit [PAYLOAD_MAX_BITS-1:0] data); /*verilator no_inline_task*/ data = {PAYLOAD_MAX_BITS{1'b1}}; return 1; endfunction endmodule verilator-4.038/test_regress/t/t_typedef_array.v0000664000177100017500000000120413702133370022034 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by James Pallister. // SPDX-License-Identifier: CC0-1.0 typedef logic logic_alias_t; module t; logic_alias_t [6:1] signal; // verilator lint_off LITENDIAN logic_alias_t [1:6] signal2; // verilator lint_on LITENDIAN initial begin signal[6:1] = 'b100001; signal[3] = 'b1; signal2[1:6] = 'b100001; signal2[4] = 'b1; if (signal != 'b100101) $stop; if (signal2 != 'b100101) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_stream.v0000664000177100017500000002622613702133370020504 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Glen Gibb. // SPDX-License-Identifier: CC0-1.0 //module t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // The 'initial' code block below tests compilation-time // evaluation/optimization of the stream operator. All occurences of the stream // operator within this block are replaced prior to generation of C code. logic [3:0] dout; logic [31:0] dout32; logic [10:0] dout11; initial begin // Stream operator: << // Location: rhs of assignment // // Test slice sizes from 1 - 5 dout = { << {4'b0001}}; if (dout != 4'b1000) $stop; dout = { << 2 {4'b0001}}; if (dout != 4'b0100) $stop; dout = { << 3 {4'b0001}}; if (dout != 4'b0010) $stop; dout = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; dout = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; // Stream operator: >> // Location: rhs of assignment // // Right-streaming operator on RHS does not reorder bits dout = { >> {4'b0001}}; if (dout != 4'b0001) $stop; dout = { >> 2 {4'b0001}}; if (dout != 4'b0001) $stop; dout = { >> 3 {4'b0001}}; if (dout != 4'b0001) $stop; dout = { >> 4 {4'b0001}}; if (dout != 4'b0001) $stop; dout = { >> 5 {4'b0001}}; if (dout != 4'b0001) $stop; // Stream operator: << // Location: lhs of assignment { << {dout}} = 4'b0001; if (dout != 4'b1000) $stop; { << 2 {dout}} = 4'b0001; if (dout != 4'b0100) $stop; { << 3 {dout}} = 4'b0001; if (dout != 4'b0010) $stop; { << 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { << 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; // Stream operator: >> // Location: lhs of assignment { >> {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { >> 2 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { >> 3 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { >> 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { >> 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; // Stream operator: << // Location: lhs of assignment // RHS is *wider* than LHS /* verilator lint_off WIDTH */ { << {dout}} = 5'b00001; if (dout != 4'b1000) $stop; { << 2 {dout}} = 5'b00001; if (dout != 4'b0100) $stop; { << 3 {dout}} = 5'b00001; if (dout != 4'b0010) $stop; { << 4 {dout}} = 5'b00001; if (dout != 4'b0001) $stop; { << 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; /* verilator lint_on WIDTH */ // Stream operator: >> // Location: lhs of assignment // RHS is *wider* than LHS /* verilator lint_off WIDTH */ { >> {dout}} = 5'b01101; if (dout != 4'b0110) $stop; { >> 2 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; { >> 3 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; { >> 4 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; { >> 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; /* verilator lint_on WIDTH */ // Stream operator: << // Location: both sides of assignment { << {dout}} = { << {4'b0001}}; if (dout != 4'b0001) $stop; { << 2 {dout}} = { << 2 {4'b0001}}; if (dout != 4'b0001) $stop; { << 3 {dout}} = { << 3 {4'b0001}}; if (dout != 4'b0100) $stop; { << 4 {dout}} = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; { << 5 {dout}} = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; // Stream operator: << // Location: as an operand within a statement // // Test slice sizes from 1 - 5 if (4'({ << {4'b0001}}) != 4'b1000) $stop; if (4'({ << 2 {4'b0001}}) != 4'b0100) $stop; if (4'({ << 3 {4'b0001}}) != 4'b0010) $stop; if (4'({ << 4 {4'b0001}}) != 4'b0001) $stop; if (4'({ << 5 {4'b0001}}) != 4'b0001) $stop; // case dout32 = { << 3 { 32'b11010111000010100100010010010111 }}; if (dout32 != 32'he92910eb) $stop; dout11 = { << 4 { 11'b10010010111 }}; if (dout11 != 11'h3cc) $stop; end // The two always blocks below test run-time evaluation of the stream // operator in generated C code. // // Various stream operators are optimized away. Here's a brief summary: // // Stream op on RHS of assign // -------------------------- // X = { << a { Y } } --- C function evaluates stream operator // -- if log2(a) == int --> "fast" eval func // -- if log2(a) != int --> "slow" eval func // X = { >> a { Y } } --- stream operator is optimized away // // Stream op on LHS of assign // -------------------------- // Note: if Y.width() > X.width, then the MSBs of Y are used, not the LSBs! // { << a { X } } = Y --- stream operator is moved to RHS, eval as above // { >> a { X } } = Y --- stream operator is optimized away logic [31:0] din_i; logic [63:0] din_q; logic [95:0] din_w; // Stream op on RHS, left-stream operator logic [31:0] dout_rhs_ls_i; logic [63:0] dout_rhs_ls_q; logic [95:0] dout_rhs_ls_w; // Stream op on RHS, right-stream operator logic [31:0] dout_rhs_rs_i; logic [63:0] dout_rhs_rs_q; logic [95:0] dout_rhs_rs_w; // Stream op on both sides, left-stream operator logic [31:0] dout_bhs_ls_i; logic [63:0] dout_bhs_ls_q; logic [95:0] dout_bhs_ls_w; // Stream op on both sides, right-stream operator logic [31:0] dout_bhs_rs_i; logic [63:0] dout_bhs_rs_q; logic [95:0] dout_bhs_rs_w; // Stream operator on LHS (with concatenation on LHS) logic [3:0] din_lhs; logic [1:0] dout_lhs_ls_a, dout_lhs_ls_b; logic [1:0] dout_lhs_rs_a, dout_lhs_rs_b; // Addition operator on LHS, right-shift tests: // Testing various shift sizes to exercise fast + slow funcs logic [22:0] dout_rhs_ls_i_23_3; logic [22:0] dout_rhs_ls_i_23_4; logic [36:0] dout_rhs_ls_q_37_3; logic [36:0] dout_rhs_ls_q_37_4; always @* begin // Stream operator: << // Location: rhs of assignment // // Test each data type (I, Q, W) dout_rhs_ls_i = { << {din_i}}; dout_rhs_ls_q = { << {din_q}}; dout_rhs_ls_w = { << {din_w}}; // Stream operator: >> // Location: rhs of assignment dout_rhs_rs_i = { >> {din_i}}; dout_rhs_rs_q = { >> {din_q}}; dout_rhs_rs_w = { >> {din_w}}; // Stream operator: << // Location: lhs of assignment { << 2 {dout_lhs_ls_a, dout_lhs_ls_b}} = din_lhs; // Stream operator: >> // Location: lhs of assignment { >> 2 {dout_lhs_rs_a, dout_lhs_rs_b}} = din_lhs; // Stream operator: << // Location: both sides of assignment { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}}; { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}}; { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}}; // Stream operator: >> // Location: both sides of assignment { >> 5 {dout_bhs_rs_i}} = { >> 5 {din_i}}; { >> 5 {dout_bhs_rs_q}} = { >> 5 {din_q}}; { >> 5 {dout_bhs_rs_w}} = { >> 5 {din_w}}; // Stream operator: << // Location: both sides of assignment { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}}; { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}}; { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}}; // Stream operator: << // Location: rhs of assignment // // Verify both fast and slow paths (fast: sliceSize = power of 2) dout_rhs_ls_i_23_3 = { << 3 {din_i[22:0]}}; // SLOW dout_rhs_ls_i_23_4 = { << 4 {din_i[22:0]}}; // FAST dout_rhs_ls_q_37_3 = { << 3 {din_q[36:0]}}; // SLOW dout_rhs_ls_q_37_4 = { << 4 {din_q[36:0]}}; // FAST end always @(posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; if (cyc == 1) begin din_i <= 32'h_00_00_00_01; din_q <= 64'h_00_00_00_00_00_00_00_01; din_w <= 96'h_00_00_00_00_00_00_00_00_00_00_00_01; din_lhs <= 4'b_00_01; end if (cyc == 2) begin din_i <= 32'h_04_03_02_01; din_q <= 64'h_08_07_06_05_04_03_02_01; din_w <= 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01; din_lhs <= 4'b_01_11; if (dout_rhs_ls_i != 32'h_80_00_00_00) $stop; if (dout_rhs_ls_q != 64'h_80_00_00_00_00_00_00_00) $stop; if (dout_rhs_ls_w != 96'h_80_00_00_00_00_00_00_00_00_00_00_00) $stop; if (dout_rhs_rs_i != 32'h_00_00_00_01) $stop; if (dout_rhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; if (dout_rhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; if (dout_lhs_ls_a != 2'b_01) $stop; if (dout_lhs_ls_b != 2'b_00) $stop; if (dout_lhs_rs_a != 2'b_00) $stop; if (dout_lhs_rs_b != 2'b_01) $stop; if (dout_bhs_rs_i != 32'h_00_00_00_01) $stop; if (dout_bhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; if (dout_bhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; if (dout_bhs_ls_i != 32'h_00_00_00_10) $stop; if (dout_bhs_ls_q != 64'h_00_00_00_00_00_00_01_00) $stop; if (dout_bhs_ls_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_04) $stop; if (dout_rhs_ls_i_23_3 != 23'h_10_00_00) $stop; if (dout_rhs_ls_i_23_4 != 23'h_08_00_00) $stop; if (dout_rhs_ls_q_37_3 != 37'h_04_00_00_00_00) $stop; if (dout_rhs_ls_q_37_4 != 37'h_02_00_00_00_00) $stop; end if (cyc == 3) begin // The values below test the strange shift-merge done at the end of // the fast stream operators. // All-1s in the bits being streamed should end up as all-1s. din_i <= 32'h_00_7f_ff_ff; din_q <= 64'h_00_00_00_1f_ff_ff_ff_ff; if (dout_rhs_ls_i != 32'h_80_40_c0_20) $stop; if (dout_rhs_ls_q != 64'h_80_40_c0_20_a0_60_e0_10) $stop; if (dout_rhs_ls_w != 96'h_80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; if (dout_rhs_rs_i != 32'h_04_03_02_01) $stop; if (dout_rhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; if (dout_rhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; if (dout_bhs_ls_i != 32'h_40_30_00_18) $stop; if (dout_bhs_ls_q != 64'h_06_00_c1_81_41_00_c1_80) $stop; if (dout_bhs_ls_w != 96'h_30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; if (dout_bhs_rs_i != 32'h_04_03_02_01) $stop; if (dout_bhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; if (dout_bhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; if (dout_lhs_ls_a != 2'b_11) $stop; if (dout_lhs_ls_b != 2'b_01) $stop; if (dout_lhs_rs_a != 2'b_01) $stop; if (dout_lhs_rs_b != 2'b_11) $stop; if (dout_rhs_ls_i_23_3 != 23'h_10_08_c0) $stop; if (dout_rhs_ls_i_23_4 != 23'h_08_10_18) $stop; if (dout_rhs_ls_q_37_3 != 37'h_04_02_30_10_44) $stop; if (dout_rhs_ls_q_37_4 != 37'h_02_04_06_08_0a) $stop; end if (cyc == 4) begin if (dout_rhs_ls_i_23_3 != 23'h_7f_ff_ff) $stop; if (dout_rhs_ls_i_23_4 != 23'h_7f_ff_ff) $stop; if (dout_rhs_ls_q_37_3 != 37'h_1f_ff_ff_ff_ff) $stop; if (dout_rhs_ls_q_37_4 != 37'h_1f_ff_ff_ff_ff) $stop; end if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_cover_toggle.v0000664000177100017500000000612113702133370021660 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { union packed { logic ua; logic ub; } u; logic b; } str_t; reg toggle; initial toggle='0; str_t stoggle; initial stoggle='0; const reg aconst = '0; reg [1:0][1:0] ptoggle; initial ptoggle=0; integer cyc; initial cyc=1; wire [7:0] cyc_copy = cyc[7:0]; wire toggle_up; alpha a1 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); alpha a2 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle_up (toggle_up)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); reg [1:0] memory[121:110]; reg [1023:0] largeish; // CHECK_COVER_MISSING(-1) always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; toggle <= '0; stoggle.u <= toggle; stoggle.b <= toggle; ptoggle[0][0] <= toggle; if (cyc==3) begin toggle <= '1; end if (cyc==4) begin toggle <= '0; end else if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module alpha (/*AUTOARG*/ // Outputs toggle_up, // Inputs clk, toggle, cyc_copy ); // t.a1 and t.a2 collapse to a count of 2 input clk; input toggle; // CHECK_COVER(-1,"top.t.a*",4) // 2 edges * (t.a1 and t.a2) input [7:0] cyc_copy; // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22) // CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10) // CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4) // CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2) // CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0) // CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0) // CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0) // CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0) reg toggle_internal; // CHECK_COVER(-1,"top.t.a*",4) // 2 edges * (t.a1 and t.a2) output reg toggle_up; // CHECK_COVER(-1,"top.t.a*",4) // 2 edges * (t.a1 and t.a2) always @ (posedge clk) begin toggle_internal <= toggle; toggle_up <= toggle; end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle_up ); input clk; input toggle_up; // CHECK_COVER(-1,"top.t.b1","toggle_up",2) /* verilator public_module */ always @ (posedge clk) begin if (0 && toggle_up) begin end end endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); // verilator coverage_off input clk; // CHECK_COVER_MISSING(-1) // verilator coverage_on input toggle; // CHECK_COVER(-1,"top.t.o1","toggle",2) endmodule verilator-4.038/test_regress/t/t_class_typedef.v0000664000177100017500000000104413702133367022033 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Parse check class uvm_resource_types; typedef int rsrc_q_t; endclass class uvm_resource_pool; uvm_resource_types::rsrc_q_t rtab [string]; uvm_resource_types#(1,2,3)::rsrc_q_t rtab_paramed [string]; endclass module t (/*AUTOARG*/); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_incabspath_bad.pl0000775000177100017500000000124213702133370023321 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_lint_incabspath.v"); lint( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc.v0000664000177100017500000004402613702133370020661 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //=========================================================================== // Includes `include "t_preproc_inc2.vh" //=========================================================================== // Comments /* verilator pass_thru comment */ // verilator pass_thru_comment2 //=========================================================================== // Defines `define DEF_A3 `define DEF_A1 // DEF_A0 set by command line wire [3:0] q = { `ifdef DEF_A3 1'b1 `else 1'b0 `endif , `ifdef DEF_A2 1'b1 `else 1'b0 `endif , `ifdef DEF_A1 1'b1 `else 1'b0 `endif , `ifdef DEF_A0 1'b1 `else 1'b0 `endif }; text. `define FOOBAR foo /*this */ bar /* this too */ `define FOOBAR2 foobar2 // but not `FOOBAR `FOOBAR2 `define MULTILINE first part \ second part \ third part `define MOREMULTILINE {\ a,\ b,\ c} /*******COMMENT*****/ `MULTILINE `MOREMULTILINE Line_Preproc_Check `__LINE__ //=========================================================================== `define syn_negedge_reset_l or negedge reset_l `define DEEP deep `define DEEPER `DEEP `DEEP `DEEPER `define nosubst NOT_SUBSTITUTED `define WITHTICK "`nosubst" "Inside: `nosubst" `WITHTICK `define withparam(a, b) a b LLZZ a b `withparam(x,y) `withparam(`withparam(p,q),`withparam ( r , s )) `withparam(firstline , comma","line) `define withquote(a, bar) a bar LLZZ "a" bar `withquote( x , y) // Simulators disagree here; some substitute "a" others do not `define noparam (a,b) `noparam(a,b) `define msg(x,y) `"x: `\`"y`\`"`" $display(`msg(left side, right side)) `define foo(f) f``_suffix `foo(bar) more `define zap(which) \ $c("Zap(\"",which,"\");"); `zap(bug1); `zap("bug2"); /* Define inside comment: `DEEPER and `WITHTICK */ // More commentary: `zap(bug1); `zap("bug2"); //====================================================================== // display passthru `define ls left_side `define rs right_side `define noarg na `define thru(x) x `define thruthru `ls `rs // Doesn't expand `define msg(x,y) `"x: `\`"y`\`"`" initial begin //$display(`msg( \`, \`)); // Illegal $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); $display(`msg(left side,right side)); $display(`msg( left side , right side )); $display(`msg( `ls , `rs )); $display(`msg( `noarg , `rs )); $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); $display(`msg(`noarg,`noarg`noarg)); $display(`msg( `thruthru , `thruthru )); // Results vary between simulators $display(`msg(`thru(),)); // Empty $display(`msg(`thru(left side),`thru(right side))); $display(`msg( `thru( left side ) , `thru( right side ) )); $display(`"standalone`"); // Unspecified when the stringification has multiple lines `define twoline first \ second $display(`msg(twoline, `twoline)); //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. $write("*-* All Finished *-*\n"); $finish; end endmodule //====================================================================== // rt.cpan.org bug34429 `define ADD_UP(a,c) \ wire tmp_``a = a; \ wire tmp_``c = tmp_``a + 1; \ assign c = tmp_``c ; module add1 ( input wire d1, output wire o1); `ADD_UP(d1,o1) // expansion is OK endmodule module add2 ( input wire d2, output wire o2); `ADD_UP( d2 , o2 ) // expansion is bad endmodule `define check(mod, width, flopname, gate, path) \ generate for (i=0; i<(width); i=i+1) begin \ psl cover { path.d[i] & ~path.q[i] & !path.cond & (gate)} report `"fondNoRise: mod.flopname`"; \ psl cover { ~path.d[i] & path.q[i] & !path.cond & (gate)} report `"fondNoFall: mod.flopname`"; \ end endgenerate // parameterized macro with arguments that are macros `define MK m5k.f `define MF `MK .ctl `define CK_fr (`MF.alive & `MF.alive_m1) `check(m5kc_fcl, 3, _ctl_mvldx_m1, `CK_fr, `MF._ctl_mvldx_m1) // ignorecmt //====================================================================== // Quotes are legal in protected blocks. Grr. module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `endprotected endmodule //" //====================================================================== // macro call with define that has comma `define REG_H 6 `define REG_L 7 `define _H regs[`REG_H] `define _L regs[`REG_L] `define _HL {`_H, `_L} `define EX_WRITE(ad, da) begin addr <= (ad); wdata <= (da); wr <= 1; end `define EX_READ(ad) begin addr <= (ad); rd <= 1; end `EX_READ((`_HL + 1)) and `EX_WRITE((`_HL), rdata) `EX_READ(`_HL + 1) `EX_WRITE(`_HL, rdata) more //====================================================================== // include of parameterized file `define INCNAME "t_preproc_inc4.vh" `include `INCNAME `ifndef T_PREPROC_INC4 `error "No Inc4" `endif `undef T_PREPROC_INC4 `ifdef NOT_DEFINED_INC `include NOT_DEFINED_INC `endif //====================================================================== // macro call with , in {} `define xxerror(logfile, msg) $blah(logfile,msg) `xxerror("ab,cd","e,f"); `xxerror(this.logfile, vec); `xxerror(this.logfile, vec[1,2,3]); `xxerror(this.logfile, {blah.name(), " is not foo"}); //====================================================================== // pragma/default net type `pragma foo = 1 `default_nettype none `default_nettype uwire //====================================================================== // Ifdef `define EMPTY_TRUE `ifndef EMPTY_TRUE `error "Empty is still true" `endif Line_Preproc_Check `__LINE__ //====================================================================== // bug84 `define ARGPAR(a, // Hello, comments MIGHT not be legal /*more,,)cmts*/ b // But newlines ARE legal... who speced THAT? ) (a,b) `ARGPAR(p,q) `ARGPAR( //Here x, y //Too ) Line_Preproc_Check `__LINE__ //====================================================================== // defines split arguments `define BEGIN begin `define END end `define BEGINEND `BEGIN`END `define quoteit(x) `"x`" `BEGIN`END // 2001 spec doesn't require two tokens, so "beginend" ok `BEGINEND // 2001 spec doesn't require two tokens, so "beginend" ok `quoteit(`BEGIN`END) // No space "beginend" //====================================================================== // bug106 `define \esc`def got_escaped `ifdef \esc`def `\esc`def `endif Not a \`define //====================================================================== // misparsed comma in submacro `define sb bee `define appease_emacs_paren_matcher ( `define sa(l) x,y) `define sfoo(q,r) q--r `sfoo(`sa(el),`sb) submacro has comma paren //====================================================================== // bug191 `define bug191(bits) $display("bits %d %d", $bits(foo), bits); `bug191(10) //====================================================================== // 1800-2009 `define UDALL `ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif `undefineall `ifdef UDALL `error "undefineall failed" `endif `ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif //====================================================================== // bug202 `define FC_INV3(out, in) \ `ifdef DC \ cell \inv_``out <$typeof(out)> (.a(), .o()); \ /* multi-line comment \ multi-line comment */ \ `else \ `ifdef MACRO_ATTRIBUTE \ (* macro_attribute = `"INV (out``,in``)`" *) \ `endif \ assign out = ~in ; \ `endif `FC_INV3(a3,b3) `define /* multi \ line1*/ \ bug202( i /*multi \ line2*/ \ ) \ /* multi \ line 3*/ \ def i \ `bug202(foo) //====================================================================== `define CMT1 // verilator NOT IN DEFINE `define CMT2 /* verilator PART OF DEFINE */ `define CMT3 /* verilator NOT PART OF DEFINE */ `define CMT4 /* verilator PART \ OF DEFINE */ `define CMT5 // CMT NOT \ also in // BUT TEXT IS \ also3 // CMT NOT 1 `CMT1 (nodef) 2 `CMT2 (hasdef) 3 `CMT3 (nodef) 4 `CMT4 (nodef) 5 `CMT5 (nodef) `define NL HAS a NEW \ LINE `NL //====================================================================== `define msg_fatal(log, msg) \ do \ /* synopsys translate_off */ \ `ifdef NEVER \ `error "WTF" \ `else \ if (start(`__FILE__, `__LINE__)) begin \ `endif \ message(msg); \ end \ /* synopsys translate_on */ \ while(0) `define msg_scen_(cl) cl``_scen `define MSG_MACRO_TO_STRING(x) `"x`" EXP: clxx_scen `msg_scen_(clxx) EXP: clxx_scen `MSG_MACRO_TO_STRING(`msg_scen_(clxx)) `define mf(clx) `msg_fatal(this.log, {"Blah-", `MSG_MACRO_TO_STRING(`msg_scen_(clx)), " end"}); EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `mf(clx) //====================================================================== `define makedefine(name) \ `define def_``name This is name \ `define def_``name``_2 This is name``_2 \ `makedefine(fooed) `ifndef def_fooed `error "No def_fooed" `endif //`ifndef def_fooed_2 `error "No def_fooed_2" `endif EXP: This is fooed `def_fooed EXP: This is fooed_2 `def_fooed_2 //====================================================================== `define NOPARAM() np `NOPARAM() `NOPARAM( ) //====================================================================== // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? `define NODS_DEFINED `define NODS_INDIRECT(x) x `ifndef `NODS_INDIRECT(NODS_DEFINED) `error "Indirect failed" `endif `ifdef `NODS_INDIRECT(NODS_UNDEFINED) `error "Indirect2 failed" `endif //====================================================================== // Metaprogramming `define REPEAT_0(d) `define REPEAT_1(d) d `define REPEAT_2(d) `REPEAT_1(d)d `define REPEAT_3(d) `REPEAT_2(d)d `define REPEAT_4(d) `REPEAT_3(d)d `define CONCAT(a, b) a``b `define REPEATC(n, d) `CONCAT(`REPEAT_, n)(d) `define REPEATT(n, d) `REPEAT_``n(d) `REPEATC(3, hello3 ) `REPEATT(4, hello4 ) //====================================================================== // Include from stringification `undef T_PREPROC_INC4 `define NODS_CONC_VH(m) `"m.vh`" `include `NODS_CONC_VH(t_preproc_inc4) `ifndef T_PREPROC_INC4 `error_here `endif //====================================================================== // Defines doing defines // Note the newline on the end - required to form the end of a define `define DEFINEIT(d) d \ `define _DEFIF_Z_0 1 `define DEFIF_NZ(d,n) `undef d `ifndef _DEFIF_Z_``n `DEFINEIT(`define d 1) `endif `DEFIF_NZ(TEMP,1) `ifndef TEMP `error "bad" `endif `DEFIF_NZ(TEMP,0) `ifdef TEMP `error "bad0" `endif Line_Preproc_Check `__LINE__ //====================================================================== // Quoted multiline - track line numbers, and ensure \\n gets propagated `define MULQUOTE "FOO \ BAR " `define MULQUOTE2(mq) `MULQUOTE mq `MULQUOTE Line_Preproc_Check `__LINE__ `MULQUOTE2("arg_line1 \ arg_line2") Line_Preproc_Check `__LINE__ //====================================================================== // bug283 `define A a `define B b `define C c // EXP: abc `define C5 `A``b```C `C5 `undef A `undef B `undef C `define XTYPE sonet `define XJOIN(__arg1, __arg2) __arg1``__arg2 `define XACTION `XJOIN(`XTYPE, _frame) EXP: sonet_frame `XACTION // `define XFRAME frame `define XACTION2 `XJOIN(sonet_, `XFRAME) EXP: sonet_frame `XACTION2 // This result varies between simulators `define sonet_frame other_frame `define XACTION3 `XTYPE``_frame EXP: sonet_frame `XACTION3 // The existance of non-existance of a base define can make a difference `define QA_b zzz `define Q1 `QA``_b EXP: module zzz ; endmodule module `Q1 ; endmodule module `Q1 ; endmodule `define QA a EXP: module a_b ; endmodule module `Q1 ; endmodule module `Q1 ; endmodule //====================================================================== // bug311 integer/*NEED_SPACE*/foo; //====================================================================== // bug441 module t; //----- // case provided // note this does NOT escape as suggested in the mail `define LEX_CAT(lexem1, lexem2) lexem1``lexem2 `define LEX_ESC(name) \name \ initial begin : `LEX_ESC( `LEX_CAT(a[0],_assignment) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end //----- // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from // substituting and the \ staying in the expansion // Note space after name is important so when substitute it has ending whitespace `define ESC_CAT(name,name2) \name``_assignment_``name2 \ initial begin : `ESC_CAT( a[0],a[1] ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end `undef ESC_CAT //----- `define CAT(a,b) a``b `define ESC(name) \`CAT(name,suffix) // RULE: Ignoring backslash does NOT allow an additional expansion level // (Because ESC gets expanded then the \ has it's normal escape meaning) initial begin : `ESC(pp) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end `undef CAT `undef ESC //----- `define CAT(a,b) a``b `define ESC(name) \name \ // Similar to above; \ does not allow expansion after substitution initial begin : `ESC( `CAT(ff,bb) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end `undef CAT `undef ESC //----- `define ESC(name) \name \ // MUST: Unknown macro with backslash escape stays as escaped symbol name initial begin : `ESC( `zzz ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end `undef ESC //----- `define FOO bar `define ESC(name) \name \ // SHOULD(simulator-dependant): Known macro with backslash escape expands initial begin : `ESC( `FOO ) $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end // SHOULD(simulator-dependant): Prefix breaks the above initial begin : `ESC( xx`FOO ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end `undef FOO `undef ESC //----- // MUST: Unknown macro not under call with backslash escape doesn't expand `undef UNKNOWN initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end //----- // MUST: Unknown macro not under call doesn't expand `define DEF_NO_EXPAND error_dont_expand initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end `undef DEF_NO_EXPAND //----- // bug441 derivative // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) `define STR(name) "foo name baz" initial $write("GOT='%s' EXP='%s'\n", `STR(bar), "foo bar baz"); `undef STR //----- // RULE: Because there are quotes after substituting STR, the `A does NOT expand `define STR(name) "foo name baz" `define A(name) boo name hiss initial $write("GOT='%s' EXP='%s'\n", `STR(`A(bar)), "foo `A(bar) baz"); `undef A `undef STR //---- // bug845 `define SLASHED "1//2.3" initial $write("Slashed=`%s'\n", `SLASHED); //---- // bug915 `define BUG915(a,b,c) \ $display("%s%s",a,`"b``c``\n`") initial `BUG915("a1",b2,c3); endmodule //====================================================================== //bug1225 `define X_ITEM(SUB,UNIT) `X_STRING(SUB``UNIT) `define X_STRING(A) `"A`" $display(`X_ITEM(RAM,0)); $display(`X_ITEM(CPU,)); `define EMPTY `define EMPTYP(foo) `define SOME some `define SOMEP(foo) foo `define XXE_FAMILY XXE_```EMPTY XXE_FAMILY = `XXE_FAMILY `define XXE_```EMPTY `ifdef XXE_ $display("XXE_ is defined"); `endif `define XYE_FAMILY XYE_```EMPTYP(foo) XYE_FAMILY = `XYE_FAMILY `define XYE_```EMPTYP(foo) `ifdef XYE_ $display("XYE_ is defined"); `endif `define XXS_FAMILY XXS_```SOME XXS_FAMILY = `XXS_FAMILY `define XXS_```SOME `ifdef XXS_some $display("XXS_some is defined"); `endif `define XYS_FAMILY XYS_```SOMEP(foo) XYS_FAMILY = `XYS_FAMILY `define XYS_```SOMEP(foo) `ifdef XYS_foo $display("XYS_foo is defined"); `endif //==== `ifdef NEVER `define NXE_FAMILY NXE_```EMPTY NXE_FAMILY = `NXE_FAMILY `define NXE_```EMPTY `ifdef NXE_ $display("NXE_ is defined"); `endif `define NYE_FAMILY NYE_```EMPTYP(foo) NYE_FAMILY = `NYE_FAMILY `define NYE_```EMPTYP(foo) `ifdef NYE_ $display("NYE_ is defined"); `endif `define NXS_FAMILY NXS_```SOME NXS_FAMILY = `NXS_FAMILY `define NXS_```SOME `ifdef NXS_some $display("NXS_some is defined"); `endif `define NYS_FAMILY NYS_```SOMEP(foo) NYS_FAMILY = `NYS_FAMILY `define NYS_```SOMEP(foo) `ifdef NYS_foo $display("NYS_foo is defined"); `endif `include `EMPTY `endif // NEVER //bug1227 `define INSTANCE(NAME) (.mySig (myInterface.``NAME), `INSTANCE(pa5) //====================================================================== // Stringify bug `define hack(GRP) `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); `hack(paramgrp) `define dbg_hdl(LVL, MSG) $display ("DEBUG : %s [%m]", $sformatf MSG) `define svfcov_new(GRP) \ initial do begin `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); end while(0) `define simple_svfcov_clk(LBL, CLK, RST, ARG) \ covergroup LBL @(posedge CLK); \ c: coverpoint ARG iff ((RST) === 1'b1); endgroup \ LBL u_``LBL; `svfcov_new(u_``LBL) module pcc2_cfg; generate `simple_svfcov_clk(a, b, c, d); endgenerate endmodule //====================================================================== // IEEE mandated predefines `undefineall // undefineall should have no effect on these predef `SV_COV_START 0 predef `SV_COV_STOP 1 predef `SV_COV_RESET 2 predef `SV_COV_CHECK 3 predef `SV_COV_MODULE 10 predef `SV_COV_HIER 11 predef `SV_COV_ASSERTION 20 predef `SV_COV_FSM_STATE 21 predef `SV_COV_STATEMENT 22 predef `SV_COV_TOGGLE 23 predef `SV_COV_OVERFLOW -2 predef `SV_COV_ERROR -1 predef `SV_COV_NOCOV 0 predef `SV_COV_OK 1 predef `SV_COV_PARTIAL 2 //====================================================================== // After `undefineall above, for testing --dump-defines `define WITH_ARG(a) (a)(a) verilator-4.038/test_regress/t/t_preproc_persist.v0000664000177100017500000000041413702133370022423 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 Inside `__FILE__. `include "t_preproc_persist_inc.v" verilator-4.038/test_regress/t/t_typename.pl0000775000177100017500000000105313702133370021173 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_inc_notfound_bad.v0000664000177100017500000000037313702133370024231 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "this_file_is_not_found.vh" verilator-4.038/test_regress/t/t_math_pow2.pl0000775000177100017500000000105313702133370021251 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_slice_part_select.v0000664000177100017500000000364013702133370023725 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by engr248. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] in = 0; wire [31:0] out; Test test( .out(out[31:0]), .clk(clk), .in (in[31:0]) ); always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule interface Intf (); endinterface module Select #( parameter int NUM_MASTER = 1 ) ( Intf Upstream, Intf Downstream[NUM_MASTER] ); endmodule module Crossbar #( parameter int NUM_MASTER = 1, parameter int NUM_SLAVE = 1 ) ( Intf Masters[NUM_MASTER] ); Intf selectOut[(NUM_MASTER * (NUM_SLAVE))-1 : 0](); genvar i; for (i = 0; i < NUM_MASTER; i = i + 1) begin Select #( .NUM_MASTER(NUM_SLAVE) ) select_inst ( .Upstream(Masters[i]), // Following line seems to trigger a bad calculation for dimension where port // is calculated as width 1 (correctly) and expression is calculated as NUM_MASTER*NUM_SLAVE rather than NUM_SLAVE .Downstream(selectOut[(i)*(NUM_SLAVE) +: (NUM_SLAVE)]) // The following line works as intended and should be functionally identical to the above line // .Downstream(selectOut[(i+1)*(NUM_SLAVE)-1 : i*(NUM_SLAVE)]) ); end endmodule module Test ( input clk, input [31:0] in, output reg [31:0] out ); always @(posedge clk) begin out <= in; end Intf MST[10](); Crossbar #( .NUM_MASTER(10), .NUM_SLAVE(1) ) xbar_inst ( .Masters(MST) ); endmodule verilator-4.038/test_regress/t/t_inst_port_array.v0000664000177100017500000000212313702133370022416 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Alex Solomatnikov. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [6-1:0] foo[4-1:0]; //initial $display("%m: %p\n", foo); //initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice //logic [6-1:0] foo2[4-1:0][5:6]; //initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal dut #(.W(6), .D(4)) udut(.clk(clk), .foo(foo[4-1:0])); endmodule module dut #(parameter W = 1, parameter D = 1) (input logic clk, input logic [W-1:0] foo[D-1:0]); genvar i, j; generate for (j = 0; j < D; j++) begin for (i = 0; i < W; i++) begin suba ua(.clk(clk), .foo(foo[j][i])); end end endgenerate endmodule module suba (input logic clk, input logic foo); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_overwidth_bad.out0000664000177100017500000000016313702133370023234 0ustar wsnyderwsnyder%Error: unknown:0: Testbench C set input 'clk' to value that overflows what the signal's width can fit Aborting... verilator-4.038/test_regress/t/t_dynarray.v0000664000177100017500000000671413702133370021042 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; integer i; string v; // verilator lint_off UNUSED integer unused[]; // verilator lint_on UNUSED typedef bit [7:0] byte_t; byte_t a[]; byte_t b[]; // wide data array typedef struct packed { logic [15:0] header; logic [223:0] payload; logic [15:0] checksum; } pck256_t; pck256_t p256[]; always @ (posedge clk) begin cyc <= cyc + 1; begin `checkh(a.size, 0); v = $sformatf("%p", a); `checks(v, "'{} "); a = new [3]; `checkh(a.size, 3); a[0] = 10; a[1] = 11; a[2] = 12; `checkh(a[0], 10); `checkh(a[1], 11); `checkh(a[2], 12); v = $sformatf("%p", a); `checks(v, "'{'ha, 'hb, 'hc} "); a.delete; `checkh(a.size, 0); a = new [2]; `ifdef verilator // Unsupported pattern assignment a[0] = 15; a[1] = 16; `else a = '{15, 16}; `endif `checkh(a.size, 2); `checkh(a[0], 15); `checkh(a[1], 16) `ifdef verilator // Unsupported pattern assignment a = new [1]; a[0] = 17; `else a = '{17}; `endif `checkh(a.size, 1); // IEEE says resizes to smallest that fits pattern `checkh(a[0], 17); a = new[2]; a[0] = 5; a[1] = 6; `checkh(a[0], 5); `checkh(a[1], 6); a = new[2]; `checkh(a[0], 0); `checkh(a[1], 0); a[0] = 5; a[1] = 6; `checkh(a[0], 5); `checkh(a[1], 6); b = new [4](a); `checkh(b.size, 4); `checkh(b[0], 5); `checkh(b[1], 6); `checkh(b[2], 0); `checkh(b[3], 0); a = b; `checkh(a.size, 4); `checkh(a[0], 5); `checkh(a[1], 6); `checkh(a[2], 0); `checkh(a[3], 0); a = new [0]; `checkh(a.size, 0); b = new [4](a); `checkh(b.size, 4); `checkh(b[0], 0); `checkh(b[1], 0); `checkh(b[2], 0); `checkh(b[4], 0); // test wide dynamic array p256 = new [11]; `checkh(p256.size, 11); `checkh(p256.size(), 11); p256[1].header = 16'hcafe; p256[1].payload = {14{16'hbabe}}; p256[1].checksum = 16'hdead; `checkh(p256[1].header, 16'hcafe); `checkh(p256[1], {16'hcafe,{14{16'hbabe}},16'hdead}); `checkh(p256[0], '0); p256[5] = '1; `checkh(p256[5], {32{8'hff}}); p256[5].header = 16'h2; `checkh(p256[5], {16'h2,{30{8'hff}}}); p256[2] = ( p256[5].header == 2 ) ? p256[1] : p256[5]; `checkh(p256[2], {16'hcafe,{14{16'hbabe}},16'hdead}); p256.delete(); `checkh(p256.size, 0); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_return_bad.out0000664000177100017500000000142413702133370022704 0ustar wsnyderwsnyder%Error: t/t_func_return_bad.v:10:7: Return underneath a task shouldn't have return value 10 | return 1; | ^~~~~~ %Error: t/t_func_return_bad.v:13:7: Return underneath a function should have return value 13 | return; | ^~~~~~ %Error: t/t_func_return_bad.v:17:7: Return isn't underneath a task or function 17 | return; | ^~~~~~ %Error: t/t_func_return_bad.v:18:7: continue isn't underneath a loop 18 | continue; | ^~~~~~~~ %Error: t/t_func_return_bad.v:19:7: break isn't underneath a loop 19 | break; | ^~~~~ %Error: t/t_func_return_bad.v:22:7: disable isn't underneath a begin with name: 'foo' 22 | disable foo; | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_generate_fatal_bad.pl0000775000177100017500000000107313702133370023122 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_repl.pl0000775000177100017500000000105313702133370021473 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_process_parse.pl0000775000177100017500000000110613702133370022220 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t_process.v"); lint( verilator_flags2 => ["--debug-exit-parse"], ); ok(1); 1; verilator-4.038/test_regress/t/t_interface2.pl0000775000177100017500000000113413702133370021373 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--top-module t"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_primitive.pl0000775000177100017500000000123713702133370022543 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["--trace"], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/simx.vcd", "sub_t_i"); }; ok(1); 1; verilator-4.038/test_regress/t/t_preproc_defines.out0000664000177100017500000000124713650310376022723 0ustar wsnyderwsnyder`define DEF_A0 `define PREDEF_COMMAND_LINE `define SV_COV_ASSERTION 20 `define SV_COV_CHECK 3 `define SV_COV_ERROR -1 `define SV_COV_FSM_STATE 21 `define SV_COV_HIER 11 `define SV_COV_MODULE 10 `define SV_COV_NOCOV 0 `define SV_COV_OK 1 `define SV_COV_OVERFLOW -2 `define SV_COV_PARTIAL 2 `define SV_COV_RESET 2 `define SV_COV_START 0 `define SV_COV_STATEMENT 22 `define SV_COV_STOP 1 `define SV_COV_TOGGLE 23 `define SYSTEMVERILOG 1 `define TEST_OBJ_DIR obj_vlt/t_preproc_defines `define VERILATOR 1 `define WITH_ARG(a) (a)(a) `define coverage_block_off /*verilator coverage_block_off*/ `define systemc_clock /*verilator systemc_clock*/ `define verilator 1 `define verilator3 1 verilator-4.038/test_regress/t/t_clk_gater.v0000664000177100017500000000644313702133367021151 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; reg reset; reg enable; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .reset (reset), .enable (enable), .in (in[31:0])); wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; reset <= (cyc < 5); enable <= cyc[4] || (cyc < 2); if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h01e1553da1dcf3af if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, reset, enable, in ); input clk; input reset; input enable; input [31:0] in; output [31:0] out; // No gating reg [31:0] d10; always @(posedge clk) begin d10 <= in; end reg displayit; `ifdef VERILATOR // Harder test initial displayit = $c1("0"); // Something that won't optimize away `else initial displayit = '0; `endif // Obvious gating + PLI reg [31:0] d20; always @(posedge clk) begin if (enable) begin d20 <= d10; // Obvious gating if (displayit) begin $display("hello!"); // Must glob with other PLI statements end end end // Reset means second-level gating reg [31:0] d30, d31a, d31b, d32; always @(posedge clk) begin d32 <= d31b; if (reset) begin d30 <= 32'h0; d31a <= 32'h0; d31b <= 32'h0; d32 <= 32'h0; // Overlaps above, just to make things interesting end else begin // Mix two outputs d30 <= d20; if (enable) begin d31a <= d30; d31b <= d31a; end end end // Multiple ORs for gater reg [31:0] d40a,d40b; always @(posedge clk) begin if (reset) begin d40a <= 32'h0; d40b <= 32'h0; end if (enable) begin d40a <= d32; d40b <= d40a; end end // Non-optimizable reg [31:0] d91, d92; reg [31:0] inverted; always @(posedge clk) begin inverted = ~d40b; if (reset) begin d91 <= 32'h0; end else begin if (enable) begin d91 <= inverted; end else begin d92 <= inverted ^ 32'h12341234; // Inverted gating condition end end end wire [31:0] out = d91 ^ d92; endmodule verilator-4.038/test_regress/t/t_lint_blksync_bad.v0000664000177100017500000000160113702133370022500 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer i; reg sync_blk; reg sync_blk2; reg sync_nblk; reg sync2_ok; reg sync3_ok; reg combo_blk; reg combo_nblk; always @(posedge clk) begin sync_blk = 1'b1; sync_blk2 = 1'b1; // Only warn once per block sync_nblk <= 1'b1; end always @* begin combo_blk = 1'b1; combo_nblk <= 1'b1; end always @(posedge clk) begin for (int i=0; i<20; i++) begin sync2_ok <= 1'b1; end end always @(posedge clk) begin sync3_ok <= f(sync3_ok); end function f (input v); f = ~v; endfunction endmodule verilator-4.038/test_regress/t/t_mod_interface_array2.v0000664000177100017500000000257413702133370023270 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 parameter N = 4; // verilator lint_off LITENDIAN interface a_if #(parameter PARAM = 0) (); logic long_name; modport source (output long_name); modport sink (input long_name); endinterface module intf_source ( input logic [0:N-1] intf_input, a_if.source i_intf_source[0:N-1] ); generate for (genvar i=0; i < N;i++) begin assign i_intf_source[i].long_name = intf_input[i]; end endgenerate endmodule module intf_sink ( output [0:N-1] a_out, a_if.sink i_intf_sink[0:N-1] ); generate for (genvar i=0; i < N;i++) begin assign a_out[i] = i_intf_sink[i].long_name; end endgenerate endmodule module t ( clk ); input clk; logic [0:N-1] a_in; logic [0:N-1] a_out; logic [0:N-1] ack_out; a_if #(.PARAM(1)) tl_intf [0:N-1] (); intf_source source(a_in, tl_intf); intf_sink sink(a_out, tl_intf); initial a_in = '0; always @(posedge clk) begin a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; if (ack_out != a_out) begin $stop; end if (& a_in) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_struct_init.pl0000775000177100017500000000105313702133370021720 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_past.v0000664000177100017500000000475313702133370020161 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; Test test (/*AUTOINST*/ // Inputs .clk (clk), .in (in[31:0])); Test2 test2 (/*AUTOINST*/ // Inputs .clk (clk), .in (in[31:0])); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Inputs clk, in ); input clk; input [31:0] in; reg [31:0] dly0; reg [31:0] dly1; reg [31:0] dly2; reg [31:0] dly3; // If called in an assertion, sequence, or property, the appropriate clocking event. // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. // Otherwise, if called in a procedure, the inferred clock // Otherwise, default clocking always @(posedge clk) begin dly0 <= in; dly1 <= dly0; dly2 <= dly1; dly3 <= dly2; // $past(expression, ticks, expression, clocking) // In clock expression if (dly0 != $past(in)) $stop; if (dly0 != $past(in,1)) $stop; if (dly1 != $past(in,2)) $stop; // $sampled(expression) -> expression if (in != $sampled(in)) $stop; end assert property (@(posedge clk) dly0 == $past(in)); endmodule module Test2 (/*AUTOARG*/ // Inputs clk, in ); input clk; input [31:0] in; reg [31:0] dly0; reg [31:0] dly1; always @(posedge clk) begin dly0 <= in; dly1 <= dly0; end default clocking @(posedge clk); endclocking assert property (@(posedge clk) $time < 40 || dly1 == $past(in, 2)); endmodule verilator-4.038/test_regress/t/t_flag_define.pl0000775000177100017500000000120313702133370021571 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( v_flags2 => ["-f t/t_flag_define.vc -DCMD_DEF -DCMD_UNDEF -UCMD_UNDEF +define+CMD_DEF2"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_future.v0000664000177100017500000000063213702133370021505 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // verilator lint_off FUTURE1 $write("*-* All Finished *-*\n"); $finish; // verilator FUTURE2 // verilator FUTURE2 blah blah end endmodule verilator-4.038/test_regress/t/t_unopt_combo.vlt0000664000177100017500000000021713702133370022065 0ustar wsnyderwsnyder`verilator_config lint_off -rule UNOPTFLAT -file "*t_unopt_combo.v" -match "Signal unoptimizable: Feedback to clock or circular logic: 't.c'" verilator-4.038/test_regress/t/t_func_twocall.v0000664000177100017500000000304013702133370021656 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [7:0] crc; wire [61:59] ah = crc[5:3]; wire [61:59] bh = ~crc[4:2]; wire [41:2] al = {crc,crc,crc,crc,crc}; wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]}; reg sel; wire [61:28] q = ( sel ? func(ah, al) : func(bh, bl)); function [61:28] func; input [61:59] inh; input [41:2] inl; reg [42:28] func_mid; reg carry; begin carry = &inl[27:2]; func_mid = {1'b0,inl[41:28]} + {14'b0, carry}; func[61:59] = inh + {2'b0, func_mid[42]}; func[58:42] = {17{func_mid[41]}}; func[41:28] = func_mid[41:28]; end endfunction integer cyc; initial cyc=1; always @ (posedge clk) begin //$write("%d %x\n", cyc, q); if (cyc!=0) begin cyc <= cyc + 1; sel <= ~sel; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==1) begin sel <= 1'b1; crc <= 8'h12; end if (cyc==2) if (q!=34'h100000484) $stop; if (cyc==3) if (q!=34'h37fffeddb) $stop; if (cyc==4) if (q!=34'h080001212) $stop; if (cyc==5) if (q!=34'h1fffff7ef) $stop; if (cyc==6) if (q!=34'h200000848) $stop; if (cyc==7) if (q!=34'h380001ebd) $stop; if (cyc==8) if (q!=34'h07fffe161) $stop; if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_gen_defparam_unsup_bad.out0000664000177100017500000000052113702133370024211 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_gen_defparam_unsup_bad.v:9:16: Unsupported: defparam with more than one dot 9 | defparam a.b.W = 3; | ^ %Error: t/t_gen_defparam_unsup_bad.v:9:17: syntax error, unexpected IDENTIFIER, expecting ',' or ';' 9 | defparam a.b.W = 3; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_select_bad_range2.out0000664000177100017500000000056313702133370023072 0ustar wsnyderwsnyder%Warning-SELRANGE: t/t_select_bad_range2.v:51:21: Selection index out of range: 3:2 outside 1:0 : ... In instance t.test 51 | assign out32 = in[3:2]; | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_dpi_vams.v0000664000177100017500000000105513702133370021004 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //`begin_keywords "VAMS-2.3" `begin_keywords "1800+VAMS" module t (/*AUTOARG*/ // Outputs out, // Inputs in ); input in; wreal in; output out; wreal out; import "DPI-C" context function void dpii_call(input real in, output real out); initial begin dpii_call(in,out); $finish; end endmodule verilator-4.038/test_regress/t/t_vpi_finish.pl0000775000177100017500000000113413702133370021507 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["--vpi t/t_vpi_finish_c.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_format_wide_decimal.pl0000775000177100017500000000117313702133370023332 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-Wall"] ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_litendian.out0000664000177100017500000002704113702133370022674 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sun May 3 21:38:46 2020 $end $timescale 1ps $end $scope module top $end $var wire 1 } clk $end $scope module t $end $var wire 8 ~ P [0:7] $end $var wire 8 !! Q [0:7] $end $var wire 1 } clk $end $var wire 32 # cyc [31:0] $end $var wire 1 $ v_a [0:0] $end $var wire 2 % v_b [0:1] $end $var wire 8 & v_c [0:7] $end $var wire 9 ' v_d [0:8] $end $var wire 16 ( v_e [0:15] $end $var wire 17 ) v_f [0:16] $end $var wire 32 * v_g [0:31] $end $var wire 33 + v_h [0:32] $end $var wire 64 - v_i [0:63] $end $var wire 65 / v_j [0:64] $end $var wire 128 2 v_k [0:127] $end $var wire 129 6 v_l [0:128] $end $var wire 256 ; v_m [0:255] $end $var wire 257 C v_n [0:256] $end $var wire 512 L v_o [0:511] $end $var wire 3 \ v_p [-1:1] $end $var wire 15 ] v_q [-7:7] $end $var wire 31 ^ v_r [-15:15] $end $var wire 63 _ v_s [-31:31] $end $var wire 127 a v_t [-63:63] $end $var wire 255 e v_u [-127:127] $end $var wire 511 m v_v [-255:255] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # 0$ b00 % b00000000 & b000000000 ' b0000000000000000 ( b00000000000000000 ) b00000000000000000000000000000000 * b000000000000000000000000000000000 + b0000000000000000000000000000000000000000000000000000000000000000 - b00000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2 b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 6 b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L b000 \ b000000000000000 ] b0000000000000000000000000000000 ^ b000000000000000000000000000000000000000000000000000000000000000 _ b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m 0} b00001010 ~ b00010100 !! #10 b00000000000000000000000000000001 # 1$ b11 % b11111111 & b111111111 ' b1111111111111111 ( b11111111111111111 ) b11111111111111111111111111111111 * b111111111111111111111111111111111 + b1111111111111111111111111111111111111111111111111111111111111111 - b11111111111111111111111111111111111111111111111111111111111111111 / b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 2 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 6 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 ; b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 C b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 L b111 \ b111111111111111 ] b1111111111111111111111111111111 ^ b111111111111111111111111111111111111111111111111111111111111111 _ b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 a b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 e b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 m 1} #15 0} #20 b00000000000000000000000000000010 # 0$ b10 % b11111110 & b111111110 ' b1111111111111110 ( b11111111111111110 ) b11111111111111111111111111111110 * b111111111111111111111111111111110 + b1111111111111111111111111111111111111111111111111111111111111110 - b11111111111111111111111111111111111111111111111111111111111111110 / b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 2 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 6 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 ; b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 C b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 L b110 \ b111111111111110 ] b1111111111111111111111111111110 ^ b111111111111111111111111111111111111111111111111111111111111110 _ b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 a b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 e b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 m 1} #25 0} #30 b00000000000000000000000000000011 # b00 % b11111100 & b111111100 ' b1111111111111100 ( b11111111111111100 ) b11111111111111111111111111111100 * b111111111111111111111111111111100 + b1111111111111111111111111111111111111111111111111111111111111100 - b11111111111111111111111111111111111111111111111111111111111111100 / b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 2 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 6 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 ; b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 C b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 L b100 \ b111111111111100 ] b1111111111111111111111111111100 ^ b111111111111111111111111111111111111111111111111111111111111100 _ b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 a b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 e b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 m 1} verilator-4.038/test_regress/t/t_func_wide.v0000664000177100017500000000161713702133370021151 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [43:0] mi; wire [31:0] mo; muxtop um ( mi, mo); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin mi <= 44'h1234567890; end if (cyc==3) begin if (mo !== 32'h12345678) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module muxtop ( input [ 43:0 ] i, output reg [ 31:0 ] o ); always @ ( i[43:0] ) // Verify we ignore ranges on always statement sense lists o = MUX( i[39:0] ); function [31:0] MUX; input [39:0] XX ; begin MUX = XX[39:8]; end endfunction endmodule verilator-4.038/test_regress/t/t_gen_for_shuffle.v0000664000177100017500000000353513702133370022342 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3e3a62edb61f8c7f if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [31:0] in; output [31:0] out; genvar i; generate for (i=0; i<16; i=i+1) begin : gblk assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)]; end endgenerate endmodule verilator-4.038/test_regress/t/t_gen_div0.pl0000775000177100017500000000105313702133370021044 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_real_abs.pl0000775000177100017500000000105313702133370022134 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_sign_extend.v0000664000177100017500000001107013702133370022520 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This test demonstrates an issue with sign extension. // Assigning to localparms larger than 32 bits broke in 3.862 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Mike Thyer. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam [ 0:0] one1_lp = 1; localparam [ 1:0] one2_lp = 1; localparam [ 2:0] one3_lp = 1; localparam [ 3:0] one4_lp = 1; localparam [ 4:0] one5_lp = 1; localparam [ 5:0] one6_lp = 1; localparam [ 6:0] one7_lp = 1; localparam [ 7:0] one8_lp = 1; localparam [ 8:0] one9_lp = 1; localparam [ 9:0] one10_lp = 1; localparam [19:0] one20_lp = 1; localparam [29:0] one30_lp = 1; localparam [30:0] one31_lp = 1; localparam [31:0] one32_lp = 1; localparam [32:0] one33_lp = 1; localparam [33:0] one34_lp = 1; localparam [34:0] one35_lp = 1; localparam [35:0] one36_lp = 1; localparam [36:0] one37_lp = 1; localparam [37:0] one38_lp = 1; localparam [38:0] one39_lp = 1; localparam [39:0] one40_lp = 1; localparam [49:0] one50_lp = 1; localparam [59:0] one60_lp = 1; localparam [60:0] one61_lp = 1; localparam [61:0] one62_lp = 1; localparam [62:0] one63_lp = 1; localparam [63:0] one64_lp = 1; localparam [64:0] one65_lp = 1; localparam [65:0] one66_lp = 1; localparam [66:0] one67_lp = 1; localparam [67:0] one68_lp = 1; localparam [68:0] one69_lp = 1; localparam [69:0] one70_lp = 1; bit all_ok = 1; initial begin `ifdef TEST_VERBOSE $display("one1_lp : %x %d", one1_lp, one1_lp==1); $display("one2_lp : %x %d", one2_lp, one2_lp==1); $display("one3_lp : %x %d", one3_lp, one3_lp==1); $display("one4_lp : %x %d", one4_lp, one4_lp==1); $display("one5_lp : %x %d", one5_lp, one5_lp==1); $display("one6_lp : %x %d", one6_lp, one6_lp==1); $display("one7_lp : %x %d", one7_lp, one7_lp==1); $display("one8_lp : %x %d", one8_lp, one8_lp==1); $display("one9_lp : %x %d", one9_lp, one9_lp==1); $display("one10_lp: %x %d", one10_lp, one10_lp==1); $display("one20_lp: %x %d", one20_lp, one20_lp==1); $display("one30_lp: %x %d", one30_lp, one30_lp==1); $display("one31_lp: %x %d", one31_lp, one31_lp==1); $display("one32_lp: %x %d", one32_lp, one32_lp==1); $display("one33_lp: %x %d", one33_lp, one33_lp==1); $display("one34_lp: %x %d", one34_lp, one34_lp==1); $display("one35_lp: %x %d", one35_lp, one35_lp==1); $display("one36_lp: %x %d", one36_lp, one36_lp==1); $display("one37_lp: %x %d", one37_lp, one37_lp==1); $display("one38_lp: %x %d", one38_lp, one38_lp==1); $display("one39_lp: %x %d", one39_lp, one39_lp==1); $display("one40_lp: %x %d", one40_lp, one40_lp==1); $display("one50_lp: %x %d", one50_lp, one50_lp==1); $display("one60_lp: %x %d", one60_lp, one60_lp==1); $display("one61_lp: %x %d", one61_lp, one61_lp==1); $display("one62_lp: %x %d", one62_lp, one62_lp==1); $display("one63_lp: %x %d", one63_lp, one63_lp==1); $display("one64_lp: %x %d", one64_lp, one64_lp==1); $display("one65_lp: %x %d", one65_lp, one65_lp==1); $display("one66_lp: %x %d", one66_lp, one66_lp==1); $display("one67_lp: %x %d", one67_lp, one67_lp==1); $display("one68_lp: %x %d", one68_lp, one68_lp==1); $display("one69_lp: %x %d", one69_lp, one69_lp==1); $display("one70_lp: %x %d", one70_lp, one70_lp==1); `endif all_ok &= one1_lp == 1; all_ok &= one2_lp == 1; all_ok &= one3_lp == 1; all_ok &= one4_lp == 1; all_ok &= one5_lp == 1; all_ok &= one6_lp == 1; all_ok &= one7_lp == 1; all_ok &= one8_lp == 1; all_ok &= one9_lp == 1; all_ok &= one10_lp == 1; all_ok &= one20_lp == 1; all_ok &= one30_lp == 1; all_ok &= one31_lp == 1; all_ok &= one32_lp == 1; all_ok &= one33_lp == 1; all_ok &= one34_lp == 1; all_ok &= one35_lp == 1; all_ok &= one36_lp == 1; all_ok &= one37_lp == 1; all_ok &= one38_lp == 1; all_ok &= one39_lp == 1; all_ok &= one40_lp == 1; all_ok &= one50_lp == 1; all_ok &= one60_lp == 1; all_ok &= one61_lp == 1; all_ok &= one62_lp == 1; all_ok &= one63_lp == 1; all_ok &= one64_lp == 1; all_ok &= one65_lp == 1; all_ok &= one66_lp == 1; all_ok &= one67_lp == 1; all_ok &= one68_lp == 1; all_ok &= one69_lp == 1; all_ok &= one70_lp == 1; if (!all_ok) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_gate_fdup.pl0000775000177100017500000000100113702133370021300 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_lib_library.v0000664000177100017500000000054013702133370022171 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module library_cell(a); input [`WIDTH-1:0] a; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_pipe_filter.pf0000664000177100017500000000370413702133370021647 0ustar wsnyderwsnyder#!/usr/bin/env perl use warnings; # DESCRIPTION: Verilator: Verilog Test example --pipe-filter script # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use strict; our $Debug = 0; autoflush STDOUT; print STDERR "t_pipe_filter.pf: Hello in Perl\n" if $Debug; while (defined(my $cmd = )) { print STDERR "t_pipe_filter.pf: gotcmd: $cmd" if $Debug; if ($cmd =~ /^read "(.*)"/) { my $filename = $1; open(my $fh, "<$filename") or die "t_pipe_filter.pf: %Error: $! $filename\n"; my $wholefile=""; # It's faster to slurp the whole file then scan (if needed), # then to read it into an array with getlines { local $/; undef $/; $wholefile = <$fh>; } close $fh; if ($wholefile =~ /example_lint/) { # else short circuit my $lineno = 1; my $pos=0; my @prefixes; while (1) { my $newpos=index($wholefile,"\n",$pos); last if $newpos<$pos; my $line = substr($wholefile,$pos,$newpos-$pos); if ($line =~ /example_lint/) { # We don't have a way to specify this yet, so just for now #print STDERR $line; push @prefixes, "int lint_off_line_${lineno} = 1;\n"; } $lineno++; $pos = $newpos+1; } #print STDERR "Line count: $lineno\n"; $wholefile = join('',@prefixes) . $wholefile; } print STDOUT "Content-Length: ".length($wholefile)."\n".$wholefile."\n"; } else { die "t_pipe_filter.pf: %Error: Unknown command: $cmd\n"; } } print STDOUT "t_pipe_filter.pf: Fin\n" if $Debug; exit(0); verilator-4.038/test_regress/t/t_flag_main_sc_bad.out0000664000177100017500000000015713702133370022756 0ustar wsnyderwsnyder%Error-UNSUPPORTED: --main not usable with SystemC. Suggest see examples for sc_main(). %Error: Exiting due to verilator-4.038/test_regress/t/t_math_const.v0000664000177100017500000001131313702133370021337 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [39:0] con1,con2, con3; reg [31:0] w32; reg [31:0] v32 [2]; // surefire lint_off UDDSCN reg [200:0] conw3, conw4; // surefire lint_on UDDSCN reg [16*8-1:0] con__ascii; reg [31:0] win; // Test casting is proper on narrow->wide->narrow conversions // verilator lint_off WIDTH wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111; wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111; // verilator lint_on WIDTH wire [31:0] narrow = wider[31:0]; wire [31:0] narrow2 = wider2[31:0]; // surefire lint_off ASWEMB // surefire lint_off ASWCMB // surefire lint_off CWECBB // surefire lint_off CWECSB // surefire lint_off STMINI integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin $write("[%0t] t_const: Running\n",$time); con1 = 4_0'h1000_0010; // Odd but legal _ in width con2 = 40'h10_0000_0010; con3 = con1 + 40'h10_1100_0101; if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop; $display("%x %x %x\n", con2, con2[31:0], con2[39:32]); if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop; if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop; // verilator lint_off WIDTH con1 = 10'h10 + 40'h80_1100_0131; // verilator lint_on WIDTH con2 = 40'h80_0000_0000 + 40'h13_7543_0107; if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop; if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop; // verilator lint_off WIDTH conw3 = 94'h000a_5010_4020_3030_2040_1050; // verilator lint_on WIDTH if (conw3[31:00]!== 32'h2040_1050 || conw3[63:32]!== 32'h4020_3030 || conw3[95:64]!== 32'h000a_5010 || conw3[128:96]!==33'h0) $stop; $display("%x... %x\n", conw3[15:0], ~| conw3[15:0]); if ((~| conw3[15:0]) !== 1'h0) $stop; if ((~& conw3[15:0]) !== 1'h1) $stop; // verilator lint_off WIDTH conw4 = 112'h7010_602a_5030_4040_3050_2060_1070; // verilator lint_on WIDTH if (conw4[31:00]!== 32'h2060_1070 || conw4[63:32]!== 32'h4040_3050 || conw4[95:64]!== 32'h602a_5030 || conw4[127:96]!==32'h7010) $stop; // conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070; w32 = 12; win <= 12; if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop; con__ascii = "abcdefghijklmnop"; if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop; con__ascii = "abcdefghijklm"; if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop; if ( 3'dx !== 3'hx) $stop; // Wide decimal if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop; if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop; // Increments w32 = 12; w32++; if (w32 != 13) $stop; w32 = 12; ++w32; if (w32 != 13) $stop; w32 = 12; w32--; if (w32 != 11) $stop; w32 = 12; --w32; if (w32 != 11) $stop; w32 = 12; w32 += 2; if (w32 != 14) $stop; w32 = 12; w32 -= 2; if (w32 != 10) $stop; w32 = 12; w32 *= 2; if (w32 != 24) $stop; w32 = 12; w32 /= 2; if (w32 != 6) $stop; w32 = 12; w32 &= 6; if (w32 != 4) $stop; w32 = 12; w32 |= 15; if (w32 != 15) $stop; w32 = 12; w32 ^= 15; if (w32 != 3) $stop; w32 = 12; w32 >>= 1; if (w32 != 6) $stop; w32 = 12; w32 <<= 1; if (w32 != 24) $stop; // Increments v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop; v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop; v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop; v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop; v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop; v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop; v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop; v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop; v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop; v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop; v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop; v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop; v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop; end if (cyc==2) begin win <= 32'h123123; if (narrow !== 32'hfffffefb) $stop; if (narrow2 !== 32'hffffff9d) $stop; end if (cyc==3) begin if (narrow !== 32'h00123012) $stop; if (narrow2 !== 32'h001230b4) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_flag_stats.v0000664000177100017500000000054313702133370021332 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (b); output reg [31:0] b; initial begin b = 22; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_case_group.v0000664000177100017500000000103013702133367021330 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 module t ( input i_clk, input [6:0] i_input, output logic o_output ); always_ff @(posedge i_clk) // verilator lint_off CASEINCOMPLETE case (i_input) 7'(92+2), 7'(92+3): o_output <= 1'b1; endcase initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_enum_type_methods.v0000664000177100017500000000477013702133370022741 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef enum [3:0] { E01 = 1, E03 = 3, E04 = 4 } my_t; integer cyc=0; my_t e; int arrayfits [e.num]; // Check can use as constant string all; // Check constification initial begin e = E03; `checkh(e.first, E01); `checkh(e.last, E04); `checkh(e.last(), E04); `checkh(e.next, E04); `checkh(e.next(), E04); `checkh(e.next(1), E04); `checkh(e.next(1).next(1), E01); `checkh(e.next(2), E01); `checkh(e.next(1).next(1).next(1), E03); `checkh(e.next(1).next(2), E03); `checkh(e.next(3), E03); `checkh(e.prev, E01); `checkh(e.prev(1), E01); `checkh(e.prev(1).prev(1), E04); `checkh(e.prev(2), E04); `checkh(e.num, 3); `checks(e.name, "E03"); // all = ""; for (my_t e = e.first; e != e.last; e = e.next) begin all = {all, e.name}; end e = e.last; all = {all, e.name}; `checks(all, "E01E03E04"); end // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup e <= E01; end else if (cyc==1) begin `checks(e.name, "E01"); `checkh(e.next, E03); `checkh(e.next(1), E03); `checkh(e.next(2), E04); `checkh(e.prev, E04); `checkh(e.prev(1), E04); `checkh(e.prev(2), E03); e <= E03; end else if (cyc==2) begin `checks(e.name, "E03"); `checkh(e.next, E04); `checkh(e.next(1), E04); `checkh(e.next(2), E01); `checkh(e.prev, E01); `checkh(e.prev(1), E01); `checkh(e.prev(2), E04); e <= E04; end else if (cyc==3) begin `checks(e.name, "E04"); `checkh(e.next, E01); `checkh(e.next(1), E01); `checkh(e.next(2), E03); `checkh(e.prev, E03); `checkh(e.prev(1), E03); `checkh(e.prev(2), E01); e <= E01; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_struct_init_bad.out0000664000177100017500000000044413702133370022722 0ustar wsnyderwsnyder%Error: t/t_struct_init.v:54:40: Assignment pattern contains duplicate entry: b1 : ... In instance t 54 | const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1}; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_pins_sc64.pl0000775000177100017500000000473713702133370022045 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_var_pinsizes.v"); compile( verilator_flags2 => ["-sc -pins64 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], make_main => 0, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16_vlt;/x); } execute(); ok(1); 1; verilator-4.038/test_regress/t/t_fuzz_negwidth_bad.pl0000775000177100017500000000107413702133370023051 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_display.out0000664000177100017500000001501113702133370021206 0ustar wsnyderwsnyder[0] In top.t: Hi [0] In top.t.sub (sub) [0] In top.t.sub.subblock (sub) [0] In top.t.sub2 (sub2) [0] In top.t.sub2.subblock2 (sub2) [0] Back \ Quote " [0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %d= 12 %0d=12 %d= 46099320012 %0d=46099320012 %d= 50692964483019020981880 %0d=50692964483019020981880 [0] %D= 12 %0D=12 %D= 46099320012 %0D=46099320012 %D= 50692964483019020981880 %0D=50692964483019020981880 [0] %h=00c %0h=c %h=00abbbbcccc %0h=abbbbcccc %h=00abc1234567812345678 %0h=abc1234567812345678 [0] %H=00c %0H=c %H=00abbbbcccc %0H=abbbbcccc %H=00abc1234567812345678 %0H=abc1234567812345678 [0] %o=014 %0o=14 %o=00527356746314 %0o=527356746314 %o=012570110642547402215053170 %0o=12570110642547402215053170 [0] %O=014 %0O=14 %O=00527356746314 %0O=527356746314 %O=012570110642547402215053170 %0O=12570110642547402215053170 [0] %x=00c %0x=c %x=00abbbbcccc %0x=abbbbcccc %x=00abc1234567812345678 %0x=abc1234567812345678 [0] %X=00c %0X=c %X=00abbbbcccc %0X=abbbbcccc %X=00abc1234567812345678 %0X=abc1234567812345678 [0] %d= 12 %0d=12 %d= -46099320012 %0d=-46099320012 %d= 50692964483019020981880 %0d=50692964483019020981880 [0] %D= 12 %0D=12 %D= -46099320012 %0D=-46099320012 %D= -50692964483019020981880 %0D=-50692964483019020981880 [0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %d= 12 %0d=12 %d= 46099320012 %0d=46099320012 %d= 50692964483019020981880 %0d=50692964483019020981880 [0] %D= 12 %0D=12 %D= 46099320012 %0D=46099320012 %D= 50692964483019020981880 %0D=50692964483019020981880 [0] %h=00c %0h=c %h=00abbbbcccc %0h=abbbbcccc %h=00abc1234567812345678 %0h=abc1234567812345678 [0] %H=00c %0H=c %H=00abbbbcccc %0H=abbbbcccc %H=00abc1234567812345678 %0H=abc1234567812345678 [0] %o=014 %0o=14 %o=00527356746314 %0o=527356746314 %o=012570110642547402215053170 %0o=12570110642547402215053170 [0] %O=014 %0O=14 %O=00527356746314 %0O=527356746314 %O=012570110642547402215053170 %0O=12570110642547402215053170 [0] %x=00c %0x=c %x=00abbbbcccc %0x=abbbbcccc %x=00abc1234567812345678 %0x=abc1234567812345678 [0] %X=00c %0X=c %X=00abbbbcccc %0X=abbbbcccc %X=00abc1234567812345678 %0X=abc1234567812345678 [0] %d= -12 %0d=-12 %d= -46099320012 %0d=-46099320012 %d= -50692964483019020981880 %0d=-50692964483019020981880 [0] %D= -12 %0D=-12 %D= -46099320012 %0D=-46099320012 %D= -50692964483019020981880 %0D=-50692964483019020981880 [0] %C=m %0C=m [0] %c=m %0c=m [0] %v=St0 St0 St0 St0 St0 St1 St1 St0 St0 %0v=St0 St0 St0 St0 St0 St1 St1 St0 St0 %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 < [0] %V=St0 St0 St0 St0 St0 St1 St1 St0 St0 %0V=St0 St0 St0 St0 St0 St1 St1 St0 St0 %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 < [0] %p= 12 %0p='hc %p= 46099320012 %0p='habbbbcccc %p= 50692964483019020981880 %0p='habc1234567812345678 [0] %P= 12 %0P='hc %P= 46099320012 %0P='habbbbcccc %P= 50692964483019020981880 %0P='habc1234567812345678 [0] %P="sv-str" [0] %u=dcba %0u=dcba [0] %U=dcba %0U=dcba [0] %D= 12 %d= 12 %01d=12 %06d=000012 %6d= 12 [0] %t= 0 %03t= 0 %0t=0 [0] %s=! %s= what! %s= hmmm!1234 [0] %6s=: !: %6s=: what!: %6s=: hmmm!1234: [0] %8s=: sv-str: d: 12 12 h: 00c 00c o: 014 014 b: 000001100 000001100 [0] hello, from a very long string. Percent %s are literally substituted in. hello, from a concatenated string. hello, from a concatenated format string [0]. extra argument: 0 0 : pre argument after [0] Embedded tab ' ' and <#013> return [0] Embedded multiline '23 23 23' '23 23 23 ' '23 23 23' '23 23 23 ' ' 24' '24 ' ' 0' '0 ' ' sv-str' 'sv-str ' ' meep' 'meep ' ' beep' 'beep ' log10(2) = 2 *-* All Finished *-* verilator-4.038/test_regress/t/t_class_param.out0000664000177100017500000000022313702133367022033 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_param.v:20:11: Unsupported: Parameter classes 20 | Cls #(.P(4)) c4; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_class1.out0000664000177100017500000000021513702133367020735 0ustar wsnyderwsnyderDisplay: null = "null" Display: newed = "`{imembera:'h0, imemberb:'h0}" Display: set = "`{imembera:'ha, imemberb:'h14}" *-* All Finished *-* verilator-4.038/test_regress/t/t_typedef_unused_bad.v0000664000177100017500000000040113702133370023025 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef logic ok_t; typedef fwd_undecl_t; verilator-4.038/test_regress/t/t_gated_clk_1.pl0000775000177100017500000000105313702133370021506 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_sys.v0000664000177100017500000000146313702133370020657 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Global is the most likely usage scenario import "DPI-C" dpii_sys_task = function void \$dpii_sys (int i); import "DPI-C" dpii_sys_func = function int \$dpii_func (int i); module t (); `ifndef verilator `error "Only Verilator supports PLI-ish DPI calls." `endif initial begin $dpii_sys(1); if ($dpii_func(2) != 3) $stop; $dpii_sys(10); if ($dpii_func(2) != 12) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_complex_fst_threads_1.pl0000775000177100017500000000141713702133370025010 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_complex.v"); $Self->{golden_filename} = "t/t_trace_complex_fst.out"; compile( verilator_flags2 => ['--cc --trace-fst --trace-threads 1'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_interface_array_modport.pl0000775000177100017500000000105313702133370024253 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_mlog2.pl0000775000177100017500000000105313702133370021404 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_decoration.v0000664000177100017500000000117113702133370022506 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer a_very_long_name_which_we_will_hash_eventually=0; always @ (posedge clk) begin a_very_long_name_which_we_will_hash_eventually <= a_very_long_name_which_we_will_hash_eventually + 1; if (a_very_long_name_which_we_will_hash_eventually == 5) begin fin(); end end task fin; $write("*-* All Finished *-*\n"); $finish; endtask endmodule verilator-4.038/test_regress/t/t_trace_timescale.pl0000775000177100017500000000124013702133370022473 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( v_flags2 => ["--trace"], ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_var_nonamebegin.out0000664000177100017500000000240413702133370022675 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Tue Jul 24 18:46:01 2012 $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $scope module t $end $var wire 1 # clk $end $var wire 1 % inmod $end $var wire 32 & rawmod [31:0] $end $var wire 1 $ reset_l $end $scope module genblk1 $end $var wire 32 ' ingen [31:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ( upa [31:0] $end $scope module d3nameda $end $var wire 32 ) d3a [31:0] $end $upscope $end $upscope $end $scope module unnamedblk2 $end $var wire 32 * b2 [31:0] $end $scope module b3named $end $var wire 32 + b3n [31:0] $end $upscope $end $scope module unnamedblk3 $end $var wire 32 , b3 [31:0] $end $scope module unnamedblk4 $end $var wire 32 - b4 [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ 0% b00000000000000000000000000000000 & b00000000000000000000000000000000 ' b00000000000000000000000000000000 ( b00000000000000000000000000000000 ) b00000000000000000000000000000000 * b00000000000000000000000000000000 + b00000000000000000000000000000000 , b00000000000000000000000000000000 - verilator-4.038/test_regress/t/t_param_width_loc_bad.pl0000775000177100017500000000120113702133370023306 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, bug1624"); scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_main.v0000664000177100017500000000057613702133370021126 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by engr248. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); initial begin $write("[%0t] Hello", $time); // Check timestamp works $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_real.v0000664000177100017500000001123513702133370021137 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) module t (/*AUTOARG*/ // Inputs clk ); input clk; integer i; reg [63:0] b; real r, r2; integer cyc=0; realtime uninit; initial if (uninit != 0.0) $stop; sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*); initial begin if (1_00_0.0_1 != 1000.01) $stop; // rtoi truncates if ($rtoi(36.7) != 36) $stop; if ($rtoi(36.5) != 36) $stop; if ($rtoi(36.4) != 36) $stop; // casting rounds if ((integer '(36.7)) != 37) $stop; if ((integer '(36.5)) != 37) $stop; if ((integer '(36.4)) != 36) $stop; // assignment rounds // verilator lint_off REALCVT i = 36.7; if (i != 37) $stop; i = 36.5; if (i != 37) $stop; i = 36.4; if (i != 36) $stop; r = 10'd38; if (r!=38.0) $stop; // verilator lint_on REALCVT // operators if ((-(1.5)) != -1.5) $stop; if ((+(1.5)) != 1.5) $stop; if (((1.5)+(1.25)) != 2.75) $stop; if (((1.5)-(1.25)) != 0.25) $stop; if (((1.5)*(1.25)) != 1.875) $stop; if (((1.5)/(1.25)) != 1.2) $stop; // if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0 if (((1.5)!=(2)) != 1'b1) $stop; if (((1.5)> (2)) != 1'b0) $stop; if (((1.5)>=(2)) != 1'b0) $stop; if (((1.5)< (2)) != 1'b1) $stop; if (((1.5)<=(2)) != 1'b1) $stop; if (((1.5)==(1.5)) != 1'b1) $stop; if (((1.5)!=(1.5)) != 1'b0) $stop; if (((1.5)> (1.5)) != 1'b0) $stop; if (((1.5)>=(1.5)) != 1'b1) $stop; if (((1.5)< (1.5)) != 1'b0) $stop; if (((1.5)<=(1.5)) != 1'b1) $stop; if (((1.6)==(1.5)) != 1'b0) $stop; if (((1.6)!=(1.5)) != 1'b1) $stop; if (((1.6)> (1.5)) != 1'b1) $stop; if (((1.6)>=(1.5)) != 1'b1) $stop; if (((1.6)< (1.5)) != 1'b0) $stop; if (((1.6)<=(1.5)) != 1'b0) $stop; // if (((0.0)?(2.0):(1.1)) != 1.1) $stop; if (((1.5)?(2.0):(1.1)) != 2.0) $stop; // if (!1.7) $stop; if (!(!0.0)) $stop; if (1.8 && 0.0) $stop; if (!(1.8 || 0.0)) $stop; // i=0; for (r=1.0; r<2.0; r=r+0.1) i++; if (i!=10) $stop; // bug r = $bitstoreal($realtobits(1.414)); if (r != 1.414) $stop; // bug r = 32'bxz000_111; // 7 accoding to IEEE if (r != 7) $stop; // bug b = 64'h7fe8000000000000; $display("%6.3f", $bitstoreal(b)); end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; if (cyc==0) begin // Setup end else if (cyc<90) begin if ($time != {32'h0, $rtoi($realtime)}) $stop; if ($itor(cyc) != cyc) $stop; //Unsup: if ((real `($time)) != $realtime) $stop; r = $itor(cyc*2); i = $rtoi(r); if (i!=cyc*2) $stop; // r = $itor(cyc)/1.5; b = $realtobits(r); r2 = $bitstoreal(b); if (r != r2) $stop; // // Trust the integer math as a comparison r = $itor(cyc); if ($rtoi(-r) != -cyc) $stop; if ($rtoi(+r) != cyc) $stop; if ($rtoi(r+2.0) != (cyc+2)) $stop; if ($rtoi(r-2.0) != (cyc-2)) $stop; if ($rtoi(r*2.0) != (cyc*2)) $stop; if ($rtoi(r/2.0) != (cyc/2)) $stop; r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash // r2 = $itor(cyc); case (r) (r2-1.0): $stop; r2: ; default: $stop; endcase // r = $itor(cyc); if ((r==50.0) != (cyc==50)) $stop; if ((r!=50.0) != (cyc!=50)) $stop; if ((r> 50.0) != (cyc> 50)) $stop; if ((r>=50.0) != (cyc>=50)) $stop; if ((r< 50.0) != (cyc< 50)) $stop; if ((r<=50.0) != (cyc<=50)) $stop; // if ($rtoi((r-50.0) ? 10.0 : 20.0) != (((cyc-50)!=0) ? 10 : 20)) $stop; // if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub_cast_bug374(input clk, input [4:0] cyc5); integer i; always @(posedge clk) begin i <= integer'(cyc5); end endmodule verilator-4.038/test_regress/t/t_uniqueif.pl0000775000177100017500000000116413702133370021201 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_writemem_b.pl0000775000177100017500000000255713702133370022413 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_sys_readmem.v"); # Use random reset to ensure we're fully initializing arrays before # $writememh, to avoid miscompares with X's on 4-state simulators. $Self->{verilated_randReset} = 2; # 2 == truly random compile(v_flags2 => [ "+define+WRITEMEM_READ_BACK=1", "+define+WRITEMEM_BIN=1", "+define+OUT_TMP1=\\\"$Self->{obj_dir}/tmp1.mem\\\"", "+define+OUT_TMP2=\\\"$Self->{obj_dir}/tmp2.mem\\\"", "+define+OUT_TMP3=\\\"$Self->{obj_dir}/tmp3.mem\\\"", "+define+OUT_TMP4=\\\"$Self->{obj_dir}/tmp4.mem\\\"", "+define+OUT_TMP5=\\\"$Self->{obj_dir}/tmp5.mem\\\"", ]); execute( check_finished => 1, ); for (my $i = 1; $i <= 5; $i++) { my $gold = "$Self->{t_dir}/t_sys_writemem_b.gold${i}.mem"; my $out = "$Self->{obj_dir}/tmp${i}.mem"; files_identical($out, $gold); } ok(1); 1; verilator-4.038/test_regress/t/t_lint_inherit.v0000664000177100017500000000176113702133370021676 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs q, // Inputs clk, d ); input clk; input d; output wire [1:0] q; // This demonstrates how warning disables should be propagated across module boundaries. m1 m1 (/*AUTOINST*/ // Outputs .q (q[1:0]), // Inputs .clk (clk), .d (d)); endmodule module m1 ( input clk, input d, output wire [1:0] q ); m2 m2 (/*AUTOINST*/ // Outputs .q (q[1:0]), // Inputs .clk (clk), .d (d)); endmodule module m2 ( input clk, input d, // Due to bug the below disable used to be ignored. // verilator lint_off UNOPT output reg [1:0] q // verilator lint_on UNOPT ); always @* begin q[1] = d; end always @* begin q[0] = q[1]; end endmodule verilator-4.038/test_regress/t/t_preproc_stringend_bad.out0000664000177100017500000000012413702133370024075 0ustar wsnyderwsnyder%Error: t/t_preproc_stringend_bad.v:8:1: Unterminated string %Error: Exiting due to verilator-4.038/test_regress/t/t_assoc_wildcard_unsup.pl0000775000177100017500000000107113702133367023572 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_method_bad.out0000664000177100017500000000051713702133367023027 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_method_bad.v:11:20: Unsupported: class extends 11 | class Cls2 extends Base1; | ^~~~~ %Error: t/t_class_method_bad.v:11:20: Found definition of 'Base1' as a CLASS but expected a variable 11 | class Cls2 extends Base1; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_split_var_1_bad.out0000664000177100017500000001434013702133370022576 0ustar wsnyderwsnyder%Warning-SPLITVAR: t/t_split_var_1_bad.v:7:13: 'should_show_warning_global0' has split_var metacomment, but will not be split because it is not declared in a module. 7 | logic [7:0] should_show_warning_global0 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ... Use "/* verilator lint_off SPLITVAR */" and lint_on around source to disable this message. %Warning-SPLITVAR: t/t_split_var_1_bad.v:8:13: 'should_show_warning_global1' has split_var metacomment, but will not be split because it is not declared in a module. 8 | logic [7:0] should_show_warning_global1 [1:0] /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:11:16: 'should_show_warning_ifs0' has split_var metacomment, but will not be split because it is not declared in a module. 11 | logic [7:0] should_show_warning_ifs0 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:12:16: 'should_show_warning_ifs1' has split_var metacomment, but will not be split because it is not declared in a module. 12 | logic [7:0] should_show_warning_ifs1 [1:0] /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:40:14: 'cannot_split1' has split_var metacomment but will not be split because it is accessed from another module via a dot. 40 | i_sub0.cannot_split1[0] = 0; | ^~~~~~~~~~~~~ %Warning-SELRANGE: t/t_split_var_1_bad.v:90:33: Selection index out of range: 13 outside 12:10 : ... In instance t.i_sub3 90 | assign outwires[12] = inwires[13]; | ^ %Warning-WIDTH: t/t_split_var_1_bad.v:41:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits. : ... In instance t 41 | i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); | ^ %Error: t/t_split_var_1_bad.v:79:16: Illegal assignment of constant to unpacked array : ... In instance t.i_sub2 79 | assign b = a[0]; | ^ %Warning-SPLITVAR: t/t_split_var_1_bad.v:56:31: 'cannot_split0' has split_var metacomment but will not be split because index cannot be determined statically. : ... In instance t.i_sub0 56 | rd_data = cannot_split0[addr]; | ^~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:90:34: 'inwires' has split_var metacomment but will not be split because index is out of range. : ... In instance t.i_sub3 90 | assign outwires[12] = inwires[13]; | ^~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:17:9: 'should_show_warning0' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic : ... In instance t 17 | real should_show_warning0 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:18:11: 'should_show_warning1' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic : ... In instance t 18 | string should_show_warning1 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:19:11: 'should_show_warning2' has split_var metacomment but will not be split because its bitwidth is 1 : ... In instance t 19 | wire should_show_warning2 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:23:16: 'public_signal' has split_var metacomment but will not be split because it is public : ... In instance t 23 | logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/ ; | ^~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:31:44: 'inout_port' has split_var metacomment but will not be split because it is an inout port : ... In instance t 31 | function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/ , | ^~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:32:42: 'ref_port' has split_var metacomment but will not be split because it is a ref argument : ... In instance t 32 | ref logic [7:0] ref_port /*verilator split_var*/ ); | ^~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:37:19: 'loop_idx' has split_var metacomment but will not be split because it is used as a loop variable : ... In instance t 37 | logic [7:0] loop_idx /*verilator split_var*/ ; | ^~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:62:11: 'cannot_split_genvar' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic : ... In instance t.i_sub1 62 | genvar cannot_split_genvar /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:65:65: 'cannot_split' has split_var metacomment but will not be split because its bit range cannot be determined statically. : ... In instance t.i_sub1 65 | logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr]; | ^ %Warning-SPLITVAR: t/t_split_var_1_bad.v:66:23: 'rd_tmp' has split_var metacomment but will not be split because its bit range cannot be determined statically. : ... In instance t.i_sub1 66 | rd_data = rd_tmp[{3'b0, addr[0]}+:8]; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_two_dump_cc.out0000664000177100017500000000271213702133370023226 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sat Mar 7 18:39:02 2020 $end $timescale 1ps $end $scope module topa $end $var wire 1 3 clk $end $scope module t $end $var wire 32 + c_trace_on [31:0] $end $var wire 1 3 clk $end $var wire 32 # cyc [31:0] $end $scope module sub $end $var wire 32 ; inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #10 b00000000000000000000000000000001 # b00000000000000000000000000000000 + 13 b00000000000000000000000000000001 ; #10 #15 #15 03 #20 #20 b00000000000000000000000000000010 # b00000000000000000000000000000011 + 13 #25 #25 03 #30 #30 b00000000000000000000000000000011 # b00000000000000000000000000000100 + 13 #35 #35 03 #40 #40 b00000000000000000000000000000100 # b00000000000000000000000000000101 + 13 #45 #45 03 #50 #50 b00000000000000000000000000000101 # b00000000000000000000000000000110 + 13 #55 #55 03 #60 #60 b00000000000000000000000000000110 # b00000000000000000000000000000111 + 13 #65 #65 03 #70 #70 b00000000000000000000000000000111 # b00000000000000000000000000001000 + 13 #75 #75 03 #80 #80 b00000000000000000000000000001000 # b00000000000000000000000000001001 + 13 #85 #85 03 #90 #90 b00000000000000000000000000001001 # b00000000000000000000000000001010 + 13 #95 #95 03 #100 #100 b00000000000000000000000000001010 # b00000000000000000000000000001011 + 13 #105 #105 03 #110 #110 13 b00000000000000000000000000001011 # b00000000000000000000000000001100 + verilator-4.038/test_regress/t/t_dos.pl0000775000177100017500000000105313702133370020136 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_for1.pl0000775000177100017500000000105313702133370021051 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_port_sc.pl0000775000177100017500000000244413702133370023076 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if (!$Self->have_sc) { skip("No SystemC installed"); } else { top_filename("t_trace_two_a.v"); compile( make_main => 0, verilator_make_gmake => 0, top_filename => 't_trace_two_b.v', VM_PREFIX => 'Vt_trace_two_b', verilator_flags2 => ['-sc -trace'], ); compile( make_main => 0, top_filename => 't_trace_two_a.v', verilator_flags2 => ['-sc', '-exe', '-trace', "$Self->{t_dir}/t_trace_two_sc.cpp"], v_flags2 => ['+define+TEST_DUMPPORTS'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } } ok(1); 1; verilator-4.038/test_regress/t/t_inst_sv.v0000664000177100017500000000265013702133370020671 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; supply0 [1:0] low; supply1 [1:0] high; reg [7:0] isizedwire; reg ionewire; wire oonewire; wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v t_inst sub ( .osizedreg, .oonewire, // Inputs .isizedwire (isizedwire[7:0]), .* //.ionewire (ionewire) ); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin ionewire <= 1'b1; isizedwire <= 8'd8; end if (cyc==2) begin if (low != 2'b00) $stop; if (high != 2'b11) $stop; if (oonewire !== 1'b1) $stop; if (isizedwire !== 8'd8) $stop; end if (cyc==3) begin ionewire <= 1'b0; isizedwire <= 8'd7; end if (cyc==4) begin if (oonewire !== 1'b0) $stop; if (isizedwire !== 8'd7) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module t_inst ( output reg [7:0] osizedreg, output wire oonewire /*verilator public*/, input [7:0] isizedwire, input wire ionewire ); assign oonewire = ionewire; always @* begin osizedreg = isizedwire; end endmodule verilator-4.038/test_regress/t/t_dpi_arg_output_type.v0000664000177100017500000011651113702133370023274 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `define NO_INTEGER `define NO_SHORTREAL `endif `ifdef MS `endif `ifdef VERILATOR `define NO_SHORTREAL `define NULL 64'd0 `else `define NULL null `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef VERILATOR wire _unused = &{1'b0, clk}; `endif // Legal output argument types for DPI functions //====================================================================== // Type definitions //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 typedef byte byte_t; typedef byte unsigned byte_unsigned_t; typedef shortint shortint_t; typedef shortint unsigned shortint_unsigned_t; typedef int int_t; typedef int unsigned int_unsigned_t; typedef longint longint_t; typedef longint unsigned longint_unsigned_t; `ifndef NO_TIME typedef time time_t; `endif `ifndef NO_INTEGER typedef integer integer_t; `endif typedef real real_t; `ifndef NO_SHORTREAL typedef shortreal shortreal_t; `endif typedef chandle chandle_t; typedef string string_t; typedef bit bit_t; typedef logic logic_t; // 2-state packed structures typedef struct packed { bit x; } struct_2_state_1; typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; // 2-state packed unions typedef union packed { bit x; bit y; } union_2_state_1; typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; // 4-state packed structures typedef struct packed { logic x; } struct_4_state_1; typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; // 4-state packed unions typedef union packed { logic x; bit y; } union_4_state_1; typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; //====================================================================== // Imports //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 import "DPI-C" function void i_byte (output byte o); import "DPI-C" function void i_byte_unsigned (output byte unsigned o); import "DPI-C" function void i_shortint (output shortint o); import "DPI-C" function void i_shortint_unsigned (output shortint unsigned o); import "DPI-C" function void i_int (output int o); import "DPI-C" function void i_int_unsigned (output int unsigned o); import "DPI-C" function void i_longint (output longint o); import "DPI-C" function void i_longint_unsigned (output longint unsigned o); `ifndef NO_TIME import "DPI-C" function void i_time (output time o); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer (output integer o); `endif import "DPI-C" function void i_real (output real o); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal (output shortreal o); `endif import "DPI-C" function void i_chandle (output chandle o); import "DPI-C" function void i_string (output string o); import "DPI-C" function void i_bit (output bit o); import "DPI-C" function void i_logic (output logic o); // Basic types via typedef import "DPI-C" function void i_byte_t (output byte_t o); import "DPI-C" function void i_byte_unsigned_t (output byte_unsigned_t o); import "DPI-C" function void i_shortint_t (output shortint_t o); import "DPI-C" function void i_shortint_unsigned_t (output shortint_unsigned_t o); import "DPI-C" function void i_int_t (output int_t o); import "DPI-C" function void i_int_unsigned_t (output int_unsigned_t o); import "DPI-C" function void i_longint_t (output longint_t o); import "DPI-C" function void i_longint_unsigned_t (output longint_unsigned_t o); `ifndef NO_TIME import "DPI-C" function void i_time_t (output time_t o); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer_t (output integer_t o); `endif import "DPI-C" function void i_real_t (output real_t o); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal_t (output shortreal_t o); `endif import "DPI-C" function void i_chandle_t (output chandle_t o); import "DPI-C" function void i_string_t (output string_t o); import "DPI-C" function void i_bit_t (output bit_t o); import "DPI-C" function void i_logic_t (output logic_t o); // 2-state packed arrays import "DPI-C" function void i_array_2_state_1 (output bit [ 0:0] o); import "DPI-C" function void i_array_2_state_32 (output bit [ 31:0] o); import "DPI-C" function void i_array_2_state_33 (output bit [ 32:0] o); import "DPI-C" function void i_array_2_state_64 (output bit [ 63:0] o); import "DPI-C" function void i_array_2_state_65 (output bit [ 64:0] o); import "DPI-C" function void i_array_2_state_128(output bit [127:0] o); // 2-state packed structures import "DPI-C" function void i_struct_2_state_1 (output struct_2_state_1 o); import "DPI-C" function void i_struct_2_state_32 (output struct_2_state_32 o); import "DPI-C" function void i_struct_2_state_33 (output struct_2_state_33 o); import "DPI-C" function void i_struct_2_state_64 (output struct_2_state_64 o); import "DPI-C" function void i_struct_2_state_65 (output struct_2_state_65 o); import "DPI-C" function void i_struct_2_state_128 (output struct_2_state_128 o); // 2-state packed unions import "DPI-C" function void i_union_2_state_1 (output union_2_state_1 o); import "DPI-C" function void i_union_2_state_32 (output union_2_state_32 o); import "DPI-C" function void i_union_2_state_33 (output union_2_state_33 o); import "DPI-C" function void i_union_2_state_64 (output union_2_state_64 o); import "DPI-C" function void i_union_2_state_65 (output union_2_state_65 o); import "DPI-C" function void i_union_2_state_128 (output union_2_state_128 o); // 4-state packed arrays import "DPI-C" function void i_array_4_state_1 (output logic [ 0:0] o); import "DPI-C" function void i_array_4_state_32 (output logic [ 31:0] o); import "DPI-C" function void i_array_4_state_33 (output logic [ 32:0] o); import "DPI-C" function void i_array_4_state_64 (output logic [ 63:0] o); import "DPI-C" function void i_array_4_state_65 (output logic [ 64:0] o); import "DPI-C" function void i_array_4_state_128(output logic [127:0] o); // 4-state packed structures import "DPI-C" function void i_struct_4_state_1 (output struct_4_state_1 o); import "DPI-C" function void i_struct_4_state_32 (output struct_4_state_32 o); import "DPI-C" function void i_struct_4_state_33 (output struct_4_state_33 o); import "DPI-C" function void i_struct_4_state_64 (output struct_4_state_64 o); import "DPI-C" function void i_struct_4_state_65 (output struct_4_state_65 o); import "DPI-C" function void i_struct_4_state_128 (output struct_4_state_128 o); // 4-state packed unions import "DPI-C" function void i_union_4_state_1 (output union_4_state_1 o); import "DPI-C" function void i_union_4_state_32 (output union_4_state_32 o); import "DPI-C" function void i_union_4_state_33 (output union_4_state_33 o); import "DPI-C" function void i_union_4_state_64 (output union_4_state_64 o); import "DPI-C" function void i_union_4_state_65 (output union_4_state_65 o); import "DPI-C" function void i_union_4_state_128 (output union_4_state_128 o); //====================================================================== // Exports //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 export "DPI-C" function e_byte; export "DPI-C" function e_byte_unsigned; export "DPI-C" function e_shortint; export "DPI-C" function e_shortint_unsigned; export "DPI-C" function e_int; export "DPI-C" function e_int_unsigned; export "DPI-C" function e_longint; export "DPI-C" function e_longint_unsigned; `ifndef NO_TIME export "DPI-C" function e_time; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer; `endif export "DPI-C" function e_real; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal; `endif export "DPI-C" function e_chandle; export "DPI-C" function e_string; export "DPI-C" function e_bit; export "DPI-C" function e_logic; // Basic types via typedef export "DPI-C" function e_byte_t; export "DPI-C" function e_byte_unsigned_t; export "DPI-C" function e_shortint_t; export "DPI-C" function e_shortint_unsigned_t; export "DPI-C" function e_int_t; export "DPI-C" function e_int_unsigned_t; export "DPI-C" function e_longint_t; export "DPI-C" function e_longint_unsigned_t; `ifndef NO_TIME export "DPI-C" function e_time_t; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer_t; `endif export "DPI-C" function e_real_t; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_t; `endif export "DPI-C" function e_chandle_t; export "DPI-C" function e_string_t; export "DPI-C" function e_bit_t; export "DPI-C" function e_logic_t; // 2-state packed arrays export "DPI-C" function e_array_2_state_1; export "DPI-C" function e_array_2_state_32; export "DPI-C" function e_array_2_state_33; export "DPI-C" function e_array_2_state_64; export "DPI-C" function e_array_2_state_65; export "DPI-C" function e_array_2_state_128; // 2-state packed structures export "DPI-C" function e_struct_2_state_1; export "DPI-C" function e_struct_2_state_32; export "DPI-C" function e_struct_2_state_33; export "DPI-C" function e_struct_2_state_64; export "DPI-C" function e_struct_2_state_65; export "DPI-C" function e_struct_2_state_128; // 2-state packed unions export "DPI-C" function e_union_2_state_1; export "DPI-C" function e_union_2_state_32; export "DPI-C" function e_union_2_state_33; export "DPI-C" function e_union_2_state_64; export "DPI-C" function e_union_2_state_65; export "DPI-C" function e_union_2_state_128; // 4-state packed arrays export "DPI-C" function e_array_4_state_1; export "DPI-C" function e_array_4_state_32; export "DPI-C" function e_array_4_state_33; export "DPI-C" function e_array_4_state_64; export "DPI-C" function e_array_4_state_65; export "DPI-C" function e_array_4_state_128; // 4-state packed structures export "DPI-C" function e_struct_4_state_1; export "DPI-C" function e_struct_4_state_32; export "DPI-C" function e_struct_4_state_33; export "DPI-C" function e_struct_4_state_64; export "DPI-C" function e_struct_4_state_65; export "DPI-C" function e_struct_4_state_128; // 4-state packed unions export "DPI-C" function e_union_4_state_1; export "DPI-C" function e_union_4_state_32; export "DPI-C" function e_union_4_state_33; export "DPI-C" function e_union_4_state_64; export "DPI-C" function e_union_4_state_65; export "DPI-C" function e_union_4_state_128; //====================================================================== // Definitions of exported functions //====================================================================== // Basic types as per IEEE 1800-2017 35.5.6 byte n_byte = 0; function void e_byte(output byte o); o = 8'd10 + n_byte; n_byte++; endfunction byte n_byte_unsigned = 0; function void e_byte_unsigned(output byte unsigned o); o = 8'd20 + n_byte_unsigned; n_byte_unsigned++; endfunction shortint n_shortint = 0; function void e_shortint(output shortint o); o = 16'd30 + n_shortint; n_shortint++; endfunction shortint n_shortint_unsigned = 0; function void e_shortint_unsigned(output shortint unsigned o); o = 16'd40 + n_shortint_unsigned; n_shortint_unsigned++; endfunction int n_int = 0; function void e_int(output int o); o = 32'd50 + n_int; n_int++; endfunction int n_int_unsigned = 0; function void e_int_unsigned(output int unsigned o); o = 32'd60 + n_int_unsigned; n_int_unsigned++; endfunction longint n_longint = 0; function void e_longint(output longint o); o = 64'd70 + n_longint; n_longint++; endfunction longint n_longint_unsigned = 0; function void e_longint_unsigned(output longint unsigned o); o = 64'd80 + n_longint_unsigned; n_longint_unsigned++; endfunction `ifndef NO_TIME longint n_time = 0; function void e_time(output time o); o = 64'd90 + n_time; n_time++; endfunction `endif `ifndef NO_INTEGER int n_integer = 0; function void e_integer(output integer o); o = 32'd100 + n_integer; n_integer++; endfunction `endif int n_real = 0; function void e_real(output real o); o = real'(2*n_real + 1) / 2.0; n_real++; endfunction `ifndef NO_SHORTREAL int n_shortreal = 0; function void e_shortreal(output shortreal o); o = shortreal'(4*n_shortreal + 1) / 4.0; n_shortreal++; endfunction `endif int n_chandle = 0; function void e_chandle(output chandle o); $display("e_chandle %1d", n_chandle); o = `NULL; n_chandle++; endfunction int n_string = 0; function void e_string(output string o); $display("e_string %1d", n_string); o = n_string[0] ? "World" : "Hello"; n_string++; endfunction int n_bit = 0; function void e_bit(output bit o); $display("e_bit %1d", n_bit); o = n_bit[0]; n_bit++; endfunction int n_logic = 0; function void e_logic(output logic o); $display("e_logic %1d", n_logic); o = ~n_logic[0]; n_logic++; endfunction // Basic types via typedefs byte_t n_byte_t = 0; function void e_byte_t(output byte_t o); o = 8'd10 + n_byte_t; n_byte_t += 2; endfunction byte n_byte_unsigned_t = 0; function void e_byte_unsigned_t(output byte_unsigned_t o); o = 8'd20 + n_byte_unsigned_t; n_byte_unsigned_t += 2; endfunction shortint_t n_shortint_t = 0; function void e_shortint_t(output shortint_t o); o = 16'd30 + n_shortint_t; n_shortint_t += 2; endfunction shortint n_shortint_unsigned_t = 0; function void e_shortint_unsigned_t(output shortint_unsigned_t o); o = 16'd40 + n_shortint_unsigned_t; n_shortint_unsigned_t += 2; endfunction int_t n_int_t = 0; function void e_int_t(output int_t o); o = 32'd50 + n_int_t; n_int_t += 2; endfunction int n_int_unsigned_t = 0; function void e_int_unsigned_t(output int_unsigned_t o); o = 32'd60 + n_int_unsigned_t; n_int_unsigned_t += 2; endfunction longint_t n_longint_t = 0; function void e_longint_t(output longint_t o); o = 64'd70 + n_longint_t; n_longint_t += 2; endfunction longint n_longint_unsigned_t = 0; function void e_longint_unsigned_t(output longint_unsigned_t o); o = 64'd80 + n_longint_unsigned_t; n_longint_unsigned_t += 2; endfunction `ifndef NO_TIME longint n_time_t = 0; function void e_time_t(output time_t o); o = 64'd90 + n_time_t; n_time_t += 2; endfunction `endif `ifndef NO_INTEGER int n_integer_t = 0; function void e_integer_t(output integer o); o = 32'd100 + n_integer_t; n_integer_t += 2; endfunction `endif int n_real_t = 0; function void e_real_t(output real_t o); o = real'(2*n_real_t + 1) / 2.0; n_real_t += 2; endfunction `ifndef NO_SHORTREAL int n_shortreal_t = 0; function void e_shortreal_t(output shortreal_t o); o = shortreal'(4*n_shortreal_t + 1) / 4.0; n_shortreal_t += 2; endfunction `endif int n_chandle_t = 0; function void e_chandle_t(output chandle_t o); $display("e_chandle_t %1d", n_chandle_t); o = `NULL; n_chandle_t++; endfunction int n_string_t = 0; function void e_string_t(output string_t o); $display("e_string_t %1d", n_string_t); o = n_string_t[0] ? "World" : "Hello"; n_string_t++; endfunction int n_bit_t = 0; function void e_bit_t(output bit_t o); $display("e_bit_t %1d", n_bit_t); o = n_bit_t[0]; n_bit_t++; endfunction int n_logic_t = 0; function void e_logic_t(output logic_t o); $display("e_logic_t %1d", n_logic_t); o = ~n_logic_t[0]; n_logic_t++; endfunction // 2-state packed arrays int n_array_2_state_1 = 0; function void e_array_2_state_1(output bit [ 0:0] o); $display("e_array_2_state_1 %1d", n_array_2_state_1); o = n_array_2_state_1[0]; n_array_2_state_1++; endfunction int n_array_2_state_32 = 0; function void e_array_2_state_32(output bit [31:0] o); $display("e_array_2_state_32 %1d", n_array_2_state_32); o = ~32'd0 >> n_array_2_state_32; n_array_2_state_32++; endfunction int n_array_2_state_33 = 0; function void e_array_2_state_33(output bit [32:0] o); $display("e_array_2_state_33 %1d", n_array_2_state_33); o = ~33'd0 >> n_array_2_state_33; n_array_2_state_33++; endfunction int n_array_2_state_64 = 0; function void e_array_2_state_64(output bit [63:0] o); $display("e_array_2_state_64 %1d", n_array_2_state_64); o = ~64'd0 >> n_array_2_state_64; n_array_2_state_64++; endfunction int n_array_2_state_65 = 0; function void e_array_2_state_65(output bit [64:0] o); $display("e_array_2_state_65 %1d", n_array_2_state_65); o = ~65'd0 >> n_array_2_state_65; n_array_2_state_65++; endfunction int n_array_2_state_128 = 0; function void e_array_2_state_128(output bit [127:0] o); $display("e_array_2_state_128 %1d", n_array_2_state_128); o = ~128'd0 >> n_array_2_state_128; n_array_2_state_128++; endfunction // 2-state packed structures int n_struct_2_state_1 = 0; function void e_struct_2_state_1(output struct_2_state_1 o); $display("e_struct_2_state_1 %1d", n_struct_2_state_1); o = n_struct_2_state_1[0]; n_struct_2_state_1++; endfunction int n_struct_2_state_32 = 0; function void e_struct_2_state_32(output struct_2_state_32 o); $display("e_struct_2_state_32 %1d", n_struct_2_state_32); o = ~32'd0 >> n_struct_2_state_32; n_struct_2_state_32++; endfunction int n_struct_2_state_33 = 0; function void e_struct_2_state_33(output struct_2_state_33 o); $display("e_struct_2_state_33 %1d", n_struct_2_state_33); o = ~33'd0 >> n_struct_2_state_33; n_struct_2_state_33++; endfunction int n_struct_2_state_64 = 0; function void e_struct_2_state_64(output struct_2_state_64 o); $display("e_struct_2_state_64 %1d", n_struct_2_state_64); o = ~64'd0 >> n_struct_2_state_64; n_struct_2_state_64++; endfunction int n_struct_2_state_65 = 0; function void e_struct_2_state_65(output struct_2_state_65 o); $display("e_struct_2_state_65 %1d", n_struct_2_state_65); o = ~65'd0 >> n_struct_2_state_65; n_struct_2_state_65++; endfunction int n_struct_2_state_128 = 0; function void e_struct_2_state_128(output struct_2_state_128 o); $display("e_struct_2_state_128 %1d", n_struct_2_state_128); o = ~128'd0 >> n_struct_2_state_128; n_struct_2_state_128++; endfunction // 2-state packed unions int n_union_2_state_1 = 0; function void e_union_2_state_1(output union_2_state_1 o); $display("e_union_2_state_1 %1d", n_union_2_state_1); o = n_union_2_state_1[0]; n_union_2_state_1++; endfunction int n_union_2_state_32 = 0; function void e_union_2_state_32(output union_2_state_32 o); $display("e_union_2_state_32 %1d", n_union_2_state_32); o = ~32'd0 >> n_union_2_state_32; n_union_2_state_32++; endfunction int n_union_2_state_33 = 0; function void e_union_2_state_33(output union_2_state_33 o); $display("e_union_2_state_33 %1d", n_union_2_state_33); o = ~33'd0 >> n_union_2_state_33; n_union_2_state_33++; endfunction int n_union_2_state_64 = 0; function void e_union_2_state_64(output union_2_state_64 o); $display("e_union_2_state_64 %1d", n_union_2_state_64); o = ~64'd0 >> n_union_2_state_64; n_union_2_state_64++; endfunction int n_union_2_state_65 = 0; function void e_union_2_state_65(output union_2_state_65 o); $display("e_union_2_state_65 %1d", n_union_2_state_65); o = ~65'd0 >> n_union_2_state_65; n_union_2_state_65++; endfunction int n_union_2_state_128 = 0; function void e_union_2_state_128(output union_2_state_128 o); $display("e_union_2_state_128 %1d", n_union_2_state_128); o = ~128'd0 >> n_union_2_state_128; n_union_2_state_128++; endfunction // 4-state packed arrays int n_array_4_state_1 = 0; function void e_array_4_state_1(output logic [ 0:0] o); $display("e_array_4_state_1 %1d", n_array_4_state_1); o = n_array_4_state_1[0]; n_array_4_state_1++; endfunction int n_array_4_state_32 = 0; function void e_array_4_state_32(output logic [31:0] o); $display("e_array_4_state_32 %1d", n_array_4_state_32); o = ~32'd0 >> n_array_4_state_32; n_array_4_state_32++; endfunction int n_array_4_state_33 = 0; function void e_array_4_state_33(output logic [32:0] o); $display("e_array_4_state_33 %1d", n_array_4_state_33); o = ~33'd0 >> n_array_4_state_33; n_array_4_state_33++; endfunction int n_array_4_state_64 = 0; function void e_array_4_state_64(output logic [63:0] o); $display("e_array_4_state_64 %1d", n_array_4_state_64); o = ~64'd0 >> n_array_4_state_64; n_array_4_state_64++; endfunction int n_array_4_state_65 = 0; function void e_array_4_state_65(output logic [64:0] o); $display("e_array_4_state_65 %1d", n_array_4_state_65); o = ~65'd0 >> n_array_4_state_65; n_array_4_state_65++; endfunction int n_array_4_state_128 = 0; function void e_array_4_state_128(output logic [127:0] o); $display("e_array_4_state_128 %1d", n_array_4_state_128); o = ~128'd0 >> n_array_4_state_128; n_array_4_state_128++; endfunction // 4-state packed structures int n_struct_4_state_1 = 0; function void e_struct_4_state_1(output struct_4_state_1 o); $display("e_struct_4_state_1 %1d", n_struct_4_state_1); o = n_struct_4_state_1[0]; n_struct_4_state_1++; endfunction int n_struct_4_state_32 = 0; function void e_struct_4_state_32(output struct_4_state_32 o); $display("e_struct_4_state_32 %1d", n_struct_4_state_32); o = ~32'd0 >> n_struct_4_state_32; n_struct_4_state_32++; endfunction int n_struct_4_state_33 = 0; function void e_struct_4_state_33(output struct_4_state_33 o); $display("e_struct_4_state_33 %1d", n_struct_4_state_33); o = ~33'd0 >> n_struct_4_state_33; n_struct_4_state_33++; endfunction int n_struct_4_state_64 = 0; function void e_struct_4_state_64(output struct_4_state_64 o); $display("e_struct_4_state_64 %1d", n_struct_4_state_64); o = ~64'd0 >> n_struct_4_state_64; n_struct_4_state_64++; endfunction int n_struct_4_state_65 = 0; function void e_struct_4_state_65(output struct_4_state_65 o); $display("e_struct_4_state_65 %1d", n_struct_4_state_65); o = ~65'd0 >> n_struct_4_state_65; n_struct_4_state_65++; endfunction int n_struct_4_state_128 = 0; function void e_struct_4_state_128(output struct_4_state_128 o); $display("e_struct_4_state_128 %1d", n_struct_4_state_128); o = ~128'd0 >> n_struct_4_state_128; n_struct_4_state_128++; endfunction // 4-state packed unions int n_union_4_state_1 = 0; function void e_union_4_state_1(output union_4_state_1 o); $display("e_union_4_state_1 %1d", n_union_4_state_1); o = n_union_4_state_1[0]; n_union_4_state_1++; endfunction int n_union_4_state_32 = 0; function void e_union_4_state_32(output union_4_state_32 o); $display("e_union_4_state_32 %1d", n_union_4_state_32); o = ~32'd0 >> n_union_4_state_32; n_union_4_state_32++; endfunction int n_union_4_state_33 = 0; function void e_union_4_state_33(output union_4_state_33 o); $display("e_union_4_state_33 %1d", n_union_4_state_33); o = ~33'd0 >> n_union_4_state_33; n_union_4_state_33++; endfunction int n_union_4_state_64 = 0; function void e_union_4_state_64(output union_4_state_64 o); $display("e_union_4_state_64 %1d", n_union_4_state_64); o = ~64'd0 >> n_union_4_state_64; n_union_4_state_64++; endfunction int n_union_4_state_65 = 0; function void e_union_4_state_65(output union_4_state_65 o); $display("e_union_4_state_65 %1d", n_union_4_state_65); o = ~65'd0 >> n_union_4_state_65; n_union_4_state_65++; endfunction int n_union_4_state_128 = 0; function void e_union_4_state_128(output union_4_state_128 o); $display("e_union_4_state_128 %1d", n_union_4_state_128); o = ~128'd0 >> n_union_4_state_128; n_union_4_state_128++; endfunction //====================================================================== // Invoke all functions 3 times (they have side effects) //====================================================================== import "DPI-C" context function void check_exports(); initial begin for (int i = 0 ; i < 3; i++) begin // Check the imports byte x_byte; byte unsigned x_byte_unsigned; shortint x_shortint; shortint unsigned x_shortint_unsigned; int x_int; int unsigned x_int_unsigned; longint x_longint; longint unsigned x_longint_unsigned; `ifndef NO_TIME time x_time; `endif `ifndef NO_INTEGER integer x_integer; `endif real x_real; `ifndef NO_SHORTREAL shortreal x_shortreal; `endif chandle x_chandle; string x_string; bit x_bit; logic x_logic; byte_t x_byte_t; byte_unsigned_t x_byte_unsigned_t; shortint_t x_shortint_t; shortint_unsigned_t x_shortint_unsigned_t; int_t x_int_t; int_unsigned_t x_int_unsigned_t; longint_t x_longint_t; longint_unsigned_t x_longint_unsigned_t; `ifndef NO_TIME time_t x_time_t; `endif `ifndef NO_INTEGER integer_t x_integer_t; `endif real_t x_real_t; `ifndef NO_SHORTREAL shortreal_t x_shortreal_t; `endif chandle_t x_chandle_t; string_t x_string_t; bit_t x_bit_t; logic_t x_logic_t; bit [ 0:0] x_bit_1; bit [ 31:0] x_bit_32; bit [ 32:0] x_bit_33; bit [ 63:0] x_bit_64; bit [ 64:0] x_bit_65; bit [127:0] x_bit_128; struct_2_state_1 x_struct_2_state_1; struct_2_state_32 x_struct_2_state_32; struct_2_state_33 x_struct_2_state_33; struct_2_state_64 x_struct_2_state_64; struct_2_state_65 x_struct_2_state_65; struct_2_state_128 x_struct_2_state_128; union_2_state_1 x_union_2_state_1; union_2_state_32 x_union_2_state_32; union_2_state_33 x_union_2_state_33; union_2_state_64 x_union_2_state_64; union_2_state_65 x_union_2_state_65; union_2_state_128 x_union_2_state_128; logic [ 0:0] x_logic_1; logic [ 31:0] x_logic_32; logic [ 32:0] x_logic_33; logic [ 63:0] x_logic_64; logic [ 64:0] x_logic_65; logic [127:0] x_logic_128; struct_4_state_1 x_struct_4_state_1; struct_4_state_32 x_struct_4_state_32; struct_4_state_33 x_struct_4_state_33; struct_4_state_64 x_struct_4_state_64; struct_4_state_65 x_struct_4_state_65; struct_4_state_128 x_struct_4_state_128; union_4_state_1 x_union_4_state_1; union_4_state_32 x_union_4_state_32; union_4_state_33 x_union_4_state_33; union_4_state_64 x_union_4_state_64; union_4_state_65 x_union_4_state_65; union_4_state_128 x_union_4_state_128; // Basic types as per IEEE 1800-2017 35.5.6 i_byte(x_byte); if (x_byte !== 8'd10 - 8'(i)) $stop; i_byte_unsigned(x_byte_unsigned); if (x_byte_unsigned !== 8'd20 - 8'(i)) $stop; i_shortint(x_shortint); if (x_shortint !== 16'd30 - 16'(i)) $stop; i_shortint_unsigned(x_shortint_unsigned); if (x_shortint_unsigned !== 16'd40 - 16'(i)) $stop; i_int(x_int); if (x_int !== 32'd50 - 32'(i)) $stop; i_int_unsigned(x_int_unsigned); if (x_int_unsigned !== 32'd60 - 32'(i)) $stop; i_longint(x_longint); if (x_longint !== 64'd70 - 64'(i)) $stop; i_longint_unsigned(x_longint_unsigned); if (x_longint_unsigned !== 64'd80 - 64'(i)) $stop; `ifndef NO_TIME i_time(x_time); if (x_time !== 64'd90 - 64'(i)) $stop; `endif `ifndef NO_INTEGER i_integer(x_integer); if (x_integer !== 32'd100- 32'(i)) $stop; `endif i_real(x_real); if (x_real != -1.0*i - 0.5 ) $stop; `ifndef NO_SHORTREAL i_shortreal(x_shortreal); if (x_shortreal != -1.0*i - 0.25) $stop; `endif if (~i[0]) begin i_chandle(x_chandle); if (x_chandle !== `NULL) $stop; i_string(x_string); if (x_string != "World") $stop; end else begin i_chandle(x_chandle); if (x_chandle === `NULL) $stop; i_string(x_string); if (x_string != "Hello") $stop; end i_bit(x_bit); if (x_bit !== ~i[0]) $stop; i_logic(x_logic); if (x_logic !== i[0]) $stop; // Basic types via typedefs i_byte_t(x_byte_t); if (x_byte_t !== 8'd10 - 8'(2*i)) $stop; i_byte_unsigned_t(x_byte_unsigned_t); if (x_byte_unsigned_t !== 8'd20 - 8'(2*i)) $stop; i_shortint_t(x_shortint_t); if (x_shortint_t !== 16'd30 - 16'(2*i)) $stop; i_shortint_unsigned_t(x_shortint_unsigned_t); if (x_shortint_unsigned_t !== 16'd40 - 16'(2*i)) $stop; i_int_t(x_int_t); if (x_int_t !== 32'd50 - 32'(2*i)) $stop; i_int_unsigned_t(x_int_unsigned_t); if (x_int_unsigned_t !== 32'd60 - 32'(2*i)) $stop; i_longint_t(x_longint_t); if (x_longint_t !== 64'd70 - 64'(2*i)) $stop; i_longint_unsigned_t(x_longint_unsigned_t); if (x_longint_unsigned_t !== 64'd80 - 64'(2*i)) $stop; `ifndef NO_TIME i_time_t(x_time_t); if (x_time_t !== 64'd90 - 64'(2*i)) $stop; `endif `ifndef NO_INTEGER i_integer_t(x_integer_t); if (x_integer_t !== 32'd100- 32'(2*i)) $stop; `endif i_real_t(x_real_t); if (x_real_t != -1.0*(2*i) - 0.5 ) $stop; `ifndef NO_SHORTREAL i_shortreal_t(x_shortreal_t); if (x_shortreal_t != -1.0*(2*i) - 0.25) $stop; `endif if (~i[0]) begin i_chandle_t(x_chandle_t); if (x_chandle_t !== `NULL) $stop; i_string_t(x_string_t); if (x_string_t != "World") $stop; end else begin i_chandle_t(x_chandle_t); if (x_chandle_t === `NULL) $stop; i_string_t(x_string_t); if (x_string_t != "Hello") $stop; end i_bit_t(x_bit_t); if (x_bit_t !== ~i[0]) $stop; i_logic_t(x_logic_t); if (x_logic_t !== i[0]) $stop; // 2-state packed arrays i_array_2_state_1(x_bit_1); if (x_bit_1 !== ~i[0] ) $stop; i_array_2_state_32(x_bit_32); if (x_bit_32 !== ~32'd0 << i) $stop; i_array_2_state_33(x_bit_33); if (x_bit_33 !== ~33'd0 << i) $stop; i_array_2_state_64(x_bit_64); if (x_bit_64 !== ~64'd0 << i) $stop; i_array_2_state_65(x_bit_65); if (x_bit_65 !== ~65'd0 << i) $stop; i_array_2_state_128(x_bit_128); if (x_bit_128 !== ~128'd0<< i) $stop; // 2-state packed structures i_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1 !== ~i[0] ) $stop; i_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32 !== ~32'd0 << i) $stop; i_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33 !== ~33'd0 << i) $stop; i_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64 !== ~64'd0 << i) $stop; i_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65 !== ~65'd0 << i) $stop; i_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128 !== ~128'd0<< i) $stop; // 2-state packed unions i_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1 !== ~i[0] ) $stop; i_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32 !== ~32'd0 << i) $stop; i_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33 !== ~33'd0 << i) $stop; i_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64 !== ~64'd0 << i) $stop; i_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65 !== ~65'd0 << i) $stop; i_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128 !== ~128'd0<< i) $stop; // 4-state packed arrays i_array_4_state_1(x_logic_1); if (x_logic_1 !== ~i[0] ) $stop; i_array_4_state_32(x_logic_32); if (x_logic_32 !== ~32'd0 << i) $stop; i_array_4_state_33(x_logic_33); if (x_logic_33 !== ~33'd0 << i) $stop; i_array_4_state_64(x_logic_64); if (x_logic_64 !== ~64'd0 << i) $stop; i_array_4_state_65(x_logic_65); if (x_logic_65 !== ~65'd0 << i) $stop; i_array_4_state_128(x_logic_128); if (x_logic_128 !== ~128'd0<< i) $stop; // 4-state packed structures i_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1 !== ~i[0] ) $stop; i_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32 !== ~32'd0 << i) $stop; i_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33 !== ~33'd0 << i) $stop; i_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64 !== ~64'd0 << i) $stop; i_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65 !== ~65'd0 << i) $stop; i_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128 !== ~128'd0<< i) $stop; // 4-state packed unions i_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1 !== ~i[0] ) $stop; i_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32 !== ~32'd0 << i) $stop; i_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33 !== ~33'd0 << i) $stop; i_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64 !== ~64'd0 << i) $stop; i_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65 !== ~65'd0 << i) $stop; i_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128 !== ~128'd0<< i) $stop; // Check the exports check_exports(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_flag_make_cmake.pl0000775000177100017500000000152713702133370022425 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_make_gmake => 0, verilator_make_cmake => 1, ); system("cmake --version"); if ($? != 0) { skip("cmake is not installed"); } else { my $cmakecache = $Self->{obj_dir}."/CMakeCache.txt"; if (! -e $cmakecache) { error("$cmakecache does not exist.") } execute( check_finished => 1, ); } ok(1); 1; verilator-4.038/test_regress/t/t_param_ceil.v0000664000177100017500000000204213702133370021273 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] O_out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .O_out (O_out[31:0])); initial begin if (O_out != 32'h4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test ( output [31:0] O_out ); test #( .pFOO(5), .pBAR(2) ) U_test ( .O_out(O_out) ); endmodule module test #(parameter pFOO = 7, parameter pBAR = 3, parameter pBAZ = ceiling(pFOO, pBAR) ) ( output [31:0] O_out ); assign O_out = pBAZ; function integer ceiling; input [31:0] x, y; ceiling = ((x%y == 0) ? x/y : (x/y)+1) + 1; endfunction endmodule verilator-4.038/test_regress/t/t_order_clkinst.v0000664000177100017500000000542213702133370022046 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off COMBDLY // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT // verilator lint_off BLKANDNBLK reg c1_start; initial c1_start = 0; wire [31:0] c1_count; comb_loop c1 (.count(c1_count), .start(c1_start)); wire s2_start = c1_start; wire [31:0] s2_count; seq_loop s2 (.count(s2_count), .start(s2_start)); wire c3_start = (s2_count[0]); wire [31:0] c3_count; comb_loop c3 (.count(c3_count), .start(c3_start)); reg [7:0] cyc; initial cyc=0; always @ (posedge clk) begin //$write("[%0t] %x counts %x %x %x\n",$time,cyc,c1_count,s2_count,c3_count); cyc <= cyc + 8'd1; case (cyc) 8'd00: begin c1_start <= 1'b0; end 8'd01: begin c1_start <= 1'b1; end default: ; endcase case (cyc) 8'd02: begin // On Verilator, we expect these comparisons to match exactly, // confirming that our settle loop repeated the exact number of // iterations we expect. No '$stop' should be called here, and we // should reach the normal '$finish' below on the next cycle. if (c1_count!=32'h3) $stop; if (s2_count!=32'h3) $stop; if (c3_count!=32'h5) $stop; end 8'd03: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase end endmodule module comb_loop (/*AUTOARG*/ // Outputs count, // Inputs start ); input start; output reg [31:0] count; initial count = 0; reg [31:0] runnerm1, runner; initial runner = 0; always @ (posedge start) begin runner = 3; end always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end always @ (/*AS*/runnerm1) begin if (runner > 0) begin count = count + 1; runner = runnerm1; $write ("%m count=%d runner =%x\n",count, runnerm1); end end endmodule module seq_loop (/*AUTOARG*/ // Outputs count, // Inputs start ); input start; output reg [31:0] count; initial count = 0; reg [31:0] runnerm1, runner; initial runner = 0; always @ (posedge start) begin runner <= 3; end always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end always @ (/*AS*/runnerm1) begin if (runner > 0) begin count = count + 1; runner <= runnerm1; $write ("%m count=%d runner<=%x\n",count, runnerm1); end end endmodule verilator-4.038/test_regress/t/t_lint_blksync_bad.out0000664000177100017500000000140013702133370023037 0ustar wsnyderwsnyder%Warning-BLKSEQ: t/t_lint_blksync_bad.v:24:16: Blocking assignments (=) in sequential (flop or latch) block : ... Suggest delayed assignments (<=) 24 | sync_blk = 1'b1; | ^ ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. %Warning-COMBDLY: t/t_lint_blksync_bad.v:31:18: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) 31 | combo_nblk <= 1'b1; | ^~ *** See the manual before disabling this, else you may end up with different sim results. %Error: Exiting due to verilator-4.038/test_regress/t/t_verilated_debug.pl0000775000177100017500000000141313702133370022476 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); $Self->{verilated_debug} = 1; compile( verilator_flags2 => [], ); execute( check_finished => 1, ); if (!$Self->{vltmt}) { # vltmt output may vary between thread exec order files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile"); } ok(1); 1; verilator-4.038/test_regress/t/t_lint_rsvd_bad.v0000664000177100017500000000040413702133370022011 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 config cfgBad; endconfig module t; endmodule verilator-4.038/test_regress/t/t_for_comma_bad.out0000664000177100017500000000115013702133370022310 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_for_comma_bad.v:27:23: Unsupported: for loop initialization after the first comma 27 | for (integer a=0, integer b=0; a<1; ) ; | ^ %Error-UNSUPPORTED: t/t_for_comma_bad.v:28:23: Unsupported: for loop initialization after the first comma 28 | for (integer a=0, integer b=0; a<1; a=a+1) ; | ^ %Error-UNSUPPORTED: t/t_for_comma_bad.v:29:23: Unsupported: for loop initialization after the first comma 29 | for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_flag_ldflags_so.cpp0000664000177100017500000000103713702133370022625 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* extern "C" { void dpii_so_library() {} }; verilator-4.038/test_regress/t/t_flag_werror_bad2.out0000664000177100017500000000043213702133370022743 0ustar wsnyderwsnyder%Error-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_time_passed.pl0000775000177100017500000000113513702133370021647 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_multidim_Ox.pl0000775000177100017500000000116713702133370022507 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_mem_multidim.v"); compile( verilator_flags2 => ['--Ox'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_file_basic_uz.v0000664000177100017500000000743013702133370022701 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2030 by Stephen Henry. // SPDX-License-Identifier: CC0-1.0 module t; int fdin_bin, fdout_txt, fdout_bin; `define STRINGIFY(x) `"x`" `define checkh(gotv,expv) \ do if ((gotv) !== (expv)) begin\ $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));\ end while(0) // // task automatic test1; begin for (int i = 0; i < 256; i++) begin byte actual, expected; expected = i[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end for (int i = 0; i < 256; i++) begin shortint actual, expected; for (int j = 0; j < 2; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end for (int i = 0; i < 256; i++) begin int actual, expected; for (int j = 0; j < 4; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end for (int i = 0; i < 256; i++) begin longint actual, expected; for (int j = 0; j < 8; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end end endtask // // task automatic test2; begin for (int i = 0; i < 256; i++) begin byte actual, expected; expected = i[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end for (int i = 0; i < 256; i++) begin shortint actual, expected; for (int j = 0; j < 2; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end for (int i = 0; i < 256; i++) begin int actual, expected; for (int j = 0; j < 4; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end for (int i = 0; i < 256; i++) begin longint actual, expected; for (int j = 0; j < 8; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end end endtask initial begin : main_PROC string filename; filename = "t/t_sys_file_basic_uz.dat"; fdin_bin = $fopen(filename, "rb"); `ifdef IVERILOG filename = $sformatf("%s/t_sys_file_basic_uz_test.log","obj_iv/t_sys_file_basic_uz"); `else filename = $sformatf("%s/t_sys_file_basic_uz_test.log",`STRINGIFY(`TEST_OBJ_DIR)); `endif fdout_txt = $fopen(filename, "w"); `ifdef IVERILOG filename = $sformatf("%s/t_sys_file_basic_uz_test.bin","obj_iv/t_sys_file_basic_uz"); `else filename = $sformatf("%s/t_sys_file_basic_uz_test.bin",`STRINGIFY(`TEST_OBJ_DIR)); `endif $display(filename); fdout_bin = $fopen(filename, "wb"); test1; test2; $fclose(fdin_bin); $fclose(fdout_txt); $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end // block: main_PROC `undef STRINGIFY endmodule // t verilator-4.038/test_regress/t/t_array_query.v0000664000177100017500000000246413702133367021560 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: System Verilog test of array querying functions. // // This code instantiates a module that calls the various array querying // functions. // // This file ONLY is placed into the Public Domain, for any use, without // warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Jeremy Bennett, Embecosm. module t (/*AUTOARG*/ // Inputs clk ); input clk; wire a = clk; wire b = 1'b0; reg c; array_test array_test_i (/*AUTOINST*/ // Inputs .clk (clk)); endmodule // Check the array sizing functions work correctly. module array_test #( parameter LEFT = 5, RIGHT = 55) (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off LITENDIAN reg [7:0] a [LEFT:RIGHT]; // verilator lint_on LITENDIAN typedef reg [7:0] r_t; integer l; integer r; integer s; always @(posedge clk) begin l = $left (a); r = $right (a); s = $size (a); `ifdef TEST_VERBOSE $write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s); `endif if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop; if ($left(r_t)!=7 || $right(r_t)!=0 || $size(r_t)!=8 || $bits(r_t) !=8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_with_unsup.out0000664000177100017500000000315113702133370021750 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_with_unsup.v:19:31: Unsupported: with statements 19 | found = aliases.find(i) with (i == to_find); | ^~~~ %Error-UNSUPPORTED: t/t_with_unsup.v:21:23: Unsupported: with statements 21 | aliases.find(i) with (i == to_find); | ^~~~ %Error-UNSUPPORTED: t/t_with_unsup.v:24:28: Unsupported: with statements 24 | found = aliases.find with (item == i); | ^~~~ %Error-UNSUPPORTED: t/t_with_unsup.v:25:20: Unsupported: with statements 25 | aliases.find with (item == i); | ^~~~ %Error-UNSUPPORTED: t/t_with_unsup.v:29:30: Unsupported: with statements 29 | found = aliases.unique with (id); | ^~~~ %Error-UNSUPPORTED: t/t_with_unsup.v:30:32: Unsupported: with statements 30 | found = aliases.unique() with (id); | ^~~~ %Error-UNSUPPORTED: t/t_with_unsup.v:31:33: Unsupported: with statements 31 | found = aliases.unique(i) with (id); | ^~~~ %Error-UNSUPPORTED: t/t_with_unsup.v:32:26: Unsupported: with statements 32 | found = aliases.or with (id); | ^~~~ %Error-UNSUPPORTED: t/t_with_unsup.v:33:27: Unsupported: with statements 33 | found = aliases.and with (id); | ^~~~ %Error-UNSUPPORTED: t/t_with_unsup.v:34:27: Unsupported: with statements 34 | found = aliases.xor with (id); | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_dpi_var.cpp0000664000177100017500000001131613702133370021144 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include VM_PREFIX_INCLUDE #include "verilated.h" #include "svdpi.h" #include "verilated_syms.h" //====================================================================== struct MyMon { vluint32_t* sigsp[2]; MyMon() { sigsp[0] = NULL; sigsp[1] = NULL; } }; MyMon mons[2]; void mon_register_a(const char* namep, void* sigp, bool isOut) { // Callback from initial block in monitor #ifdef TEST_VERBOSE VL_PRINTF("- mon_register_a(\"%s\", %p, %d);\n", namep, sigp, isOut); #endif mons[0].sigsp[isOut] = (vluint32_t*)sigp; } void mon_do(MyMon* monp) { if (!monp->sigsp[0]) vl_fatal(__FILE__, __LINE__, "", "never registered"); if (!monp->sigsp[1]) vl_fatal(__FILE__, __LINE__, "", "never registered"); *monp->sigsp[1] = (*(monp->sigsp[0])) + 1; #ifdef TEST_VERBOSE VL_PRINTF("- mon_do(%08x(&%p) -> %08x(&%p));\n", *(monp->sigsp[0]), monp->sigsp[0], *(monp->sigsp[1]), monp->sigsp[1]); #endif } void mon_class_name(const char* namep) { #ifdef TEST_VERBOSE VL_PRINTF("- mon_class_name(\"%s\");\n", namep); #endif // Check the C's calling name of "" doesn't lead to extra dots in the name() if (namep && namep[0] == '.') vl_fatal(__FILE__, __LINE__, "", (std::string("Unexp class name ") + namep).c_str()); } extern "C" void mon_scope_name(const char* namep); void mon_scope_name(const char* namep) { const char* modp = svGetNameFromScope(svGetScope()); #ifdef TEST_VERBOSE VL_PRINTF("- mon_scope_name('%s', \"%s\");\n", modp, namep); #endif if (strcmp(namep, "t.sub")) vl_fatal(__FILE__, __LINE__, "", (std::string("Unexp scope name ") + namep).c_str()); if (strcmp(modp, "t.sub")) vl_fatal(__FILE__, __LINE__, "", (std::string("Unexp dpiscope name ") + modp).c_str()); } extern "C" void mon_register_b(const char* namep, int isOut); void mon_register_b(const char* namep, int isOut) { const char* modp = svGetNameFromScope(svGetScope()); #ifdef TEST_VERBOSE VL_PRINTF("- mon_register_b('%s', \"%s\", %d);\n", modp, namep, isOut); #endif // Use scope to get pointer and size of signal const VerilatedScope* scopep = Verilated::dpiScope(); const VerilatedVar* varp = scopep->varFind(namep); if (!varp) { VL_PRINTF("%%Warning: mon_register_b signal not found: \"%s\"\n", namep); } else if (varp->vltype() != VLVT_UINT32) { VL_PRINTF("%%Warning: wrong type for signal: \"%s\"\n", namep); } else { vluint32_t* datap = (vluint32_t*)(varp->datap()); VL_PRINTF("- mon_register_b('%s', \"%s\", %p, %d);\n", modp, namep, datap, isOut); mons[1].sigsp[isOut] = (vluint32_t*)(varp->datap()); } } extern "C" void mon_register_done(); void mon_register_done() { #ifdef TEST_VERBOSE const char* modp = svGetNameFromScope(svGetScope()); VL_PRINTF("- mon_register_done('%s');\n", modp); #endif // Print list of all signals - if we didn't register2 anything we'd pick them off here const VerilatedScope* scopep = Verilated::dpiScope(); if (VerilatedVarNameMap* varsp = scopep->varsp()) { for (VerilatedVarNameMap::const_iterator it = varsp->begin(); it != varsp->end(); ++it) { VL_PRINTF("- mon2: %s\n", it->first); } } } extern "C" void mon_eval(); void mon_eval() { // Callback from always@ negedge mon_do(&mons[0]); mon_do(&mons[1]); } //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out #ifdef VERILATOR # ifdef TEST_VERBOSE Verilated::scopesDump(); # endif #endif topp->eval(); topp->clk = 0; main_time += 10; while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += 1; topp->eval(); topp->clk = !topp->clk; // mon_do(); } if (!Verilated::gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); VL_DO_DANGLING(delete topp, topp); exit(0L); } verilator-4.038/test_regress/t/t_protect_ids_bad.pl0000775000177100017500000000135513702133370022503 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ["--protect-ids", "--trace", "--public", "--vpi", ], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_notfound_bad.pl0000775000177100017500000000107413702133370023422 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_with_unsup.v0000664000177100017500000000173013702133370021407 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); initial begin int tofind; int aliases[$]; int found[$]; int id; int i; aliases = '{ 1, 4, 6, 8}; tofind = 6; found = aliases.find(i) with (i == to_find); // And as function aliases.find(i) with (i == to_find); // No parenthesis found = aliases.find with (item == i); aliases.find with (item == i); // Unique (array method) id = 4; found = aliases.unique with (id); found = aliases.unique() with (id); found = aliases.unique(i) with (id); found = aliases.or with (id); found = aliases.and with (id); found = aliases.xor with (id); end endmodule verilator-4.038/test_regress/t/t_verilated_debug.v0000664000177100017500000000061713702133370022332 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Test loop always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_const2_bad.out0000664000177100017500000000153413702133370022577 0ustar wsnyderwsnyder%Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const2_bad.v:22:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t.b8_a7.c9 t/t_func_const2_bad.v:10:6: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const2_bad.v:15:13: ... Called from f_add() with parameters: a = 32'h7 b = 32'h8 t/t_func_const2_bad.v:22:23: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 22 | localparam SOMEP = f_add2(A, B, 9); | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_udp_noname.pl0000775000177100017500000000124013702133370021474 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( expect_filename => $Self->{golden_filename}, fails => $Self->{vlt_all}, # Verilator unsupported, bug468" ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_basic.v0000664000177100017500000000251213702133367021651 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; integer cyc; initial cyc=1; wire [7:0] cyc_copy = cyc[7:0]; always @ (negedge clk) begin AssertionFalse1: assert (cyc<100); assert (!(cyc==5) || toggle); // FIX cover {cyc==3 || cyc==4}; // FIX cover {cyc==9} report "DefaultClock,expect=1"; // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; end always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; toggle <= !cyc[0]; if (cyc==7) assert (cyc[0] == cyc[1]); // bug743 if (cyc==9) begin `ifdef FAILING_ASSERTIONS assert (0) else $info; assert (0) else $info("Info message"); assume (0) else $info("Info message from failing assumption"); assert (0) else $info("Info message, cyc=%d", cyc); InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); InErrorBlock: assert (0) else $error("Error...."); assert (0) else $fatal(1,"Fatal...."); `endif end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_dedupe_seq_logic.v0000664000177100017500000000532613702133370022502 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Dedupe optimization test. // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Varun Koyyalagunta, Centaur Technology. // // Test consists of the follow logic tree, which has many obvious // places for dedupe: /* output + --------------/ \-------------- / \ + + ----/ \----- ----/ \---- / + / + + / \ + / \ -/ \- a b -/ \- a b / \ / \ + + + + / \ / \ / \ / \ a b c d a b c d */ module t(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left,right; add add(sum,left,right,clk); l l(left,a,b,c,d,clk); r r(right,a,b,c,d,clk); endmodule module l(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left, right; add add(sum,left,right,clk); ll ll(left,a,b,c,d,clk); lr lr(right,a,b,c,d,clk); endmodule module ll(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left, right; add add(sum,left,right,clk); lll lll(left,a,b,c,d,clk); llr llr(right,a,b,c,d,clk); endmodule module lll(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add add(sum,a,b,clk); endmodule module llr(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add add(sum,c,d,clk); endmodule module lr(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add add(sum,a,b,clk); endmodule module r(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left, right; add add(sum,left,right,clk); rl rl(left,a,b,c,d,clk); rr rr(right,a,b,c,d,clk); endmodule module rr(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add add(sum,a,b,clk); endmodule module rl(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left, right; add add(sum,left,right,clk); rll rll(left,a,b,c,d,clk); rlr rlr(right,a,b,c,d,clk); endmodule module rll(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add2 add(sum,a,b,clk); endmodule module rlr(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add2 add(sum,c,d,clk); endmodule module add(sum,x,y,clk); output reg sum; input x,y,clk; reg t1,t2; always @(posedge clk) begin sum <= x + y; end endmodule module add2(sum,x,y,clk); output reg sum; input x,y,clk; reg t1,t2; always @(posedge clk) begin sum <= x + y; end endmodule verilator-4.038/test_regress/t/t_gen_inc.pl0000775000177100017500000000105313702133370020753 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_synth.v0000664000177100017500000000431113702133367021734 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg a; initial a = 1'b1; reg b_fc; initial b_fc = 1'b0; reg b_pc; initial b_pc = 1'b0; reg b_oh; initial b_oh = 1'b0; reg b_oc; initial b_oc = 1'b0; wire a_l = ~a; wire b_oc_l = ~b_oc; // Note we must ensure that full, parallel, etc, only fire during // edges (not mid-cycle), and must provide a way to turn them off. // SystemVerilog provides: $asserton and $assertoff. // verilator lint_off CASEINCOMPLETE always @* begin // Note not all tools support directives on casez's `ifdef ATTRIBUTES case ({a,b_fc}) // synopsys full_case `else case ({a,b_fc}) `endif 2'b0_0: ; 2'b0_1: ; 2'b1_0: ; // Note no default endcase priority case ({a,b_fc}) 2'b0_0: ; 2'b0_1: ; 2'b1_0: ; // Note no default endcase end always @* begin `ifdef ATTRIBUTES case (1'b1) // synopsys full_case parallel_case `else `ifdef FAILING_FULL case (1'b1) // synopsys parallel_case `else case (1'b1) // synopsys parallel_full `endif `endif a: ; b_pc: ; endcase end `ifdef NOT_YET_VERILATOR // Unsupported // ambit synthesis one_hot "a, b_oh" // cadence one_cold "a_l, b_oc_l" `endif integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 1'b1; b_fc <= 1'b0; b_pc <= 1'b0; b_oh <= 1'b0; b_oc <= 1'b0; end if (cyc==2) begin a <= 1'b0; b_fc <= 1'b1; b_pc <= 1'b1; b_oh <= 1'b1; b_oc <= 1'b1; end if (cyc==3) begin a <= 1'b1; b_fc <= 1'b0; b_pc <= 1'b0; b_oh <= 1'b0; b_oc <= 1'b0; end if (cyc==4) begin `ifdef FAILING_FULL b_fc <= 1'b1; `endif `ifdef FAILING_PARALLEL b_pc <= 1'b1; `endif `ifdef FAILING_OH b_oh <= 1'b1; `endif `ifdef FAILING_OC b_oc <= 1'b1; `endif end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_trace_array_threads_1.pl0000775000177100017500000000133213702133370023577 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_trace_array.v"); compile( verilator_flags2 => ['--cc --trace --trace-threads 1 --trace-structs'], ); execute( check_finished => 1, ); file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); ok(1); 1; verilator-4.038/test_regress/t/t_pp_defparen_bad.v0000664000177100017500000000041313702133370022270 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define test(a1,a2) ((a1) + (a2)) `test val ( 1,2) verilator-4.038/test_regress/t/t_trace_complex_fst_threads_2.pl0000775000177100017500000000141713702133370025011 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_complex.v"); $Self->{golden_filename} = "t/t_trace_complex_fst.out"; compile( verilator_flags2 => ['--cc --trace-fst --trace-threads 2'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_param.pl0000775000177100017500000000163113702133370021331 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); skip("Known compiler limitation") if $Self->cxx_version =~ /\(GCC\) 4.4/; compile( make_top_shell => 0, make_main => 0, make_pli => 1, iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2 => ["+define+USE_VPI_NOT_DPI"], verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_param.cpp"], ); execute( iv_pli => 1, check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_cover_sva_notflat.v0000664000177100017500000000223613702133370022722 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; integer cyc; initial cyc=1; Test suba (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle), .cyc (cyc[31:0])); Test subb (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle), .cyc (cyc[31:0])); Test subc (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle), .cyc (cyc[31:0])); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; toggle <= !cyc[0]; if (cyc==9) begin end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test ( input clk, input toggle, input [31:0] cyc ); // Don't flatten out these modules please: // verilator no_inline_module // Labeled cover cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); endmodule verilator-4.038/test_regress/t/t_mem_packed_assign.v0000664000177100017500000000157713702133370022644 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); /* verilator lint_off WIDTH */ input clk; integer cyc; initial cyc = 0; logic [31:0] arr_c; initial arr_c = 0; logic [7:0] [3:0] arr; logic [31:0] arr2_c; initial arr2_c = 0; logic [7:0] [3:0] arr2; assign arr2_c = arr2; always @ (posedge clk) begin cyc <= cyc + 1; arr_c <= arr_c + 1; arr2 <= arr2 + 1; `ifdef TEST_VERBOSE $write("cyc%0d c:%0x a0:%0x a1:%0x a2:%0x a3:%0x\n", cyc, arr_c, arr[0], arr[1], arr[2], arr[3]); `endif if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end /* verilator lint_on WIDTH */ endmodule verilator-4.038/test_regress/t/t_param_first.v0000664000177100017500000001102213702133370021504 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [4:0] par1; // From a1 of t_param_first_a.v wire [4:0] par2; // From a2 of t_param_first_a.v wire [4:0] par3; // From a3 of t_param_first_a.v wire [4:0] par4; // From a4 of t_param_first_a.v wire [1:0] varwidth1; // From a1 of t_param_first_a.v wire [2:0] varwidth2; // From a2 of t_param_first_a.v wire [3:0] varwidth3; // From a3 of t_param_first_a.v wire [3:0] varwidth4; // From a4 of t_param_first_a.v // End of automatics /*t_param_first_a AUTO_TEMPLATE ( .par (par@[])); .varwidth (varwidth@[])); */ parameter XX = 2'bXX; parameter THREE = 3; t_param_first_a #(1,5) a1 ( // Outputs .varwidth (varwidth1[1:0]), /*AUTOINST*/ // Outputs .par (par1[4:0])); // Templated t_param_first_a #(2,5) a2 ( // Outputs .varwidth (varwidth2[2:0]), /*AUTOINST*/ // Outputs .par (par2[4:0])); // Templated t_param_first_a #(THREE,5) a3 ( // Outputs .varwidth (varwidth3[3:0]), /*AUTOINST*/ // Outputs .par (par3[4:0])); // Templated t_param_first_a #(THREE,5) a4 ( // Outputs .varwidth (varwidth4[3:0]), /*AUTOINST*/ // Outputs .par (par4[4:0])); // Templated parameter THREE_BITS_WIDE = 3'b011; parameter THREE_2WIDE = 2'b11; parameter ALSO_THREE_WIDE = THREE_BITS_WIDE; parameter THREEPP_32_WIDE = 2*8*2+3; parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide // Width propagation doesn't care about LHS vs RHS // But the width of a RHS/LHS on a upper node does affect lower nodes; // Thus must double-descend in width analysis. // VCS 7.0.1 is broken on this test! parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop; parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop; // Parameters assign LHS is affectively width zero. parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop; parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop; // Must be careful about LSB's with extracts parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop; // parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3; parameter THREE_32_WIDE = 3%32; parameter THIRTYTWO = 2; // Param is 32 bits parameter [40:0] WIDEPARAM = 41'h12_3456789a; parameter [40:0] WIDEPARAM2 = WIDEPARAM; reg [7:0] eightb; reg [3:0] fourb; wire [7:0] eight = 8'b00010000; wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE]; wire [2:0] threebits = ALSO_THREE_WIDE; // surefire lint_off CWCCXX initial _ranit = 0; always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; $write("[%0t] t_param: Running\n", $time); // $write(" %d %d %d\n", par1,par2,par3); if (par1!==5'd1) $stop; if (par2!==5'd2) $stop; if (par3!==5'd3) $stop; if (par4!==5'd3) $stop; if (varwidth1!==2'd2) $stop; if (varwidth2!==3'd2) $stop; if (varwidth3!==4'd2) $stop; if (varwidth4!==4'd2) $stop; if (threebits !== 3'b011) $stop; if (eight !== 8'b00010000) $stop; if (eight2two !== 2'b10) $stop; $write(" Params = %b %b\n %b %b\n", THREEPP_32_WIDE,THREEPP_3_WIDE, THIRTYTWO, THREEPP_32P_WIDE); if (THREEPP_32_WIDE !== 32'h23) $stop; if (THREEPP_3_WIDE !== 3'h3) $stop; if (THREEPP_32P_WIDE !== 32'h23) $stop; if (THIRTYTWO[1:0] !== 2'h2) $stop; if (THIRTYTWO !== 32'h2) $stop; if (THIRTYTWO !== 2) $stop; if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop; if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop; if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1 // // Example of assignment LHS affecting expression widths. // verilator lint_off WIDTH // surefire lint_off ASWCMB // surefire lint_off ASWCBB eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop; fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop; fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop; // verilator lint_on WIDTH // surefire lint_on ASWCMB // surefire lint_on ASWCBB // $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_driver_random.pl0000775000177100017500000000150513702133370022206 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use Time::HiRes; scenarios(dist => 1); if (!$ENV{VERILATOR_TEST_RANDOM_FAILURE}) { ok("Test is for harness checking only, setenv VERILATOR_TEST_RANDOM_FAILURE=1 "); } else { # Randomly fail to test driver.pl my ($ign, $t) = Time::HiRes::gettimeofday(); if ($t % 2) { error("random failure ".$t); } else { ok(1); } } 1; verilator-4.038/test_regress/t/t_savable_class_bad.v0000664000177100017500000000074513702133370022617 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int imembera; endclass : Cls module t (/*AUTOARG*/); initial begin Cls c; if (c != null) $stop; c = new; c.imembera = 10; if (c.imembera != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_savable_class_bad.pl0000775000177100017500000000116113702133370022761 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( v_flags2 => ["--savable"], save_time => 500, fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_sc.v0000664000177100017500000000103513702133370020463 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; // bug1081 - We don't use VPI, just need SC with VPI initial begin $write("%0t: Hello\n", $time); $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-4.038/test_regress/t/t_unopt_combo.pl0000775000177100017500000000112413702133370021674 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ['+define+ALLOW_UNOPT'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_fst.v0000664000177100017500000000447413702133370021164 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs state, // Inputs clk ); input clk; int cyc; reg rstn; output [4:0] state; parameter real fst_gparam_real = 1.23; localparam real fst_lparam_real = 4.56; real fst_real = 1.23; integer fst_integer; bit fst_bit; logic fst_logic; int fst_int; shortint fst_shortint; longint fst_longint; byte fst_byte; parameter fst_parameter = 123; localparam fst_lparam = 456; supply0 fst_supply0; supply1 fst_supply1; tri0 fst_tri0; tri1 fst_tri1; tri fst_tri; wire fst_wire; Test test (/*AUTOINST*/ // Outputs .state (state[4:0]), // Inputs .clk (clk), .rstn (rstn)); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup rstn <= ~'1; end else if (cyc<10) begin rstn <= ~'1; end else if (cyc<90) begin rstn <= ~'0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input rstn, output logic [4:0] state ); logic [4:0] state_w; logic [4:0] state_array [3]; assign state = state_array[0]; always_comb begin state_w[4] = state_array[2][0]; state_w[3] = state_array[2][4]; state_w[2] = state_array[2][3] ^ state_array[2][0]; state_w[1] = state_array[2][2]; state_w[0] = state_array[2][1]; end always_ff @(posedge clk or negedge rstn) begin if (!rstn) begin for (int i = 0; i < 3; i++) state_array[i] <= 'b1; end else begin for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; state_array[2] <= state_w; end end endmodule verilator-4.038/test_regress/t/t_flag_build_bad.out0000664000177100017500000000013713702133370022442 0ustar wsnyderwsnyder%Error: --make cannot be used together with --build. Suggest see manual %Error: Exiting due to verilator-4.038/test_regress/t/t_case_onehot.pl0000775000177100017500000000105313702133367021646 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_cond_bitrange_bad.out0000664000177100017500000000235213702133370024002 0ustar wsnyderwsnyder%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:58:38: Selection index out of range: 2:2 outside 1:0 : ... In instance t.i_test_gen 58 | if ((g < (SIZE + 1)) && MASK[g]) begin | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70:32: Selection index out of range: 2:2 outside 1:0 : ... In instance t.i_test_gen 70 | if ((g < SIZE) && MASK[g + 1]) begin | ^ %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:83:33: Selection index out of range: 2:2 outside 1:0 : ... In instance t.i_test_gen 83 | if ((g < (SIZE)) & MASK[g]) begin | ^ %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:96:35: Selection index out of range: 2:2 outside 1:0 : ... In instance t.i_test_gen 96 | if (!((g >= SIZE) | ~MASK[g])) begin | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_array_nocolon_bad.out0000664000177100017500000000243713702133370025244 0ustar wsnyderwsnyder%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 : ... In instance t 26 | foo_intf foos [N] (.x(X)); | ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 : ... In instance t 27 | foo_intf fool [1:3] (.x(X)); | ^ %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 : ... In instance t 30 | foo_subm subs [N] (.x(X)); | ^ %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 : ... In instance t 31 | foo_subm subl [1:3] (.x(X)); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_star.pl0000775000177100017500000000106013702133370022340 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_const_dec_mixed_bad.out0000664000177100017500000000032613702133367023507 0ustar wsnyderwsnyder%Error: t/t_const_dec_mixed_bad.v:9:30: Mixing X/Z/? with digits not legal in decimal constant: x_1 9 | parameter [200:0] MIXED = 32'dx_1; | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_inst_misarray2_bad.v0000664000177100017500000000102413702133370022752 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); wire signed [16:0] fft_oQ [6:0]; round round( .i_data(fft_oQ[6:0]) ); endmodule module round( input wire signed [16:0] i_data // Misdeclared, not a vector ); wire signed [15:0] w_convergent = {10'b0, {6{~i_data[7]}}}; endmodule verilator-4.038/test_regress/t/t_sys_rand.v0000664000177100017500000000153113702133370021023 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [31:0] lastrand; reg [31:0] thisrand; integer same = 0; integer i; `define TRIES 20 initial begin // There's a 1^32 chance of the numbers being the same twice, // so we'll allow one failure lastrand = $random; for (i=0; i<`TRIES; i=i+1) begin thisrand = $random; `ifdef TEST_VERBOSE $write("Random = %x\n", thisrand); `endif if (thisrand == lastrand) same=same+1; lastrand = thisrand; end if (same > 1) begin $write("%%Error: Too many similar numbers: %d\n", same); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_mismodport_bad.v0000664000177100017500000000125313702133370024225 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer ok; integer bad; modport out_modport (output ok); endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc itop(); counter_ansi c1 (.isub(itop), .i_value(4'h4)); endmodule module counter_ansi ( ifc.out_modport isub, input logic [3:0] i_value ); always @* begin isub.ok = i_value; isub.bad = i_value; // Illegal access end endmodule verilator-4.038/test_regress/t/t_func_public.v0000664000177100017500000001270213702133370021474 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; tpub p1 (.clk(clk), .i(32'd1)); tpub p2 (.clk(clk), .i(32'd2)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin `ifdef verilator $c("publicTop();"); `endif end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end task publicTop; // verilator public // We have different optimizations if only one of something, so try it out. $write("Hello in publicTop\n"); endtask endmodule module tpub ( input clk, input [31:0] i); reg [23:0] var_long; reg [59:0] var_quad; reg [71:0] var_wide; reg var_bool; // verilator lint_off BLKANDNBLK reg [11:0] var_flop; // verilator lint_on BLKANDNBLK reg [23:0] got_long /*verilator public*/; reg [59:0] got_quad /*verilator public*/; reg [71:0] got_wide /*verilator public*/; reg got_bool /*verilator public*/; integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; // cyc==1 is in top level if (cyc==2) begin publicNoArgs; publicSetBool(1'b1); publicSetLong(24'habca); publicSetQuad(60'h4444_3333_2222); publicSetWide(72'h12_5678_9123_1245_2352); var_flop <= 12'habe; end if (cyc==3) begin if (1'b1 != publicGetSetBool(1'b0)) $stop; if (24'habca != publicGetSetLong(24'h1234)) $stop; if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop; if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop; end if (cyc==4) begin publicGetBool(got_bool); if (1'b0 != got_bool) $stop; publicGetLong(got_long); if (24'h1234 != got_long) $stop; publicGetQuad(got_quad); if (60'h123_4567_89ab != got_quad) $stop; publicGetWide(got_wide); if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; end // `ifdef VERILATOR_PUBLIC_TASKS if (cyc==11) begin $c("publicNoArgs();"); $c("publicSetBool(true);"); $c("publicSetLong(0x11bca);"); $c("publicSetQuad(0x66655554444ULL);"); $c("publicSetFlop(0x321);"); //Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);"); end if (cyc==12) begin $c("got_bool = publicGetSetBool(true);"); $c("got_long = publicGetSetLong(0x11bca);"); $c("got_quad = publicGetSetQuad(0xaaaabbbbccccULL);"); end if (cyc==13) begin $c("{ bool gb; publicGetBool(gb); got_bool=gb; }"); if (1'b1 != got_bool) $stop; $c("publicGetLong(got_long);"); if (24'h11bca != got_long) $stop; $c("{ vluint64_t qq; publicGetQuad(qq); got_quad=qq; }"); if (60'haaaa_bbbb_cccc != got_quad) $stop; $c("{ WData gw[3]; publicGetWide(gw); VL_ASSIGN_W(72,got_wide,gw); }"); if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; //Below doesn't work, because we're calling it inside the loop that sets var_flop // if (12'h321 != var_flop) $stop; end if (cyc==14) begin if ($c32("publicInstNum()") != i) $stop; end `endif end end task publicEmpty; // verilator public begin end endtask task publicNoArgs; // verilator public $write("Hello in publicNoArgs\n"); endtask task publicSetBool; // verilator public input in_bool; var_bool = in_bool; endtask task publicSetLong; // verilator public input [23:0] in_long; reg [23:0] not_long; begin not_long = ~in_long; // Test that we can have local variables var_long = ~not_long; end endtask task publicSetQuad; // verilator public input [59:0] in_quad; var_quad = in_quad; endtask task publicSetFlop; // verilator public input [11:0] in_flop; var_flop = in_flop; endtask task publicSetWide; // verilator public input [71:0] in_wide; var_wide = in_wide; endtask task publicGetBool; // verilator public output out_bool; out_bool = var_bool; endtask task publicGetLong; // verilator public output [23:0] out_long; out_long = var_long; endtask task publicGetQuad; // verilator public output [59:0] out_quad; out_quad = var_quad; endtask task publicGetWide; // verilator public output [71:0] out_wide; out_wide = var_wide; endtask function publicGetSetBool; // verilator public input in_bool; begin publicGetSetBool = var_bool; var_bool = in_bool; end endfunction function [23:0] publicGetSetLong; // verilator public input [23:0] in_long; begin publicGetSetLong = var_long; var_long = in_long; end endfunction function [59:0] publicGetSetQuad; // verilator public input [59:0] in_quad; begin publicGetSetQuad = var_quad; var_quad = in_quad; end endfunction function [71:0] publicGetSetWide; // Can't be public, as no wide return types in C++ input [71:0] in_wide; begin publicGetSetWide = var_wide; var_wide = in_wide; end endfunction `ifdef VERILATOR_PUBLIC_TASKS function [31:0] publicInstNum; // verilator public publicInstNum = i; endfunction `endif endmodule verilator-4.038/test_regress/t/t_flag_invalid2_bad.pl0000775000177100017500000000114513702133370022662 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, verilator_flags2 => ['+invalid-plus'], expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_hdrfst_cc.out0000775000177100017500000000355013702133370023557 0ustar wsnyderwsnyder$date Sun Apr 19 04:15:51 2020 $end $version fstWriter $end $timescale 1ps $end $scope module topa $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $var integer 32 # c_trace_on $end $scope module sub $end $var integer 32 $ inside_sub_a $end $upscope $end $upscope $end $upscope $end $scope module topb $end $var wire 1 % clk $end $scope module t $end $var wire 1 % clk $end $var integer 32 & cyc $end $var integer 32 ' c_trace_on $end $var real 64 ( r $end $scope module sub $end $var integer 32 ) inside_sub_a $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000000000000000000000000000001 " b00000000000000000000000000000000 # b00000000000000000000000000000001 $ 0% b00000000000000000000000000000001 & b00000000000000000000000000000000 ' r0 ( b00000000000000000000000000000010 ) #10 r0.1 ( 1% b00000000000000000000000000000011 # b00000000000000000000000000000010 " 1! #15 0! 0% #20 1% 1! b00000000000000000000000000000011 " b00000000000000000000000000000100 # r0.2 ( #25 0! 0% #30 1% 1! r0.3 ( b00000000000000000000000000000101 # b00000000000000000000000000000100 " #35 0! 0% #40 1% 1! b00000000000000000000000000000101 " b00000000000000000000000000000110 # r0.4 ( #45 0! 0% #50 1% 1! r0.5 ( b00000000000000000000000000000111 # b00000000000000000000000000000110 " #55 0! 0% #60 1% 1! b00000000000000000000000000000111 " b00000000000000000000000000001000 # r0.6 ( #65 0! 0% #70 1% 1! r0.7 ( b00000000000000000000000000001001 # b00000000000000000000000000001000 " #75 0! 0% #80 1% 1! b00000000000000000000000000001001 " b00000000000000000000000000001010 # r0.7999999999999999 ( #85 0! 0% #90 1% 1! r0.8999999999999999 ( b00000000000000000000000000001011 # b00000000000000000000000000001010 " #95 0! 0% #100 1% 1! b00000000000000000000000000001011 " b00000000000000000000000000001100 # r0.9999999999999999 ( verilator-4.038/test_regress/t/t_tri_pullup.pl0000775000177100017500000000123713702133370021554 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_assign.pl0000775000177100017500000000100413702133370021462 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_select_plusloop.pl0000775000177100017500000000105313702133370022565 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_foreach.v0000664000177100017500000000667313702133370020624 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/); // verilator lint_off LITENDIAN // verilator lint_off WIDTH reg [63:0] sum; // Checked not in objects reg [63:0] add; reg [2:1] [4:3] array [5:6] [7:8]; reg [1:2] [3:4] larray [6:5] [8:7]; bit [31:0] depth1_array [0:0]; typedef struct packed { reg [1:0] [63:0] subarray; } str_t; typedef struct packed { str_t mid; } mid_t; mid_t strarray[3]; function [63:0] crc (input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); crc = {sum[62:0],sum[63]} ^ {4'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; endfunction initial begin sum = 0; // We use 'index_' as the prefix for all loop vars, // this allows t_foreach.pl to confirm that all loops // have been unrolled and flattened away and no loop vars // remain in the generated .cpp foreach (depth1_array[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); // Ensure the index never goes out of bounds. // We used to get this wrong for an array of depth 1. assert (index_a != -1); assert (index_a != 1); end `checkh(sum, 64'h0); sum = 0; foreach (array[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); end `checkh(sum, 64'h000000c000000000); sum = 0; foreach (array[index_a,index_b]) begin sum = crc(sum, index_a, index_b, 0, 0); end `checkh(sum, 64'h000003601e000000); sum = 0; foreach (array[index_a,index_b,index_c]) begin sum = crc(sum, index_a, index_b, index_c, 0); end `checkh(sum, 64'h00003123fc101000); sum = 0; foreach (array[index_a,index_b,index_c,index_d]) begin sum = crc(sum, index_a, index_b, index_c, index_d); end `checkh(sum, 64'h0030128ab2a8e557); // sum = 0; foreach (larray[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); end `checkh(sum, 64'h0000009000000000); sum = 0; foreach (larray[index_a,index_b]) begin sum = crc(sum, index_a, index_b, 0, 0); sum = sum + {4'b0,index_a[7:0], 4'h0,index_b[7:0]}; end `checkh(sum, 64'h000002704b057073); sum = 0; foreach (larray[index_a,index_b,index_c]) begin sum = crc(sum, index_a, index_b, index_c, 0); end `checkh(sum, 64'h00002136f9000000); sum = 0; foreach (larray[index_a,index_b,index_c,index_d]) begin sum = crc(sum, index_a, index_b, index_c, index_d); end `checkh(sum, 64'h0020179aa7aa0aaa); add = 0; strarray[0].mid.subarray[0] = 1; strarray[0].mid.subarray[1] = 2; strarray[1].mid.subarray[0] = 4; strarray[1].mid.subarray[1] = 5; strarray[2].mid.subarray[0] = 6; strarray[2].mid.subarray[1] = 7; `ifndef VERILATOR // Unsupported foreach (strarray[s]) foreach (strarray[s].mid.subarray[ss]) add += strarray[s].mid.subarray[ss]; `checkh(add, 'h19); `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_sys_readmem_align_h.mem0000664000177100017500000000106713702133370023507 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 77554004_37654321_27654321_17654321_07654321_abcdef10 @a 7755400a_37654321_27654321_17654321_07654321_abcdef11 7755400b_37654321_27654321_17654321_07654321_abcdef12 7755400c_37654321_27654321_17654321_07654321_abcdef13 verilator-4.038/test_regress/t/t_flag_wpedantic_bad.v0000664000177100017500000000040713702133370022757 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg global; endmodule verilator-4.038/test_regress/t/t_flag_define.vc0000664000177100017500000000051313702133370021566 0ustar wsnyderwsnyder+define+D1A +define+D2A=VALA +define+D3A+D3B +define+D4A=VALA+D4B +define+D5A=VALA+D5B=VALB // Quotes do NOT escape the plus //+define+D5A="VALA+D5B"+D5C +define+STRING1="\"New String\"" +define+STRING2='"New String"' +define+STRING3=\"New\ String\" +define+LIT1=32'h600D600D +define+LIT2=32\'h600D600D +define+LIT3="32'h600D600D" verilator-4.038/test_regress/t/t_clk_gen.v0000664000177100017500000000455013702133367020615 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // verilator lint_off GENCLK reg gendlyclk_r; reg [31:0] gendlydata_r; reg [31:0] dlydata_gr; reg genblkclk; reg [31:0] genblkdata; reg [31:0] blkdata_gr; wire [31:0] constwire = 32'h11; reg [31:0] initwire; integer i; initial begin for (i=0; i<10000; i=i+1) begin initwire = 32'h2200; end end wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; always @ (posedge clk) begin gendlydata_r <= 32'h0011_0000; gendlyclk_r <= 0; // surefire lint_off SEQASS genblkclk = 0; genblkdata = 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==2) begin gendlyclk_r <= 1; gendlydata_r <= 32'h00540000; genblkclk = 1; genblkdata = 32'hace; $write("[%0t] Send pulse\n", $time); end if (cyc==3) begin genblkdata = 32'hdce; gendlydata_r <= 32'h00ff0000; if (either != 32'h87542211) $stop; $write("*-* All Finished *-*\n"); $finish; end end // surefire lint_on SEQASS end always @ (posedge gendlyclk_r) begin if ($time>0) begin // Hack, don't split the block $write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata); dlydata_gr <= 32'h80000000; // Delayed activity list will already be completed for gendlydata // because genclk is from a delayed assignment. // Thus we get the NEW not old value of gendlydata_r if (gendlydata_r != 32'h00540000) $stop; if (genblkdata != 32'hace) $stop; end end always @ (posedge genblkclk) begin if ($time>0) begin // Hack, don't split the block $write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata); blkdata_gr <= 32'h07000000; // Clock from non-delayed assignment, we get old value of gendlydata_r `ifdef verilator `else // V3.2 races... technically legal if (gendlydata_r != 32'h00110000) $stop; `endif if (genblkdata != 32'hace) $stop; end end endmodule verilator-4.038/test_regress/t/t_lint_width_genfor_bad.v0000664000177100017500000000154113702133370023515 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs rc, rg, ri, rp, rw ); parameter P = 17; wire [4:0] w = 5'd1; output reg [3:0] rc; output reg [3:0] rg; output reg [3:0] ri; output reg [3:0] rp; output reg [3:0] rw; for (genvar g=16; g < 17; ++g) begin // Index 17 makes a width violation initial begin rg = g; // WidthMin mismatch rp = P; // WidthMin mismatch rw = w; // Always a mismatch rc = 64'h1; // Always a mismatch (as sized) end end initial begin for (integer i=16; i < 17; ++i) begin ri = i; // WidthMin mismatch end end endmodule verilator-4.038/test_regress/t/t_time_vpi_1fs1fs.out0000664000177100017500000000125313702133370022543 0ustar wsnyderwsnyder:: In top.t Time scale of t is 1fs / 1fs [60] time%0d=60 123%0t=123 dig%0t=5432109876543210 dig%0d=5432109876543210 rdig%0t=5432109876543210 rdig%0f=5432109876543210.000000 [0.000060ns] time%0d=60 123%0t=0.000123ns dig%0t=5432109876.543210ns dig%0d=5432109876543210 rdig%0t=5432109876.543210ns rdig%0f=5432109876543210.000000 [0.000060ns] stime%0t=0.000060ns stime%0d=60 stime%0f=60.000000 [0.000060ns] rtime%0t=0.000060ns rtime%0d=60 rtime%0f=60.000000 global vpiSimTime = 0,60 vpiScaledRealTime = 60 global vpiTimeUnit = -15 vpiTimePrecision = -15 top.t vpiSimTime = 0,60 vpiScaledRealTime = 60 top.t vpiTimeUnit = -15 vpiTimePrecision = -15 *-* All Finished *-* verilator-4.038/test_regress/t/t_scope_map.v0000664000177100017500000000255713702133370021160 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test symbol table scope map and general public // signal reflection // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t ( input wire CLK ); foo #(.WIDTH (1)) foo1 (.*); foo #(.WIDTH (7)) foo7 (.*); foo #(.WIDTH (8)) foo8 (.*); foo #(.WIDTH (32)) foo32 (.*); foo #(.WIDTH (33)) foo33 (.*); foo #(.WIDTH (40)) foo40 (.*); foo #(.WIDTH (41)) foo41 (.*); foo #(.WIDTH (64)) foo64 (.*); foo #(.WIDTH (65)) foo65 (.*); foo #(.WIDTH (96)) foo96 (.*); foo #(.WIDTH (97)) foo97 (.*); foo #(.WIDTH (128)) foo128 (.*); foo #(.WIDTH (256)) foo256 (.*); foo #(.WIDTH (1024)) foo1024 (.*); bar #(.WIDTH (1024)) bar1024 (.*); endmodule module foo #( parameter WIDTH = 32 ) ( input CLK ); logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value; logic [ WIDTH - 1 : 0 ] value_q /* verilator public */; integer i; initial begin initial_value = '1; for (i = 0; i < WIDTH / 8; i++) initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ]; value_q = initial_value[ WIDTH - 1 : 0 ]; end always @(posedge CLK) value_q <= ~value_q; endmodule module bar #( parameter WIDTH = 32 ) ( input CLK ); foo #(.WIDTH (WIDTH)) foo (.*); endmodule verilator-4.038/test_regress/t/t_pp_defparen_bad.out0000664000177100017500000000035713702133370022641 0ustar wsnyderwsnyder%Error: t/t_pp_defparen_bad.v:10:2: Illegal text before '(' that starts define arguments 10 | ( 1,2) | ^ %Error: t/t_pp_defparen_bad.v:10:1: syntax error, unexpected '(' 10 | ((val 1) + (2)) | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_real_param.v0000664000177100017500000000113113702133370022313 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug475 module t(); function real get_real_one; input ignored; get_real_one = 1.1; endfunction localparam R_PARAM = get_real_one(1'b0); localparam R_PARAM_2 = (R_PARAM > 0); generate initial begin if (R_PARAM != 1.1) $stop; if (R_PARAM_2 != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endgenerate endmodule verilator-4.038/test_regress/t/t_dpi_export_noopt.pl0000775000177100017500000000157313702133370022754 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end scenarios(simulator => 1); top_filename("t/t_dpi_export.v"); compile( # Amazingly VCS, NC and Verilator all just accept the C file here! v_flags2 => ["t/t_dpi_export_c.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME -no-l2name", $Self->{vlt_all} ? "-O0" : ""], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_slice_struct_array_modport.v0000664000177100017500000000065113702133370024650 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic p; } s_data; module m1 (output s_data data[1:0]); assign data[0].p = 0; assign data[1].p = 0; endmodule module top (output s_data data[2:0]); m1 m1_inst (.data(data[1:0])); endmodule verilator-4.038/test_regress/t/t_math_shortreal_unsup_bad.out0000664000177100017500000000047113702133370024621 0ustar wsnyderwsnyder%Warning-SHORTREAL: t/t_math_shortreal_unsup_bad.v:9:4: Unsupported: shortreal being promoted to real (suggest use real instead) 9 | shortreal s; | ^~~~~~~~~ ... Use "/* verilator lint_off SHORTREAL */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_wait.pl0000775000177100017500000000114513702133370020317 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ['--lint-only'], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_extern.pl0000775000177100017500000000117613702133367022057 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_detectarray_2.pl0000775000177100017500000000114613702133370022104 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-Wno-CLKDATA", "-Wno-UNOPTFLAT"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_multiwire.v0000664000177100017500000000353013702133370022061 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off LITENDIAN wire [7:0] array [2:0][1:3]; wire [7:0] arrayNoColon [2][3]; // verilator lint_on LITENDIAN integer cyc; initial cyc=0; integer i0,i1,i2; genvar g0,g1,g2; generate for (g0=0; g0<3; g0=g0+1) begin for (g1=1; g1<4; g1=g1+1) begin inst inst (.q(array[g0[1:0]] [g1[1:0]]), .cyc(cyc), .i0(g0[1:0]), .i1(g1[1:0])); end end endgenerate always @ (posedge clk) begin //$write("cyc==%0d\n",cyc); cyc <= cyc + 1; if (cyc==2) begin if (array[2][1] !== 8'h92) $stop; for (i0=0; i0<3; i0=i0+1) begin for (i1=1; i1<4; i1=i1+1) begin //$write(" array[%0d][%0d] == 8'h%x\n",i0,i1,array[i0[1:0]] [i1[1:0]]); if (array[i0[1:0]] [i1[1:0]] != {i0[1:0], i1[1:0], cyc[3:0]}) $stop; end end end else if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module inst (/*AUTOARG*/ // Outputs q, // Inputs cyc, i0, i1 ); output reg [7:0] q; input [31:0] cyc; input [1:0] i0; input [1:0] i1; inst2 inst2 (/*AUTOINST*/ // Inputs .cyc (cyc[31:0]), .i0 (i0[1:0]), .i1 (i1[1:0])); always @* begin q = {i0, i1, cyc[3:0]}; end endmodule module inst2 (/*AUTOARG*/ // Inputs cyc, i0, i1 ); /*verilator no_inline_module*/ // So we'll get a CELL under a GENFOR, without inlining input [31:0] cyc; input [1:0] i0; input [1:0] i1; initial begin if (cyc==32'h1) $write("[%0t] i0=%d i1=%d\n", $time, i0, i1); end endmodule verilator-4.038/test_regress/t/t_mod_interface_array1.v0000664000177100017500000000263513702133370023265 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 parameter N = 4; interface a_if #(parameter PARAM = 0) (); logic long_name; modport source (output long_name); modport sink (input long_name); endinterface module intf_source ( input logic [N-1:0] intf_input, a_if.source i_intf_source[N-1:0] ); generate for (genvar i=0; i < N;i++) begin assign i_intf_source[i].long_name = intf_input[i]; end endgenerate endmodule module intf_sink ( output [N-1:0] a_out, a_if.sink i_intf_sink[N-1:0] ); generate for (genvar i=0; i < N;i++) begin assign a_out[i] = i_intf_sink[i].long_name; end endgenerate endmodule module t ( clk ); input clk; logic [N-1:0] a_in; logic [N-1:0] a_out; logic [N-1:0] ack_out; // verilator lint_off LITENDIAN a_if #(.PARAM(1)) tl_intf [N] (); // verilator lint_on LITENDIAN intf_source source(a_in, tl_intf); intf_sink sink(a_out, tl_intf); initial a_in = '0; always @(posedge clk) begin a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; if (ack_out != a_out) begin $stop; end if (& a_in) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_var_ref_bad2.pl0000775000177100017500000000107413702133370021670 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_unpacked2.out0000664000177100017500000000101413702133370023017 0ustar wsnyderwsnyder%Warning-UNPACKED: t/t_struct_unpacked2.v:10:13: Unsupported: Unpacked array in packed struct/union (struct/union converted to unpacked) 10 | int b [2]; | ^ ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message. %Warning-UNPACKED: t/t_struct_unpacked2.v:9:12: Unsupported: Unpacked struct/union : ... In instance x 9 | typedef struct { | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_numones.v0000664000177100017500000000210613702133370021677 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [31:0] r32; wire [3:0] w4; wire [4:0] w5; assign w4 = NUMONES_8 ( r32[7:0] ); assign w5 = NUMONES_16( r32[15:0] ); function [3:0] NUMONES_8; input [7:0] i8; reg [7:0] i8; begin NUMONES_8 = 4'b1; end endfunction // NUMONES_8 function [4:0] NUMONES_16; input [15:0] i16; reg [15:0] i16; begin NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] )); end endfunction integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin r32 <= 32'h12345678; end if (cyc==2) begin if (w4 !== 1) $stop; if (w5 !== 2) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_math_msvc_64.pl0000775000177100017500000000115513702133370021646 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--compiler msvc"], # Bug requires msvc ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_implicit_def_bad.pl0000775000177100017500000000120113702133370023630 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_large_methods.v0000664000177100017500000000245713702133370023052 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef enum { E01 = 'h1, ELARGE = 'hf00d } my_t; integer cyc=0; my_t e; string all; // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup e <= E01; end else if (cyc==1) begin `checks(e.name, "E01"); `checkh(e.next, ELARGE); e <= ELARGE; end else if (cyc==3) begin `checks(e.name, "ELARGE"); `checkh(e.next, E01); `checkh(e.prev, E01); e <= E01; end else if (cyc==20) begin e <= 'h11; // Unknown end else if (cyc==20) begin `checks(e.name, ""); // Unknown end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_math_real.pl0000775000177100017500000000105313702133370021305 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_embed1.v0000664000177100017500000000630213702133370020337 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire bit_in = crc[0]; wire [30:0] vec_in = crc[31:1]; wire [123:0] wide_in = {crc[59:0],~crc[63:0]}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire exp_bit_out; // From reference of t_embed1_child.v wire exp_did_init_out; // From reference of t_embed1_child.v wire [30:0] exp_vec_out; // From reference of t_embed1_child.v wire [123:0] exp_wide_out; // From reference of t_embed1_child.v wire got_bit_out; // From test of t_embed1_wrap.v wire got_did_init_out; // From test of t_embed1_wrap.v wire [30:0] got_vec_out; // From test of t_embed1_wrap.v wire [123:0] got_wide_out; // From test of t_embed1_wrap.v // End of automatics // A non-embedded master /* t_embed1_child AUTO_TEMPLATE( .\(.*_out\) (exp_\1[]), .is_ref (1'b1)); */ t_embed1_child reference (/*AUTOINST*/ // Outputs .bit_out (exp_bit_out), // Templated .vec_out (exp_vec_out[30:0]), // Templated .wide_out (exp_wide_out[123:0]), // Templated .did_init_out (exp_did_init_out), // Templated // Inputs .clk (clk), .bit_in (bit_in), .vec_in (vec_in[30:0]), .wide_in (wide_in[123:0]), .is_ref (1'b1)); // Templated // The embeded comparison /* t_embed1_wrap AUTO_TEMPLATE( .\(.*_out\) (got_\1[]), .is_ref (1'b0)); */ t_embed1_wrap test (/*AUTOINST*/ // Outputs .bit_out (got_bit_out), // Templated .vec_out (got_vec_out[30:0]), // Templated .wide_out (got_wide_out[123:0]), // Templated .did_init_out (got_did_init_out), // Templated // Inputs .clk (clk), .bit_in (bit_in), .vec_in (vec_in[30:0]), .wide_in (wide_in[123:0]), .is_ref (1'b0)); // Templated // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, got_wide_out !== exp_wide_out, got_vec_out !== exp_vec_out, got_bit_out !== exp_bit_out, got_did_init_out !== exp_did_init_out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n",$time, cyc, crc, result, got_vec_out, exp_vec_out); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin end else if (cyc<90) begin if (result != 64'h0) begin $display("Bit mismatch, result=%x\n", result); $stop; end end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; //Child prints this: $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_func_dotted_inl2_vlt.pl0000775000177100017500000000165113702133370023464 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_func_dotted.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( v_flags2 => ["t/t_func_dotted_inl2.vlt",], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_hierarchy_unnamed.v0000664000177100017500000000067613702133370022677 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Chandan Egbert. // SPDX-License-Identifier: CC0-1.0 module sub(); endmodule module t(input logic a, input logic b, output logic x, output logic y); always_comb begin integer i; x = a; end sub u0(); always_comb begin integer j; y = b; end endmodule verilator-4.038/test_regress/t/t_sys_readmem_b.mem0000664000177100017500000000067313702133370022331 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # SRecord style comment 010 0_1_1 100/*Space*/101// Space 110 111 @00_0_8 10000 @c 10100 10101 verilator-4.038/test_regress/t/t_math_real_public.pl0000775000177100017500000000112613702133370022644 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--cc --public'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_if_blk.v0000664000177100017500000000570713702133370021620 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. // SPDX-License-Identifier: CC0-1.0 // bug648 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] datai = crc[7:0]; wire enable = crc[8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [7:0] datao; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .datao (datao[7:0]), // Inputs .clk (clk), .datai (datai[7:0]), .enable (enable)); // Aggregate outputs into a single result vector wire [63:0] result = {56'h0, datao}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h9d550d82d38926fa if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule `define FAIL 1 module Nested ( input logic clk, input logic x, output logic y ); logic t; always_comb t = x ^ 1'b1; always_ff @(posedge clk) begin if (clk) y <= t; end endmodule module Test ( input logic clk, input logic [7:0] datai, input logic enable, output logic [7:0] datao ); // verilator lint_off BLKANDNBLK logic [7:0] datat; // verilator lint_on BLKANDNBLK for (genvar i = 0; i < 8; i++) begin if (i%4 != 3) begin `ifndef FAIL logic t; always_comb begin t = datai[i] ^ 1'b1; end always_ff @(posedge clk) begin if (clk) datat[i] <= t; end `else Nested nested_i ( .clk(clk), .x(datai[i]), .y(datat[i]) //<== via Vcellout wire ); `endif always_comb begin casez (enable) 1'b1: datao[i] = datat[i]; 1'b0: datao[i] = '0; default: datao[i] = 'x; endcase end end else begin always_ff @(posedge clk) begin if (clk) datat[i] <= 0; //<== assign delayed end always_comb begin casez (enable) 1'b1: datao[i] = datat[i] ^ 1'b1; 1'b0: datao[i] = '1; default: datao[i] = 'x; endcase end end end endmodule verilator-4.038/test_regress/t/t_inst_wideconst.v0000664000177100017500000000227213702133370022240 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [41:0] aaa; wire [41:0] bbb; // verilator public_module wire [41:0] z_0; wire [41:0] z_1; wide w_0( .xxx( { {40{1'b0}},2'b11 } ), .yyy( aaa[1:0] ), .zzz( z_0 ) ); wide w_1( .xxx( aaa ), .yyy( 2'b10 ), .zzz( z_1 ) ); assign bbb= z_0 + z_1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin aaa <= 42'b01; end if (cyc==2) begin aaa <= 42'b10; if (z_0 != 42'h4) $stop; if (z_1 != 42'h3) $stop; end if (cyc==3) begin if (z_0 != 42'h5) $stop; if (z_1 != 42'h4) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module wide ( input [41:0] xxx, input [1:0] yyy, output [41:0] zzz ); // verilator public_module assign zzz = xxx+ { {40{1'b0}},yyy }; endmodule verilator-4.038/test_regress/t/t_inst_array_inl1.pl0000775000177100017500000000117413702133370022453 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_array.v"); compile( v_flags2 => ['+define+USE_INLINE',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_modport.v0000664000177100017500000000621613702133370022712 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface counter_if; logic [3:0] value; logic reset; modport counter_mp (input reset, output value); modport core_mp (output reset, input value); endinterface // Check can have inst module before top module module counter_ansi ( input clkm, counter_if c_data, input logic [3:0] i_value ); always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_ansi module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; counter_if c1_data(); counter_if c2_data(); counter_if c3_data(); counter_if c4_data(); counter_ansi c1 (.clkm(clk), .c_data(c1_data.counter_mp), .i_value(4'h1)); `ifdef VERILATOR counter_ansi `else counter_nansi `endif /**/ c2 (.clkm(clk), .c_data(c2_data.counter_mp), .i_value(4'h2)); counter_ansi_m c3 (.clkm(clk), .c_data(c3_data), .i_value(4'h3)); `ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif /**/ c4 (.clkm(clk), .c_data(c4_data), .i_value(4'h4)); initial begin c1_data.value = 4'h4; c2_data.value = 4'h5; c3_data.value = 4'h6; c4_data.value = 4'h7; end always @ (posedge clk) begin cyc <= cyc + 1; if (cyc<2) begin c1_data.reset <= 1; c2_data.reset <= 1; c3_data.reset <= 1; c4_data.reset <= 1; end if (cyc==2) begin c1_data.reset <= 0; c2_data.reset <= 0; c3_data.reset <= 0; c4_data.reset <= 0; end if (cyc==20) begin $write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc, c1_data.value, c1_data.reset, c2_data.value, c2_data.reset, c3_data.value, c3_data.reset, c4_data.value, c4_data.reset); if (c1_data.value != 2) $stop; if (c2_data.value != 3) $stop; if (c3_data.value != 4) $stop; if (c4_data.value != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule `ifndef VERILATOR // non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. module counter_nansi (clkm, c_data, i_value); input clkm; counter_if c_data; input logic [3:0] i_value; always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_nansi `endif module counter_ansi_m ( input clkm, counter_if.counter_mp c_data, input logic [3:0] i_value ); always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_ansi_m `ifndef VERILATOR // non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. module counter_nansi_m (clkm, c_data, i_value); input clkm; counter_if.counter_mp c_data; input logic [3:0] i_value; always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_nansi_m `endif verilator-4.038/test_regress/t/t_sv_bus_mux_demux.v0000664000177100017500000001644213702133370022604 0ustar wsnyderwsnyder//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // // // This testbench contains a bus source and a bus drain. The source creates // // address and data bus values, while the drain is the final destination of // // such pairs. All source and drain transfers are logged into memories, which // // are used at the end of simulation to check for data transfer correctness. // // Inside the RLT wrapper there is a multiplexer and a demultiplexer, they // // bus transfers into a 8bit data stream and back. Both stream input and // // output are exposed, they are connected together into a loopback. // // // // ----------- --------------------- // // | bso_mem | | wrap | // // ----------- | | // // ----------- | | ----------- | // // | bsi src | ------------> | -> | mux | -> | -> - sto // // ----------- | ----------- | \ // // | | | loopback // // ----------- | ----------- | / // // | bso drn | <------------ | <- | demux | <- | <- - sti // // ----------- | | ----------- | // // ----------- | | // // | bso_mem | | | // // ----------- --------------------- // // // // PROTOCOL: // // // // The 'vld' signal is driven by the source to indicate valid data is // // available, 'rdy' is used by the drain to indicate is is ready to accept // // valid data. A data transfer only happens if both 'vld' & 'rdy' are active. // // // //////////////////////////////////////////////////////////////////////////////// `timescale 1ns/1ps // include RTL files `include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv" `include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv" `include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv" `include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv" module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter SIZ = 10; // system signals //logic clk = 1'b1; // clock logic rst = 1'b1; // reset integer rst_cnt = 0; // input bus logic bsi_vld; // valid (chip select) logic [31:0] bsi_adr; // address logic [31:0] bsi_dat; // data logic bsi_rdy; // ready (acknowledge) logic bsi_trn; // data transfer logic [31:0] bsi_mem [SIZ]; // output stream logic sto_vld; // valid (chip select) logic [7:0] sto_bus; // data bus logic sto_rdy; // ready (acknowledge) // input stream logic sti_vld; // valid (chip select) logic [7:0] sti_bus; // data bus logic sti_rdy; // ready (acknowledge) // output bus logic bso_vld; // valid (chip select) logic [31:0] bso_adr; // address logic [31:0] bso_dat; // data logic bso_rdy; // ready (acknowledge) logic bso_trn; // data transfer logic [31:0] bso_mem [SIZ]; integer bso_cnt = 0; //////////////////////////////////////////////////////////////////////////////// // clock and reset //////////////////////////////////////////////////////////////////////////////// // clock toggling //always #5 clk = ~clk; // reset is removed after a delay always @ (posedge clk) begin rst_cnt <= rst_cnt + 1; rst <= rst_cnt <= 3; end // reset is removed after a delay always @ (posedge clk) if (bso_cnt == SIZ) begin if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end else begin $display ("FAILED"); $stop(); end end //////////////////////////////////////////////////////////////////////////////// // input data generator //////////////////////////////////////////////////////////////////////////////// // input data transfer assign bsi_trn = bsi_vld & bsi_rdy; // valid (for SIZ transfers) always @ (posedge clk, posedge rst) if (rst) bsi_vld = 1'b0; else bsi_vld = (bsi_adr < SIZ); // address (increments every transfer) always @ (posedge clk, posedge rst) if (rst) bsi_adr <= 32'h00000000; else if (bsi_trn) bsi_adr <= bsi_adr + 'd1; // data (new random value generated after every transfer) always @ (posedge clk, posedge rst) if (rst) bsi_dat <= 32'h00000000; else if (bsi_trn) bsi_dat <= $random(); // storing transferred data into memory for final check always @ (posedge clk) if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat; //////////////////////////////////////////////////////////////////////////////// // RTL instance //////////////////////////////////////////////////////////////////////////////// sv_bus_mux_demux_wrap wrap ( // system signals .clk (clk), .rst (rst), // input bus .bsi_vld (bsi_vld), .bsi_adr (bsi_adr), .bsi_dat (bsi_dat), .bsi_rdy (bsi_rdy), // output stream .sto_vld (sto_vld), .sto_bus (sto_bus), .sto_rdy (sto_rdy), // input stream .sti_vld (sti_vld), .sti_bus (sti_bus), .sti_rdy (sti_rdy), // output bus .bso_vld (bso_vld), .bso_adr (bso_adr), .bso_dat (bso_dat), .bso_rdy (bso_rdy) ); // stream output from mux is looped back into stream input for demux assign sti_vld = sto_vld; assign sti_bus = sto_bus; assign sto_rdy = sti_rdy; //////////////////////////////////////////////////////////////////////////////// // output data monitor //////////////////////////////////////////////////////////////////////////////// // input data transfer assign bso_trn = bso_vld & bso_rdy; // output transfer counter used to end the test always @ (posedge clk, posedge rst) if (rst) bso_cnt <= 0; else if (bso_trn) bso_cnt <= bso_cnt + 1; // storing transferred data into memory for final check always @ (posedge clk) if (bso_trn) bso_mem [bso_adr] <= bso_dat; // every output transfer against expected value stored in memory always @ (posedge clk) if (bso_trn && (bsi_mem [bso_adr] !== bso_dat)) $display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat); // ready is active for SIZ transfers always @ (posedge clk, posedge rst) if (rst) bso_rdy = 1'b0; else bso_rdy = 1'b1; endmodule verilator-4.038/test_regress/t/t_altera_lpm_ram_io.pl0000775000177100017500000000120613702133367023025 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_protect_ids_bad.v0000664000177100017500000000037013702133370022326 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); endmodule verilator-4.038/test_regress/t/t_dpi_context.pl0000775000177100017500000000112613702133370021672 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["t/t_dpi_context_c.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_implicit.pl0000775000177100017500000000105213702133370022210 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( verilator_flags2 => ["-Wno-IMPLICIT"], ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_skipidentical.v0000664000177100017500000000037113702133370023016 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); endmodule verilator-4.038/test_regress/t/t_fork_func2_bad.pl0000775000177100017500000000114513702133370022217 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ['--lint-only'], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_itemwidth.pl0000775000177100017500000000105313702133367022350 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_input_type.pl0000775000177100017500000000256113702133370023243 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if ($Self->{nc}) { # For NC, compile twice, first just to generate DPI headers compile( nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] ); } compile( v_flags2 => ["t/t_dpi_arg_input_type.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], # NC: Gdd the obj_dir to the C include path nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", "-ccflags -I$Self->{obj_dir}"], ); if ($Self->{vlt_all}) { files_identical( "$Self->{obj_dir}/Vt_dpi_arg_input_type__Dpi.h", "t/t_dpi_arg_input_type__Dpi.out" ); } execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ms_pli => 0 ); ok(1); 1; verilator-4.038/test_regress/t/t_class_unsup_bad.pl0000775000177100017500000000107113702133367022524 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex_fst.out0000664000177100017500000001012313702133370023241 0ustar wsnyderwsnyder$date Sun Apr 19 04:15:26 2020 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $var logic 2 # v_strp $end $var logic 4 $ v_strp_strp $end $var logic 2 % v_unip_strp $end $var logic 2 & v_arrp $end $var logic 4 ' v_arrp_arrp $end $var logic 4 ( v_arrp_strp $end $var logic 1 ) v_arru(1) $end $var logic 1 * v_arru(2) $end $var logic 1 + v_arru_arru(3)(1) $end $var logic 1 , v_arru_arru(3)(2) $end $var logic 1 - v_arru_arru(4)(1) $end $var logic 1 . v_arru_arru(4)(2) $end $var logic 2 / v_arru_arrp(3) $end $var logic 2 0 v_arru_arrp(4) $end $var logic 2 1 v_arru_strp(3) $end $var logic 2 2 v_arru_strp(4) $end $var real 64 3 v_real $end $var real 64 4 v_arr_real(0) $end $var real 64 5 v_arr_real(1) $end $var logic 64 6 v_str32x2 $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var logic 32 7 v_enumed $end $attrbegin misc 07 "" 1 $end $var logic 32 8 v_enumed2 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 9 v_enumb $end $var logic 6 : v_enumb2_str $end $var logic 8 ; unpacked_array(-2) $end $var logic 8 < unpacked_array(-1) $end $var logic 8 = unpacked_array(0) $end $scope module unnamedblk1 $end $var integer 32 > b $end $scope module unnamedblk2 $end $var integer 32 ? a $end $upscope $end $upscope $end $scope module p2 $end $var parameter 32 @ PARAM $end $upscope $end $scope module p3 $end $var parameter 32 A PARAM $end $upscope $end $upscope $end $scope module $unit $end $var bit 1 B global_bit $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000000000000000000000000000000 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( 0) 0* 0+ 0, 0- 0. b00 / b00 0 b00 1 b00 2 r0 3 r0 4 r0 5 b0000000000000000000000000000000000000000000000000000000011111111 6 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 b000 9 b000000 : b00000000 ; b00000000 < b00000000 = b00000000000000000000000000000000 > b00000000000000000000000000000000 ? b00000000000000000000000000000010 @ b00000000000000000000000000000011 A 1B #10 b00000000000000000000000000000101 ? b00000000000000000000000000000101 > b111 9 b00000000000000000000000000000010 8 b00000000000000000000000000000001 7 b0000000000000000000000000000000100000000000000000000000011111110 6 r0.3 5 r0.2 4 r0.1 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000001 " 1! #15 0! #20 1! b00000000000000000000000000000010 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.2 3 r0.4 4 r0.6 5 b0000000000000000000000000000001000000000000000000000000011111101 6 b00000000000000000000000000000010 7 b00000000000000000000000000000100 8 b110 9 b111111 : #25 0! #30 1! b110110 : b101 9 b00000000000000000000000000000110 8 b00000000000000000000000000000011 7 b0000000000000000000000000000001100000000000000000000000011111100 6 r0.8999999999999999 5 r0.6000000000000001 4 r0.3 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000011 " #35 0! #40 1! b00000000000000000000000000000100 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.4 3 r0.8 4 r1.2 5 b0000000000000000000000000000010000000000000000000000000011111011 6 b00000000000000000000000000000100 7 b00000000000000000000000000001000 8 b100 9 b101101 : #45 0! #50 1! b100100 : b011 9 b00000000000000000000000000001010 8 b00000000000000000000000000000101 7 b0000000000000000000000000000010100000000000000000000000011111010 6 r1.5 5 r1 4 r0.5 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000101 " #55 0! #60 1! b00000000000000000000000000000110 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.6 3 r1.2 4 r1.8 5 b0000000000000000000000000000011000000000000000000000000011111001 6 b00000000000000000000000000000110 7 b00000000000000000000000000001100 8 b010 9 b011011 : verilator-4.038/test_regress/t/t_interface_param_acc_bits.pl0000775000177100017500000000115013702133370024316 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, # Unsupported bug1523 expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_type_bad.out0000664000177100017500000000031113702133370022505 0ustar wsnyderwsnyder%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting TYPE-IDENTIFIER 9 | localparam type bad2 = 2; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_class_module.v0000664000177100017500000000110713702133367021660 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); class Cls; int imembera; int imemberb; endclass : Cls class Dead; endclass initial begin Cls c; if (c != null) $stop; c = new; c.imembera = 10; c.imemberb = 20; if (c.imembera != 10) $stop; if (c.imemberb != 20) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_ref_bad3.out0000664000177100017500000000033513702133370022061 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_var_ref_bad3.v:10:18: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' 10 | module t(ref int bad_primary_ref | ^~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_unbounded.pl0000775000177100017500000000106013702133370021332 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex_params.out0000664000177100017500000001017613702133370023740 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Tue Jan 21 18:15:28 2020 $end $timescale 1ps $end $scope module top $end $var wire 1 7" clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module t $end $var wire 1 7" clk $end $var wire 32 + cyc [31:0] $end $var wire 8 p" unpacked_array(-1) [7:0] $end $var wire 8 o" unpacked_array(-2) [7:0] $end $var wire 8 q" unpacked_array(0) [7:0] $end $var real 64 E! v_arr_real(0) $end $var real 64 G! v_arr_real(1) $end $var wire 2 [ v_arrp [2:1] $end $var wire 4 c v_arrp_arrp [3:0] $end $var wire 4 k v_arrp_strp [3:0] $end $var wire 1 ?" v_arru(1) $end $var wire 1 @" v_arru(2) $end $var wire 2 s v_arru_arrp(3) [2:1] $end $var wire 2 t v_arru_arrp(4) [2:1] $end $var wire 1 O" v_arru_arru(3)(1) $end $var wire 1 W" v_arru_arru(3)(2) $end $var wire 1 _" v_arru_arru(4)(1) $end $var wire 1 g" v_arru_arru(4)(2) $end $var wire 2 %! v_arru_strp(3) [1:0] $end $var wire 2 -! v_arru_strp(4) [1:0] $end $var wire 3 u! v_enumb [2:0] $end $var wire 6 }! v_enumb2_str [5:0] $end $var wire 32 e! v_enumed [31:0] $end $var wire 32 m! v_enumed2 [31:0] $end $var real 64 5! v_real $end $var wire 64 3 v_str32x2 [63:0] $end $var wire 2 C v_strp [1:0] $end $var wire 4 K v_strp_strp [3:0] $end $var wire 2 S v_unip_strp [1:0] $end $scope module p2 $end $var wire 32 )# PARAM [31:0] $end $upscope $end $scope module p3 $end $var wire 32 1# PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 '" b [31:0] $end $scope module unnamedblk2 $end $var wire 32 /" a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 + b0000000000000000000000000000000000000000000000000000000011111111 3 b00 C b0000 K b00 S b00 [ b0000 c b0000 k b00 s b00 t b00 %! b00 -! r0 5! r0 E! r0 G! b00000000000000000000000000000000 e! b00000000000000000000000000000000 m! b000 u! b000000 }! b00000000000000000000000000000000 '" b00000000000000000000000000000000 /" 07" 0?" 0@" 0O" 0W" 0_" 0g" b00000000 o" b00000000 p" b00000000 q" b00000000000000000000000000000010 )# b00000000000000000000000000000011 1# #10 b00000000000000000000000000000001 + b0000000000000000000000000000000100000000000000000000000011111110 3 b11 C b1111 K b11 S b11 [ b1111 c b1111 k b11 s b11 t b11 %! b11 -! r0.1 5! r0.2 E! r0.3 G! b00000000000000000000000000000001 e! b00000000000000000000000000000010 m! b111 u! b00000000000000000000000000000101 '" b00000000000000000000000000000101 /" 17" #15 07" #20 b00000000000000000000000000000010 + b0000000000000000000000000000001000000000000000000000000011111101 3 b00 C b0000 K b00 S b00 [ b0000 c b0000 k b00 s b00 t b00 %! b00 -! r0.2 5! r0.4 E! r0.6 G! b00000000000000000000000000000010 e! b00000000000000000000000000000100 m! b110 u! b111111 }! 17" #25 07" #30 b00000000000000000000000000000011 + b0000000000000000000000000000001100000000000000000000000011111100 3 b11 C b1111 K b11 S b11 [ b1111 c b1111 k b11 s b11 t b11 %! b11 -! r0.3 5! r0.6000000000000001 E! r0.8999999999999999 G! b00000000000000000000000000000011 e! b00000000000000000000000000000110 m! b101 u! b110110 }! 17" #35 07" #40 b00000000000000000000000000000100 + b0000000000000000000000000000010000000000000000000000000011111011 3 b00 C b0000 K b00 S b00 [ b0000 c b0000 k b00 s b00 t b00 %! b00 -! r0.4 5! r0.8 E! r1.2 G! b00000000000000000000000000000100 e! b00000000000000000000000000001000 m! b100 u! b101101 }! 17" #45 07" #50 b00000000000000000000000000000101 + b0000000000000000000000000000010100000000000000000000000011111010 3 b11 C b1111 K b11 S b11 [ b1111 c b1111 k b11 s b11 t b11 %! b11 -! r0.5 5! r1 E! r1.5 G! b00000000000000000000000000000101 e! b00000000000000000000000000001010 m! b011 u! b100100 }! 17" #55 07" #60 b00000000000000000000000000000110 + b0000000000000000000000000000011000000000000000000000000011111001 3 b00 C b0000 K b00 S b00 [ b0000 c b0000 k b00 s b00 t b00 %! b00 -! r0.6 5! r1.2 E! r1.8 G! b00000000000000000000000000000110 e! b00000000000000000000000000001100 m! b010 u! b011011 }! 17" verilator-4.038/test_regress/t/t_pp_resetall_bad.pl0000775000177100017500000000114413702133370022472 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["-Wpedantic"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_string.out0000664000177100017500000000021413666032701022600 0ustar wsnyderwsnyderString: ' 1' foo(1): ' 1' s f(1): ' 1' s parm: ' 1' s strg: ' 1' r: 1.234 *-* All Finished *-* verilator-4.038/test_regress/t/t_pli_bbox.pl0000775000177100017500000000110113702133370021141 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_pli_bad.v"); lint( verilator_flags2 => ["--bbox-sys"], ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_litendian.v0000664000177100017500000000434213702133370022331 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t #( parameter [0:7] P = 8'd10 )(/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; localparam [0:7] Q = 8'd20; logic [ 0: 0] v_a = '0; logic [ 0: 1] v_b = '0; logic [ 0: 7] v_c = '0; logic [ 0: 8] v_d = '0; logic [ 0: 15] v_e = '0; logic [ 0: 16] v_f = '0; logic [ 0: 31] v_g = '0; logic [ 0: 32] v_h = '0; logic [ 0: 63] v_i = '0; logic [ 0: 64] v_j = '0; logic [ 0:127] v_k = '0; logic [ 0:128] v_l = '0; logic [ 0:255] v_m = '0; logic [ 0:256] v_n = '0; logic [ 0:511] v_o = '0; logic [ -1: 1] v_p = '0; logic [ -7: 7] v_q = '0; logic [ -15: 15] v_r = '0; logic [ -31: 31] v_s = '0; logic [ -63: 63] v_t = '0; logic [-127:127] v_u = '0; logic [-255:255] v_v = '0; always @(posedge clk) begin if (cyc == 0) begin v_a <= '1; v_b <= '1; v_c <= '1; v_d <= '1; v_e <= '1; v_f <= '1; v_g <= '1; v_h <= '1; v_i <= '1; v_j <= '1; v_k <= '1; v_l <= '1; v_m <= '1; v_n <= '1; v_o <= '1; v_p <= '1; v_q <= '1; v_r <= '1; v_s <= '1; v_t <= '1; v_u <= '1; v_v <= '1; end else begin v_a <= v_a << 1; v_b <= v_b << 1; v_c <= v_c << 1; v_d <= v_d << 1; v_e <= v_e << 1; v_f <= v_f << 1; v_g <= v_g << 1; v_h <= v_h << 1; v_i <= v_i << 1; v_j <= v_j << 1; v_k <= v_k << 1; v_l <= v_l << 1; v_m <= v_m << 1; v_n <= v_n << 1; v_o <= v_o << 1; v_p <= v_p << 1; v_q <= v_q << 1; v_r <= v_r << 1; v_s <= v_s << 1; v_t <= v_t << 1; v_u <= v_u << 1; v_v <= v_v << 1; end cyc <= cyc + 1; if (cyc == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_var_in_assign.pl0000775000177100017500000000105313702133370022173 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_runflag_seed.pl0000775000177100017500000000127013702133370022010 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( ); execute( all_run_flags => ["+verilator+seed+5 +SEED=fffffff4"], fails => 0, ); execute( all_run_flags => ["+verilator+seed+6 +SEED=fffffff2"], fails => 0, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_basic.pl0000775000177100017500000000116413702133367022024 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_real2.pl0000775000177100017500000000105313702133370021536 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can predistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_negative.pl0000775000177100017500000000105313702133370022512 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_woff_bad.out0000664000177100017500000000007213702133370022302 0ustar wsnyderwsnyder%Error: Unknown warning specified: -Wno-NOSUCHERRORASTHIS verilator-4.038/test_regress/t/t_display_mcd.out0000664000177100017500000000005113650310376022034 0ustar wsnyderwsnyderTo stdout To stderr *-* All Finished *-* verilator-4.038/test_regress/t/t_flag_language_bad.pl0000775000177100017500000000107013702133370022732 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ['--language 1-2-3-4'], fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_cover_toggle.pl0000775000177100017500000000143413702133370022033 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--cc --coverage-toggle --stats'], ); execute( check_finished => 1, ); # Read the input .v file and do any CHECK_COVER requests inline_checks(); file_grep($Self->{stats}, qr/Coverage, Toggle points joined\s+(\d+)/i, 25) if $Self->{vlt_all}; ok(1); 1; verilator-4.038/test_regress/t/t_a1_first_cc.pl0000775000177100017500000000163613702133367021543 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # show-config: This test runs the very first time we've executed Verilator # after building so we make sure to run with --gdbbt, so if it dumps we'll # get a trace. scenarios(simulator => 1); $DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree"; run(cmd => ["perl", "../bin/verilator", $DEBUG_QUIET, "-V"], verilator_run => 1, ); compile( verilator_flags2 => [$DEBUG_QUIET, "--trace"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_sc_ns.pl0000775000177100017500000000141313702133370021474 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_time_sc.v"); $Self->{sc_time_resolution} = 'SC_NS'; compile( verilator_flags2 => ['-sc', '-timescale 1ns/1ns', '+define+TEST_EXPECT=20ns'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_gate_bufif0.pl0000775000177100017500000000142113702133370022401 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_tri_gate.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ['+define+T_BUFIF0',], make_flags => 'CPPFLAGS_ADD=-DT_BUFIF0', verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_elab_bad.pl0000775000177100017500000000161313702133367022453 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_elab.v"); unlink("$Self->{obj_dir}/t_assert_elab_bad.log"); compile( v_flags2 => ['+define+FAILING_ASSERTIONS', $Self->{vlt_all} ? '--assert' : ($Self->{nc} ? '+assert':'')], fails => 1, ); execute( fails => $Self->{vlt_all}, ); file_grep("$Self->{obj_dir}/vlt_compile.log", qr/%Warning-USERFATAL: "Parameter 5 is invalid...string and constant both work"/); ok(1); 1; verilator-4.038/test_regress/t/t_array_list_bad.pl0000775000177100017500000000107413702133367022341 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dynarray.pl0000775000177100017500000000105313702133370021202 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_longname.pl0000775000177100017500000000105313702133370022010 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_circ_subst_bad.pl0000775000177100017500000000107413702133370023021 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_param_acc_bits.v0000664000177100017500000000100513702133370024144 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 // bug1593 interface simple_bus #(PARAMETER = 0); parameter [6:0] dummy = 22; endinterface module t (); simple_bus sb_intf(); simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); initial begin if (simple.PARAMETER != 7) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_unsup_deassign.v0000664000177100017500000000054613702133370023263 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire rst ); integer q; always @(*) if (rst) assign q = 0; else deassign q; endmodule verilator-4.038/test_regress/t/t_verilated_all_newest.pl0000775000177100017500000000153313702133370023550 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_verilated_all.v"); my $root = ".."; compile( # Can't use --coverage and --savable together, so cheat and compile inline verilator_flags2 => ["--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi $root/include/verilated_save.cpp"], make_flags => 'DRIVER_STD=newest', ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_question.pl0000775000177100017500000000112613702133367022610 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_xml_output.out0000664000177100017500000000166413702133370021772 0ustar wsnyderwsnyder verilator-4.038/test_regress/t/t_vlcov_info.pl0000775000177100017500000000153413702133370021521 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); run(cmd => ["../bin/verilator_coverage", "--write-info", "$Self->{obj_dir}/coverage.info", "t/t_vlcov_data_a.dat", "t/t_vlcov_data_b.dat", "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat", ], verilator_run => 1, ); files_identical("$Self->{obj_dir}/coverage.info", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_gate_ormux.v0000775000177100017500000002670313702133370021366 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; logic [31:0] rdata; logic [31:0] rdata2; wire [31:0] wdata = crc[31:0]; wire [15:0] sel = {11'h0, crc[36:32]}; wire we = crc[48]; Test test (/*AUTOINST*/ // Outputs .rdata (rdata[31:0]), .rdata2 (rdata2[31:0]), // Inputs .clk (clk), .we (we), .sel (sel[15:0]), .wdata (wdata[31:0])); // 5.07 4.42 -> 13% wire [63:0] result = {rdata2, rdata}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (rdata2 != rdata) $stop; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h8977713eb467bc86 if (sum !== `EXPECTED_SUM) $stop; end else if (cyc == `SIM_CYCLES) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs rdata, rdata2, // Inputs clk, we, sel, wdata ); input clk; input we; input [15:0] sel; input [31:0] wdata; output logic [31:0] rdata; output logic [31:0] rdata2; logic we_d1r; logic [15:0] sel_d1r; logic [31:0] wdata_d1r; always_ff @ (posedge clk) begin we_d1r <= we; sel_d1r <= sel; wdata_d1r <= wdata; end reg [31:0] csr0000; reg [31:0] csr0001; reg [31:0] csr0002; reg [31:0] csr0003; reg [31:0] csr0004; reg [31:0] csr0005; reg [31:0] csr0006; reg [31:0] csr0007; reg [31:0] csr0008; reg [31:0] csr0009; reg [31:0] csr000a; reg [31:0] csr000b; reg [31:0] csr000c; reg [31:0] csr000d; reg [31:0] csr000e; reg [31:0] csr000f; wire [31:0] csr0010 = 32'h33675230; wire [31:0] csr0011 = 32'h00fa2144; wire [31:0] csr0012 = 32'h6a5e8e10; wire [31:0] csr0013 = 32'h000a5b5e; wire [31:0] csr0014 = 32'h002fe51b; wire [31:0] csr0015 = 32'h00027e00; wire [31:0] csr0016 = 32'h0000e3c0; wire [31:0] csr0017 = 32'h00efcf16; wire [31:0] csr0018 = 32'h007a2600; wire [31:0] csr0019 = 32'h0a4a9f10; wire [31:0] csr001a = 32'h7d789de3; wire [31:0] csr001b = 32'h40f655f9; wire [31:0] csr001c = 32'hadad01f4; wire [31:0] csr001d = 32'h02e7b33c; wire [31:0] csr001e = 32'h12101533; wire [31:0] csr001f = 32'h2cc1cce5; initial begin csr0000 = 32'he172d365; csr0001 = 32'h35cc25e2; csr0002 = 32'haf48436e; csr0003 = 32'h135e55e4; csr0004 = 32'h5fd6e48a; csr0005 = 32'hb07d34ad; csr0006 = 32'h2aa05deb; csr0007 = 32'hfe97b680; csr0008 = 32'h960f20bb; csr0009 = 32'h251129f0; csr000a = 32'hef3d2f93; csr000b = 32'hef4bc127; csr000c = 32'h3dfecb10; csr000d = 32'h1b4690f5; csr000e = 32'ha07822ab; csr000f = 32'hf817cbf6; end always_ff @ (posedge clk) begin if (we_d1r && sel_d1r == 16'h0000) csr0000 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0001) csr0001 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0002) csr0002 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0003) csr0003 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0004) csr0004 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0005) csr0005 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0006) csr0006 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0007) csr0007 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0008) csr0008 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0009) csr0009 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000a) csr000a <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000b) csr000b <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000c) csr000c <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000d) csr000d <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000e) csr000e <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000f) csr000f <= wdata_d1r; end wire dec0000 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0001 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0002 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0003 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0004 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0005 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0006 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0007 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0008 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0009 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec000a = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec000b = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec000c = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec000d = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec000e = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec000f = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0010 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0011 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0012 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0013 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0014 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0015 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0016 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0017 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0018 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0019 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec001a = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec001b = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec001c = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec001d = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec001e = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec001f = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; assign rdata = (32'h0 | {32{dec0000}} & csr0000 | {32{dec0001}} & csr0001 | {32{dec0002}} & csr0002 | {32{dec0003}} & csr0003 | {32{dec0004}} & csr0004 | {32{dec0005}} & csr0005 | {32{dec0006}} & csr0006 | {32{dec0007}} & csr0007 | {32{dec0008}} & csr0008 | {32{dec0009}} & csr0009 | {32{dec000a}} & csr000a | {32{dec000b}} & csr000b | {32{dec000c}} & csr000c | {32{dec000d}} & csr000d | {32{dec000e}} & csr000e | {32{dec000f}} & csr000f | {32{dec0010}} & csr0010 | {32{dec0011}} & csr0011 | {32{dec0012}} & csr0012 | {32{dec0013}} & csr0013 | {32{dec0014}} & csr0014 | {32{dec0015}} & csr0015 | {32{dec0016}} & csr0016 | {32{dec0017}} & csr0017 | {32{dec0018}} & csr0018 | {32{dec0019}} & csr0019 | {32{dec001a}} & csr001a | {32{dec001b}} & csr001b | {32{dec001c}} & csr001c | {32{dec001d}} & csr001d | {32{dec001e}} & csr001e | {32{dec001f}} & csr001f ); always_comb begin case (sel_d1r) 16'h0000: rdata2 = csr0000; 16'h0001: rdata2 = csr0001; 16'h0002: rdata2 = csr0002; 16'h0003: rdata2 = csr0003; 16'h0004: rdata2 = csr0004; 16'h0005: rdata2 = csr0005; 16'h0006: rdata2 = csr0006; 16'h0007: rdata2 = csr0007; 16'h0008: rdata2 = csr0008; 16'h0009: rdata2 = csr0009; 16'h000a: rdata2 = csr000a; 16'h000b: rdata2 = csr000b; 16'h000c: rdata2 = csr000c; 16'h000d: rdata2 = csr000d; 16'h000e: rdata2 = csr000e; 16'h000f: rdata2 = csr000f; 16'h0010: rdata2 = csr0010; 16'h0011: rdata2 = csr0011; 16'h0012: rdata2 = csr0012; 16'h0013: rdata2 = csr0013; 16'h0014: rdata2 = csr0014; 16'h0015: rdata2 = csr0015; 16'h0016: rdata2 = csr0016; 16'h0017: rdata2 = csr0017; 16'h0018: rdata2 = csr0018; 16'h0019: rdata2 = csr0019; 16'h001a: rdata2 = csr001a; 16'h001b: rdata2 = csr001b; 16'h001c: rdata2 = csr001c; 16'h001d: rdata2 = csr001d; 16'h001e: rdata2 = csr001e; 16'h001f: rdata2 = csr001f; default: rdata2 = 0; endcase end endmodule verilator-4.038/test_regress/t/t_var_assign_landr.pl0000775000177100017500000000105313702133370022665 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unroll_signed.pl0000775000177100017500000000105313702133370022215 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_event.v0000664000177100017500000000336513702133370020331 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif module t(/*AUTOARG*/ // Inputs clk ); input clk; event e1; event e2; `ifndef IVERILOG event ev [3:0]; `endif int cyc; int last_event; always @(e1) begin `WRITE_VERBOSE(("[%0t] e1\n", $time)); if (!e1.triggered) $stop; last_event[1] = 1; end always @(e2) begin `WRITE_VERBOSE(("[%0t] e2\n", $time)); last_event[2] = 1; end always @(posedge clk) begin `WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event)); cyc <= cyc + 1; if (cyc == 1) begin // Check no initial trigger if (last_event != 0) $stop; end // else if (cyc == 10) begin last_event = 0; -> e1; end else if (cyc == 12) begin if (last_event != 32'b10) $stop; last_event = 0; end else if (cyc == 13) begin // Check not still triggering if (last_event != 0) $stop; last_event = 0; end // else if (cyc == 10) begin last_event = 0; ->> e2; end else if (cyc == 12) begin if (last_event != 32'b100) $stop; last_event = 0; end else if (cyc == 13) begin // Check not still triggering if (last_event != 0) $stop; last_event = 0; end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_enum_recurse_bad.out0000664000177100017500000000057213702133370023051 0ustar wsnyderwsnyder%Error: t/t_enum_recurse_bad.v:7:9: Recursive enum value: 'u' 7 | enum {u=u} e_t; | ^ %Error: t/t_enum_recurse_bad.v:7:9: Expecting expression to be constant, but variable isn't const: 'u' 7 | enum {u=u} e_t; | ^ %Error: t/t_enum_recurse_bad.v:7:9: Enum value isn't a constant 7 | enum {u=u} e_t; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_syncasyncnet_bad.v0000664000177100017500000000507513702133370023565 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs rst_sync_l, rst_both_l, rst_async_l, d, clk ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input clk; // To sub1 of sub1.v, ... input d; // To sub1 of sub1.v, ... input rst_async_l; // To sub2 of sub2.v input rst_both_l; // To sub1 of sub1.v, ... input rst_sync_l; // To sub1 of sub1.v // End of automatics sub1 sub1 (/*AUTOINST*/ // Inputs .clk (clk), .rst_both_l (rst_both_l), .rst_sync_l (rst_sync_l), .d (d)); sub2 sub2 (/*AUTOINST*/ // Inputs .clk (clk), .rst_both_l (rst_both_l), .rst_async_l (rst_async_l), .d (d)); endmodule module sub1 (/*AUTOARG*/ // Inputs clk, rst_both_l, rst_sync_l, d ); input clk; input rst_both_l; input rst_sync_l; //input rst_async_l; input d; reg q1; reg q2; always @(posedge clk) begin if (~rst_sync_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops q1 <= 1'h0; // End of automatics end else begin q1 <= d; end end always @(posedge clk) begin q2 <= (rst_both_l) ? d : 1'b0; if (0 && q1 && q2) ; end endmodule module sub2 (/*AUTOARG*/ // Inputs clk, rst_both_l, rst_async_l, d ); input clk; input rst_both_l; //input rst_sync_l; input rst_async_l; input d; reg q1; reg q2; reg q3; always @(posedge clk or negedge rst_async_l) begin if (~rst_async_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops q1 <= 1'h0; // End of automatics end else begin q1 <= d; end end always @(posedge clk or negedge rst_both_l) begin q2 <= (~rst_both_l) ? 1'b0 : d; end // Make there be more async uses than sync uses always @(posedge clk or negedge rst_both_l) begin q3 <= (~rst_both_l) ? 1'b0 : d; if (0 && q1 && q2 && q3) ; end endmodule verilator-4.038/test_regress/t/t_pp_lib.pl0000775000177100017500000000112513702133370020616 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( v_flags2 => ['-v', 't/t_pp_lib_library.v'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_bound2.v0000664000177100017500000000433113702133370021732 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug823 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [6:0] in = crc[6:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] mask; // From test of Test.v wire [3:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[3:0]), .mask (mask[3:0]), // Inputs .clk (clk), .in (in[6:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out & mask}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4e9d3a74e9d3f656 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, mask, // Inputs clk, in ); input clk; input [6:0] in; // Note much wider than any index output reg [3:0] out; output reg [3:0] mask; localparam [15:5] p = 11'h1ac; always @(posedge clk) begin // verilator lint_off WIDTH out <= p[15 + in -: 5]; // verilator lint_on WIDTH mask[3] <= ((15 + in - 5) < 12); mask[2] <= ((15 + in - 5) < 13); mask[1] <= ((15 + in - 5) < 14); mask[0] <= ((15 + in - 5) < 15); end endmodule verilator-4.038/test_regress/t/t_trace_two_dump_sc.out0000664000177100017500000000261013702133370023243 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sun Mar 1 20:49:13 2020 $end $timescale 1ps $end $scope module topa $end $scope module t $end $var wire 32 3 c_trace_on [31:0] $end $var wire 1 # clk $end $var wire 32 + cyc [31:0] $end $scope module sub $end $var wire 32 ; inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 + b00000000000000000000000000000000 3 b00000000000000000000000000000001 ; #10000 1# b00000000000000000000000000000010 + b00000000000000000000000000000011 3 #15000 0# #20000 1# b00000000000000000000000000000011 + b00000000000000000000000000000100 3 #25000 0# #30000 1# b00000000000000000000000000000100 + b00000000000000000000000000000101 3 #35000 0# #40000 1# b00000000000000000000000000000101 + b00000000000000000000000000000110 3 #45000 0# #50000 1# b00000000000000000000000000000110 + b00000000000000000000000000000111 3 #55000 0# #60000 1# b00000000000000000000000000000111 + b00000000000000000000000000001000 3 #65000 0# #70000 1# b00000000000000000000000000001000 + b00000000000000000000000000001001 3 #75000 0# #80000 1# b00000000000000000000000000001001 + b00000000000000000000000000001010 3 #85000 0# #90000 1# b00000000000000000000000000001010 + b00000000000000000000000000001011 3 #95000 0# #100000 1# b00000000000000000000000000001011 + b00000000000000000000000000001100 3 verilator-4.038/test_regress/t/t_dpi_result_type__Dpi.out0000664000177100017500000001423013702133370023711 0ustar wsnyderwsnyder// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS // DPI export at t/t_dpi_result_type.v:393:24 extern svBitVecVal e_array_2_state_1(); // DPI export at t/t_dpi_result_type.v:400:24 extern svBitVecVal e_array_2_state_32(); // DPI export at t/t_dpi_result_type.v:284:17 extern svBit e_bit(); // DPI export at t/t_dpi_result_type.v:377:19 extern svBit e_bit_t(); // DPI export at t/t_dpi_result_type.v:206:18 extern char e_byte(); // DPI export at t/t_dpi_result_type.v:299:20 extern char e_byte_t(); // DPI export at t/t_dpi_result_type.v:212:27 extern unsigned char e_byte_unsigned(); // DPI export at t/t_dpi_result_type.v:305:29 extern unsigned char e_byte_unsigned_t(); // DPI export at t/t_dpi_result_type.v:270:21 extern void* e_chandle(); // DPI export at t/t_dpi_result_type.v:363:23 extern void* e_chandle_t(); // DPI export at t/t_dpi_result_type.v:230:17 extern int e_int(); // DPI export at t/t_dpi_result_type.v:323:19 extern int e_int_t(); // DPI export at t/t_dpi_result_type.v:236:26 extern unsigned int e_int_unsigned(); // DPI export at t/t_dpi_result_type.v:329:28 extern unsigned int e_int_unsigned_t(); // DPI export at t/t_dpi_result_type.v:291:19 extern svLogic e_logic(); // DPI export at t/t_dpi_result_type.v:384:21 extern svLogic e_logic_t(); // DPI export at t/t_dpi_result_type.v:242:21 extern long long e_longint(); // DPI export at t/t_dpi_result_type.v:335:23 extern long long e_longint_t(); // DPI export at t/t_dpi_result_type.v:248:30 extern unsigned long long e_longint_unsigned(); // DPI export at t/t_dpi_result_type.v:341:32 extern unsigned long long e_longint_unsigned_t(); // DPI export at t/t_dpi_result_type.v:255:18 extern double e_real(); // DPI export at t/t_dpi_result_type.v:348:20 extern double e_real_t(); // DPI export at t/t_dpi_result_type.v:218:22 extern short e_shortint(); // DPI export at t/t_dpi_result_type.v:311:24 extern short e_shortint_t(); // DPI export at t/t_dpi_result_type.v:224:31 extern unsigned short e_shortint_unsigned(); // DPI export at t/t_dpi_result_type.v:317:33 extern unsigned short e_shortint_unsigned_t(); // DPI export at t/t_dpi_result_type.v:277:20 extern const char* e_string(); // DPI export at t/t_dpi_result_type.v:370:22 extern const char* e_string_t(); // DPI export at t/t_dpi_result_type.v:410:30 extern svBitVecVal e_struct_2_state_1(); // DPI export at t/t_dpi_result_type.v:417:32 extern svBitVecVal e_struct_2_state_32(); // DPI export at t/t_dpi_result_type.v:425:29 extern svBitVecVal e_union_2_state_1(); // DPI export at t/t_dpi_result_type.v:432:30 extern svBitVecVal e_union_2_state_32(); // DPI export at t/t_dpi_result_type.v:200:18 extern void e_void(); // DPI IMPORTS // DPI import at t/t_dpi_result_type.v:443:41 extern void check_exports(); // DPI import at t/t_dpi_result_type.v:115:39 extern svBitVecVal i_array_2_state_1(); // DPI import at t/t_dpi_result_type.v:116:39 extern svBitVecVal i_array_2_state_32(); // DPI import at t/t_dpi_result_type.v:92:46 extern svBit i_bit(); // DPI import at t/t_dpi_result_type.v:110:48 extern svBit i_bit_t(); // DPI import at t/t_dpi_result_type.v:78:46 extern char i_byte(); // DPI import at t/t_dpi_result_type.v:96:48 extern char i_byte_t(); // DPI import at t/t_dpi_result_type.v:79:46 extern unsigned char i_byte_unsigned(); // DPI import at t/t_dpi_result_type.v:97:48 extern unsigned char i_byte_unsigned_t(); // DPI import at t/t_dpi_result_type.v:90:46 extern void* i_chandle(); // DPI import at t/t_dpi_result_type.v:108:48 extern void* i_chandle_t(); // DPI import at t/t_dpi_result_type.v:82:46 extern int i_int(); // DPI import at t/t_dpi_result_type.v:100:48 extern int i_int_t(); // DPI import at t/t_dpi_result_type.v:83:46 extern unsigned int i_int_unsigned(); // DPI import at t/t_dpi_result_type.v:101:48 extern unsigned int i_int_unsigned_t(); // DPI import at t/t_dpi_result_type.v:93:46 extern svLogic i_logic(); // DPI import at t/t_dpi_result_type.v:111:48 extern svLogic i_logic_t(); // DPI import at t/t_dpi_result_type.v:84:46 extern long long i_longint(); // DPI import at t/t_dpi_result_type.v:102:48 extern long long i_longint_t(); // DPI import at t/t_dpi_result_type.v:85:46 extern unsigned long long i_longint_unsigned(); // DPI import at t/t_dpi_result_type.v:103:48 extern unsigned long long i_longint_unsigned_t(); // DPI import at t/t_dpi_result_type.v:86:46 extern double i_real(); // DPI import at t/t_dpi_result_type.v:104:48 extern double i_real_t(); // DPI import at t/t_dpi_result_type.v:80:46 extern short i_shortint(); // DPI import at t/t_dpi_result_type.v:98:48 extern short i_shortint_t(); // DPI import at t/t_dpi_result_type.v:81:46 extern unsigned short i_shortint_unsigned(); // DPI import at t/t_dpi_result_type.v:99:48 extern unsigned short i_shortint_unsigned_t(); // DPI import at t/t_dpi_result_type.v:91:46 extern const char* i_string(); // DPI import at t/t_dpi_result_type.v:109:48 extern const char* i_string_t(); // DPI import at t/t_dpi_result_type.v:121:47 extern svBitVecVal i_struct_2_state_1(); // DPI import at t/t_dpi_result_type.v:122:47 extern svBitVecVal i_struct_2_state_32(); // DPI import at t/t_dpi_result_type.v:125:46 extern svBitVecVal i_union_2_state_1(); // DPI import at t/t_dpi_result_type.v:126:46 extern svBitVecVal i_union_2_state_32(); // DPI import at t/t_dpi_result_type.v:77:46 extern void i_void(); #ifdef __cplusplus } #endif verilator-4.038/test_regress/t/t_preproc_persist.out0000664000177100017500000000014513536675452023007 0ustar wsnyderwsnyderInside "t/t_preproc_persist.v". Inside "t/t_preproc_persist_inc.v". Inside "t/t_preproc_persist2.v". verilator-4.038/test_regress/t/t_interface_gen2_noinl.pl0000775000177100017500000000116013702133370023422 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen2.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_copy_bad.out0000664000177100017500000000041613702133367022517 0ustar wsnyderwsnyder%Error: t/t_class_copy_bad.v:19:16: New-as-copier passed different data type 'CLASSREFDTYPE 'Cls'' then expected 'CLASSREFDTYPE 'Other'' : ... In instance t 19 | c1 = new co; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_bind.v0000664000177100017500000000260413702133367020125 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 bit a_finished; bit b_finished; module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] o; wire si = 1'b0; ExampInst i (// Outputs .o (o[31:0]), // Inputs .i (1'b0) /*AUTOINST*/); Prog p (/*AUTOINST*/ // Inputs .si (si)); always @ (posedge clk) begin if (!a_finished) $stop; if (!b_finished) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module InstModule ( output logic [31:0] so, input si ); assign so = {32{si}}; endmodule program Prog (input si); initial a_finished = 1'b1; endprogram module ExampInst (o,i); output logic [31:0] o; input i; InstModule instName (// Outputs .so (o[31:0]), // Inputs .si (i) /*AUTOINST*/); //bind InstModule Prog instProg // (.si(si)); // Note is based on context of caller bind InstModule Prog instProg (/*AUTOBIND*/ .si (si)); endmodule // Check bind at top level bind InstModule Prog2 instProg2 (/*AUTOBIND*/ .si (si)); // Check program declared after bind program Prog2 (input si); initial b_finished = 1'b1; endprogram verilator-4.038/test_regress/t/t_bug3180.v0000664000177100017500000000233513702133367020303 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs someOutput, // Inputs clk, reset_l, InOne, InTwo ); input clk; input reset_l; input InOne, InTwo; output logic someOutput; typedef enum { STATE_ONE, STATE_TWO, STATE_THREE, STATE_FOUR } some_state_t; some_state_t some_FSM; always_ff @ (posedge clk or negedge reset_l) begin if(!reset_l) some_FSM <= some_FSM.first; else begin unique case (some_FSM) STATE_ONE, STATE_TWO, STATE_THREE: begin if(InOne & InTwo) some_FSM <= some_FSM.next; else if(InOne) some_FSM <= some_FSM; else some_FSM <= some_FSM.first; end default: begin some_FSM <= STATE_ONE; end endcase end end always_comb begin someOutput = (some_FSM == STATE_FOUR); end endmodule verilator-4.038/test_regress/t/t_with_unsup.pl0000775000177100017500000000111613702133370021556 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_long.v0000664000177100017500000002140713702133370021324 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; input clk; defparam i.L00 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L01 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L02 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L03 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L04 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L05 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L06 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L07 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L08 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L09 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L0A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L0B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L0C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L0D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L0E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L0F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L10 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L11 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L12 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L13 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L14 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L15 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L16 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L17 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L18 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L19 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L1A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L1B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L1C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L1D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L1E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L1F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L20 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L21 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L22 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L23 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L24 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L25 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L26 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L27 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L28 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L29 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L2A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L2B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L2C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L2D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L2E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L2F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L30 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L31 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L32 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L33 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L34 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L35 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L36 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L37 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L38 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L39 = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L3A = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L3B = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L3C = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L3D = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L3E = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.L3F = 256'h000012300000000000000000000000000000000000000000000000000000cdef; defparam i.A0 = "HELLO_WORLD_BOY_THIS_IS_LONG"; defparam i.A1 = "HELLO_WORLD_BOY_THIS_IS_LONG"; defparam i.A2 = "HELLO_WORLD_BOY_THIS_IS_LONG"; i i (.clk(clk)); integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module i (/*AUTOARG*/ // Inputs clk ); // verilator public_module input clk; parameter [255:0] L00 = 256'h0; parameter [255:0] L01 = 256'h0; parameter [255:0] L02 = 256'h0; parameter [255:0] L03 = 256'h0; parameter [255:0] L04 = 256'h0; parameter [255:0] L05 = 256'h0; parameter [255:0] L06 = 256'h0; parameter [255:0] L07 = 256'h0; parameter [255:0] L08 = 256'h0; parameter [255:0] L09 = 256'h0; parameter [255:0] L0A = 256'h0; parameter [255:0] L0B = 256'h0; parameter [255:0] L0C = 256'h0; parameter [255:0] L0D = 256'h0; parameter [255:0] L0E = 256'h0; parameter [255:0] L0F = 256'h0; parameter [255:0] L10 = 256'h0; parameter [255:0] L11 = 256'h0; parameter [255:0] L12 = 256'h0; parameter [255:0] L13 = 256'h0; parameter [255:0] L14 = 256'h0; parameter [255:0] L15 = 256'h0; parameter [255:0] L16 = 256'h0; parameter [255:0] L17 = 256'h0; parameter [255:0] L18 = 256'h0; parameter [255:0] L19 = 256'h0; parameter [255:0] L1A = 256'h0; parameter [255:0] L1B = 256'h0; parameter [255:0] L1C = 256'h0; parameter [255:0] L1D = 256'h0; parameter [255:0] L1E = 256'h0; parameter [255:0] L1F = 256'h0; parameter [255:0] L20 = 256'h0; parameter [255:0] L21 = 256'h0; parameter [255:0] L22 = 256'h0; parameter [255:0] L23 = 256'h0; parameter [255:0] L24 = 256'h0; parameter [255:0] L25 = 256'h0; parameter [255:0] L26 = 256'h0; parameter [255:0] L27 = 256'h0; parameter [255:0] L28 = 256'h0; parameter [255:0] L29 = 256'h0; parameter [255:0] L2A = 256'h0; parameter [255:0] L2B = 256'h0; parameter [255:0] L2C = 256'h0; parameter [255:0] L2D = 256'h0; parameter [255:0] L2E = 256'h0; parameter [255:0] L2F = 256'h0; parameter [255:0] L30 = 256'h0; parameter [255:0] L31 = 256'h0; parameter [255:0] L32 = 256'h0; parameter [255:0] L33 = 256'h0; parameter [255:0] L34 = 256'h0; parameter [255:0] L35 = 256'h0; parameter [255:0] L36 = 256'h0; parameter [255:0] L37 = 256'h0; parameter [255:0] L38 = 256'h0; parameter [255:0] L39 = 256'h0; parameter [255:0] L3A = 256'h0; parameter [255:0] L3B = 256'h0; parameter [255:0] L3C = 256'h0; parameter [255:0] L3D = 256'h0; parameter [255:0] L3E = 256'h0; parameter [255:0] L3F = 256'h0; parameter [255:0] A0 = 256'h0; parameter [255:0] A1 = 256'h0; parameter [255:0] A2 = 256'h0; always @ (posedge clk) begin end endmodule verilator-4.038/test_regress/t/t_inst_signed1.pl0000775000177100017500000000105313702133370021740 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_pragma_bad.out0000664000177100017500000000042313702133370022316 0ustar wsnyderwsnyder%Error: t/t_pp_pragma_bad.v:7:1: `pragma is missing a pragma_expression. 7 | `pragma | ^~~~~~~ `line 1 "t/t_pp_pragma_bad.v" 1 `line 3 "t/t_pp_pragma_bad.v" 0 `line 7 "t/t_pp_pragma_bad.v" 0 `pragma `line 9 "t/t_pp_pragma_bad.v" 2 %Error: Exiting due to verilator-4.038/test_regress/t/t_param_named_2.v0000664000177100017500000000215113702133370021665 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; input clk; m3 m3_inst (.clk(clk)); defparam m3_inst.FROMDEFP = 19; defparam m3_inst.P2 = 2; //defparam m3_inst.P3 = PAR; defparam m3_inst.P3 = 3; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module m3 (/*AUTOARG*/ // Inputs clk ); input clk; localparam LOC = 13; parameter UNCH = 99; parameter P1 = 10; parameter P2 = 20; parameter P3 = 30; parameter FROMDEFP = 11; initial begin $display("%x %x %x",P1,P2,P3); end always @ (posedge clk) begin if (UNCH !== 99) $stop; if (P1 !== 10) $stop; if (P2 !== 2) $stop; if (P3 !== 3) $stop; if (FROMDEFP !== 19) $stop; end endmodule verilator-4.038/test_regress/t/t_clk_condflop_nord.v0000664000177100017500000000472713702133367022700 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [0:0] d1; reg [2:0] d3; reg [7:0] d8; wire [0:0] q1; wire [2:0] q3; wire [7:0] q8; // verilator lint_off UNOPTFLAT reg ena; // verilator lint_on UNOPTFLAT condff #(12) condff (.clk(clk), .sen(1'b0), .ena(ena), .d({d8,d3,d1}), .q({q8,q3,q1})); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin //$write("%x %x %x %x\n", cyc, q8, q3, q1); cyc <= cyc + 1; if (cyc==1) begin d1 <= 1'b1; d3<=3'h1; d8<=8'h11; ena <= 1'b1; end if (cyc==2) begin d1 <= 1'b0; d3<=3'h2; d8<=8'h33; ena <= 1'b0; end if (cyc==3) begin d1 <= 1'b1; d3<=3'h3; d8<=8'h44; ena <= 1'b1; if (q8 != 8'h11) $stop; end if (cyc==4) begin d1 <= 1'b1; d3<=3'h4; d8<=8'h77; ena <= 1'b1; if (q8 != 8'h11) $stop; end if (cyc==5) begin d1 <= 1'b1; d3<=3'h0; d8<=8'h88; ena <= 1'b1; if (q8 != 8'h44) $stop; end if (cyc==6) begin if (q8 != 8'h77) $stop; end if (cyc==7) begin if (q8 != 8'h88) $stop; end // if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module condff (clk, sen, ena, d, q); parameter WIDTH = 1; input clk; input sen; input ena; input [WIDTH-1:0] d; output [WIDTH-1:0] q; condffimp #(.WIDTH(WIDTH)) imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q)); endmodule module condffimp (clk, sen, ena, d, q); parameter WIDTH = 1; input clk; input sen; input ena; input [WIDTH-1:0] d; output reg [WIDTH-1:0] q; wire gatedclk; clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk)); always @(posedge gatedclk) begin if (gatedclk === 1'bX) begin q <= {WIDTH{1'bX}}; end else begin q <= d; end end endmodule module clockgate (clk, sen, ena, gatedclk); input clk; input sen; input ena; output gatedclk; reg ena_b; wire gatedclk = clk & ena_b; // verilator lint_off COMBDLY always @(clk or ena or sen) begin if (~clk) begin ena_b <= ena | sen; end else begin if ((clk^sen)===1'bX) ena_b <= 1'bX; end end // verilator lint_on COMBDLY endmodule verilator-4.038/test_regress/t/t_select_runtime_range.pl0000775000177100017500000000105313702133370023547 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_castdyn.v0000664000177100017500000000065013702133367020655 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); int i; int a; int b; initial begin i = $cast(a, b); if (i != 1) $stop; $cast(a, b); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_cat.out0000664000177100017500000001177613702133370021504 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Thu Aug 30 16:11:10 2018 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # 1$ #1 0$ #2 b00000000000000000000000000000001 # 1$ #3 0$ #4 b00000000000000000000000000000010 # 1$ #5 0$ #6 b00000000000000000000000000000011 # 1$ #7 0$ #8 b00000000000000000000000000000100 # 1$ #9 0$ #10 b00000000000000000000000000000101 # 1$ #11 0$ #12 b00000000000000000000000000000110 # 1$ #13 0$ #14 b00000000000000000000000000000111 # 1$ #15 0$ #16 b00000000000000000000000000001000 # 1$ #17 0$ #18 b00000000000000000000000000001001 # 1$ #19 0$ #20 b00000000000000000000000000001010 # 1$ #21 0$ #22 b00000000000000000000000000001011 # 1$ #23 0$ #24 b00000000000000000000000000001100 # 1$ #25 0$ #26 b00000000000000000000000000001101 # 1$ #27 0$ #28 b00000000000000000000000000001110 # 1$ #29 0$ #30 b00000000000000000000000000001111 # 1$ #31 0$ #32 b00000000000000000000000000010000 # 1$ #33 0$ #34 b00000000000000000000000000010001 # 1$ #35 0$ #36 b00000000000000000000000000010010 # 1$ #37 0$ #38 b00000000000000000000000000010011 # 1$ #39 0$ #40 b00000000000000000000000000010100 # 1$ #41 0$ #42 b00000000000000000000000000010101 # 1$ #43 0$ #44 b00000000000000000000000000010110 # 1$ #45 0$ #46 b00000000000000000000000000010111 # 1$ #47 0$ #48 b00000000000000000000000000011000 # 1$ #49 0$ #50 b00000000000000000000000000011001 # 1$ #51 0$ #52 b00000000000000000000000000011010 # 1$ #53 0$ #54 b00000000000000000000000000011011 # 1$ #55 0$ #56 b00000000000000000000000000011100 # 1$ #57 0$ #58 b00000000000000000000000000011101 # 1$ #59 0$ #60 b00000000000000000000000000011110 # 1$ #61 0$ #62 b00000000000000000000000000011111 # 1$ #63 0$ #64 b00000000000000000000000000100000 # 1$ #65 0$ #66 b00000000000000000000000000100001 # 1$ #67 0$ #68 b00000000000000000000000000100010 # 1$ #69 0$ #70 b00000000000000000000000000100011 # 1$ #71 0$ #72 b00000000000000000000000000100100 # 1$ #73 0$ #74 b00000000000000000000000000100101 # 1$ #75 0$ #76 b00000000000000000000000000100110 # 1$ #77 0$ #78 b00000000000000000000000000100111 # 1$ #79 0$ #80 b00000000000000000000000000101000 # 1$ #81 0$ #82 b00000000000000000000000000101001 # 1$ #83 0$ #84 b00000000000000000000000000101010 # 1$ #85 0$ #86 b00000000000000000000000000101011 # 1$ #87 0$ #88 b00000000000000000000000000101100 # 1$ #89 0$ #90 b00000000000000000000000000101101 # 1$ #91 0$ #92 b00000000000000000000000000101110 # 1$ #93 0$ #94 b00000000000000000000000000101111 # 1$ #95 0$ #96 b00000000000000000000000000110000 # 1$ #97 0$ #98 b00000000000000000000000000110001 # 1$ #99 0$ #100 b00000000000000000000000000110010 # 1$ #101 0$ #102 b00000000000000000000000000110011 # 1$ #103 0$ #104 b00000000000000000000000000110100 # 1$ #105 0$ #106 b00000000000000000000000000110101 # 1$ #107 0$ #108 b00000000000000000000000000110110 # 1$ #109 0$ #110 b00000000000000000000000000110111 # 1$ #111 0$ #112 b00000000000000000000000000111000 # 1$ #113 0$ #114 b00000000000000000000000000111001 # 1$ #115 0$ #116 b00000000000000000000000000111010 # 1$ #117 0$ #118 b00000000000000000000000000111011 # 1$ #119 0$ #120 b00000000000000000000000000111100 # 1$ #121 0$ #122 b00000000000000000000000000111101 # 1$ #123 0$ #124 b00000000000000000000000000111110 # 1$ #125 0$ #126 b00000000000000000000000000111111 # 1$ #127 0$ #128 b00000000000000000000000001000000 # 1$ #129 0$ #130 b00000000000000000000000001000001 # 1$ #131 0$ #132 b00000000000000000000000001000010 # 1$ #133 0$ #134 b00000000000000000000000001000011 # 1$ #135 0$ #136 b00000000000000000000000001000100 # 1$ #137 0$ #138 b00000000000000000000000001000101 # 1$ #139 0$ #140 b00000000000000000000000001000110 # 1$ #141 0$ #142 b00000000000000000000000001000111 # 1$ #143 0$ #144 b00000000000000000000000001001000 # 1$ #145 0$ #146 b00000000000000000000000001001001 # 1$ #147 0$ #148 b00000000000000000000000001001010 # 1$ #149 0$ #150 b00000000000000000000000001001011 # 1$ #151 0$ #152 b00000000000000000000000001001100 # 1$ #153 0$ #154 b00000000000000000000000001001101 # 1$ #155 0$ #156 b00000000000000000000000001001110 # 1$ #157 0$ #158 b00000000000000000000000001001111 # 1$ #159 0$ #160 b00000000000000000000000001010000 # 1$ #161 0$ #162 b00000000000000000000000001010001 # 1$ #163 0$ #164 b00000000000000000000000001010010 # 1$ #165 0$ #166 b00000000000000000000000001010011 # 1$ #167 0$ #168 b00000000000000000000000001010100 # 1$ #169 0$ #170 b00000000000000000000000001010101 # 1$ #171 0$ #172 b00000000000000000000000001010110 # 1$ #173 0$ #174 b00000000000000000000000001010111 # 1$ #175 0$ #176 b00000000000000000000000001011000 # 1$ #177 0$ #178 b00000000000000000000000001011001 # 1$ #179 0$ #180 b00000000000000000000000001011010 # 1$ #181 0$ #182 b00000000000000000000000001011011 # 1$ #183 0$ #184 b00000000000000000000000001011100 # 1$ #185 0$ #186 b00000000000000000000000001011101 # 1$ #187 0$ #188 b00000000000000000000000001011110 # 1$ #189 0$ verilator-4.038/test_regress/t/t_array_pattern_packed.v0000664000177100017500000001531213702133367023373 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [1:0] [3:0] [3:0] array_simp; // big endian array logic [3:0] array_oned; initial begin array_oned = '{2:1'b1, 0:1'b1, default:1'b0}; if (array_oned != 4'b0101) $stop; array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; if (array_simp[0] !== 16'h3210) $stop; // verilator lint_off WIDTH array_simp[0] = '{ 3 ,2 ,1, 0 }; // verilator lint_on WIDTH if (array_simp[0] !== 16'h3210) $stop; // Doesn't seem to work for unpacked arrays in other simulators //if (array_simp[0] !== 16'h3210) $stop; //array_simp[0] = '{ 1:4'd3, default:13}; //if (array_simp[0] !== 16'hDD3D) $stop; array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; if (array_simp !== 32'h3210_1234) $stop; // IEEE says '{} allowed only on assignments, not !=, ==. // Doesn't seem to work for unpacked arrays in other simulators array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; if (array_simp !== 32'h3210_3210) $stop; array_simp = '{2{ '{4{ 4'd3 }} }}; if (array_simp !== 32'h3333_3333) $stop; // Not legal in other simulators - replication doesn't match // However IEEE suggests this is legal. //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} $write("*-* All Finished *-*\n"); $finish; end //==================== // parameters for array sizes localparam WA = 4; // address dimension size localparam WB = 4; // bit dimension size localparam NO = 11; // number of access events // 2D packed arrays logic [WA-1:0] [WB-1:0] array_bg; // big endian array /* verilator lint_off LITENDIAN */ logic [0:WA-1] [0:WB-1] array_lt; // little endian array /* verilator lint_on LITENDIAN */ integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin $write("*-* All Finished *-*\n"); $finish; end // big endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]== 0) array_bg <= '0; else if (cnt[30:2]== 1) array_bg <= '0; else if (cnt[30:2]== 2) array_bg <= '0; else if (cnt[30:2]== 3) array_bg <= '0; else if (cnt[30:2]== 4) array_bg <= '0; else if (cnt[30:2]== 5) array_bg <= '0; else if (cnt[30:2]== 6) array_bg <= '0; else if (cnt[30:2]== 7) array_bg <= '0; else if (cnt[30:2]== 8) array_bg <= '0; else if (cnt[30:2]== 9) array_bg <= '0; else if (cnt[30:2]==10) array_bg <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]== 0) begin end else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 }; else if (cnt[30:2]== 2) array_bg <= '{default:13}; else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7}; else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13}; else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }}; else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 2) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 3) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end else if (cnt[30:2]== 6) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end end // little endian always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]== 0) array_lt <= '0; else if (cnt[30:2]== 1) array_lt <= '0; else if (cnt[30:2]== 2) array_lt <= '0; else if (cnt[30:2]== 3) array_lt <= '0; else if (cnt[30:2]== 4) array_lt <= '0; else if (cnt[30:2]== 5) array_lt <= '0; else if (cnt[30:2]== 6) array_lt <= '0; else if (cnt[30:2]== 7) array_lt <= '0; else if (cnt[30:2]== 8) array_lt <= '0; else if (cnt[30:2]== 9) array_lt <= '0; else if (cnt[30:2]==10) array_lt <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]== 0) begin end else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 }; else if (cnt[30:2]== 2) array_lt <= '{default:13}; else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7}; else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13}; else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }}; else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 2) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 3) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end end endmodule verilator-4.038/test_regress/t/t_protect_ids_key.pl0000775000177100017500000000153613702133370022546 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_protect_ids.v"); compile( verilator_flags2 => ["--protect-ids --protect-key SECRET_KEY", "t/t_protect_ids_c.cpp"], ); execute( check_finished => 1, ); # Since using a named key, we can check for always identical map files_identical("$Self->{obj_dir}/$Self->{VM_PREFIX}__idmap.xml", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen5.v0000664000177100017500000000244013702133370022057 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); logic val; function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t(); generate begin : TestIf intf #(.PARAM(1)) my_intf (); assign my_intf.val = '0; t1 t (.mod_intf(my_intf)); // initial $display("%0d", my_intf.func()); end endgenerate generate begin intf #(.PARAM(1)) my_intf (); assign my_intf.val = '1; t1 t (.mod_intf(my_intf)); // initial $display("%0d", my_intf.func()); end endgenerate localparam LP = 1; logic val; generate begin if (LP) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; assign val = my_intf.val; end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '1; assign val = my_intf.val; end end endgenerate initial begin $display("%0d", val); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_inst_ccall.pl0000775000177100017500000000105313702133370021464 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_latch_bad.v0000664000177100017500000000104313702133370022126 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs bl, cl, bc, cc, // Inputs a ); input logic a; output logic bl; output logic cl; always_latch begin bl <= a; // No warning cl = a; end output logic bc; output logic cc; always_comb begin bc <= a; // Warning cc = a; end endmodule verilator-4.038/test_regress/t/t_struct_port.v0000664000177100017500000000362213702133370021574 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { bit b9; byte b1; bit b0; } pack_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs pack_t in; always @* in = crc[9:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) pack_t out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out), // Inputs .in (in)); // Aggregate outputs into a single result vector wire [63:0] result = {54'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h99c434d9b08c2a8a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input pack_t in, output pack_t out); always @* begin out = in; out.b1 = in.b1 + 1; out.b0 = 1'b1; end endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-4.038/test_regress/t/t_type_param.v0000664000177100017500000000603413702133370021345 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module foo #(parameter type bar = logic) (output int bar_size); localparam baz = $bits(bar); assign bar_size = baz; endmodule module foo_wrapper #(parameter bar_bits = 9) (output int bar_size); foo #(.bar (logic[bar_bits-1:0])) foo_inst (.bar_size (bar_size)); endmodule module t(); logic [7:0] qux1; int bar_size1; foo #(.bar (logic [ $bits(qux1) - 1 : 0])) foo_inst1 (.bar_size (bar_size1)); logic [7:0] qux2; int bar_size2; foo #(.bar (logic [ $bits(qux2) - 1 : 0])) foo_inst2 (.bar_size (bar_size2)); logic [7:0] qux3; int bar_size3; foo #(.bar (logic [ $bits(qux3) - 1 : 0])) foo_inst3 (.bar_size (bar_size3)); localparam bar_bits = 13; int bar_size_wrapper; foo_wrapper #(.bar_bits (bar_bits)) foo_wrapper_inst (.bar_size (bar_size_wrapper)); initial begin if ($bits(qux1) != foo_inst1.baz) begin $display("%m: bits of qux1 != bits of foo_inst1.baz (%0d, %0d)", $bits(qux1), foo_inst1.baz); $stop(); end if ($bits(qux2) != foo_inst2.baz) begin $display("%m: bits of qux2 != bits of foo_inst2.baz (%0d, %0d)", $bits(qux2), foo_inst2.baz); $stop(); end if ($bits(qux3) != foo_inst3.baz) begin $display("%m: bits of qux3 != bits of foo_inst3.baz (%0d, %0d)", $bits(qux3), foo_inst3.baz); $stop(); end if (bar_bits != foo_wrapper_inst.foo_inst.baz) begin $display("%m: bar_bits != bits of foo_wrapper_inst.foo_inst.baz (%0d, %0d)", bar_bits, foo_wrapper_inst.foo_inst.baz); $stop(); end if (bar_size1 != $bits(qux1)) begin $display("%m: bar_size1 != bits of qux1 (%0d, %0d)", bar_size1, $bits(qux1)); $stop(); end if (bar_size2 != $bits(qux2)) begin $display("%m: bar_size2 != bits of qux2 (%0d, %0d)", bar_size2, $bits(qux2)); $stop(); end if (bar_size3 != $bits(qux3)) begin $display("%m: bar_size3 != bits of qux3 (%0d, %0d)", bar_size3, $bits(qux3)); $stop(); end if (bar_size_wrapper != bar_bits) begin $display("%m: bar_size_wrapper != bar_bits (%0d, %0d)", bar_size_wrapper, bar_bits); $stop(); end end genvar m; generate for (m = 1; m <= 8; m+=1) begin : gen_m initial begin if (m != foo_inst.baz) begin $display("%m: m != bits of foo_inst.baz (%0d, %0d)", m, foo_inst.baz); $stop(); end end foo #(.bar (logic[m-1:0])) foo_inst (.bar_size ()); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_program.v0000664000177100017500000000047313702133370020654 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 program t; initial begin $write("*-* All Finished *-*\n"); $finish; end endprogram verilator-4.038/test_regress/t/t_func_bad_width.out0000664000177100017500000000123313702133370022502 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_func_bad_width.v:13:13: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits. : ... In instance t 13 | out = MUX (in); | ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. : ... In instance t 13 | out = MUX (in); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_ref_trace_fst.out0000664000177100017500000003725013702133370024400 0ustar wsnyderwsnyder$date Sun Apr 19 04:13:22 2020 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $scope module intf_1 $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end $scope module the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $scope module s1 $end $scope module intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end $scope module the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $scope module c1 $end $scope module intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end $scope module the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $scope module a $end $scope module intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end $scope module the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $scope module ac1 $end $scope module intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end $scope module the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end $scope module intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end $scope module the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $scope module ac2 $end $scope module intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end $scope module the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module intf_2 $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end $scope module the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $scope module s2 $end $scope module intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end $scope module the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $upscope $end $scope module c2 $end $scope module intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end $scope module the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $upscope $end $scope module a $end $scope module intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end $scope module the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $scope module ac2 $end $scope module intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end $scope module the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end $scope module intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end $scope module the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $scope module ac1 $end $scope module intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end $scope module the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module a $end $scope module intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 ) value $end $scope module the_struct $end $var logic 32 * val100 $end $var logic 32 + val200 $end $upscope $end $upscope $end $scope module as3 $end $scope module intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 ) value $end $scope module the_struct $end $var logic 32 * val100 $end $var logic 32 + val200 $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope module intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 ) value $end $scope module the_struct $end $var logic 32 * val100 $end $var logic 32 + val200 $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end $scope module intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 , value $end $scope module the_struct $end $var logic 32 - val100 $end $var logic 32 . val200 $end $upscope $end $upscope $end $scope module as3 $end $scope module intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 , value $end $scope module the_struct $end $var logic 32 - val100 $end $var logic 32 . val200 $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope module intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 , value $end $scope module the_struct $end $var logic 32 - val100 $end $var logic 32 . val200 $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000000000000000000000000000000 " b00000000000000000000000000000001 # b00000000000000000000000001100101 $ b00000000000000000000000011001001 % b00000000000000000000000000000010 & b00000000000000000000000001100110 ' b00000000000000000000000011001010 ( b00000000000000000000001111101001 ) b00000000000000000000010001001101 * b00000000000000000000010010110001 + b00000000000000000000001111101010 , b00000000000000000000010001001110 - b00000000000000000000010010110010 . #10 b00000000000000000000010010110011 . b00000000000000000000010001001111 - b00000000000000000000001111101011 , b00000000000000000000010010110010 + b00000000000000000000010001001110 * b00000000000000000000001111101010 ) b00000000000000000000000011001011 ( b00000000000000000000000001100111 ' b00000000000000000000000000000011 & b00000000000000000000000011001010 % b00000000000000000000000001100110 $ b00000000000000000000000000000010 # b00000000000000000000000000000001 " 1! #15 0! #20 1! b00000000000000000000000000000010 " b00000000000000000000000000000011 # b00000000000000000000000001100111 $ b00000000000000000000000011001011 % b00000000000000000000000000000100 & b00000000000000000000000001101000 ' b00000000000000000000000011001100 ( b00000000000000000000001111101011 ) b00000000000000000000010001001111 * b00000000000000000000010010110011 + b00000000000000000000001111101100 , b00000000000000000000010001010000 - b00000000000000000000010010110100 . #25 0! #30 1! b00000000000000000000010010110101 . b00000000000000000000010001010001 - b00000000000000000000001111101101 , b00000000000000000000010010110100 + b00000000000000000000010001010000 * b00000000000000000000001111101100 ) b00000000000000000000000011001101 ( b00000000000000000000000001101001 ' b00000000000000000000000000000101 & b00000000000000000000000011001100 % b00000000000000000000000001101000 $ b00000000000000000000000000000100 # b00000000000000000000000000000011 " #35 0! #40 1! b00000000000000000000000000000100 " b00000000000000000000000000000101 # b00000000000000000000000001101001 $ b00000000000000000000000011001101 % b00000000000000000000000000000110 & b00000000000000000000000001101010 ' b00000000000000000000000011001110 ( b00000000000000000000001111101101 ) b00000000000000000000010001010001 * b00000000000000000000010010110101 + b00000000000000000000001111101110 , b00000000000000000000010001010010 - b00000000000000000000010010110110 . #45 0! #50 1! b00000000000000000000010010110111 . b00000000000000000000010001010011 - b00000000000000000000001111101111 , b00000000000000000000010010110110 + b00000000000000000000010001010010 * b00000000000000000000001111101110 ) b00000000000000000000000011001111 ( b00000000000000000000000001101011 ' b00000000000000000000000000000111 & b00000000000000000000000011001110 % b00000000000000000000000001101010 $ b00000000000000000000000000000110 # b00000000000000000000000000000101 " #55 0! #60 1! b00000000000000000000000000000110 " b00000000000000000000000000000111 # b00000000000000000000000001101011 $ b00000000000000000000000011001111 % b00000000000000000000000000001000 & b00000000000000000000000001101100 ' b00000000000000000000000011010000 ( b00000000000000000000001111101111 ) b00000000000000000000010001010011 * b00000000000000000000010010110111 + b00000000000000000000001111110000 , b00000000000000000000010001010100 - b00000000000000000000010010111000 . #65 0! #70 1! b00000000000000000000010010111001 . b00000000000000000000010001010101 - b00000000000000000000001111110001 , b00000000000000000000010010111000 + b00000000000000000000010001010100 * b00000000000000000000001111110000 ) b00000000000000000000000011010001 ( b00000000000000000000000001101101 ' b00000000000000000000000000001001 & b00000000000000000000000011010000 % b00000000000000000000000001101100 $ b00000000000000000000000000001000 # b00000000000000000000000000000111 " #75 0! #80 1! b00000000000000000000000000001000 " b00000000000000000000000000001001 # b00000000000000000000000001101101 $ b00000000000000000000000011010001 % b00000000000000000000000000001010 & b00000000000000000000000001101110 ' b00000000000000000000000011010010 ( b00000000000000000000001111110001 ) b00000000000000000000010001010101 * b00000000000000000000010010111001 + b00000000000000000000001111110010 , b00000000000000000000010001010110 - b00000000000000000000010010111010 . #85 0! #90 1! b00000000000000000000010010111011 . b00000000000000000000010001010111 - b00000000000000000000001111110011 , b00000000000000000000010010111010 + b00000000000000000000010001010110 * b00000000000000000000001111110010 ) b00000000000000000000000011010011 ( b00000000000000000000000001101111 ' b00000000000000000000000000001011 & b00000000000000000000000011010010 % b00000000000000000000000001101110 $ b00000000000000000000000000001010 # b00000000000000000000000000001001 " #95 0! #100 1! b00000000000000000000000000001010 " b00000000000000000000000000001011 # b00000000000000000000000001101111 $ b00000000000000000000000011010011 % b00000000000000000000000000001100 & b00000000000000000000000001110000 ' b00000000000000000000000011010100 ( b00000000000000000000001111110011 ) b00000000000000000000010001010111 * b00000000000000000000010010111011 + b00000000000000000000001111110100 , b00000000000000000000010001011000 - b00000000000000000000010010111100 . #105 0! #110 1! b00000000000000000000010010111101 . b00000000000000000000010001011001 - b00000000000000000000001111110101 , b00000000000000000000010010111100 + b00000000000000000000010001011000 * b00000000000000000000001111110100 ) b00000000000000000000000011010101 ( b00000000000000000000000001110001 ' b00000000000000000000000000001101 & b00000000000000000000000011010100 % b00000000000000000000000001110000 $ b00000000000000000000000000001100 # b00000000000000000000000000001011 " #115 0! #120 1! b00000000000000000000000000001100 " b00000000000000000000000000001101 # b00000000000000000000000001110001 $ b00000000000000000000000011010101 % b00000000000000000000000000001110 & b00000000000000000000000001110010 ' b00000000000000000000000011010110 ( b00000000000000000000001111110101 ) b00000000000000000000010001011001 * b00000000000000000000010010111101 + b00000000000000000000001111110110 , b00000000000000000000010001011010 - b00000000000000000000010010111110 . #125 0! #130 1! b00000000000000000000010010111111 . b00000000000000000000010001011011 - b00000000000000000000001111110111 , b00000000000000000000010010111110 + b00000000000000000000010001011010 * b00000000000000000000001111110110 ) b00000000000000000000000011010111 ( b00000000000000000000000001110011 ' b00000000000000000000000000001111 & b00000000000000000000000011010110 % b00000000000000000000000001110010 $ b00000000000000000000000000001110 # b00000000000000000000000000001101 " #135 0! #140 1! b00000000000000000000000000001110 " b00000000000000000000000000001111 # b00000000000000000000000001110011 $ b00000000000000000000000011010111 % b00000000000000000000000000010000 & b00000000000000000000000001110100 ' b00000000000000000000000011011000 ( b00000000000000000000001111110111 ) b00000000000000000000010001011011 * b00000000000000000000010010111111 + b00000000000000000000001111111000 , b00000000000000000000010001011100 - b00000000000000000000010011000000 . #145 0! #150 1! b00000000000000000000010011000001 . b00000000000000000000010001011101 - b00000000000000000000001111111001 , b00000000000000000000010011000000 + b00000000000000000000010001011100 * b00000000000000000000001111111000 ) b00000000000000000000000011011001 ( b00000000000000000000000001110101 ' b00000000000000000000000000010001 & b00000000000000000000000011011000 % b00000000000000000000000001110100 $ b00000000000000000000000000010000 # b00000000000000000000000000001111 " #155 0! #160 1! b00000000000000000000000000010000 " b00000000000000000000000000010001 # b00000000000000000000000001110101 $ b00000000000000000000000011011001 % b00000000000000000000000000010010 & b00000000000000000000000001110110 ' b00000000000000000000000011011010 ( b00000000000000000000001111111001 ) b00000000000000000000010001011101 * b00000000000000000000010011000001 + b00000000000000000000001111111010 , b00000000000000000000010001011110 - b00000000000000000000010011000010 . #165 0! #170 1! b00000000000000000000010011000011 . b00000000000000000000010001011111 - b00000000000000000000001111111011 , b00000000000000000000010011000010 + b00000000000000000000010001011110 * b00000000000000000000001111111010 ) b00000000000000000000000011011011 ( b00000000000000000000000001110111 ' b00000000000000000000000000010011 & b00000000000000000000000011011010 % b00000000000000000000000001110110 $ b00000000000000000000000000010010 # b00000000000000000000000000010001 " #175 0! #180 1! b00000000000000000000000000010010 " b00000000000000000000000000010011 # b00000000000000000000000001110111 $ b00000000000000000000000011011011 % b00000000000000000000000000010100 & b00000000000000000000000001111000 ' b00000000000000000000000011011100 ( b00000000000000000000001111111011 ) b00000000000000000000010001011111 * b00000000000000000000010011000011 + b00000000000000000000001111111100 , b00000000000000000000010001100000 - b00000000000000000000010011000100 . #185 0! #190 1! b00000000000000000000010011000101 . b00000000000000000000010001100001 - b00000000000000000000001111111101 , b00000000000000000000010011000100 + b00000000000000000000010001100000 * b00000000000000000000001111111100 ) b00000000000000000000000011011101 ( b00000000000000000000000001111001 ' b00000000000000000000000000010101 & b00000000000000000000000011011100 % b00000000000000000000000001111000 $ b00000000000000000000000000010100 # b00000000000000000000000000010011 " #195 0! #200 1! b00000000000000000000000000010100 " b00000000000000000000000000010101 # b00000000000000000000000001111001 $ b00000000000000000000000011011101 % b00000000000000000000000000010110 & b00000000000000000000000001111010 ' b00000000000000000000000011011110 ( b00000000000000000000001111111101 ) b00000000000000000000010001100001 * b00000000000000000000010011000101 + b00000000000000000000001111111110 , b00000000000000000000010001100010 - b00000000000000000000010011000110 . #205 0! #210 1! b00000000000000000000010011000111 . b00000000000000000000010001100011 - b00000000000000000000001111111111 , b00000000000000000000010011000110 + b00000000000000000000010001100010 * b00000000000000000000001111111110 ) b00000000000000000000000011011111 ( b00000000000000000000000001111011 ' b00000000000000000000000000010111 & b00000000000000000000000011011110 % b00000000000000000000000001111010 $ b00000000000000000000000000010110 # b00000000000000000000000000010101 " verilator-4.038/test_regress/t/t_scope_map.cpp0000664000177100017500000001234513702133370021471 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include #include #include #include "Vt_scope_map.h" unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const unsigned long long dt_2 = 3; int main(int argc, char** argv, char** env) { Vt_scope_map* top = new Vt_scope_map("top"); Verilated::debug(0); Verilated::traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; top->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); top->CLK = 0; top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; const VerilatedScopeNameMap* scopeMapp = Verilated::scopeNameMap(); for (VerilatedScopeNameMap::const_iterator it = scopeMapp->begin(); it != scopeMapp->end(); ++it) { #ifdef TEST_VERBOSE VL_PRINTF("---------------------------------------------\n"); VL_PRINTF("Scope = %s\n", it->first); it->second->scopeDump(); #endif VerilatedVarNameMap* varNameMap = it->second->varsp(); if (varNameMap == NULL) { VL_PRINTF("%%Error: Bad varsp()\n"); return -1; } for (VerilatedVarNameMap::iterator varIt = varNameMap->begin(); varIt != varNameMap->end(); ++varIt) { VerilatedVar* var = &varIt->second; int varLeft = var->packed().left(); int varRight = var->packed().right(); #ifdef TEST_VERBOSE VL_PRINTF("\tVar = %s\n", varIt->first); VL_PRINTF("\t Type = %d\n", var->vltype()); VL_PRINTF("\t EntSize = %d\n", var->entSize()); VL_PRINTF("\t Dims = %d\n", var->dims()); VL_PRINTF("\t Range = %d:%d\n", varLeft, varRight); VL_PRINTF("\t Is RW = %d\n", var->isPublicRW()); #endif if (varRight != 0) { VL_PRINTF("%%Error: Was expecting right range value = 0\n"); return -1; } int varBits = varLeft + 1; // First expect an incrementing byte pattern vluint8_t* varData = reinterpret_cast(var->datap()); for (int i = 0; i < varBits / 8; i++) { #ifdef TEST_VERBOSE VL_PRINTF("%02x ", varData[i]); #endif vluint8_t expected = i % 0xff; if (varData[i] != expected) { VL_PRINTF("%%Error: Data mismatch, got 0x%02x, expected 0x%02x\n", varData[i], expected); return -1; } } // Extra bits all set high initially if (varBits % 8 != 0) { vluint8_t got = varData[varBits / 8]; vluint8_t expected = ~(0xff << (varBits % 8)); if (got != expected) { VL_PRINTF("%%Error: Data mismatch, got 0x%02x, expected 0x%02x\n", got, expected); return -1; } } #ifdef TEST_VERBOSE VL_PRINTF("\n"); #endif // Clear out the data memset(varData, 0, (varBits + 7) / 8); } } top->CLK = 0; top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; // Posedge on clock, expect all the public bits to flip top->CLK = 1; top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; for (VerilatedScopeNameMap::const_iterator it = scopeMapp->begin(); it != scopeMapp->end(); ++it) { VerilatedVarNameMap* varNameMap = it->second->varsp(); if (varNameMap == NULL) { VL_PRINTF("%%Error: Bad varsp()\n"); return -1; } for (VerilatedVarNameMap::iterator varIt = varNameMap->begin(); varIt != varNameMap->end(); ++varIt) { VerilatedVar* var = &varIt->second; int varLeft = var->packed().left(); int varBits = varLeft + 1; vluint8_t* varData = reinterpret_cast(var->datap()); // Check that all bits are high now for (int i = 0; i < varBits / 8; i++) { vluint8_t expected = 0xff; if (varData[i] != expected) { VL_PRINTF("%%Error: Data mismatch (%s), got 0x%02x, expected 0x%02x\n", varIt->first, varData[i], expected); return -1; } } if (varBits % 8 != 0) { vluint8_t got = varData[varBits / 8]; vluint8_t expected = ~(0xff << (varBits % 8)); if (got != expected) { VL_PRINTF("%%Error: Data mismatch (%s), got 0x%02x, expected 0x%02x\n", varIt->first, got, expected); return -1; } } } } top->CLK = 0; top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; tfp->close(); top->final(); VL_PRINTF("*-* All Finished *-*\n"); return 0; } verilator-4.038/test_regress/t/t_interface_down_inlac.pl0000775000177100017500000000125513702133370023512 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_A +define+INLINE_C'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_concat_opt.pl0000775000177100017500000000105313702133367021510 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_for_comma_bad.v0000664000177100017500000000174313702133370021756 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); integer a, b; initial begin for (; ; ) ; for (; ; a=a+1) ; for (; ; a=a+1, b=b+1) ; for (; a<1; ) ; for (; a<1; a=a+1) ; for (; a<1; a=a+1, b=b+1) ; for (a=0; a<1; ) ; for (a=0; a<1; a=a+1) ; for (a=0; a<1; a=a+1, b=b+1) ; for (integer a=0; a<1; ) ; for (integer a=0; a<1; a=a+1) ; for (integer a=0; a<1; a=a+1, b=b+1) ; for (var integer a=0; a<1; ) ; for (var integer a=0; a<1; a=a+1) ; for (var integer a=0; a<1; a=a+1, b=b+1) ; for (integer a=0, integer b=0; a<1; ) ; for (integer a=0, integer b=0; a<1; a=a+1) ; for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_fork_func_bad.pl0000775000177100017500000000114513702133370022135 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ['--lint-only'], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_debug_graph_test.v0000664000177100017500000000044113702133370022506 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); endmodule verilator-4.038/test_regress/t/t_initarray_nonarray.v0000664000177100017500000000120313702133370023110 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // The code here is used to trigger Verilator internal error // "InitArray on non-array" // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 typedef logic [7:0] mask_t [7:0]; // parameter logic [7:0] IMP_MASK[7:0] = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37}; parameter mask_t IMP_MASK = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37}; module t (/*AUTOARG*/ // Inputs clk ); input clk; mask_t a; //logic [7:0] a[7:0]; assign a = IMP_MASK; endmodule verilator-4.038/test_regress/t/t_vpi_zero_time_cb.v0000664000177100017500000000626713702133370022533 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs input clk ); `ifndef VERILATOR reg clk_r = 0; always #10 clk_r = ~clk_r; assign clk = clk_r; `endif reg onebit /*verilator public_flat_rw @(posedge clk) */; reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */; reg [31:0] count /*verilator public_flat_rd */; reg [31:0] half_count /*verilator public_flat_rd */; reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */; reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */; reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */; reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */; reg [511:0] text /*verilator public_flat_rw @(posedge clk) */; integer status; sub sub(); // Test loop initial begin count = 0; onebit = 1'b0; fourthreetwoone[3] = 0; // stop icarus optimizing away text_byte = "B"; text_half = "Hf"; text_word = "Word"; text_long = "Long64b"; text = "Verilog Test module"; /* if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop; end $write("%%Info: Checking results\n"); if (onebit != 1'b1) $stop; if (quads[2] != 62'h12819213_abd31a1c) $stop; if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; if (text_byte != "A") $stop; if (text_half != "T2") $stop; if (text_word != "Tree") $stop; if (text_long != "44Four44") $stop; if (text != "lorem ipsum") $stop; */ end always @(posedge clk) begin count <= count + 2; if (count[1]) half_count <= half_count + 2; if (count == 1000) begin // $write("*-* All Finished *-*\n"); $finish; end end genvar i; generate for (i=1; i<=128; i=i+1) begin : arr arr #(.LENGTH(i)) arr(); end endgenerate endmodule : t module sub; reg subsig1 /*verilator public_flat_rd*/; reg subsig2 /*verilator public_flat_rd*/; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = subsig1 | subsig2; `endif endmodule : sub module arr; parameter LENGTH = 1; reg [LENGTH-1:0] sig /*verilator public_flat_rw*/; reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/; reg check /*verilator public_flat_rw*/; reg verbose /*verilator public_flat_rw*/; initial begin sig = {LENGTH{1'b0}}; rfr = {LENGTH{1'b0}}; end always @(posedge check) begin if (verbose) $display("%m : %x %x", sig, rfr); if (check && sig != rfr) $stop; check <= 0; end endmodule : arr verilator-4.038/test_regress/t/t_var_static.v0000664000177100017500000000462613702133370021350 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; function int f_no_no (); int st = 2; st++; return st; endfunction function int f_no_st (); static int st = 2; st++; return st; endfunction function int f_no_au (); automatic int au = 2; au++; return au; endfunction function static int f_st_no (); int st = 2; st++; return st; endfunction function static int f_st_st (); static int st = 2; st++; return st; endfunction function static int f_st_au (); automatic int au = 2; au++; return au; endfunction function automatic int f_au_no (); int au = 2; au++; return au; endfunction function automatic int f_au_st (); static int st = 2; st++; return st; endfunction function automatic int f_au_au (); automatic int au = 2; au++; return au; endfunction initial begin `checkh(f_no_no(), 3); `checkh(f_no_no(), 4); `checkh(f_no_st(), 3); `checkh(f_no_st(), 4); `checkh(f_no_au(), 3); `checkh(f_no_au(), 3); // `checkh(f_st_no(), 3); `checkh(f_st_no(), 4); `checkh(f_st_st(), 3); `checkh(f_st_st(), 4); `checkh(f_st_au(), 3); `checkh(f_st_au(), 3); // `checkh(f_au_no(), 3); `checkh(f_au_no(), 3); `checkh(f_au_st(), 3); `checkh(f_au_st(), 4); `checkh(f_au_au(), 3); `checkh(f_au_au(), 3); // end int cyc = 0; always @ (posedge clk) begin int ist1; static int ist2; automatic int iau3; cyc <= cyc + 1; if (cyc == 0) begin ist1 = 10; ist2 = 20; iau3 = 30; `checkh(ist1, 10); `checkh(ist2, 20); `checkh(iau3, 30); ++ist1; ++ist2; ++iau3; end else if (cyc == 1) begin `checkh(ist1, 11); `checkh(ist2, 21); `checkh(iau3, 0); end else if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_enumeration.v0000664000177100017500000002777413702133370021550 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cnt = 0; integer mod = 0; // event counter always @ (posedge clk) if (cnt==20) begin cnt <= 0; mod <= mod + 1; end else begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if (mod==3) begin $write("*-* All Finished *-*\n"); $finish; end // anonymous type variable declaration enum logic [2:0] {red=1, orange, yellow, green, blue, indigo, violet} rainbow7; // named type typedef enum logic {OFF, ON} t_switch; t_switch switch; // numbering examples enum integer {father, mother, son[2], daughter, gerbil, dog[3]=10, cat[3:5]=20, car[3:1]=30} family; // test of raibow7 type always @ (posedge clk) if (mod==0) begin // write value to array if (cnt== 0) begin rainbow7 <= rainbow7.first(); // check number if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end if (rainbow7 !== 3'bxxx ) begin $display("%b", rainbow7 ); $stop(); end end else if (cnt== 1) begin if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 2) begin if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 3) begin if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 4) begin if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 5) begin if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 6) begin if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 7) begin if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 8) begin if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end end else if (mod==1) begin // write value to array if (cnt== 0) begin rainbow7 <= rainbow7.last(); // check number if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end end else if (cnt== 1) begin if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 2) begin if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 3) begin if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 4) begin if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 5) begin if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 6) begin if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 7) begin if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 8) begin if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end end // test of t_switch type always @ (posedge clk) if (mod==0) begin // write value to array if (cnt== 0) begin switch <= switch.first(); // check number if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end if (switch !== 1'bx) begin $display("%b", switch ); $stop(); end end else if (cnt== 1) begin if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end if (switch !== OFF ) begin $display("%b", switch ); $stop(); end switch <= switch.next(); end else if (cnt== 2) begin if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end if (switch !== ON ) begin $display("%b", switch ); $stop(); end switch <= switch.next(); end else if (cnt== 3) begin if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end if (switch !== OFF ) begin $display("%b", switch ); $stop(); end switch <= switch.next(); end end else if (mod==1) begin // write value to array if (cnt== 0) begin rainbow7 <= rainbow7.last(); // check number if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end end else if (cnt== 1) begin if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end if (switch !== ON ) begin $display("%b", switch ); $stop(); end switch <= switch.prev(); end else if (cnt== 2) begin if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end if (switch !== OFF ) begin $display("%b", switch ); $stop(); end switch <= switch.prev(); end else if (cnt== 3) begin if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end if (switch !== ON ) begin $display("%b", switch ); $stop(); end switch <= switch.prev(); end end // test of raibow7 type always @ (posedge clk) if (mod==0) begin // write value to array if (cnt== 0) begin family <= family.first(); // check number if (family.num() !== 15 ) begin $display("%d", family.num() ); $stop(); end if (family !== 32'dx ) begin $display("%b", family ); $stop(); end end else if (cnt== 1) begin if (family !== 0 ) begin $display("%b", family ); $stop(); end if (family !== father ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 2) begin if (family !== 1 ) begin $display("%b", family ); $stop(); end if (family !== mother ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 3) begin if (family !== 2 ) begin $display("%b", family ); $stop(); end if (family !== son0 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 4) begin if (family !== 3 ) begin $display("%b", family ); $stop(); end if (family !== son1 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 5) begin if (family !== 4 ) begin $display("%b", family ); $stop(); end if (family !== daughter ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 6) begin if (family !== 5 ) begin $display("%b", family ); $stop(); end if (family !== gerbil ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 7) begin if (family !== 10 ) begin $display("%b", family ); $stop(); end if (family !== dog0 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 8) begin if (family !== 11 ) begin $display("%b", family ); $stop(); end if (family !== dog1 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 9) begin if (family !== 12 ) begin $display("%b", family ); $stop(); end if (family !== dog2 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 10) begin if (family !== 20 ) begin $display("%b", family ); $stop(); end if (family !== cat3 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 11) begin if (family !== 21 ) begin $display("%b", family ); $stop(); end if (family !== cat4 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 12) begin if (family !== 22 ) begin $display("%b", family ); $stop(); end if (family !== cat5 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 13) begin if (family !== 30 ) begin $display("%b", family ); $stop(); end if (family !== car3 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 14) begin if (family !== 31 ) begin $display("%b", family ); $stop(); end if (family !== car2 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 15) begin if (family !== 32 ) begin $display("%b", family ); $stop(); end if (family !== car1 ) begin $display("%b", family ); $stop(); end family <= family.next(); end end endmodule verilator-4.038/test_regress/t/t_alias2_unsup.v0000664000177100017500000000160113702133367021612 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Values to swap and locations for the swapped values. reg [31:0] x = 32'ha5a5a5a5; wire [31:0] y; testit testi_i (.a (x[7:0]), .b (y[31:24])); always @ (posedge clk) begin x <= {x[30:0],1'b0}; $write("x = %x, y = %x\n", x, y); if (x[3:0] != 4'h0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule // Swap the byte order of two args. module testit (input wire [7:0] a, output wire [7:0] b ); alias b = {a[3:0],a[7:4]}; endmodule verilator-4.038/test_regress/t/t_interface_gen12.v0000664000177100017500000000111213702133370022130 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug1005 module foo_module; generate for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block logic baz; end endgenerate endmodule module bar_module; foo_module foo(); endmodule module t; bar_module bar(); initial begin bar.foo.my_gen_block[0].baz = 1; if (bar.foo.my_gen_block[0].baz) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_attr_parenstar.v0000664000177100017500000000142213702133367022237 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @(*) begin if (clk) begin end end always @(* ) begin if (clk) begin end end // Not legal in some simulators, legal in others // always @(* /*cmt*/ ) begin // if (clk) begin end // end // Not legal in some simulators, legal in others // always @(* // cmt // ) begin // if (clk) begin end // end always @ (* ) begin if (clk) begin end end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_altera_lpm_clshift.pl0000775000177100017500000000120613702133367023213 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_package_verb.pl0000775000177100017500000000105313702133370021762 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_concat5.pl0000775000177100017500000000106013702133367021542 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_bit_sel.v0000664000177100017500000000136713702133370022011 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // We see Verilator assumes a 1-bit parameter is a scalar rather than a 1-bit // long vector. This causes the following code to fail. // // Other event drive simulators accept this. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // At this point it is ambiguous whether a is scalar or vector parameter a = 1'b0; wire b = a[0]; // Note however b[0] is illegal. always @(posedge clk) begin if (b == 1'b0) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-4.038/test_regress/t/t_tri_array_bufif.v0000664000177100017500000000606613702133370022360 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; parameter DW = 4; wire [3:0] drv_a = crc[3:0]; wire [3:0] drv_b = crc[7:4]; wire [3:0] drv_e = crc[19:16]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [DW-1:0] drv; // To/From test1 of Test1.v wire [DW-1:0] drv2; // From test2 of Test2.v // End of automatics Test1 test1 (/*AUTOINST*/ // Inouts .drv (drv[DW-1:0]), // Inputs .drv_a (drv_a[DW-1:0]), .drv_b (drv_b[DW-1:0]), .drv_e (drv_e[DW-1:0])); Test2 test2 (/*AUTOINST*/ // Outputs .drv2 (drv2[DW-1:0]), // Inputs .drv_a (drv_a[DW-1:0]), .drv_b (drv_b[DW-1:0]), .drv_e (drv_e[DW-1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, drv}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x drv=%x %x (%b??%b:%b)\n",$time, cyc, crc, drv, drv2, drv_e,drv_a,drv_b); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin if (drv2 != drv) $stop; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hd95d216c5a2945d0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test1 #( parameter DW = 4 )( input wire [DW-1:0] drv_a, input wire [DW-1:0] drv_b, input wire [DW-1:0] drv_e, inout wire [DW-1:0] drv ); wire drv_0, drv_1, drv_2, drv_3; bufif1 bufa0 (drv_0, drv_a[0], drv_e[0]); bufif1 bufb0 (drv_0, drv_b[0], ~drv_e[0]); bufif1 bufa1 (drv_1, drv_a[1], drv_e[1]); bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]); bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]); bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]); bufif1 bufa3 (drv_3, drv_a[3], drv_e[3]); bufif1 bufb3 (drv_3, drv_b[3], ~drv_e[3]); assign drv = {drv_3,drv_2,drv_1,drv_0}; endmodule module Test2 #( parameter DW = 4 )( input wire [DW-1:0] drv_a, input wire [DW-1:0] drv_b, input wire [DW-1:0] drv_e, inout wire [DW-1:0] drv2 ); wire [DW-1:0] drv_all; bufif1 bufa [DW-1:0] (drv_all, drv_a, drv_e); // Below ~= bufif1 bufb [DW-1:0] (drv_all, drv_b, ~drv_e); bufif1 bufb [DW-1:0] ({drv_all[3], drv_all[2], drv_all[1], drv_all[0]}, {drv_b[3], drv_b[2], drv_b[1], drv_b[0]}, {~drv_e[3], ~drv_e[2], ~drv_e[1], ~drv_e[0]}); assign drv2 = drv_all; endmodule verilator-4.038/test_regress/t/t_wire_behp1364_bad.pl0000775000177100017500000000116713702133370022447 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only --language 1364-2001"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_altera_lpm_ram_dp.pl0000775000177100017500000000120613702133367023021 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_context_bad.v0000664000177100017500000000043013702133370022461 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); wire [2:0] foo = 5'b11111; endmodule verilator-4.038/test_regress/t/t_for_local.pl0000775000177100017500000000105313702133370021311 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_in_assign_bad.pl0000775000177100017500000000131513702133370023002 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2005 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only --Mdir obj_lint_only"], fails => 1, expect_filename => $Self->{golden_filename}, ); (!-d "obj_lint_only") or error("%Error: lint-only shouldn't make output directory"); ok(1); 1; verilator-4.038/test_regress/t/t_inst_signed1.v0000664000177100017500000000177513702133370021602 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg signed i; wire signed o1; wire signed o2; integer cyc; initial cyc=0; sub1 sub1 (.i(i), .o(o1)); sub2 sub2 (.i(o1), .o(o2)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin i <= 1'b0; end else if (cyc==1) begin if (o2 != 1'b0) $stop; i <= 1'b1; end else if (cyc==2) begin if (o2 != 1'b1) $stop; end if (cyc==3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule //msg2540 module sub1 ( input signed i, output wire signed o); assign o = ~i; endmodule module sub2 (i,o); input signed i; output signed o; wire signed o = ~i; endmodule verilator-4.038/test_regress/t/t_enum_size.pl0000775000177100017500000000105313702133370021347 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_trig.v0000664000177100017500000001250113702133370021156 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; real r, r2; integer cyc=0; task check(integer line, real got, real ex); if (got != ex) begin if ((got > ex ? got - ex : ex - got) > 0.000001) begin $display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex); $stop; end end endtask initial begin // Check constant propagation // Note $abs is not defined in SystemVerilog (as of 2012) check(`__LINE__, $ceil(-1.2), -1); check(`__LINE__, $ceil(1.2), 2); check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125); check(`__LINE__, $exp(0.0), 1); check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375); check(`__LINE__, $floor(-1.2), -2); check(`__LINE__, $floor(1.2), 1); check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625); //check(`__LINE__, $ln(0), 0); // Bad value //check(`__LINE__, $ln(-1.2), 0); // Bad value check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875); //check(`__LINE__, $log10(0), 0); // Bad value //check(`__LINE__, $log10(-1.2), 0); check(`__LINE__, $pow(2.3,1.2), 2.71689843249914897427288451581262052059173583984375); check(`__LINE__, $pow(2.3,-1.2), 0.368066758785732861536388327294844202697277069091796875); //check(`__LINE__, $pow(-2.3,1.2),0); // Bad value check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125); //check(`__LINE__, $sqrt(-1.2), 0); // Bad value check(`__LINE__, ((1.5)**(1.25)), 1.660023); check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1 check(`__LINE__, $acosh(1.2), 0.622362503); check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1 check(`__LINE__, $asinh(1.2), 1.015973134); check(`__LINE__, $atan (0.2), 0.197395559); check(`__LINE__, $atan2(0.2,2.3), 0.086738338); // Arg1 is -1..1 check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1 check(`__LINE__, $cos (1.2), 0.362357754); check(`__LINE__, $cosh (1.2), 1.810655567); check(`__LINE__, $hypot(1.2,2.3), 2.594224354); check(`__LINE__, $sin (1.2), 0.932039085); check(`__LINE__, $sinh (1.2), 1.509461355); check(`__LINE__, $tan (1.2), 2.572151622); check(`__LINE__, $tanh (1.2), 0.833654607); end real sum_ceil; real sum_exp; real sum_floor; real sum_ln; real sum_log10; real sum_pow1; real sum_pow2; real sum_sqrt; real sum_acos; real sum_acosh; real sum_asin; real sum_asinh; real sum_atan; real sum_atan2; real sum_atanh; real sum_cos ; real sum_cosh; real sum_hypot; real sum_sin; real sum_sinh; real sum_tan; real sum_tanh; // Test loop always @ (posedge clk) begin r = $itor(cyc)/10.0 - 5.0; // Crosses 0 `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n",$time, cyc, r, sum_ln); `endif cyc <= cyc + 1; if (cyc==0) begin end else if (cyc<90) begin // Setup sum_ceil += 1.0+$ceil(r); sum_exp += 1.0+$exp(r); sum_floor += 1.0+$floor(r); if (r > 0.0) sum_ln += 1.0+$ln(r); if (r > 0.0) sum_log10 += 1.0+$log10(r); // Pow requires if arg1<0 then arg1 integral sum_pow1 += 1.0+$pow(2.3,r); if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3); if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r); if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r); if (r>=1.0) sum_acosh += 1.0+$acosh(r); if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r); sum_asinh += 1.0+$asinh(r); sum_atan += 1.0+$atan (r); if (r>=-1.0 && r<=1.0) sum_atan2 += 1.0+$atan2(r,2.3); if (r>=-1.0 && r<=1.0) sum_atanh += 1.0+$atanh(r); sum_cos += 1.0+$cos (r); sum_cosh += 1.0+$cosh (r); sum_hypot += 1.0+$hypot(r,2.3); sum_sin += 1.0+$sin (r); sum_sinh += 1.0+$sinh (r); sum_tan += 1.0+$tan (r); sum_tanh += 1.0+$tanh (r); end else if (cyc==99) begin check (`__LINE__, sum_ceil, 85); check (`__LINE__, sum_exp, 608.06652950); check (`__LINE__, sum_floor, 4); check (`__LINE__, sum_ln, 55.830941633); check (`__LINE__, sum_log10, 46.309585076); check (`__LINE__, sum_pow1, 410.98798177); check (`__LINE__, sum_pow2, 321.94765689); check (`__LINE__, sum_sqrt, 92.269677253); check (`__LINE__, sum_acos, 53.986722862); check (`__LINE__, sum_acosh, 72.685208498); check (`__LINE__, sum_asin, 21); check (`__LINE__, sum_asinh, 67.034973416); check (`__LINE__, sum_atan, 75.511045389); check (`__LINE__, sum_atan2, 21); check (`__LINE__, sum_atanh, 0); check (`__LINE__, sum_cos, 72.042023124); check (`__LINE__, sum_cosh, 1054.0178222); check (`__LINE__, sum_hypot, 388.92858406); check (`__LINE__, sum_sin, 98.264184989); check (`__LINE__, sum_sinh, -356.9512927); check (`__LINE__, sum_tan, 1.7007946043); check (`__LINE__, sum_tanh, 79.003199681); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_trace_ena_cc.out0000664000177100017500000000253213702133370022133 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sat Jan 27 15:03:24 2018 $end $timescale 1ps $end $scope module top $end $var wire 1 ' clk $end $scope module t $end $var wire 32 $ c_trace_on [31:0] $end $var wire 1 ' clk $end $var wire 32 # cyc [31:0] $end $var real 64 % r $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # b00000000000000000000000000000000 $ r0 % 0' #10 b00000000000000000000000000000010 # r0.1 % 1' #15 0' #20 b00000000000000000000000000000011 # b00000000000000000000000000000001 $ r0.2 % 1' #25 0' #30 b00000000000000000000000000000100 # b00000000000000000000000000000010 $ r0.3 % 1' #35 0' #40 b00000000000000000000000000000101 # b00000000000000000000000000000011 $ r0.4 % 1' #45 0' #50 b00000000000000000000000000000110 # b00000000000000000000000000000100 $ r0.5 % 1' #55 0' #60 b00000000000000000000000000000111 # b00000000000000000000000000000101 $ r0.6 % 1' #65 0' #70 b00000000000000000000000000001000 # b00000000000000000000000000000110 $ r0.7 % 1' #75 0' #80 b00000000000000000000000000001001 # b00000000000000000000000000000111 $ r0.7999999999999999 % 1' #85 0' #90 b00000000000000000000000000001010 # b00000000000000000000000000001000 $ r0.8999999999999999 % 1' #95 0' #100 1' b00000000000000000000000000001011 # b00000000000000000000000000001001 $ r0.9999999999999999 % verilator-4.038/test_regress/t/t_flag_werror_bad1.out0000664000177100017500000000061213702133370022742 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_inst_tree_inl0_pub0.pl0000775000177100017500000000245713702133370023226 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_tree.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( v_flags2 => ["$Self->{t_dir}/$Self->{name}.vlt"], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, expect => '\] (%m|.*t\.ps): Clocked ', ); ok(1); 1; verilator-4.038/test_regress/t/t_param_array5.v0000664000177100017500000000165413702133370021572 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1578 module t; parameter N = 4; typedef logic array_t[N]; parameter array_t MASK = mask_array(); //TODO bug1578: parameter MASK = mask_array(); function array_t mask_array(); for(int i = 0; i < N; i++) begin mask_array[i] = i[0]; end endfunction array_t norm; initial begin if (N != 4) $stop; norm = mask_array(); if (norm[0] != 1'b0) $stop; if (norm[1] != 1'b1) $stop; if (norm[2] != 1'b0) $stop; if (norm[3] != 1'b1) $stop; if (MASK[0] != 1'b0) $stop; if (MASK[1] != 1'b1) $stop; if (MASK[2] != 1'b0) $stop; if (MASK[3] != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_bit_sel.pl0000775000177100017500000000105313702133370022152 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_lib_inc.vh0000664000177100017500000000034713702133370021453 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define WIDTH 10 verilator-4.038/test_regress/t/t_interface_modport_import_noinl.pl0000775000177100017500000000116513702133370025652 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_modport_import.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_noop_bad.v0000664000177100017500000000050713702133370021755 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); int u1; int u1; int u1; int u1; int u1; int u1; int u1; endmodule verilator-4.038/test_regress/t/t_preproc_persist_inc.v0000664000177100017500000000043413702133370023256 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef COMMON_GUARD `define COMMON_GUARD 1 Inside `__FILE__. `endif verilator-4.038/test_regress/t/t_x_assign.v0000664000177100017500000000074613702133370021023 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t_x_assign( input wire clk, output reg o ); always @(posedge clk) begin if (1'bx) o <= 1'd1; else o <= 1'd0; end endmodule verilator-4.038/test_regress/t/t_inst_missing.v0000664000177100017500000000107713702133370021714 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); wire ok = 1'b0; // verilator lint_off PINNOCONNECT // verilator lint_off PINCONNECTEMPTY sub sub (.ok(ok), , .nc()); // verilator lint_on PINCONNECTEMPTY // verilator lint_on PINNOCONNECT endmodule module sub (input ok, input none, input nc); initial if (ok && none && nc) begin end // No unused warning endmodule verilator-4.038/test_regress/t/t_lint_width_bad.pl0000775000177100017500000000107613702133370022331 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_packed_sysfunct.v0000664000177100017500000001451013702133367023573 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); // parameters for array sizes localparam WA = 4; localparam WB = 6; localparam WC = 8; // 2D packed arrays logic [WA+1:2] [WB+1:2] [WC+1:2] array_bg; // big endian array /* verilator lint_off LITENDIAN */ logic [2:WA+1] [2:WB+1] [2:WC+1] array_lt; // little endian array /* verilator lint_on LITENDIAN */ logic [1:0] array_unpk [3:2][1:0]; integer cnt = 0; integer slc = 0; // slice type integer dim = 0; // dimension integer wdt = 0; // width initial begin `checkh($dimensions (array_unpk), 3); `ifndef VCS `checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009 `endif `checkh($bits (array_unpk), 2*2*2); `checkh($low (array_unpk), 2); `checkh($high (array_unpk), 3); `checkh($left (array_unpk), 3); `checkh($right(array_unpk), 2); `checkh($increment(array_unpk), 1); `checkh($size (array_unpk), 2); end // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin $write("*-* All Finished *-*\n"); $finish; end integer slc_next; // calculation of dimention sizes always @ (posedge clk) begin // slicing type counter case (cnt[3:2]) 2'd0 : begin slc_next = 0; end // full array 2'd1 : begin slc_next = 1; end // single array element 2'd2 : begin slc_next = 2; end // half array default: begin slc_next = 0; end endcase slc <= slc_next; // dimension counter case (cnt[1:0]) 2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end 2'd1 : begin dim <= 2; wdt <= WB; end 2'd2 : begin dim <= 3; wdt <= WC; end default: begin dim <= 0; wdt <= 0; end endcase end always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); `endif if (cnt[30:4]==1) begin // big endian if (slc==0) begin // full array `checkh($dimensions (array_bg), 3); `checkh($bits (array_bg), WA*WB*WC); if ((dim>=1)&&(dim<=3)) begin `checkh($left (array_bg, dim), wdt+1); `checkh($right (array_bg, dim), 2 ); `checkh($low (array_bg, dim), 2 ); `checkh($high (array_bg, dim), wdt+1); `checkh($increment (array_bg, dim), 1 ); `checkh($size (array_bg, dim), wdt ); end end else if (slc==1) begin // single array element `checkh($dimensions (array_bg[2]), 2); `checkh($bits (array_bg[2]), WB*WC); if ((dim>=2)&&(dim<=3)) begin `checkh($left (array_bg[2], dim-1), wdt+1); `checkh($right (array_bg[2], dim-1), 2 ); `checkh($low (array_bg[2], dim-1), 2 ); `checkh($high (array_bg[2], dim-1), wdt+1); `checkh($increment (array_bg[2], dim-1), 1 ); `checkh($size (array_bg[2], dim-1), wdt ); end `ifndef VERILATOR // Unsupported slices don't maintain size correctly end else if (slc==2) begin // half array `checkh($dimensions (array_bg[WA/2+1:2]), 3); `checkh($bits (array_bg[WA/2+1:2]), WA/2*WB*WC); if ((dim>=1)&&(dim<=3)) begin `checkh($left (array_bg[WA/2+1:2], dim), wdt+1); `checkh($right (array_bg[WA/2+1:2], dim), 2 ); `checkh($low (array_bg[WA/2+1:2], dim), 2 ); `checkh($high (array_bg[WA/2+1:2], dim), wdt+1); `checkh($increment (array_bg[WA/2+1:2], dim), 1 ); `checkh($size (array_bg[WA/2+1:2], dim), wdt); end `endif end end else if (cnt[30:4]==2) begin // little endian if (slc==0) begin // full array `checkh($dimensions (array_lt), 3); `checkh($bits (array_lt), WA*WB*WC); if ((dim>=1)&&(dim<=3)) begin `checkh($left (array_lt, dim), 2 ); `checkh($right (array_lt, dim), wdt+1); `checkh($low (array_lt, dim), 2 ); `checkh($high (array_lt, dim), wdt+1); `checkh($increment (array_lt, dim), -1 ); `checkh($size (array_lt, dim), wdt ); end end else if (slc==1) begin // single array element `checkh($dimensions (array_lt[2]), 2); `checkh($bits (array_lt[2]), WB*WC); if ((dim>=2)&&(dim<=3)) begin `checkh($left (array_lt[2], dim-1), 2 ); `checkh($right (array_lt[2], dim-1), wdt+1); `checkh($low (array_lt[2], dim-1), 2 ); `checkh($high (array_lt[2], dim-1), wdt+1); `checkh($increment (array_lt[2], dim-1), -1 ); `checkh($size (array_lt[2], dim-1), wdt ); end `ifndef VERILATOR // Unsupported slices don't maintain size correctly end else if (slc==2) begin // half array `checkh($dimensions (array_lt[2:WA/2+1]), 3); `checkh($bits (array_lt[2:WA/2+1]), WA/2*WB*WC); if ((dim>=1)&&(dim<=3)) begin `checkh($left (array_lt[2:WA/2+1], dim), 2 ); `checkh($right (array_lt[2:WA/2+1], dim), wdt+1); `checkh($low (array_lt[2:WA/2+1], dim), 2 ); `checkh($high (array_lt[2:WA/2+1], dim), wdt+1); `checkh($increment (array_lt[2:WA/2+1], dim), -1 ); `checkh($size (array_lt[2:WA/2+1], dim), wdt ); end `endif end end end endmodule verilator-4.038/test_regress/t/t_tri_array.v0000664000177100017500000000320113702133370021171 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; parameter NPAD = 4; tri pad [NPAD-1:0]; // Array wire [NPAD-1:0] data0 = crc[0 +: 4]; wire [NPAD-1:0] data1 = crc[8 +: 4]; wire [NPAD-1:0] en = crc[16 +: 4]; for (genvar g=0; g> 33 {in}}; endmodule verilator-4.038/test_regress/t/t_fork.pl0000775000177100017500000000107113702133370020312 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_top_bad.v0000664000177100017500000000074313702133370022635 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; logic [3:0] value; logic reset; modport counter_mp (input reset, output value); modport core_mp (output reset, input value); endinterface module t (// Inputs input clk, ifc.counter_mp c_data ); integer cyc=1; endmodule verilator-4.038/test_regress/t/t_flag_debugi9.pl0000775000177100017500000000120113702133370021665 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( v_flags2 => ["--debug --debugi 9"], tee => 0, verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); ok(1); 1; verilator-4.038/test_regress/t/t_alw_nosplit.pl0000775000177100017500000000126513702133367021717 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats"], ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); } execute( check_finished=>1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_concat64.v0000664000177100017500000001533413702133370021641 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [127:0] i; wire [127:0] q1; wire [127:0] q32; wire [127:0] q64; wire [63:0] q64_low; assign q1 = { i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1], i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; assign q64[127:64] = { i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; assign q64[63:0] = { i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; assign q64_low = { i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; assign q32[127:96] = { i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]}; assign q32[95:64] = { i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; assign q32[63:32] = { i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]}; assign q32[31:0] = { i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%x %x\n", q1, i); `endif if (cyc==1) begin i <= 128'hed388e646c843d35de489bab2413d770; end if (cyc==2) begin i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3; if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop; if (q1 != q32) $stop; if (q1 != q64) $stop; if (q1[63:0] != q64_low) $stop; end if (cyc==3) begin i <= 128'he236ddfddddbdad20a48e039c9f395b8; if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop; if (q1 != q32) $stop; if (q1 != q64) $stop; if (q1[63:0] != q64_low) $stop; end if (cyc==4) begin i <= 128'h45e0eb7642b148537491f3da147e7f26; if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop; if (q1 != q32) $stop; if (q1 != q64) $stop; if (q1[63:0] != q64_low) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_display_esc_bad.v0000664000177100017500000000046013702133370022306 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $display("\x\y\z"); // Illegal escapes end endmodule verilator-4.038/test_regress/t/t_sys_readmem_bad_end.v0000664000177100017500000000064313702133370023150 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; integer i; initial begin $readmemh("t/t_sys_readmem_bad_end.mem", hex, 0, 15); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_array.v0000664000177100017500000000117013702133370021474 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer cyc=0; // Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk typedef struct packed { logic [1024*1024:0] d; } s1_t; // 128 b s1_t biggie; always @ (posedge clk) begin cyc <= cyc + 1; biggie [ cyc +: 32 ] <= 32'hfeedface; if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_sv_cpu_code/0000775000177100017500000000000013702335701021305 5ustar wsnyderwsnyderverilator-4.038/test_regress/t/t_sv_cpu_code/pads_if.sv0000664000177100017500000000574713702133370023277 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. interface pads_if(); // *************************************************************************** // Local Parameters // *************************************************************************** localparam NUMPADS = $size( pinout ); // *************************************************************************** // Interface Variables // *************************************************************************** // - PADS Digital Interface - logic pullup_en [1:NUMPADS];// Pull-up/down/bus-keeper enable. logic pulldown_en [1:NUMPADS];// Pull direction (0:Pull-up; 1:Pull-down). logic output_en [1:NUMPADS];// Digital output buffer enable. logic output_val [1:NUMPADS];// Digital output value. logic input_en [1:NUMPADS];// Digital input buffer enable. logic slew_limit_en [1:NUMPADS];// Slew rate limiter enable. logic input_val [1:NUMPADS];// Digital input value. // - PADS Analog Interface - logic ana_override [1:NUMPADS];// Disables digital output when driving analog output. wire ana [1:NUMPADS]; // *************************************************************************** // Modports // *************************************************************************** modport mp_pads( input pullup_en, input pulldown_en, input output_en, input output_val, input slew_limit_en, input input_en, output input_val, input ana_override, inout ana ); modport mp_dig( import IsPad, import IsPort, import Init, output pullup_en, output pulldown_en, output output_en, output output_val, output slew_limit_en, output input_en, input input_val ); modport mp_ana( import IsPad, output ana_override, inout ana ); // *************************************************************************** // Check for which pins exists // *************************************************************************** bit [PINID_D7:PINID_A0] exists; function automatic void Init( ); exists = {(PINID_D7+1){1'b0}}; for ( int i = 1; i <= $size( pinout ); i++ ) if ( PINID_D7 >= pinout[i].id ) exists[pinout[i].id] = 1'b1; endfunction // *************************************************************************** // Functions and Tasks // *************************************************************************** function automatic bit IsPad( integer i ); IsPad = exists[i]; endfunction function automatic bit IsPort( integer i ); IsPort = |exists[8*i+:8]; endfunction endinterface // pads_if verilator-4.038/test_regress/t/t_sv_cpu_code/ac_dig.sv0000664000177100017500000000651713702133370023074 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module ac_dig #( parameter ID = 1 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** genbus_if.slave dbus, // **** Outputs **** output logic acenable, // **** Inputs **** input logic acout, // - System - input logic clk, input logic rst ); // *************************************************************************** // Regs and Wires // *************************************************************************** // **** Internal Data Bus **** logic [15:0] sdata; logic ws; logic [15:0] mdata; logic [15:0] adr; logic [1:0] we; logic [1:0] re; // **** User Registers **** struct packed { logic [7:1] reserved; logic enable; } control; struct packed { logic [7:1] reserved; logic acout; } status; // **** Internals **** logic [1:0] sync; // *************************************************************************** // Assignments // *************************************************************************** assign acenable = control.enable; // *************************************************************************** // "dbus" Connection // *************************************************************************** always_comb begin `ifdef VERILATOR //TODO dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr ), .we(we), .re(re) ); `else dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr[1:0]), .we(we), .re(re) ); `endif // dbus.sConnect( ID, rst, sdata, ws, mdata, adr, we, re ); end // *************************************************************************** // Register Access // *************************************************************************** // **** Register Write **** always_ff @( posedge clk ) begin if ( rst ) control <= 8'h00; else if ( (adr[1:0] == 2'b00) & we[0] ) control <= mdata[7:0]; end // **** Regiser Read **** always_comb begin: RegisterRead // - Local Variables - logic [7:0] data[0:3]; // Read access concatination. // - Setup read multiplexer - data = '{ control, status, 8'h00, 8'h00 }; // - Connect "genbusif" - sdata = { 8'h00, data[ adr[1:0] ] }; ws = 1'b0; end // *************************************************************************** // Status // *************************************************************************** // **** Synchronization **** always_ff @( posedge clk ) begin if ( rst ) sync <= 2'b00; else if ( control.enable ) sync <= {sync[0], acout}; end always_comb begin // - Defaults - status = {$size(status){1'b0}}; // - Set register values - status.acout = sync[1]; end endmodule // ac_dig verilator-4.038/test_regress/t/t_sv_cpu_code/pad_gpio.sv0000664000177100017500000000215513702133370023442 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. //***************************************************************************** // PAD_GPIO - General Purpose I/O Pad (Dummy!!!!) //***************************************************************************** module pad_gpio #( parameter ID = 0 ) ( input logic pullup_en, input logic pulldown_en, input logic output_en, input logic output_val, input logic slew_limit_en, input logic input_en, output logic input_val, inout wire ana, inout wire pad ); // **** Analog <-> pad connection **** `ifndef VERILATOR //TODO alias alias ana = pad; `endif // **** Digital driver <-> pad connection **** assign pad = (output_en) ? output_val : 1'bz; // **** Digital pull-up/pull-down <-> pad connection **** // TO BE ADDED!!!! // **** Digital input <-> pad connection **** assign input_val = (input_en) ? pad : 1'b0; endmodule // pad_gpio verilator-4.038/test_regress/t/t_sv_cpu_code/ac.sv0000664000177100017500000000355113702133370022244 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module ac #( parameter ID = 1 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** genbus_if.slave dbus, pads_if.mp_ana padsif, // - System - input logic clk, input logic rst ); // *************************************************************************** // Regs and Wires, Automatics // *************************************************************************** /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic acenable; // From i_ac_dig of ac_dig.v logic acout; // From i_ac_ana of ac_ana.v // End of automatics // *************************************************************************** // Digital Control // *************************************************************************** ac_dig #( .ID(ID) ) i_ac_dig ( .dbus (dbus), /*AUTOINST*/ // Outputs .acenable (acenable), // Inputs .acout (acout), .clk (clk), .rst (rst)); // *************************************************************************** // Analog Model // *************************************************************************** ac_ana i_ac_ana ( .padsif (padsif), /*AUTOINST*/ // Outputs .acout (acout), // Inputs .acenable (acenable), .clk (clk), .rst (rst)); endmodule // ac verilator-4.038/test_regress/t/t_sv_cpu_code/cpu.sv0000664000177100017500000001342713702133370022453 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module cpu #( parameter // ... ID = 1 ) // Not used! ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** genbus_if.master dbus, // **** Outputs **** // N/A // **** Inputs **** input logic clk, input logic rst ); // *************************************************************************** // Regs and Wires // *************************************************************************** // **** Program Memory **** logic [15:0] rom_out; // **** Register File (RF) **** logic [7:0] rf[0:15]; // **** Fetch Stage **** logic [7:0] pc; // PC -> Program counter. logic [15:0] ir; // IR -> Instruction Register. // **** Decode **** logic [3:0] idec_rd; logic idec_rd_we; logic [7:0] idec_rd_data; logic [3:0] idec_rs; logic [7:0] idec_nextpc; // New PC if change of program flow. logic idec_coff; // Indicates a change of program flow. logic [7:0] idec_mem_adr; logic idec_mem_re; logic idec_mem_we; // **** Memory **** logic [7:0] mem_data; // Data from peripheral. logic mem_ws; // Waitstate. // *************************************************************************** // Program Memory (ROM) Interface // *************************************************************************** always_comb begin: ROM // - Local Variables - integer i; reg [15:0] irom [0:255]; // - Set default - for ( i = 0; i < 256; i++ ) begin if ( i < $size(rom) ) irom[i] = rom[i]; else irom[i] = 16'h0000; end rom_out = irom[pc[7:0]]; end // *************************************************************************** // Register File (RF) // *************************************************************************** always_ff @( posedge clk ) begin: RegFile // - Local Variables - integer i; // - Register File - for ( i = 0; i < 16; i++ ) begin if ( rst ) rf[i][7:0] <= 8'h00; else if ( idec_rd_we & (idec_rd == i[3:0]) ) rf[i] <= idec_rd_data; end end // *************************************************************************** // Fetch Stage // *************************************************************************** // **** Program Counter (PC) / Instruction Register (IR) **** always_ff @( posedge clk ) begin if ( rst ) begin pc <= 8'h00; ir <= 16'h0000; end else //if ( ~mem_ws ) begin if ( ~idec_coff ) begin pc <= pc + 1; ir <= rom_out; // Fetch Instruction. end else begin pc <= idec_nextpc; ir <= 16'h0000; // Insert no operation (NOP). end end end // *************************************************************************** // Decode/Execute Stage // *************************************************************************** always_comb begin // - Defaults - idec_rd = 4'h0; idec_rd_we = 1'b0; idec_rd_data = 8'h00; idec_rs = 4'h0; idec_nextpc = 8'h00; idec_coff = 1'b0; idec_mem_adr = 8'h00; idec_mem_re = 1'b0; idec_mem_we = 1'b0; // verilator lint_off CASEINCOMPLETE casez ( ir ) 16'h0000:; // NOP (<=> Default) 16'h1???: // JMP imm begin idec_nextpc = ir[7:0]; idec_coff = 1'b1; end 16'h4???: // LDI rd, imm begin idec_rd = ir[8+:4]; idec_rd_we = 1'b1; idec_rd_data = ir[0+:8]; end 16'h8???: begin // STS imm, rs idec_mem_adr = ir[0+:8]; idec_mem_we = 1'b1; idec_rs = ir[8+:4]; end 16'h9???: begin // LDS rd, imm idec_mem_adr = ir[0+:8]; idec_mem_we = 1'b1; idec_rd = ir[8+:4]; idec_rd_we = 1'b1; idec_rd_data = mem_data[0+:8]; end endcase end // *************************************************************************** // Memory Access ("Stage") // *************************************************************************** // **** Connect to "dbus" **** always_comb begin: Conntect reg [15:0] sdata16; dbus.mConnect ( ID, // ID sdata16, // sdata mem_ws, // ws {2{rf[idec_rs]}}, // mdata // adr {8'h00, idec_mem_adr[7:1], 1'b0}, // we {idec_mem_adr[0],~idec_mem_adr[0]} & {2{idec_mem_we}}, // re {idec_mem_adr[0],~idec_mem_adr[0]} & {2{idec_mem_re}} ); // - Connect 16-bit databus to 8-bit CPU - mem_data = ( idec_mem_adr[0] ) ? sdata16[15:8] : sdata16[7:0]; end mPreAdrDecode_resp busproperty; always_comb begin: PreAdrDecode // verilator lint_off WIDTH busproperty = dbus.mPreAdrDecode( 0, idec_mem_adr ); // verilator lint_on WIDTH end endmodule // cpu verilator-4.038/test_regress/t/t_sv_cpu_code/pads_h.sv0000664000177100017500000000541713702133370023122 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. `ifndef _PADS_H_SV_ `define _PADS_H_SV_ // ***************************************************************************** // // ***************************************************************************** // **** Pin Identifiers **** typedef enum int { PINID_A0 = 32'd0, // MUST BE ZERO! // - Standard Ports - PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7, PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7, PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7, PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7, PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7, PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7, PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7, PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7, // PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1 PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7, PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7, PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7, PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7, PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7, // PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0 PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7, PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7, PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7, // - AUX Port (Custom) - PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7, // - PDI Port - PINID_D2W_DAT, PINID_D2W_CLK, // - Power Pins - PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3, PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3, // - Maximum number of pins - PINID_MAX } t_pinid; // **** Pad types **** typedef enum int { PADTYPE_DEFAULT = 32'd0, PADTYPE_GPIO, // General Purpose I/O Pad (GPIO). PADTYPE_GPIO_ANA, // GPIO with Analog connection. Low noise GPIO. PADTYPE_GPIO_HDS, // GPIO with High Drive Strength. PADTYPE_VDD, // VDD Supply Pad PADTYPE_GND // Ground Pad } t_padtype; `endif // !`ifdef _PADS_H_SV_ verilator-4.038/test_regress/t/t_sv_cpu_code/pads.sv0000664000177100017500000000527713702133370022617 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module pads #( parameter NUMPADS = $size( pinout ) ) ( // *************************************************************************** // Module Interface // *************************************************************************** // **** Interfaces **** pads_if.mp_pads padsif, // **** Pinout **** `ifdef VERILATOR // see t_tri_array inout wire [NUMPADS:1] pad, `else inout wire pad [1:NUMPADS], `endif // **** Inputs **** input logic clk, input logic rst ); // *************************************************************************** // Code Section // *************************************************************************** `ifdef VERILATOR // see t_tri_array tri [NUMPADS:1] _anahack; `endif genvar i; for ( i = 1; i <= NUMPADS; i++ ) begin `ifdef VCS localparam t_padtype p_type = t_padtype'(pinout_wa[i][pinout_wa_padtype]); localparam t_pinid p_id = t_pinid'(pinout_wa[i][pinout_wa_id]); `else localparam t_padtype p_type = pinout[i].padtype; localparam t_pinid p_id = pinout[i].id; `endif case ( p_type ) PADTYPE_GPIO: pad_gpio #( .ID( i ) ) i_pad_gpio( .pad (pad [i]), // Outputs .input_val (padsif.input_val [i]), // Inouts `ifdef VERILATOR // see t_tri_array .ana (_anahack [i]), `else .ana (padsif.ana [i]), `endif // Inputs .pullup_en (padsif.pullup_en [i]), .pulldown_en (padsif.pulldown_en [i]), .output_en (padsif.output_en [i]), .output_val (padsif.output_val [i]), .slew_limit_en (padsif.slew_limit_en[i]), .input_en (padsif.input_en [i]) /*AUTOINST*/); PADTYPE_VDD: begin pad_vdd #( .ID( i ) ) i_pad_vdd( .pad (pad[i]) /*AUTOINST*/); // Not SV standard, yet... assign padsif.input_val[i] = (); end PADTYPE_GND: begin pad_gnd #( .ID( i ) ) i_pad_gnd(.pad (pad[i]) /*AUTOINST*/); end endcase end endmodule // pads verilator-4.038/test_regress/t/t_sv_cpu_code/ports.sv0000664000177100017500000001025313702133370023025 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. `ifdef VERILATOR //TODO `define PACKED packed `else `define packed `endif module ports #( parameter ID = 1 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** genbus_if.slave dbus, pads_if.mp_dig padsif, // - System - input logic clk, input logic rst ); // *************************************************************************** // Regs and Wires // *************************************************************************** // **** Internal Data Bus **** logic [15:0] sdata; logic ws; logic [15:0] mdata; logic [15:0] adr; logic [1:0] we; logic [1:0] re; // **** Interal Registers **** struct `PACKED { logic [7:0][1:0] in; logic [7:0] dir; logic [7:0] out; struct `PACKED { logic [7:2] reserved; logic pullupen; logic slewlim; } cfg; } port [PORTID_A:PORTID_D]; // *************************************************************************** // "dbus" Connection // *************************************************************************** always_comb begin: dbus_Connect dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr), .we(we), .re(re) ); end // *************************************************************************** // Register Access // For PORTA...PORTD (Excluding I and O) // +0x00 DIR // +0x01 OUT // +0x02 IN // +0x03 CFG // *************************************************************************** always_comb begin padsif.Init(); end // **** Register Write **** always_ff @( posedge clk ) begin // - Local Variables - integer i, j; // **** Setup Port Registers **** for ( j = PORTID_A; j <= PORTID_D; j++ ) begin if ( padsif.IsPort( j ) ) begin if ( ((adr[3:2] == j[1:0]) && (adr[1] == 1'b0)) | rst ) begin if ( we[0] ) port[j].dir <= mdata[7:0]; if ( we[1] ) port[j].out <= mdata[15:8]; end end else begin port[j].dir <= 8'h00; port[j].out <= 8'h00; end end end // **** Regiser Read **** always_comb begin: RegisterRead // - Local Variables - integer i, j; logic [7:0] data [PORTID_D:PORTID_A][3:0]; // **** Output to "dbus" **** // - Setup read multiplexer - for ( j = PORTID_A; j <= PORTID_D; j++ ) begin if ( padsif.IsPort( j ) ) data[j] = '{ port[j].dir, port[j].out, 8'h00, 8'h00 }; else data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 }; end // - Connect "genbusif" - sdata = { 8'h00, data[ adr[3:2] ][ adr[1:0] ] }; ws = 1'b0; end // *************************************************************************** // Output // *************************************************************************** always_comb begin // - Local Variables - integer i, j; // **** Defaults **** for ( i = 1; i <= $size( pinout ); i++ ) begin padsif.pullup_en [i] = 1'b0; padsif.pulldown_en [i] = 1'b0; padsif.output_en [i] = 1'b0; padsif.output_val [i] = 1'b0; padsif.slew_limit_en[i] = 1'b0; padsif.input_en [i] = 1'b0; end // **** Connect to Pads **** for ( i = 1; i <= $size( pinout ); i++ ) begin j = pinout[i].id; if ( PINID_D7 >= j ) begin padsif.output_en [i] = port[j[4:3]].dir[j[2:0]]; padsif.output_val[i] = port[j[4:3]].out[j[2:0]]; end end end endmodule // ports verilator-4.038/test_regress/t/t_sv_cpu_code/pad_gnd.sv0000664000177100017500000000104213702133370023246 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. //***************************************************************************** // PAD_GND - Ground Supply Pad (Dummy!!!!) //***************************************************************************** module pad_gnd #( parameter ID = 0 ) ( inout wire pad ); assign pad = 1'b0; endmodule // pad_gnd verilator-4.038/test_regress/t/t_sv_cpu_code/timescale.sv0000664000177100017500000000044413702133370023625 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. // **** Set simulation time scale **** `timescale 1ns/1ps verilator-4.038/test_regress/t/t_sv_cpu_code/pad_vdd.sv0000664000177100017500000000103713702133370023257 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. //***************************************************************************** // PAD_VDD - VDD Supply Pad (Dummy!!!!) //***************************************************************************** module pad_vdd #( parameter ID = 0 ) ( inout wire pad ); assign pad = 1'b1; endmodule // pad_vdd verilator-4.038/test_regress/t/t_sv_cpu_code/rom.sv0000664000177100017500000000153613702133370022457 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. // ***************************************************************************** // Code ROM // // IMPORTANT! // Array size must be uppdated according to program size. // ***************************************************************************** const logic [15:0] rom[0:13] = '{ `LDI( R0, 11 ) `LDI( R1, 22 ) `LDI( R2, 33 ) `LDI( R3, 44 ) `STS( 0, R0 ) `STS( 1, R1 ) `STS( 2, R2 ) `STS( 3, R3 ) `LDS( R4, 0 ) `LDS( R5, 1 ) `LDS( R6, 0 ) `LDS( R7, 0 ) `JMP( 00 ) `EOP // End of Program (NOP) }; verilator-4.038/test_regress/t/t_sv_cpu_code/ac_ana.sv0000664000177100017500000000207213702133370023060 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module ac_ana // #( parameter // ID = 1 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** pads_if.mp_ana padsif, // **** Outputs **** output logic acout, // **** Inputs **** input logic acenable, // - System - input logic clk, input logic rst ); // *************************************************************************** // Analog Model // *************************************************************************** assign acout = (padsif.ana[1] - padsif.ana[2]) & acenable; assign padsif.ana_override[1] = 1'b0; assign padsif.ana_override[2] = 1'b0; endmodule // ac_ana verilator-4.038/test_regress/t/t_sv_cpu_code/adrdec.sv0000664000177100017500000000221713702133370023101 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module adrdec #( parameter NSLAVES = 2 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** genbus_if.adrdec dbus ); // *************************************************************************** // Address Decode // *************************************************************************** // const logic [15:0] adrmap[1:2] = '{} always_comb begin logic sel [1:NSLAVES]; sel[1] = (dbus.s_adr[1][7:4] == 4'h0); sel[2] = (dbus.s_adr[2][7:4] == 4'h1); // sel[3] = (dbus.s_adr[3][7:4] == 4'h2); dbus.s_sel = sel; // for ( i = 1; i <= dbus.aNumSlaves; i++ ) // begin // dbus.s_sel[i] = (dbus.s_adr[i] == adrmap[i]); // end end endmodule // adrdec verilator-4.038/test_regress/t/t_sv_cpu_code/chip.sv0000664000177100017500000000660613702133370022610 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. // ***************************************************************************** // Top level of System Verilog evalution (Full chip level) // ***************************************************************************** module chip #( parameter NUMPADS = $size( pinout ) ) ( // **** Pinout **** `ifdef VERILATOR // see t_tri_array inout wire [NUMPADS:1] pad, `else inout wire pad [1:NUMPADS], `endif // **** Inputs !!!! **** input logic clk, input logic rst ); // *************************************************************************** // Local Parameters // *************************************************************************** localparam NSLAVES = 2; // *************************************************************************** // PADS // *************************************************************************** // **** Interface **** pads_if padsif(); // **** Pad Instansiations **** pads // #( ) i_pads ( /*AUTOINST*/ // Interfaces .padsif (padsif.mp_pads), // Inouts .pad (pad), // Inputs .clk (clk), .rst (rst)); // *************************************************************************** // "dbus" Interface // *************************************************************************** genbus_if #( .NSLAVES(NSLAVES) ) dbus( .clk(clk), .rst(rst), .test_mode(1'b0) ); adrdec // #( ) i_adrdec ( /*AUTOINST*/ // Interfaces .dbus (dbus.adrdec)); // *************************************************************************** // CPU ("dbus" Master) // *************************************************************************** cpu #( .ID(1) ) i_cpu ( /*AUTOINST*/ // Interfaces .dbus (dbus.master), // Inputs .clk (clk), .rst (rst)); // *************************************************************************** // PORTS ("dbus" Slave #1) // *************************************************************************** ports #( .ID(1) ) i_ports ( /*AUTOINST*/ // Interfaces .dbus (dbus.slave), .padsif (padsif.mp_dig), // Inputs .clk (clk), .rst (rst)); // *************************************************************************** // Analog Comparator ("dbus" Slave #2) // *************************************************************************** ac #( .ID(2) ) i_ac ( /*AUTOINST*/ // Interfaces .dbus (dbus.slave), .padsif (padsif.mp_ana), // Inputs .clk (clk), .rst (rst)); endmodule // chip verilator-4.038/test_regress/t/t_sv_cpu_code/genbus_if.sv0000664000177100017500000001511413702133370023620 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. typedef struct packed { bit [1:0] size; } mPreAdrDecode_resp; interface genbus_if #( parameter DSIZE = 2, SSIZE = DSIZE, ASIZE = 16, NMASTERS = 1, NSLAVES = 1, DMSB = (DSIZE<<3) - 1, SMSB = SSIZE - 1, AMSB = ASIZE - 1 ) ( // **** Inputs **** // - System - input logic clk, // Device Clock. input logic rst, // Device Reset. input logic test_mode // Test mode. ); // *************************************************************************** // Interface Variables // *************************************************************************** // **** Master **** logic [DMSB:0] m_sdata[1:NMASTERS]; // Slave data. logic m_ws [1:NMASTERS]; // Slave wait state. logic [DMSB:0] m_mdata[1:NMASTERS]; // Master data. logic [AMSB:0] m_adr [1:NMASTERS]; // Address. logic [SMSB:0] m_we [1:NMASTERS]; // Write enable. logic [SMSB:0] m_re [1:NMASTERS]; // Read enable. // **** Slave **** logic [DMSB:0] s_sdata[1:NSLAVES]; // Slave data (from slave). logic s_ws [1:NSLAVES]; // Slave wait state (from slave). logic [DMSB:0] s_mdata[1:NSLAVES]; // Master data (to slave). logic [AMSB:0] s_adr [1:NSLAVES]; // Address (to slave). logic [SMSB:0] s_we [1:NSLAVES]; // Write enable (to slave). logic [SMSB:0] s_re [1:NSLAVES]; // Read enable (to slave). // **** Address Decoder **** logic s_sel [1:NSLAVES]; // Slave select (to slave). // *************************************************************************** // Modports // *************************************************************************** modport master( import mConnect, import mPreAdrDecode, input m_sdata, input m_ws, output m_mdata, output m_adr, output m_we, output m_re ); // - Slaves - modport slave( import sConnect, output s_sdata, output s_ws, input s_mdata, input s_adr, input s_we, input s_re, input s_sel ); // UNSUPPORTED // for (genvar i = 1; i <= NSLAVES; i++ ) // begin: mps // modport slave( // import sConnect, // output .s_sdata( s_sdata[i] ), // output .s_ws ( s_ws [i] ), // input .s_mdata( s_mdata[i] ), // input .s_adr ( s_adr [i] ), // input .s_we ( s_we [i] ), // input .s_re ( s_re [i] ), // input .s_sel ( s_sel [i] ) // ); // end // blocks modport adrdec( import aNumSlaves, input s_adr, output s_sel ); // *************************************************************************** // Bus Multiplexers // *************************************************************************** always_comb begin: busmux // - Local Variables - integer i; // - Defautls - m_sdata[1] = {(DSIZE<<3){1'b0}}; m_ws [1] = 1'b0; for ( i = 1; i <= NSLAVES; i++ ) begin m_sdata[1] |= s_sdata[i]; m_ws [1] |= s_ws [i]; s_mdata[i] = m_mdata[1]; s_adr [i] = m_adr [1]; s_we [i] = m_we [1]; s_re [i] = m_re [1]; end end // *************************************************************************** // Master Functions and Tasks // *************************************************************************** function automatic void mConnect( input integer id, output logic [DMSB:0] sdata, output logic ws, input logic [DMSB:0] mdata, input logic [AMSB:0] adr, input logic [SMSB:0] we, input logic [SMSB:0] re ); begin m_mdata[id] = mdata; m_adr [id] = adr; m_we [id] = we; m_re [id] = re; sdata = m_sdata[id]; ws = m_ws [id]; end endfunction function automatic mPreAdrDecode_resp mPreAdrDecode( input integer id, input logic [AMSB:0] adr ); begin // ToDo: Add parameterized address decoding!!!! // Example code: if ( adr[0] ) mPreAdrDecode.size = 2'b01; // Word (16-bit) memory. else mPreAdrDecode.size = 2'b10; // Double Word (32-bit) memory. end endfunction // *************************************************************************** // Slave Functions and Tasks // *************************************************************************** function automatic void sConnect( input integer id, input logic rst, input logic [DMSB:0] sdata, input logic ws, output logic [DMSB:0] mdata, output logic [AMSB:0] adr, output logic [SMSB:0] we, output logic [SMSB:0] re ); begin s_sdata[id] = sdata & {(DSIZE<<3){s_sel[id]}}; // verilator lint_off WIDTH s_ws [id] = ws & {SSIZE{s_sel[id]}}; // verilator lint_on WIDTH mdata = s_mdata[id] & {16{~rst}}; adr = s_adr [id]; we = (s_we [id] & {SSIZE{s_sel[id]}}) | {SSIZE{rst}}; re = s_re [id] & {SSIZE{s_sel[id]}}; end endfunction // *************************************************************************** // Address Decoder Functions and Tasks // *************************************************************************** function automatic integer aNumSlaves; aNumSlaves = NSLAVES; endfunction endinterface // genbus_if verilator-4.038/test_regress/t/t_sv_cpu_code/program_h.sv0000664000177100017500000000206013702133370023631 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. `ifndef _PROGRAM_H_V_ `define _PROGRAM_H_V_ // ***************************************************************************** // Assembly Mnemonic Defines // ***************************************************************************** typedef enum reg [3:0] { R0,R1,R2,R3,R4,R5,R6,R7, R8,R9,R10,R11,R12,R13,R14,R15 } cpu_registers; `define NOP 16'h0000, `define JMP( k8 ) {4'h1, 4'h0, 8'h k8}, `define LDI( rd, k8 ) {4'h4, rd, 8'h k8}, `define STS( k8, rs ) {4'h8, rs, 8'h k8}, `define LDS( rd, k8 ) {4'h9, rd, 8'h k8}, `define EOP 16'h0000 // ***************************************************************************** // Include ROM // ***************************************************************************** `include "rom.sv" `endif // !`ifdef _PROGRAM_H_V_ verilator-4.038/test_regress/t/t_sv_cpu_code/pinout_h.sv0000664000177100017500000000327213702133370023506 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. `ifndef _PINOUT_H_SV_ `define _PINOUT_H_SV_ // ***************************************************************************** // Structs/Unions // ***************************************************************************** // **** Pin Descriptor **** // - Pin Descriptor - typedef struct packed { t_pinid id; t_padtype padtype; int aux; } t_pin_descriptor; // ***************************************************************************** // Pinout // ***************************************************************************** // **** Preferred Solution !!!! **** localparam t_pin_descriptor pinout[ 1: 6] = '{ '{default:0, id:PINID_A0, padtype:PADTYPE_GPIO, aux:1}, '{default:0, id:PINID_A1, padtype:PADTYPE_GPIO}, '{default:0, id:PINID_A2, padtype:PADTYPE_GPIO}, '{default:0, id:PINID_D0, padtype:PADTYPE_GPIO}, '{default:0, id:PINID_VDD0, padtype:PADTYPE_VDD}, '{default:0, id:PINID_GND0, padtype:PADTYPE_GND} }; // **** Workaround !!!! **** typedef enum int { pinout_wa_id = 1, pinout_wa_padtype, pinout_wa_aux } t_pinout_wa; localparam int pinout_size = 6; localparam int pinout_wa[1:pinout_size][pinout_wa_id:pinout_wa_aux] = '{ '{PINID_A0, PADTYPE_GPIO, 0}, '{PINID_A1, PADTYPE_GPIO, 0}, '{PINID_A2, PADTYPE_GPIO, 0}, '{PINID_D0, PADTYPE_GPIO, 0}, '{PINID_VDD0, PADTYPE_VDD, 0}, '{PINID_GND0, PADTYPE_GND , 0} }; `endif // `ifndef _PINOUT_H_SV_ // **** End of File **** verilator-4.038/test_regress/t/t_sv_cpu_code/ports_h.sv0000664000177100017500000000177313702133370023343 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. `ifndef _PORTS_H_SV_ `define _PORTS_H_SV_ // ***************************************************************************** // // ***************************************************************************** // !!!! Incomplete! localparam int str_pinid [0:15] = '{ "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" }; // **** Port Identifiers **** typedef enum int { PORTID_A = 32'd0, // MUST BE ZERO! PORTID_B, PORTID_C, PORTID_D, PORTID_E, PORTID_F, PORTID_G, PORTID_H, // PORTID_I, -> DO NOT USE! PORTID_J, PORTID_K, PORTID_L, PORTID_M, PORTID_N, // PORTID_O, -> DO NOT USE! PORTID_P, PORTID_Q, PORTID_R } t_portid; `endif // !`ifdef _PORTS_H_SV_ // **** End of File **** verilator-4.038/test_regress/t/t_split_var_3_wreal.v0000664000177100017500000000234013702133370022617 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" module t (/*autoarg*/ // Inputs clk ); input clk; integer cyc=0; real vin[0:1] /*verilator split_var*/; wreal vout[0:1] /*verilator split_var*/; swap i_swap(.in0(vin[0]), .in1(vin[1]), .out0(vout[0]), .out1(vout[1])); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup vin[0] = 1.0; vin[1] = 2.0; end else if (cyc==2) begin vin[0] = 3.0; vin[1] = 4.0; end else if (cyc==3) begin if (vout[0] == vin[1] && vout[1] == vin[0]) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Mismatch %f %f\n", vout[0], vout[1]); $stop; end end end endmodule module swap (input wreal in0, in1, output wreal out0, out1); wreal tmp[0:1] /* verilator split_var*/; assign tmp[0] = in0; assign tmp[1] = in1; assign out0 = tmp[1]; assign out1 = tmp[0]; endmodule verilator-4.038/test_regress/t/t_string_type_methods_bad.pl0000775000177100017500000000107413702133370024254 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_rand.cpp0000664000177100017500000000134513702133370021460 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include "Vt_func_rand.h" int main(int argc, char* argv[]) { Vt_func_rand* topp = new Vt_func_rand; Verilated::debug(0); printf("\nTesting\n"); for (int i = 0; i < 10; i++) { topp->clk = 0; topp->eval(); topp->clk = 1; topp->eval(); } if (topp->Rand != 0xfeed0fad) { vl_fatal(__FILE__, __LINE__, "top", "Unexpected value for Rand output\n"); } printf("*-* All Finished *-*\n"); } verilator-4.038/test_regress/t/t_pli_bad.pl0000775000177100017500000000107513702133370020747 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_system.pl0000775000177100017500000000105313702133370021573 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_threads_counter_1.pl0000775000177100017500000000120213702133370022756 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); top_filename("t/t_threads_counter.v"); compile( verilator_flags2 => ['--cc --threads 1'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_packed_struct.pl0000775000177100017500000000110713702133370023362 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["--trace"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlcov_debugi.pl0000775000177100017500000000155213702133370022025 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); foreach my $basename ("t_vlcov_data_a.dat", "t_vlcov_data_b.dat", "t_vlcov_data_c.dat", "t_vlcov_data_d.dat", ) { run(cmd => ["../bin/verilator_coverage", "t/${basename}", "--debugi 9", ], tee => $Self->{verbose}, verilator_run => 1, ); } ok(1); 1; verilator-4.038/test_regress/t/t_flag_make_cmake_sc.v0000664000177100017500000000057513702133370022743 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_pins_sc_uint.pl0000775000177100017500000000470413702133370022724 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_var_pinsizes.v"); compile( verilator_flags2 => ["-sc --pins-sc-uint --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], make_main => 0, ); { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i128;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i513;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o128;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o513;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16;/x); } execute(); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_bad_end.pl0000775000177100017500000000114213702133370023314 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_const_overflow_bad.v0000664000177100017500000000135413702133367023071 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; // One to many digits parameter [200:0] SMALLH = 8'habc; // One to many digits parameter [200:0] SMALLO = 6'o1234; // One to many digits parameter [200:0] SMALLB = 3'b1111; // One to many digits // We'll allow this though; no reason to be cruel parameter [200:0] OKH = 8'h000000001; // bug1380 parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; endmodule verilator-4.038/test_regress/t/t_param_circ_bad.out0000664000177100017500000000041613702133370022452 0ustar wsnyderwsnyder%Error: t/t_param_circ_bad.v:11:43: Variable's initial value is circular: 'X' : ... In instance t.sub 11 | module sub #(parameter WIDTH=X, parameter X=WIDTH) | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_protect_ids.v0000664000177100017500000000276613702133370021533 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface secret_intf(); logic secret_a; integer secret_b; endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; secret_sub secret_inst (.*); secret_other secret_inst2 (.*); endmodule module secret_sub ( input clk); // verilator no_inline_module integer secret_cyc; real secret_cyc_r; integer secret_o; real secret_r; export "DPI-C" task dpix_a_task; task dpix_a_task(input int i, output int o); o = i + 1; endtask import "DPI-C" context task dpii_a_task(input int i, output int o); export "DPI-C" function dpix_a_func; function int dpix_a_func(input int i); return i + 2; endfunction import "DPI-C" context function int dpii_a_func(input int i); // Test loop always @ (posedge clk) begin secret_cyc_r = $itor(secret_cyc)/10.0 - 5.0; secret_cyc <= dpii_a_func(secret_cyc); secret_r += 1.0 + $cos(secret_cyc_r); dpix_a_task(secret_cyc, secret_o); if (secret_cyc==90) begin $write("*-* All Finished *-*\n"); end end endmodule module secret_other ( input clk); integer secret_cyc; always @ (posedge clk) begin secret_cyc <= secret_cyc + 1; if (secret_cyc==99) begin $finish; end end secret_intf secret_interface(); endmodule verilator-4.038/test_regress/t/t_inst_comma_inl1.pl0000775000177100017500000000117413702133370022431 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_comma.v"); compile( v_flags2 => ['+define+USE_INLINE',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_static_elab.pl0000775000177100017500000000105313702133370021623 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_sformat.pl0000775000177100017500000000105313702133370021722 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_packed_struct.v0000664000177100017500000000160713702133370023216 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Andrew Bardsley. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cnt; // This won't compile with tracing as an incorrect declaration is made for // the temp variables used to represent the elements of localparam v typedef struct packed { logic [2:0][31:0] a; } t; localparam t v[2:0] = '{ '{'{32'h10000002, 32'h10000001, 32'h10000000}}, '{'{32'h20000002, 32'h20000001, 32'h20000000}}, '{'{32'h30000002, 32'h30000001, 32'h30000000}} }; initial cnt = 0; always@(posedge clk) begin if (cnt < 3) begin cnt = cnt + 1; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_preproc_defines.pl0000775000177100017500000000154413702133370022525 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_preproc.v"); my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; compile( verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --dump-defines'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, stdout_filename => $stdout_filename, ); files_identical($stdout_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_export_bad.out0000664000177100017500000000034013702133370022523 0ustar wsnyderwsnyder%Error: t/t_dpi_export_bad.v:10:24: Can't find definition of exported task/function: 'dpix_bad_missing' 10 | export "DPI-C" task dpix_bad_missing; | ^~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_cast.v0000664000177100017500000000410413702133367020140 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef logic [3:0] mc_t; typedef mc_t tocast_t; typedef struct packed { logic [15:0] data; } packed_t; packed_t pdata; assign pdata.data = 16'h1234; logic [7:0] logic8bit; assign logic8bit = $bits(logic8bit)'(pdata >> 8); mc_t o; logic [15:0] allones = 16'hffff; parameter FOUR = 4; // bug925 localparam [6:0] RESULT = 7'((6*9+92)%96); logic signed [14:0] samp0 = 15'h0000; logic signed [14:0] samp1 = 15'h0000; logic signed [14:0] samp2 = 15'h6000; logic signed [11:0] coeff0 = 12'h009; logic signed [11:0] coeff1 = 12'h280; logic signed [11:0] coeff2 = 12'h4C5; logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11)); // verilator lint_off WIDTH logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11)); // verilator lint_on WIDTH logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector (27'(coeff1 * samp1) >>> 11) + (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings initial begin if (logic8bit != 8'h12) $stop; if (4'shf > 4'sh0) $stop; if (signed'(4'hf) > 4'sh0) $stop; if (4'hf < 4'h0) $stop; if (unsigned'(4'shf) < 4'h0) $stop; if (const'(4'shf) !== 4'shf) $stop; if (4'(allones) !== 4'hf) $stop; if (6'(allones) !== 6'h3f) $stop; if ((4)'(allones) !== 4'hf) $stop; if ((4+2)'(allones) !== 6'h3f) $stop; if ((4-2)'(allones) !== 2'h3) $stop; if ((FOUR+2)'(allones) !== 6'h3f) $stop; if (50 !== RESULT) $stop; o = tocast_t'(4'b1); if (o != 4'b1) $stop; if (15'h6cec != outa) $stop; if (27'h7ffecec != mida) $stop; if (27'h7ffecec != midb) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_case_group.pl0000775000177100017500000000105313702133367021506 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_countbits.v0000664000177100017500000001002313702133370022220 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Yossi Nivin. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; reg [15:0] in16; reg [31:0] in32; reg [63:0] in64; // Non-standard size reg [9:0] in10; reg [20:0] in21; reg [58:0] in59; reg [69:0] in70; reg [31:0] ctrl0; reg [31:0] ctrl1; reg [31:0] ctrl2; reg [4:0] result_16_1; reg [4:0] result_16_2; reg [4:0] result_16_3; reg [5:0] result_32_1; reg [5:0] result_32_2; reg [5:0] result_32_3; reg [6:0] result_64_1; reg [6:0] result_64_2; reg [6:0] result_64_3; reg [3:0] result_10_3; reg [4:0] result_21_3; reg [5:0] result_59_3; reg [6:0] result_70_3; always @* begin result_16_1 = $countbits(in16, ctrl0); result_16_2 = $countbits(in16, ctrl0, ctrl1); result_16_3 = $countbits(in16, ctrl0, ctrl1, ctrl2); result_32_1 = $countbits(in32, ctrl0); result_32_2 = $countbits(in32, ctrl0, ctrl1); result_32_3 = $countbits(in32, ctrl0, ctrl1, ctrl2); result_64_1 = $countbits(in64, ctrl0); result_64_2 = $countbits(in64, ctrl0, ctrl1); result_64_3 = $countbits(in64, ctrl0, ctrl1, ctrl2); result_10_3 = $countbits(in10, ctrl0, ctrl1, ctrl2); result_21_3 = $countbits(in21, ctrl0, ctrl1, ctrl2); result_59_3 = $countbits(in59, ctrl0, ctrl1, ctrl2); result_70_3 = $countbits(in70, ctrl0, ctrl1, ctrl2); end integer cyc=0; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin // Constants if ($countbits(32'b11001011101, '1) != 7) $stop; if ($countbits(32'b11001011101, '1, 'z) != 7) $stop; if ($countbits(32'b11001011101, '1, '0) != 32) $stop; if ($countbits(20'b11001011101, '1, '0) != 20) $stop; if ($countbits(20'b1100x01z101, '1, '0) != 18) $stop; if ($countbits(20'b1100x01z101, 2, 2'bx1) != 18) $stop; if ($countbits(32'b1100x01z101, 'x, 'z) != 2) $stop; if ($countbits(32'b1100x01z101, 'x, 'z, '1) != 7) $stop; end else if (cyc == 1) begin in16 <= 16'h0AF0; in32 <= 32'hA0F300; in64 <= 64'hA5A5A5A5A5A5A5A5; in10 <= 10'b1010_1011; in21 <= 21'h10F102; in59 <= 59'h7050137210; in70 <= 70'hF00030008000; ctrl0 <= '0; ctrl1 <= '1; ctrl2 <= '1; end else if (cyc == 2) begin if (result_16_1 != 10) $stop; if (result_16_2 != 16) $stop; if (result_16_3 != 16) $stop; if (result_32_1 != 24) $stop; if (result_32_2 != 32) $stop; if (result_32_3 != 32) $stop; if (result_64_1 != 32) $stop; if (result_64_2 != 64) $stop; if (result_64_3 != 64) $stop; if (result_10_3 != 10) $stop; if (result_21_3 != 21) $stop; if (result_59_3 != 59) $stop; if (result_70_3 != 70) $stop; in16 <= 16'h82B; in32 <= 32'h305372; in64 <= 64'h7777777777777777; in10 <= 10'b1001_0111; in21 <= 21'h91040C; in59 <= 59'h12345678; in70 <= 70'hF11111111; // Confirm upper bits of the control arguments are ignored ctrl0 <= 5; ctrl1 <= 3; ctrl2 <= 2; end else if (cyc == 3) begin if (result_16_1 != 5) $stop; if (result_16_2 != 5) $stop; if (result_16_3 != 16) $stop; if (result_32_1 != 10) $stop; if (result_32_2 != 10) $stop; if (result_32_3 != 32) $stop; if (result_64_1 != 48) $stop; if (result_64_2 != 48) $stop; if (result_64_3 != 64) $stop; if (result_10_3 != 10) $stop; if (result_21_3 != 21) $stop; if (result_59_3 != 59) $stop; if (result_70_3 != 70) $stop; end else if (cyc == 4) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_dpi_arg_input_type.out0000664000177100017500000001206113702133370023430 0ustar wsnyderwsnyderi_chandle 0 i_string 0 i_bit 0 i_logic 0 i_chandle_t 0 i_string_t 0 i_bit_t 0 i_logic_t 0 i_array_2_state_1 0 i_array_2_state_32 0 i_array_2_state_33 0 i_array_2_state_64 0 i_array_2_state_65 0 i_array_2_state_128 0 i_struct_2_state_1 0 i_struct_2_state_32 0 i_struct_2_state_33 0 i_struct_2_state_64 0 i_struct_2_state_65 0 i_struct_2_state_128 0 i_union_2_state_1 0 i_union_2_state_32 0 i_union_2_state_33 0 i_union_2_state_64 0 i_union_2_state_65 0 i_union_2_state_128 0 i_array_4_state_1 0 i_array_4_state_32 0 i_array_4_state_33 0 i_array_4_state_64 0 i_array_4_state_65 0 i_array_4_state_128 0 i_struct_4_state_1 0 i_struct_4_state_32 0 i_struct_4_state_33 0 i_struct_4_state_64 0 i_struct_4_state_65 0 i_struct_4_state_128 0 i_union_4_state_1 0 i_union_4_state_32 0 i_union_4_state_33 0 i_union_4_state_64 0 i_union_4_state_65 0 i_union_4_state_128 0 e_chandle 0 e_string 0 e_bit 0 e_logic 0 e_chandle_t 0 e_string_t 0 e_bit_t 0 e_logic_t 0 e_array_2_state_1 0 e_array_2_state_32 0 e_array_2_state_33 0 e_array_2_state_64 0 e_array_2_state_65 0 e_array_2_state_128 0 e_struct_2_state_1 0 e_struct_2_state_32 0 e_struct_2_state_33 0 e_struct_2_state_64 0 e_struct_2_state_65 0 e_struct_2_state_128 0 e_union_2_state_1 0 e_union_2_state_32 0 e_union_2_state_33 0 e_union_2_state_64 0 e_union_2_state_65 0 e_union_2_state_128 0 e_array_4_state_1 0 e_array_4_state_32 0 e_array_4_state_33 0 e_array_4_state_64 0 e_array_4_state_65 0 e_array_4_state_128 0 e_struct_4_state_1 0 e_struct_4_state_32 0 e_struct_4_state_33 0 e_struct_4_state_64 0 e_struct_4_state_65 0 e_struct_4_state_128 0 e_union_4_state_1 0 e_union_4_state_32 0 e_union_4_state_33 0 e_union_4_state_64 0 e_union_4_state_65 0 e_union_4_state_128 0 i_chandle 1 i_string 1 i_bit 1 i_logic 1 i_chandle_t 1 i_string_t 1 i_bit_t 1 i_logic_t 1 i_array_2_state_1 1 i_array_2_state_32 1 i_array_2_state_33 1 i_array_2_state_64 1 i_array_2_state_65 1 i_array_2_state_128 1 i_struct_2_state_1 1 i_struct_2_state_32 1 i_struct_2_state_33 1 i_struct_2_state_64 1 i_struct_2_state_65 1 i_struct_2_state_128 1 i_union_2_state_1 1 i_union_2_state_32 1 i_union_2_state_33 1 i_union_2_state_64 1 i_union_2_state_65 1 i_union_2_state_128 1 i_array_4_state_1 1 i_array_4_state_32 1 i_array_4_state_33 1 i_array_4_state_64 1 i_array_4_state_65 1 i_array_4_state_128 1 i_struct_4_state_1 1 i_struct_4_state_32 1 i_struct_4_state_33 1 i_struct_4_state_64 1 i_struct_4_state_65 1 i_struct_4_state_128 1 i_union_4_state_1 1 i_union_4_state_32 1 i_union_4_state_33 1 i_union_4_state_64 1 i_union_4_state_65 1 i_union_4_state_128 1 e_chandle 1 e_string 1 e_bit 1 e_logic 1 e_chandle_t 1 e_string_t 1 e_bit_t 1 e_logic_t 1 e_array_2_state_1 1 e_array_2_state_32 1 e_array_2_state_33 1 e_array_2_state_64 1 e_array_2_state_65 1 e_array_2_state_128 1 e_struct_2_state_1 1 e_struct_2_state_32 1 e_struct_2_state_33 1 e_struct_2_state_64 1 e_struct_2_state_65 1 e_struct_2_state_128 1 e_union_2_state_1 1 e_union_2_state_32 1 e_union_2_state_33 1 e_union_2_state_64 1 e_union_2_state_65 1 e_union_2_state_128 1 e_array_4_state_1 1 e_array_4_state_32 1 e_array_4_state_33 1 e_array_4_state_64 1 e_array_4_state_65 1 e_array_4_state_128 1 e_struct_4_state_1 1 e_struct_4_state_32 1 e_struct_4_state_33 1 e_struct_4_state_64 1 e_struct_4_state_65 1 e_struct_4_state_128 1 e_union_4_state_1 1 e_union_4_state_32 1 e_union_4_state_33 1 e_union_4_state_64 1 e_union_4_state_65 1 e_union_4_state_128 1 i_chandle 2 i_string 2 i_bit 2 i_logic 2 i_chandle_t 2 i_string_t 2 i_bit_t 2 i_logic_t 2 i_array_2_state_1 2 i_array_2_state_32 2 i_array_2_state_33 2 i_array_2_state_64 2 i_array_2_state_65 2 i_array_2_state_128 2 i_struct_2_state_1 2 i_struct_2_state_32 2 i_struct_2_state_33 2 i_struct_2_state_64 2 i_struct_2_state_65 2 i_struct_2_state_128 2 i_union_2_state_1 2 i_union_2_state_32 2 i_union_2_state_33 2 i_union_2_state_64 2 i_union_2_state_65 2 i_union_2_state_128 2 i_array_4_state_1 2 i_array_4_state_32 2 i_array_4_state_33 2 i_array_4_state_64 2 i_array_4_state_65 2 i_array_4_state_128 2 i_struct_4_state_1 2 i_struct_4_state_32 2 i_struct_4_state_33 2 i_struct_4_state_64 2 i_struct_4_state_65 2 i_struct_4_state_128 2 i_union_4_state_1 2 i_union_4_state_32 2 i_union_4_state_33 2 i_union_4_state_64 2 i_union_4_state_65 2 i_union_4_state_128 2 e_chandle 2 e_string 2 e_bit 2 e_logic 2 e_chandle_t 2 e_string_t 2 e_bit_t 2 e_logic_t 2 e_array_2_state_1 2 e_array_2_state_32 2 e_array_2_state_33 2 e_array_2_state_64 2 e_array_2_state_65 2 e_array_2_state_128 2 e_struct_2_state_1 2 e_struct_2_state_32 2 e_struct_2_state_33 2 e_struct_2_state_64 2 e_struct_2_state_65 2 e_struct_2_state_128 2 e_union_2_state_1 2 e_union_2_state_32 2 e_union_2_state_33 2 e_union_2_state_64 2 e_union_2_state_65 2 e_union_2_state_128 2 e_array_4_state_1 2 e_array_4_state_32 2 e_array_4_state_33 2 e_array_4_state_64 2 e_array_4_state_65 2 e_array_4_state_128 2 e_struct_4_state_1 2 e_struct_4_state_32 2 e_struct_4_state_33 2 e_struct_4_state_64 2 e_struct_4_state_65 2 e_struct_4_state_128 2 e_union_4_state_1 2 e_union_4_state_32 2 e_union_4_state_33 2 e_union_4_state_64 2 e_union_4_state_65 2 e_union_4_state_128 2 *-* All Finished *-* verilator-4.038/test_regress/t/t_mem.v0000664000177100017500000000303013702133370017753 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // [16] is SV syntax for [0:15] reg [7:0] memory8_16 [16]; reg m_we; reg [3:1] m_addr; reg [15:0] m_data; always @ (posedge clk) begin // Load instructions from cache memory8_16[{m_addr,1'd0}] <= 8'hfe; if (m_we) begin {memory8_16[{m_addr,1'd1}], memory8_16[{m_addr,1'd0}]} <= m_data; end end reg [7:0] memory8_16_4; reg [7:0] memory8_16_5; // Test complicated sensitivity lists always @ (memory8_16[4][7:1] or memory8_16[5]) begin memory8_16_4 = memory8_16[4]; memory8_16_5 = memory8_16[5]; end always @ (posedge clk) begin m_we <= 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin m_we <= 1'b1; m_addr <= 3'd2; m_data <= 16'h55_44; end if (cyc==2) begin m_we <= 1'b1; m_addr <= 3'd3; m_data <= 16'h77_66; end if (cyc==3) begin m_we <= 0; // Check we really don't write this m_addr <= 3'd3; m_data <= 16'h0bad; end if (cyc==5) begin if (memory8_16_4 != 8'h44) $stop; if (memory8_16_5 != 8'h55) $stop; if (memory8_16[6] != 8'hfe) $stop; if (memory8_16[7] != 8'h77) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_interface_down_inlc.pl0000775000177100017500000000123413702133370023346 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_C'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_vgen.v0000664000177100017500000002431013702133370021151 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg check; initial check = 1'b0; // verilator lint_off WIDTH //============================================================ reg [ 1:0] W0095; //=3 reg [ 58:0] W0101; //=0000000FFFFFFFF always @(posedge clk) begin if (cyc==1) begin W0095 = ((2'h3)); W0101 = ({27'h0,({16{(W0095)}})}); end end always @(posedge clk) begin if (cyc==2) begin if ((W0101) != (59'h0FFFFFFFF)) if (check) $stop; end end //============================================================ reg [ 0:0] W1243; //=1 always @(posedge clk) begin if (cyc==1) begin W1243 = ((1'h1)); end end always @(posedge clk) begin if (cyc==2) begin // Width violation, but still... if (((-W1243) < 32'h01) != (1'h0)) if (check) $stop; if (({32{W1243}} < 32'h01) != (1'h0)) if (check) $stop; end end //============================================================ reg [ 0:0] W0344; //=0 always @(posedge clk) begin if (cyc==1) begin W0344 = 1'b0; end end always @(posedge clk) begin if (cyc==2) begin if ((W0344) != (1'h0)) if (check) $stop; if (({116{(((- 95'h7FFFFFFFFFFFFFFFFFFFFFFF) ^ 95'h7FFFFFFFFFFFFFFFFFFFFFFF ) == ({94'h0,W0344}))}})) if (check) $stop; end end //============================================================ reg [ 63:0] W0372; //=FFFFFFFFFFFFFFFF reg [118:0] W0420; //=7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF reg [115:0] W0421; //=00000000000000000000000000000 always @(posedge clk) begin if (cyc==1) begin W0372 = ({64{((1'h1))}}); W0421 = 116'h0; W0420 = ({119{((W0372) <= (W0372))}}); end end always @(posedge clk) begin if (cyc==2) begin if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop; end end //============================================================ // gcc_2_96_bug reg [ 31:0] W0161; //=FFFFFFFF reg [ 62:0] W0217; //=0000000000000000 reg [ 53:0] W0219; //=00000000000000 always @(posedge clk) begin if (cyc==1) begin W0161 = 32'hFFFFFFFF; W0217 = 63'h0; W0219 = 54'h0; end end always @(posedge clk) begin if (cyc==2) begin if ((W0161) != (32'hFFFFFFFF)) if (check) $stop; if (((- (W0161)) & ((W0217[62:31]) & ({25'h0,(W0219[53:47])}))) != (32'h00000000)) if (check) $stop; end end //============================================================ reg [119:0] W0592; //=000000000000000000000000000000 reg [ 7:0] W0593; //=70 always @(posedge clk) begin if (cyc==1) begin W0593 = (((8'h90)) * ((8'hFF))); W0592 = 120'h000000000000000000000000000000; end end always @(posedge clk) begin if (cyc==2) begin if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop; end end //============================================================ reg [127:0] WA1063 ; //=00000000000000000000000000000001 reg [ 34:0] WA1064 /*verilator public*/; //=7FFFFFFFF reg [ 62:0] WA1065 ; //=0000000000000000 reg [ 89:0] WA1066 /*verilator public*/; //=00000000000000000000001 reg [ 34:0] WA1067 ; //=7FFFFFFFF reg [111:0] WA1068; always @(check) begin WA1067 = (~ (35'h0)); WA1066 = (90'h00000000000000000000001); WA1065 = (WA1066[89:27]); WA1064 = (WA1067); WA1063 = (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); end always @(posedge clk) begin if (cyc==2) begin if ((WA1063[(WA1064[(WA1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; end end //============================================================ reg [127:0] WB1063 ; //=00000000000000000000000000000001 reg [ 34:0] WB1064 /*verilator public*/; //=7FFFFFFFF reg [ 62:0] WB1065 ; //=0000000000000000 reg [ 89:0] WB1066 /*verilator public*/; //=00000000000000000000001 reg [ 34:0] WB1067 ; //=7FFFFFFFF reg [111:0] WB1068; always @(posedge clk) begin if (cyc==1) begin WB1067 = (~ (35'h0)); WB1066 = (90'h00000000000000000000001); end if (cyc==2) WB1065 <= (WB1066[89:27]); if (cyc==3) WB1064 <= (WB1067); if (cyc==4) WB1063 <= (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); if (cyc==5) WB1068 <= (WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]); end always @(posedge clk) begin if (cyc==9) begin if (WB1068 != 112'h0) if (check) $stop; if ((WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; end end //============================================================ reg signed [ 60:0] WC0064 ; //=1FFFFFFFFFFFFFFF reg signed [ 6:0] WC0065 ; //=00 reg signed [ 62:0] WC0067 /*verilator public*/; //=33250A3BFFFFFFFF always @(check) begin WC0064 = 61'sh1FFFFFFFFFFFFFFF; WC0065 = 7'sh0; if (((WC0064) >>> (WC0065)) != 61'sh1fffffffffffffff) if (check) $stop; end //============================================================ reg signed [ 76:0] W0234 ; //=00000000000000000000 reg signed [ 7:0] W0235 /*verilator public*/; //=B6 always @(check) begin W0235 = 8'shb6; W0234 = ((77'sh0001ffffffffffffffff) >>> (W0235)); if ((W0234) != 77'sh0) if (check) $stop; end //============================================================ reg signed [ 30:0] W0146 ; //=00000001 always @(check) begin : Block71 W0146 = (31'sh00000001); if ((W0146 >>> 6'sh3f) != 31'sh0) if (check) $stop; end //============================================================ reg signed [ 54:0] W0857 /*verilator public*/; //=7FFFFFFFFFFFFF always @(check) begin : Block405 W0857 = 55'sh7fffffffffffff; if ((63'sh7fffffffffffffff >>> (W0857[54:54] ? 7'sh56 : 7'sh7f)) != 63'sh7fffffffffffffff) if (check) $stop; end //============================================================ always @(posedge clk) begin if ((((122'sh3ffffffffffffffd3e48e0900000001 >>> 8'shff) >>> 8'b1) ) != 122'sh3ffffffffffffffffffffffffffffff) if (check) $stop; if (((95'sh7fff_ffff_ffffffff_ffffffff < 95'sh4a76_3d8b_0f4e3995_1146e342) != 1'h0)) if (check) $stop; end //============================================================ reg signed [ 82:0] W0226 ; //=47A4301EE3FB4133EE3DA always @* begin : Block144 W0226 = 83'sh47A4301EE3FB4133EE3DA; if ((W0226 >>> 8'sh1a) != 83'sh7ffffff1e90c07b8fed04) if (check) $stop; end //============================================================ reg signed [ 68:0] W0792 /*verilator public*/; //=169351569551247E0C reg signed [ 68:0] W0793 ; //=1FFFFFFFFF4EB1A91A always @(posedge clk) begin W0793 <= 69'sh1f_ffffffff_4eb1a91a; W0792 <= (W0793 * 69'sh1F_0E989F3E_F15F509E); if (W0792 != 69'sh16_93515695_51247E0C) if (check) $stop; end //============================================================ reg signed [ 2:0] DW0515 /*verilator public*/; //=7 always @(posedge clk) begin DW0515 <= 3'sh7; if ($signed({62'h0,DW0515[1'h1]}) != 63'sh0000000000000001) if (check) $stop; end //============================================================ reg signed [ 62:0] W0753 ; //=004E20004ED93E26 reg [ 2:0] W0772 /*verilator public*/; //=7 always @(posedge clk) begin W0753 <= 63'sh004E20004ED93E26; //(63'sh7fffffffffffffff + (63'sh464eac8c4ed93e27 & (63'sh08cf6243ffffffff))); W0772 <= 3'h7; if ((W0772[(W0753 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; if ((W0772[(63'sh004E20004ED93E26 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; end //============================================================ reg [ 98:0] W1027 ; //=7FFFFFFFFFFFFFFFFFFFFFFFF always @(posedge clk) begin W1027 <= ~99'h0; // verilator lint_off CMPCONST if (((1'sb1 < (95'sh7fffffffffffffffffffffff >= 95'sh09deb904ffffffffe062d44c))) != 1'h0) if (check) $stop; // verilator lint_on CMPCONST end //============================================================ reg signed [ 5:0] W123_is_3f ; //=3F always @(posedge clk) begin W123_is_3f <= 6'sh3f; end always @(posedge clk) begin if (((~ ((32'sh088d1bcb) <<< W123_is_3f)) >>> 6'sh3f) != 32'shffffffff) if (check) $stop; end //============================================================ reg signed [105: 0] W0032 /*verilator public*/; //=106'h3ff0000000100000000bd597bb1 always @(check) begin : Block237 W0032 = 106'sh3ff0000000100000000bd597bb1; if ((106'sh1ca0000000000000000b96b8dc2 / 106'sh3ff0000000100000000bd597bb1) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; if ((106'sh1ca0000000000000000b96b8dc2 / W0032) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; end //============================================================ reg signed [ 83: 0] W0024 ; //=84'h0000000000000e1fe9094 reg signed [ 83: 0] W0025 ; //=84'h0f66afffffffe308b3d7c always @(posedge clk) begin W0024 <= 84'h0000000000000e1fe9094; W0025 <= 84'h0f66afffffffe308b3d7c; if ((W0024 % W0025) != 84'sh0000000000000e1fe9094) if (check) $stop; end //============================================================ always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==18) begin check <= 1'b1; end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_display_esc_bad.out0000664000177100017500000000023413702133370022647 0ustar wsnyderwsnyder%Error: t/t_display_esc_bad.v:9:16: Unknown escape sequence: \x 9 | $display("\x\y\z"); | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_select_index2.v0000664000177100017500000000160013702133370021726 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] x; wire [3:0] en; wire sel; wire a; // bug675 generate genvar g_k; for ( g_k = 0; g_k < 8; g_k = g_k + 1 ) begin: g_index always @* begin // Note this isn't a genif, but normal if // verilator lint_off SELRANGE if(g_k<4) begin x[g_k] = (sel == 1'b1) ? 1'b1 : (en[g_k] == 1'b0) ? 1'b1 : a; end else begin x[g_k] = (sel == 1'b0) ? 1'b1 : (en[g_k-4] == 1'b0) ? 1'b1 : a; end // verilator lint_on SELRANGE end end endgenerate endmodule verilator-4.038/test_regress/t/t_lint_always_comb_bad.v0000664000177100017500000000163013702133370023335 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs mid, o3, // Inputs clk, i3 ); input clk; output logic mid; input i3; output logic o3; wire [15:0] temp1; wire [15:0] temp1_d1r; logic setbefore; always_comb begin setbefore = 1'b1; if (setbefore) setbefore = 1'b0; // fine end always_comb begin if (mid) temp1 = 'h0; else temp1 = (temp1_d1r - 'h1); mid = (temp1_d1r == 'h0); // BAD end always_comb begin o3 = 'h0; case (i3) 1'b1: begin o3 = i3; end default: ; endcase end always_ff @ (posedge clk) begin temp1_d1r <= temp1; end endmodule verilator-4.038/test_regress/t/t_var_static.out0000664000177100017500000000164113702133370021704 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_var_static.v:20:18: Unsupported: 'static' function/task variables : ... In instance t 20 | static int st = 2; st++; return st; | ^~ %Error-UNSUPPORTED: t/t_var_static.v:27:11: Unsupported: 'static' function/task variables : ... In instance t 27 | int st = 2; st++; return st; | ^~ %Error-UNSUPPORTED: t/t_var_static.v:30:18: Unsupported: 'static' function/task variables : ... In instance t 30 | static int st = 2; st++; return st; | ^~ %Error-UNSUPPORTED: t/t_var_static.v:40:18: Unsupported: 'static' function/task variables : ... In instance t 40 | static int st = 2; st++; return st; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_sys_file_basic.out0000664000177100017500000000025613702133370022524 0ustar wsnyderwsnyder[0] hello v=12345667 [0] Hello2 d: 12 12 h: 00000000014 0000000c o: 0000000c 00000000014 b: 00000000000000000000000000001100 00000000000000000000000000001100 verilator-4.038/test_regress/t/t_func_bad.v0000664000177100017500000000166013702133370020745 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (add(3'd1) != 0) $stop; // Too few args if (add(3'd1, 3'd2, 3'd3) != 0) $stop; // Too many args x; // Too few args if (hasout(3'd1) != 0) $stop; // outputs // f(.j(1), .no_such(2)); // Name mismatch f(.dup(1), .dup(3)); // Duplicate f(1,2,3); // Too many end function [2:0] add; input [2:0] from1; input [2:0] from2; begin add = from1 + from2; end endfunction task x; output y; begin end endtask function hasout; output [2:0] illegal_output; hasout = 0; endfunction function int f( int j = 1, int dup = 0 ); return (j<<16) | dup; endfunction endmodule verilator-4.038/test_regress/t/t_enum_type_pins.pl0000775000177100017500000000105313702133370022407 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_order_multidriven.cpp0000664000177100017500000000214413702133370023254 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Ted Campbell. // SPDX-License-Identifier: CC0-1.0 #include "Vt_order_multidriven.h" #include "verilated.h" #include "verilated_vcd_c.h" Vt_order_multidriven* vcore; VerilatedVcdC* vcd; vluint64_t vtime; #define PHASE_90 static void half_cycle(int clk) { if (clk & 1) vcore->i_clk_wr = !vcore->i_clk_wr; if (clk & 2) vcore->i_clk_rd = !vcore->i_clk_rd; vtime += 10 / 2; vcore->eval(); vcore->eval(); vcd->dump(vtime); } static void cycle() { #ifdef PHASE_90 half_cycle(1); half_cycle(2); half_cycle(1); half_cycle(2); #else half_cycle(3); half_cycle(3); #endif } int main() { Verilated::traceEverOn(true); vcore = new Vt_order_multidriven; vcd = new VerilatedVcdC; vcore->trace(vcd, 99); vcd->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); vcore->i_clk_wr = 0; vcore->i_clk_rd = 0; for (int i = 0; i < 256; ++i) cycle(); vcd->close(); printf("*-* All Finished *-*\n"); } verilator-4.038/test_regress/t/t_dpi_threads_c.cpp0000664000177100017500000000421113702133370022304 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2018-2018 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # ifdef T_DPI_THREADS_COLLIDE # include "Vt_dpi_threads_collide__Dpi.h" # else # include "Vt_dpi_threads__Dpi.h" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { extern void dpii_sys_task(); extern int dpii_failure(); } #endif //====================================================================== struct state { std::atomic task_is_running; std::atomic failure; state() : task_is_running(false) , failure(false) {} }; static state st; void dpii_sys_task() { bool other_task_running = atomic_exchange(&st.task_is_running, true); if (other_task_running) { // Another task is running. This is a collision. st.failure = 1; std::cerr << "t_dpi_threads_c.cpp dpii_sys_task() saw threads collide.\n"; } else { std::cerr << "t_dpi_threads_c.cpp dpii_sys_task() no collision. @" << &st.task_is_running << "\n"; } // Spend some time in the DPI call, so that if we can have a collision // we probably will. Technically this is not guaranteed to detect every // race. However, one second is so much greater than the expected // runtime of everything else in the test, it really should pick up on // races just about all of the time. sleep(1); atomic_exchange(&st.task_is_running, false); } int dpii_failure() { return st.failure; } verilator-4.038/test_regress/t/t_gen_for0.pl0000775000177100017500000000105313702133370021050 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_altera_lpm_constant.pl0000775000177100017500000000120613702133367023410 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_tree_inl1_pub1.vlt0000664000177100017500000000041713702133370023411 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config inline -module "l*" public -module "l*" -var "z*" verilator-4.038/test_regress/t/t_math_signed6.pl0000775000177100017500000000105313702133370021721 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_finish.v0000664000177100017500000000100613702133370021334 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/); import "DPI-C" function void dpii_test(); initial begin $write("*-* All Finished *-*\n"); dpii_test(); // $finish end endmodule verilator-4.038/test_regress/t/t_array_pattern_2d.v0000664000177100017500000000213713702133367022452 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 //bug991 module t (/*AUTOARG*/); logic [31:0] array_assign [3:0]; logic [31:0] array_other [3:0]; logic [31:0] larray_assign [0:3]; logic [31:0] larray_other [0:3]; initial begin array_assign[0] = 32'd1; array_assign[3:1] = '{32'd4, 32'd3, 32'd2}; array_other[0] = array_assign[0]+10; array_other[3:1] = array_assign[3:1]; if (array_other[0] != 11) $stop; if (array_other[1] != 2) $stop; if (array_other[2] != 3) $stop; if (array_other[3] != 4) $stop; larray_assign[0] = 32'd1; larray_assign[1:3] = '{32'd4, 32'd3, 32'd2}; larray_other[0] = larray_assign[0]+10; larray_other[1:3] = larray_assign[1:3]; if (larray_other[0] != 11) $stop; if (larray_other[1] != 4) $stop; if (larray_other[2] != 3) $stop; if (larray_other[3] != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_langext_order_sub.v0000664000177100017500000000055213702133370022711 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD module t_langext_order_sub(input do); endmodule verilator-4.038/test_regress/t/t_x_assign_unique_1.pl0000775000177100017500000000131713702133370022775 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_x_assign.v"); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--x-assign unique --exe $Self->{t_dir}/t_x_assign.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_abort.pl0000775000177100017500000000121513702133370021636 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( verilator_flags2 => ['--cc --trace'], ); execute( fails => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_const_bad.pl0000775000177100017500000000107413702133367021316 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_dotted1_inl2.pl0000775000177100017500000000120113702133370022504 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_var_dotted1.v"); compile( v_flags2 => ['+define+USE_INLINE_MID',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_pow5.pl0000775000177100017500000000105313702133370021254 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_block_redecl_bad.v0000664000177100017500000000074313702133370023451 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug485, but see t_gen_forif.v for an OK example. module t (/*AUTOARG*/ // Inputs clk ); input clk; always_comb begin integer i; for(i=0; i<10; i++ ) begin: COMB end for(i=0; i<9; i++ ) begin: COMB end end endmodule verilator-4.038/test_regress/t/t_tri_pull_bad.v0000664000177100017500000000043513702133370021643 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; wire A; pullup p1(A); pulldown p2(A); endmodule verilator-4.038/test_regress/t/t_timescale_lint_bad.pl0000775000177100017500000000114513702133370023155 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_timescale.pl0000775000177100017500000000120713702133370022311 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ["-timescale 1ms/1us"], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_shift.pl0000775000177100017500000000112413702133370021476 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-Wno-CLKDATA"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unopt_converge_unopt_bad.pl0000775000177100017500000000114713702133370024445 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2007 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_unopt_converge.v"); compile( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_queue_bounded.pl0000775000177100017500000000105313702133370022175 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_altera_lpm_fifo.pl0000775000177100017500000000120613702133367022502 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_dup_bad.out0000664000177100017500000000115513702133370021777 0ustar wsnyderwsnyder%Error: t/t_dpi_dup_bad.v:13:51: Duplicate declaration of DPI function with different formal arguments: 't.oth_f_int2' 13 | import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); | ^~~~~~~~~~ : ... New prototype: pure int dpii_fa_bit (int, int) t/t_dpi_dup_bad.v:12:47: ... Original prototype: int dpii_fa_bit (int) 12 | import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); | ^~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_bad2.pl0000775000177100017500000000112113702133370021170 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_bad.out0000664000177100017500000000271213702133370021306 0ustar wsnyderwsnyder%Error: t/t_func_bad.v:9:11: Missing argument on non-defaulted argument 'from2' in function call to FUNC 'add' : ... In instance t 9 | if (add(3'd1) != 0) $stop; | ^~~ %Error: t/t_func_bad.v:10:27: Too many arguments in function call to FUNC 'add' : ... In instance t 10 | if (add(3'd1, 3'd2, 3'd3) != 0) $stop; | ^~~~ %Error: t/t_func_bad.v:11:7: Missing argument on non-defaulted argument 'y' in function call to TASK 'x' : ... In instance t 11 | x; | ^ %Error-UNSUPPORTED: t/t_func_bad.v:11:7: Unsupported: Function output argument 'y' requires 1 bits, but connection's CONST '?32?h0' generates 32 bits. : ... In instance t 11 | x; | ^ %Error: t/t_func_bad.v:14:17: No such argument 'no_such' in function call to FUNC 'f' : ... In instance t 14 | f(.j(1), .no_such(2)); | ^~~~~~~ %Error: t/t_func_bad.v:15:19: Duplicate argument 'dup' in function call to FUNC 'f' : ... In instance t 15 | f(.dup(1), .dup(3)); | ^~~ %Error: t/t_func_bad.v:16:13: Too many arguments in function call to FUNC 'f' : ... In instance t 16 | f(1,2,3); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_mem_slice_bad.pl0000775000177100017500000000107413702133370022117 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_overlap_bad.out0000664000177100017500000000047613702133370023054 0ustar wsnyderwsnyder%Error: t/t_enum_overlap_bad.v:12:11: Overlapping enumeration value: 'e1b' : ... In instance t 12 | e1b=1 | ^~~ t/t_enum_overlap_bad.v:10:11: ... Location of original declaration 10 | e1, | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_flag_csplit.v0000664000177100017500000000225313702133370021472 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; parameter CNT = 5; wire [31:0] w [CNT:0]; generate for (genvar g=0; g 1); top_filename("t/t_var_pinsizes.v"); compile( verilator_flags2 => ['-cc'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); { file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN8 \(i1,0,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN8 \(i8,7,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN16 \(i16,15,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN \(i32,31,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN64 \(i64,63,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_INW \(i65,64,0,3\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8 \(o1,0,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8 \(o8,7,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT16\(o16,15,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT \(o32,31,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT64\(o64,63,0\);/x); file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUTW \(o65,64,0,3\);/x); } ok(1); 1; verilator-4.038/test_regress/t/t_bitsel_const_bad.out0000664000177100017500000000042113702133367023044 0ustar wsnyderwsnyder%Error: t/t_bitsel_const_bad.v:21:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... In instance t 21 | assign a = b[0]; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_inst_port_array.pl0000775000177100017500000000105313702133370022570 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_threads_counter_0.pl0000775000177100017500000000120713702133370022762 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_threads_counter.v"); compile( verilator_flags2 => ['--cc --no-threads'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_pull2_bad.v0000664000177100017500000000060313702133370021722 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; wire A; pullup p1(A); child child(/*AUTOINST*/ // Inouts .A (A)); endmodule module child(inout A); pulldown p2(A); endmodule verilator-4.038/test_regress/t/t_lint_subout_bad.pl0000775000177100017500000000121713702133370022530 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( # No --lint-only as got compile error verilator_flags2 => ["--trace"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_string.pl0000775000177100017500000000112513702133370022035 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--cc --trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_display.out0000664000177100017500000000063613702133370021714 0ustar wsnyderwsnyderpre thrupre thrumid thrupost post: "right side" left side: "right side" left side: "right side" left_side: "right_side" na: "right_side" prep ( midp1 left_side midp2 ( outp ) ): "right_side" na: "nana" left_side right_side: "left_side right_side" left side: "right side" : "" left side: "right side" left side: "right side" standalone twoline: "first second" Line 50 File "t/t_pp_display.v" *-* All Finished *-* verilator-4.038/test_regress/t/t_crazy_sel.pl0000775000177100017500000000105313702133370021344 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_delay_func_bad.v0000664000177100017500000000072013702133370022117 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); function int f; #1 $stop; f = 0; endfunction int i; initial begin i = f(); $write("*-* All Finished *-*\n"); $finish; end final begin #1; $stop; end endmodule verilator-4.038/test_regress/t/t_clk_scope_bad.pl0000775000177100017500000000110113702133367022121 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_stop_bad.v0000664000177100017500000000107013702133370021650 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/); import "DPI-C" function void dpii_test(); initial begin dpii_test(); $display("Should have stopped above"); //$write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_tri_select_unsized.pl0000775000177100017500000000107513702133370023253 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Compile only test compile( verilator_flags2 => ["-Wno-WIDTH"], ); ok(1); 1; verilator-4.038/test_regress/t/t_math_pow6.v0000664000177100017500000000266013702133370021111 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs i65, j65, i33, j33, i30, j30, q65, r65, q33, r33, q30, r30, w65, x65, w33, x33, w30, x30, // Inputs a, a40, a70 ); input [3:0] a; input [39:0] a40; input [69:0] a70; // -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI() // verilator lint_off WIDTH output [3:0] i65 = 65'd3 ** a; // WWI output [3:0] j65 = a ** 65'd3; // IIW output [3:0] i33 = 33'd3 ** a; // QQI output [3:0] j33 = a ** 33'd3; // IIQ output [3:0] i30 = 30'd3 ** a; // III output [3:0] j30 = a ** 30'd3; // III output [39:0] q65 = 65'd3 ** a40; // WWQ output [39:0] r65 = a40 ** 65'd3; // WWQ output [39:0] q33 = 33'd3 ** a40; // QQQ output [39:0] r33 = a40 ** 33'd3; // QQQ output [39:0] q30 = 30'd3 ** a40; // QQI output [39:0] r30 = a40 ** 30'd3; // QQI output [69:0] w65 = 65'd3 ** a70; // WWW output [69:0] x65 = a70 ** 65'd3; // WWW output [69:0] w33 = 33'd3 ** a70; // WWW output [69:0] x33 = a70 ** 33'd3; // WWW output [69:0] w30 = 30'd3 ** a70; // WWW output [69:0] x30 = a70 ** 30'd3; // WWW // verilator lint_on WIDTH initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_cover_line.vlt0000664000177100017500000000057413702133367021702 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config coverage_block_off -file "t/t_cover_line.v" -lines 137 coverage_block_off -file "t/t_cover_line.v" -lines 171 coverage_block_off -module "beta" -block "block" verilator-4.038/test_regress/t/t_param_scope_bad.out0000664000177100017500000000043513702133370022644 0ustar wsnyderwsnyder%Warning-CASEOVERLAP: t/t_param_scope_bad.v:28:9: Case values overlap (example pattern 0x2) 28 | 2'h2: $stop; | ^~~~ ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_fuzz_genintf_bad.pl0000775000177100017500000000107413702133370022672 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_randomize.v0000664000177100017500000000236313702133370021175 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int header; rand int length; extern constraint ex; constraint a { header > 0 && header < 1000; } constraint b { if (64 > header) { header < (64'h1 << length); } } constraint b { header >= length - 10; header <= length; } constraint c { foreach (in_use[i]) { !(start_offset <= in_use[i].Xend_offsetX && start_offset + len - 1 >= in_use[i].Xstart_offsetX); } } constraint order { solve length before header; } constraint dis { disable soft x; x dist { [100:102] :/ 1, 200 := 2, 300 := 5}; } endclass module t (/*AUTOARG*/); Packet p; initial begin int v; v = p.randomize(); if (v != 1) $stop; v = p.randomize(1); if (v != 1) $stop; v = p.randomize(1, 2); if (v != 1) $stop; v = p.randomize() with {}; if (v != 1) $stop; // Not testing other randomize forms as unused in UVM $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_array.v0000664000177100017500000000336513702133370022346 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; modport source ( output a ); modport sink ( input a ); endinterface function integer identity (input integer val); return val; endfunction module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam N = 5; logic [N-1:0] a_in; logic [N-1:0] a_out; logic [N-1:0] ack_out; foo_intf foos [N-1:0] (); // Deferred link dotting with genvars generate genvar i; for (i = 0; i < N-4; i++) begin : someLoop assign ack_out[i] = a_in[i]; assign foos[i].a = a_in[i]; assign a_out[i] = foos[i].a; end endgenerate // Defferred link dotting with localparam localparam THE_LP = N-3; assign ack_out[THE_LP] = a_in[THE_LP]; assign foos[THE_LP].a = a_in[THE_LP]; assign a_out[THE_LP] = foos[THE_LP].a; // Defferred link dotting with arithmetic expression assign ack_out[N-2] = a_in[N-2]; assign foos[N-2].a = a_in[N-2]; assign a_out[N-2] = foos[N-2].a; // Defferred link dotting with funcrefs assign ack_out[identity(N-1)] = a_in[identity(N-1)]; assign foos[identity(N-1)].a = a_in[identity(N-1)]; assign a_out[identity(N-1)] = foos[identity(N-1)].a; initial a_in = '0; always @(posedge clk) begin a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; if (ack_out != a_out) begin $display("%%Error: Interface and non-interface paths do not match: 0b%b 0b%b", ack_out, a_out); $stop; end if (& a_in) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_mem_multi_io2_cc.pl0000775000177100017500000000134713702133370022565 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_mem_multi_io2.v"); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/t_mem_multi_io2.cpp -Oi"], verilator_flags3 => [], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_nofile_bad.pl0000775000177100017500000000124313702133370022425 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); run(cmd => ["../bin/verilator --lint-only"], fails => 1, logfile => "$Self->{obj_dir}/sim.log", expect_filename => $Self->{golden_filename}, verilator_run => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vams_kwd_bad.v0000664000177100017500000000256313702133370021630 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" module t (/*AUTOARG*/); // Just get errors on bad keywords (for code coverage) int above; int abs; int absdelay; int abstol; int ac_stim; int access; int acos; int acosh; int aliasparam; int analog; int analysis; int assert; int branch; int connect; int connectmodule; int connectrules; int continuous; int cross; int ddt; int ddt_nature; int ddx; int discipline; int discrete; int domain; int driver_update; int endconnectrules; int enddiscipline; int endnature; int endparamset; int exclude; int final_step; int flicker_noise; int flow; int from; int ground; int idt; int idt_nature; int idtmod; int inf; int initial_step; int laplace_nd; int laplace_np; int laplace_zd; int laplace_zp; int last_crossing; int limexp; int max; int merged; int min; int nature; int net_resolution; int noise_table; int paramset; int potential; int resolveto; int slew; int split; int timer; int transition; int units; int white_noise; int zi_nd; int zi_np; int zi_zd; int zi_zp; endmodule verilator-4.038/test_regress/t/t_initial_edge_bad.pl0000775000177100017500000000131313702133370022573 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This works with other vlt_alls, we we don't run it for them. It should # fail with Verilator if --x-initial-edge is not specified. scenarios(vlt_all => 1); top_filename("t/t_initial_edge.v"); compile( ); execute( fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_implication.pl0000775000177100017500000000113313702133367023247 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert --cc'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_string.pl0000775000177100017500000000105313702133370020657 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_const_bad.v0000664000177100017500000000072513702133370022011 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; const logic [2:0] five = 3'd5; always @ (posedge clk) begin five = 3'd4; if (five !== 3'd5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_wait.v0000664000177100017500000000134213702133370020145 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); int value; initial begin wait (value == 1); if (value != 1) $stop; wait (0); if (value != 1) $stop; // wait (value == 2); if (value != 2) $stop; // wait (value == 3) if (value != 3) $stop; if (value != 3) $stop; end initial begin #10; value = 1; #10; value = 2; #10; value = 3; #10; value = 4; #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_select_bad_range.pl0000775000177100017500000000111313702133370022607 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_inout.v0000664000177100017500000000120213702133370021210 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module top (input A, input B, input SEL, output Y1, output Y2, output Z); io io1(.A(A), .OE( SEL), .Z(Z), .Y(Y1)); pass io2(.A(B), .OE(!SEL), .Z(Z), .Y(Y2)); assign Z = 1'bz; endmodule module pass (input A, input OE, inout Z, output Y); io io(.A(A), .OE(OE), .Z(Z), .Y(Y)); assign Z = 1'bz; endmodule module io (input A, input OE, inout Z, output Y); assign Z = (OE) ? A : 1'bz; assign Y = Z; assign Z = 1'bz; endmodule verilator-4.038/test_regress/t/t_inst_dtree_inlcd.pl0000775000177100017500000000125113702133370022662 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_C +define+INLINE_D'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_inout_type.pl0000775000177100017500000000256113702133370023242 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if ($Self->{nc}) { # For NC, compile twice, first just to generate DPI headers compile( nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] ); } compile( v_flags2 => ["t/t_dpi_arg_inout_type.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], # NC: Gdd the obj_dir to the C include path nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", "-ccflags -I$Self->{obj_dir}"], ); if ($Self->{vlt_all}) { files_identical( "$Self->{obj_dir}/Vt_dpi_arg_inout_type__Dpi.h", "t/t_dpi_arg_inout_type__Dpi.out" ); } execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ms_pli => 0 ); ok(1); 1; verilator-4.038/test_regress/t/t_time_vpi_1s10ns.pl0000775000177100017500000000150713702133370022276 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator_st => 1); top_filename("t/t_time_vpi.v"); $Self->{main_time_multiplier} = 1e0 / 10e-9; compile( v_flags2 => ['+define+time_scale_units=1s +define+time_scale_prec=10ns', 't/t_time_vpi_c.cpp'], verilator_flags2 => ['--vpi'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_signed2.pl0000775000177100017500000000105313702133370021715 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_slice_part_select.pl0000775000177100017500000000105313702133370024072 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_optm_redor.v0000664000177100017500000000406513702133370021360 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [15:0] in = crc[15:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out), // Inputs .in (in[15:0])); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h162c58b1635b8d6e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [15:0] in; output reg out; // TODO this should flatten into a reduction OR always_comb begin out = 0; for (int i=0; i<16; i=i+1) begin if (in[i]) begin out = 1; end end end endmodule verilator-4.038/test_regress/t/t_preproc_kwd.v0000664000177100017500000000242013702133370021516 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; v95 v95 (); v01 v01 (); v05 v05 (); s05 s05 (); s09 s09 (); s12 s12 (); s17 s17 (); a23 a23 (); initial begin $finish; end endmodule `begin_keywords "1364-1995" module v95; integer signed; initial signed = 1; endmodule `end_keywords `begin_keywords "1364-2001" module v01; integer bit; initial bit = 1; endmodule `end_keywords `begin_keywords "1364-2005" module v05; integer final; initial final = 1; endmodule `end_keywords `begin_keywords "1800-2005" module s05; integer global; initial global = 1; endmodule `end_keywords `begin_keywords "1800-2009" module s09; integer soft; initial soft = 1; endmodule `end_keywords `begin_keywords "1800-2012" module s12; final begin $write("*-* All Finished *-*\n"); end endmodule `end_keywords `begin_keywords "1800-2017" module s17; final begin $write("*-* All Finished *-*\n"); end endmodule `end_keywords `begin_keywords "VAMS-2.3" module a23; real foo; initial foo = sqrt(2.0); endmodule `end_keywords verilator-4.038/test_regress/t/t_lint_blksync_loop.pl0000775000177100017500000000107613702133370023102 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"], ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_property_fail_2.pl0000775000177100017500000000134013702133367024037 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_property.v"); compile( v_flags2 => ['+define+FAIL_ASSERT_2'], verilator_flags2 => ['--assert --cc'], ); execute( fails => 1 ); file_grep($Self->{run_log_filename}, qr/'assert' failed/); ok(1); 1; verilator-4.038/test_regress/t/t_event.pl0000775000177100017500000000105313702133370020472 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_rand.pl0000775000177100017500000000105313702133370021173 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_cmtend_bad.out0000664000177100017500000000013713702133370023356 0ustar wsnyderwsnyder%Error: t/t_preproc_cmtend_bad.v:10:1: EOF in '/* ... */' block comment %Error: Exiting due to verilator-4.038/test_regress/t/t_vpi_get.v0000664000177100017500000000365613702133370020650 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function integer mon_check(); `endif `ifdef VERILATOR_COMMENTS `define PUBLIC_FLAT_RD /*verilator public_flat_rd*/ `define PUBLIC_FLAT_RW /*verilator public_flat_rw @(posedge clk)*/ `else `define PUBLIC_FLAT_RD `define PUBLIC_FLAT_RW `endif module t (/*AUTOARG*/ // Inputs input clk `PUBLIC_FLAT_RD, // test ports input [15:0] testin `PUBLIC_FLAT_RD, output [23:0] testout `PUBLIC_FLAT_RW ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif reg onebit `PUBLIC_FLAT_RW; reg [2:1] twoone `PUBLIC_FLAT_RW; reg onetwo [1:2] `PUBLIC_FLAT_RW; reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW; integer status; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3]; `endif wire subin `PUBLIC_FLAT_RD; wire subout `PUBLIC_FLAT_RD; sub sub(.*); // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t module sub ( input subin `PUBLIC_FLAT_RD, output subout `PUBLIC_FLAT_RD ); endmodule : sub verilator-4.038/test_regress/t/t_trace_complex_params_fst.out0000664000177100017500000001012313702133370024604 0ustar wsnyderwsnyder$date Sun Apr 19 04:15:31 2020 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $var logic 2 # v_strp $end $var logic 4 $ v_strp_strp $end $var logic 2 % v_unip_strp $end $var logic 2 & v_arrp $end $var logic 4 ' v_arrp_arrp $end $var logic 4 ( v_arrp_strp $end $var logic 1 ) v_arru(1) $end $var logic 1 * v_arru(2) $end $var logic 1 + v_arru_arru(3)(1) $end $var logic 1 , v_arru_arru(3)(2) $end $var logic 1 - v_arru_arru(4)(1) $end $var logic 1 . v_arru_arru(4)(2) $end $var logic 2 / v_arru_arrp(3) $end $var logic 2 0 v_arru_arrp(4) $end $var logic 2 1 v_arru_strp(3) $end $var logic 2 2 v_arru_strp(4) $end $var real 64 3 v_real $end $var real 64 4 v_arr_real(0) $end $var real 64 5 v_arr_real(1) $end $var logic 64 6 v_str32x2 $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var logic 32 7 v_enumed $end $attrbegin misc 07 "" 1 $end $var logic 32 8 v_enumed2 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 9 v_enumb $end $var logic 6 : v_enumb2_str $end $var logic 8 ; unpacked_array(-2) $end $var logic 8 < unpacked_array(-1) $end $var logic 8 = unpacked_array(0) $end $scope module unnamedblk1 $end $var integer 32 > b $end $scope module unnamedblk2 $end $var integer 32 ? a $end $upscope $end $upscope $end $scope module p2 $end $var parameter 32 @ PARAM $end $upscope $end $scope module p3 $end $var parameter 32 A PARAM $end $upscope $end $upscope $end $scope module $unit $end $var bit 1 B global_bit $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000000000000000000000000000000 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( 0) 0* 0+ 0, 0- 0. b00 / b00 0 b00 1 b00 2 r0 3 r0 4 r0 5 b0000000000000000000000000000000000000000000000000000000011111111 6 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 b000 9 b000000 : b00000000 ; b00000000 < b00000000 = b00000000000000000000000000000000 > b00000000000000000000000000000000 ? b00000000000000000000000000000010 @ b00000000000000000000000000000011 A 1B #10 b00000000000000000000000000000101 ? b00000000000000000000000000000101 > b111 9 b00000000000000000000000000000010 8 b00000000000000000000000000000001 7 b0000000000000000000000000000000100000000000000000000000011111110 6 r0.3 5 r0.2 4 r0.1 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000001 " 1! #15 0! #20 1! b00000000000000000000000000000010 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.2 3 r0.4 4 r0.6 5 b0000000000000000000000000000001000000000000000000000000011111101 6 b00000000000000000000000000000010 7 b00000000000000000000000000000100 8 b110 9 b111111 : #25 0! #30 1! b110110 : b101 9 b00000000000000000000000000000110 8 b00000000000000000000000000000011 7 b0000000000000000000000000000001100000000000000000000000011111100 6 r0.8999999999999999 5 r0.6000000000000001 4 r0.3 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000011 " #35 0! #40 1! b00000000000000000000000000000100 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.4 3 r0.8 4 r1.2 5 b0000000000000000000000000000010000000000000000000000000011111011 6 b00000000000000000000000000000100 7 b00000000000000000000000000001000 8 b100 9 b101101 : #45 0! #50 1! b100100 : b011 9 b00000000000000000000000000001010 8 b00000000000000000000000000000101 7 b0000000000000000000000000000010100000000000000000000000011111010 6 r1.5 5 r1 4 r0.5 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000101 " #55 0! #60 1! b00000000000000000000000000000110 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.6 3 r1.2 4 r1.8 5 b0000000000000000000000000000011000000000000000000000000011111001 6 b00000000000000000000000000000110 7 b00000000000000000000000000001100 8 b010 9 b011011 : verilator-4.038/test_regress/t/t_alw_split_rst.v0000664000177100017500000000747513702133367022112 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] in = crc[3:0]; wire clken = crc[4]; wire rstn = !(cyc < 20 || (crc[11:8]==0)); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] ff_out; // From test of Test.v wire [3:0] fg_out; // From test of Test.v wire [3:0] fh_out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .ff_out (ff_out[3:0]), .fg_out (fg_out[3:0]), .fh_out (fh_out[3:0]), // Inputs .clk (clk), .clken (clken), .rstn (rstn), .in (in[3:0])); // Aggregate outputs into a single result vector wire [63:0] result = {52'h0, ff_out, fg_out, fh_out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h77979747fd1b3a5a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs ff_out, fg_out, fh_out, // Inputs clk, clken, rstn, in ); input clk; input clken; input rstn; input [3:0] in; output reg [3:0] ff_out; reg [3:0] ff_10; reg [3:0] ff_11; reg [3:0] ff_12; reg [3:0] ff_13; always @(posedge clk) begin if ((rstn == 0)) begin ff_10 <= 0; ff_11 <= 0; ff_12 <= 0; ff_13 <= 0; end else begin ff_10 <= in; ff_11 <= ff_10; ff_12 <= ff_11; ff_13 <= ff_12; ff_out <= ff_13; end end output reg [3:0] fg_out; reg [3:0] fg_10; reg [3:0] fg_11; reg [3:0] fg_12; reg [3:0] fg_13; always @(posedge clk) begin if (clken) begin if ((rstn == 0)) begin fg_10 <= 0; fg_11 <= 0; fg_12 <= 0; fg_13 <= 0; end else begin fg_10 <= in; fg_11 <= fg_10; fg_12 <= fg_11; fg_13 <= fg_12; fg_out <= fg_13; end end end output reg [3:0] fh_out; reg [3:0] fh_10; reg [3:0] fh_11; reg [3:0] fh_12; reg [3:0] fh_13; always @(posedge clk) begin if ((rstn == 0)) begin fh_10 <= 0; fh_11 <= 0; fh_12 <= 0; fh_13 <= 0; end else begin if (clken) begin fh_10 <= in; fh_11 <= fh_10; fh_12 <= fh_11; fh_13[3:1] <= fh_12[3:1]; fh_13[0] <= fh_12[0]; fh_out <= fh_13; end end end endmodule verilator-4.038/test_regress/t/t_select_plusloop.v0000664000177100017500000000347113702133370022422 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] narrow; reg [63:0] quad; reg [127:0] wide; integer cyc; initial cyc=0; reg [7:0] crc; reg [6:0] index; always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b n=%x\n",$time, cyc, crc, narrow); cyc <= cyc + 1; if (cyc==0) begin // Setup narrow <= 32'h0; quad <= 64'h0; wide <= 128'h0; crc <= 8'hed; index <= 7'h0; end else if (cyc<90) begin index <= index + 7'h2; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; // verilator lint_off WIDTH if (index < 9'd20) narrow[index +: 3] <= crc[2:0]; if (index < 9'd60) quad [index +: 3] <= crc[2:0]; if (index < 9'd120) wide [index +: 3] <= crc[2:0]; // narrow[index[3:0]] <= ~narrow[index[3:0]]; quad [~index[3:0]]<= ~quad [~index[3:0]]; wide [~index[3:0]] <= ~wide [~index[3:0]]; // verilator lint_on WIDTH end else if (cyc==90) begin wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6; wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6; wide[82 +: 4] <=4'h6; end else if (cyc==91) begin wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1; wide[41] <=1'b1; quad[41] <=1'b1; wide[81] <=1'b1; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n",$time, cyc, crc, narrow, quad, wide); if (crc != 8'b01111001) $stop; if (narrow != 32'h001661c7) $stop; if (quad != 64'h16d49b6f64266039) $stop; if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_var_rsvd.pl0000775000177100017500000000105313702133370021177 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_lib.v0000664000177100017500000000046613702133370020454 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_pp_lib_inc.vh" module t(); wire [`WIDTH-1:0] a; library_cell n1(a); endmodule verilator-4.038/test_regress/t/t_prot_lib_inout_bad.v0000664000177100017500000000061113702133370023035 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module secret_impl ( input a, input oe, inout z, output y); assign z = oe ? a : 1'bz; assign y = z; endmodule verilator-4.038/test_regress/t/t_class_new.v0000664000177100017500000000137513702133367021173 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsNoArg; int imembera; function new(); imembera = 5; endfunction endclass class ClsArg; int imembera; function new(int i); imembera = i + 1; endfunction function int geta; return imembera; endfunction endclass module t (/*AUTOARG*/); initial begin ClsNoArg c1; ClsArg c2; c1 = new; if (c1.imembera != 5) $stop; c2 = new(2); if (c2.imembera != 3) $stop; if (c2.geta() != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_concat_bad.out0000664000177100017500000000166413702133370023007 0ustar wsnyderwsnyder%Warning-WIDTHCONCAT: t/t_param_concat.v:19:15: Unsized numbers/parameters not allowed in concatenations. : ... In instance t 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; | ^~~~~~~ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_param_concat.v:19:22: Unsized numbers/parameters not allowed in replications. : ... In instance t 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; | ^ %Warning-WIDTHCONCAT: t/t_param_concat.v:20:17: Unsized numbers/parameters not allowed in replications. : ... In instance t 20 | if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_dotted1.v0000664000177100017500000001331113702133370021414 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // verilator lint_off MULTIDRIVEN wire [31:0] outb0c0; wire [31:0] outb0c1; wire [31:0] outb1c0; wire [31:0] outb1c1; reg [7:0] lclmem [7:0]; ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1), .outb1c0(outb1c0), .outb1c1(outb1c1) ); global_mod #(32'hf00d) global_cell (); global_mod #(32'hf22d) global_cell2 (); input clk; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1); `endif if (cyc==2) begin if (global_cell.globali != 32'hf00d) $stop; if (global_cell2.globali != 32'hf22d) $stop; if ($root.t.global_cell.globali != 32'hf00d) $stop; if ($root.t.global_cell2.globali != 32'hf22d) $stop; if (outb0c0 != 32'h00) $stop; if (outb0c1 != 32'h01) $stop; if (outb1c0 != 32'h10) $stop; if (outb1c1 != 32'h11) $stop; end if (cyc==3) begin // Can we scope down and read and write vars? ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100; ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100; ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100; ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100; end if (cyc==4) begin // Can we do dotted's inside array sels? ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12; lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24; if (outb0c0 != 32'h100) $stop; if (outb0c1 != 32'h101) $stop; if (outb1c0 != 32'h110) $stop; if (outb1c1 != 32'h111) $stop; end if (cyc==5) begin if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop; if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop; if (outb0c0 != 32'h1100) $stop; if (outb0c1 != 32'h2101) $stop; if (outb1c0 != 32'h2110) $stop; if (outb1c1 != 32'h3111) $stop; end if (cyc==6) begin if (outb0c0 != 32'h31100) $stop; if (outb0c1 != 32'h02101) $stop; if (outb1c0 != 32'h42110) $stop; if (outb1c1 != 32'h03111) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule `ifdef USE_INLINE_MID `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator no_inline_module*/ `else `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `define INLINE_MID_MODULE /*verilator public_module*/ `endif `endif module global_mod; `INLINE_MODULE parameter INITVAL = 0; integer globali; initial globali = INITVAL; endmodule module ma ( output wire [31:0] outb0c0, output wire [31:0] outb0c1, output wire [31:0] outb1c0, output wire [31:0] outb1c1 ); `INLINE_MODULE reg [7:0] rmtmem [7:0]; mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1)); mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1)); endmodule module mb ( output wire [31:0] outc0, output wire [31:0] outc1 ); `INLINE_MID_MODULE parameter P2 = 0; mc #(P2,0) mc0 (.out(outc0)); mc #(P2,1) mc1 (.out(outc1)); global_mod #(32'hf33d) global_cell2 (); wire reach_up_clk = t.clk; always @(reach_up_clk) begin if (P2==0) begin // Only for mb0 if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances if (outc0 !== mc0.out) $stop; // Lower instances if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances if (outc1 !== mc1.out) $stop; // Lower instances end end endmodule module mc (output reg [31:0] out); `INLINE_MODULE parameter P2 = 0; parameter P3 = 0; initial begin out = {24'h0,P2[3:0],P3[3:0]}; //$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out); end // Can we look from the top module name down? wire [31:0] reach_up_cyc = t.cyc; always @ (posedge t.clk) begin //$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc); if (reach_up_cyc==2) begin if (global_cell.globali != 32'hf00d) $stop; if (global_cell2.globali != 32'hf33d) $stop; end if (reach_up_cyc==4) begin out[15:12] <= {P2[3:0]+P3[3:0]+4'd1}; end if (reach_up_cyc==5) begin // Can we set another instance? if (P3==1) begin // Without this, there are two possible correct answers... mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}; $display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2); end end end endmodule verilator-4.038/test_regress/t/t_mem_shift.pl0000775000177100017500000000127713702133370021334 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats"], ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Delayed shared-sets\s+(\d+)/i, 14); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_altera_lpm_bustri.pl0000775000177100017500000000120613702133367023067 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_alw_combdly.v0000664000177100017500000000252713702133367021511 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] a, b, c, d, e, f, g, h; always @ (*) begin // Test Verilog 2001 (*) // verilator lint_off COMBDLY c <= a | b; // verilator lint_on COMBDLY end always @ (posedge (clk)) begin // always bug 2008/4/18 d <= a | b; end always @ ((d)) begin // always bug 2008/4/18 e = d; end parameter CONSTANT = 1; always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412 f = e; end always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412 g = f; end always @ ({CONSTANT, g}) begin // bug745 h = g; end //always @ ((posedge b) or (a or b)) begin // note both illegal always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==1) begin a <= 32'hfeed0000; b <= 32'h0000face; end if (cyc==2) begin if (c != 32'hfeedface) $stop; end if (cyc==3) begin if (h != 32'hfeedface) $stop; end if (cyc==7) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_dist_cinclude.pl0000775000177100017500000000406413702133370022167 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; scenarios(dist => 1); my $root = ".."; my $Debug; if (!-r "$root/.git") { skip("Not in a git repository"); } else { ### Must trim output before and after our file list my $files = `cd $root && git ls-files --exclude-standard`; print "ST $files\n" if $Debug; $files =~ s/\s+/ /g; my $cmd = "cd $root && fgrep -n include $files | sort"; my $grep = `$cmd`; foreach my $line (split /\n/, $grep) { next if $line =~ m!include/vltstd/vpi_user.h!; # IEEE Standard file - can't change it next if $line =~ m!include/gtkwave/!; # Standard file - can't change it my $hit; $hit = 1 if $line =~ /\bassert\.h/; $hit = 1 if $line =~ /\bctype\.h/; $hit = 1 if $line =~ /\berrno\.h/; $hit = 1 if $line =~ /\bfloat\.h/; $hit = 1 if $line =~ /\blimits\.h/; $hit = 1 if $line =~ /\blocale\.h/; $hit = 1 if $line =~ /\bmath\.h/; $hit = 1 if $line =~ /\bsetjmp\.h/; $hit = 1 if $line =~ /\bsignal\.h/; $hit = 1 if $line =~ /\bstdarg\.h/; $hit = 1 if $line =~ /\bstdbool\.h/; $hit = 1 if $line =~ /\bstddef\.h/; #Not yet: $hit = 1 if $line =~ /\bstdint\.h/; $hit = 1 if $line =~ /\bstdio\.h/; $hit = 1 if $line =~ /\bstdlib\.h/; $hit = 1 if $line =~ /\bstring\.h/; $hit = 1 if $line =~ /\btime\.h/ && $line !~ m!sys/time.h!; next if !$hit; print "$line\n"; $names{$1} = 1 if $line =~ /^([^:]+)/; } if (keys %names) { error("Files like stdint.h instead of cstdint: ",join(' ',sort keys %names)); } } ok(1); 1; verilator-4.038/test_regress/t/t_increment_bad.out0000664000177100017500000000221013702133370022330 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_increment_bad.v:15:31: Unsupported: Incrementation in this context. 15 | if (0 && test_string[pos++] != "e"); | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:16:19: Unsupported: Incrementation in this context. 16 | if (1 || pos-- != 1); | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:18:17: Unsupported: Incrementation in this context. 18 | if (a <-> --b); | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:19:16: Unsupported: Incrementation in this context. 19 | if (0 -> ++b); | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:21:24: Unsupported: Incrementation in this context. 21 | pos = (a > 0) ? a++ : --b; | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:21:29: Unsupported: Incrementation in this context. 21 | pos = (a > 0) ? a++ : --b; | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:23:24: Unsupported: Incrementation in this context. 23 | pos = array[0][0]++; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_gantt.pl0000775000177100017500000000547513702133370020502 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; # Test for bin/verilator_gantt, # # Only needed in multithreaded regression. scenarios(vltmt => 1); # It doesn't really matter what test # we use, so long as it runs several cycles, # enough for the profiling to happen: top_filename("t/t_gen_alw.v"); compile( # Checks below care about thread count, so use 2 (minimum reasonable) v_flags2 => ["--prof-threads --threads 2"] ); execute( all_run_flags => ["+verilator+prof+threads+start+2", " +verilator+prof+threads+window+2", " +verilator+prof+threads+file+$Self->{obj_dir}/profile_threads.dat", ], check_finished => 1, ); # For now, verilator_gantt still reads from STDIN # (probably it should take a file, gantt.dat like verilator_profcfunc) # The profiling data still goes direct to the runtime's STDOUT # (maybe that should go to a separate file - gantt.dat?) run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_gantt", "$Self->{obj_dir}/profile_threads.dat", "--vcd $Self->{obj_dir}/profile_threads.vcd", "> $Self->{obj_dir}/gantt.log"], verilator_run => 1, ); # We should have three lines of gantt chart, each with # an even number of mtask-bars (eg "[123--]") my $gantt_line_ct = 0; my $global_mtask_ct = 0; { my $fh = IO::File->new("<$Self->{obj_dir}/gantt.log") or error("$! $Self->{obj_dir}/gantt.log"); while (my $line = ($fh && $fh->getline)) { if ($line !~ m/^ t:/) { next; } $gantt_line_ct++; my $this_thread_mtask_ct = 0; my @mtasks = split(/\[/, $line); shift @mtasks; # throw the '>> ' away foreach my $mtask (@mtasks) { # Format of each mtask is "[123--]" where the hyphens # number or ] may or may not appear; it depends on exact timing. $this_thread_mtask_ct++; $global_mtask_ct++; } if ($this_thread_mtask_ct % 2 != 0) { error("odd number of mtasks found"); } } } if ($gantt_line_ct != 2) { error("wrong number of gantt lines"); } if ($global_mtask_ct == 0) { error("wrong number of mtasks, should be > 0"); } print "Found $gantt_line_ct lines of gantt data with $global_mtask_ct mtasks\n" if $Self->{verbose}; # Diff to itself, just to check parsing vcd_identical("$Self->{obj_dir}/profile_threads.vcd", "$Self->{obj_dir}/profile_threads.vcd"); ok(1); 1; verilator-4.038/test_regress/t/t_extend_class.pl0000775000177100017500000000114113702133370022023 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_flags => "CPPFLAGS_ADD=-I$Self->{t_dir}", ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_mnpipe.v0000664000177100017500000000275513702133370021537 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [7:0] crc; reg [2:0] sum; wire [2:0] in = crc[2:0]; wire [2:0] out; MxN_pipeline pipe (in, out, clk); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b sum=%x\n",$time, cyc, crc, sum); cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==0) begin // Setup crc <= 8'hed; sum <= 3'h0; end else if (cyc>10 && cyc<90) begin sum <= {sum[1:0],sum[2]} ^ out; end else if (cyc==99) begin if (crc !== 8'b01110000) $stop; if (sum !== 3'h3) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module dffn (q,d,clk); parameter BITS = 1; input [BITS-1:0] d; output reg [BITS-1:0] q; input clk; always @ (posedge clk) begin q <= d; end endmodule module MxN_pipeline (in, out, clk); parameter M=3, N=4; input [M-1:0] in; output [M-1:0] out; input clk; // Unsupported: Per-bit array instantiations with output connections to non-wires. //wire [M*(N-1):1] t; //dffn #(M) p[N:1] ({out,t},{t,in},clk); wire [M*(N-1):1] w; wire [M*N:1] q; dffn #(M) p[N:1] (q,{w,in},clk); assign {out,w} = q; endmodule verilator-4.038/test_regress/t/t_array_interface.v0000664000177100017500000000261213702133367022346 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 interface intf; logic logic_in_intf; modport source(output logic_in_intf); modport sink(input logic_in_intf); endinterface module modify_interface ( input logic value, intf.source intf_inst ); assign intf_inst.logic_in_intf = value; endmodule function integer return_3(); return 3; endfunction module t #( parameter N = 6 )(); intf ifs[N-1:0] (); logic [N-1:0] data; assign data = {1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1}; generate genvar i; for (i = 0;i < 3; i++) begin assign ifs[i].logic_in_intf = data[i]; end endgenerate modify_interface m3 ( .value(data[return_3()]), .intf_inst(ifs[return_3()])); modify_interface m4 ( .value(data[4]), .intf_inst(ifs[4])); modify_interface m5 ( .value(~ifs[4].logic_in_intf), .intf_inst(ifs[5])); generate genvar j; for (j = 0;j < N-1; j++) begin initial begin if (ifs[j].logic_in_intf != data[j]) $stop; end end endgenerate initial begin if (ifs[5].logic_in_intf != ~ifs[4].logic_in_intf) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_flag_xinitial_0.v0000664000177100017500000000102713702133370022232 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs value ); output reg [63:0] value; initial begin `ifdef VERILATOR // Default is all ones, so we assume that here if (value != '0) $stop; `else if (value != {64{1'bx}}) $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_verilated_all_oldest.pl0000775000177100017500000000110713702133370023532 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); # This test now does nothing, because using DRIVER_STD=oldest tends to blow up glibc. ok(1); 1; verilator-4.038/test_regress/t/t_type_param.pl0000775000177100017500000000105213702133370021511 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_typedef_package.pl0000775000177100017500000000105313702133370022464 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_regfirst.v0000664000177100017500000000247513702133370022051 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [2:0] a; reg [2:0] b; reg q; f6 f6 (/*AUTOINST*/ // Outputs .q (q), // Inputs .a (a[2:0]), .b (b[2:0]), .clk (clk)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 3'b000; b <= 3'b100; end if (cyc==2) begin a <= 3'b011; b <= 3'b001; if (q != 1'b0) $stop; end if (cyc==3) begin a <= 3'b011; b <= 3'b011; if (q != 1'b0) $stop; end if (cyc==9) begin if (q != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module f6 (a, b, clk, q); input [2:0] a; input [2:0] b; input clk; output q; reg out; function func6; reg result; input [5:0] src; begin if (src[5:0] == 6'b011011) begin result = 1'b1; end else begin result = 1'b0; end func6 = result; end endfunction wire [5:0] w6 = {a, b}; always @(posedge clk) begin out <= func6(w6); end assign q = out; endmodule verilator-4.038/test_regress/t/t_trace_param.pl0000775000177100017500000000111313702133370021624 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( v_flags2 => ["--trace"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_public.v0000664000177100017500000000275213702133370021643 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire CLK, output reg RESET ); neg neg (.clk(CLK)); little little (.clk(CLK)); glbl glbl (); // A vector logic [2:1] vec [4:3]; integer val = 0; always @ (posedge CLK) begin if (RESET) val <= 0; else val <= val + 1; vec[3] <= val[1:0]; vec[4] <= val[3:2]; end initial RESET = 1'b1; always @ (posedge CLK) RESET <= glbl.GSR; endmodule module glbl(); `ifdef PUB_FUNC reg GSR; task setGSR; `ifdef ATTRIBUTES /* verilator public */ `endif input value; GSR = value; endtask `else `ifdef ATTRIBUTES reg GSR /*verilator public*/; `else reg GSR; `endif `endif endmodule module neg ( input clk ); reg [0:-7] i8; initial i8 = '0; reg [-1:-48] i48; initial i48 = '0; reg [63:-64] i128; initial i128 = '0; always @ (posedge clk) begin i8 <= ~i8; i48 <= ~i48; i128 <= ~i128; end endmodule module little ( input clk ); // verilator lint_off LITENDIAN reg [0:7] i8; initial i8 = '0; reg [1:49] i48; initial i48 = '0; reg [63:190] i128; initial i128 = '0; // verilator lint_on LITENDIAN always @ (posedge clk) begin i8 <= ~i8; i48 <= ~i48; i128 <= ~i128; end endmodule verilator-4.038/test_regress/t/t_dpi_result_type_bad.out0000664000177100017500000010501013702133370023561 0ustar wsnyderwsnyder%Error: t/t_dpi_result_type_bad.v:79:40: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 79 | import "DPI-C" function bit [ 32:0] i_array_2_state_33(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:80:40: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 80 | import "DPI-C" function bit [ 63:0] i_array_2_state_64(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:81:40: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 81 | import "DPI-C" function bit [ 64:0] i_array_2_state_65(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:82:40: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 82 | import "DPI-C" function bit [127:0] i_array_2_state_128(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:85:48: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 85 | import "DPI-C" function array_2_state_33_t i_array_2_state_33_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:86:48: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 86 | import "DPI-C" function array_2_state_64_t i_array_2_state_64_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:87:48: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 87 | import "DPI-C" function array_2_state_65_t i_array_2_state_65_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:88:48: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 88 | import "DPI-C" function array_2_state_128_t i_array_2_state_128_t(); | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:91:47: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 91 | import "DPI-C" function struct_2_state_33 i_struct_2_state_33(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:92:47: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 92 | import "DPI-C" function struct_2_state_64 i_struct_2_state_64(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:93:47: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 93 | import "DPI-C" function struct_2_state_65 i_struct_2_state_65(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:94:47: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 94 | import "DPI-C" function struct_2_state_128 i_struct_2_state_128(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:97:46: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 97 | import "DPI-C" function union_2_state_33 i_union_2_state_33(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:98:46: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 98 | import "DPI-C" function union_2_state_64 i_union_2_state_64(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:99:46: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 99 | import "DPI-C" function union_2_state_65 i_union_2_state_65(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:100:46: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 100 | import "DPI-C" function union_2_state_128 i_union_2_state_128(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:103:36: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 103 | import "DPI-C" function integer i_integer(); | ^~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:106:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 106 | import "DPI-C" function logic [ 0:0] i_array_4_state_1(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:107:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 107 | import "DPI-C" function logic [ 1:0] i_array_4_state_2(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:108:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 108 | import "DPI-C" function logic [ 7:0] i_array_4_state_8(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:109:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 109 | import "DPI-C" function logic [ 8:0] i_array_4_state_9(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:110:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 110 | import "DPI-C" function logic [ 15:0] i_array_4_state_16(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:111:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 111 | import "DPI-C" function logic [ 16:0] i_array_4_state_17(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:112:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 112 | import "DPI-C" function logic [ 31:0] i_array_4_state_32(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:113:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 113 | import "DPI-C" function logic [ 32:0] i_array_4_state_33(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:114:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 114 | import "DPI-C" function logic [ 63:0] i_array_4_state_64(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:115:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 115 | import "DPI-C" function logic [ 64:0] i_array_4_state_65(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:116:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 116 | import "DPI-C" function logic [127:0] i_array_4_state_128(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:119:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 119 | import "DPI-C" function array_4_state_1_t i_array_4_state_1_t(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:120:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 120 | import "DPI-C" function array_4_state_2_t i_array_4_state_2_t(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:121:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 121 | import "DPI-C" function array_4_state_8_t i_array_4_state_8_t(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:122:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 122 | import "DPI-C" function array_4_state_9_t i_array_4_state_9_t(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:123:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 123 | import "DPI-C" function array_4_state_16_t i_array_4_state_16_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:124:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 124 | import "DPI-C" function array_4_state_17_t i_array_4_state_17_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:125:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 125 | import "DPI-C" function array_4_state_32_t i_array_4_state_32_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:126:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 126 | import "DPI-C" function array_4_state_33_t i_array_4_state_33_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:127:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 127 | import "DPI-C" function array_4_state_64_t i_array_4_state_64_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:128:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 128 | import "DPI-C" function array_4_state_65_t i_array_4_state_65_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:129:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 129 | import "DPI-C" function array_4_state_128_t i_array_4_state_128_t(); | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:132:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 132 | import "DPI-C" function struct_4_state_1 i_struct_4_state_1(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:133:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 133 | import "DPI-C" function struct_4_state_2 i_struct_4_state_2(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:134:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 134 | import "DPI-C" function struct_4_state_8 i_struct_4_state_8(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:135:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 135 | import "DPI-C" function struct_4_state_9 i_struct_4_state_9(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:136:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 136 | import "DPI-C" function struct_4_state_16 i_struct_4_state_16(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:137:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 137 | import "DPI-C" function struct_4_state_17 i_struct_4_state_17(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:138:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 138 | import "DPI-C" function struct_4_state_32 i_struct_4_state_32(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:139:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 139 | import "DPI-C" function struct_4_state_33 i_struct_4_state_33(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:140:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 140 | import "DPI-C" function struct_4_state_64 i_struct_4_state_64(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:141:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 141 | import "DPI-C" function struct_4_state_65 i_struct_4_state_65(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:142:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 142 | import "DPI-C" function struct_4_state_128 i_struct_4_state_128(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:145:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 145 | import "DPI-C" function union_4_state_1 i_union_4_state_1(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:146:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 146 | import "DPI-C" function union_4_state_2 i_union_4_state_2(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:147:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 147 | import "DPI-C" function union_4_state_8 i_union_4_state_8(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:148:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 148 | import "DPI-C" function union_4_state_9 i_union_4_state_9(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:149:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 149 | import "DPI-C" function union_4_state_16 i_union_4_state_16(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:150:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 150 | import "DPI-C" function union_4_state_17 i_union_4_state_17(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:151:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 151 | import "DPI-C" function union_4_state_32 i_union_4_state_32(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:152:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 152 | import "DPI-C" function union_4_state_33 i_union_4_state_33(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:153:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 153 | import "DPI-C" function union_4_state_64 i_union_4_state_64(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:154:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 154 | import "DPI-C" function union_4_state_65 i_union_4_state_65(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:155:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 155 | import "DPI-C" function union_4_state_128 i_union_4_state_128(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:245:25: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 245 | function bit [ 32:0] e_array_2_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:246:25: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 246 | function bit [ 63:0] e_array_2_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:247:25: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 247 | function bit [ 64:0] e_array_2_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:248:25: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 248 | function bit [127:0] e_array_2_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:251:33: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 251 | function array_2_state_33_t e_array_2_state_33_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:252:33: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 252 | function array_2_state_64_t e_array_2_state_64_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:253:33: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 253 | function array_2_state_65_t e_array_2_state_65_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:254:33: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 254 | function array_2_state_128_t e_array_2_state_128_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:257:32: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 257 | function struct_2_state_33 e_struct_2_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:258:32: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 258 | function struct_2_state_64 e_struct_2_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:259:32: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 259 | function struct_2_state_65 e_struct_2_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:260:32: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 260 | function struct_2_state_128 e_struct_2_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:263:31: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 263 | function union_2_state_33 e_union_2_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:264:31: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 264 | function union_2_state_64 e_union_2_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:265:31: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 265 | function union_2_state_65 e_union_2_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:266:31: DPI function may not return a > 32 bits wide type other than basic types. ... Suggest make it an output argument instead? 266 | function union_2_state_128 e_union_2_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:269:21: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 269 | function integer e_integer(); return 0; endfunction | ^~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:272:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 272 | function logic [ 0:0] e_array_4_state_1(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:273:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 273 | function logic [ 1:0] e_array_4_state_2(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:274:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 274 | function logic [ 7:0] e_array_4_state_8(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:275:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 275 | function logic [ 8:0] e_array_4_state_9(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:276:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 276 | function logic [ 15:0] e_array_4_state_16(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:277:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 277 | function logic [ 16:0] e_array_4_state_17(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:278:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 278 | function logic [ 31:0] e_array_4_state_32(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:279:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 279 | function logic [ 32:0] e_array_4_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:280:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 280 | function logic [ 63:0] e_array_4_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:281:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 281 | function logic [ 64:0] e_array_4_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:282:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 282 | function logic [127:0] e_array_4_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:285:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 285 | function array_4_state_1_t e_array_4_state_1_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:286:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 286 | function array_4_state_2_t e_array_4_state_2_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:287:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 287 | function array_4_state_8_t e_array_4_state_8_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:288:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 288 | function array_4_state_9_t e_array_4_state_9_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:289:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 289 | function array_4_state_16_t e_array_4_state_16_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:290:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 290 | function array_4_state_17_t e_array_4_state_17_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:291:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 291 | function array_4_state_32_t e_array_4_state_32_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:292:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 292 | function array_4_state_33_t e_array_4_state_33_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:293:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 293 | function array_4_state_64_t e_array_4_state_64_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:294:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 294 | function array_4_state_65_t e_array_4_state_65_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:295:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 295 | function array_4_state_128_t e_array_4_state_128_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:298:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 298 | function struct_4_state_1 e_struct_4_state_1(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:299:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 299 | function struct_4_state_2 e_struct_4_state_2(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:300:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 300 | function struct_4_state_8 e_struct_4_state_8(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:301:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 301 | function struct_4_state_9 e_struct_4_state_9(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:302:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 302 | function struct_4_state_16 e_struct_4_state_16(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:303:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 303 | function struct_4_state_17 e_struct_4_state_17(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:304:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 304 | function struct_4_state_32 e_struct_4_state_32(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:305:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 305 | function struct_4_state_33 e_struct_4_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:306:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 306 | function struct_4_state_64 e_struct_4_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:307:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 307 | function struct_4_state_65 e_struct_4_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:308:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 308 | function struct_4_state_128 e_struct_4_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:311:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 311 | function union_4_state_1 e_union_4_state_1(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:312:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 312 | function union_4_state_2 e_union_4_state_2(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:313:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 313 | function union_4_state_8 e_union_4_state_8(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:314:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 314 | function union_4_state_9 e_union_4_state_9(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:315:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 315 | function union_4_state_16 e_union_4_state_16(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:316:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 316 | function union_4_state_17 e_union_4_state_17(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:317:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 317 | function union_4_state_32 e_union_4_state_32(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:318:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 318 | function union_4_state_33 e_union_4_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:319:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 319 | function union_4_state_64 e_union_4_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:320:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 320 | function union_4_state_65 e_union_4_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:321:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2017 35.5.5) 321 | function union_4_state_128 e_union_4_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_vams_basic.v0000664000177100017500000000205613702133370021313 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" module t (/*AUTOARG*/ // Inputs clk ); input clk; task check (integer line, real got, real expec); real delta; delta = got-expec; if (delta > 0.001) begin $display("Line%d: Got %g Exp %g\n", line, got, expec); $stop; end endtask wreal wr; assign wr = 1.1; sub sub (.*); initial begin check(`__LINE__, sqrt(2.0) , 1.414); check(`__LINE__, pow(2.0,2.0) , 4.0); check(`__LINE__, ln(2.0) , 0.693147); check(`__LINE__, log(2.0) , 0.30103); check(`__LINE__, floor(2.5) , 2.0); check(`__LINE__, exp(2.0) , 7.38906); check(`__LINE__, ceil(2.5) , 3.0); $write("*-* All Finished *-*\n"); $finish; end endmodule module sub ( input wreal wr ); initial begin if (wr != 1.1) $stop; end endmodule verilator-4.038/test_regress/t/t_dpi_string.v0000664000177100017500000000126313702133370021345 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); import "DPI-C" function int dpii_string(input string DSM_NAME); generate begin : DSM string SOME_STRING; end endgenerate initial begin $sformat(DSM.SOME_STRING, "%m"); if (dpii_string(DSM.SOME_STRING) != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_func_dotted_inl1.pl0000775000177100017500000000156213702133370022577 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_func_dotted.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( v_flags2 => ['+define+ATTRIBUTES', '+define+USE_INLINE',], ); if ($Self->{vlt_all}) { file_grep_not("$out_filename", qr/ma0/i); file_grep_not("$out_filename", qr/mb0/i); file_grep_not("$out_filename", qr/mc0/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_c_api.v0000664000177100017500000000035213702133370021432 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-4.038/test_regress/t/t_class_virtual.v0000664000177100017500000000036113702133367022062 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 virtual class VC; endclass verilator-4.038/test_regress/t/t_vpi_module.cpp0000664000177100017500000001051713702133370021665 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "Vt_vpi_module.h" #include "verilated.h" #include "svdpi.h" #include "Vt_vpi_module__Dpi.h" #include "verilated_vpi.h" #include "verilated_vcd_c.h" #endif #include #include #include #include "TestSimulator.h" #include "TestVpi.h" // __FILE__ is too long #define FILENM "t_vpi_module.cpp" #define DEBUG \ if (0) printf unsigned int main_time = 0; #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ (got) ? (got) : "", (exp) ? (exp) : ""); \ return __LINE__; \ } extern "C" { int mon_check() { vpiHandle it = vpi_iterate(vpiModule, NULL); CHECK_RESULT_NZ(it); vpiHandle topmod = vpi_scan(it); CHECK_RESULT_NZ(topmod); char* name = vpi_get_str(vpiName, topmod); CHECK_RESULT_NZ(name); CHECK_RESULT_CSTR(name, "t"); it = vpi_iterate(vpiModule, topmod); CHECK_RESULT_NZ(it); vpiHandle mod = vpi_scan(it); CHECK_RESULT_NZ(mod); name = vpi_get_str(vpiName, mod); CHECK_RESULT_CSTR(name, "mod_a"); it = vpi_iterate(vpiModule, mod); CHECK_RESULT_NZ(it); mod = vpi_scan(it); CHECK_RESULT_NZ(mod); name = vpi_get_str(vpiName, mod); if (strcmp(name, "mod_b") == 0) { // Full visibility in other simulators, skip mod_b mod = vpi_scan(it); CHECK_RESULT_NZ(mod); name = vpi_get_str(vpiName, mod); } CHECK_RESULT_CSTR(name, "mod_c."); return 0; // Ok } } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { vpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); // we're going to be checking for these errors do don't crash out Verilated::fatalOnVpiError(0); VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out #ifdef VERILATOR #ifdef TEST_VERBOSE Verilated::scopesDump(); #endif #endif #if VM_TRACE Verilated::traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; main_time += 10; while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += 1; topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } if (!Verilated::gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete topp, topp); exit(0L); } #endif verilator-4.038/test_regress/t/t_queue.v0000664000177100017500000001537213702133370020335 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; integer i; typedef integer q_t[$]; initial begin q_t iq; iq.push_back(42); end always @ (posedge clk) begin cyc <= cyc + 1; begin // Very simple test using bit bit q[$]; bit x; `checkh($left(q), 0); `checkh($right(q), -1); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), -1); `checkh($size(q), 0); `checkh($dimensions(q), 1); // Unsup: `checkh($bits(q), 0); q.push_back(1'b1); `checkh($left(q), 0); `checkh($right(q), 0); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), 0); `checkh($size(q), 1); `checkh($dimensions(q), 1); // Unsup: `checkh($bits(q), 2); `checkh(q.size(), 1); q.push_back(1'b1); q.push_back(1'b0); q.push_back(1'b1); `checkh($left(q), 0); `checkh($right(q), 3); `checkh($low(q), 0); `checkh($high(q), 3); `checkh($size(q), 4); // Unsup: `checkh($bits(q), 4); `checkh(q.size(), 4); x = q.pop_back(); `checkh(x, 1'b1); `checkh($left(q), 0); `checkh($right(q), 2); `checkh($low(q), 0); `checkh($high(q), 2); `checkh($size(q), 3); // sure those are working now.. x = q.pop_front(); `checkh(x, 1'b1); x = q.pop_front(); `checkh(x, 1'b1); x = q.pop_front(); `checkh(x, 1'b0); `checkh(q.size(), 0); end begin // Simple test using integer typedef bit [3:0] nibble_t; nibble_t q[$]; nibble_t v; `checkh($left(q), 0); `checkh($right(q), -1); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), -1); `checkh($size(q), 0); `checkh($dimensions(q), 2); i = q.size(); `checkh(i, 0); q.push_back(4'd1); // 1 q.push_front(4'd2); // 2 1 q.push_back(4'd3); // 2 1 3 i = q.size; `checkh(i, 3); // Also checks no parens end begin // Strings string q[$]; string v; int j = 0; // Empty queue checks `checkh($left(q), 0); `checkh($right(q), -1); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), -1); `checkh($size(q), 0); `checkh($dimensions(q), 2); //Unsup: `checkh($bits(q), 0); q.push_front("f1"); //Unsup: `checkh($bits(q), 16); q.push_back("b1"); q.push_front("f2"); q.push_back("b2"); i = q.size(); `checkh(i, 4); v = q[0]; `checks(v, "f2"); v = q[1]; `checks(v, "f1"); v = q[2]; `checks(v, "b1"); v = q[3]; `checks(v, "b2"); v = q[4]; `checks(v, ""); //Unsup: `checkh(q[$], "b2"); v = $sformatf("%p", q); `checks(v, "'{\"f2\", \"f1\", \"b1\", \"b2\"} "); //Unsup: q.delete(1); //Unsup: v = q[1]; `checks(v, "b1"); //Unsup: q.insert(0, "ins0"); //Unsup: q.insert(3, "ins3"); //v = q[0]; `checks(v, "ins0"); //v = q[3]; `checks(v, "ins3"); foreach (q[i]) begin j++; v = q[i]; if (i == 0) `checks(v, "f2"); if (i == 1) `checks(v, "f1"); if (i == 2) `checks(v, "b1"); if (i == 3) `checks(v, "b2"); end `checkh(j,4); q.pop_front(); v = q.pop_front(); `checks(v, "f1"); v = q.pop_back(); `checks(v, "b2"); v = q.pop_back(); `checks(v, "b1"); i = q.size(); `checkh(i, 0); // Empty queue, this should be 0 foreach (q[i]) begin j++; end `checkh(j,4); q.push_front("non-empty"); i = q.size(); `checkh(i, 1); q.delete(); i = q.size(); `checkh(i, 0); v = q.pop_front(); `checks(v, ""); // Was empty, optional warning v = q.pop_back(); `checks(v, ""); // Was empty, optional warning // Conversion of insert/delete with zero to operator q.push_front("front"); q.insert(0, "newfront"); i = q.size(); `checkh(i, 2); q.delete(0); i = q.size(); `checkh(i, 1); `checks(q[0], "front"); //Unsup: `checks(q[$], "front"); end begin typedef struct packed { bit [7:0] opcode; bit [23:0] addr; } instruction; // named structure type instruction q[$]; `checkh($dimensions(q), 2); //Unsup: `checkh($bits(q), 0); end // testing a wide queue begin typedef struct packed { bit [7:0] opcode; bit [23:0] addr; bit [127:0] data; } instructionW; // named structure type instructionW inst_push; instructionW inst_pop; instructionW q[$]; `checkh($dimensions(q), 2); `checkh(q[0].opcode, 0); `checkh(q[0].addr, 0); `checkh(q[0].data, 0); inst_push.opcode = 1; inst_push.addr = 42; inst_push.data = {4{32'hdeadbeef}}; q.push_back(inst_push); `checkh(q[0].opcode, 1); `checkh(q[0].addr, 42); `checkh(q[0].data, {4{32'hdeadbeef}}); inst_pop = q.pop_front(); `checkh(inst_pop.opcode, 1); `checkh(inst_pop.addr, 42); `checkh(inst_pop.data, {4{32'hdeadbeef}}); `checkh(q.size(), 0); `checkh(q[0].opcode, 0); `checkh(q[0].addr, 0); `checkh(q[0].data, 0); end /* Unsup: begin int q[4][$]; q[0].push_back(0); q[0].push_back(1); q[1].push_back(2); q[2].push_back(3); end */ // See t_queue_unsup_bad for more unsupported stuff $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_avec.out0000664000177100017500000000044513702133370021644 0ustar wsnyderwsnyder%Error: t/t_param_avec.v:34:43: Expecting expression to be constant, but variable isn't const: 'array' : ... In instance t.i0 34 | localparam elementf = get_element(IDX, array); | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_tri_gate_bufif1.pl0000775000177100017500000000127413702133370022410 0ustar wsnyderwsnyder#!/usr/bin/env perl # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_tri_gate.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ['+define+T_BUFIF1',], make_flags => 'CPPFLAGS_ADD=-DT_BUFIF1', verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_detectarray_3.pl0000775000177100017500000000114113702133370022100 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-Wno-UNOPTFLAT -Wno-WIDTH"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_order_2d.v0000664000177100017500000000400413702133370020677 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire input_signal = crc[0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire output_signal; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .output_signal (output_signal), // Inputs .input_signal (input_signal)); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, output_signal}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h765b2e12b25ec97b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input input_signal, output output_signal ); // bug872 // verilator lint_off UNOPTFLAT wire some_signal[1:0][1:0]; assign some_signal[0][0] = input_signal; assign some_signal[0][1] = some_signal[0][0]; assign some_signal[1][0] = some_signal[0][1]; assign some_signal[1][1] = some_signal[1][0]; assign output_signal = some_signal[1][1]; endmodule verilator-4.038/test_regress/t/t_repeat.pl0000775000177100017500000000105313702133370020631 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_slice_conc_bad.pl0000775000177100017500000000101313702133370023112 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_port_sc.out0000664000177100017500000000261013702133370023262 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sun Mar 1 21:32:22 2020 $end $timescale 1ps $end $scope module topa $end $scope module t $end $var wire 32 3 c_trace_on [31:0] $end $var wire 1 # clk $end $var wire 32 + cyc [31:0] $end $scope module sub $end $var wire 32 ; inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 + b00000000000000000000000000000000 3 b00000000000000000000000000000001 ; #10000 1# b00000000000000000000000000000010 + b00000000000000000000000000000011 3 #15000 0# #20000 1# b00000000000000000000000000000011 + b00000000000000000000000000000100 3 #25000 0# #30000 1# b00000000000000000000000000000100 + b00000000000000000000000000000101 3 #35000 0# #40000 1# b00000000000000000000000000000101 + b00000000000000000000000000000110 3 #45000 0# #50000 1# b00000000000000000000000000000110 + b00000000000000000000000000000111 3 #55000 0# #60000 1# b00000000000000000000000000000111 + b00000000000000000000000000001000 3 #65000 0# #70000 1# b00000000000000000000000000001000 + b00000000000000000000000000001001 3 #75000 0# #80000 1# b00000000000000000000000000001001 + b00000000000000000000000000001010 3 #85000 0# #90000 1# b00000000000000000000000000001010 + b00000000000000000000000000001011 3 #95000 0# #100000 1# b00000000000000000000000000001011 + b00000000000000000000000000001100 3 verilator-4.038/test_regress/t/t_case_zx_bad.v0000664000177100017500000000070013702133367021446 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [3:0] value; always @ (/*AS*/value) begin casez (value) 4'b0000: $stop; 4'b1xxx: $stop; default: $stop; endcase end endmodule verilator-4.038/test_regress/t/t_param_first.pl0000775000177100017500000000105313702133370021660 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_in_inc_bad_1.vh0000664000177100017500000000037013702133370022664 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_lint_in_inc_bad_2.vh" verilator-4.038/test_regress/t/t_interface_ref_trace_inlab.pl0000775000177100017500000000152713702133370024476 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_ref_trace.v"); $Self->{golden_filename} = "t/t_interface_ref_trace.out"; compile( v_flags2 => ['+define+NO_INLINE_A +define+NO_INLINE_B'], verilator_flags2 => ['--trace-structs --trace'], ); execute( check_finished => 1, ); vcd_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_func.v0000664000177100017500000000661613702133370020145 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [2:0] value; reg [31:0] rglobal; reg [31:0] vec [1:0]; reg [31:0] n; initial begin rglobal = 1; value = 2; if (add(value) != 3'd3) $stop; if (rglobal != 2) $stop; if (add(add(3'd1)) != 3'd3) $stop; if (rglobal != 4) $stop; if (munge4(4'b0010) != 4'b1011) $stop; if (toint(2) != 3) $stop; if (rglobal != 5) $stop; setit; incr(rglobal,rglobal,32'h10); if (rglobal != 32'h17) $stop; nop(32'h11); empty; empty(); rglobal = 32'h00000001; flipupperbit(rglobal,4'd4); flipupperbit(rglobal,4'd12); if (rglobal !== 32'h10100001) $stop; if (nil_func(32'h12,32'h12) != 32'h24) $stop; nil_task(32'h012,32'h112,rglobal); if (rglobal !== 32'h124) $stop; vec[0] = 32'h333; vec[1] = 32'habc; incr(vec[1],vec[0],vec[1]); if (vec[0] != 32'h333) $stop; if (vec[1] != 32'hdef) $stop; // verilator lint_off SELRANGE incr(vec[2],vec[0],vec[2]); // Reading/Writing past end of vector! // verilator lint_on SELRANGE n=1; nil(); if (n !== 10) $stop; // Functions called as tasks // verilator lint_off IGNOREDRETURN rglobal = 32'h4; if (inc_and_return(32'h2) != 32'h6) $stop; if (rglobal !== 32'h6) $stop; rglobal = 32'h6; inc_and_return(32'h3); if (rglobal !== 32'h9) $stop; // verilator lint_on IGNOREDRETURN $write("*-* All Finished *-*\n"); $finish; end function [2:0] add; input [2:0] fromv; begin add = fromv + 3'd1; begin : named reg [31:0] flocal; flocal = 1; rglobal = rglobal + flocal; end : named // SystemVerilog end labels end endfunction function [3:0] munge4; input [3:0] fromv; // Different fromv than the 'fromv' signal above reg one; begin : named reg [1:0] flocal; // Function calling a function one = 1'b1; munge4 = {one, add(fromv[2:0])}; end endfunction task setit; reg [31:0] temp; begin temp = rglobal + 32'h1; rglobal = temp + 32'h1; end endtask task incr ( // Check a V2K style input/output list output [31:0] z, input [31:0] a, inc ); z = a + inc; endtask task nop; input [31:0] a; begin end endtask task empty; endtask task flipupperbit; inout [31:0] vector; input [3:0] bitnum; reg [4:0] bitnum2; begin bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation vector[bitnum2] = vector[bitnum2] ^ 1'b1; end endtask task nil_task; input [31:0] a; input [31:0] b; output [31:0] q; // verilator no_inline_task q = nil_func(a, b); endtask function void nil; n = 10; endfunction function [31:0] nil_func; input [31:0] fa; input [31:0] fb; // verilator no_inline_task nil_func = fa + fb; endfunction function integer toint; input integer fa; toint = fa + 32'h1; endfunction function [31:0] inc_and_return; input [31:0] inc; rglobal = rglobal + inc; return rglobal; endfunction endmodule verilator-4.038/test_regress/t/t_bitsel_enum.v0000664000177100017500000000133213702133367021514 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 module t_bitsel_enum ( output out0, output out1 ); localparam [6:0] CNST_VAL = 7'h22; enum logic [6:0] { ENUM_VAL = 7'h33 } MyEnum; assign out0 = CNST_VAL[0]; // Not supported by NC-verilog nor VCS, but other simulators do assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_escape.out0000664000177100017500000000412213702133370021652 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Tue Jul 24 18:44:43 2012 $end $timescale 1ps $end $scope module top $end $var wire 1 * 9num $end $var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end $var wire 1 ' clk $end $var wire 1 ) double__underscore $end $var wire 1 ( escaped_normal $end $scope module t $end $var wire 1 * 9num $end $var wire 32 & a0.cyc [31:0] $end $var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end $var wire 1 $ check:alias $end $var wire 1 % check;alias $end $var wire 1 $ check_alias $end $var wire 1 ' clk $end $var wire 32 # cyc [31:0] $end $var wire 1 ) double__underscore $end $var wire 1 ( escaped_normal $end $var wire 32 & other.cyc [31:0] $end $var wire 1 $ wire $end $scope module a0 $end $var wire 32 # cyc [31:0] $end $upscope $end $scope module mod.with_dot $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1$ 0% b11111111111111111111111111111110 & b00000000000000000000000000000001 # 0' 1( 1) 1* 1+ #10 0$ 1% b11111111111111111111111111111101 & b00000000000000000000000000000010 # 1' 0( 0) 0* 0+ #15 0' #20 1$ 0% b11111111111111111111111111111100 & b00000000000000000000000000000011 # 1' 1( 1) 1* 1+ #25 0' #30 0$ 1% b11111111111111111111111111111011 & b00000000000000000000000000000100 # 1' 0( 0) 0* 0+ #35 0' #40 1$ 0% b11111111111111111111111111111010 & b00000000000000000000000000000101 # 1' 1( 1) 1* 1+ #45 0' #50 0$ 1% b11111111111111111111111111111001 & b00000000000000000000000000000110 # 1' 0( 0) 0* 0+ #55 0' #60 1$ 0% b11111111111111111111111111111000 & b00000000000000000000000000000111 # 1' 1( 1) 1* 1+ #65 0' #70 0$ 1% b11111111111111111111111111110111 & b00000000000000000000000000001000 # 1' 0( 0) 0* 0+ #75 0' #80 1$ 0% b11111111111111111111111111110110 & b00000000000000000000000000001001 # 1' 1( 1) 1* 1+ #85 0' #90 0$ 1% b11111111111111111111111111110101 & b00000000000000000000000000001010 # 1' 0( 0) 0* 0+ #95 0' #100 1$ 0% b11111111111111111111111111110100 & b00000000000000000000000000001011 # 1' 1( 1) 1* 1+ verilator-4.038/test_regress/t/t_math_equal.pl0000775000177100017500000000105313702133370021471 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_paramed.pl0000775000177100017500000000105313702133370021775 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_package.pl0000775000177100017500000000105313702133370022124 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_signed.pl0000775000177100017500000000113413702133370022347 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_pins_sc2.pl0000775000177100017500000000473613702133370021754 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_var_pinsizes.v"); compile( verilator_flags2 => ["-sc -pins-bv 2 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], make_main => 0, ); { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16_vlt;/x); } execute(); ok(1); 1; verilator-4.038/test_regress/t/t_array_pattern_unpacked.pl0000775000177100017500000000105313702133367024104 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_array2.pl0000775000177100017500000000105313702133370021731 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_dotted_inl2.pl0000775000177100017500000000167513702133370022605 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_func_dotted.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( v_flags2 => ['+define+ATTRIBUTES', '+define+USE_INLINE_MID',], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_file_scan.pl0000775000177100017500000000125613702133370022177 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); unlink("$Self->{obj_dir}/t_sys_file_scan_test.log"); compile( ); execute( check_finished => 1, ); file_grep("$Self->{obj_dir}/t_sys_file_scan_test.log", "# a 1 "); ok(1); 1; verilator-4.038/test_regress/t/t_time_vpi_10ms10ns.out0000664000177100017500000000126313702133370022723 0ustar wsnyderwsnyder:: In top.t Time scale of t is 10ms / 10ns [60000000] time%0d=60 123%0t=123000000 dig%0t=543000000 dig%0d=543 rdig%0t=543210987 rdig%0f=543.210988 [600000000.000000ns] time%0d=60 123%0t=1230000000.000000ns dig%0t=5430000000.000000ns dig%0d=543 rdig%0t=5432109876.543210ns rdig%0f=543.210988 [600000000.000000ns] stime%0t=600000000.000000ns stime%0d=60 stime%0f=60.000000 [600000000.000000ns] rtime%0t=600000000.000000ns rtime%0d=60 rtime%0f=60.000000 global vpiSimTime = 0,60000000 vpiScaledRealTime = 6e+07 global vpiTimeUnit = -2 vpiTimePrecision = -8 top.t vpiSimTime = 0,60000000 vpiScaledRealTime = 60 top.t vpiTimeUnit = -2 vpiTimePrecision = -8 *-* All Finished *-* verilator-4.038/test_regress/t/t_timing_clkgen.v0000664000177100017500000000163513702133370022020 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module clkgen(output bit clk); initial begin #(8.0:5:3) clk = 1; // Middle is default forever begin #5 clk = ~clk; end end endmodule module t(/*AUTOARG*/); wire logic clk; clkgen clkgen (.clk); int cyc; always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $display("[%0t] cyc=%0d", $time, cyc); `endif if (cyc == 0) begin if ($time != 5) $stop; end else if (cyc == 1) begin if ($time != 15) $stop; end else if (cyc == 2) begin if ($time != 25) $stop; end else if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_trace_complex_fst.pl0000775000177100017500000000130513702133370023052 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_complex.v"); compile( verilator_flags2 => ['--cc --trace-fst'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_math_signed3.pl0000775000177100017500000000105313702133370021716 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_width.v0000664000177100017500000000250513702133370021333 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); // See also t_lint_width parameter A_ONE = '1; // verilator lint_off WIDTH parameter [3:0] A_W4 = A_ONE; // verilator lint_on WIDTH initial begin if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop; if ($bits(A_W4) != 4) $stop; if (A_W4 != 4'b0001) $stop; end b #(.B_WIDTH(48)) b (); reg [4:0] c; integer c_i; initial begin c_i = 3; c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax if (c != 5'b1000) $stop; end localparam D_TT = 32'd23; localparam D_SIX = 6; // verilator lint_off WIDTH localparam [5:0] D_SUB = D_TT - D_SIX; // verilator lint_on WIDTH initial begin if (D_SUB != 17) $stop; end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module b; parameter B_WIDTH = 1; localparam B_VALUE0 = {B_WIDTH{1'b0}}; localparam B_VALUE1 = {B_WIDTH{1'b1}}; reg [47:0] b_val; initial begin b_val = B_VALUE0; if (b_val != 48'b0) $stop; b_val = B_VALUE1; if (b_val != ~48'b0) $stop; end endmodule verilator-4.038/test_regress/t/t_lint_unused_iface_bad.pl0000775000177100017500000000117513702133370023644 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_file.v0000664000177100017500000001145213702133370020761 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; reg [63:0] sum; wire r1_en /*verilator public*/ = crc[12]; wire [1:0] r1_ad /*verilator public*/ = crc[9:8]; wire r2_en /*verilator public*/ = 1'b1; wire [1:0] r2_ad /*verilator public*/ = crc[11:10]; wire w1_en /*verilator public*/ = crc[5]; wire [1:0] w1_a /*verilator public*/ = crc[1:0]; wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}}; wire w2_en /*verilator public*/ = crc[4]; wire [1:0] w2_a /*verilator public*/ = crc[3:2]; wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [63:0] r1_d_d2r; // From file of file.v wire [63:0] r2_d_d2r; // From file of file.v // End of automatics file file (/*AUTOINST*/ // Outputs .r1_d_d2r (r1_d_d2r[63:0]), .r2_d_d2r (r2_d_d2r[63:0]), // Inputs .clk (clk), .r1_en (r1_en), .r1_ad (r1_ad[1:0]), .r2_en (r2_en), .r2_ad (r2_ad[1:0]), .w1_en (w1_en), .w1_a (w1_a[1:0]), .w1_d (w1_d[63:0]), .w2_en (w2_en), .w2_a (w2_a[1:0]), .w2_d (w2_d[63:0])); always @ (posedge clk) begin //$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n",$time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r); cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin // We've manually verified all X's are out of the design by this point sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== 64'h5e9ea8c33a97f81e) $stop; $finish; end end endmodule module file (/*AUTOARG*/ // Outputs r1_d_d2r, r2_d_d2r, // Inputs clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d ); input clk; input r1_en; input [1:0] r1_ad; output [63:0] r1_d_d2r; input r2_en; input [1:0] r2_ad; output [63:0] r2_d_d2r; input w1_en; input [1:0] w1_a; input [63:0] w1_d; input w2_en; input [1:0] w2_a; input [63:0] w2_d; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) // End of automatics /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [63:0] r1_d_d2r; reg [63:0] r2_d_d2r; // End of automatics // Writes wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a)); wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a)); wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d; wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d; wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d; wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d; wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe; // Storage reg [63:0] m_rg0_r; reg [63:0] m_rg1_r; reg [63:0] m_rg2_r; reg [63:0] m_rg3_r; always @ (posedge clk) begin if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat; if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat; if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat; if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat; end // Reads reg [1:0] m_r1_ad_d1r; reg [1:0] m_r2_ad_d1r; reg [1:0] m_ren_d1r; always @ (posedge clk) begin if (r1_en) m_r1_ad_d1r <= r1_ad; if (r2_en) m_r2_ad_d1r <= r2_ad; m_ren_d1r <= {r2_en, r1_en}; end // Scheme1: shift... wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r); // Scheme2: bit mask reg [3:0] m_r2_onehot_d1; always @* begin m_r2_onehot_d1 = 4'd0; m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1; end wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) | ({64{m_r1_onehot_d1[1]}} & m_rg1_r) | ({64{m_r1_onehot_d1[2]}} & m_rg2_r) | ({64{m_r1_onehot_d1[3]}} & m_rg3_r)); wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) | ({64{m_r2_onehot_d1[1]}} & m_rg1_r) | ({64{m_r2_onehot_d1[2]}} & m_rg2_r) | ({64{m_r2_onehot_d1[3]}} & m_rg3_r)); always @ (posedge clk) begin if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1; if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1; end endmodule verilator-4.038/test_regress/t/t_param_width_loc_bad.v0000664000177100017500000000070413702133370023144 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; test #(.param(32'd0)) test_i; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module test #( parameter logic param = 1'b0 ) (); endmodule verilator-4.038/test_regress/t/t_dynarray_bad.pl0000775000177100017500000000107413702133370022013 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_longname.v0000664000177100017500000000346413702133370021647 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // The code as shown makes a really big file name with Verilator. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 `define LONG_NAME_MOD modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie `define LONG_NAME_SUB sublongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie `define LONG_NAME_VAR varlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie module t (); initial begin $write("*-* All Finished *-*\n"); $finish; end logic `LONG_NAME_VAR; `LONG_NAME_MOD `LONG_NAME_SUB (); endmodule module `LONG_NAME_MOD (); // Force Verilator to make a new class logic a1 /* verilator public */; endmodule verilator-4.038/test_regress/t/t_inst_aport.v0000664000177100017500000000502613702133370021366 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [15:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[15:0]), // Inputs .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module callee (input [7:0] port [7:0], output [7:0] o); assign o = ^{port[0], port[1], port[2], port[3], port[4], port[5], port[6], port[7]}; endmodule // callee module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [31:0] in; output reg [15:0] out; wire [7:0] port [15:0]; wire [7:0] goodport [7:0]; always_comb begin port[0][7:0] = in[7:0]; port[1][7:0] = in[16:8]; port[2] = '0; port[3] = '0; port[4] = '0; port[5] = '0; port[6] = '0; port[7] = '0; end always_comb begin goodport[0][7:0] = in[7:0]; goodport[1][7:0] = in[16:8]; goodport[2] = '0; goodport[3] = '0; goodport[4] = '0; goodport[5] = '0; goodport[6] = '0; goodport[7] = '0; end callee good (.port(goodport), .o(out[7:0])); // This is a slice, unsupported by other tools, bug711 callee bad (.port(port[7:0]), .o(out[15:8])); endmodule verilator-4.038/test_regress/t/t_func_dotted_inl1_vlt.pl0000775000177100017500000000154213702133370023462 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_func_dotted.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( v_flags2 => ["t/t_func_dotted_inl1.vlt",], ); if ($Self->{vlt_all}) { file_grep_not("$out_filename", qr/ma0/i); file_grep_not("$out_filename", qr/mb0/i); file_grep_not("$out_filename", qr/mc0/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_types.v0000664000177100017500000000407713702133370021370 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function int int123(); int123 = 32'h123; endfunction function bit f_bit ; input bit i; f_bit = ~i; endfunction function int f_int ; input int i; f_int = ~i; endfunction function byte f_byte ; input byte i; f_byte = ~i; endfunction function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction function longint f_longint ; input longint i; f_longint = ~i; endfunction function chandle f_chandle ; input chandle i; f_chandle = i; endfunction // Note there's no "input" here vvvv, it's the default function bit g_bit (bit i); g_bit = ~i; endfunction function int g_int (int i); g_int = ~i; endfunction function byte g_byte (byte i); g_byte = ~i; endfunction function shortint g_shortint(shortint i); g_shortint = ~i; endfunction function longint g_longint (longint i); g_longint = ~i; endfunction function chandle g_chandle (chandle i); g_chandle = i; endfunction chandle c; initial begin if (int123() !== 32'h123) $stop; if (f_bit(1'h1) !== 1'h0) $stop; if (f_bit(1'h0) !== 1'h1) $stop; if (f_int(32'h1) !== 32'hfffffffe) $stop; if (f_byte(8'h1) !== 8'hfe) $stop; if (f_shortint(16'h1) !== 16'hfffe) $stop; if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (f_chandle(c) !== c) $stop; if (g_bit(1'h1) !== 1'h0) $stop; if (g_bit(1'h0) !== 1'h1) $stop; if (g_int(32'h1) !== 32'hfffffffe) $stop; if (g_byte(8'h1) !== 8'hfe) $stop; if (g_shortint(16'h1) !== 16'hfffe) $stop; if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (g_chandle(c) !== c) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_multidriven_bad.v0000664000177100017500000000136713702133370023406 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs out, out2, // Inputs clk, a0, d0, d1 ); input clk; input [1:0] a0; input [7:0] d0; input [7:0] d1; output reg [31:0] out; output reg [15:0] out2; reg [7:0] mem [4]; always @(posedge clk) begin mem[a0] <= d0; end always @(negedge clk) begin mem[a0] <= d1; end assign out = {mem[3],mem[2],mem[1],mem[0]}; always @(posedge clk) begin out2[7:0] <= d0; end always @(negedge clk) begin out2[15:8] <= d0; end endmodule verilator-4.038/test_regress/t/t_func_check.pl0000775000177100017500000000111613702133370021441 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{verilated_randReset} = 1; compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_file_basic_mcd_test2_1.dat0000664000177100017500000000020213702133370024640 0ustar wsnyderwsnyderScotland is the greatest country. All other countries are inferior. Woe betide those to stand against the mighty Scottish nation. verilator-4.038/test_regress/t/t_package_export_bad.out0000664000177100017500000000305213702133370023345 0ustar wsnyderwsnyder%Error: t/t_package_export.v:45:17: Export object not found: 'pkg1::BAD_DOES_NOT_EXIST' 45 | export pkg1::BAD_DOES_NOT_EXIST; | ^~~~~~~~~~~~~~~~~~ %Error: t/t_package_export.v:60:16: Can't find definition of scope/variable: 'PARAM2' : ... Suggested alternative: 'PARAM1' 60 | reg [pkg11::PARAM2 : 0] bus12; | ^~~~~~ %Error: t/t_package_export.v:61:16: Can't find definition of scope/variable: 'PARAM3' : ... Suggested alternative: 'PARAM1' 61 | reg [pkg11::PARAM3 : 0] bus13; | ^~~~~~ %Error: t/t_package_export.v:64:16: Can't find definition of scope/variable: 'PARAM2' : ... Suggested alternative: 'PARAM1' 64 | reg [pkg21::PARAM2 : 0] bus22; | ^~~~~~ %Error: t/t_package_export.v:65:16: Can't find definition of scope/variable: 'PARAM3' : ... Suggested alternative: 'PARAM1' 65 | reg [pkg21::PARAM3 : 0] bus23; | ^~~~~~ %Error: t/t_package_export.v:68:16: Can't find definition of scope/variable: 'PARAM2' : ... Suggested alternative: 'PARAM1' 68 | reg [pkg31::PARAM2 : 0] bus32; | ^~~~~~ %Error: t/t_package_export.v:69:16: Can't find definition of scope/variable: 'PARAM3' : ... Suggested alternative: 'PARAM1' 69 | reg [pkg31::PARAM3 : 0] bus33; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_pipe_filter_inc.vh0000664000177100017500000000050213702133370022501 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 inc line 6; inc line 7; // example_lint_off_line FOO inc line 8; // example_lint_off_line BAR inc line 9; verilator-4.038/test_regress/t/t_class_name.pl0000775000177100017500000000117613702133367021472 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_public_func_vlt.pl0000775000177100017500000000151713702133370023712 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_trace_public.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["-DPUB_FUNC --trace --exe $Self->{t_dir}/t_trace_public_func.cpp $Self->{t_dir}/t_trace_public_func.vlt"], ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", "t/t_trace_public.out"); ok(1); 1; verilator-4.038/test_regress/t/t_fuzz_negwidth_bad.v0000664000177100017500000000042513702133370022677 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 int a = -12'd1; int b = 65536'd1; int c = 1231232312312312'd1; verilator-4.038/test_regress/t/t_unoptflat_simple.v0000664000177100017500000000116113702133370022565 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Simple test of unoptflat // // Simple demonstration of an UNOPTFLAT combinatorial loop, using just 2 bits. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [1:0] x = { x[0], clk }; initial begin x = 0; end always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("x = %x\n", x); `endif if (x[1] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_assert_basic_cover.pl0000775000177100017500000000164013702133367023221 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_basic.v"); compile( verilator_flags2 => ['--assert --cc --coverage-user'], ); execute( check_finished => 1, ); #Needs work print "-Info: NOT checking for coverage\n"; #file_grep($Self->{coverage_filename}, qr/t=>'psl_cover',o=>'cover',c=>2\);/); #file_grep($Self->{coverage_filename}, qr/DefaultClock.*,c=>1\);/); #file_grep($Self->{coverage_filename}, qr/ToggleLogIf.*,c=>9\);/); ok(1); 1; verilator-4.038/test_regress/t/t_clk_condflop.v0000664000177100017500000000472713702133367021656 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [0:0] d1; reg [2:0] d3; reg [7:0] d8; wire [0:0] q1; wire [2:0] q3; wire [7:0] q8; // verilator lint_off UNOPTFLAT reg ena; // verilator lint_on UNOPTFLAT condff #(12) condff (.clk(clk), .sen(1'b0), .ena(ena), .d({d8,d3,d1}), .q({q8,q3,q1})); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin //$write("%x %x %x %x\n", cyc, q8, q3, q1); cyc <= cyc + 1; if (cyc==1) begin d1 <= 1'b1; d3<=3'h1; d8<=8'h11; ena <= 1'b1; end if (cyc==2) begin d1 <= 1'b0; d3<=3'h2; d8<=8'h33; ena <= 1'b0; end if (cyc==3) begin d1 <= 1'b1; d3<=3'h3; d8<=8'h44; ena <= 1'b1; if (q8 != 8'h11) $stop; end if (cyc==4) begin d1 <= 1'b1; d3<=3'h4; d8<=8'h77; ena <= 1'b1; if (q8 != 8'h11) $stop; end if (cyc==5) begin d1 <= 1'b1; d3<=3'h0; d8<=8'h88; ena <= 1'b1; if (q8 != 8'h44) $stop; end if (cyc==6) begin if (q8 != 8'h77) $stop; end if (cyc==7) begin if (q8 != 8'h88) $stop; end // if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module condff (clk, sen, ena, d, q); parameter WIDTH = 1; input clk; input sen; input ena; input [WIDTH-1:0] d; output [WIDTH-1:0] q; condffimp #(.WIDTH(WIDTH)) imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q)); endmodule module condffimp (clk, sen, ena, d, q); parameter WIDTH = 1; input clk; input sen; input ena; input [WIDTH-1:0] d; output reg [WIDTH-1:0] q; wire gatedclk; clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk)); always @(posedge gatedclk) begin if (gatedclk === 1'bX) begin q <= {WIDTH{1'bX}}; end else begin q <= d; end end endmodule module clockgate (clk, sen, ena, gatedclk); input clk; input sen; input ena; output gatedclk; reg ena_b; wire gatedclk = clk & ena_b; // verilator lint_off COMBDLY always @(clk or ena or sen) begin if (~clk) begin ena_b <= ena | sen; end else begin if ((clk^sen)===1'bX) ena_b <= 1'bX; end end // verilator lint_on COMBDLY endmodule verilator-4.038/test_regress/t/t_order_quad.cpp0000664000177100017500000000213313702133370021642 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include "Vt_order_quad.h" //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = NULL; bool fail = false; void check(QData got, QData exp) { if (got != exp) { VL_PRINTF("%%Error: got=0x%" VL_PRI64 "x exp=0x%" VL_PRI64 "x\n", got, exp); fail = true; } } int main(int argc, char* argv[]) { topp = new VM_PREFIX; Verilated::debug(0); topp->a0 = 0; topp->eval(); check(topp->y, 0x0ULL); topp->a0 = 15; topp->eval(); check(topp->y, 0x3c00000000ULL); topp->final(); if (!fail) { VL_PRINTF("*-* All Finished *-*\n"); topp->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results\n"); } return 0; } verilator-4.038/test_regress/t/t_sys_plusargs_bad.v0000664000177100017500000000110413702133370022541 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer p_i; initial begin // BAD: Missing argument if ($value$plusargs("NOTTHERE", p_i)!==0) $stop; // BAD: Bad letter if ($value$plusargs("INT=%z", p_i)!==0) $stop; // BAD: Multi letter if ($value$plusargs("INT=%x%x", p_i)!==0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_pkg_colon_bad.v0000664000177100017500000000043313702133370023010 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (input mispkg::foo_t a); reg mispkgb::bar_t b; endmodule verilator-4.038/test_regress/t/t_dpi_2exp_bad.out0000664000177100017500000000037713702133370022072 0ustar wsnyderwsnyder%Error: t/t_dpi_2exp_bad.v:12:45: Function was already DPI Exported, duplicate not allowed: 'dpix_twice' 12 | export "DPI-C" dpix_t_int_renamed = task dpix_twice; | ^~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_uniqueif_fail1.out0000664000177100017500000000025113702133370022442 0ustar wsnyderwsnydertesting fail 1: 1 [10] %Error: t_uniqueif.v:74: Assertion failed in top.t: 'unique if' statement violated %Error: t/t_uniqueif.v:74: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_dpi_qw.v0000664000177100017500000000164713702133370020474 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; wire [39:0] out; sub a(.value(out)); import "DPI-C" context function void poke_value(input int i); initial begin poke_value(32'hdeadbeef); if (out !== 40'hdeadbeef) begin $display("[%0t] %%Error: t_dpi_qw: failed", $time); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule module sub(value); parameter WIDTH = 40; output [WIDTH-1:0] value; reg [WIDTH-1:0] value; task set_value(input bit [WIDTH-1:0] v); value = v; endtask export "DPI-C" task set_value; endmodule verilator-4.038/test_regress/t/t_case_genx_bad.v0000664000177100017500000000067713702133367021763 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); parameter P = 32'b1000; generate case (P) 32'b0: initial begin end 32'b1xxx: initial begin end default: initial begin end endcase endgenerate endmodule verilator-4.038/test_regress/t/t_clk_gen.pl0000775000177100017500000000105313702133367020761 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_packed_value_list.pl0000775000177100017500000000105313702133370024433 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_param.v0000664000177100017500000000141013702133370021453 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 package my_funcs; function automatic int simple_func (input int value); begin simple_func = value; end endfunction endpackage package my_module_types; import my_funcs::*; localparam MY_PARAM = 3; localparam MY_PARAM2 /*verilator public*/ = simple_func(12); endpackage module t import my_module_types::*; ( input i_clk, input [MY_PARAM-1:0] i_d, output logic [MY_PARAM-1:0] o_q ); always_ff @(posedge i_clk) o_q <= i_d; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_assign_landr.v0000664000177100017500000000406413702133370022521 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [255:0] sum; // Take CRC data and apply to testblock inputs wire [127:0] in = {~crc[63:0], crc[63:0]}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [127:0] o1; // From test of Test.v wire [127:0] o2; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .o1 (o1[127:0]), .o2 (o2[127:0]), // Inputs .in (in[127:0])); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x %x\n",$time, cyc, crc, o1, o2); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs o1, o2, // Inputs in ); input [127:0] in; output logic [127:0] o1; output logic [127:0] o2; always_comb begin: b_test logic [127:0] tmpp; logic [127:0] tmp; tmp = '0; tmpp = '0; tmp[63:0] = in[63:0]; tmpp[63:0] = in[63:0]; tmpp[63:0] = {tmp[0+:32], tmp[32+:32]}; tmp[63:0] = {tmp[0+:32], tmp[32+:32]}; o1 = tmp; o2 = tmpp; end endmodule verilator-4.038/test_regress/t/t_select_loop.v0000664000177100017500000000250213702133370021510 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [255:0] a; reg [255:0] q; reg [63:0] qq; integer i; always @* begin for (i=0; i<256; i=i+1) begin q[255-i] = a[i]; end q[27:16] = 12'hfed; for (i=0; i<64; i=i+1) begin qq[63-i] = a[i]; end qq[27:16] = 12'hfed; end always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%x/%x %x\n", q, qq, a); `endif if (cyc==1) begin a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; end if (cyc==2) begin a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop; if (qq != 64'h64fe7e285fed892e) $stop; end if (cyc==3) begin if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop; if (qq != 64'h1da9cf939fed1250) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_inst_dtree_inlbd.pl0000775000177100017500000000125113702133370022661 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_B +define+INLINE_D'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_red.v0000664000177100017500000000351613702133370020771 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [67:0] r; wire and_reduce = &r; wire or_reduce = |r; wire xor_reduce = ^r; wire xnor_reduce = ~^r; wire check_equal = r == 68'hffff_ffff_ffff_ffff_f; always @(posedge clk) begin `ifdef TEST_VERBOSE $display("cyc=%0d, r = %x, and_reduce = %x, or=%x xor=%x check_equal = %x", cyc, r, and_reduce, or_reduce, xor_reduce, check_equal); `endif cyc <= cyc + 1; if (cyc == 1) begin r <= 68'd0; end else if (cyc == 10) begin `checkh(r, 68'h0000_0000_0000_0000_0); `checkh(and_reduce, '0); `checkh(or_reduce, '0); `checkh(xor_reduce, '0); `checkh(xnor_reduce, '1); r <= 68'hffff_ffff_ffff_ffff_e; end else if (cyc == 11) begin `checkh(r, 68'hffff_ffff_ffff_ffff_e); `checkh(and_reduce, '0); `checkh(or_reduce, '1); `checkh(xor_reduce, '1); `checkh(xnor_reduce, '0); r <= 68'hffff_ffff_ffff_ffff_f; end else if (cyc == 12) begin `checkh(r, 68'hffff_ffff_ffff_ffff_f); `checkh(and_reduce, '1); `checkh(or_reduce, '1); `checkh(xor_reduce, '0); `checkh(xnor_reduce, '1); end else if (cyc == 90) begin $write("*-* All Finished *-*\n"); $finish; end else begin r <= 68'd0; end end endmodule verilator-4.038/test_regress/t/t_EXAMPLE.v0000664000177100017500000000513313702133367020304 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Use this file as a template for submitting bugs, etc. // This module takes a single clock input, and should either // $write("*-* All Finished *-*\n"); // $finish; // on success, or $stop. // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 ____YOUR_NAME_HERE____. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test(/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 90) begin end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs out, // Inputs clk, in ); // Replace this module with the device under test. // // Change the code in the t module to apply values to the inputs and // merge the output values into the result vector. input clk; input [31:0] in; output reg [31:0] out; always @(posedge clk) begin out <= in; end endmodule verilator-4.038/test_regress/t/t_gen_for_overlap.pl0000775000177100017500000000105313702133370022520 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_eqcase.v0000664000177100017500000000713613702133370021327 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; wire [3:0] drv_a = crc[3:0]; wire [3:0] drv_b = crc[7:4]; wire [3:0] drv_e = crc[19:16]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [8:0] match1; // From test1 of Test1.v wire [8:0] match2; // From test2 of Test2.v // End of automatics Test1 test1 (/*AUTOINST*/ // Outputs .match1 (match1[8:0]), // Inputs .drv_a (drv_a[3:0]), .drv_e (drv_e[3:0])); Test2 test2 (/*AUTOINST*/ // Outputs .match2 (match2[8:0]), // Inputs .drv_a (drv_a[3:0]), .drv_e (drv_e[3:0])); // Aggregate outputs into a single result vector wire [63:0] result = {39'h0, match2, 7'h0, match1}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n",$time, cyc, crc, match1, match2, drv_e,drv_a,drv_b); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test1 ( input wire [3:0] drv_a, input wire [3:0] drv_e, output wire [8:0] match1 ); wire [2:1] drv_all; bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]); `ifdef VERILATOR // At present Verilator only allows comparisons with Zs assign match1[0] = (drv_a[2:1]== 2'b00 && drv_e[2:1]==2'b11); assign match1[1] = (drv_a[2:1]== 2'b01 && drv_e[2:1]==2'b11); assign match1[2] = (drv_a[2:1]== 2'b10 && drv_e[2:1]==2'b11); assign match1[3] = (drv_a[2:1]== 2'b11 && drv_e[2:1]==2'b11); `else assign match1[0] = drv_all === 2'b00; assign match1[1] = drv_all === 2'b01; assign match1[2] = drv_all === 2'b10; assign match1[3] = drv_all === 2'b11; `endif assign match1[4] = drv_all === 2'bz0; assign match1[5] = drv_all === 2'bz1; assign match1[6] = drv_all === 2'bzz; assign match1[7] = drv_all === 2'b0z; assign match1[8] = drv_all === 2'b1z; endmodule module Test2 ( input wire [3:0] drv_a, input wire [3:0] drv_e, output wire [8:0] match2 ); wire [2:1] drv_all; bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]); `ifdef VERILATOR assign match2[0] = (drv_all !== 2'b00 || drv_e[2:1]!=2'b11); assign match2[1] = (drv_all !== 2'b01 || drv_e[2:1]!=2'b11); assign match2[2] = (drv_all !== 2'b10 || drv_e[2:1]!=2'b11); assign match2[3] = (drv_all !== 2'b11 || drv_e[2:1]!=2'b11); `else assign match2[0] = drv_all !== 2'b00; assign match2[1] = drv_all !== 2'b01; assign match2[2] = drv_all !== 2'b10; assign match2[3] = drv_all !== 2'b11; `endif assign match2[4] = drv_all !== 2'bz0; assign match2[5] = drv_all !== 2'bz1; assign match2[6] = drv_all !== 2'bzz; assign match2[7] = drv_all !== 2'b0z; assign match2[8] = drv_all !== 2'b1z; endmodule verilator-4.038/test_regress/t/t_interface_ref_trace_fst.pl0000775000177100017500000000132613702133370024202 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_ref_trace.v"); compile( verilator_flags2 => ['--trace-structs --trace-fst'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_func_task_bad.out0000664000177100017500000000027313702133370022330 0ustar wsnyderwsnyder%Error: t/t_func_task_bad.v:10:11: Illegal call of a task as a function: 'task_as_func' 10 | if (task_as_func(1'b0)) $stop; | ^~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_case_66bits.pl0000775000177100017500000000105313702133367021467 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_cat_reopen.pl0000775000177100017500000000157413702133370022656 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_trace_cat.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_cat.cpp"], ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simpart_0000.vcd", "t/$Self->{name}_0000.out"); vcd_identical("$Self->{obj_dir}/simpart_0100.vcd", "t/$Self->{name}_0100.out"); ok(1); 1; verilator-4.038/test_regress/t/t_unpacked_concat_bad.pl0000775000177100017500000000107113702133370023300 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_comp.pl0000775000177100017500000000116413702133367021701 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_slice_bad.v0000664000177100017500000000320013702133370021737 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic use_AnB; logic [1:0] active_command [8:0]; logic [1:0] command_A [8:0]; logic [1:0] command_B [8:0]; logic [1:0] active_command2 [8:0]; logic [1:0] command_A2 [7:0]; logic [1:0] command_B2 [8:0]; logic [1:0] active_command3 [1:0][2:0][3:0]; logic [1:0] command_A3 [1:0][2:0][3:0]; logic [1:0] command_B3 [1:0][2:0][3:0]; logic [1:0] active_command4 [8:0]; logic [1:0] command_A4 [7:0]; logic [1:0] active_command5 [8:0]; logic [1:0] command_A5 [7:0]; // Single dimension assign assign active_command[3:0] = (use_AnB) ? command_A[7:0] : command_B[7:0]; // Assignment of entire arrays assign active_command2 = (use_AnB) ? command_A2 : command_B2; // Multi-dimension assign assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; // Supported: Delayed assigment with RHS Var == LHS Var logic [7:0] arrd [7:0]; always_ff @(posedge clk) arrd[7:4] <= arrd[3:0]; // Unsupported: Non-delayed assigment with RHS Var == LHS Var logic [7:0] arr [7:0]; assign arr[7:4] = arr[3:0]; // Delayed assign always @(posedge clk) begin active_command4[7:0] <= command_A4[8:0]; end // Combinational assign always_comb begin active_command5[8:0] = command_A5[7:0]; end endmodule : t verilator-4.038/test_regress/t/t_preproc_inc_notfound_bad.out0000664000177100017500000000154113702133370024571 0ustar wsnyderwsnyder%Error: t/t_preproc_inc_notfound_bad.v:7:10: Cannot find include file: this_file_is_not_found.vh 7 | `include "this_file_is_not_found.vh" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ... Looked in: t/this_file_is_not_found.vh t/this_file_is_not_found.vh.v t/this_file_is_not_found.vh.sv ../include/this_file_is_not_found.vh ../include/this_file_is_not_found.vh.v ../include/this_file_is_not_found.vh.sv this_file_is_not_found.vh this_file_is_not_found.vh.v this_file_is_not_found.vh.sv obj_vlt/t_preproc_inc_notfound_bad/this_file_is_not_found.vh obj_vlt/t_preproc_inc_notfound_bad/this_file_is_not_found.vh.v obj_vlt/t_preproc_inc_notfound_bad/this_file_is_not_found.vh.sv %Error: Exiting due to verilator-4.038/test_regress/t/t_math_svl2.v0000664000177100017500000000163713702133370021107 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin // New number format if ('0 !== {66{1'b0}}) $stop; if ('1 !== {66{1'b1}}) $stop; if ('x !== {66{1'bx}}) $stop; if ('z !== {66{1'bz}}) $stop; `ifndef NC // NC-Verilog 5.50-s09 chokes on this test if ("\v" != 8'd11) $stop; if ("\f" != 8'd12) $stop; if ("\a" != 8'd7) $stop; if ("\x9a" != 8'h9a) $stop; if ("\xf1" != 8'hf1) $stop; `endif end if (cyc==8) begin end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_pp_circ_subst_bad.v0000664000177100017500000000035213702133370022646 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define e fun `e `e verilator-4.038/test_regress/t/t_interface_wrong_bad.pl0000775000177100017500000000107413702133370023336 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_typedef_unused_bad.out0000664000177100017500000000033013702133370023370 0ustar wsnyderwsnyder%Error: t/t_typedef_unused_bad.v:9:9: Forward typedef unused or does not resolve to a data type (IEEE 1800-2017 6.18): 'fwd_undecl_t' 9 | typedef fwd_undecl_t; | ^~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_preproc_stringend_bad.pl0000775000177100017500000000107413702133370023711 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlt_warn_bad.pl0000775000177100017500000000123013702133370022010 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_vlt_warn.v"); lint( verilator_flags2 => ["--lint-only t/t_vlt_warn_bad.vlt"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_inc_inc_bad.vh0000664000177100017500000000041113702133370023307 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module xx; xx // intentional error endmodule verilator-4.038/test_regress/t/t_display_real.out0000664000177100017500000000176213702133370022221 0ustar wsnyderwsnyder[0] e=0.000000e+00 e1=0.000000e+00 e30=0e+00 e32=0.00e+00 p=0 [0] f=0.000000 f1=0.000000e+00 f30=0e+00 f32=0.00e+00 p=0 [0] g=0 g1=0.000000e+00 g30=0e+00 g32=0.00e+00 p=0 [0] e=1.000000e+00 e1=1.000000e+00 e30=1e+00 e32=1.00e+00 p=1 [0] f=1.000000 f1=1.000000e+00 f30=1e+00 f32=1.00e+00 p=1 [0] g=1 g1=1.000000e+00 g30=1e+00 g32=1.00e+00 p=1 [0] e=1.000000e-01 e1=1.000000e-01 e30=1e-01 e32=1.00e-01 p=0.1 [0] f=0.100000 f1=1.000000e-01 f30=1e-01 f32=1.00e-01 p=0.1 [0] g=0.1 g1=1.000000e-01 g30=1e-01 g32=1.00e-01 p=0.1 [0] e=1.234500e-15 e1=1.234500e-15 e30=1e-15 e32=1.23e-15 p=1.2345e-15 [0] f=0.000000 f1=1.234500e-15 f30=1e-15 f32=1.23e-15 p=1.2345e-15 [0] g=1.2345e-15 g1=1.234500e-15 g30=1e-15 g32=1.23e-15 p=1.2345e-15 [0] e=2.579000e+15 e1=2.579000e+15 e30=3e+15 e32=2.58e+15 p=2.579e+15 [0] f=2579000000000000.000000 f1=2.579000e+15 f30=3e+15 f32=2.58e+15 p=2.579e+15 [0] g=2.579e+15 g1=2.579000e+15 g30=3e+15 g32=2.58e+15 p=2.579e+15 r8= 3 n1=1 n2=0.1 n1=1 n2=0.1 r8= 3 *-* All Finished *-* verilator-4.038/test_regress/t/t_dpi_var.v0000664000177100017500000000473513702133370020636 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; wire monclk = ~clk; int in; int fr_a; int fr_b; int fr_chk; sub sub (.*); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk); `endif cyc <= cyc + 1; in <= {in[30:0], in[31]^in[2]^in[0]}; if (cyc==0) begin // Setup in <= 32'hd70a4497; end else if (cyc<3) begin end else if (cyc<10) begin if (fr_chk != fr_a) $stop; if (fr_chk != fr_b) $stop; end else if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end always @(posedge t.monclk) begin mon_eval(); end endmodule `ifdef ATTRIBUTES import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ ); `else import "DPI-C" context function void mon_scope_name (input string formatted); `endif import "DPI-C" context function void mon_register_b(string name, int isOut); import "DPI-C" context function void mon_register_done(); import "DPI-C" context function void mon_eval(); module sub (/*AUTOARG*/ // Outputs fr_a, fr_b, fr_chk, // Inputs in ); `systemc_imp_header void mon_class_name(const char* namep); void mon_register_a(const char* namep, void* sigp, bool isOut); `verilog `ifdef ATTRIBUTES input int in /*verilator public_flat_rd*/; output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/; output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/; `else input int in; output int fr_a; output int fr_b; `endif output int fr_chk; always @* fr_chk = in + 1; initial begin // Test the naming $c("mon_class_name(name());"); mon_scope_name("%m"); // Scheme A - pass pointer directly $c("mon_register_a(\"in\",&",in,",false);"); $c("mon_register_a(\"fr_a\",&",fr_a,",true);"); // Scheme B - use VPIish callbacks to see what signals exist mon_register_b("in", 0); mon_register_b("fr_b", 1); mon_register_done(); end endmodule verilator-4.038/test_regress/t/t_bitsel_enum.pl0000775000177100017500000000105313702133367021665 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_implicit_bad.pl0000775000177100017500000000123013702133370023014 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_lint_implicit.v"); lint( verilator_flags2 => ["--lint-only -Wwarn-IMPLICIT"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_unpacked_public.v0000664000177100017500000000063613702133367023542 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 module t(); logic din [0:15]; array_test array_test_inst(.din(din)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module array_test( input din [0:15] ); endmodule verilator-4.038/test_regress/t/t_trace_primitive.v0000664000177100017500000000125313702133370022370 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 module t ( clk ); input clk; integer cyc; initial cyc = 0; reg a; reg b; reg z; sub_t sub_t_i (z, a, b); always @ (posedge clk) begin cyc <= cyc + 1; a <= cyc[0]; b <= cyc[1]; if (cyc > 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule primitive CINV (a, b); output b; input a; assign b = ~a; endprimitive module sub_t (z, x, y); input x, y; output z; assign z = x & y; endmodule verilator-4.038/test_regress/t/t_math_signed4.pl0000775000177100017500000000105313702133370021717 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_setout_bad_noinl.out0000664000177100017500000000040413702133370024117 0ustar wsnyderwsnyder%Error-PORTSHORT: t/t_lint_setout_bad.v:17:8: Output port is connected to a constant pin, electrical short : ... In instance t 17 | .cpu_if_timeout(1'b0) | ^~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_unoptflat_simple_2.v0000664000177100017500000000120713702133370023007 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Simple test of unoptflat // // Simple demonstration of an UNOPTFLAT combinatorial loop, using 3 bits. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [2:0] x; assign x[1:0] = { x[0], clk }; assign x[2:1] = x[1:0]; always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("x = %x\n", x); `endif if (x[2] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule // t verilator-4.038/test_regress/t/t_dist_contributors.pl0000775000177100017500000000445513702133370023142 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use strict; use vars qw($Self); scenarios(dist => 1); my $root = ".."; my $Debug; my %Contributors; my %Authors; if (!-r "$root/.git") { skip("Not in a git repository"); } else { check(); } ok(1); 1; sub check { read_contributors("$root/docs/CONTRIBUTORS"); read_user(); read_authors(); for my $author (sort keys %Authors) { print "Check: $author\n" if $Self->{verbose}; if (!$Contributors{$author}) { error("Certify your contribution by sorted-inserting '$author' into docs/CONTRIBUTORS.\n" ." If '$author' is not your real name, please fix 'name=' in ~/.gitconfig\n" ." Also check your https://github.com account's Settings->Profile->Name\n" ." matches your ~/.gitconfig 'name='.\n"); } } } sub read_contributors { my $filename = shift; my $fh = IO::File->new("<$filename") or error("$! $filename"); # Assumes git .mailmap format while (my $line = ($fh && $fh->getline)) { while ($line =~ /(.*)/g) { $line =~ s/ *<[^>]*>//; $Contributors{$1} = 1; } } } sub read_user { my $changes = `cd $root ; git diff-index --quiet HEAD --`; chomp $changes; if (!$changes) { print "No git changes\n" if $Self->{verbose}; } else { # Uncommitted changes, so check the user's git name my $user = `git config user.name`; chomp $user; my $email = `git config user.email`; chomp $email; if ($user && $email) { $Authors{"$user <$email>"} = 1; } } } sub read_authors { # Check recent commits in case did commit my $git_auths = `git log '--pretty=format:%aN <%aE>' | head -5`; foreach my $line (split /\n/, $git_auths) { $line =~ s/ *<[^>]*>//; $Authors{$line} = 1; } } verilator-4.038/test_regress/t/t_pp_dupdef_bad.out0000664000177100017500000000106013702133370022314 0ustar wsnyderwsnyder%Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Redefining existing define: 'DUP', with different value: barney ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message. %Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Previous definition is here, with value: fred %Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Redefining existing define: 'DUPP', with different value: paramed(x,z) (x*z) %Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Previous definition is here, with value: paramed(x) (x) %Error: Exiting due to verilator-4.038/test_regress/t/t_f_bad.out0000664000177100017500000000012313702133370020572 0ustar wsnyderwsnyder%Error: Cannot open -f command file: file_will_not_exist.vc %Error: Exiting due to verilator-4.038/test_regress/t/t_vpi_param.cpp0000664000177100017500000002125313702133370021477 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "Vt_vpi_param.h" #include "verilated.h" #include "svdpi.h" #include "Vt_vpi_param__Dpi.h" #include "verilated_vpi.h" #include "verilated_vcd_c.h" #endif #include #include #include #include "TestSimulator.h" #include "TestVpi.h" // __FILE__ is too long #define FILENM "t_vpi_param.cpp" #define DEBUG \ if (0) printf unsigned int main_time = 0; //====================================================================== #define CHECK_RESULT_VH(got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d: GOT = %p EXP = %p\n", FILENM, __LINE__, (got), (exp)); \ return __LINE__; \ } #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ return __LINE__; \ } // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_HEX(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << std::hex \ << ": GOT = " << (got) << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ (got) ? (got) : "", (exp) ? (exp) : ""); \ return __LINE__; \ } #define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp) int check_param_int(std::string name, PLI_INT32 format, int exp_value, bool verbose) { int vpi_type; TestVpiHandle param_h; s_vpi_value value; value.format = format; value.value.integer = 0; s_vpi_error_info e; const char* p; vpi_printf((PLI_BYTE8*)"Check parameter %s vpi ...\n", name.c_str()); param_h = vpi_handle_by_name((PLI_BYTE8*)TestSimulator::rooted(name.c_str()), NULL); CHECK_RESULT_NZ(param_h); vpi_type = vpi_get(vpiType, param_h); CHECK_RESULT(vpi_type, vpiParameter); if (verbose) {vpi_printf((PLI_BYTE8*)" vpiType: %s (%d)\n", vpi_get_str(vpiType, param_h), vpi_type); } // attributes p = vpi_get_str(vpiName, param_h); CHECK_RESULT_CSTR(p, name.c_str()); p = vpi_get_str(vpiFullName, param_h); CHECK_RESULT_CSTR(p, std::string("t." + name).c_str()); p = vpi_get_str(vpiType, param_h); CHECK_RESULT_CSTR(p, "vpiParameter"); vpi_type = vpi_get(vpiLocalParam, param_h); CHECK_RESULT_NZ(vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) {vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } // values if (verbose) {vpi_printf((PLI_BYTE8*)" Try writing value to %s ...\n", name.c_str()); } value.value.integer = exp_value; vpi_put_value(param_h, &value, NULL, vpiNoDelay); CHECK_RESULT_NZ(vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) {vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } if (verbose) {vpi_printf((PLI_BYTE8*)" Try reading value of %s ...\n", name.c_str()); } vpi_get_value(param_h, &value); CHECK_RESULT_NZ(!vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) {vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } if (verbose) {vpi_printf((PLI_BYTE8*)" value of %s: %d\n", name.c_str(), value.value.integer); } CHECK_RESULT(value.value.integer, exp_value); return 0; } int check_param_str(std::string name, PLI_INT32 format, std::string exp_value, bool verbose) { int vpi_type; TestVpiHandle param_h; s_vpi_value value; value.format = format; value.value.integer = 0; s_vpi_error_info e; const char* p; vpi_printf((PLI_BYTE8*)"Check parameter %s vpi ...\n", name.c_str()); param_h = vpi_handle_by_name((PLI_BYTE8*)TestSimulator::rooted(name.c_str()), NULL); CHECK_RESULT_NZ(param_h); vpi_type = vpi_get(vpiType, param_h); CHECK_RESULT(vpi_type, vpiParameter); if (verbose) {vpi_printf((PLI_BYTE8*)" vpiType: %s (%d)\n", vpi_get_str(vpiType, param_h), vpi_type); } // attributes p = vpi_get_str(vpiName, param_h); CHECK_RESULT_CSTR(p, name.c_str()); p = vpi_get_str(vpiFullName, param_h); CHECK_RESULT_CSTR(p, std::string("t." + name).c_str()); p = vpi_get_str(vpiType, param_h); CHECK_RESULT_CSTR(p, "vpiParameter"); vpi_type = vpi_get(vpiLocalParam, param_h); CHECK_RESULT_NZ(vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) {vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } // values if (verbose) {vpi_printf((PLI_BYTE8*)" Try writing value to %s ...\n", name.c_str()); } value.value.str = (PLI_BYTE8*) exp_value.c_str(); vpi_put_value(param_h, &value, NULL, vpiNoDelay); CHECK_RESULT_NZ(vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) {vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } if (verbose) {vpi_printf((PLI_BYTE8*)" Try reading value of %s ...\n", name.c_str()); } vpi_get_value(param_h, &value); CHECK_RESULT_NZ(!vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) {vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } if (verbose) {vpi_printf((PLI_BYTE8*)" value of %s: %s\n", name.c_str(), value.value.str); } CHECK_RESULT_CSTR(value.value.str, exp_value.c_str()); return 0; } int _mon_check_param() { int status = 0; #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif status += check_param_int("WIDTH", vpiIntVal, 32, verbose); status += check_param_int("DEPTH", vpiIntVal, 16, verbose); status += check_param_str("PARAM_LONG", vpiHexStrVal, "fedcba9876543210", verbose); status += check_param_str("PARAM_STR", vpiStringVal, "'some string value'", verbose); return status; } int mon_check() { // Callback from initial block in monitor if (int status = _mon_check_param()) return status; return 0; // Ok } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { vpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); // we're going to be checking for these errors do don't crash out Verilated::fatalOnVpiError(0); VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out #ifdef VERILATOR #ifdef TEST_VERBOSE Verilated::scopesDump(); #endif #endif #if VM_TRACE Verilated::traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; main_time += 10; while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += 1; topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } if (!Verilated::gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete topp, topp); exit(0L); } #endif verilator-4.038/test_regress/t/t_langext_4_bad.pl0000775000177100017500000000115513702133370022047 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_langext_2.v"); # This is a lint only test. lint( v_flags2 => ["+1800-2005ext+v"], fails => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_invalid_bad.pl0000775000177100017500000000114613702133370022601 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, verilator_flags2 => ['--invalid-dash'], expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_under2.v0000664000177100017500000000173013702133370021414 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug598 module t (/*AUTOARG*/ // Outputs val, // Inputs clk ); input clk; output integer val; integer dbg_addr = 0; function func1; input en; input [31:0] a; func1 = en && (a == 1); endfunction function func2; input en; input [31:0] a; func2 = en && (a == 2); endfunction always @(posedge clk) begin case( 1'b1 ) // This line is OK: func1(1'b1, dbg_addr) : val = 1; // This fails: // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement func2(1'b1, dbg_addr) : val = 2; default : val = 0; endcase // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_sys_readmem_b_8.mem0000664000177100017500000000076013702133370022555 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // ** Note this file has DOS CR's so we can test them! 10000 10001 10010 10011 /* multi line ignored */ 10100 10101 10110 10111 verilator-4.038/test_regress/t/t_flag_debug_noleak.pl0000775000177100017500000000117013702133370022761 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( v_flags2 => ["--debug --no-debug-leak"], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_recurse1.v0000664000177100017500000000130413702133370021567 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Sean Moore. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); rec rec (); endmodule module rec; parameter DEPTH = 1; generate if (DEPTH==1) begin rec #(.DEPTH(DEPTH+1)) sub; end else if (DEPTH==2) begin rec #(.DEPTH(DEPTH+1)) subb; end else if (DEPTH==3) begin bottom #(.DEPTH(DEPTH+1)) bot; end endgenerate endmodule module bottom; parameter DEPTH = 1; initial begin if (DEPTH!=4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_struct_nest.v0000664000177100017500000000203113702133370021552 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic [1:0] b1; logic [1:0] b2; logic [1:0] b3; logic [1:0] b4; } t__aa_bbbbbbb_ccccc_dddddd_eee; typedef struct packed { logic [31:0] a; union packed { logic [7:0] fbyte; t__aa_bbbbbbb_ccccc_dddddd_eee pairs; } b1; logic [23:0] b2; logic [7:0] c1; logic [23:0] c2; logic [31:0] d; } t__aa_bbbbbbb_ccccc_dddddd; typedef struct packed { logic [31:0] a; logic [31:0] b; logic [31:0] c; logic [31:0] d; } t__aa_bbbbbbb_ccccc_eee; typedef union packed { t__aa_bbbbbbb_ccccc_dddddd dddddd; t__aa_bbbbbbb_ccccc_eee eee; } t__aa_bbbbbbb_ccccc; module t ( input t__aa_bbbbbbb_ccccc xxxxxxx_yyyyy_zzzz, output logic [15:0] datao_pre ); always_comb datao_pre = { xxxxxxx_yyyyy_zzzz.dddddd.b1.fbyte, xxxxxxx_yyyyy_zzzz.dddddd.c1 }; endmodule verilator-4.038/test_regress/t/t_lint_input_eq_bad.v0000664000177100017500000000044413702133370022663 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire i, input wire i2 = i // BAD ); endmodule verilator-4.038/test_regress/t/t_unopt_combo_isolate.vlt0000664000177100017500000000070713702133370023611 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config isolate_assignments -module "file" -var "b" isolate_assignments -module "file" -task "set_b_d" -var "t_c*" isolate_assignments -module "file" -function "get_31_16" -var "t_crc" isolate_assignments -module "file" -function "get_31_16" verilator-4.038/test_regress/t/t_sys_rand_seed.pl0000775000177100017500000000116713702133370022201 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); execute( ) if !$Self->{vlt_all}; ok(1); 1; verilator-4.038/test_regress/t/t_var_xref_gen.v0000664000177100017500000000163313702133370021651 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This is to test the handling of VarXRef when the referenced VAR is // under a generate construction. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Jie Xu and Roland Kruse. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, addr, res ); input clk; input [31:0] addr; output [15:0] res; memory i_mem(.addr(addr),.dout(res)); assign i_mem.cxrow_inst[0].cmem_xrow[0] = 16'h0; endmodule module memory(addr, dout); parameter CM_XROWSIZE = 256; parameter CM_NUMXROWS = 2; input [31:0] addr; output [15:0] dout; generate genvar g_cx; for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++) begin: cxrow_inst reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1]; end endgenerate assign dout = cxrow_inst[0].cmem_xrow[addr]; endmodule verilator-4.038/test_regress/t/t_interface_param_loop_bad.v0000664000177100017500000000107513702133370024163 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 module t (); simple_bus #(.WIDTH(simple.get_width())) sb_intf(); simple_bus #(.WIDTH(sb_intf.get_width())) simple(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule interface simple_bus #(parameter int WIDTH = 8); logic [WIDTH-1:0] data; function automatic int get_width(); return WIDTH; endfunction endinterface verilator-4.038/test_regress/t/t_param_concat_bad.pl0000775000177100017500000000114113702133370022604 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_param_concat.v"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_open_query.pl0000775000177100017500000000213113702133370022371 0ustar wsnyderwsnyder#!/usr/bin/perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if ($Self->{nc}) { # For NC, compile twice, first just to generate DPI headers compile( nc_flags2 => ["+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] ); } compile( v_flags2 => ["t/t_dpi_open_query.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], # NC: Gdd the obj_dir to the C include path nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", "-ccflags -I$Self->{obj_dir}"], ); execute( check_finished => 1, ms_pli => 0 ); ok(1); 1; verilator-4.038/test_regress/t/t_case_x.pl0000775000177100017500000000113213702133367020617 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--x-assign 0"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_split_var_0.v0000664000177100017500000003624213702133370021432 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 // If split_var pragma is removed, UNOPTFLAT appears. module barshift_1d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out /*verilator split_var*/); localparam OFFSET = -3; `ifdef TEST_ATTRIBUTES logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; `else logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET]; `endif generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp[i+1+OFFSET] = tmp[i+OFFSET]; end end endgenerate assign tmp[0+OFFSET] = in; assign out[WIDTH-1-:WIDTH-1] = tmp[DEPTH+OFFSET][WIDTH-1:1]; assign out[0] = tmp[DEPTH+OFFSET][0+:1]; endmodule module barshift_1d_unpacked_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = -3; // almost same as above module, but tmp[smaller:bigger] here. logic [WIDTH-1:0] tmp[OFFSET:DEPTH+OFFSET] /*verilator split_var*/; generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp[i+1+OFFSET] = tmp[i+OFFSET]; end end endgenerate assign tmp[0+OFFSET] = in; assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_1d_unpacked_struct0 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = 1; typedef struct packed { logic [WIDTH-1:0] data; } data_type; data_type tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp[i+1+OFFSET] = tmp[i+OFFSET]; end end endgenerate assign tmp[0+OFFSET] = in; assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_2d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = 1; localparam N = 3; reg [WIDTH-1:0] tmp0[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp1[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp2[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; reg [WIDTH-1:0] tmp3[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp4[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp5[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; reg [WIDTH-1:0] tmp6[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp7[DEPTH+OFFSET+1:OFFSET+1][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp8[DEPTH+OFFSET+3:OFFSET-1][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp9[DEPTH+OFFSET+3:OFFSET+3][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp10[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; // because tmp11 is not split for testing mixture usage of split_var and no-spliv_ar, // UNOPTFLAT appears, but it's fine. /*verilator lint_off UNOPTFLAT*/ reg [WIDTH-1:0] tmp11[-1:1][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator lint_on UNOPTFLAT*/ reg [WIDTH-1:0] tmp12[-1:0][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp13[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; generate for(genvar i = 0; i < DEPTH; ++i) begin for(genvar j = OFFSET; j < N + OFFSET; ++j) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp0[i+1+OFFSET][j] = {tmp0[i+OFFSET][j][(1 << i)-1:0], tmp0[i+OFFSET][j][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp0[i+1+OFFSET][j] = tmp0[i+OFFSET][j]; end end end for(genvar j = OFFSET; j < N + OFFSET; ++j) begin assign tmp0[0 + OFFSET][j] = in; end endgenerate assign tmp1 = tmp0; // split both side assign tmp2 = tmp1; // split only rhs assign tmp3 = tmp2; // split only lhs always_comb tmp4 = tmp3; // split both side always_comb tmp5 = tmp4; // split only rhs always_comb tmp6 = tmp5; // split only lhs assign tmp7 = tmp6; assign tmp8[DEPTH+OFFSET+1:OFFSET+1] = tmp7; assign tmp9 = tmp8[DEPTH+OFFSET+1:OFFSET+1]; assign tmp10[DEPTH+OFFSET:OFFSET] = tmp9[DEPTH+OFFSET+3:OFFSET+3]; assign tmp11[1] = tmp10; assign tmp11[-1] = tmp11[1]; assign tmp11[0] = tmp11[-1]; assign tmp12 = tmp11[0:1]; assign out = tmp12[1][DEPTH+OFFSET][OFFSET]; endmodule module barshift_1d_unpacked_struct1 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = 2; typedef struct packed { int data; } data_type; data_type tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; localparam [32-WIDTH-1:0] pad = 0; generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp[i+1+OFFSET] = {pad, tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp[i+1+OFFSET] = tmp[i+OFFSET]; end end endgenerate assign tmp[0+OFFSET] = {pad, in}; assign out = tmp[DEPTH+OFFSET][WIDTH-1:0]; endmodule module barshift_2d_packed_array #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = -2; /*verilator lint_off LITENDIAN*/ reg [OFFSET:DEPTH+OFFSET][WIDTH-1:0] tmp /*verilator split_var*/; /*verilator lint_on LITENDIAN*/ generate for(genvar i = 0; i < DEPTH; ++i) begin always @(shift or tmp) /*verilator lint_off ALWCOMBORDER*/ if (shift[i]) begin tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; end else begin tmp[i+1+OFFSET][1:0] = tmp[i+OFFSET][1:0]; tmp[i+1+OFFSET][WIDTH-1:2] = tmp[i+OFFSET][WIDTH-1:2]; end /*verilator lint_on ALWCOMBORDER*/ end endgenerate assign tmp[0+OFFSET] = in; assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_2d_packed_array_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = -2; /*verilator lint_off LITENDIAN*/ reg [OFFSET:DEPTH+OFFSET][OFFSET:WIDTH-1+OFFSET] tmp /*verilator split_var*/; /*verilator lint_on LITENDIAN*/ generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb /*verilator lint_off ALWCOMBORDER*/ if (shift[i]) begin tmp[i+1+OFFSET] = {tmp[i+OFFSET][WIDTH-(2**i)+OFFSET:WIDTH-1+OFFSET], tmp[i+OFFSET][OFFSET:WIDTH-(2**i)-1+OFFSET]}; end else begin // actulally just tmp[i+1+OFFSET] = tmp[i+OFFSET] tmp[i+1+OFFSET][0+OFFSET:2+OFFSET] = tmp[i+OFFSET][0+OFFSET:2+OFFSET]; tmp[i+1+OFFSET][3+OFFSET] = tmp[i+OFFSET][3+OFFSET]; {tmp[i+1+OFFSET][4+OFFSET],tmp[i+1+OFFSET][5+OFFSET]} = {tmp[i+OFFSET][4+OFFSET], tmp[i+OFFSET][5+OFFSET]}; {tmp[i+1+OFFSET][7+OFFSET],tmp[i+1+OFFSET][6+OFFSET]} = {tmp[i+OFFSET][7+OFFSET], tmp[i+OFFSET][6+OFFSET]}; end /*verilator lint_on ALWCOMBORDER*/ end endgenerate assign tmp[0+OFFSET] = in; assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_1d_packed_struct #(localparam DEPTH = 3, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); typedef struct packed { logic [WIDTH-1:0] v0, v1, v2, v3; } data_type; wire data_type tmp /*verilator split_var*/; assign tmp.v0 = in; assign tmp.v1 = shift[0] == 1'b1 ? {tmp.v0[(1 << 0)-1:0], tmp.v0[WIDTH-1:2**0]} : tmp.v0; assign tmp.v2 = shift[1] == 1'b1 ? {tmp.v1[(1 << 1)-1:0], tmp.v1[WIDTH-1:2**1]} : tmp.v1; assign tmp.v3 = shift[2] == 1'b1 ? {tmp.v2[(1 << 2)-1:0], tmp.v2[WIDTH-1:2**2]} : tmp.v2; assign out = tmp.v3; endmodule module barshift_bitslice #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); /*verilator lint_off LITENDIAN*/ wire [0:WIDTH*(DEPTH+1) - 1] tmp /*verilator split_var*/; /*verilator lint_on LITENDIAN*/ generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin tmp[WIDTH*(i+1):WIDTH*(i+1+1)-1] = {tmp[WIDTH*(i+1)-(1< 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_queue_unsup_bad.v0000664000177100017500000000502313702133370022365 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/); initial begin string q[$]; string v; int i; q.push_front("non-empty"); i = q.size(); `checkh(i, 0); q = {"q", "b", "c", "d", "e", "f"}; v = $sformatf("%p", q); `checks(v, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"} "); q.delete(1); v = q[1]; `checks(v, "c"); q.insert(0, "ins0"); q.insert(2, "ins2"); v = q[0]; `checks(v, "ins0"); v = q[2]; `checks(v, "ins2"); v = $sformatf("%p", q); `checks(v, "'{need_update, \"q\", \"b\", \"c\", \"d\", \"e\", \"f\"} "); // Similar using implied notation q = {q, "f1"}; // push_front q = {q, "f2"}; // push_front q = {"b1", q}; // push_back q = {"b2", q}; // push_back q = {q[0], q[2:$]}; // delete element 1 v = $sformatf("%p", q); `checks(v, "'{need_update, \"q\", \"b\", \"c\", \"d\", \"e\", \"f\"} "); begin string ai[$] = { "Foo", "Bar" }; q = ai; // Copy i = q.size(); `checkh(i, 2); v = q.pop_front(); `checks(v, "Foo"); v = q.pop_front(); `checks(v, "Bar"); q = '{ "BB", "CC" }; // Note '{} not {} v = q.pop_front(); `checks(v, "BB"); v = q.pop_front(); `checks(v, "CC"); q = { "BB", "CC" }; // Note {} not '{} v = q.pop_front(); `checks(v, "BB"); v = q.pop_front(); `checks(v, "CC"); end // Unpacked methods also allowed. Not supported yet. // find() // find_index() // find_first() // find_first_index() // find_last() // find_last_index() // min() // max() // unique() // unique_index() // reverse() // sort() // rsort() // shuffle() // sum() // product() // and() // or() // xor() end endmodule verilator-4.038/test_regress/t/t_math_msvc_64.v0000664000177100017500000000274313702133370021501 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [89:0] in; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [89:0] out; // From test of Test.v wire [44:0] line0; wire [44:0] line1; // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[89:0]), .line0 (line0[44:0]), .line1 (line1[44:0]), // Inputs .clk (clk), .in (in[89:0])); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out); `endif cyc <= cyc + 1; if (cyc==0) begin // Setup in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; end else if (cyc==10) begin if (in==out) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("*-* Failed!! *-*\n"); $finish; end end end endmodule module Test (/*AUTOARG*/ // Outputs line0, line1, out, // Inputs clk, in ); input clk; input [89:0] in; output reg [44:0] line0; output reg [44:0] line1; output reg [89:0] out; assign {line0,line1} = in; always @(posedge clk) begin out <= {line0,line1}; end endmodule verilator-4.038/test_regress/t/t_preproc_noline.out0000664000177100017500000000010713702133370022557 0ustar wsnyderwsnyderHello in t_preproc_psl.v yes Multi text multiline line Line: 21 verilator-4.038/test_regress/t/t_trace_two_port_cc.pl0000775000177100017500000000221313702133370023050 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); top_filename("t_trace_two_a.v"); compile( make_main => 0, verilator_make_gmake => 0, top_filename => 't_trace_two_b.v', VM_PREFIX => 'Vt_trace_two_b', verilator_flags2 => ['-trace'], ); compile( make_main => 0, top_filename => 't_trace_two_a.v', verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"], v_flags2 => ['+define+TEST_DUMPPORTS'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } ok(1); 1; verilator-4.038/test_regress/t/t_select_little_pack.v0000664000177100017500000000122213702133370023030 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // No endian warning here reg [7:0] pack [3:0]; initial begin pack[0] = 8'h78; pack[1] = 8'h88; pack[2] = 8'h98; pack[3] = 8'hA8; if (pack[0] !== 8'h78) $stop; if (pack[1] !== 8'h88) $stop; if (pack[2] !== 8'h98) $stop; if (pack[3] !== 8'hA8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_unsized_bad.pl0000775000177100017500000000107413702133370022671 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_pullup.v0000664000177100017500000000121413702133370021376 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module top (input A, input OE, output X, output Y, output Z); pullup p1(Z); assign Z = OE ? A : 1'bz; pulldown p2(Y); assign Y = OE ? A : 1'bz; pass pass(.A(A), .OE(OE), .X(X)); pullup_module p(X); endmodule module pass (input A, input OE, inout X); io io(.A(A), .OE(OE), .X(X)); endmodule module io (input A, input OE, inout X); assign X = (OE) ? A : 1'bz; endmodule module pullup_module (output X); pullup p1(X); endmodule verilator-4.038/test_regress/t/t_trace_complex_old_api.pl0000775000177100017500000000253613702133370023674 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Same test as t_trace_complex, but exercising the old VCD tracing API scenarios(vlt => 1); top_filename("t/t_trace_complex.v"); compile( verilator_flags2 => ['--cc --trace -CFLAGS -DVL_TRACE_VCD_OLD_API'], ); execute( check_finished => 1, ); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_arrp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arrp\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_strp\(/); vcd_identical ("$Self->{obj_dir}/simx.vcd", "t/t_trace_complex.out"); ok(1); 1; verilator-4.038/test_regress/t/t_unroll_forfor.v0000664000177100017500000000156013702133370022073 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This files is used to generated the following error: // %Error: Internal Error: t/t_unroll_forfor.v:27: ../V3Simulate.h:177: No value found for node. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Jan Egil Ruud. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, in ); input clk; input [71:0] in; reg [71:0] in_tmp; localparam [71:0] TEST_PARAM = {72{1'b0}}; // Test loop always @* begin: testmap byte i, j; // bug1044 for ( i = 0; i < 9; i = i + 1 ) // verilator lint_off WIDTH for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1) begin in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j]; end // verilator lint_on WIDTH $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_preproc_undefineall.pl0000775000177100017500000000105413702133370023372 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( v_flags2 => ['+define+PREDEF_COMMAND_LINE'], ); ok(1); 1; verilator-4.038/test_regress/t/t_class_extends_bad.out0000664000177100017500000000041513702133367023216 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_class_extends_bad.v:13:26: Multiple inheritance illegal on non-interface classes (IEEE 1800-2017 8.13), and unsupported for interface classes. 13 | class Cls extends Base1, Base2; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_assoc_meth_bad.out0000664000177100017500000000407613702133367022513 0ustar wsnyderwsnyder%Error: t/t_assoc_meth_bad.v:14:13: The 1 arguments passed to .num method does not match its requiring 0 arguments : ... In instance t 14 | v = a.num("badarg"); | ^~~ %Error: t/t_assoc_meth_bad.v:15:13: The 1 arguments passed to .size method does not match its requiring 0 arguments : ... In instance t 15 | v = a.size("badarg"); | ^~~~ %Error: t/t_assoc_meth_bad.v:16:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments : ... In instance t 16 | v = a.exists(); | ^~~~~~ %Error: t/t_assoc_meth_bad.v:17:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments : ... In instance t 17 | v = a.exists(k, "bad2"); | ^~~~~~ %Error: t/t_assoc_meth_bad.v:18:13: The 0 arguments passed to .first method does not match its requiring 1 arguments : ... In instance t 18 | v = a.first(); | ^~~~~ %Error: t/t_assoc_meth_bad.v:19:13: The 2 arguments passed to .next method does not match its requiring 1 arguments : ... In instance t 19 | v = a.next(k, "bad2"); | ^~~~ %Error: t/t_assoc_meth_bad.v:20:13: The 0 arguments passed to .last method does not match its requiring 1 arguments : ... In instance t 20 | v = a.last(); | ^~~~ %Error: t/t_assoc_meth_bad.v:21:13: The 2 arguments passed to .prev method does not match its requiring 1 arguments : ... In instance t 21 | v = a.prev(k, "bad2"); | ^~~~ %Error: t/t_assoc_meth_bad.v:22:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments : ... In instance t 22 | a.delete(k, "bad2"); | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_array_fst_portable.pl0000775000177100017500000000147213702133370024416 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_trace_array.v"); $Self->{golden_filename} = "t/t_trace_array_fst.out"; compile( verilator_flags2 => ['--cc --trace-fst --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_flag_topmodule.v0000664000177100017500000000117413702133370022205 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module a; c c (); initial begin $write("Bad top modules\n"); $stop; end endmodule module a2; initial begin $write("Bad top modules\n"); $stop; end endmodule module b; d d (); endmodule module c; initial begin $write("Bad mid modules\n"); $stop; end endmodule module d; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_rsvd_bad.out0000664000177100017500000000070213702133370022354 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:7:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config' 7 | config cfgBad; | ^~~~~~ %Error: t/t_lint_rsvd_bad.v:7:8: syntax error, unexpected IDENTIFIER 7 | config cfgBad; | ^~~~~~ %Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:8:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig' 8 | endconfig | ^~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_langext_order.pl0000775000177100017500000000110513702133370022204 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # This is a compile only test. compile( v_flags2 => ["+1364-2005ext+v"], ); ok(1); 1; verilator-4.038/test_regress/t/t_extend_class.v0000664000177100017500000000236313702133370021661 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc=0; reg [31:0] in; wire [31:0] out; t_extend_class_v sub (.in(in), .out(out)); always @ (posedge clk) begin cyc <= cyc+8'd1; if (cyc == 8'd1) begin in <= 32'h10; end if (cyc == 8'd2) begin if (out != 32'h11) $stop; end if (cyc == 8'd9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_extend_class_v (/*AUTOARG*/ // Outputs out, // Inputs in ); input [31:0] in; output logic [31:0] out; always @* begin // When "in" changes, call my method out = $c("m_myobjp->my_math(",in,")"); end `systemc_header #include "t_extend_class_c.h" // Header for contained object `systemc_interface t_extend_class_c* m_myobjp; // Pointer to object we are embedding `systemc_ctor m_myobjp = new t_extend_class_c(); // Construct contained object `systemc_dtor delete m_myobjp; // Destruct contained object `verilog endmodule verilator-4.038/test_regress/t/t_wire_beh1364_bad.out0000664000177100017500000000227213702133370022456 0ustar wsnyderwsnyder%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' : ... In instance t 25 | w = '0; | ^ %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 26 | o = '0; | ^ %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' : ... In instance t 27 | oa = '0; | ^~ %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo' : ... In instance t 28 | wo = '0; | ^~ %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa' : ... In instance t 29 | woa = '0; | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_inst_first.v0000664000177100017500000000703013702133370021365 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, fastclk ); input clk; input fastclk; genvar unused; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire o_com; // From b of t_inst_first_b.v wire o_seq_d1r; // From b of t_inst_first_b.v // End of automatics integer _mode; // initial _mode=0 reg na,nb,nc,nd,ne; wire ma,mb,mc,md,me; wire da,db,dc,dd,de; reg [7:0] wa,wb,wc,wd,we; wire [7:0] qa,qb,qc,qd,qe; wire [5:0] ra; wire [4:0] rb; wire [29:0] rc; wire [63:0] rd; reg [5:0] sa; reg [4:0] sb; reg [29:0] sc; reg [63:0] sd; reg _guard1; initial _guard1=0; wire [104:0] r_wide = {ra,rb,rc,rd}; reg _guard2; initial _guard2=0; wire [98:0] r_wide0 = {rb,rc,rd}; reg _guard3; initial _guard3=0; wire [93:0] r_wide1 = {rc,rd}; reg _guard4; initial _guard4=0; wire [63:0] r_wide2 = {rd}; reg _guard5; initial _guard5=0; wire [168:0] r_wide3 = {ra,rb,rc,rd,rd}; reg [127:0] _guard6; initial _guard6=0; t_inst_first_a a ( .clk (clk), // Outputs .o_w5 ({ma,mb,mc,md,me}), .o_w5_d1r ({da,db,dc,dd,de}), .o_w40 ({qa,qb,qc,qd,qe}), .o_w104 ({ra,rb,rc,rd}), // Inputs .i_w5 ({na,nb,nc,nd,ne}), .i_w40 ({wa,wb,wc,wd,we}), .i_w104 ({sa,sb,sc,sd}) ); reg i_seq; reg i_com; wire [15:14] o2_comhigh; t_inst_first_b b ( .o2_com (o2_comhigh), .i2_com ({i_com,~i_com}), .wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd), .wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd), /*AUTOINST*/ // Outputs .o_seq_d1r (o_seq_d1r), .o_com (o_com), // Inputs .clk (clk), .i_seq (i_seq), .i_com (i_com)); // surefire lint_off STMINI initial _mode = 0; always @ (posedge fastclk) begin if (_mode==1) begin if (o_com !== ~i_com) $stop; if (o2_comhigh !== {~i_com,i_com}) $stop; end end always @ (posedge clk) begin //$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode, // {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de}); $write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r); if (_mode==0) begin $write("[%0t] t_inst: Running\n", $time); _mode<=1; {na,nb,nc,nd,ne} <= 5'b10110; {wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he}; {sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}; // i_seq <= 1'b1; i_com <= 1'b1; end else if (_mode==1) begin _mode<=2; if ({ma,mb,mc,md,me} !== 5'b10110) $stop; if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop; if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop; end else if (_mode==2) begin _mode<=3; if ({da,db,dc,dd,de} !== 5'b10110) $stop; if (o_seq_d1r !== ~i_seq) $stop; // $write("*-* All Finished *-*\n"); $finish; end if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); $stop; end end // surefire lint_off UDDSDN wire _unused_ok = |{1'b1, r_wide0, r_wide1,r_wide2,r_wide3,r_wide}; endmodule verilator-4.038/test_regress/t/t_var_bad_hide.pl0000775000177100017500000000116613702133370021745 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_pipe_filter.pl0000775000177100017500000000150113702133370021651 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010-2011 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; compile( verilator_flags2 => ['-E --pipe-filter \'perl t/t_pipe_filter.pf\' '], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, stdout_filename => $stdout_filename, ); files_identical($stdout_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_var.pl0000775000177100017500000000267413702133370021007 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["-DATTRIBUTES --exe --no-l2name $Self->{t_dir}/t_dpi_var.cpp"], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_vparam_unsup.v0000664000177100017500000000131513702133367023114 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class paramed_class_t; typedef class arg_class_t; virtual class vclass #(type CTYPE_t = arg_class_t); pure virtual function void funcname(paramed_class_t #(CTYPE_t) v); endclass class paramed_class_t #(type TYPE=int); endclass class arg_class_t; endclass module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_mem_iforder.v0000664000177100017500000000420413702133370021471 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; reg [31:0] sum; wire [15:0] out0; wire [15:0] out1; wire [15:0] inData = crc[15:0]; wire wr0a = crc[16]; wire wr0b = crc[17]; wire wr1a = crc[18]; wire wr1b = crc[19]; fifo fifo ( // Outputs .out0 (out0[15:0]), .out1 (out1[15:0]), // Inputs .clk (clk), .wr0a (wr0a), .wr0b (wr0b), .wr1a (wr1a), .wr1b (wr1b), .inData (inData[15:0])); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum); cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 32'h0; end else if (cyc>10 && cyc<90) begin sum <= {sum[30:0],sum[31]} ^ {out1, out0}; end else if (cyc==99) begin if (sum !== 32'he8bbd130) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module fifo (/*AUTOARG*/ // Outputs out0, out1, // Inputs clk, wr0a, wr0b, wr1a, wr1b, inData ); input clk; input wr0a; input wr0b; input wr1a; input wr1b; input [15:0] inData; output [15:0] out0; output [15:0] out1; reg [15:0] mem [1:0]; reg [15:0] memtemp2 [1:0]; reg [15:0] memtemp3 [1:0]; assign out0 = {mem[0] ^ memtemp2[0]}; assign out1 = {mem[1] ^ memtemp3[1]}; always @(posedge clk) begin // These mem assignments must be done in order after processing if (wr0a) begin memtemp2[0] <= inData; mem[0] <= inData; end if (wr0b) begin memtemp3[0] <= inData; mem[0] <= ~inData; end if (wr1a) begin memtemp3[1] <= inData; mem[1] <= inData; end if (wr1b) begin memtemp2[1] <= inData; mem[1] <= ~inData; end end endmodule verilator-4.038/test_regress/t/t_func_const_packed_struct_bad.pl0000775000177100017500000000107313702133370025235 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2017 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_assoc_bad.out0000664000177100017500000000105713702133370024054 0ustar wsnyderwsnyder%Error: t/t_sys_readmem_assoc_bad.v:13:24: $readmemb address/key must be integral (IEEE 1800-2017 21.4.1) : ... In instance t 13 | $readmemb("not", assoc_bad_key); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_readmem_assoc_bad.v:14:24: Unsupported: $readmemb array values must be integral : ... In instance t 14 | $readmemb("not", assoc_bad_value); | ^~~~~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_math_pow4.pl0000775000177100017500000000105313702133370021253 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_assoc.pl0000775000177100017500000000134613702133370023056 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); files_identical("$Self->{obj_dir}/t_sys_writemem_c_b.mem", "t/t_sys_readmem_assoc_c_b.out"); files_identical("$Self->{obj_dir}/t_sys_writemem_w_h.mem", "t/t_sys_readmem_assoc_w_h.out"); ok(1); 1; verilator-4.038/test_regress/t/t_select_bad_range3.out0000664000177100017500000000061113702133370023065 0ustar wsnyderwsnyder%Warning-SELRANGE: t/t_select_bad_range3.v:19:33: Selection index out of range: 13 outside 12:10 : ... In instance t 19 | assign outwires[12] = inwires[13]; | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_parent_scope_bad.pl0000775000177100017500000000120113702133370024654 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, bug1623"); scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_bad.out0000664000177100017500000000043213702133370022015 0ustar wsnyderwsnyder%Error: t/t_display_bad.v:11:7: Missing arguments for $display-like format 11 | $display("%x"); | ^~~~~~~~ %Error: t/t_display_bad.v:13:7: Unknown $display-like format code: '%q' 13 | $display("%q"); | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_twod_noinl.pl0000775000177100017500000000116013702133370023544 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_twod.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_upscope.pl0000775000177100017500000000113413702133370021660 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_dtree_inlc.pl0000775000177100017500000000123013702133370022513 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_C'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_repeat.v0000664000177100017500000000154413702133370020465 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg signed [2:0] negcnt; integer times; initial begin times = 0; repeat (1) begin repeat (0) $stop; repeat (-1) $stop; negcnt = 'sb111; // Not all commercial simulators agree on the below stopping or not // verilator lint_off WIDTH repeat (negcnt) $stop; // verilator lint_on WIDTH repeat (5) begin repeat (2) begin times = times + 1; end end end if (times != 10) $stop; // // verilator lint_off INFINITELOOP forever begin // verilator lint_on INFINITELOOP $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_case_genx_bad.out0000664000177100017500000000040613702133367022313 0ustar wsnyderwsnyder%Error: t/t_case_genx_bad.v:14:9: Use of x/? constant in generate case statement, (no such thing as 'generate casez') : ... In instance t 14 | 32'b1xxx: initial begin end | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_case_itemwidth.v0000664000177100017500000000466513702133367022213 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Some inputs we'll set to random values reg [6:0] addr; reg [6:0] e0; reg [5:0] e1; reg [5:0] e2; wire [7:0] data; reg [2:0] wrapcheck_a; reg [2:0] wrapcheck_b; test test (/*AUTOINST*/ // Outputs .data (data[7:0]), // Inputs .addr (addr[6:0]), .e0 (e0[6:0]), .e1 (e1[5:0]), .e2 (e2[5:0])); always @(/*AS*/addr) begin case(addr[2:0]) 3'd0+3'd0: wrapcheck_a = 3'h0; 3'd0+3'd1: wrapcheck_a = 3'h1; 3'd0+3'd2: wrapcheck_a = 3'h2; 3'd0+3'd3: wrapcheck_a = 3'h3; default: wrapcheck_a = 3'h4; endcase case(addr[2:0]) 3'd0+0: wrapcheck_b = 3'h0; 3'd1+1: wrapcheck_b = 3'h1; 3'd2+2: wrapcheck_b = 3'h2; 3'd3+3: wrapcheck_b = 3'h3; default: wrapcheck_b = 3'h4; endcase end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); if (cyc==1) begin addr <= 7'h28; e0 <= 7'h11; e1 <= 6'h02; e2 <= 6'h03; end if (cyc==2) begin addr <= 7'h2b; if (data != 8'h11) $stop; end if (cyc==3) begin addr <= 7'h2c; if (data != 8'h03) $stop; if (wrapcheck_a != 3'h3) $stop; if (wrapcheck_b != 3'h4) $stop; end if (cyc==4) begin addr <= 7'h0; if (data != 8'h00) $stop; if (wrapcheck_a != 3'h4) $stop; if (wrapcheck_b != 3'h2) $stop; end if (cyc==5) begin if (data != 8'h00) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule /* verilator lint_off WIDTH */ `define AI 7'h28 module test (/*AUTOARG*/ // Outputs data, // Inputs addr, e0, e1, e2 ); output [7:0] data; input [6:0] addr; input [6:0] e0; input [5:0] e1, e2; reg [7:0] data; always @(/*AS*/addr or e0 or e1 or e2) begin case (addr) `AI: data = {e0[6], 1'b0, e0[5:0]}; `AI+1: data = e1; `AI+2, `AI+3: data = e2; default: data = 0; endcase end endmodule // Local Variables: // eval:(verilog-read-defines) // verilog-auto-sense-defines-constant: t // End: verilator-4.038/test_regress/t/t_trace_scstruct.pl0000775000177100017500000000117113702133370022402 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--sc --trace --trace-structs --pins-bv 2'], ); #execute(); # didn't bother with top shell ok(1); 1; verilator-4.038/test_regress/t/t_flag_noop_bad.pl0000775000177100017500000000127013702133370022124 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); run(cmd => ["../bin/verilator", "t_flag_noop_bad.v"], fails => 1, logfile => "$Self->{obj_dir}/sim.log", expect_filename => $Self->{golden_filename}, verilator_run => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_event_control_unsup.out0000664000177100017500000000112313702133370023653 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_event_control_unsup.v:14:7: Unsupported: timing control statement in this location : ... Suggest have one timing control statement per procedure, at the top of the procedure 14 | @(clk); | ^ %Error-UNSUPPORTED: t/t_event_control_unsup.v:16:7: Unsupported: timing control statement in this location : ... Suggest have one timing control statement per procedure, at the top of the procedure 16 | @(clk); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_escape.pl0000775000177100017500000000213113702133370021457 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( # Access is so we can dump waves v_flags2 => [$Self->{vlt_all} ? '-trace' : ' +access+rwc'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); my $sig = quotemeta("bra[ket]slash/dash-colon:9"); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ $sig/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ other\.cyc /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ module mod\.with_dot /); vcd_identical ("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } ok(1); 1; verilator-4.038/test_regress/t/t_param_up_bad.out0000664000177100017500000000025113702133370022153 0ustar wsnyderwsnyder%Error: t/t_param_up_bad.v:16:19: Can't find definition of scope/variable: 'bar' 16 | assign a_bad = bar.foo; | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_func_range.pl0000775000177100017500000000105313702133370021460 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_interface_array0.pl0000775000177100017500000000105313702133370023426 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_types_bad.v0000664000177100017500000000320413702133370022022 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); // IEEE: integer_atom_type byte d_byte; shortint d_shortint; int d_int; longint d_longint; integer d_integer; time d_time; chandle d_chandle; // IEEE: integer_atom_type bit d_bit; logic d_logic; reg d_reg; bit [0:0] d_bit1; logic [0:0] d_logic1; reg [0:0] d_reg1; bit d_bitz; logic d_logicz; reg d_regz; // IEEE: non_integer_type //UNSUP shortreal d_shortreal; real d_real; realtime d_realtime; initial begin // below errors might cause spurious warnings // verilator lint_off WIDTH d_bitz[0] = 1'b1; // Illegal range d_logicz[0] = 1'b1; // Illegal range d_regz[0] = 1'b1; // Illegal range `ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now d_chandle[0] = 1'b1; // Illegal `endif d_real[0] = 1'b1; // Illegal d_realtime[0] = 1'b1; // Illegal // verilator lint_on WIDTH d_byte[0] = 1'b1; // OK d_shortint[0] = 1'b1; // OK d_int[0] = 1'b1; // OK d_longint[0] = 1'b1; // OK d_integer[0] = 1'b1; // OK d_time[0] = 1'b1; // OK d_bit1[0] = 1'b1; // OK d_logic1[0] = 1'b1; // OK d_reg1[0] = 1'b1; // OK end endmodule verilator-4.038/test_regress/t/t_tri_pullvec_bad.v0000664000177100017500000000075113702133370022342 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; tri [3:0] w; pullup p0 (w[0]); pulldown p1 (w[1]); pulldown p2 (w[2]); pullup p3 (w[3]); always_ff @ (posedge clk) begin if (w != 4'b1001) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_fuzz_eof_bad.pl0000775000177100017500000000101313702133370022002 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlt_warn_bad.vlt0000664000177100017500000000117413702133370022206 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v" lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 18 // Test wildcard filenames lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 19-19 // Test global disables lint_off -file "*/t_vlt_warn.v" -lines 20-20 coverage_off -file "t/t_vlt_warn.v" // Test --flag is also accepted tracing_off --file "t/t_vlt_warn.v" verilator-4.038/test_regress/t/t_math_signed5.pl0000775000177100017500000000105313702133370021720 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_initial_dlyass.pl0000775000177100017500000000113013702133370022355 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['-Wno-INITIALDLY'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_unsized_bad.v0000664000177100017500000000043613702133370022521 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit [256:0] num = 'd123456789123456789123456789; endmodule verilator-4.038/test_regress/t/t_param_named.v0000664000177100017500000000222513702133370021446 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; input clk; `ifdef verilator // Else it becomes a localparam, per IEEE 4.10.1, but we don't check it defparam m3.FROMDEFP = 19; `endif m3 #(.P3(PAR), .P2(2)) m3(.clk(clk)); integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module m3 #( parameter UNCH = 99, parameter P1 = 10, parameter P2 = 20, P3 = 30 ) (/*AUTOARG*/ // Inputs clk ); input clk; localparam LOC = 13; parameter FROMDEFP = 11; initial begin $display("%x %x %x",P1,P2,P3); end always @ (posedge clk) begin if (UNCH !== 99) $stop; if (P1 !== 10) $stop; if (P2 !== 2) $stop; if (P3 !== 3) $stop; `ifdef verilator if (FROMDEFP !== 19) $stop; `endif end endmodule verilator-4.038/test_regress/t/t_lint_import_name_bad.pl0000775000177100017500000000117213702133370023521 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_fuzz_triand_bad.pl0000775000177100017500000000107413702133370022521 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_array.v0000664000177100017500000000250213702133370021353 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; parameter ONE = 1; wire [17:10] bitout; reg [7:0] allbits; reg [15:0] onebit; sub sub [7:0] (allbits, onebit, bitout); integer x; always @ (posedge clk) begin //$write("%x\n", bitout); if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin allbits <= 8'hac; onebit <= 16'hc01a; end if (cyc==2) begin if (bitout !== 8'h07) $stop; allbits <= 8'hca; onebit <= 16'h1f01; end if (cyc==3) begin if (bitout !== 8'h41) $stop; if (sub[0].bitout !== 1'b1) $stop; if (sub[1].bitout !== 1'b0) $stop; `ifndef verilator // Hacky array subscripting if (sub[ONE].bitout !== 1'b0) $stop; `endif $write("*-* All Finished *-*\n"); $finish; end end end endmodule `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `endif module sub (input [7:0] allbits, input [1:0] onebit, output bitout); `INLINE_MODULE assign bitout = (^ onebit) ^ (^ allbits); endmodule verilator-4.038/test_regress/t/t_interface_gen10.v0000664000177100017500000000121613702133370022133 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); logic val; function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t(); generate begin : TestIf intf #(.PARAM(1)) my_intf [0:0] (); t1 t (.mod_intf(my_intf[0])); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_sys_file_basic.pl0000775000177100017500000000147513702133370022337 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); unlink("$Self->{obj_dir}/t_sys_file_basic_test.log"); compile( v_flags2 => ['+incdir+../include'], # Build without cached objects, see bug363 make_flags => 'VM_PARALLEL_BUILDS=0', ); execute( check_finished => 1, ); files_identical("$Self->{obj_dir}/t_sys_file_basic_test.log", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_class2.pl0000775000177100017500000000130613702133367020547 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); # #file_grep_not("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/Dead/x); ok(1); 1; verilator-4.038/test_regress/t/t_display_signed.v0000664000177100017500000000326713702133370022207 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg signed [20:0] longp; reg signed [20:0] longn; reg signed [40:0] quadp; reg signed [40:0] quadn; reg signed [80:0] widep; reg signed [80:0] widen; initial begin longp = 21'shbbccc; longn = 21'shbbccc; longn[20] = 1'b1; quadp = 41'sh1_bbbb_cccc; quadn = 41'sh1_bbbb_cccc; quadn[40] = 1'b1; widep = 81'shbc_1234_5678_1234_5678; widen = 81'shbc_1234_5678_1234_5678; widen[40] = 1'b1; // Display formatting $display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p", $time, longp, longp, longp, longp, longp, longp, longp, longp); $display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p", $time, longn, longn, longn, longn, longn, longn, longn, longn); $display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p", $time, quadp, quadp, quadp, quadp, quadp, quadp, quadp, quadp); $display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p", $time, quadn, quadn, quadn, quadn, quadn, quadn, quadn, quadn); $display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b %%p=%p %%0p=%0p", $time, widep, widep, widep, widep, widep, widep); $display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b %%p=%p %%0p=%0p", $time, widen, widen, widen, widen, widen, widen); $display; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_clk_powerdn.v0000664000177100017500000000620313702133367021517 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg reset_l; // verilator lint_off GENCLK /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) // End of automatics reg clkgate_e2r; reg clkgate_e1r_l; always @(posedge clk or negedge reset_l) begin if (!reset_l) begin clkgate_e1r_l <= ~1'b1; end else begin clkgate_e1r_l <= ~clkgate_e2r; end end reg clkgate_e1f; always @(negedge clk) begin // Yes, it's really a = clkgate_e1f = ~clkgate_e1r_l | ~reset_l; end wire clkgated = clk & clkgate_e1f; reg [31:0] countgated; always @(posedge clkgated or negedge reset_l) begin if (!reset_l) begin countgated <= 32'h1000; end else begin countgated <= countgated + 32'd1; end end reg [31:0] count; always @(posedge clk or negedge reset_l) begin if (!reset_l) begin count <= 32'h1000; end else begin count <= count + 32'd1; end end reg [7:0] cyc; initial cyc=0; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n",$time,reset_l,cyc,clkgate_e1f,count,countgated); `endif cyc <= cyc + 8'd1; case (cyc) 8'd00: begin reset_l <= ~1'b0; clkgate_e2r <= 1'b1; end 8'd01: begin reset_l <= ~1'b0; end 8'd02: begin end 8'd03: begin reset_l <= ~1'b1; // Need a posedge end 8'd04: begin end 8'd05: begin reset_l <= ~1'b0; end 8'd09: begin clkgate_e2r <= 1'b0; end 8'd11: begin clkgate_e2r <= 1'b1; end 8'd20: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase case (cyc) 8'd00: ; 8'd01: ; 8'd02: ; 8'd03: ; 8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; 8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; 8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; 8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop; 8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop; 8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop; 8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop; 8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop; 8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop; 8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop; 8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop; 8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop; 8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop; 8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop; 8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop; 8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop; 8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop; default: $stop; endcase end endmodule verilator-4.038/test_regress/t/t_flag_topmodule_inline.v0000664000177100017500000000106513702133370023542 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module a; a2 a2 (.tmp(1'b0)); initial begin $write("Bad top modules\n"); $stop; end endmodule module a2 (input tmp); l3 l3 (.tmp(tmp)); endmodule module b; l3 l3 (.tmp(1'b1)); endmodule module l3 (input tmp); initial begin if (tmp) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_param_type2.pl0000775000177100017500000000105613702133370021577 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_writemem_b.gold2.mem0000664000177100017500000000007013702133370023545 0ustar wsnyderwsnyder010000 010001 010010 010011 010100 010101 010110 010111 verilator-4.038/test_regress/t/t_select_plus_mul_pow2.pl0000775000177100017500000000105313702133370023517 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_uniqueif_fail4.pl0000775000177100017500000000142613702133370022261 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_uniqueif.v"); compile( v_flags2 => ['+define+FAILING_ASSERTION4'], verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], fails => $Self->{nc}, ); execute( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_tieout.pl0000775000177100017500000000105313702133370021532 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_wwarn_bad.pl0000775000177100017500000000123013702133370022303 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_werror.v"); lint( fails => 1, verilator_flags => [qw(-cc -Wwarn-NOSUCHERRORASTHIS)], expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_genblk.v0000664000177100017500000000247013702133370021277 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, reset_l ); input clk; input reset_l; generate show #(`__LINE__, "top.t.show0") show0(); if (0) ; else if (0) ; else if (1) show #(`__LINE__, "top.t.genblk1.show1") show1(); if (0) begin end else if (0) begin end else if (1) begin show #(`__LINE__, "top.t.genblk2.show2") show2(); end if (0) ; else begin if (0) begin end else if (1) begin show #(`__LINE__, "top.t.genblk3.genblk1.show3") show3(); end end if (0) ; else begin : x1 if (0) begin : x2 end else if (1) begin : x3 show #(`__LINE__, "top.t.x1.x3.show4") show4(); end end endgenerate int cyc; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module show #(parameter LINE=0, parameter string EXPT) (); always @ (posedge t.clk) begin if (t.cyc == LINE) begin $display("%03d: exp=%s got=%m", LINE, EXPT); end end endmodule verilator-4.038/test_regress/t/t_tri_select.cpp0000664000177100017500000000365013702133370021657 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_select.h" Vt_tri_select* tb = NULL; double sc_time_stamp() { return 0; } bool check() { bool pass = true; #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif int Y = ((tb->OE1) & (!tb->OE2)) ? tb->A1 : ((!tb->OE1) & (tb->OE2)) ? tb->A2 : ((tb->OE1) & (tb->OE2)) ? (tb->A1 | tb->A2) : 3; // pullup int W = (((tb->OE2) ? (tb->A2 & 0x1) : 0) << tb->A1) | (((tb->OE1) ? (tb->A2 >> 1) & 0x1 : 0) << tb->A2); if (tb->Y1 == Y && tb->Y2 == Y && tb->Y3 == Y && tb->W == W) { pass = true; if (verbose) printf("- pass: "); } else { pass = false; verbose = true; printf("%%E-Fail: "); } if (verbose) printf("Read: OE1=%d OE2=%d A1=0x%x A2=0x%x Y1=0x%x Y2=0x%x Y3=0x%x W=0x%x Expected: " "Y1=Y2=Y3=%d and W=0x%x\n", tb->OE1, tb->OE2, tb->A1, tb->A2, tb->Y1, tb->Y2, tb->Y3, tb->W, Y, W); return pass; } int main() { bool pass = true; Verilated::debug(0); tb = new Vt_tri_select("tb"); // loop through every possibility and check the result for (tb->OE1 = 0; tb->OE1 < 2; tb->OE1++) { for (tb->OE2 = 0; tb->OE2 < 2; tb->OE2++) { for (tb->A1 = 0; tb->A1 < 4; tb->A1++) { for (tb->A2 = 0; tb->A2 < 4; tb->A2++) { tb->eval(); if (!check()) { pass = false; } } } } } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from t_tri_select\n"); } return 0; } verilator-4.038/test_regress/t/t_clk_concat2.pl0000775000177100017500000000106013702133367021537 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_dotted_inl2.vlt0000664000177100017500000000047013702133370022764 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config inline -module "global_mod" inline -module "ma" no_inline -module "mb" inline -module "mc" verilator-4.038/test_regress/t/t_queue.pl0000775000177100017500000000105313702133370020475 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_file_basic_uz.out0000664000177100017500000004200013702133370023233 0ustar wsnyderwsnyder00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 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verilator-4.038/test_regress/t/t_dpi_name_bad.v0000664000177100017500000000075213702133370021567 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); // Can't handle logic (yet?) import "DPI-C" function int \badly.named (int i); initial begin $stop; end endmodule verilator-4.038/test_regress/t/t_gen_div0.v0000664000177100017500000000137313702133370020700 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOINST*/); Test #( .BIT_WIDTH (72), .BYTE_WIDTH (9) ) u_test_inst(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module Test (); parameter BIT_WIDTH = ""; parameter BYTE_WIDTH = ""; localparam BYTES = BIT_WIDTH / BYTE_WIDTH; wire [BYTES - 1:0] i; wire [BYTES - 1:0] o; genvar g; generate for (g = 0; g < BYTES; g = g + 1) begin: gen assign o[g] = (i[g] !== 1'b0); end endgenerate endmodule verilator-4.038/test_regress/t/t_inst_implicit.pl0000775000177100017500000000105313702133370022220 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_event_copy.v0000664000177100017500000001002313702133370021350 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif module t(/*AUTOARG*/ // Inputs clk ); input clk; event e1; event e2; event e3; event e4; `ifndef IVERILOG event ev [3:0]; `endif int cyc; int last_event; always @(e1) begin `WRITE_VERBOSE(("[%0t] e1\n", $time)); `ifndef IVERILOG if (!e1.triggered) $stop; `endif last_event[1] = 1; end always @(e2) begin `WRITE_VERBOSE(("[%0t] e2\n", $time)); last_event[2] = 1; end always @(e3) begin `WRITE_VERBOSE(("[%0t] e3\n", $time)); last_event[3] = 1; end always @(e4) begin `WRITE_VERBOSE(("[%0t] e4\n", $time)); last_event[4] = 1; end always @(posedge clk) begin `WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event)); cyc <= cyc + 1; if (cyc == 1) begin // Check no initial trigger if (last_event != 0) $stop; end // else if (cyc == 10) begin last_event = 0; -> e1; end else if (cyc == 12) begin if (last_event != 32'b10) $stop; last_event = 0; end else if (cyc == 13) begin // Check not still triggering if (last_event != 0) $stop; last_event = 0; end // else if (cyc == 20) begin last_event = 0; `ifdef IVERILOG -> e2; `else // Events are both references and events themselves. I.e. 'event e' // declaration means 'event e = new'. Then e is a reference to that // created event. // // Always having indirection is bad for performance, so Verilator // should have 'event e' as an "EVENTVALUE" stored as a char, or // ideally a one bit field reference (not vector as that can't be // V3Ordered). // // Then events once copied become EVENTREFs, much like a ClassRef which // points to an EVENTVALUE. Thus a Verilog "event" starts as an // EVENTVALUE, and if an assignment is made it becomes an EVENTVALUE // and an EVENTREF initing to that EVENTVALUE. // // All static scheduling for events would go out the window once an // event can be pointed to by an EVENTREF, as basically any EVENTREF // activation could be activating any event. A graph algorithm could // determine what events/eventrefs are associated and only // pessamistically schedule those events (users of EVENTVALUES) that // are ever pointed to by an EVENTREF. e4 = e3; // Old handle to e4 e3 = e2; // Same event, also triggers e2 // IEEE 2017 15.5.5.1 says that this causes a merge, and the below // should also activate the "old e3". However we could not find any // simulator that actually does this. Instead the "old e3" becomes // unreachable (via old handle), but is reachable by "e4" as assigned // earlier. ->> e3; // Delayed `endif end else if (cyc == 22) begin if (last_event != 32'b100) $stop; last_event = 0; -> e2; // IEEE says triggers e3, but does not end else if (cyc == 24) begin if (last_event != 32'b100) $stop; last_event = 0; -> e4; // Triggers old e3 end else if (cyc == 26) begin if (last_event != 32'b1000) $stop; last_event = 0; end // else if (cyc == 30) begin last_event = 0; `ifndef IVERILOG e3 = null; -> e3; // Triggers nothing `endif end else if (cyc == 32) begin if (last_event != 0) $stop; last_event = 0; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_interface_modport.pl0000775000177100017500000000106013702133370023053 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_open_c.cpp0000664000177100017500000002557713702133370021635 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_open__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS // #elif defined(MS) // # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern void dpii_unused(const svOpenArrayHandle u); extern void dpii_open_p0_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_bit(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_byte(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_int(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_integer(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_logic(const svOpenArrayHandle i, const svOpenArrayHandle o); extern int dpii_failure(); } #endif //====================================================================== // Untested: // void *svGetArrElemPtr(const svOpenArrayHandle, int indx1, ...); // void svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1, ...); // void svPutBitArrElem1VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1); // void svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1, ...); // void svPutLogicArrElem1VecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1); // void svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1, ...); // void svGetBitArrElem1VecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1); // void svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, ...); // void svGetLogicArrElem1VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1); // svBit svGetBitArrElem(const svOpenArrayHandle s, int indx1, ...); // svBit svGetBitArrElem1(const svOpenArrayHandle s, int indx1); // svLogic svGetLogicArrElem(const svOpenArrayHandle s, int indx1, ...); // svLogic svGetLogicArrElem1(const svOpenArrayHandle s, int indx1); // void svPutBitArrElem(const svOpenArrayHandle d, svBit value, int indx1, ...); // void svPutBitArrElem1(const svOpenArrayHandle d, svBit value, int indx1); // void svPutLogicArrElem(const svOpenArrayHandle d, svLogic value, int indx1, ...); // void svPutLogicArrElem1(const svOpenArrayHandle d, svLogic value, int indx1); //====================================================================== int failure = 0; int dpii_failure() { return failure; } #ifdef _WIN32 # define T_PRI64 "I64" #else // Linux or compliant Unix flavors # define T_PRI64 "ll" #endif #define CHECK_RESULT_HEX(got, exp) \ do { \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << std::hex \ << ": GOT=" << (got) << " EXP=" << (exp) << std::endl; \ failure = __LINE__; \ } \ } while (0) #define CHECK_RESULT_HEX_NE(got, exp) \ do { \ if ((got) == (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << std::hex \ << ": GOT=" << (got) << " EXP!=" << (exp) << std::endl; \ failure = __LINE__; \ } \ } while (0) void dpii_unused(const svOpenArrayHandle u) {} void _dpii_all(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { #ifdef TEST_VERBOSE printf("-:%s:%d: For case c=%d p=%d u=%d data=%p\n", __FILE__, __LINE__, c, p, u, svGetArrayPtr(i)); #endif (void)svGetArrayPtr(i); #ifndef NC // NC always returns zero and warns (void)svSizeOfArray(i); #endif #ifndef VCS // VCS does not support dimension 0 query if (p) { int d = 0; if (c == 0 || c == 1) { CHECK_RESULT_HEX(svLeft(i, d), 1); CHECK_RESULT_HEX(svRight(i, d), -1); CHECK_RESULT_HEX(svLow(i, d), -1); CHECK_RESULT_HEX(svHigh(i, d), 1); // CHECK_RESULT_HEX(svIncrement(i, d), 0); CHECK_RESULT_HEX(svSize(i, d), 3); } else if (c == 2) { CHECK_RESULT_HEX(svLeft(i, d), 95); CHECK_RESULT_HEX(svRight(i, d), 1); CHECK_RESULT_HEX(svLow(i, d), 1); CHECK_RESULT_HEX(svHigh(i, d), 95); // CHECK_RESULT_HEX(svIncrement(i, d), 0); CHECK_RESULT_HEX(svSize(i, d), 95); } else { CHECK_RESULT_HEX(0, 1); } } #endif if (u >= 1) { int d = 1; if (c == 0) { CHECK_RESULT_HEX(svLeft(i, d), -2); CHECK_RESULT_HEX(svRight(i, d), 2); CHECK_RESULT_HEX(svLow(i, d), -2); CHECK_RESULT_HEX(svHigh(i, d), 2); // CHECK_RESULT_HEX(svIncrement(i, d), 0); CHECK_RESULT_HEX(svSize(i, d), 5); } else if (c == 1) { CHECK_RESULT_HEX(svLeft(i, d), 2); CHECK_RESULT_HEX(svRight(i, d), -2); CHECK_RESULT_HEX(svLow(i, d), -2); CHECK_RESULT_HEX(svHigh(i, d), 2); // CHECK_RESULT_HEX(svIncrement(i, d), 0); CHECK_RESULT_HEX(svSize(i, d), 5); } } if (u >= 2) { int d = 2; if (c == 0) { CHECK_RESULT_HEX(svLeft(i, d), -3); CHECK_RESULT_HEX(svRight(i, d), 3); CHECK_RESULT_HEX(svLow(i, d), -3); CHECK_RESULT_HEX(svHigh(i, d), 3); // CHECK_RESULT_HEX(svIncrement(i, d), 0); CHECK_RESULT_HEX(svSize(i, d), 7); } else if (c == 1) { CHECK_RESULT_HEX(svLeft(i, d), 3); CHECK_RESULT_HEX(svRight(i, d), -3); CHECK_RESULT_HEX(svLow(i, d), -3); CHECK_RESULT_HEX(svHigh(i, d), 3); // CHECK_RESULT_HEX(svIncrement(i, d), 0); CHECK_RESULT_HEX(svSize(i, d), 7); } } if (c == 2 && p == 1 && u == 3) { for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { for (int b = svLow(i, 2); b <= svHigh(i, 2); ++b) { for (int c = svLow(i, 3); c <= svHigh(i, 3); ++c) { // printf("Copy abc %d,%d,%d\n", a,b,c); svLogicVecVal vec[3]; svGetLogicArrElemVecVal(vec, i, a, b, c); #ifdef NC // printf(" %08lx_%08lx_%08lx\n", vec[2].a, vec[1].a, vec[0].a); vec[0].a = (~vec[0].a); vec[1].a = (~vec[1].a); vec[2].a = (~vec[2].a) & 0x7fffffff; // vec[0].b = vec[0].b; // vec[1].b = vec[1].b; // vec[2].b = vec[2].b; #else vec[0].aval = (~vec[0].aval); vec[1].aval = (~vec[1].aval); vec[2].aval = (~vec[2].aval) & 0x7fffffff; // vec[0].bval = vec[0].bval; // vec[1].bval = vec[1].bval; // vec[2].bval = vec[2].bval; #endif svPutLogicArrElemVecVal(o, vec, a, b, c); } } } } } void dpii_open_p0_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_bit(const svOpenArrayHandle i, const svOpenArrayHandle o) {} void dpii_open_byte(const svOpenArrayHandle i, const svOpenArrayHandle o) { intptr_t arrPtr = (intptr_t)svGetArrayPtr(i); CHECK_RESULT_HEX_NE(arrPtr, 0); // All the arrays should actually exist #ifndef NC // NC always returns zero and warns int sizeInputOfArray = svSizeOfArray(i); CHECK_RESULT_HEX_NE(sizeInputOfArray, 0); // None of the test cases have zero size CHECK_RESULT_HEX_NE(svDimensions(i), 0); // All the test cases are unpacked arrays #endif } void dpii_open_int(const svOpenArrayHandle i, const svOpenArrayHandle o) { intptr_t arrPtr = (intptr_t)svGetArrayPtr(i); CHECK_RESULT_HEX_NE(arrPtr, 0); // All the arrays should actually exist #ifndef NC // NC always returns zero and warns int sizeInputOfArray = svSizeOfArray(i); CHECK_RESULT_HEX_NE(sizeInputOfArray, 0); // None of the test cases have zero size CHECK_RESULT_HEX_NE(svDimensions(i), 0); // All the test cases are unpacked arrays #endif } void dpii_open_integer(const svOpenArrayHandle i, const svOpenArrayHandle o) {} void dpii_open_logic(const svOpenArrayHandle i, const svOpenArrayHandle o) {} int dpii_failed() { return failure; } verilator-4.038/test_regress/t/t_func_graphcirc.v0000664000177100017500000000206113702133370022155 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer cyc; initial cyc=0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin ReadContDisps; end else if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end `ifndef verilator DispContDisps; `endif end task ReadContDisps; begin $display("%m: Here: %d", cyc); end endtask integer dindex; task DispContDisps; /* verilator public */ begin if (cyc >= 2) begin if ( cyc >= 4 ) begin dindex = dindex + 2; //*** Error line $display("%m: DIndex increment %d", cyc); `ifdef VERILATOR $c("VL_PRINTF(\"Hello1?\\n\");"); `endif end `ifdef VERILATOR $c("VL_PRINTF(\"Hello2?\\n\");"); $c("VL_PRINTF(\"Hello3?\\n\");"); `endif end end endtask endmodule verilator-4.038/test_regress/t/t_param_in_func_bad.pl0000775000177100017500000000107413702133370022763 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_graphcirc.pl0000775000177100017500000000105313702133370022326 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex.pl0000775000177100017500000000233013702133370022175 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['--cc --trace'], ); execute( check_finished => 1, ); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_strp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_arrp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arrp_strp /); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arru\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_arrp\(/); file_grep ("$Self->{obj_dir}/simx.vcd", qr/ v_arru_strp\(/); vcd_identical ("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_lint_implicit_bad.out0000664000177100017500000000171713702133370023217 0ustar wsnyderwsnyder%Warning-IMPLICIT: t/t_lint_implicit.v:11:11: Signal definition not found, creating implicitly: 'b' 11 | assign b = 1'b1; | ^ ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Warning-IMPLICIT: t/t_lint_implicit.v:13:14: Signal definition not found, creating implicitly: 'nt0' 13 | or OR0 (nt0, a, b); | ^~~ %Warning-IMPLICIT: t/t_lint_implicit.v:16:12: Signal definition not found, creating implicitly: 'dummy1' : ... Suggested alternative: 'dummy_ip' 16 | assign {dummy1, dummy2} = dummy_ip; | ^~~~~~ %Warning-IMPLICIT: t/t_lint_implicit.v:16:20: Signal definition not found, creating implicitly: 'dummy2' : ... Suggested alternative: 'dummy1' 16 | assign {dummy1, dummy2} = dummy_ip; | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_param_in_func_bad.v0000664000177100017500000000125213702133370022610 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [7:0] digit = getDigit(4'd1); initial begin if (digit != "1") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule function automatic logic[7:0] getDigit(logic[3:0] d); localparam logic[7:0] digits[10] = '{ "0", "1", "2", "3", "4", "5", "6", "7", "8", "9" }; return digits[d]; endfunction verilator-4.038/test_regress/t/t_preproc_noline.pl0000775000177100017500000000150013702133370022364 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; top_filename("t/t_preproc_noline.v"); compile( verilator_flags2 => ['-E -P'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, stdout_filename => $stdout_filename, ); files_identical($stdout_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_mailbox.pl0000775000177100017500000000117613702133370021012 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_unopt_converge_ndbg_bad.out0000664000177100017500000000011413702133370024374 0ustar wsnyderwsnyder%Error: t/t_unopt_converge.v:7: Verilated model didn't converge Aborting... verilator-4.038/test_regress/t/t_lint_unused_iface.v0000664000177100017500000000203413702133370022660 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic signal; modport slave ( input signal ); modport master ( output signal ); endinterface: dummy_if module sub ( input wire signal_i, output wire signal_o, dummy_if.master dummy_in, dummy_if.slave dummy_out ); assign dummy_in.signal = signal_i; assign signal_o = dummy_out.signal; endmodule module t (/*AUTOARG*/ // Outputs signal_o, // Inputs signal_i ); input signal_i; output signal_o; // verila tor lint_off UUSD // verila tor lint_off UNDRIVEN dummy_if dummy_if (); // verila tor lint_on UUSD // verila tor lint_on UNDRIVEN dummy_if uusd_if (); sub sub ( .signal_i(signal_i), .signal_o(signal_o), .dummy_in(dummy_if), .dummy_out(dummy_if) ); endmodule verilator-4.038/test_regress/t/t_tri_compass_bad.pl0000775000177100017500000000107113702133370022502 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( expect_filename => $Self->{golden_filename}, fails => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_func.pl0000775000177100017500000000100113702133370021455 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_class_new_bad.pl0000775000177100017500000000107413702133367022146 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_setout_bad.pl0000775000177100017500000000107413702133370022533 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_pp_defparen_bad.pl0000775000177100017500000000114113702133370022440 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["-Wpedantic"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_timescale_default.v0000664000177100017500000000071513702133370022656 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Intentionally no timescale here, nor in driver file module t; initial begin // Unspecified, but general consensus is 1s is default timeunit $printtimescale; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_prot_lib_secret.v0000664000177100017500000000447613702133370022373 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module secret #(parameter GATED_CLK = 0) ( input [31:0] accum_in, output wire [31:0] accum_out, input accum_bypass, output [31:0] accum_bypass_out, input s1_in, output logic s1_out, input [1:0] s2_in, output logic [1:0] s2_out, input [7:0] s8_in, output logic [7:0] s8_out, input [32:0] s33_in, output logic [32:0] s33_out, input [63:0] s64_in, output logic [63:0] s64_out, input [64:0] s65_in, output logic [64:0] s65_out, input [128:0] s129_in, output logic [128:0] s129_out, input [3:0] [31:0] s4x32_in, output logic [3:0] [31:0] s4x32_out, input clk_en, input clk /*verilator clocker*/); logic [31:0] secret_accum_q = 0; logic [31:0] secret_value = 7; initial $display("created %m"); logic the_clk; generate if (GATED_CLK != 0) begin: yes_gated_clock logic clk_en_latch /*verilator clock_enable*/; /* verilator lint_off COMBDLY */ always_comb if (clk == '0) clk_en_latch <= clk_en; /* verilator lint_on COMBDLY */ assign the_clk = clk & clk_en_latch; end else begin: no_gated_clock assign the_clk = clk; end endgenerate always @(posedge the_clk) begin secret_accum_q <= secret_accum_q + accum_in + secret_value; end // Test combinatorial paths of different sizes always @(*) begin s1_out = s1_in; s2_out = s2_in; s8_out = s8_in; s64_out = s64_in; s65_out = s65_in; s129_out = s129_in; s4x32_out = s4x32_in; end sub sub (.sub_in(s33_in), .sub_out(s33_out)); // Test sequential path assign accum_out = secret_accum_q; // Test mixed combinatorial/sequential path assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q; final $display("destroying %m"); endmodule module sub ( input [32:0] sub_in, output [32:0] sub_out); /*verilator no_inline_module*/ assign sub_out = sub_in; endmodule verilator-4.038/test_regress/t/t_param_avec.pl0000775000177100017500000000123613702133370021452 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, # Verilator unsupported, bug477 expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_type.v0000664000177100017500000000070313702133370020162 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); real x; real y; var type(x+y) z; initial begin x = 1.2; y = 2.3; z = x + y; if (z != (1.2+2.3)) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_clk_vecgen3.pl0000775000177100017500000000116513702133367021546 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_clk_vecgen1.v"); compile( v_flags2 => ['+define+T_TEST3',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_embed1_wrap.v0000664000177100017500000000470513702133370021375 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_embed1_wrap (/*AUTOARG*/ // Outputs bit_out, vec_out, wide_out, did_init_out, // Inputs clk, bit_in, vec_in, wide_in, is_ref ); /*AUTOINOUTMODULE("t_embed1_child")*/ // Beginning of automatic in/out/inouts (from specific module) output bit bit_out; output bit [30:0] vec_out; output bit [123:0] wide_out; output bit did_init_out; input clk; input bit_in; input [30:0] vec_in; input [123:0] wide_in; input is_ref; // End of automatics `ifdef verilator // Import $t_embed_child__initial etc as a DPI function `endif //TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this import "DPI-C" context function void t_embed_child_initial(); import "DPI-C" context function void t_embed_child_final(); import "DPI-C" context function void t_embed_child_eval(); import "DPI-C" context function void t_embed_child_io_eval ( //TODO we support bit, but not logic input bit clk, input bit bit_in, input bit [30:0] vec_in, input bit [123:0] wide_in, input bit is_ref, output bit bit_out, output bit [30:0] vec_out, output bit [123:0] wide_out, output bit did_init_out); initial begin // Load all values t_embed_child_initial(); end // Only if system verilog, and if a "final" block in the code final begin t_embed_child_final(); end bit _temp_bit_out; bit _temp_did_init_out; bit [30:0] _temp_vec_out; bit [123:0] _temp_wide_out; always @* begin t_embed_child_io_eval( clk, bit_in, vec_in, wide_in, is_ref, _temp_bit_out, _temp_vec_out, _temp_wide_out, _temp_did_init_out ); // TODO might eliminate these temporaries bit_out = _temp_bit_out; did_init_out = _temp_did_init_out; end // Send all variables every cycle, // or have a sensitivity routine for each? // How to make sure we call eval at end of variable changes? // #0 (though not verilator compatible!) // TODO for now, we know what changes when always @ (posedge clk) begin vec_out <= _temp_vec_out; wide_out <= _temp_wide_out; end endmodule verilator-4.038/test_regress/t/t_assert_question.v0000664000177100017500000000146513702133367022445 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dout, // Inputs clk, sel, a, c ); input clk; input bit [3:0] sel; input bit [3:0] a; input bit c; output bit dout; localparam logic DC = 1'b?; always_ff @(posedge clk) begin unique casez(sel) 4'b0000: dout <= a[0]; 4'b001?: dout <= a[1]; {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; default: dout <= '0; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_vams_basic.pl0000775000177100017500000000105313702133370021460 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_outp.v0000664000177100017500000000322313702133370021203 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [7:0] a,b; wire [7:0] z; mytop u0 ( a, b, clk, z ); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x\n", cyc, z); if (cyc==1) begin a <= 8'h07; b <= 8'h20; end if (cyc==2) begin a <= 8'h8a; b <= 8'h12; end if (cyc==3) begin if (z !== 8'hdf) $stop; a <= 8'h71; b <= 8'hb2; end if (cyc==4) begin if (z !== 8'hed) $stop; end if (cyc==5) begin if (z !== 8'h4d) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule // mytop module inv( input [ 7:0 ] a, output wire [ 7:0 ] z ); assign z = ~a; endmodule module ftest( input [ 7:0 ] a, b, // Test legal syntax input clk, output reg [ 7:0 ] z ); wire [7:0] zi; inv u1 (.a(myadd(a,b)), .z(zi)); always @ ( posedge clk ) begin z <= myadd( a, zi ); end function [ 7:0 ] myadd; input [7:0] ina; input [7:0] inb; begin myadd = ina + inb; end endfunction // myadd endmodule // ftest module mytop ( input [ 7:0 ] a, b, input clk, output [ 7:0 ] z ); ftest u0( a, b, clk, z ); endmodule // mytop verilator-4.038/test_regress/t/t_param_bracket.pl0000775000177100017500000000077313702133370022154 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( ); ok(1); 1; verilator-4.038/test_regress/t/t_func_const_bad.pl0000775000177100017500000000107413702133370022323 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_array_bad.pl0000775000177100017500000000110113702133370022324 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_bad_digit.out0000664000177100017500000000014513702133370024041 0ustar wsnyderwsnyder%Error: t/t_sys_readmem_bad_digit.mem:8: $readmemb (binary) file contains hex characters Aborting... verilator-4.038/test_regress/t/t_fuzz_genintf_bad.v0000664000177100017500000000072513702133370022523 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1588 interface intf; logic a; modport source(output a); endinterface module m1 ( input logic value, intf.source b ); endmodule module t; intf ifs; m1 m0( j.e(0), .b(ifs) ); genvar j; endmodule verilator-4.038/test_regress/t/t_udp_bad.v0000664000177100017500000000067413702133370020606 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); wire a, b; udp_x x (a, b); endmodule primitive udp_x (a_bad, b, c_bad); tri a_bad; output b; output c_bad; table //a b 0 : 1; 1 : 0; endtable endprimitive verilator-4.038/test_regress/t/t_var_pins_sc_uint_biguint.pl0000775000177100017500000000475213702133370024450 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_var_pinsizes.v"); compile( verilator_flags2 => ["-sc --pins-sc-uint --pins-sc-biguint --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp"], make_main => 0, ); { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i128;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i513;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o128;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o513;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16;/x); } execute(); ok(1); 1; verilator-4.038/test_regress/t/t_unconnected_bad.pl0000775000177100017500000000107413702133370022467 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_pins_sc1.pl0000775000177100017500000000500013702133370021734 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_var_pinsizes.v"); compile( verilator_flags2 => ["-sc -pins-bv 1 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], make_main => 0, ); if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16_vlt;/x); } execute(); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_comments.out0000664000177100017500000004614513702133370023134 0ustar wsnyderwsnyder`line 1 "t/t_preproc.v" 1 // DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc.v" 0 //=========================================================================== // Includes `line 8 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc2.vh" 0 // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 At file "t/t_preproc_inc2.vh" line 5 `line 7 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 `line 2 "inc3_a_filename_from_line_directive" 0 // DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line 7 "inc3_a_filename_from_line_directive" 0 // FOO At file "inc3_a_filename_from_line_directive" line 11 `line 13 "inc3_a_filename_from_line_directive" 0 // guard `line 16 "inc3_a_filename_from_line_directive" 0 `line 20 "inc3_a_filename_from_line_directive" 2 `line 7 "t/t_preproc_inc2.vh" 0 `line 9 "t/t_preproc_inc2.vh" 2 `line 8 "t/t_preproc.v" 0 `line 10 "t/t_preproc.v" 0 //=========================================================================== // Comments `line 13 "t/t_preproc.v" 0 /* verilator pass_thru comment */ `line 15 "t/t_preproc.v" 0 // verilator pass_thru_comment2 `line 17 "t/t_preproc.v" 0 //=========================================================================== // Defines `line 20 "t/t_preproc.v" 0 // DEF_A0 set by command line wire [3:0] q = { 1'b1 , 1'b0 , 1'b1 , 1'b1 }; `line 30 "t/t_preproc.v" 0 text. `line 32 "t/t_preproc.v" 0 foo /*this */ bar /* this too */ foobar2 // but not `line 37 "t/t_preproc.v" 0 `line 41 "t/t_preproc.v" 0 `line 46 "t/t_preproc.v" 0 /*******COMMENT*****/ first part `line 47 "t/t_preproc.v" 0 second part `line 47 "t/t_preproc.v" 0 third part { `line 48 "t/t_preproc.v" 0 a, `line 48 "t/t_preproc.v" 0 b, `line 48 "t/t_preproc.v" 0 c} Line_Preproc_Check 49 `line 51 "t/t_preproc.v" 0 //=========================================================================== `line 53 "t/t_preproc.v" 0 `line 55 "t/t_preproc.v" 0 deep deep `line 59 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" `line 64 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s `line 70 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line `line 72 "t/t_preproc.v" 0 x y LLZZ "x" y // Simulators disagree here; some substitute "a" others do not `line 75 "t/t_preproc.v" 0 (a,b)(a,b) `line 78 "t/t_preproc.v" 0 $display("left side: \"right side\"") `line 81 "t/t_preproc.v" 0 bar_suffix more `line 84 "t/t_preproc.v" 0 `line 86 "t/t_preproc.v" 0 $c("Zap(\"",bug1,"\");");; `line 87 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; `line 89 "t/t_preproc.v" 0 /* Define inside comment: `DEEPER and `WITHTICK */ // More commentary: `zap(bug1); `zap("bug2"); `line 92 "t/t_preproc.v" 0 //====================================================================== // display passthru `line 95 "t/t_preproc.v" 0 initial begin //$display(`msg( \`, \`)); // Illegal $display("pre thrupre thrumid thrupost post: \"right side\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("left_side: \"right_side\""); $display("na: \"right_side\""); $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); $display("na: \"nana\""); $display("left_side right_side // Doesn't expand: \"left_side right_side // Doesn't expand\""); // Results vary between simulators $display(": \"\""); // Empty $display("left side: \"right side\""); $display("left side: \"right side\""); $display("standalone"); `line 116 "t/t_preproc.v" 0 // Unspecified when the stringification has multiple lines $display("twoline: \"first second\""); //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. $write("*-* All Finished *-*\n"); $finish; end endmodule `line 126 "t/t_preproc.v" 0 //====================================================================== // rt.cpan.org bug34429 `line 129 "t/t_preproc.v" 0 `line 134 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); `line 135 "t/t_preproc.v" 0 wire tmp_d1 = d1; `line 135 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; `line 135 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; // expansion is OK endmodule module add2 ( input wire d2, output wire o2); `line 138 "t/t_preproc.v" 0 wire tmp_d2 = d2; `line 138 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; `line 138 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; // expansion is bad endmodule `line 141 "t/t_preproc.v" 0 `line 147 "t/t_preproc.v" 0 // parameterized macro with arguments that are macros `line 152 "t/t_preproc.v" 0 `line 152 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin `line 152 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; `line 152 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; `line 152 "t/t_preproc.v" 0 end endgenerate // ignorecmt `line 154 "t/t_preproc.v" 0 //====================================================================== // Quotes are legal in protected blocks. Grr. module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `line 160 "t/t_preproc.v" 0 `endprotected endmodule //" `line 164 "t/t_preproc.v" 0 //====================================================================== // macro call with define that has comma `line 174 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 178 "t/t_preproc.v" 0 //====================================================================== // include of parameterized file `line 181 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 2 `line 181 "t/t_preproc.v" 0 `line 182 "t/t_preproc.v" 0 `line 185 "t/t_preproc.v" 0 `line 187 "t/t_preproc.v" 0 `line 191 "t/t_preproc.v" 0 //====================================================================== // macro call with , in {} `line 194 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); `line 200 "t/t_preproc.v" 0 //====================================================================== // pragma/default net type `line 203 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire `line 207 "t/t_preproc.v" 0 //====================================================================== // Ifdef `line 210 "t/t_preproc.v" 0 `line 214 "t/t_preproc.v" 0 Line_Preproc_Check 214 `line 216 "t/t_preproc.v" 0 //====================================================================== // bug84 `line 219 "t/t_preproc.v" 0 // Hello, comments MIGHT not be legal /*more,,)cmts*/ // But newlines ARE legal... who speced THAT? (p,q) `line 226 "t/t_preproc.v" 0 (//Here x,y //Too) Line_Preproc_Check 227 `line 229 "t/t_preproc.v" 0 //====================================================================== // defines split arguments `line 232 "t/t_preproc.v" 0 beginend // 2001 spec doesn't require two tokens, so "beginend" ok beginend // 2001 spec doesn't require two tokens, so "beginend" ok "beginend" // No space "beginend" `line 240 "t/t_preproc.v" 0 //====================================================================== // bug106 `\esc`def `line 246 "t/t_preproc.v" 0 Not a \`define `line 248 "t/t_preproc.v" 0 //====================================================================== // misparsed comma in submacro x,y)--bee submacro has comma paren `line 256 "t/t_preproc.v" 0 //====================================================================== // bug191 $display("10 %d %d", $bits(foo), 10); `line 261 "t/t_preproc.v" 0 //====================================================================== // 1800-2009 `line 266 "t/t_preproc.v" 0 `line 269 "t/t_preproc.v" 0 //====================================================================== // bug202 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 `line 283 "t/t_preproc.v" 0 assign a3 = ~b3 ; `line 283 "t/t_preproc.v" 0 `line 285 "t/t_preproc.v" 0 /* multi \ line1*/ \ `line 287 "t/t_preproc.v" 0 /*multi \ line2*/ `line 294 "t/t_preproc.v" 0 `line 294 "t/t_preproc.v" 0 `line 294 "t/t_preproc.v" 0 /* multi line 3*/ `line 294 "t/t_preproc.v" 0 def i `line 296 "t/t_preproc.v" 0 //====================================================================== `line 298 "t/t_preproc.v" 0 `line 302 "t/t_preproc.v" 0 `line 308 "t/t_preproc.v" 0 1 // verilator NOT IN DEFINE (nodef) 2 /* verilator PART OF DEFINE */ (hasdef) 3 `line 310 "t/t_preproc.v" 0 /* verilator NOT PART OF DEFINE */ (nodef) `line 311 "t/t_preproc.v" 0 4 `line 311 "t/t_preproc.v" 0 /* verilator PART OF DEFINE */ (nodef) `line 312 "t/t_preproc.v" 0 5 also in `line 312 "t/t_preproc.v" 0 also3 // CMT NOT (nodef) HAS a NEW `line 315 "t/t_preproc.v" 0 LINE `line 317 "t/t_preproc.v" 0 //====================================================================== `line 319 "t/t_preproc.v" 0 `line 332 "t/t_preproc.v" 0 `line 335 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen "clxx_scen" EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `line 341 "t/t_preproc.v" 0 do `line 341 "t/t_preproc.v" 0 /* synopsys translate_off */ `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 if (start("t/t_preproc.v", 341)) begin `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); `line 341 "t/t_preproc.v" 0 end `line 341 "t/t_preproc.v" 0 /* synopsys translate_on */ `line 341 "t/t_preproc.v" 0 while(0); `line 343 "t/t_preproc.v" 0 //====================================================================== `line 345 "t/t_preproc.v" 0 `line 349 "t/t_preproc.v" 0 `line 349 "t/t_preproc.v" 0 `line 350 "t/t_preproc.v" 0 //`ifndef def_fooed_2 `error "No def_fooed_2" `endif EXP: This is fooed This is fooed EXP: This is fooed_2 This is fooed_2 `line 357 "t/t_preproc.v" 0 //====================================================================== np np //====================================================================== // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? `line 368 "t/t_preproc.v" 0 `line 371 "t/t_preproc.v" 0 //====================================================================== // Metaprogramming `line 379 "t/t_preproc.v" 0 `line 383 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 //====================================================================== // Include from stringification `line 389 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 2 `line 389 "t/t_preproc.v" 0 `line 390 "t/t_preproc.v" 0 //====================================================================== // Defines doing defines // Note the newline on the end - required to form the end of a define `line 398 "t/t_preproc.v" 0 Line_Preproc_Check 402 //====================================================================== // Quoted multiline - track line numbers, and ensure \\n gets propagated Line_Preproc_Check 408 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " `line 411 "t/t_preproc.v" 0 Line_Preproc_Check 411 //====================================================================== // bug283 `line 415 "t/t_preproc.v" 0 // EXP: abc abc `line 425 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame `line 431 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame // This result varies between simulators EXP: sonet_frame sonet_frame `line 441 "t/t_preproc.v" 0 // The existance of non-existance of a base define can make a difference EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule `line 448 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule `line 453 "t/t_preproc.v" 0 //====================================================================== // bug311 integer/*NEED_SPACE*/ foo; //====================================================================== // bug441 module t; //----- // case provided // note this does NOT escape as suggested in the mail initial begin : \`LEX_CAT(a[0],_assignment) `line 465 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end //----- // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from // substituting and the \ staying in the expansion // Note space after name is important so when substitute it has ending whitespace initial begin : \a[0]_assignment_a[1] `line 472 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end //----- // RULE: Ignoring backslash does NOT allow an additional expansion level // (Because ESC gets expanded then the \ has it's normal escape meaning) initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end //----- // Similar to above; \ does not allow expansion after substitution initial begin : \`CAT(ff,bb) `line 486 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end //----- // MUST: Unknown macro with backslash escape stays as escaped symbol name initial begin : \`zzz `line 492 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end //----- // SHOULD(simulator-dependant): Known macro with backslash escape expands initial begin : \`FOO `line 499 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end // SHOULD(simulator-dependant): Prefix breaks the above initial begin : \xx`FOO `line 501 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end //----- // MUST: Unknown macro not under call with backslash escape doesn't expand initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end //----- // MUST: Unknown macro not under call doesn't expand initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end //----- // bug441 derivative // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz"); //----- // RULE: Because there are quotes after substituting STR, the `A does NOT expand initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz"); //---- // bug845 initial $write("Slashed=`%s'\n", "1//2.3"); //---- // bug915 initial `line 532 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule `line 535 "t/t_preproc.v" 0 //====================================================================== //bug1225 `line 538 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); `line 543 "t/t_preproc.v" 0 `line 548 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ $display("XXE_ is defined"); `line 555 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ $display("XYE_ is defined"); `line 562 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some $display("XXS_some is defined"); `line 569 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); `line 576 "t/t_preproc.v" 0 //==== `line 578 "t/t_preproc.v" 0 `line 586 "t/t_preproc.v" 0 `line 593 "t/t_preproc.v" 0 `line 600 "t/t_preproc.v" 0 `line 607 "t/t_preproc.v" 0 `line 609 "t/t_preproc.v" 0 // NEVER `line 611 "t/t_preproc.v" 0 //bug1227 (.mySig (myInterface.pa5), `line 615 "t/t_preproc.v" 0 //====================================================================== // Stringify bug `line 618 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); `line 621 "t/t_preproc.v" 0 `line 629 "t/t_preproc.v" 0 module pcc2_cfg; generate `line 631 "t/t_preproc.v" 0 covergroup a @(posedge b); `line 631 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup `line 631 "t/t_preproc.v" 0 a u_a; `line 631 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule `line 635 "t/t_preproc.v" 0 //====================================================================== // IEEE mandated predefines // undefineall should have no effect on these predef 0 0 predef 1 1 predef 2 2 predef 3 3 predef 10 10 predef 11 11 predef 20 20 predef 21 21 predef 22 22 predef 23 23 predef -2 -2 predef -1 -1 predef 0 0 predef 1 1 predef 2 2 //====================================================================== // After `undefineall above, for testing --dump-defines `line 657 "t/t_preproc.v" 2 verilator-4.038/test_regress/t/t_enum_public.v0000664000177100017500000000123213702133370021501 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package p3; typedef enum logic [2:0] { ZERO = 3'b0, ONE = 3'b1 } e3_t /*verilator public*/; endpackage package p62; typedef enum logic [62:0] { ZERO = '0, ALLONE = '1 } e62_t /*verilator public*/; endpackage module t (/*AUTOARG*/); enum integer { EI_A, EI_B, EI_C } m_state; initial begin m_state = EI_A; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_tri_pull01.v0000664000177100017500000000402013702133370021170 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Test: tri t; bufif1 (t, crc[1], cyc[1:0]==2'b00); bufif1 (t, crc[2], cyc[1:0]==2'b10); tri0 t0; bufif1 (t0, crc[1], cyc[1:0]==2'b00); bufif1 (t0, crc[2], cyc[1:0]==2'b10); tri1 t1; bufif1 (t1, crc[1], cyc[1:0]==2'b00); bufif1 (t1, crc[2], cyc[1:0]==2'b10); tri t2; t_tri2 t_tri2 (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00)); bufif1 (t2, crc[2], cyc[1:0]==2'b10); tri t3; t_tri3 t_tri3 (.t3, .d(crc[1]), .oe(cyc[1:0]==2'b00)); bufif1 (t3, crc[2], cyc[1:0]==2'b10); wire [63:0] result = {51'h0, t3, 3'h0,t2, 3'h0,t1, 3'h0,t0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h04f91df71371e950 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_tri2 (/*AUTOARG*/ // Outputs t2, // Inputs d, oe ); output t2; input d; input oe; tri1 t2; bufif1 (t2, d, oe); endmodule module t_tri3 (/*AUTOARG*/ // Outputs t3, // Inputs d, oe ); output tri1 t3; input d; input oe; bufif1 (t3, d, oe); endmodule verilator-4.038/test_regress/t/t_inst_misarray_bad.v0000664000177100017500000000144213702133370022674 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic foo; initial foo = 0; // dut #(.W(4)) udut(.*); dut #(.W(4)) udut(.clk(clk), .foo(foo)); // Assigning logic to logic array endmodule module dut #(parameter W = 1) (input logic clk, input logic foo[W-1:0]); genvar i; generate for (i = 0; i < W; i++) begin suba ua(.clk(clk), .foo(foo[i])); end endgenerate endmodule module suba (input logic clk, input logic foo); always @(posedge clk) $display("foo=%b", foo); endmodule verilator-4.038/test_regress/t/t_order_doubleloop.pl0000775000177100017500000000114713702133370022714 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); my $fail = $Self->{vlt_all}; compile( ); execute( check_finished => !$fail, fails => $fail, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_interface_array3.v0000664000177100017500000000176513702133370023272 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); interface a_if (); string s; endinterface module sub (output string s); initial s = $sformatf("%m"); endmodule module t ( clk ); input clk; string str [2:0][1:0]; a_if iface [2:0][1:0]; sub i_sub[2:0][1:0] (.s(str)); initial begin // TODO make self checking $display(iface[0][0]); $display(iface[0][1]); $display(iface[1][0]); $display(iface[1][1]); $display(iface[2][0]); $display(iface[2][1]); $display(str[0][0]); $display(str[0][1]); $display(str[1][0]); $display(str[1][1]); $display(str[2][0]); $display(str[2][1]); end endmodule verilator-4.038/test_regress/t/t_prot_lib_unpacked_bad.pl0000775000177100017500000000143613702133370023650 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile ( verilator_flags2 => ["--protect-lib", "secret"], verilator_make_gcc => 0, fails => 1, expect_filename => $Self->{golden_filename}, ); #run(cmd=>["make", # "-C", # "$Self->{obj_dir}", # "-f", # "V$Self->{name}.mk"]); ok(1); 1; verilator-4.038/test_regress/t/t_sv_cpu.v0000664000177100017500000000651113702133370020503 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: System Verilog test of a complete CPU // // This code instantiates and runs a simple CPU written in System Verilog. // // This file ONLY is placed into the Public Domain, for any use, without // warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. module t (/*AUTOARG*/ // Inputs clk ); input clk; /*AUTOWIRE*/ // ************************************************************************** // Regs and Wires // ************************************************************************** reg rst; integer rst_count; integer clk_count; testbench testbench_i (/*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); // ************************************************************************** // Reset Generation // ************************************************************************** initial begin rst = 1'b1; rst_count = 0; end always @( posedge clk ) begin if (rst_count < 2) begin rst_count++; end else begin rst = 1'b0; end end // ************************************************************************** // Drive simulation for 500 clock cycles // ************************************************************************** initial begin `ifdef TEST_VERBOSE $display( "[testbench] - Start of simulation ----------------------- " ); `endif clk_count = 0; end always @( posedge clk ) begin if (90 == clk_count) begin $finish (); end else begin clk_count++; end end final begin `ifdef TEST_VERBOSE $display( "[testbench] - End of simulation ------------------------- " ); `endif $write("*-* All Finished *-*\n"); end endmodule module testbench (/*AUTOARG*/ // Inputs clk, rst ); input clk; input rst; // ************************************************************************** // Local parameters // ************************************************************************** localparam NUMPADS = $size( pinout ); // ************************************************************************** // Regs and Wires // ************************************************************************** // **** Pinout **** `ifdef VERILATOR // see t_tri_array wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}). `else wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}). `endif // ************************************************************************** // Regs and Wires, Automatics // ************************************************************************** /*AUTOWIRE*/ // ************************************************************************** // Includes (Testbench extensions) // ************************************************************************** // N/A // ************************************************************************** // Chip Instance // ************************************************************************** chip i_chip ( /*AUTOINST*/ // Inouts .pad (pad[NUMPADS:1]), // Inputs .clk (clk), .rst (rst)); endmodule // test // Local Variables: // verilog-library-directories:("." "t_sv_cpu_code") // End: verilator-4.038/test_regress/t/t_genvar_misuse_bad.v0000664000177100017500000000061313702133370022656 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // See bug408 module top ( output logic [1:0] q, input logic [1:0] d, input logic clk ); genvar i; assign q[i] = d[i]; endmodule verilator-4.038/test_regress/t/t_math_pow.pl0000775000177100017500000000105313702133370021167 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_get_public_rw_switch.pl0000775000177100017500000000210613702133370024435 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); skip("Known compiler limitation") if $Self->cxx_version =~ /\(GCC\) 4.4/; VM_PREFIX("Vt_vpi_get"); top_filename("t/t_vpi_get.v"); pli_filename("t_vpi_get.cpp"); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi" ." --public-flat-rw --prefix Vt_vpi_get --no-l2name" ." $Self->{t_dir}/t_vpi_get.cpp"], make_pli => 1, iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2 => ["+define+USE_VPI_NOT_DPI"], ); execute( iv_pli => 1, check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_display_string.v0000664000177100017500000000142213702133370022233 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function automatic string foo(int i); return $sformatf("'%d'", i); // %0d does not work here endfunction real r = 1.234; string bar = foo(1); localparam string pbar = foo(1); initial begin $write("String: "); $display("' 1'"); $write("foo(1): "); $display(foo(1)); $write("s f(1): "); $display("%s", foo(1)); $write("s parm: "); $display("%s", pbar); $write("s strg: "); $display("%s", bar); $write("r: "); $display(r); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_assoc_meth_bad.v0000664000177100017500000000113513702133367022142 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); initial begin string a [string]; string k; string v; v = a.num("badarg"); v = a.size("badarg"); v = a.exists(); // Bad v = a.exists(k, "bad2"); v = a.first(); // Bad v = a.next(k, "bad2"); // Bad v = a.last(); // Bad v = a.prev(k, "bad2"); // Bad a.delete(k, "bad2"); end endmodule verilator-4.038/test_regress/t/t_enum_x_bad.out0000664000177100017500000000076313702133370021652 0ustar wsnyderwsnyder%Error: t/t_enum_x_bad.v:9:21: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 1800-2017 6.19) : ... In instance t 9 | enum bit [1:0] { BADX = 2'b1x } BAD1; | ^~~~ %Error: t/t_enum_x_bad.v:12:23: Enum value that is unassigned cannot follow value with X/Zs (IEEE 1800-2017 6.19) : ... In instance t 12 | e1 | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_generate_fatal_bad.out0000664000177100017500000001562213702133370023320 0ustar wsnyderwsnyder%Warning-USERFATAL: "boom" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.genloop[0].foo_inst t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = ?32?h0 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.genloop[1].foo_inst t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = ?32?h1 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.gen_l1[2].gen_l2[0].foo_inst2 t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h2 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.gen_l1[2].gen_l2[1].foo_inst2 t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h4 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.gen_l1[3].gen_l2[0].foo_inst2 t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h3 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.gen_l1[3].gen_l2[1].foo_inst2 t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h5 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.cond_true.foo_inst3 t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = ?32?h6 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.genblk1.foo_inst4 t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = ?32?h7 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.nested_loop[8].foo2_inst.foo2_loop[0].foo_in_foo2_inst t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h8 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.nested_loop[8].foo2_inst.foo2_loop[1].foo_in_foo2_inst t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h9 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.nested_loop[10].foo2_inst.foo2_loop[0].foo_in_foo2_inst t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'ha 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'hb 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_nest.pl0000775000177100017500000000105313702133370022342 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_optm_if_array.pl0000775000177100017500000000127613702133370022213 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", qr/rstn_r/); file_grep_not("$Self->{obj_dir}/$Self->{VM_PREFIX}__Slow.cpp", qr/rstn_r/); ok(1); 1; verilator-4.038/test_regress/t/t_param_mem_attr.v0000664000177100017500000000215613702133370022175 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // A test case for parameterized module. // // When a module is instantiatied with parameter, there will be two modules in // the tree and eventually one will be removed after param and deadifyModules. // // This test is to check that the removal of dead module will not cause // compilation error. Possible error was/is seen as: // // pure virtual method called // terminate called without an active exception // %Error: Verilator aborted. Consider trying --debug --gdbbt // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [71:0] ctrl; wire [7:0] cl; // this line is added memory #(.words(72)) i_memory (.clk (clk)); assign ctrl = i_memory.mem[0]; assign cl = i_memory.mem[0][7:0]; // and this line endmodule // memory module, which is used with parameter module memory (clk); input clk; parameter words = 16384, bits = 72; reg [bits-1 :0] mem[words-1 : 0]; endmodule verilator-4.038/test_regress/t/t_func_grey.pl0000775000177100017500000000105313702133370021332 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_module.pl0000775000177100017500000000107713702133370022024 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Compile only test compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_get.cpp0000664000177100017500000002135413702133370021160 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "Vt_vpi_get.h" #include "verilated.h" #include "svdpi.h" #include "Vt_vpi_get__Dpi.h" #include "verilated_vpi.h" #include "verilated_vcd_c.h" #endif #include #include #include #include "TestSimulator.h" #include "TestVpi.h" // __FILE__ is too long #define FILENM "t_vpi_get.cpp" #define TEST_MSG \ if (0) printf unsigned int main_time = 0; //====================================================================== #define CHECK_RESULT_VH(got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d: GOT = %p EXP = %p\n", FILENM, __LINE__, (got), (exp)); \ return __LINE__; \ } #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ return __LINE__; \ } // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_HEX(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << std::hex \ << ": GOT = " << (got) << " EXP = " << (exp) << endl; \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ (got) ? (got) : "", (exp) ? (exp) : ""); \ return __LINE__; \ } #define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp) static int _mon_check_props(TestVpiHandle& handle, int size, int direction, int scalar, int type) { s_vpi_value value; value.format = vpiIntVal; value.value.integer = 0; // check size of object int vpisize = vpi_get(vpiSize, handle); CHECK_RESULT(vpisize, size); // icarus verilog does not support vpiScalar, vpiVector or vpi*Range if (TestSimulator::has_get_scalar()) { int vpiscalar = vpi_get(vpiScalar, handle); CHECK_RESULT((bool)vpiscalar, (bool)scalar); int vpivector = vpi_get(vpiVector, handle); CHECK_RESULT((bool)vpivector, (bool)!scalar); } // Icarus only supports ranges on memories if (!scalar && !(TestSimulator::is_icarus() && type != vpiMemory)) { TestVpiHandle left_h, right_h; // check coherency for vectors // get left hand side of range left_h = vpi_handle(vpiLeftRange, handle); CHECK_RESULT_NZ(left_h); vpi_get_value(left_h, &value); int coherency = value.value.integer; // get right hand side of range right_h = vpi_handle(vpiRightRange, handle); CHECK_RESULT_NZ(right_h); vpi_get_value(right_h, &value); TEST_MSG("%d:%d\n", coherency, value.value.integer); coherency -= value.value.integer; // calculate size & check coherency = abs(coherency) + 1; CHECK_RESULT(coherency, size); } // Only check direction on ports if (type == vpiPort) { // check direction of object int vpidir = vpi_get(vpiDirection, handle); // Don't check port directions in verilator // see #681 if (!TestSimulator::is_verilator()) { CHECK_RESULT(vpidir, direction); } } // check type of object int vpitype = vpi_get(vpiType, handle); if (!(TestSimulator::is_verilator() && type == vpiPort)) { // Don't check for ports in verilator // see #681 CHECK_RESULT(vpitype, type); } return 0; // Ok } struct params { const char* signal; struct { unsigned int size; unsigned int direction; unsigned int scalar; int type; } attributes, children; }; int mon_check_props() { // This table needs to be function-static. // This avoids calling is_verilator() below at global-static init time. // When global-static led to a race between the is_verilator call below, and // the code that sets up the VerilatedAssertOneThread() check in // verilated_vpi.cc, it was causing the check to falsely fail // (due to m_threadid within the check not being initted yet.) static struct params values[] = {{"onebit", {1, vpiNoDirection, 1, vpiReg}, {0, 0, 0, 0}}, {"twoone", {2, vpiNoDirection, 0, vpiReg}, {0, 0, 0, 0}}, {"onetwo", {2, vpiNoDirection, 0, TestSimulator::is_verilator() ? vpiReg : vpiMemory}, {0, 0, 0, 0}}, {"fourthreetwoone", {2, vpiNoDirection, 0, vpiMemory}, {2, vpiNoDirection, 0, vpiMemoryWord}}, {"clk", {1, vpiInput, 1, vpiPort}, {0, 0, 0, 0}}, {"testin", {16, vpiInput, 0, vpiPort}, {0, 0, 0, 0}}, {"testout", {24, vpiOutput, 0, vpiPort}, {0, 0, 0, 0}}, {"sub.subin", {1, vpiInput, 1, vpiPort}, {0, 0, 0, 0}}, {"sub.subout", {1, vpiOutput, 1, vpiPort}, {0, 0, 0, 0}}, {NULL, {0, 0, 0, 0}, {0, 0, 0, 0}}}; struct params* value = values; while (value->signal) { TestVpiHandle h = VPI_HANDLE(value->signal); CHECK_RESULT_NZ(h); TEST_MSG("%s\n", value->signal); if (int status = _mon_check_props(h, value->attributes.size, value->attributes.direction, value->attributes.scalar, value->attributes.type)) return status; if (value->children.size) { int size = 0; TestVpiHandle iter_h = vpi_iterate(vpiMemoryWord, h); while (TestVpiHandle word_h = vpi_scan(iter_h.nofree())) { // check size and range if (int status = _mon_check_props(word_h, value->children.size, value->children.direction, value->children.scalar, value->children.type)) return status; size++; } CHECK_RESULT(size, value->attributes.size); } value++; } return 0; } int mon_check() { // Callback from initial block in monitor if (int status = mon_check_props()) return status; return 0; // Ok } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { vpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); Vt_vpi_get* topp = new Vt_vpi_get(""); // Note null name - we're flattening it out #ifdef VERILATOR #ifdef TEST_VERBOSE Verilated::scopesDump(); #endif #endif #if VM_TRACE Verilated::traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; main_time += 10; while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += 1; topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } if (!Verilated::gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete topp, topp); exit(0L); } #endif verilator-4.038/test_regress/t/t_math_cond_huge.v0000664000177100017500000005010413702133370022145 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] sel = crc[7:0]; wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] out; // From test of Test.v // End of automatics /* Test AUTO_TEMPLATE ( .i\([0-9]+\) (in[\1 +:4]), ); */ Test test (/*AUTOINST*/ // Outputs .out (out[3:0]), // Inputs .sel (sel[7:0]), .i0 (in[0 +:4]), // Templated .i1 (in[1 +:4]), // Templated .i2 (in[2 +:4]), // Templated .i3 (in[3 +:4]), // Templated .i4 (in[4 +:4]), // Templated .i5 (in[5 +:4]), // Templated .i6 (in[6 +:4]), // Templated .i7 (in[7 +:4]), // Templated .i8 (in[8 +:4]), // Templated .i9 (in[9 +:4]), // Templated .i10 (in[10 +:4]), // Templated .i11 (in[11 +:4]), // Templated .i12 (in[12 +:4]), // Templated .i13 (in[13 +:4]), // Templated .i14 (in[14 +:4]), // Templated .i15 (in[15 +:4]), // Templated .i16 (in[16 +:4]), // Templated .i17 (in[17 +:4]), // Templated .i18 (in[18 +:4]), // Templated .i19 (in[19 +:4]), // Templated .i20 (in[20 +:4]), // Templated .i21 (in[21 +:4]), // Templated .i22 (in[22 +:4]), // Templated .i23 (in[23 +:4]), // Templated .i24 (in[24 +:4]), // Templated .i25 (in[25 +:4]), // Templated .i26 (in[26 +:4]), // Templated .i27 (in[27 +:4]), // Templated .i28 (in[28 +:4]), // Templated .i29 (in[29 +:4]), // Templated .i30 (in[30 +:4]), // Templated .i31 (in[31 +:4]), // Templated .i32 (in[32 +:4]), // Templated .i33 (in[33 +:4]), // Templated .i34 (in[34 +:4]), // Templated .i35 (in[35 +:4]), // Templated .i36 (in[36 +:4]), // Templated .i37 (in[37 +:4]), // Templated .i38 (in[38 +:4]), // Templated .i39 (in[39 +:4]), // Templated .i40 (in[40 +:4]), // Templated .i41 (in[41 +:4]), // Templated .i42 (in[42 +:4]), // Templated .i43 (in[43 +:4]), // Templated .i44 (in[44 +:4]), // Templated .i45 (in[45 +:4]), // Templated .i46 (in[46 +:4]), // Templated .i47 (in[47 +:4]), // Templated .i48 (in[48 +:4]), // Templated .i49 (in[49 +:4]), // Templated .i50 (in[50 +:4]), // Templated .i51 (in[51 +:4]), // Templated .i52 (in[52 +:4]), // Templated .i53 (in[53 +:4]), // Templated .i54 (in[54 +:4]), // Templated .i55 (in[55 +:4]), // Templated .i56 (in[56 +:4]), // Templated .i57 (in[57 +:4]), // Templated .i58 (in[58 +:4]), // Templated .i59 (in[59 +:4]), // Templated .i60 (in[60 +:4]), // Templated .i61 (in[61 +:4]), // Templated .i62 (in[62 +:4]), // Templated .i63 (in[63 +:4]), // Templated .i64 (in[64 +:4]), // Templated .i65 (in[65 +:4]), // Templated .i66 (in[66 +:4]), // Templated .i67 (in[67 +:4]), // Templated .i68 (in[68 +:4]), // Templated .i69 (in[69 +:4]), // Templated .i70 (in[70 +:4]), // Templated .i71 (in[71 +:4]), // Templated .i72 (in[72 +:4]), // Templated .i73 (in[73 +:4]), // Templated .i74 (in[74 +:4]), // Templated .i75 (in[75 +:4]), // Templated .i76 (in[76 +:4]), // Templated .i77 (in[77 +:4]), // Templated .i78 (in[78 +:4]), // Templated .i79 (in[79 +:4]), // Templated .i80 (in[80 +:4]), // Templated .i81 (in[81 +:4]), // Templated .i82 (in[82 +:4]), // Templated .i83 (in[83 +:4]), // Templated .i84 (in[84 +:4]), // Templated .i85 (in[85 +:4]), // Templated .i86 (in[86 +:4]), // Templated .i87 (in[87 +:4]), // Templated .i88 (in[88 +:4]), // Templated .i89 (in[89 +:4]), // Templated .i90 (in[90 +:4]), // Templated .i91 (in[91 +:4]), // Templated .i92 (in[92 +:4]), // Templated .i93 (in[93 +:4]), // Templated .i94 (in[94 +:4]), // Templated .i95 (in[95 +:4]), // Templated .i96 (in[96 +:4]), // Templated .i97 (in[97 +:4]), // Templated .i98 (in[98 +:4]), // Templated .i99 (in[99 +:4]), // Templated .i100 (in[100 +:4]), // Templated .i101 (in[101 +:4]), // Templated .i102 (in[102 +:4]), // Templated .i103 (in[103 +:4]), // Templated .i104 (in[104 +:4]), // Templated .i105 (in[105 +:4]), // Templated .i106 (in[106 +:4]), // Templated .i107 (in[107 +:4]), // Templated .i108 (in[108 +:4]), // Templated .i109 (in[109 +:4]), // Templated .i110 (in[110 +:4]), // Templated .i111 (in[111 +:4]), // Templated .i112 (in[112 +:4]), // Templated .i113 (in[113 +:4]), // Templated .i114 (in[114 +:4]), // Templated .i115 (in[115 +:4]), // Templated .i116 (in[116 +:4]), // Templated .i117 (in[117 +:4]), // Templated .i118 (in[118 +:4]), // Templated .i119 (in[119 +:4]), // Templated .i120 (in[120 +:4]), // Templated .i121 (in[121 +:4]), // Templated .i122 (in[122 +:4]), // Templated .i123 (in[123 +:4]), // Templated .i124 (in[124 +:4]), // Templated .i125 (in[125 +:4]), // Templated .i126 (in[126 +:4]), // Templated .i127 (in[127 +:4]), // Templated .i128 (in[128 +:4]), // Templated .i129 (in[129 +:4]), // Templated .i130 (in[130 +:4]), // Templated .i131 (in[131 +:4]), // Templated .i132 (in[132 +:4]), // Templated .i133 (in[133 +:4]), // Templated .i134 (in[134 +:4]), // Templated .i135 (in[135 +:4]), // Templated .i136 (in[136 +:4]), // Templated .i137 (in[137 +:4]), // Templated .i138 (in[138 +:4]), // Templated .i139 (in[139 +:4]), // Templated .i140 (in[140 +:4]), // Templated .i141 (in[141 +:4]), // Templated .i142 (in[142 +:4]), // Templated .i143 (in[143 +:4]), // Templated .i144 (in[144 +:4]), // Templated .i145 (in[145 +:4]), // Templated .i146 (in[146 +:4]), // Templated .i147 (in[147 +:4]), // Templated .i148 (in[148 +:4]), // Templated .i149 (in[149 +:4]), // Templated .i150 (in[150 +:4]), // Templated .i151 (in[151 +:4]), // Templated .i152 (in[152 +:4]), // Templated .i153 (in[153 +:4]), // Templated .i154 (in[154 +:4]), // Templated .i155 (in[155 +:4]), // Templated .i156 (in[156 +:4]), // Templated .i157 (in[157 +:4]), // Templated .i158 (in[158 +:4]), // Templated .i159 (in[159 +:4]), // Templated .i160 (in[160 +:4]), // Templated .i161 (in[161 +:4]), // Templated .i162 (in[162 +:4]), // Templated .i163 (in[163 +:4]), // Templated .i164 (in[164 +:4]), // Templated .i165 (in[165 +:4]), // Templated .i166 (in[166 +:4]), // Templated .i167 (in[167 +:4]), // Templated .i168 (in[168 +:4]), // Templated .i169 (in[169 +:4]), // Templated .i170 (in[170 +:4]), // Templated .i171 (in[171 +:4]), // Templated .i172 (in[172 +:4]), // Templated .i173 (in[173 +:4]), // Templated .i174 (in[174 +:4]), // Templated .i175 (in[175 +:4]), // Templated .i176 (in[176 +:4]), // Templated .i177 (in[177 +:4]), // Templated .i178 (in[178 +:4]), // Templated .i179 (in[179 +:4]), // Templated .i180 (in[180 +:4]), // Templated .i181 (in[181 +:4]), // Templated .i182 (in[182 +:4]), // Templated .i183 (in[183 +:4]), // Templated .i184 (in[184 +:4]), // Templated .i185 (in[185 +:4]), // Templated .i186 (in[186 +:4]), // Templated .i187 (in[187 +:4]), // Templated .i188 (in[188 +:4]), // Templated .i189 (in[189 +:4]), // Templated .i190 (in[190 +:4]), // Templated .i191 (in[191 +:4]), // Templated .i192 (in[192 +:4]), // Templated .i193 (in[193 +:4]), // Templated .i194 (in[194 +:4]), // Templated .i195 (in[195 +:4]), // Templated .i196 (in[196 +:4]), // Templated .i197 (in[197 +:4]), // Templated .i198 (in[198 +:4]), // Templated .i199 (in[199 +:4]), // Templated .i200 (in[200 +:4]), // Templated .i201 (in[201 +:4]), // Templated .i202 (in[202 +:4]), // Templated .i203 (in[203 +:4]), // Templated .i204 (in[204 +:4]), // Templated .i205 (in[205 +:4]), // Templated .i206 (in[206 +:4]), // Templated .i207 (in[207 +:4]), // Templated .i208 (in[208 +:4]), // Templated .i209 (in[209 +:4]), // Templated .i210 (in[210 +:4]), // Templated .i211 (in[211 +:4]), // Templated .i212 (in[212 +:4]), // Templated .i213 (in[213 +:4]), // Templated .i214 (in[214 +:4]), // Templated .i215 (in[215 +:4]), // Templated .i216 (in[216 +:4]), // Templated .i217 (in[217 +:4]), // Templated .i218 (in[218 +:4]), // Templated .i219 (in[219 +:4]), // Templated .i220 (in[220 +:4]), // Templated .i221 (in[221 +:4]), // Templated .i222 (in[222 +:4]), // Templated .i223 (in[223 +:4]), // Templated .i224 (in[224 +:4]), // Templated .i225 (in[225 +:4]), // Templated .i226 (in[226 +:4]), // Templated .i227 (in[227 +:4]), // Templated .i228 (in[228 +:4]), // Templated .i229 (in[229 +:4]), // Templated .i230 (in[230 +:4]), // Templated .i231 (in[231 +:4]), // Templated .i232 (in[232 +:4]), // Templated .i233 (in[233 +:4]), // Templated .i234 (in[234 +:4]), // Templated .i235 (in[235 +:4]), // Templated .i236 (in[236 +:4]), // Templated .i237 (in[237 +:4]), // Templated .i238 (in[238 +:4]), // Templated .i239 (in[239 +:4]), // Templated .i240 (in[240 +:4]), // Templated .i241 (in[241 +:4]), // Templated .i242 (in[242 +:4]), // Templated .i243 (in[243 +:4]), // Templated .i244 (in[244 +:4]), // Templated .i245 (in[245 +:4]), // Templated .i246 (in[246 +:4]), // Templated .i247 (in[247 +:4]), // Templated .i248 (in[248 +:4]), // Templated .i249 (in[249 +:4]), // Templated .i250 (in[250 +:4]), // Templated .i251 (in[251 +:4]), // Templated .i252 (in[252 +:4]), // Templated .i253 (in[253 +:4]), // Templated .i254 (in[254 +:4]), // Templated .i255 (in[255 +:4])); // Templated // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'h36f3051d15caf07a // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( output wire [3:0] out, input [7:0] sel, input [3:0] i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50, i51, i52, i53, i54, i55, i56, i57, i58, i59, i60, i61, i62, i63, i64, i65, i66, i67, i68, i69, i70, i71, i72, i73, i74, i75, i76, i77, i78, i79, i80, i81, i82, i83, i84, i85, i86, i87, i88, i89, i90, i91, i92, i93, i94, i95, i96, i97, i98, i99, i100, i101, i102, i103, i104, i105, i106, i107, i108, i109, i110, i111, i112, i113, i114, i115, i116, i117, i118, i119, i120, i121, i122, i123, i124, i125, i126, i127, i128, i129, i130, i131, i132, i133, i134, i135, i136, i137, i138, i139, i140, i141, i142, i143, i144, i145, i146, i147, i148, i149, i150, i151, i152, i153, i154, i155, i156, i157, i158, i159, i160, i161, i162, i163, i164, i165, i166, i167, i168, i169, i170, i171, i172, i173, i174, i175, i176, i177, i178, i179, i180, i181, i182, i183, i184, i185, i186, i187, i188, i189, i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, i200, i201, i202, i203, i204, i205, i206, i207, i208, i209, i210, i211, i212, i213, i214, i215, i216, i217, i218, i219, i220, i221, i222, i223, i224, i225, i226, i227, i228, i229, i230, i231, i232, i233, i234, i235, i236, i237, i238, i239, i240, i241, i242, i243, i244, i245, i246, i247, i248, i249, i250, i251, i252, i253, i254, i255 ); assign out = (sel==8'h00) ? i0 : (sel==8'h01) ? i1 : (sel==8'h02) ? i2 : (sel==8'h03) ? i3 : (sel==8'h04) ? i4 : (sel==8'h05) ? i5 : (sel==8'h06) ? i6 : (sel==8'h07) ? i7 : (sel==8'h08) ? i8 : (sel==8'h09) ? i9 : (sel==8'h0a) ? i10 : (sel==8'h0b) ? i11 : (sel==8'h0c) ? i12 : (sel==8'h0d) ? i13 : (sel==8'h0e) ? i14 : (sel==8'h0f) ? i15 : (sel==8'h10) ? i16 : (sel==8'h11) ? i17 : (sel==8'h12) ? i18 : (sel==8'h13) ? i19 : (sel==8'h14) ? i20 : (sel==8'h15) ? i21 : (sel==8'h16) ? i22 : (sel==8'h17) ? i23 : (sel==8'h18) ? i24 : (sel==8'h19) ? i25 : (sel==8'h1a) ? i26 : (sel==8'h1b) ? i27 : (sel==8'h1c) ? i28 : (sel==8'h1d) ? i29 : (sel==8'h1e) ? i30 : (sel==8'h1f) ? i31 : (sel==8'h20) ? i32 : (sel==8'h21) ? i33 : (sel==8'h22) ? i34 : (sel==8'h23) ? i35 : (sel==8'h24) ? i36 : (sel==8'h25) ? i37 : (sel==8'h26) ? i38 : (sel==8'h27) ? i39 : (sel==8'h28) ? i40 : (sel==8'h29) ? i41 : (sel==8'h2a) ? i42 : (sel==8'h2b) ? i43 : (sel==8'h2c) ? i44 : (sel==8'h2d) ? i45 : (sel==8'h2e) ? i46 : (sel==8'h2f) ? i47 : (sel==8'h30) ? i48 : (sel==8'h31) ? i49 : (sel==8'h32) ? i50 : (sel==8'h33) ? i51 : (sel==8'h34) ? i52 : (sel==8'h35) ? i53 : (sel==8'h36) ? i54 : (sel==8'h37) ? i55 : (sel==8'h38) ? i56 : (sel==8'h39) ? i57 : (sel==8'h3a) ? i58 : (sel==8'h3b) ? i59 : (sel==8'h3c) ? i60 : (sel==8'h3d) ? i61 : (sel==8'h3e) ? i62 : (sel==8'h3f) ? i63 : (sel==8'h40) ? i64 : (sel==8'h41) ? i65 : (sel==8'h42) ? i66 : (sel==8'h43) ? i67 : (sel==8'h44) ? i68 : (sel==8'h45) ? i69 : (sel==8'h46) ? i70 : (sel==8'h47) ? i71 : (sel==8'h48) ? i72 : (sel==8'h49) ? i73 : (sel==8'h4a) ? i74 : (sel==8'h4b) ? i75 : (sel==8'h4c) ? i76 : (sel==8'h4d) ? i77 : (sel==8'h4e) ? i78 : (sel==8'h4f) ? i79 : (sel==8'h50) ? i80 : (sel==8'h51) ? i81 : (sel==8'h52) ? i82 : (sel==8'h53) ? i83 : (sel==8'h54) ? i84 : (sel==8'h55) ? i85 : (sel==8'h56) ? i86 : (sel==8'h57) ? i87 : (sel==8'h58) ? i88 : (sel==8'h59) ? i89 : (sel==8'h5a) ? i90 : (sel==8'h5b) ? i91 : (sel==8'h5c) ? i92 : (sel==8'h5d) ? i93 : (sel==8'h5e) ? i94 : (sel==8'h5f) ? i95 : (sel==8'h60) ? i96 : (sel==8'h61) ? i97 : (sel==8'h62) ? i98 : (sel==8'h63) ? i99 : (sel==8'h64) ? i100 : (sel==8'h65) ? i101 : (sel==8'h66) ? i102 : (sel==8'h67) ? i103 : (sel==8'h68) ? i104 : (sel==8'h69) ? i105 : (sel==8'h6a) ? i106 : (sel==8'h6b) ? i107 : (sel==8'h6c) ? i108 : (sel==8'h6d) ? i109 : (sel==8'h6e) ? i110 : (sel==8'h6f) ? i111 : (sel==8'h70) ? i112 : (sel==8'h71) ? i113 : (sel==8'h72) ? i114 : (sel==8'h73) ? i115 : (sel==8'h74) ? i116 : (sel==8'h75) ? i117 : (sel==8'h76) ? i118 : (sel==8'h77) ? i119 : (sel==8'h78) ? i120 : (sel==8'h79) ? i121 : (sel==8'h7a) ? i122 : (sel==8'h7b) ? i123 : (sel==8'h7c) ? i124 : (sel==8'h7d) ? i125 : (sel==8'h7e) ? i126 : (sel==8'h7f) ? i127 : (sel==8'h80) ? i128 : (sel==8'h81) ? i129 : (sel==8'h82) ? i130 : (sel==8'h83) ? i131 : (sel==8'h84) ? i132 : (sel==8'h85) ? i133 : (sel==8'h86) ? i134 : (sel==8'h87) ? i135 : (sel==8'h88) ? i136 : (sel==8'h89) ? i137 : (sel==8'h8a) ? i138 : (sel==8'h8b) ? i139 : (sel==8'h8c) ? i140 : (sel==8'h8d) ? i141 : (sel==8'h8e) ? i142 : (sel==8'h8f) ? i143 : (sel==8'h90) ? i144 : (sel==8'h91) ? i145 : (sel==8'h92) ? i146 : (sel==8'h93) ? i147 : (sel==8'h94) ? i148 : (sel==8'h95) ? i149 : (sel==8'h96) ? i150 : (sel==8'h98) ? i151 : (sel==8'h99) ? i152 : (sel==8'h9a) ? i153 : (sel==8'h9b) ? i154 : (sel==8'h9c) ? i155 : (sel==8'h9d) ? i156 : (sel==8'h9e) ? i157 : (sel==8'h9f) ? i158 : (sel==8'ha0) ? i159 : (sel==8'ha1) ? i160 : (sel==8'ha2) ? i161 : (sel==8'ha3) ? i162 : (sel==8'ha4) ? i163 : (sel==8'ha5) ? i164 : (sel==8'ha6) ? i165 : (sel==8'ha7) ? i166 : (sel==8'ha8) ? i167 : (sel==8'ha9) ? i168 : (sel==8'haa) ? i169 : (sel==8'hab) ? i170 : (sel==8'hac) ? i171 : (sel==8'had) ? i172 : (sel==8'hae) ? i173 : (sel==8'haf) ? i174 : (sel==8'hb0) ? i175 : (sel==8'hb1) ? i176 : (sel==8'hb2) ? i177 : (sel==8'hb3) ? i178 : (sel==8'hb4) ? i179 : (sel==8'hb5) ? i180 : (sel==8'hb6) ? i181 : (sel==8'hb7) ? i182 : (sel==8'hb8) ? i183 : (sel==8'hb9) ? i184 : (sel==8'hba) ? i185 : (sel==8'hbb) ? i186 : (sel==8'hbc) ? i187 : (sel==8'hbd) ? i188 : (sel==8'hbe) ? i189 : (sel==8'hbf) ? i190 : (sel==8'hc0) ? i191 : (sel==8'hc1) ? i192 : (sel==8'hc2) ? i193 : (sel==8'hc3) ? i194 : (sel==8'hc4) ? i195 : (sel==8'hc5) ? i196 : (sel==8'hc6) ? i197 : (sel==8'hc7) ? i198 : (sel==8'hc8) ? i199 : (sel==8'hc9) ? i200 : (sel==8'hca) ? i201 : (sel==8'hcb) ? i202 : (sel==8'hcc) ? i203 : (sel==8'hcd) ? i204 : (sel==8'hce) ? i205 : (sel==8'hcf) ? i206 : (sel==8'hd0) ? i207 : (sel==8'hd1) ? i208 : (sel==8'hd2) ? i209 : (sel==8'hd3) ? i210 : (sel==8'hd4) ? i211 : (sel==8'hd5) ? i212 : (sel==8'hd6) ? i213 : (sel==8'hd7) ? i214 : (sel==8'hd8) ? i215 : (sel==8'hd9) ? i216 : (sel==8'hda) ? i217 : (sel==8'hdb) ? i218 : (sel==8'hdc) ? i219 : (sel==8'hdd) ? i220 : (sel==8'hde) ? i221 : (sel==8'hdf) ? i222 : (sel==8'he0) ? i223 : (sel==8'he1) ? i224 : (sel==8'he2) ? i225 : (sel==8'he3) ? i226 : (sel==8'he4) ? i227 : (sel==8'he5) ? i228 : (sel==8'he6) ? i229 : (sel==8'he7) ? i230 : (sel==8'he8) ? i231 : (sel==8'he9) ? i232 : (sel==8'hea) ? i233 : (sel==8'heb) ? i234 : (sel==8'hec) ? i235 : (sel==8'hed) ? i236 : (sel==8'hee) ? i237 : (sel==8'hef) ? i238 : (sel==8'hf0) ? i239 : (sel==8'hf1) ? i240 : (sel==8'hf2) ? i241 : (sel==8'hf3) ? i242 : (sel==8'hf4) ? i243 : (sel==8'hf5) ? i244 : (sel==8'hf6) ? i245 : (sel==8'hf7) ? i246 : (sel==8'hf8) ? i247 : (sel==8'hf9) ? i248 : (sel==8'hfa) ? i249 : (sel==8'hfb) ? i250 : (sel==8'hfc) ? i251 : (sel==8'hfd) ? i252 : (sel==8'hfe) ? i253 : (sel==8'hff) ? i254 : i255; endmodule verilator-4.038/test_regress/t/t_inst_aport.pl0000775000177100017500000000115213702133370021533 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); unsupported("Verilator/commercial slice unsupported, bug711"); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_slot.pl0000775000177100017500000000123213702133370021167 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_cond.pl0000775000177100017500000000105313702133370021132 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_nomod_bad.out0000664000177100017500000000007113702133341022452 0ustar wsnyderwsnyder%Error: No top level module found %Error: Exiting due to verilator-4.038/test_regress/t/t_class_param.pl0000775000177100017500000000117613702133367021652 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_cover_line_cc.pl0000775000177100017500000000307613702133367022160 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_cover_line.v"); compile( verilator_flags2 => ['--cc --coverage-line +define+ATTRIBUTE'], ); execute( check_finished => 1, ); # Read the input .v file and do any CHECK_COVER requests inline_checks(); run(cmd => ["../bin/verilator_coverage", "--annotate", "$Self->{obj_dir}/annotated", "$Self->{obj_dir}/coverage.dat"], verilator_run => 1, ); files_identical("$Self->{obj_dir}/annotated/t_cover_line.v", "t/t_cover_line.out"); # Also try lcov run(cmd => ["../bin/verilator_coverage", "--write-info", "$Self->{obj_dir}/coverage.info", "$Self->{obj_dir}/coverage.dat"], verilator_run => 1, ); # If installed if (`lcov --version` !~ /version/i || `genhtml --version` !~ /version ([0-9.]+)/i) { skip("lcov or genhtml not installed"); } elsif ($1 < 1.14) { skip("lcov or genhtml too old (version $1), need version >= 1.14"); } else { run(cmd => ["genhtml", "$Self->{obj_dir}/coverage.info", "--output-directory $Self->{obj_dir}/html", ]); } ok(1); 1; verilator-4.038/test_regress/t/t_param_repl.v0000664000177100017500000000237013702133370021325 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter [31:0] TWENTY4 = 24; parameter [31:0] PA = TWENTY4/8; parameter [1:0] VALUE = 2'b10; parameter [5:0] REPL = {PA{VALUE}}; parameter [7:0] CONC = {REPL,VALUE}; parameter DBITS = 32; parameter INIT_BYTE = 8'h1F; parameter DWORDS_LOG2 = 7; parameter DWORDS = (1< 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_flip.v0000664000177100017500000000253313702133370021151 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define INT_RANGE 31:0 `define INT_RANGE 31:0 // Duplicate identical defs are OK `define INT_RANGE_MAX 31 `define VECTOR_RANGE 511:0 module t (clk); // verilator lint_off WIDTH parameter WIDTH = 16; // Must be a power of 2 parameter WIDTH_LOG2 = 4; // set to log2(WIDTH) parameter USE_BS = 1; // set to 1 for enable input clk; function [`VECTOR_RANGE] func_tree_left; input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector reg [`VECTOR_RANGE] flip; begin flip = 'd0; func_tree_left = flip; end endfunction reg [WIDTH-1:0] a; // value to be shifted reg [WIDTH-1:0] tree_left; always @(a) begin : barrel_shift tree_left = func_tree_left (a); end // barrel_shift integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a = 5; end if (cyc==2) begin $display ("%x\n",tree_left); //if (tree_left != 'd15) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_langext_1.pl0000775000177100017500000000110713702133370021233 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # This is a compile only test. compile( v_flags2 => ["+verilog2001ext+v"], ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_func.v0000664000177100017500000000534513702133370021001 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [2:0] q; // From test of Test.v // End of automatics Test test ( // Outputs .q (q[2:0]), // Inputs .clk (clk), .reset_l (crc[0]), .enable (crc[2]), .q_var0 (crc[19:10]), .q_var2 (crc[29:20]), .q_var4 (crc[39:30]), .q_var6 (crc[49:40]) /*AUTOINST*/); // Aggregate outputs into a single result vector wire [63:0] result = {61'h0,q}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h58b162c58d6e35ba if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input reset_l, input enable, input [ 9:0] q_var0, input [ 9:0] q_var2, input [ 9:0] q_var4, input [ 9:0] q_var6, output reg [2:0] q ); reg [7:0] p1_r [6:0]; always @(posedge clk) begin if (!reset_l) begin p1_r[0] <= 'b0; p1_r[1] <= 'b0; p1_r[2] <= 'b0; p1_r[3] <= 'b0; p1_r[4] <= 'b0; p1_r[5] <= 'b0; p1_r[6] <= 'b0; end else if (enable) begin : pass1 match(q_var0, q_var2, q_var4, q_var6); end end // verilator lint_off WIDTH always @(posedge clk) begin : l reg [10:0] bd; reg [3:0] idx; q = 0; bd = 0; for (idx=0; idx<7; idx=idx+1) begin q = idx+1; bd = bd + p1_r[idx]; end end task match; input [9:0] p0, p1, p2, p3; reg [9:0] p[3:0]; begin p[0] = p0; p[1] = p1; p[2] = p2; p[3] = p3; p1_r[0] <= p[0]; p1_r[1] <= p[1]; end endtask endmodule verilator-4.038/test_regress/t/t_gate_array.pl0000775000177100017500000000105313702133370021467 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_name_bad.out0000664000177100017500000000036213702133370022126 0ustar wsnyderwsnyder%Error: t/t_dpi_name_bad.v:12:32: DPI function has illegal characters in C identifier name: 'badly.named' 12 | import "DPI-C" function int \badly.named (int i); | ^~~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_math_pow.v0000664000177100017500000000501213702133370021015 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef VERILATOR `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) `else `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [60:0] p; reg [60:0] a; reg [20:0] b; reg [60:0] shifted; always @* begin p = a[60:0] ** b[20:0]; shifted = 2 ** b[20:0]; end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%0x %x %x\n", cyc, p, shifted); `endif // Constant versions `checkh(61'h1 ** 21'h31, 61'h1); `checkh(61'h2 ** 21'h10, 61'h10000); `checkh(61'd10 ** 21'h3, 61'h3e8); `checkh(61'h3 ** 21'h7, 61'h88b); `ifndef VCS `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81); `endif if (cyc==1) begin a <= 61'h0; b <= 21'h0; end if (cyc==2) begin a <= 61'h0; b <= 21'h3; end if (cyc==3) begin a <= 61'h1; b <= 21'h31; end if (cyc==4) begin a <= 61'h2; b <= 21'h10; end if (cyc==5) begin a <= 61'd10; b <= 21'd3; end if (cyc==6) begin a <= 61'd3; b <= 21'd7; end if (cyc==7) begin a <= 61'h7ab3811219; b <= 21'ha6e30; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end case (cyc) 32'd00: ; 32'd01: ; 32'd02: ; // 0^x is indeterminate 32'd03: ; // 0^x is indeterminate 32'd04: `checkh(p, 61'h1); 32'd05: `checkh(p, 61'h10000); 32'd06: `checkh(p, 61'h3e8); 32'd07: `checkh(p, 61'h88b); 32'd08: `checkh(p, 61'h01ea58c703687e81); 32'd09: `checkh(p, 61'h01ea58c703687e81); default: $stop; endcase case (cyc) 32'd00: ; 32'd01: ; 32'd02: `checkh(shifted, 61'h0000000000000001); 32'd03: `checkh(shifted, 61'h0000000000000008); 32'd04: `checkh(shifted, 61'h0002000000000000); 32'd05: `checkh(shifted, 61'h0000000000010000); 32'd06: `checkh(shifted, 61'h0000000000000008); 32'd07: `checkh(shifted, 61'h0000000000000080); 32'd08: `checkh(shifted, 61'h0000000000000000); 32'd09: `checkh(shifted, 61'h0000000000000000); default: $stop; endcase end endmodule verilator-4.038/test_regress/t/t_interface_array_bad.v0000664000177100017500000000220613702133370023145 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Demonstrate deferred linking error messages // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; endinterface function integer the_other_func (input integer val); return val; endfunction module t (/*AUTOARG*/); localparam N = 4; foo_intf foos [N-1:0] (); logic [ 7 : 0 ] bar; // Non-constant dotted select is not allowed assign foos[bar].a = 1'b1; baz baz_inst (); // Unsure how to produce V3Param AstCellRef visitor errors //assign baz_inst.x = 1'b1; //assign baz_inst.N = 1'b1; //assign baz_inst.7 = 1'b1; //assign baz_inst.qux_t = 1'b1; //assign baz_inst.the_func = 1'b1; //assign baz_inst.the_lp = 1'b1; //assign bar.x = 1'b1; //assign fake_inst.x = 1'b1; //assign the_other_func.x = 1'b1; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module baz; typedef integer qux_t; function integer the_func (input integer val); return val; endfunction localparam the_lp = 5; endmodule verilator-4.038/test_regress/t/t_array_index_increment.v0000664000177100017500000000502313702133367023560 0ustar wsnyderwsnydermodule t (/*AUTOARG*/ // Inputs clk ); input clk; string test_string = "abcd"; int array3d[2][3][4] = '{ '{ '{ 0, 1, 2, 3}, '{ 4, 5, 6, 7}, '{ 8, 9, 10, 11} }, '{ '{ 12, 13, 14, 15}, '{ 16, 17, 18, 19}, '{ 20, 21, 22, 23} } }; int pos; int val; int i; byte b; int data[4] = '{1, 2, 3, 4}; generate genvar j; int gdata[4]; for (j=0; j < 5; j++) begin initial if (j >= 5) $stop; end for (j=0; j < 5; ++j) begin initial if (j >= 5) $stop; end for (j=10; j >= 5; j--) begin initial if (j < 5) $stop; end for (j=10; j >= 5; --j) begin initial if (j < 5) $stop; end endgenerate initial begin pos = 0; pos++; if (pos != 1) $stop; array3d[0][0][0]++; if (array3d[0][0][0] != 1) $stop; --array3d[0][0][0]; if (array3d[0][0][0] != 0) $stop; pos = 2; b = test_string[--pos]; if (b !== "b") $stop; if (pos !== 1) $stop; pos = 1; b = test_string[++pos]; if (b !== "c") $stop; if (pos !== 2) $stop; pos = 3; b = test_string[pos--]; if (b !== "d") $stop; if (pos !== 2) $stop; pos = 0; b = test_string[pos++]; if (b !== "a") $stop; if (pos !== 1) $stop; pos = 0; val = array3d[++pos][--pos][++pos]; if (pos !== 1) $stop; if (val !== 13) $stop; pos = 0; val = array3d[++pos][pos--][++pos]; if (pos !== 1) $stop; if (val !== 17) $stop; for (i=0; data[++i]<4;) begin // loop with multiple statements pos = i; val = data[i]; end if (pos !== 2) $stop; if (i !== 3) $stop; if (val !== 3) $stop; i = 0; while (data[i++]<4) begin // loop with multiple statements pos = i; val = data[i]; end if (pos !== 3) $stop; if (i !== 4) $stop; if (val !== 4) $stop; pos = 0; if (1 == 1) begin pos++; end if (pos != 1) $stop; pos = 0; if (1 == 1) pos++; if (pos != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_mod_recurse.pl0000775000177100017500000000105313702133370021660 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_waiveroutput.out0000664000177100017500000000110513702133370022316 0ustar wsnyderwsnyder// DESCRIPTION: Verilator output: Waivers generated with --waiver-output `verilator_config // Below you find suggested waivers. You have three options: // 1. Fix the reason for the linter warning // 2. Keep the waiver permanently if you are sure this is okay // 3. Keep the waiver temporarily to suppress the output // lint_off -rule WIDTH -file "*t/t_waiveroutput.v" -match "Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits." // lint_off -rule UNUSED -file "*t/t_waiveroutput.v" -match "Signal is not used: 'width_warn'" verilator-4.038/test_regress/t/t_mod_interface_array2_noinl.pl0000775000177100017500000000116113702133370024627 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_mod_interface_array2.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_tree_inl1_pub0.pl0000775000177100017500000000222113702133370023214 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_tree.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( v_flags2 => ["$Self->{t_dir}/t_inst_tree_inl1_pub0.vlt"], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, expect => '\] (%m|.*t\.ps): Clocked ', ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_packed_struct_fst.out0000664000177100017500000000151213702133370024427 0ustar wsnyderwsnyder$date Sun Apr 19 04:15:38 2020 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var int 32 " cnt $end $var parameter 96 # v(0) $end $var parameter 96 $ v(1) $end $var parameter 96 % v(2) $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000000000000000000000000000000 " b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 # b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $ b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 % #10 b00000000000000000000000000000001 " 1! #15 0! #20 1! b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " #35 0! #40 1! verilator-4.038/test_regress/t/t_order_multidriven.pl0000775000177100017500000000124513702133370023111 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, v_flags2 => ["--trace --exe $Self->{t_dir}/t_order_multidriven.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_life.v0000664000177100017500000000452413702133370020775 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // Life analysis checks reg [15:0] life; // Ding case reg [7:0] din; reg [15:0] fixin; always @* begin fixin = {din[7:0],din[7:0]}; case (din[1:0]) 2'b00: begin fixin = {fixin[14:0], 1'b1}; if (cyc==101) $display("Prevent ?: optimization a"); end 2'b01: begin fixin = {fixin[13:0], 2'b11}; if (cyc==101) $display("Prevent ?: optimization b"); end 2'b10: begin fixin = {fixin[12:0], 3'b111}; if (cyc==101) $display("Prevent ?: optimization c"); end 2'b11: begin fixin = {fixin[11:0], 4'b1111}; if (cyc==101) $display("Prevent ?: optimization d"); end endcase end always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==1) begin life = 16'h8000; // Dropped life = 16'h0010; // Used below if (life != 16'h0010) $stop; // life = 16'h0020; // Used below if ($time < 10000) if (life != 16'h0020) $stop; // life = 16'h8000; // Dropped if ($time > 100000) begin if ($time != 0) $stop; // Prevent conversion to ?: life = 16'h1030; end else life = 16'h0030; if (life != 16'h0030) $stop; // life = 16'h0040; // Not dropped, no else below if ($time > 100000) life = 16'h1040; if (life != 16'h0040) $stop; // life = 16'h8000; // Dropped if ($time > 100000) begin life = 16'h1050; if (life != 0) $stop; // Ignored, as set is first end else begin if ($time > 100010) life = 16'h1050; else life = 16'h0050; end if (life != 16'h0050) $stop; end if (cyc==2) begin din <= 8'haa; end if (cyc==3) begin din <= 8'hfb; if (fixin != 16'h5557) $stop; end if (cyc==4) begin din <= 8'h5c; if (fixin != 16'hbfbf) $stop; end if (cyc==5) begin din <= 8'hed; if (fixin != 16'hb8b9) $stop; end if (cyc==6) begin if (fixin != 16'hb7b7) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_lint_implicit_port.pl0000775000177100017500000000105213702133370023254 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( verilator_flags2 => ["-Wno-IMPLICIT"], ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_vecgen1.pl0000775000177100017500000000116513702133367021544 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_clk_vecgen1.v"); compile( v_flags2 => ['+define+T_TEST1',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_writemem_b.gold5.mem0000664000177100017500000000014213702133370023550 0ustar wsnyderwsnyder000010 000011 000100 000101 000110 000111 010000 000000 000000 000000 010100 010101 000000 000000 verilator-4.038/test_regress/t/t_case_wild.pl0000775000177100017500000000105313702133367021311 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_slice_conc_bad.v0000664000177100017500000000474613702133370022761 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // bug354 typedef logic [5:0] data_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire rst; data_t iii_in = crc[5:0]; data_t jjj_in = crc[11:6]; data_t iii_out; data_t jjj_out; logic [1:0] ctl0 = crc[63:62]; aaa aaa (.*); // Aggregate outputs into a single result vector wire [63:0] result = {64'h0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; rst <= 1'b0; end else if (cyc<10) begin sum <= 64'h0; rst <= 1'b1; end else if (cyc<90) begin rst <= 1'b0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module bbb ( output data_t ggg_out[1:0], input data_t ggg_in [1:0], input [1:0] [1:0] ctl, input logic clk, input logic rst ); genvar i; generate for (i=0; i<2; i++) begin: PPP always_ff @(posedge clk) begin if (rst) begin ggg_out[i] <= 6'b0; end else begin if (ctl[i][0]) begin if (ctl[i][1]) begin ggg_out[i] <= ~ggg_in[i]; end else begin ggg_out[i] <= ggg_in[i]; end end end end end endgenerate endmodule module aaa ( input data_t iii_in, input data_t jjj_in, input [1:0] ctl0, output data_t iii_out, output data_t jjj_out, input logic clk, input logic rst ); // Below is a bug; {} concat isn't used to make arrays bbb bbb ( .ggg_in ({jjj_in, iii_in}), .ggg_out ({jjj_out, iii_out}), .ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}), .*); endmodule verilator-4.038/test_regress/t/t_gen_local.pl0000775000177100017500000000105313702133370021274 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_vpi_sc.cpp0000664000177100017500000000062013702133370020777 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include "Vt_vpi_sc.h" VM_PREFIX* tb = NULL; int sc_main(int argc, char* argv[]) { tb = new VM_PREFIX("tb"); VL_PRINTF("*-* All Finished *-*\n"); tb->final(); return 0; } verilator-4.038/test_regress/t/t_preproc_inc2.vh0000664000177100017500000000046613702133370021744 0ustar wsnyderwsnyder// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 At file `__FILE__ line `__LINE__ `define INCFILE `include `INCFILE verilator-4.038/test_regress/t/t_func_dotted_inl0.vlt0000664000177100017500000000041513702133370022761 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config public -module "global_mod" public -module "m*" verilator-4.038/test_regress/t/t_func_unit.pl0000775000177100017500000000105313702133370021343 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_interface_array3.out0000664000177100017500000000054713702133370023631 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_mod_interface_array3.v:25:20: Unsupported: Multidimensional cells/interfaces. 25 | a_if iface [2:0][1:0]; | ^ %Error-UNSUPPORTED: t/t_mod_interface_array3.v:27:18: Unsupported: Multidimensional cells/interfaces. 27 | sub i_sub[2:0][1:0] (.s(str)); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_unsup_deassign.pl0000775000177100017500000000105613702133370023431 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only --bbox-unsup"], ); ok(1); 1; verilator-4.038/test_regress/t/t_mem.pl0000775000177100017500000000105313702133370020127 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_const.pl0000775000177100017500000000105313702133367020505 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_mp_func.pl0000775000177100017500000000105313702133370023020 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_index.v0000664000177100017500000000212213702133370021644 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); // surefire lint_off NBAJAM input clk; reg [7:0] _ranit; reg [2:0] a; reg [7:0] vvector; reg [7:0] vvector_flip; // surefire lint_off STMINI initial _ranit = 0; always @ (posedge clk) begin a <= a + 3'd1; vvector[a] <= 1'b1; // This should use "old" value for a vvector_flip[~a] <= 1'b1; // This should use "old" value for a // //======== if (_ranit==8'd0) begin _ranit <= 8'd1; $write("[%0t] t_select_index: Running\n", $time); vvector <= 0; vvector_flip <= 0; a <= 3'b1; end else _ranit <= _ranit + 8'd1; // if (_ranit==8'd3) begin $write("%x %x\n",vvector,vvector_flip); if (vvector !== 8'b0000110) $stop; if (vvector_flip !== 8'b0110_0000) $stop; // $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_flag_timescale_override2.pl0000775000177100017500000000127513702133370024277 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_timescale_override.v"); compile( verilator_flags2 => ["-timescale-override /1us"], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_packed_sysfunct.pl0000775000177100017500000000105313702133370024142 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_alw_split_cond.v0000664000177100017500000000242413702133367022212 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1604 module t (/*AUTOARG*/ // Outputs two, // Inputs clk, aresetn, ten ); input wire clk; input wire aresetn; input reg [9:0] ten; output reg [1:0] two; // Passes with this //output reg [1:0] rx; //output reg [1:0] ry; function [1:0] func ( input [1:0] p0_x, input [1:0] p0_y, input [1:0] p1_x, input [1:0] p1_y, input [1:0] sel); reg [1:0] rx; reg [1:0] ry; `ifdef NOT_DEF // This way works rx = sel == 2'b10 ? p1_x : p0_x; ry = sel == 2'b10 ? p1_y : p0_y; `else // This way fails to compile if (sel == 2'b10) begin rx = p1_x; ry = p1_y; end else begin rx = p0_x; ry = p0_y; end `endif // Note rx and ry are unused //func = rx | ry; // Also passes func = 0; endfunction always @(*) begin two = func( ten[8 +: 2], ten[6 +: 2], ten[4 +: 2], ten[2 +: 2], ten[0 +: 2]); end endmodule verilator-4.038/test_regress/t/t_metacmt_onoff.pl0000775000177100017500000000111013702133370022164 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_public_func.vlt0000664000177100017500000000040613702133370023210 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config public -module "glbl" -function "setGSR" verilator-4.038/test_regress/t/t_mem_slice.pl0000775000177100017500000000105313702133370021306 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_task_bad.v0000664000177100017500000000055213702133370021766 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); initial begin if (task_as_func(1'b0)) $stop; end task task_as_func; input ign; endtask endmodule verilator-4.038/test_regress/t/t_class_class.v0000664000177100017500000000143513702133367021504 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Note UVM internals do not require classes-in-classes package P; class Cls; int imembera; int imemberb; class SubCls; int smembera; int smemberb; endclass : SubCls SubCls sc; endclass : Cls endpackage : P module t (/*AUTOARG*/); P::Cls c; initial begin c = new; c.imembera = 10; c.imemberb = 20; c.sc = new; c.sc.smembera = 30; c.sc.smemberb = 40; if (c.imembera != 10) $stop; if (c.imemberb != 20) $stop; if (c.sc.smembera != 30) $stop; if (c.sc.smemberb != 40) $stop; end endmodule verilator-4.038/test_regress/t/t_vpi_memory.v0000664000177100017500000000256513702133370021377 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function integer mon_check(); `endif module t (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */; integer i, status; // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop; end for (i = 16; i > 0; i--) if (mem0[i] !== i) begin $write("%%Error: %d : GOT = %d EXP = %d\n", i, mem0[i], i); status = 1; end if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-4.038/test_regress/t/t_math_cmp.v0000664000177100017500000001052413702133370020773 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [2:0] index_a; reg [2:0] index_b; prover #(4) p4 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(32) p32 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(63) p63 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(64) p64 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(72) p72 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(126) p126 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(128) p128 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); integer cyc; initial cyc=0; initial index_a = 3'b0; initial index_b = 3'b0; always @* begin index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4; index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4; end always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module prover ( input clk, input [2:0] index_a, input [2:0] index_b ); parameter WIDTH = 4; reg signed [WIDTH-1:0] as; reg signed [WIDTH-1:0] bs; wire [WIDTH-1:0] b = bs; always @* begin casez (index_a) 3'd0: as = {(WIDTH){1'd0}}; // 0 3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv 3'd3: as = {(WIDTH){1'd1}}; // -1 3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv default: $stop; endcase casez (index_b) 3'd0: bs = {(WIDTH){1'd0}}; // 0 3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv 3'd3: bs = {(WIDTH){1'd1}}; // -1 3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv default: $stop; endcase end reg [7:0] results[4:0][4:0]; wire gt = as>b; wire gts = as>bs; wire gte = as>=b; wire gtes = as>=bs; wire lt = as2) begin `ifdef TEST_VERBOSE $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n", index_a, index_b, gt, gts, gte, gtes, lt, lts, lte, ltes); `endif exp = results[index_a][index_b]; got = {gt, gts, gte, gtes, lt, lts, lte, ltes}; if (exp !== got) begin $display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp); $stop; end end end // Result table initial begin // Indexes: 0, 1, -1, 127, -128 // Gt Gts Gte Gtes Lt Lts Lte Ltes results[0][0] = 8'b0_0_1_1_0_0_1_1; results[0][1] = 8'b0_0_0_0_1_1_1_1; results[0][2] = 8'b0_0_1_1_0_0_1_1; results[0][3] = 8'b0_1_0_1_1_0_1_0; results[0][4] = 8'b0_1_0_1_1_0_1_0; results[1][0] = 8'b1_1_1_1_0_0_0_0; results[1][1] = 8'b0_0_1_1_0_0_1_1; results[1][2] = 8'b1_1_1_1_0_0_0_0; results[1][3] = 8'b0_1_0_1_1_0_1_0; results[1][4] = 8'b0_1_0_1_1_0_1_0; results[2][0] = 8'b0_0_1_1_0_0_1_1; results[2][1] = 8'b0_0_0_0_1_1_1_1; results[2][2] = 8'b0_0_1_1_0_0_1_1; results[2][3] = 8'b0_1_0_1_1_0_1_0; results[2][4] = 8'b0_1_0_1_1_0_1_0; results[3][0] = 8'b1_0_1_0_0_1_0_1; results[3][1] = 8'b1_0_1_0_0_1_0_1; results[3][2] = 8'b1_0_1_0_0_1_0_1; results[3][3] = 8'b0_0_1_1_0_0_1_1; results[3][4] = 8'b1_1_1_1_0_0_0_0; results[4][0] = 8'b1_0_1_0_0_1_0_1; results[4][1] = 8'b1_0_1_0_0_1_0_1; results[4][2] = 8'b1_0_1_0_0_1_0_1; results[4][3] = 8'b0_0_0_0_1_1_1_1; results[4][4] = 8'b0_0_1_1_0_0_1_1; end endmodule verilator-4.038/test_regress/t/t_savable_class_bad.out0000664000177100017500000000012313702133370023147 0ustar wsnyderwsnyder%Error-UNSUPPORTED: Unsupported: --savable with dynamic new %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_array_nocolon.v0000664000177100017500000000324413702133370024071 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Mike Popoloski. // SPDX-License-Identifier: CC0-1.0 interface foo_intf ( input x ); endinterface module foo_subm ( input x ); endmodule module t (); localparam N = 3; wire [2:0] X = 3'b110; // Should not cause LITENDIAN warning, as no harm in array selections. // verilator lint_on LITENDIAN foo_intf foo1 [N] (.x(1'b1)); foo_subm sub1 [N] (.x(1'b1)); // Will cause LITENDIAN warning? // verilator lint_off LITENDIAN foo_intf foos [N] (.x(X)); foo_intf fool [1:3] (.x(X)); foo_intf foom [3:1] (.x(X)); foo_subm subs [N] (.x(X)); foo_subm subl [1:3] (.x(X)); foo_subm subm [3:1] (.x(X)); initial begin // Check numbering with 0 first // NC has a bug here if (foos[0].x !== 1'b1) $stop; if (foos[1].x !== 1'b1) $stop; if (foos[2].x !== 1'b0) $stop; // if (fool[1].x !== 1'b1) $stop; if (fool[2].x !== 1'b1) $stop; if (fool[3].x !== 1'b0) $stop; // if (foom[1].x !== 1'b0) $stop; if (foom[2].x !== 1'b1) $stop; if (foom[3].x !== 1'b1) $stop; // if (subs[0].x !== 1'b1) $stop; if (subs[1].x !== 1'b1) $stop; if (subs[2].x !== 1'b0) $stop; // if (subl[1].x !== 1'b1) $stop; if (subl[2].x !== 1'b1) $stop; if (subl[3].x !== 1'b0) $stop; // if (subm[1].x !== 1'b0) $stop; if (subm[2].x !== 1'b1) $stop; if (subm[3].x !== 1'b1) $stop; // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_cdc_async_bad.out0000664000177100017500000000147113702133367022310 0ustar wsnyderwsnyder%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:28:21: Logic in path that feeds async reset, via signal: 't.rst2_bad_n' 28 | wire rst2_bad_n = rst0_n | rst1_n; | ^ ... Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message. %Warning-CDCRSTLOGIC: See details in obj_vlt/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53:21: Logic in path that feeds async reset, via signal: 't.rst6a_bad_n' 53 | wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); | ^ %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:54:21: Logic in path that feeds async reset, via signal: 't.rst6b_bad_n' 54 | wire rst6b_bad_n = rst6_bad_n ^ $c1("1"); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_parameter_access.v0000664000177100017500000000534013702133370024524 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Interface parameter getter // // A test of the import parameter used with modport // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader // SPDX-License-Identifier: CC0-1.0 interface test_if #(parameter integer FOO = 1); // Interface variable logic data; // Modport modport mp( import getFoo, output data ); function integer getFoo (); return FOO; endfunction endinterface // test_if function integer identity (input integer x); return x; endfunction module t (/*AUTOARG*/ // Inputs clk ); input clk; test_if #( .FOO (identity(5)) ) the_interface (); test_if #( .FOO (identity(7)) ) array_interface [1:0] (); testmod testmod_i (.clk (clk), .intf (the_interface), .intf_no_mp (the_interface), .intf_array (array_interface) ); localparam THE_TOP_FOO = the_interface.FOO; localparam THE_TOP_FOO_BITS = $bits({the_interface.FOO, the_interface.FOO}); localparam THE_ARRAY_FOO = array_interface[0].FOO; initial begin if (THE_TOP_FOO != 5) begin $display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO); $stop; end if (THE_TOP_FOO_BITS != 64) begin $display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS); $stop; end if (THE_ARRAY_FOO != 7) begin $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); $stop; end end endmodule module testmod ( input clk, test_if.mp intf, test_if intf_no_mp, test_if.mp intf_array [1:0] ); localparam THE_FOO = intf.FOO; localparam THE_OTHER_FOO = intf_no_mp.FOO; localparam THE_ARRAY_FOO = intf_array[0].FOO; always @(posedge clk) begin if (THE_FOO != 5) begin $display("%%Error: THE_FOO = %0d", THE_FOO); $stop; end if (THE_OTHER_FOO != 5) begin $display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO); $stop; end if (THE_ARRAY_FOO != 7) begin $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); $stop; end if (intf.FOO != 5) begin $display("%%Error: intf.FOO = %0d", intf.FOO); $stop; end if (intf_no_mp.FOO != 5) begin $display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO); $stop; end if (intf_array[0].FOO != 7) begin $display("%%Error: intf_array[0].FOO = %0d", intf_array[0].FOO); $stop; end // if (i.getFoo() != 5) begin // $display("%%Error: i.getFoo() = %0d", i.getFoo()); // $stop; // end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_array_fst.pl0000775000177100017500000000131513702133370022522 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_trace_array.v"); compile( verilator_flags2 => ['--cc --trace-fst --trace-structs'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_pp_display.v0000664000177100017500000000437513702133370021356 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire d1 = 1'b1; wire d2 = 1'b1; wire d3 = 1'b1; wire o1,o2,o3; add1 add1 (d1,o1); add2 add2 (d2,o2); `define ls left_side `define rs right_side `define noarg na//note extra space `define thru(x) x `define thruthru `ls `rs // Doesn't expand `define msg(x,y) `"x: `\`"y`\`"`" `define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string initial begin //$display(`msg( \`, \`)); // Illegal $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); $display(`msg(left side,right side)); $display(`msg( left side , right side )); $display(`msg( `ls , `rs )); $display(`msg( `noarg , `rs )); $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); $display(`msg(`noarg,`noarg`noarg)); $display(`msg( `thruthru , `thruthru )); // Results vary between simulators $display(`left(`msg( left side , right side ), left_replaced)); //$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error `ifndef VCS // Sim bug - wrong number of arguments, but we're right $display(`msg(`thru(),)); // Empty `endif $display(`msg(`thru(left side),`thru(right side))); $display(`msg( `thru( left side ) , `thru( right side ) )); `ifndef NC $display(`"standalone`"); `endif `ifdef VERILATOR // Illegal on some simulators, as the "..." crosses two lines `define twoline first \ second $display(`msg(twoline, `twoline)); `endif $display("Line %0d File \"%s\"",`__LINE__,`__FILE__); //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. $write("*-* All Finished *-*\n"); $finish; end endmodule `define ADD_UP(a,c) \ wire tmp_``a = a; \ wire tmp_``c = tmp_``a + 1; \ assign c = tmp_``c ; module add1 ( input wire d1, output wire o1); `ADD_UP(d1,o1) // expansion is OK endmodule module add2 ( input wire d2, output wire o2); `ADD_UP( d2 , o2 ) // expansion is bad endmodule // `ADD_UP( \d3 , \o3 ) // This really is illegal verilator-4.038/test_regress/t/t_verilated_all.pl0000775000177100017500000000372713702133370022172 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); my $root = ".."; compile( # Can't use --coverage and --savable together, so cheat and compile inline verilator_flags2 => ["--cc", "--coverage-toggle --coverage-line --coverage-user", "--trace --vpi ", ($Self->cfg_with_threaded ? "--threads 2 $root/include/verilated_threads.cpp" : ""), ($Self->cfg_with_threaded ? "--trace-threads 1" : ""), "$root/include/verilated_save.cpp"], ); execute( check_finished => 1, ); my %hit; foreach my $file (glob("$root/include/*.cpp $root/include/*.h")) { $file =~ s!.*/!!; # This file isn't actually used by the runtime (though # it might be in the future? hence it's under include/) # It is used to build verilator. if ($file =~ /verilated_unordered_set_map\.h/) { next; } print "NEED: $file\n" if $Self->{verbose}; $hit{$file} = 0; } foreach my $dfile (glob("$Self->{obj_dir}/*.d")) { my $wholefile = file_contents($dfile); foreach my $file (split /\s+/, $wholefile) { $file =~ s!.*/!!; print "USED: $file\n" if $Self->{verbose}; $hit{$file} = 1; } } foreach my $file (sort keys %hit) { if (!$hit{$file} && $file !~ /_sc/ && $file !~ /_fst/ && ($file !~ /_thread/ || $Self->cfg_with_threaded)) { error("Include file not covered by t_verilated_all test: ",$file); } } ok(1); 1; verilator-4.038/test_regress/t/t_order_first.v0000664000177100017500000000261713702133370021531 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs fastclk ); input fastclk; t_netlist tnetlist (.also_fastclk (fastclk), /*AUTOINST*/ // Inputs .fastclk (fastclk)); endmodule module t_netlist (/*AUTOARG*/ // Inputs fastclk, also_fastclk ); // surefire lint_off ASWEMB input fastclk; input also_fastclk; integer _mode; initial _mode = 0; // This entire module should optimize to nearly nothing... // verilator lint_off UNOPTFLAT reg [4:0] a,a2,b,c,d,e; // verilator lint_on UNOPTFLAT initial a=5'd1; always @ (posedge fastclk) begin b <= a+5'd1; c <= b+5'd1; // Better for ordering if this moves before previous statement end // verilator lint_off UNOPT always @ (d or /*AS*/a or c) begin e = d+5'd1; a2 = a+5'd1; // This can be pulled out of the middle of the always d = c+5'd1; // Better for ordering if this moves before previous statement end // verilator lint_on UNOPT always @ (posedge also_fastclk) begin if (_mode==5) begin if (a2 != 5'd2) $stop; if (e != 5'd5) $stop; $write("*-* All Finished *-*\n"); $finish; end _mode <= _mode + 1; end endmodule verilator-4.038/test_regress/t/t_param_array2.v0000664000177100017500000000104613702133370021562 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam int c[4] = '{5, 6, 7, 8}; a #(.p(c)) i_a (); endmodule module a #( parameter int p[4] = '{1, 2, 3, 4} ); initial begin if (p[0] != 5) $stop; if (p[1] != 6) $stop; if (p[2] != 7) $stop; if (p[3] != 8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_queue_unsup_bad.out0000664000177100017500000000637413702133370022741 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_queue_unsup_bad.v:21:11: Unsupported: Replication to form 'string[$]' data type : ... In instance t 21 | q = {"q", "b", "c", "d", "e", "f"}; | ^ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:24:9: Unsupported: Queue .delete(index) method, as is O(n) complexity and slow. : ... In instance t 24 | q.delete(1); | ^~~~~~ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:28:9: Unsupported: Queue .insert method, as is O(n) complexity and slow. : ... In instance t 28 | q.insert(2, "ins2"); | ^~~~~~ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:34:11: Unsupported: Replication to form 'string[$]' data type : ... In instance t 34 | q = {q, "f1"}; | ^ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:35:11: Unsupported: Replication to form 'string[$]' data type : ... In instance t 35 | q = {q, "f2"}; | ^ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:36:11: Unsupported: Replication to form 'string[$]' data type : ... In instance t 36 | q = {"b1", q}; | ^ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:37:11: Unsupported: Replication to form 'string[$]' data type : ... In instance t 37 | q = {"b2", q}; | ^ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:38:11: Unsupported: Replication to form 'string[$]' data type : ... In instance t 38 | q = {q[0], q[2:$]}; | ^ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:38:22: Unsupported/illegal unbounded ('$') in this context. : ... In instance t 38 | q = {q[0], q[2:$]}; | ^ %Error: t/t_queue_unsup_bad.v:38:22: First value of [a:b] isn't a constant, maybe you want +: or -: : ... In instance t 38 | q = {q[0], q[2:$]}; | ^ %Error: t/t_queue_unsup_bad.v:38:19: Illegal range select; type already selected, or bad dimension: data type is 'string[$]' : ... In instance t 38 | q = {q[0], q[2:$]}; | ^ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:42:25: Unsupported: Replication to form 'string[$]' data type : ... In instance t 42 | string ai[$] = { "Foo", "Bar" }; | ^ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:47:14: Unsupported: Assignment pattern applies against non struct/union data type: 'string[$]' : ... In instance t 47 | q = '{ "BB", "CC" }; | ^~ %Error-UNSUPPORTED: t/t_queue_unsup_bad.v:50:14: Unsupported: Replication to form 'string[$]' data type : ... In instance t 50 | q = { "BB", "CC" }; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_top_bad.pl0000775000177100017500000000107613702133370023006 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_detectarray_1.pl0000775000177100017500000000114613702133370022103 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-Wno-CLKDATA", "-Wno-UNOPTFLAT"] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_vpi_c.cpp0000664000177100017500000000346413702133370021643 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2011 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include "svdpi.h" #include "vpi_user.h" //====================================================================== #define NEED_EXTERNS #ifdef NEED_EXTERNS extern "C" { extern void dpii_check(); } #endif //====================================================================== void show(vpiHandle obj) { const char* namep; if (obj) { namep = vpi_get_str(vpiName, obj); } else { namep = "global"; } s_vpi_time t; t.type = vpiSimTime; vpi_get_time(obj, &t); vpi_printf(const_cast("%s vpiSimTime = %d,%d"), namep, (int)t.high, (int)t.low); // Should be same value as vpiSimTime, just converted to real t.type = vpiScaledRealTime; vpi_get_time(obj, &t); vpi_printf(const_cast(" vpiScaledRealTime = %g\n"), t.real); // These will both print the precision, because the 0 asks for global scope int u = vpi_get(vpiTimeUnit, obj); int p = vpi_get(vpiTimePrecision, obj); vpi_printf(const_cast("%s vpiTimeUnit = %d"), namep, u); vpi_printf(const_cast(" vpiTimePrecision = %d\n"), p); } void dpii_check() { show(0); vpiHandle mod = vpi_handle_by_name((PLI_BYTE8*)"top.t", NULL); if (!mod) { vpi_printf(const_cast("-- Cannot vpi_find module\n")); } else { show(mod); } } verilator-4.038/test_regress/t/t_lint_realcvt_bad.pl0000775000177100017500000000117113702133370022646 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wwarn-REALCVT"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_cc.cpp0000664000177100017500000000451313702133370022155 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #include "verilatedos.h" #include VM_PREFIX_INCLUDE #include "Vt_trace_two_b.h" #include "verilated.h" #ifdef TEST_HDR_TRACE # ifdef TEST_FST # include "verilated_fst_c.h" # else # include "verilated_vcd_c.h" # endif #endif // Compile in place #include "Vt_trace_two_b.cpp" #include "Vt_trace_two_b__Slow.cpp" #include "Vt_trace_two_b__Syms.cpp" #include "Vt_trace_two_b__Trace.cpp" #include "Vt_trace_two_b__Trace__Slow.cpp" VM_PREFIX* ap; Vt_trace_two_b* bp; vluint64_t main_time = 0; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); Verilated::traceEverOn(true); srand48(5); ap = new VM_PREFIX("topa"); bp = new Vt_trace_two_b("topb"); #ifdef TEST_HDR_TRACE Verilated::traceEverOn(true); # ifdef TEST_FST VerilatedFstC* tfp = new VerilatedFstC; ap->trace(tfp, 99); bp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.fst"); # else VerilatedVcdC* tfp = new VerilatedVcdC; ap->trace(tfp, 99); bp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); # endif #endif #ifdef TEST_HDR_TRACE ap->eval_step(); bp->eval_step(); ap->eval_end_step(); bp->eval_end_step(); if (tfp) tfp->dump(main_time); #endif { ap->clk = false; main_time += 10; } while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { ap->clk = !ap->clk; bp->clk = ap->clk; ap->eval_step(); bp->eval_step(); ap->eval_end_step(); bp->eval_end_step(); #ifdef TEST_HDR_TRACE if (tfp) tfp->dump(main_time); #endif main_time += 5; } if (!Verilated::gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } ap->final(); bp->final(); #ifdef TEST_HDR_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete ap, ap); VL_DO_DANGLING(delete bp, bp); exit(0L); } verilator-4.038/test_regress/t/t_enum_size.v0000664000177100017500000000222213702133370021175 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off WIDTH typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs; typedef enum integer {UP=0, UW=1'b1} UNSIZED; // verilator lint_on WIDTH localparam LEN = 3; localparam COL = 4; localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P) ,LEN'(S), LEN'(E), LEN'(W), LEN'(P) ,LEN'(S), LEN'(N), LEN'(W), LEN'(P) ,LEN'(S), LEN'(N), LEN'(E), LEN'(P) ,LEN'(S), LEN'(N), LEN'(E), LEN'(W)}; bit [59:0] SE2 = {N, E, W, P ,S, E, W, P ,S, N, W, P ,S, N, E, P ,S, N, E, W}; initial begin if (SEQ != 60'o32104210431043204321) $stop; if (SE2 != 60'o32104210431043204321) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_package_dimport.v0000664000177100017500000000312113702133370022327 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package defs; function automatic integer max; input integer a; input integer b; max = (a > b) ? a : b; endfunction function automatic integer log2; input integer value; value = value >> 1; for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1; endfunction function automatic integer ceil_log2; input integer value; value = value - 1; for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1) value = value >> 1; endfunction endpackage module sub(); import defs::*; parameter RAND_NUM_MAX = ""; localparam DATA_RANGE = RAND_NUM_MAX + 1; localparam DATA_WIDTH = ceil_log2(DATA_RANGE); localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1)); endmodule module t(/*AUTOARG*/ // Inputs clk ); import defs::*; parameter WHICH = 0; parameter MAX_COUNT = 10; localparam MAX_EXPONENT = log2(MAX_COUNT); localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1); input clk; generate if (WHICH == 1) begin : which_true sub sub_true(); defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT; end else begin : which_false sub sub_false(); defparam sub_false.RAND_NUM_MAX = MAX_COUNT; end endgenerate endmodule verilator-4.038/test_regress/t/t_dpi_arg_output_type.pl0000775000177100017500000000256413702133370023447 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Geza Lore. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if ($Self->{nc}) { # For NC, compile twice, first just to generate DPI headers compile( nc_flags2 => ["+ncdpiheader+$Self->{obj_dir}/dpi-exp.h", "+ncdpiimpheader+$Self->{obj_dir}/dpi-imp.h"] ); } compile( v_flags2 => ["t/t_dpi_arg_output_type.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME"], # NC: Gdd the obj_dir to the C include path nc_flags2 => ["+ncscargs+-I$Self->{obj_dir}"], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2 => ["-dpiheader $Self->{obj_dir}/dpi.h", "-ccflags -I$Self->{obj_dir}"], ); if ($Self->{vlt_all}) { files_identical( "$Self->{obj_dir}/Vt_dpi_arg_output_type__Dpi.h", "t/t_dpi_arg_output_type__Dpi.out" ); } execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ms_pli => 0 ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_overwide_bad.out0000664000177100017500000000254513702133370023240 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_inst_overwide.v:23:14: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. : ... In instance t 23 | .outy_w92 (outc_w30), | ^~~~~~~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. : ... In instance t 24 | .outz_w22 (outd_w73), | ^~~~~~~~ %Warning-WIDTH: t/t_inst_overwide.v:27:14: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. : ... In instance t 27 | .inw_w31 (ina_w1), | ^~~~~~~ %Warning-WIDTH: t/t_inst_overwide.v:28:14: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. : ... In instance t 28 | .inx_w11 (inb_w61) | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_clk_concat_vlt.pl0000775000177100017500000000256313702133367022353 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_clk_concat.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( verilator_flags2 => ["t/t_clk_concat.vlt"], ); if ($Self->{vlt_all}) { file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_noval_bad.pl0000775000177100017500000000107413702133370022461 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_file.pl0000775000177100017500000000115413702133370021130 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => [$Self->wno_unopthreads_for_few_cores()] ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_prot_lib_clk_gated.pl0000775000177100017500000000453713702133370023172 0ustar wsnyderwsnyder#!/usr/bin/env perl # Makes the test run with tracing enabled by default, can be overridden # with --notrace unshift(@ARGV, "--trace"); if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Todd Strader. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios( vlt => 1, xsim => 1, ); $Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark}; top_filename("t/t_prot_lib.v"); my $secret_prefix = "secret"; my $secret_dir = "$Self->{obj_dir}/$secret_prefix"; mkdir $secret_dir; while (1) { # Always compile the secret file with Verilator no matter what simulator # we are testing with run(logfile => "$secret_dir/vlt_compile.log", cmd => ["perl", "$ENV{VERILATOR_ROOT}/bin/verilator", "--prefix", "Vt_prot_lib_secret", "-cc", "-Mdir", $secret_dir, "-GGATED_CLK=1", "--protect-lib", $secret_prefix, "t/t_prot_lib_secret.v"], verilator_run => 1, ); last if $Self->{errors}; run(logfile => "$secret_dir/secret_gcc.log", cmd=>[$ENV{MAKE}, "-C", $secret_dir, "-f", "Vt_prot_lib_secret.mk"]); last if $Self->{errors}; compile( verilator_flags2 => ["$secret_dir/secret.sv", "-GGATED_CLK=1", "-LDFLAGS", "$secret_prefix/libsecret.a"], xsim_flags2 => ["$secret_dir/secret.sv"], ); execute( check_finished => 1, xsim_run_flags2 => ["--sv_lib", "$secret_dir/libsecret", "--dpi_absolute"], ); if ($Self->{vlt} && $Self->{trace}) { # We can see the ports of the secret module file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/); # but we can't see what's inside file_grep_not("$Self->{obj_dir}/simx.vcd", qr/secret_/); } ok(1); last; } 1; verilator-4.038/test_regress/t/t_var_static.pl0000775000177100017500000000123613702133370021513 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( expect_filename => $Self->{golden_filename}, fails => $Self->{vlt_all} # Verilator unsupported, bug546 ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_func_gen.v0000664000177100017500000000164413702133370020772 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2012 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; genvar g; logic [1:0] mask = 0; generate for (g=0; g<2; g++) begin : picker logic block_passed = 0; // Just for visualizing V3LinkDot debug function [3:0] pick; input [3:0] randnum; pick = randnum+g[3:0]; endfunction always @(posedge clk) begin if (pick(3)!=3+g[3:0]) $stop; else mask[g] = 1'b1; if (mask == 2'b11) begin // All iterations must be finished $write("*-* All Finished *-*\n"); $finish; end end end endgenerate endmodule verilator-4.038/test_regress/t/t_interface_mp_func_noinl.pl0000775000177100017500000000115613702133370024223 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_mp_func.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_pindup_bad.out0000664000177100017500000000251313702133370022677 0ustar wsnyderwsnyder%Warning-PINMISSING: t/t_lint_pindup_bad.v:19:4: Cell has missing pin: 'exists' 19 | sub (.o(o), | ^~~ ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_lint_pindup_bad.v:21:10: Duplicate pin connection: 'i' 21 | .i(i2), | ^ t/t_lint_pindup_bad.v:20:10: ... Location of original pin connection 20 | .i(i), | ^ %Error: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist' : ... Suggested alternative: 'exists' 22 | .nexist(i2) | ^~~~~~ %Error: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST' : ... Suggested alternative: 'EXIST' 16 | .NEXIST(1), | ^~~~~~ %Error: t/t_lint_pindup_bad.v:17:9: Duplicate parameter pin connection: 'P' 17 | .P(2), | ^ t/t_lint_pindup_bad.v:15:8: ... Location of original parameter pin connection 15 | #(, | ^ %Error: t/t_lint_pindup_bad.v:18:9: Duplicate parameter pin connection: 'P' 18 | .P(3)) | ^ t/t_lint_pindup_bad.v:15:8: ... Location of original parameter pin connection 15 | #(, | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_dpi_export_context_bad.out0000664000177100017500000000027013702133370024271 0ustar wsnyderwsnyder%Error: unknown:0: Testbench C called 'dpix_task' but scope wasn't set, perhaps due to dpi import call without 'context', or missing svSetScope. See IEEE 1800-2017 35.5.3. Aborting... verilator-4.038/test_regress/t/t_var_bad_sv.pl0000775000177100017500000000111313702133370021454 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_huge_sub.v0000664000177100017500000004016513702133367022011 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub (/*AUTOARG*/ // Outputs outa, outb, outc, // Inputs index ); input [7:0] index; output [9:0] outa; output [1:0] outb; output outc; // ============================= /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [9:0] outa; reg [1:0] outb; reg outc; // End of automatics // ============================= // Created from perl // for $i (0..1023) { printf "\t10'h%03x: begin outa = 10'h%03x; outb = 2'b%02b; outc = 1'b%d; end\n", $i, rand(1024),rand(4),rand(2); }; always @(/*AS*/index) begin case (index) 8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end 8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end 8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end 8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end 8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end 8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end 8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end 8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end 8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end 8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end 8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end 8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end 8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end 8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end 8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end 8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end 8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end 8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end 8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end 8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end 8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end 8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end 8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end 8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end 8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end 8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end 8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end 8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end 8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end 8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end 8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end 8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end 8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end 8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end 8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end 8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end 8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end 8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end 8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end 8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end 8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end 8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end 8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end 8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end 8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end 8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end 8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end 8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end 8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end 8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end 8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end 8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end 8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end 8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end 8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end 8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end 8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end 8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end 8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end 8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end 8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end 8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end 8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end 8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end 8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end 8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end 8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end 8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end 8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end 8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end 8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end 8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end 8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end 8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end 8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end 8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end 8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end 8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end 8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end 8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end 8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end 8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end 8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end 8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end 8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end 8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end 8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end 8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end 8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end 8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end 8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end 8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end 8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end 8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end 8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end 8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end 8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end 8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end 8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end 8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end 8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end 8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end 8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end 8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end 8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end 8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end 8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end 8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end 8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end 8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end 8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end 8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end 8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end 8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end 8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end 8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end 8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end 8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end 8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end 8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end 8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end 8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end 8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end 8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end 8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end 8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end 8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end 8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end 8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end 8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end 8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end 8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end 8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end 8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end 8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end 8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end 8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end 8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end 8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end 8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end 8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end 8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end 8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end 8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end 8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end 8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end 8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end 8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end 8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end 8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end 8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end 8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end 8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end 8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end 8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end 8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end 8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end 8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end 8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end 8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end 8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end 8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end 8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end 8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end 8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end 8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end 8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end 8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end 8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end 8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end 8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end 8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end 8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end 8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end 8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end 8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end 8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end 8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end 8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end 8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end 8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end 8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end 8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end 8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end 8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end 8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end 8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end 8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end 8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end 8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end 8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end 8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end 8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end 8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end 8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end 8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end 8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end 8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end 8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end 8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end 8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end 8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end 8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end 8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end 8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end 8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end 8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end 8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end 8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end 8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end 8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end 8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end 8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end 8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end 8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end 8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end 8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end 8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end 8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end 8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end 8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end 8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end 8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end 8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end 8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end 8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end 8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end 8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end 8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end 8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end 8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end 8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end 8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end 8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end 8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end 8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end 8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end 8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end 8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end 8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end 8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end 8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end 8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end 8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end 8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end 8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end 8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end 8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end 8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end 8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end 8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end 8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end 8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end 8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end 8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end 8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end endcase end endmodule verilator-4.038/test_regress/t/t_udp_bad.pl0000775000177100017500000000120113702133370020742 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only --bbox-unsup"], fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_public.pl0000775000177100017500000000102513702133370021504 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Compile only test compile( ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_compass_bad.out0000664000177100017500000000036013702133370022673 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_tri_compass_bad.v:16:12: Unsupported: tristate in top-level IO: '__pinNumber1' : ... In instance t 16 | sub sub(i, o); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_pp_pragma_bad.v0000664000177100017500000000033613702133370021757 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `pragma verilator-4.038/test_regress/t/t_slice_init.pl0000775000177100017500000000105313702133370021473 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_unsup_bad.v0000664000177100017500000000212613702133367022355 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 virtual interface vi_t vi; virtual vi_t vi2; typedef class c; typedef interface class ic; class C #(parameter P=1); localparam LOCPAR = 10; int imember; static int istatic; local int loc; protected int prot; rand int irand; randc int icrand; task classtask; endtask function int classfunc; endfunction virtual function void func_virtual; endfunction pure virtual function void func_pure_virtual; automatic function void func_automatic; endfunction const function void func_const; endfunction extern task exttask; endclass virtual class VC; endclass module t (/*AUTOARG*/); endmodule typedef class uvm_root; typedef class uvm_coreservice_t; class uvm_default_coreservice_t extends uvm_coreservice_t; virtual function uvm_root get_root(); uvm_root::m_forward_task_call(); return uvm_root::m_uvm_get_root(); endfunction endclass verilator-4.038/test_regress/t/t_func_outp.pl0000775000177100017500000000105313702133370021353 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_array_nocolon_bad.v0000664000177100017500000000123113702133370024671 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Mike Popoloski. // SPDX-License-Identifier: CC0-1.0 interface foo_intf ( input x ); endinterface module foo_subm ( input x ); endmodule module t (); localparam N = 3; wire [2:0] X = 3'b110; // Will cause LITENDIAN warning? foo_intf foos [N] (.x(X)); // bad foo_intf fool [1:3] (.x(X)); // bad foo_intf foom [3:1] (.x(X)); // ok foo_subm subs [N] (.x(X)); // bad foo_subm subl [1:3] (.x(X)); // bad foo_subm subm [3:1] (.x(X)); // ok endmodule verilator-4.038/test_regress/t/t_process.pl0000775000177100017500000000117613702133370021035 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_elab.v0000664000177100017500000000122513702133367021473 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 module t; localparam str = "string"; function logic checkParameter(input logic [8:0] N); $display("x is %d.", N); if (N == 1) return 0; $fatal(1, "Parameter %d is invalid...%s and %s", N, str, "constant both work"); endfunction `ifdef FAILING_ASSERTIONS localparam x = checkParameter(5); `else localparam x = checkParameter(1); `endif initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_real_param.v0000664000177100017500000000155613702133370021313 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module foo #( parameter real bar = 2.0) (); endmodule module t(); genvar m, r; generate for (m = 10; m <= 20; m+=10) begin : gen_m for (r = 0; r <= 1; r++) begin : gen_r localparam real lparam = m + (r + 0.5); initial begin if (lparam != foo_inst.bar) begin $display("%m: lparam != foo_inst.bar (%f, %f)", lparam, foo_inst.bar); $stop(); end end foo #(.bar (lparam)) foo_inst (); end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_flag_relinc_dir/0000775000177100017500000000000013702335701022117 5ustar wsnyderwsnyderverilator-4.038/test_regress/t/t_flag_relinc_dir/include/0000775000177100017500000000000013702335701023542 5ustar wsnyderwsnyderverilator-4.038/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh0000664000177100017500000000061413702133370026670 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define all_finished $write("*-* All Finished *-*\n") verilator-4.038/test_regress/t/t_flag_relinc_dir/chip/0000775000177100017500000000000013702335701023042 5ustar wsnyderwsnyderverilator-4.038/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v0000664000177100017500000000074113702133370026672 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `include "../include/t_flag_relinc.vh" module t_flag_relinc_sub (); initial begin `all_finished; $finish; end endmodule verilator-4.038/test_regress/t/t_interface_size_bad.out0000664000177100017500000000121313702133370023340 0ustar wsnyderwsnyder%Error: t/t_interface_size_bad.v:16:20: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 4. : ... In instance t 16 | baz baz4_inst (.foo(foo4)); | ^~~ %Error: t/t_interface_size_bad.v:17:20: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 6. : ... In instance t 17 | baz baz6_inst (.foo(foo6)); | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_struct_notfound_bad.v0000664000177100017500000000061013702133370023244 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); typedef struct packed { bit m; } struct_t; struct_t s; initial begin s.nfmember = 0; // Member not found $finish; end endmodule verilator-4.038/test_regress/t/t_trace_ena_sc.pl0000775000177100017500000000167413702133370021770 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); if (!$Self->have_sc) { skip("No SystemC installed"); } else { top_filename("t/t_trace_ena.v"); compile( verilator_flags2 => ['-trace -sc'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { # Note more checks in _cc.pl file_grep ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); } } ok(1); 1; verilator-4.038/test_regress/t/t_param_circ_bad.pl0000775000177100017500000000107413702133370022262 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_build_bad2.pl0000775000177100017500000000165113702133370022335 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_make_cmake.v"); compile( verilator_make_cmake => 0, verilator_make_gmake => 0, # Need --no-print-directory so golden file doesn't compare directory names verilator_flags2 => ["--build --MAKEFLAGS --no-print-directory" ." --MAKEFLAGS illegal-flag-to-fail-make"], fails => 1, # Recursive make breaks the golden compare #expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_lib.pl0000775000177100017500000000113113702133370021127 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ['-v', 't/t_func_lib_sub.v'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dynarray_bad.v0000664000177100017500000000053613702133370021644 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); integer a[]; string s; initial begin s = "str"; a = new [s]; // Bad end endmodule verilator-4.038/test_regress/t/t_unopt_combo_bad.pl0000775000177100017500000000130313702133370022501 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_unopt_combo.v"); compile( v_flags2 => ['+define+ATTRIBUTES'], fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); execute( ) if !$Self->{vlt_all}; ok(1); 1; verilator-4.038/test_regress/t/t_select_lhs_oob2.v0000664000177100017500000000630313702133370022251 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [63:0] out; // From test of Test.v // End of automatics wire reset_l = ~(cyc<15); wire [63:0] d = crc[63:0]; wire [8:0] t_wa = crc[8:0]; wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]}; Test test (/*AUTOINST*/ // Outputs .out (out[63:0]), // Inputs .clk (clk), .reset_l (reset_l), .t_wa (t_wa[8:0]), .d (d[63:0]), .t_addr (t_addr[8:0])); // Aggregate outputs into a single result vector wire [63:0] result = {out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h421a41d1541ea652 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, reset_l, t_wa, d, t_addr ); input clk; input reset_l; reg [63:0] m_w0 [47:0]; reg [63:0] m_w1 [23:0]; reg [63:0] m_w2 [23:0]; reg [63:0] m_w3 [23:0]; reg [63:0] m_w4 [23:0]; reg [63:0] m_w5 [23:0]; input [8:0] t_wa; input [63:0] d; always @ (posedge clk) begin if (~reset_l) begin : blk integer i; for (i=0; i<48; i=i+1) begin m_w0[i] <= 64'h0; end for (i=0; i<24; i=i+1) begin m_w1[i] <= 64'h0; m_w2[i] <= 64'h0; m_w3[i] <= 64'h0; m_w4[i] <= 64'h0; m_w5[i] <= 64'h0; end end else begin casez (t_wa[8:6]) 3'd0: m_w0[t_wa[5:0]] <= d; 3'd1: m_w1[t_wa[4:0]] <= d; 3'd2: m_w2[t_wa[4:0]] <= d; 3'd3: m_w3[t_wa[4:0]] <= d; 3'd4: m_w4[t_wa[4:0]] <= d; default: m_w5[t_wa[4:0]] <= d; endcase end end input [8:0] t_addr; wire [63:0] t_w0 = m_w0[t_addr[5:0]]; wire [63:0] t_w1 = m_w1[t_addr[4:0]]; wire [63:0] t_w2 = m_w2[t_addr[4:0]]; wire [63:0] t_w3 = m_w3[t_addr[4:0]]; wire [63:0] t_w4 = m_w4[t_addr[4:0]]; wire [63:0] t_w5 = m_w5[t_addr[4:0]]; output reg [63:0] out; always @* begin casez (t_addr[8:6]) 3'd0: out = t_w0; 3'd1: out = t_w1; 3'd2: out = t_w2; 3'd3: out = t_w3; 3'd4: out = t_w4; default: out = t_w5; endcase end endmodule verilator-4.038/test_regress/t/t_interface.pl0000775000177100017500000000105313702133370021311 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_inc_notfound_bad.pl0000775000177100017500000000107413702133370024401 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_bad_hide.v0000664000177100017500000000051213702133370021742 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum { HIDE_VALUE = 0 } hide_enum_t; module t; typedef enum { HIDE_VALUE = 0 } hide_enum_t; endmodule verilator-4.038/test_regress/t/t_vams_kwd_bad.pl0000775000177100017500000000115113702133370021771 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, verilator_flags2 => ["--error-limit 1000"], expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_wideconst.pl0000775000177100017500000000112013702133370022400 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['-public'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_hdr_sc.out0000664000177100017500000000371513702133370023062 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Sat Feb 29 09:18:19 2020 $end $timescale 1ps $end $scope module topa $end $scope module t $end $var wire 32 3 c_trace_on [31:0] $end $var wire 1 # clk $end $var wire 32 + cyc [31:0] $end $scope module sub $end $var wire 32 ; inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $scope module t $end $var wire 32 ^ c_trace_on [31:0] $end $var wire 1 > clk $end $var wire 32 V cyc [31:0] $end $var real 64 F r $end $scope module sub $end $var wire 32 f inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 + b00000000000000000000000000000000 3 b00000000000000000000000000000001 ; 0> r0 F b00000000000000000000000000000001 V b00000000000000000000000000000000 ^ b00000000000000000000000000000010 f #10000 1# b00000000000000000000000000000010 + b00000000000000000000000000000011 3 1> r0.1 F #15000 0# 0> #20000 1# b00000000000000000000000000000011 + b00000000000000000000000000000100 3 1> r0.2 F #25000 0# 0> #30000 1# b00000000000000000000000000000100 + b00000000000000000000000000000101 3 1> r0.3 F #35000 0# 0> #40000 1# b00000000000000000000000000000101 + b00000000000000000000000000000110 3 1> r0.4 F #45000 0# 0> #50000 1# b00000000000000000000000000000110 + b00000000000000000000000000000111 3 1> r0.5 F #55000 0# 0> #60000 1# b00000000000000000000000000000111 + b00000000000000000000000000001000 3 1> r0.6 F #65000 0# 0> #70000 1# b00000000000000000000000000001000 + b00000000000000000000000000001001 3 1> r0.7 F #75000 0# 0> #80000 1# b00000000000000000000000000001001 + b00000000000000000000000000001010 3 1> r0.7999999999999999 F #85000 0# 0> #90000 1# b00000000000000000000000000001010 + b00000000000000000000000000001011 3 1> r0.8999999999999999 F #95000 0# 0> #100000 1# 1> b00000000000000000000000000001011 + b00000000000000000000000000001100 3 r0.9999999999999999 F verilator-4.038/test_regress/t/t_var_dotted1_inl1.pl0000775000177100017500000000117513702133370022515 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_var_dotted1.v"); compile( v_flags2 => ['+define+USE_INLINE',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_param_array4.pl0000775000177100017500000000105313702133370021733 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_graph.v0000664000177100017500000000101413702133370021154 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Unsupported tristate construct error // // This is a compile only regression test of tristate handling for bug514 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [11:0] ck; assign ck[1:0] = {1'bz,{1{1'b0}}}; test i_test (.clk (ck[1:0])); endmodule module test (clk); output wire [1:0] clk; endmodule // test verilator-4.038/test_regress/t/t_xml_flat.out0000664000177100017500000001602613702133370021356 0ustar wsnyderwsnyder verilator-4.038/test_regress/t/t_inst_recurse_bad.pl0000775000177100017500000000107413702133370022667 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_pipe_exit_bad.pf0000664000177100017500000000071313702133370022136 0ustar wsnyderwsnyder#!/usr/bin/env perl use warnings; # DESCRIPTION: Verilator: Verilog Test example --pipe-filter script # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 die "%Error: t_pipe_exit_bad.pf: Intentional bad exit status...\n"; verilator-4.038/test_regress/t/t_past_bad.out0000664000177100017500000000110413702133370021314 0ustar wsnyderwsnyder%Error: t/t_past_bad.v:12:11: $past tick value must be constant (IEEE 1800-2017 16.9.3) : ... In instance t 12 | if ($past(d, 0)) $stop; | ^~~~~ %Warning-TICKCOUNT: t/t_past_bad.v:13:20: $past tick value of 10000 may have a large performance cost : ... In instance t 13 | if ($past(d, 10000)) $stop; | ^~~~~ ... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_func_void_bad.pl0000775000177100017500000000107413702133370022136 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_array.v0000664000177100017500000000160313702133370021723 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package TEST_TYPES; typedef struct packed { logic stuff; } a_struct_t; endpackage // TEST_TYPES module t(clk); input clk; TEST_TYPES::a_struct_t [3:0] a_out; sub sub (.a_out); always @ (posedge clk) begin if (a_out[0] != 1'b0) $stop; if (a_out[1] != 1'b1) $stop; if (a_out[2] != 1'b0) $stop; if (a_out[3] != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub(a_out); parameter n = 4; output TEST_TYPES::a_struct_t [n-1:0] a_out; always_comb begin for (int i=0;i 1); top_filename("t/t_uniqueif.v"); compile( v_flags2 => ['+define+FAILING_ASSERTION3'], verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], fails => $Self->{nc}, ); execute( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_xml_output.v0000664000177100017500000000042213702133370021417 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m (input clk); // verilator tag foo_op endmodule verilator-4.038/test_regress/t/t_array_type_methods.pl0000775000177100017500000000105313702133367023261 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_dumporder_bad.v0000664000177100017500000000064313702133370023171 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); initial begin // Check error when this missing: $dumpfile("/should/not/be/opened"); $dumpvars; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_pp_dupdef_bad.pl0000775000177100017500000000113313702133370022124 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_pp_dupdef.v"); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_if_deep.v0000664000177100017500000001353713702133370020605 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'h966e272fd829e672 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output [31:0] out; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [31:0] out; // End of automatics `ifdef verilator `define dontOptimize $c1("1") `else `define dontOptimize 1'b1 `endif always @(posedge clk) begin out <= in; if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (in[0]) out <= ~in; end endmodule verilator-4.038/test_regress/t/t_vlcov_merge.out0000664000177100017500000000046013343101620022045 0ustar wsnyderwsnyder# SystemC::Coverage-3 C 'CoverPoint0ffile1.sphl159' 0 C 'CoverPoint1ffile1.sphl159' 1 C 'CoverPoint2ffile1.sphl159' 20 C 'CoverPoint3ffile1.sphl159' 0 C 'CoverPoint4ffile1.sphl159' 1 C 'CoverPoint5ffile1.sphl159' 9 C 'CoverPoint6ffile1.sphl159' 22 verilator-4.038/test_regress/t/t_time_vpi_1ns1ns.out0000664000177100017500000000121213702133370022556 0ustar wsnyderwsnyder:: In top.t Time scale of t is 1ns / 1ns [60] time%0d=60 123%0t=123 dig%0t=5432109877 dig%0d=5432109877 rdig%0t=5432109876 rdig%0f=5432109876.543210 [60.000000ns] time%0d=60 123%0t=123.000000ns dig%0t=5432109877.000000ns dig%0d=5432109877 rdig%0t=5432109876.543210ns rdig%0f=5432109876.543210 [60.000000ns] stime%0t=60.000000ns stime%0d=60 stime%0f=60.000000 [60.000000ns] rtime%0t=60.000000ns rtime%0d=60 rtime%0f=60.000000 global vpiSimTime = 0,60 vpiScaledRealTime = 60 global vpiTimeUnit = -9 vpiTimePrecision = -9 top.t vpiSimTime = 0,60 vpiScaledRealTime = 60 top.t vpiTimeUnit = -9 vpiTimePrecision = -9 *-* All Finished *-* verilator-4.038/test_regress/t/t_init_concat.pl0000775000177100017500000000105313702133370021643 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_cast.pl0000775000177100017500000000105313702133367020311 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_extend.v0000664000177100017500000000341513702133370020473 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); /*verilator public_module*/ input clk; // No verilator_public needed, because it's outside the "" in the $c statement reg [7:0] cyc; initial cyc=0; reg c_worked; reg [8:0] c_wider; wire one = 1'b1; always @ (posedge clk) begin cyc <= cyc+8'd1; // coverage testing if (one) begin end if (!one) begin end if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line if (cyc == 8'd1) begin c_worked <= 0; end if (cyc == 8'd2) begin `ifdef VERILATOR $c("VL_PRINTF(\"Calling $c, calling $c...\\n\");"); $c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");"); c_worked <= $c("my_function()"); c_wider <= $c9("0x10"); `else c_worked <= 1'b1; c_wider <= 9'h10; `endif end if (cyc == 8'd3) begin if (c_worked !== 1'b1) $stop; if (c_wider !== 9'h10) $stop; $finish; end end `ifdef verilator `systemc_header #define DID_INT_HEADER 1 `systemc_interface #ifndef DID_INT_HEADER #error "`systemc_header didn't work" #endif bool m_did_ctor; vluint32_t my_function() { if (!m_did_ctor) vl_fatal(__FILE__, __LINE__, __FILE__, "`systemc_ctor didn't work"); return 1; } `systemc_imp_header #define DID_IMP_HEADER 1 `systemc_implementation #ifndef DID_IMP_HEADER #error "`systemc_imp_header didn't work" #endif `systemc_ctor m_did_ctor = 1; `systemc_dtor printf("In systemc_dtor\n"); printf("*-* All Finished *-*\n"); `verilog // Test verilator comment after a endif `endif // verilator endmodule verilator-4.038/test_regress/t/t_trace_two_a.v0000664000177100017500000000323513702133370021473 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define CONCAT(a, b) a``b `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; integer c_trace_on; sub sub (); // verilator tracing_off string filename; // verilator tracing_on initial begin `ifdef TEST_FST filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.fst"}; `else filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.vcd"}; `endif `ifdef TEST_DUMP $dumpfile(filename); $dumpvars(0, top); $dumplimit(10 * 1024 * 1024); `elsif TEST_DUMPPORTS $dumpports(top, filename); $dumpportslimit(10 * 1024 * 1024, filename); `endif end always @ (posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; c_trace_on <= cyc + 2; if (cyc == 3) begin `ifdef TEST_DUMP $dumpoff; `elsif TEST_DUMPPORTS $dumpportsoff(filename); `endif end else if (cyc == 5) begin `ifdef TEST_DUMP $dumpall; $dumpflush; `elsif TEST_DUMPPORTS $dumpportsall(filename); $dumpportsflush(filename); `endif end else if (cyc == 7) begin `ifdef TEST_DUMP $dumpon; `elsif TEST_DUMPPORTS $dumpportson(filename); `endif end else if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module sub; integer inside_sub_a = 1; endmodule verilator-4.038/test_regress/t/t_mem_multidim.v0000664000177100017500000000573413702133370021674 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off LITENDIAN // verilator lint_off BLKANDNBLK // 3 3 4 reg [71:0] memw [2:0][1:3][5:2]; reg [7:0] memn [2:0][1:3][5:2]; // verilator lint_on BLKANDNBLK integer cyc; initial cyc=0; reg [63:0] crc; reg [71:0] wide; reg [7:0] narrow; reg [1:0] index0; reg [1:0] index1; reg [2:0] index2; integer i0,i1,i2; integer imem[2:0][1:3]; reg [2:0] cstyle[2]; // verilator lint_on LITENDIAN initial begin for (i0=0; i0<3; i0=i0+1) begin for (i1=1; i1<4; i1=i1+1) begin imem[i0[1:0]] [i1[1:0]] = i1; for (i2=2; i2<6; i2=i2+1) begin memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]}; memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001; end end end end reg [71:0] wread; reg wreadb; always @ (posedge clk) begin //$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide); cyc <= cyc + 1; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; narrow <= 8'h0; wide <= 72'h0; index0 <= 2'b0; index1 <= 2'b0; index2 <= 3'b0; end else if (cyc<90) begin index0 <= crc[1:0]; index1 <= crc[3:2]; index2 <= crc[6:4]; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; // We never read past bounds, or get unspecific results // We also never read lowest indexes, as writing outside of range may corrupt them if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin narrow <= ({narrow[6:0], narrow[7]^narrow[0]} ^ {memn[index0][index1][index2]}); wread = memw[index0][index1][index2]; wreadb = memw[index0][index1][index2][2]; wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread); //$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread); end // We may write past bounds of memory memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0]; memn[index0][index1][index2] <= {~crc[6:0],crc[7]}; memw[index0][index1][index2] <= {~crc[7:0],crc}; //$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc}); cstyle[cyc[0]] <= cyc[2:0]; if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop; end else if (cyc==90) begin memn[0][1][3] <= memn[0][1][3] ^ 8'ha8; end else if (cyc==91) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n",$time, cyc, crc, narrow, wide); if (crc != 64'h65e3bddcd9bc2750) $stop; if (narrow != 8'hca) $stop; if (wide != 72'h4edafed31ba6873f73) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_uniqueif_fail1.pl0000775000177100017500000000142613702133370022256 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_uniqueif.v"); compile( v_flags2 => ['+define+FAILING_ASSERTION1'], verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], fails => $Self->{nc}, ); execute( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_alw_split.pl0000775000177100017500000000126713702133367021364 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats"], ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 3); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unoptflat_simple_bad.pl0000775000177100017500000000111013702133370023536 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_unoptflat_simple.v"); # Compile only compile( fails => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_sv.pl0000775000177100017500000000105313702133370021036 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unopt_combo_isolate_vlt.pl0000775000177100017500000000347113702133370024310 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_unopt_combo.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( verilator_flags2 => ["--stats $Self->{t_dir}/t_unopt_combo_isolate.vlt"], ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( ); ok(1); 1; verilator-4.038/test_regress/t/t_var_bad_sv.out0000664000177100017500000000106613702133370021654 0ustar wsnyderwsnyder%Error: t/t_var_bad_sv.v:8:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language. 8 | reg do; | ^~ %Error: t/t_var_bad_sv.v:9:14: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. 9 | mod mod (.do(bar)); | ^~ %Error: t/t_var_bad_sv.v:9:16: syntax error, unexpected '(', expecting ')' 9 | mod mod (.do(bar)); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_verilated_threaded.pl0000775000177100017500000000150213702133370023167 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); top_filename("t/t_verilated_all.v"); my $root = ".."; compile( # Can't use --coverage and --savable together, so cheat and compile inline verilator_flags2 => ["--cc --coverage-toggle --coverage-line --coverage-user --trace --threads 1 --vpi $root/include/verilated_save.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_array_modport.v0000664000177100017500000000125013702133370024101 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Connecting an interface array slice to a module's portmap // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; modport m(input a); endinterface module foo_mod ( foo_intf foo, foo_intf.m bars[4] ); endmodule module t (/*AUTOARG*/); localparam N = 4; foo_intf foos [N-1:0] (); foo_intf bars [N] (); //foo_intf foos (); foo_mod foo_mod ( .foo (foos[2]), .bars (bars) //.foo (foos) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_var_pins_sc32.pl0000775000177100017500000000471613702133370022035 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_var_pinsizes.v"); compile( verilator_flags2 => ["-sc -no-pins64 --trace --exe $Self->{t_dir}/t_var_pinsizes.cpp $Self->{t_dir}/t_var_pinsizes.vlt"], make_main => 0, ); { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ i32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv1_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ ibv16_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ o32;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv1_vlt;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ obv16_vlt;/x); } execute(); ok(1); 1; verilator-4.038/test_regress/t/t_string.v0000664000177100017500000000604313702133370020512 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [4*8:1] vstr; const string s = "a"; // Check static assignment string s2; string s3; reg eq; byte unpack1[0:4]; // Operators == != < <= > >= {a,b} {a{b}} a[b] // a.len, a.putc, a.getc, a.toupper, a.tolower, a.compare, a.icompare, a.substr // a.atoi, a.atohex, a.atooct, a.atobin, a.atoreal, // a.itoa, a.hextoa, a.octoa, a.bintoa, a.realtoa initial begin $sformat(vstr, "s=%s", s); `checks(vstr, "s=a"); `checks(string'(vstr), "s=a"); `checks(s, "a"); `checks({s,s,s}, "aaa"); `checks({4{s}}, "aaaa"); // Constification `checkh(s == "a", 1'b1); `checkh(s == "b", 1'b0); `checkh(s != "a", 1'b0); `checkh(s != "b", 1'b1); `checkh(s > " ", 1'b1); `checkh(s > "a", 1'b0); `checkh(s >= "a", 1'b1); `checkh(s >= "b", 1'b0); `checkh(s < "a", 1'b0); `checkh(s < "b", 1'b1); `checkh(s <= " ", 1'b0); `checkh(s <= "a", 1'b1); `ifndef VCS `ifndef VERILATOR `ifndef NC // IEEE 1800-2017 5.9 assignment to byte array unpack1 = "five"; `checkh(unpack1[0], "f"); `checkh(unpack1[1], "i"); `checkh(unpack1[2], "v"); `checkh(unpack1[3], "e"); `checkh(unpack1[4], 8'h0); `endif `endif `endif end // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup s2 = "c0"; end else if (cyc==1) begin $sformat(vstr, "s2%s", s2); `checks(vstr, "s2c0"); end else if (cyc==2) begin s3 = s2; $sformat(vstr, "s2%s", s3); `checks(vstr, "s2c0"); end else if (cyc==3) begin s2 = "a"; s3 = "b"; end else if (cyc==4) begin `checks({s2,s3}, "ab"); `checks({3{s3}}, "bbb"); `checkh(s == "a", 1'b1); `checkh(s == "b", 1'b0); `checkh(s != "a", 1'b0); `checkh(s != "b", 1'b1); `checkh(s > " ", 1'b1); `checkh(s > "a", 1'b0); `checkh(s >= "a", 1'b1); `checkh(s >= "b", 1'b0); `checkh(s < "a", 1'b0); `checkh(s < "b", 1'b1); `checkh(s <= " ", 1'b0); `checkh(s <= "a", 1'b1); end // String character references else if (cyc==10) begin s2 = "astring"; end else if (cyc==11) begin `checks(s2, "astring"); `checkh(s2.len(), 7); `checkh(s2[1], "s"); s2[0] = "0"; s2[3] = "3"; `checks(s2, "0st3ing"); end // else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_assoc_pattern_unsup.out0000664000177100017500000000051613702133367023652 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_assoc_pattern_unsup.v:19:11: Unsupported: Assignment pattern applies against non struct/union data type: 'string[string]' : ... In instance t 19 | a = '{ "f": "fooed", "b": "bared", default: "defaulted" }; | ^~ %Error: Exiting due to verilator-4.038/test_regress/t/t_sys_readmem_bad_addr.mem0000664000177100017500000000054413702133370023625 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @121212 10 verilator-4.038/test_regress/t/t_flag_csplit.pl0000775000177100017500000001003513702133370021640 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); while (1) { # Thi rule requires GNU make > 4.1 (or so, known broken in 3.81) #%__Slow.o: %__Slow.cpp # $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< if (make_version() < 4.1) { skip("Test requires GNU Make version >= 4.1"); last; } compile( v_flags2 => ["--trace --output-split 1 --output-split-cfuncs 1 --exe ../$Self->{main_filename}"], verilator_make_gmake => 0, ); # We don't use the standard test_regress rules, as want to test the rules # properly build run(logfile => "$Self->{obj_dir}/vlt_gcc.log", tee => $self->{verbose}, cmd=>[$ENV{MAKE}, "-C ".$Self->{obj_dir}, "-f $Self->{VM_PREFIX}.mk", "-j 4", "VM_PREFIX=$Self->{VM_PREFIX}", "TEST_OBJ_DIR=$Self->{obj_dir}", "CPPFLAGS_DRIVER=-D".uc($Self->{name}), ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1":""), "OPT_FAST=-O2", "OPT_SLOW=-O0", "OPT_GLOBAL=-Os", ($param{make_flags}||""), ]); execute( check_finished => 1, ); # Splitting should set VM_PARALLEL_BUILDS to 1 by default file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}_classes.mk", qr/VM_PARALLEL_BUILDS\s*=\s*1/); check_splits(); check_no_all_file(); check_gcc_flags("$Self->{obj_dir}/vlt_gcc.log"); ok(1); last; } 1; sub check_splits { my $got1; my $gotSyms1; foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { if ($file =~ /Syms__1/) { $gotSyms1 = 1; } elsif ($file =~ /__1/) { $got1 = 1; } check_cpp($file); } $got1 or error("No __1 split file found"); $gotSyms1 or error("No Syms__1 split file found"); } sub check_no_all_file { foreach my $file (glob("$Self->{obj_dir}/*.cpp")) { if ($file =~ qr/__ALL.cpp/) { error("__ALL.cpp file found: $file"); } } } sub check_cpp { my $filename = shift; my $size = -s $filename; printf " File %6d %s\n", $size, $filename if $Self->{verbose}; my $fh = IO::File->new("<$filename") or error("$! $filenme"); my @funcs; while (defined (my $line = $fh->getline)) { if ($line =~ /^(void|IData)\s+(.*::.*)/) { my $func = $2; $func =~ s/\(.*$//; print "\tFunc $func\n" if $Self->{verbose}; if ($func !~ /::_eval_initial_loop$/ && $func !~ /::__Vconfigure$/ && $func !~ /::trace$/ && $func !~ /::traceInit$/ && $func !~ /::traceFull$/ ) { push @funcs, $func; } } } if ($#funcs > 0) { error("Split had multiple functions in $filename\n\t".join("\n\t",@funcs)); } } sub check_gcc_flags { my $filename = shift; my $fh = IO::File->new("<$filename") or error("$! $filenme"); while (defined (my $line = $fh->getline)) { chomp $line; print ":log: $line\n" if $Self->{verbose}; if ($line =~ /$Self->{VM_PREFIX}\S*\.cpp/) { my $filetype = ($line =~ /Slow|Syms/) ? "slow":"fast"; my $opt = ($line !~ /-O2/) ? "slow":"fast"; print "$filetype, $opt, $line\n" if $Self->{verbose}; if ($filetype ne $opt) { error("${filetype} file compiled as if was ${opt}: $line"); } } elsif ($line =~ /\.cpp/ and $line !~ /-Os/) { error("library file not compiled with OPT_GLOBAL: $line"); } } } verilator-4.038/test_regress/t/t_clk_first.pl0000775000177100017500000000123013702133367021334 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( verilator_flags2 => ["+define+ATTRIBUTES=1"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_set.v0000664000177100017500000000225113702133370021333 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [63:0] inwide; reg [39:0] addr; integer cyc; initial cyc=1; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write ("%x %x\n", cyc, addr); `endif if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin addr <= 40'h12_3456_7890; end if (cyc==2) begin if (addr !== 40'h1234567890) $stop; addr[31:0] <= 32'habcd_efaa; end if (cyc==3) begin if (addr !== 40'h12abcdefaa) $stop; addr[39:32] <= 8'h44; inwide <= 64'hffeeddcc_11334466; end if (cyc==4) begin if (addr !== 40'h44abcdefaa) $stop; addr[31:0] <= inwide[31:0]; end if (cyc==5) begin if (addr !== 40'h4411334466) $stop; $display ("Flip [%x]\n", inwide[3:0]); addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}]; end if (cyc==6) begin if (addr !== 40'h4411334426) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/TestVpi.h0000664000177100017500000000235313702133367020247 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2013-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "vpi_user.h" //====================================================================== class TestVpiHandle { /// For testing, etc, wrap vpiHandle in an auto-releasing class vpiHandle m_handle; bool m_free; public: TestVpiHandle() : m_handle(NULL) , m_free(true) {} TestVpiHandle(vpiHandle h) : m_handle(h) , m_free(true) {} ~TestVpiHandle() { if (m_handle && m_free) { { vpi_free_object(m_handle); m_handle = NULL; } } } operator vpiHandle() const { return m_handle; } inline TestVpiHandle& operator=(vpiHandle h) { m_handle = h; return *this; } TestVpiHandle& nofree() { m_free = false; return *this; } }; verilator-4.038/test_regress/t/t_assert_synth_off.pl0000775000177100017500000000140013702133367022733 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_synth.v"); compile( v_flags2 => ['+define+FAILING_FULL', '+define+FAILING_PARALLEL', '+define+FAILING_OH', '+define+FAILING_OC', ], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_outfirst.v0000664000177100017500000000547713702133370022110 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define DDIFF_BITS 9 `define AOA_BITS 8 `define HALF_DDIFF `DDIFF_BITS'd256 `define MAX_AOA `AOA_BITS'd255 `define BURP_DIVIDER 9'd16 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0]; wire reset = (cyc<7); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .AOA_B (AOA_B[`AOA_BITS-1:0]), // Inputs .DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]), .reset (reset), .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {56'h0, AOA_B}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3a74e9d34771ad93 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs AOA_B, // Inputs DDIFF_B, reset, clk ); input [`DDIFF_BITS-1:0] DDIFF_B; input reset; input clk; output reg [`AOA_BITS-1:0] AOA_B; reg [`AOA_BITS-1:0] AOA_NEXT_B; reg [`AOA_BITS-1:0] tmp; always @(posedge clk) begin if (reset) begin AOA_B <= 8'h80; end else begin AOA_B <= AOA_NEXT_B; end end always @* begin // verilator lint_off WIDTH tmp = ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER); t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER)); // verilator lint_on WIDTH end task t_aoa_update; output [`AOA_BITS-1:0] aoa_reg_next; input [`AOA_BITS-1:0] aoa_reg; input [`AOA_BITS-1:0] aoa_delta_update; begin if ((`MAX_AOA-aoa_reg) 1); # This is a compile only test. compile( v_flags2 => ["+systemverilogext+v"], ); ok(1); 1; verilator-4.038/test_regress/t/t_foreach_bad.out0000664000177100017500000000055113702133370021761 0ustar wsnyderwsnyder%Error: t/t_foreach_bad.v:14:7: Syntax error; foreach missing bracketed index variable (IEEE 1800-2017 12.7.3) 14 | foreach (array); | ^~~~~~~ %Error-UNSUPPORTED: t/t_foreach_bad.v:16:21: Unsupported: foreach on non-simple variable reference 16 | foreach (array.array[a]); | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_cellarray.pl0000775000177100017500000000126713702133367021344 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["--stats"], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Gate assign merged\s+(\d+)/i, 28); }; ok(1); 1; verilator-4.038/test_regress/t/t_sys_file_basic_mcd.v0000664000177100017500000000632013702133370023003 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define STR(__s) `"__s`" task automatic fail(string s); begin $display({"FAIL! Reason: ", s}); $stop; end endtask task automatic test1; begin int fd[30], fd_fail, fd_success, fd_close, tmp; for (int i = 0; i < 30; i++) begin // Attempt to allocate 30 MCD descriptors; returned descriptors // should fall within correct range: [1, 30]. tmp = $fopen($sformatf("%s/some_file%0d.dat", `STR(`TEST_OBJ_DIR), i)); fd[i] = tmp; if ((fd[i] == 0) || !$onehot(fd[i])) fail($sformatf("MCD descriptor out of range %d", fd[i])); end // Attempt to allocate another MCD descriptor when all should // be used. We expect this operation to fail and return the // invalid descriptor (0). fd_fail = $fopen($sformatf("%s/another_file.dat", `STR(`TEST_OBJ_DIR))); if (fd_fail != 0) fail("Able to allocate MCD descriptor when fully utilized."); // Return descriptor back to pool fd_close = fd[0]; $fclose(fd_close); // Re-attempt MCD allocation; should pass at this point. fd_success = $fopen($sformatf("%s/yet_another_file.dat", `STR(`TEST_OBJ_DIR))); if (fd_success == 0) fail("Expect to have free descriptors at this point."); // Returned descriptor should have a value matching that which // had previously just been returned back to the pool. if (fd_success != fd[0]) fail("Descriptor has incorrect value."); // Return all descriptors back to the pool. for (int i = 1; i < 30; i++) begin fd_close = fd[i]; $fclose(fd_close); end end endtask task automatic test2; begin // Validate basic MCD functionality. integer fd[3], fd_all, tmp; for (int i = 0; i < 3; i++) begin tmp = $fopen($sformatf("%s/t_sys_file_basic_mcd_test2_%0d.dat", `STR(`TEST_OBJ_DIR), i)); fd[i] = tmp; end fd_all = 0; for (int i = 0; i < 3; i++) fd_all |= fd[i]; $fwrite(fd_all, "Scotland is the greatest country.\n"); $fwrite(fd_all, "All other countries are inferior.\n"); $fwrite(fd_all, "Woe betide those to stand against the mighty Scottish nation.\n"); $fclose(fd_all); end endtask task automatic test3; begin // Write some things to standard output. $fwrite(32'h8000_0001, "Sean Connery was the best Bond.\n"); end endtask task automatic test4; begin int fd; // Wide filename fd = $fopen({`STR(`TEST_OBJ_DIR), "some_very_large_filename_that_no_one_would_ever_use_", "except_to_purposefully_break_my_beautiful_code.dat"}); if (fd == 0) fail("Long filename could not be opened."); $fclose(fd); end endtask initial begin // Test1: Validate file descriptor region. test1; // Test2: Validate basic MCD functionality. test2; // Test3: Validate explicit descriptor ID test3; // Test4: Validate filename lengths test4; $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end // initial begin `undef STR endmodule // t verilator-4.038/test_regress/t/t_assert_synth_parallel.vlt0000664000177100017500000000042013702133367024145 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config parallel_case -file "t/t_assert_synth.v" -lines 55 verilator-4.038/test_regress/t/t_tri_dangle.pl0000775000177100017500000000105313702133370021461 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_for_loop.v0000664000177100017500000000466713702133370021035 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc=0; reg [31:0] loops; reg [31:0] loops2; integer i; always @ (posedge clk) begin cyc <= cyc+8'd1; if (cyc == 8'd1) begin $write("[%0t] t_loop: Running\n",$time); // Unwind < loops = 0; loops2 = 0; for (i=0; i<16; i=i+1) begin loops = loops + i; // surefire lint_off_line ASWEMB loops2 = loops2 + i; // surefire lint_off_line ASWEMB end if (i !== 16) $stop; if (loops !== 120) $stop; if (loops2 !== 120) $stop; // Unwind <= loops = 0; for (i=0; i<=16; i=i+1) begin loops = loops + 1; end if (i !== 17) $stop; if (loops !== 17) $stop; // Don't unwind breaked loops loops = 0; for (i=0; i<16; i=i+1) begin loops = loops + 1; if (i==7) i=99; // break out of loop end if (loops !== 8) $stop; // Don't unwind large loops! loops = 0; for (i=0; i<100000; i=i+1) begin loops = loops + 1; end if (loops !== 100000) $stop; // Test post-increment loops = 0; for (i=0; i<=16; i++) begin loops = loops + 1; end if (i !== 17) $stop; if (loops !== 17) $stop; // Test pre-increment loops = 0; for (i=0; i<=16; ++i) begin loops = loops + 1; end if (i !== 17) $stop; if (loops !== 17) $stop; // Test post-decrement loops = 0; for (i=16; i>=0; i--) begin loops = loops + 1; end if (i !== -1) $stop; if (loops !== 17) $stop; // Test pre-decrement loops = 0; for (i=16; i>=0; --i) begin loops = loops + 1; end if (i !== -1) $stop; if (loops !== 17) $stop; // // 1800-2017 optionals init/expr/incr loops = 0; i = 0; for (; i<10; ++i) ++loops; if (loops !== 10) $stop; // loops = 0; i = 0; for (i=0; i<10; ) begin ++loops; ++i; end if (loops !== 10) $stop; // loops = 0; i = 0; for (; ; ++i) begin ++loops; break; end if (loops !== 1) $stop; // // bug1605 i = 1; for (i=20; 0; ) ; if (i != 20) $stop; for (i=30; i<10; i++) ; if (i != 30) $stop; // Comma loops = 0; for (i=0; i<20; ++i, ++loops); if (loops !== 20) $stop; loops = 0; for (i=0; i<20; ++loops, ++i); if (loops !== 20) $stop; // $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_pp_pragmas.pl0000775000177100017500000000104513702133370021503 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_modportlist.pl0000775000177100017500000000113513702133370023752 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => 0, verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_overzero.pl0000775000177100017500000000113113702133370022071 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--x-initial fast"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_context_c.cpp0000664000177100017500000000634713702133370022352 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # ifdef T_DPI_CONTEXT_NOOPT # include "Vt_dpi_context_noopt__Dpi.h" # else # include "Vt_dpi_context__Dpi.h" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef VERILATOR # include "verilated.h" #endif #ifdef NEED_EXTERNS extern "C" { extern int dpic_line(); extern int dpic_save(int value); extern int dpic_restore(); extern unsigned dpic_getcontext(); } #endif //====================================================================== int dpic_line() { svScope scope = svGetScope(); if (!scope) { printf("%%Warning: svGetScope failed\n"); return 0; } #ifdef VERILATOR static int didDump = 0; if (didDump++ == 0) { Verilated::scopesDump(); } #endif const char* scopenamep = svGetNameFromScope(scope); if (!scopenamep) { printf("%%Warning: svGetNameFromScope failed\n"); return 0; } if (scope != svGetScopeFromName(scopenamep)) { printf("%%Warning: svGetScopeFromName repeat failed\n"); return 0; } const char* filenamep = ""; int lineno = 0; if (svGetCallerInfo(&filenamep, &lineno)) { printf("Call from %s:%d:%s\n", filenamep, lineno, scopenamep); } else { printf("%%Warning: svGetCallerInfo failed\n"); return 0; } return lineno; } extern int Dpic_Unique; int Dpic_Unique = 0; // Address used for uniqueness int dpic_save(int value) { svScope scope = svGetScope(); if (!scope) { printf("%%Warning: svGetScope failed\n"); return 0; } // Use union to avoid cast to different size pointer warnings union valpack { void* ptr; int i; } vp; vp.i = value; if (vp.i) { } if (svPutUserData(scope, &Dpic_Unique, vp.ptr)) { printf("%%Warning: svPutUserData failed\n"); return 0; } return 1; } int dpic_restore() { svScope scope = svGetScope(); if (!scope) { printf("%%Warning: svGetScope failed\n"); return 0; } if (void* userp = svGetUserData(scope, (void*)&Dpic_Unique)) { // Use union to avoid cast to different size pointer warnings union valpack { void* ptr; int i; } vp; vp.ptr = userp; return vp.i; } else { printf("%%Warning: svGetUserData failed\n"); return 0; } } unsigned dpic_getcontext() { svScope scope = svGetScope(); printf("%%Info: svGetScope returned scope (%p) with name %s\n", scope, svGetNameFromScope(scope)); return (unsigned)(uintptr_t)scope; } verilator-4.038/test_regress/t/t_func_while.v0000664000177100017500000000144113702133370021324 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Julien Margetts. // SPDX-License-Identifier: CC0-1.0 module t #(parameter sz = 4096) ( input wire clk, output reg [tdw(sz)-1:0] data ); // bug1330 function integer clog2(input integer value); integer tmp; tmp = value-1; clog2 = 0; for (clog2=0; (tmp>0) && (clog2<32); clog2=clog2+1) tmp = tmp>>1; endfunction function integer tdw(input integer sz); tdw = clog2(sz); endfunction integer b; always @(posedge clk) for (b=0; b 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_runtime_range.v0000664000177100017500000000344213702133370023402 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [43:0] mi; reg [5:0] index; integer indexi; reg read; initial begin // Static mi = 44'b01010101010101010101010101010101010101010101; if (mi[0] !== 1'b1) $stop; if (mi[1 -: 2] !== 2'b01) $stop; `ifdef VERILATOR // verilator lint_off SELRANGE if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop; if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop; if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop; // verilator lint_on SELRANGE `else if (mi[-1] !== 1'bx) $stop; if (mi[0 -: 2] !== 2'b1x) $stop; if (mi[-1 -: 2] !== 2'bxx) $stop; `endif end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin mi = 44'h123; end if (cyc==2) begin index = 6'd43; indexi = 43; end if (cyc==3) begin read = mi[index]; if (read!==1'b0) $stop; read = mi[indexi]; if (read!==1'b0) $stop; end if (cyc==4) begin index = 6'd44; indexi = 44; end if (cyc==5) begin read = mi[index]; $display("-Illegal read value: %x",read); //if (read!==1'b1 && read!==1'bx) $stop; read = mi[indexi]; $display("-Illegal read value: %x",read); //if (read!==1'b1 && read!==1'bx) $stop; end if (cyc==6) begin indexi = -1; end if (cyc==7) begin read = mi[indexi]; $display("-Illegal read value: %x",read); //if (read!==1'b1 && read!==1'bx) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-4.038/test_regress/t/t_dpi_context.v0000664000177100017500000000336413702133370021527 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); sub a (.inst(1)); sub b (.inst(2)); initial begin a.test1; b.test1; a.test2; b.test2; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (input integer inst); import "DPI-C" context function int dpic_line(); import "DPI-C" context function int dpic_save(int value); import "DPI-C" context function int dpic_restore(); import "DPI-C" context function int unsigned dpic_getcontext(); int result; task test1; // Check line numbering `ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test result = dpic_line(); if (!result) $stop; `else result = dpic_line(); if (result !== `__LINE__) $stop; // result = dpic_line(); if (result !== `__LINE__) $stop; `endif // Check save-restore result = dpic_save(23+inst); if (result==0) $stop; endtask task test2; if (dpic_restore() != 23+inst) $stop; endtask int unsigned cntxt1; int unsigned cntxt2; initial begin cntxt1 = dpic_getcontext(); begin : caller_context // call from a different scope - should still get the context of the function declaration cntxt2 = dpic_getcontext(); end // svContext should be the context of the function declaration, not the context of the function call if (cntxt1 != cntxt2) $stop; end endmodule verilator-4.038/test_regress/t/t_timescale_parse.v0000664000177100017500000000370013702133370022341 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //verilator lint_off REALCVT `define testmod(modname) \ module modname; \ time t; \ task check; t = 1ns; $write("%m %0t\n", t); endtask \ endmodule `timescale 100s/1fs `testmod(sp2) `timescale 10s/1fs `testmod(sp1) `timescale 1s/1fs `testmod(sp0) `timescale 100ms/1fs `testmod(sm1) `timescale 10ms/1fs `testmod(sm2) `timescale 1ms/1fs `testmod(sm3) `timescale 100us/1fs `testmod(sm4) `timescale 10us/1fs `testmod(sm5) `timescale 1us/1fs `testmod(sm6) `timescale 100ns/1fs `testmod(sm7) `timescale 10ns/1fs `testmod(sm8) `timescale 1ns/1fs `testmod(sm9) `timescale 100ps/1fs `testmod(sm10) `timescale 10ps/1fs `testmod(sm11) `timescale 1ps/1fs `testmod(sm12) `timescale 100 fs/1fs `testmod(sm13) `timescale 10fs/1 fs `testmod(sm14) `timescale 1 fs / 1 fs // Comment `testmod(sm15) module r0; timeunit 10ns / 1ns; task check; $write("%m %0t\n", $time); endtask endmodule module r1; timeunit 10ns; timeprecision 1ns; task check; $write("%m %0t\n", $time); endtask endmodule module t; sp2 sp2(); sp1 sp1(); sp0 sp0(); sm1 sm1(); sm2 sm2(); sm3 sm3(); sm4 sm4(); sm5 sm5(); sm6 sm6(); sm7 sm7(); sm8 sm8(); sm9 sm9(); sm10 sm10(); sm11 sm11(); sm12 sm12(); sm13 sm13(); sm14 sm14(); sm15 sm15(); r0 r0(); r1 r1(); final begin sp2.check(); sp1.check(); sp0.check(); sm1.check(); sm2.check(); sm3.check(); sm4.check(); sm5.check(); sm6.check(); sm7.check(); sm8.check(); sm9.check(); sm10.check(); sm11.check(); sm12.check(); sm13.check(); sm14.check(); sm15.check(); r0.check(); r1.check(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_class_param.v0000664000177100017500000000176013702133367021500 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); class Cls #(parameter P = 12); bit [P-1:0] member; function bit [P-1:0] get_member; return member; endfunction function int get_p; return P; endfunction endclass Cls c12; Cls #(.P(4)) c4; initial begin c12 = new; c4 = new; if (c12.P != 12) $stop; if (c4.P != 4) $stop; if (c12.get_p() != 12) $stop; if (c4.get_p() != 4) $stop; // verilator lint_off WIDTH c12.member = 32'haaaaaaaa; c4.member = 32'haaaaaaaa; // verilator lint_on WIDTH if (c12.member != 12'haaa) $stop; if (c4.member != 4'ha) $stop; if (c12.get_member() != 12'haaa) $stop; if (c4.get_member() != 4'ha) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_debug_sigsegv_bt_bad.pl0000775000177100017500000000144613702133370023467 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB"); lint( verilator_flags2 => ["--lint-only --debug --gdbbt --debug-sigsegv"], fails => $Self->{vlt_all}, expect => '.* Program received signal SIGSEGV, Segmentation fault. .*in V3Options::.* .*%Error: Command Failed.*', ); ok(1); 1; verilator-4.038/test_regress/t/t_bitsel_wire_array_bad.pl0000775000177100017500000000112513702133367023673 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); # Comple time only test lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_stamp64.pl0000775000177100017500000000131513702133370021666 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); # Verilator before 4.033 had 'double sc_time_stamp()', make sure new form compiles $self->{vl_time_stamp64} = 1; compile( verilator_flags2 => ['-DVL_TIME_STAMP64=1'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_various.pl0000775000177100017500000000106013702133370021715 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_first.pl0000775000177100017500000000105313702133370021336 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_packed_concat.v0000664000177100017500000000132613702133370021761 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; // bug1627 localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; initial begin if (count_bits[0] != 16) $stop; if (count_bits[1] != 16) $stop; if (count_bitsc[0] != 16) $stop; if (count_bitsc[1] != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_struct_unpacked_bad.v0000664000177100017500000000076413702133370023214 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module x; typedef struct { int a; } notpacked_t; typedef struct packed { notpacked_t b; } ispacked_t; ispacked_t p; initial begin p.b = 1; if (p.b != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_gen6.pl0000775000177100017500000000106013702133370022226 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_fifo.pl0000775000177100017500000000105313702133370021132 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_format_wide_decimal.v0000664000177100017500000000235013702133370023157 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t_format_wide_decimal(/*AUTOARG*/ // Inputs clk ); input clk; int cycle = 0; bit [1023:0] x = '1; always @(posedge clk) begin if (cycle == 0) begin // Format very wide constant number (which has more bits than can // be counted in exponent of a double precision float), with %d. $display("%d", 1024'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff); end else begin // Same, but for a variable with value only known at run-time $display("%d", x); end cycle <= cycle + 1; x <= x >> 1; if (cycle == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_bitsel_slice.pl0000775000177100017500000000105313702133367022020 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_vpi_1ms10ns.pl0000775000177100017500000000161713702133370022455 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator_st => 1); top_filename("t/t_time_vpi.v"); $Self->{main_time_multiplier} = 1e-3 / 10e-9; compile( v_flags2 => ['+define+time_scale_units=1ms +define+time_scale_prec=10ns', 't/t_time_vpi_c.cpp'], verilator_flags2 => ['--vpi --trace'], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); file_grep("$Self->{obj_dir}/simx.vcd", qr!timescale +10ns!); ok(1); 1; verilator-4.038/test_regress/t/t_math_concat_sel_bad.v0000664000177100017500000000310413702133370023130 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] a = crc[3:0]; wire [3:0] b = crc[19:16]; // TEST wire [3:0] out1 = {a,b}[2 +: 4]; wire [3:0] out2 = {a,b}[5 -: 4]; wire [3:0] out3 = {a,b}[5 : 2]; wire [0:0] out4 = {a,b}[2]; // Aggregate outputs into a single result vector wire [63:0] result = {51'h0, out4, out3, out2, out1}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_package_enum.v0000664000177100017500000000142413702133370021621 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef enum bit [1:0] { E__NOT = 2'b00, E__VAL = 2'b11 } E_t; endpackage module t; reg [1:0] ttype; reg m; enum bit [1:0] { LOCAL } l; always @ (m or 1'b0 or LOCAL) begin // Don't complain about constants in sensitivity lists end initial begin ttype = pkg::E__NOT; m = (ttype == pkg::E__VAL); if (m != 1'b0) $stop; ttype = pkg::E__VAL; m = (ttype == pkg::E__VAL); if (m != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_class_extends_bad.pl0000775000177100017500000000107413702133367023027 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_slice.v0000664000177100017500000000555613702133370021151 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic use_AnB; logic [1:0] active_command [8:0]; logic [1:0] command_A [8:0]; logic [1:0] command_B [8:0]; logic [1:0] active_command2 [8:0]; logic [1:0] command_A2 [8:0]; logic [1:0] command_B2 [8:0]; logic [1:0] active_command3 [1:0][2:0][3:0]; logic [1:0] command_A3 [1:0][2:0][3:0]; logic [1:0] command_B3 [1:0][2:0][3:0]; logic [2:0] use_A4nB4; logic [8:0][1:0] active_command4; logic [8:0][1:0] command_A4; logic [8:0][1:0] command_B4; logic [8:0] pipe1 [7:0]; logic [8:0] pipe1_input; integer cyc; assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0]; assign active_command2 = (use_AnB) ? command_A2 : command_B2; // Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0]; // Check we can cope with things other than packed arrays assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4; always @ (posedge clk) begin pipe1_input <= pipe1_input + 1; pipe1[0] <= pipe1_input; pipe1[7:1] <= pipe1[6:0]; end logic [3:0][13:0] iq_read_data [15:0]; logic [3:0][13:0] iq_data; logic [3:0] sel; assign iq_data = iq_read_data[sel]; always @ (posedge clk) begin sel = sel + 1; end initial begin cyc = 0; use_AnB = 0; for (int i = 0; i < 7; ++i) begin command_A[i] = 2'b00; command_B[i] = 2'b11; command_A2[i] = 2'b00; command_B2[i] = 2'b11; pipe1_input = 9'b0; end for (int i = 0; i < 2; ++i) begin for (int j = 0; j < 3; ++j) begin for (int k = 0; k < 4; ++k) begin command_A3[i][j][k] = 2'b00; command_B3[i][j][k] = 2'b11; end end end end always @ (posedge clk) begin use_AnB <= ~use_AnB; cyc <= cyc + 1; if (use_AnB) begin if (active_command[3] != 2'b00) begin $stop; end if (active_command2[3] != 2'b00) begin $stop; end if (active_command3[0][1][2] != 2'b00) begin $stop; end end if (!use_AnB) begin if (active_command[3] != 2'b11) begin $stop; end if (active_command2[3] != 2'b11) begin $stop; end end end logic [8:0] last_pipe; always @(posedge clk) begin if (cyc < 3) begin last_pipe <= pipe1[0]; end else begin if (last_pipe + 1 != pipe1[0]) begin $stop; end else begin last_pipe <= pipe1[0]; end end if (cyc > 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule : t verilator-4.038/test_regress/t/t_flag_stats.pl0000775000177100017500000000113313702133370021477 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( verilator_flags2 => ["--stats --stats-vars"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_if_deep.pl0000775000177100017500000000120413702133370020742 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_copy_bad.v0000664000177100017500000000074313702133367022160 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Other; endclass class Cls; int imembera; function int inc_methoda; imembera += 1; return imembera; endfunction endclass module t (/*AUTOARG*/); initial begin Cls c1; Other co; c1 = new co; // Bad, incompatible types end endmodule verilator-4.038/test_regress/t/t_runflag_errorlimit.pl0000775000177100017500000000120513702133370023256 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( ); execute( all_run_flags => ["+verilator+error+limit+3"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_array_index_increment.pl0000775000177100017500000000075613702133367023741 0ustar wsnyderwsnyder#!/usr/bin/perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_66bits.v0000664000177100017500000000100313702133367021311 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [65:0] idx /*verilator public*/; initial idx = 1; always @(posedge clk) begin case(idx) 1: idx = 100; 100: begin $write("*-* All Finished *-*\n"); $finish; end default: $stop; endcase end endmodule verilator-4.038/test_regress/t/t_flag_bboxsys.v0000664000177100017500000000074513702133370021671 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg a; initial begin $unknown_sys_task_call_to_be_bbox("blah"); $unkown_sys_task_call_noarg; a = $unknown_sys_func_call(23); a = $unknown_sys_func_call_noarg; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_inst_v2k.pl0000775000177100017500000000123313702133370021110 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ['+libext+.vi+.extranoneed'], nc => 0, # Error: Multiple +libext flags found vcs => 0, ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen10_noinl.pl0000775000177100017500000000116113702133370023502 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen10.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_infinite.pl0000775000177100017500000000107613702133370022211 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_stop_bad.v0000664000177100017500000000046313702133370020777 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("Intentional stop\n"); $stop; end endmodule verilator-4.038/test_regress/t/t_trace_complex.v0000664000177100017500000000536113702133370022033 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 bit global_bit; module t (clk); input clk; integer cyc=0; typedef struct packed { bit b1; bit b0; } strp_t; typedef struct packed { strp_t x1; strp_t x0; } strp_strp_t; typedef union packed { strp_t x1; strp_t x0; } unip_strp_t; typedef bit [2:1] arrp_t; typedef arrp_t [4:3] arrp_arrp_t; typedef strp_t [4:3] arrp_strp_t; typedef bit arru_t [2:1]; typedef arru_t arru_arru_t [4:3]; typedef arrp_t arru_arrp_t [4:3]; typedef strp_t arru_strp_t [4:3]; strp_t v_strp; strp_strp_t v_strp_strp; unip_strp_t v_unip_strp; arrp_t v_arrp; arrp_arrp_t v_arrp_arrp; arrp_strp_t v_arrp_strp; arru_t v_arru; arru_arru_t v_arru_arru; arru_arrp_t v_arru_arrp; arru_strp_t v_arru_strp; real v_real; real v_arr_real [2]; string v_string; string v_assoc[string]; initial v_assoc["key"] = "value"; typedef struct packed { logic [31:0] data; } str32_t; str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0 initial v_str32x2[0] = 32'hff; initial v_str32x2[1] = 0; typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t; enumed_t v_enumed; enumed_t v_enumed2; typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t; enumb_t v_enumb; typedef struct packed { enumb_t a; enumb_t b; } enumb2_str_t; enumb2_str_t v_enumb2_str; logic [7:0] unpacked_array[-2:0]; p #(.PARAM(2)) p2 (); p #(.PARAM(3)) p3 (); always @ (posedge clk) begin cyc <= cyc + 1; v_strp <= ~v_strp; v_strp_strp <= ~v_strp_strp; v_unip_strp <= ~v_unip_strp; v_arrp_strp <= ~v_arrp_strp; v_arrp <= ~v_arrp; v_arrp_arrp <= ~v_arrp_arrp; v_real <= v_real + 0.1; v_string <= cyc[0] ? "foo" : "bar"; v_arr_real[0] <= v_arr_real[0] + 0.2; v_arr_real[1] <= v_arr_real[1] + 0.3; v_enumed <= v_enumed + 1; v_enumed2 <= v_enumed2 + 2; v_enumb <= v_enumb - 1; v_enumb2_str <= {v_enumb, v_enumb}; for (integer b=3; b<=4; b++) begin v_arru[b] <= ~v_arru[b]; v_arru_strp[b] <= ~v_arru_strp[b]; v_arru_arrp[b] <= ~v_arru_arrp[b]; for (integer a=3; a<=4; a++) begin v_arru_arru[a][b] = ~v_arru_arru[a][b]; end end v_str32x2[0] <= v_str32x2[0] - 1; v_str32x2[1] <= v_str32x2[1] + 1; if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module p; parameter PARAM = 1; initial global_bit = 1; endmodule verilator-4.038/test_regress/t/t_timing_long.pl0000775000177100017500000000373413702133370021667 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; scenarios(simulator => 1); # Look for O(n^2) problems in process handling sub gen { my $filename = shift; my $fh = IO::File->new(">$filename"); $fh->print("// Generated by t_timing_long.pl\n"); $fh->print("\n"); $fh->print("`ifdef TEST_VERBOSE\n"); $fh->print(" `define MSG(m) \$display m\n"); $fh->print("`else\n"); $fh->print(" `define MSG(m)\n"); $fh->print("`endif\n"); $fh->print("\n"); $fh->print("module t;\n"); $fh->print("\n"); $fh->print(" int cnt;\n"); $fh->print("\n"); $fh->print(" initial begin\n"); my $n = 100; for (my $i=1; $i<$n; ++$i) { # If statement around the timing is important to make the code scheduling # mostly unpredictable $fh->printf(" if (cnt == %d) begin\n", $i-1); $fh->printf(" #1; ++cnt; `MSG((\"[%0t] cnt?=${i}\", \$time));" ." if (cnt != %d) \$stop;\n", $i); $fh->printf(" end\n"); } $fh->print("\n"); $fh->print(' $write("*-* All Finished *-*\n");',"\n"); $fh->print(' $finish;',"\n"); $fh->print(" end\n"); $fh->print("endmodule\n"); } top_filename("$Self->{obj_dir}/t_timing_long.v"); gen($Self->{top_filename}); compile( #verilator_flags2=>["--exe --build --main --timing"], # Unsupported verilator_flags2=>["--exe --build --main -Wno-STMTDLY"], verilator_make_cmake => 0, verilator_make_gmake => 0, make_main => 0, make_top => 1, ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_package_twodeep.v0000664000177100017500000000110313702133370022316 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 // see bug 591 package pkg2; parameter PARAM2 = 16; endpackage // pkg2 package pkg1; import pkg2::*; parameter PARAM1 = 8; endpackage // pkg1 module t import pkg1::*; // Test SV 2012 import format (/*AUTOARG*/ // Inputs clk ); input clk; reg [PARAM1:0] bus1; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_unopt_combo_bad.out0000664000177100017500000000125613702133370022701 0ustar wsnyderwsnyder%Warning-UNOPTFLAT: t/t_unopt_combo.v:24:25: Signal unoptimizable: Feedback to clock or circular logic: 't.c' 24 | wire [31:0] c; | ^ ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unopt_combo.v:24:25: Example path: t.c t/t_unopt_combo.v:81:4: Example path: ALWAYS t/t_unopt_combo.v:23:25: Example path: t.b t/t_unopt_combo.v:124:4: Example path: ALWAYS t/t_unopt_combo.v:24:25: Example path: t.c %Error: Exiting due to verilator-4.038/test_regress/t/t_param_first_a.v0000664000177100017500000000134213702133370022010 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_param_first_a (/*AUTOARG*/ // Outputs varwidth, par ); parameter X = 1; parameter FIVE = 0; // Overridden parameter TWO = 2; /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output [4:0] par; // From b of t_param_first_b.v output [X:0] varwidth; // From b of t_param_first_b.v // End of automatics t_param_first_b #(X,FIVE,TWO) b (/*AUTOINST*/ // Outputs .par (par[4:0]), .varwidth (varwidth[X:0])); endmodule verilator-4.038/test_regress/t/t_lint_comb_bad.pl0000775000177100017500000000107113702133370022125 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_package_export.v0000664000177100017500000000263313702133370022201 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 // see bug 591 package pkg1; parameter PARAM2 = 16; parameter PARAM3 = 16; endpackage : pkg1 package pkg10; import pkg1::*; import pkg1::*; // Ignore if already `ifdef T_PACKAGE_EXPORT export *::*; // Not supported on all simulators `endif parameter PARAM1 = 8; endpackage package pkg11; import pkg10::*; endpackage package pkg20; import pkg1::*; `ifdef T_PACKAGE_EXPORT export pkg1::*; `endif parameter PARAM1 = 8; endpackage package pkg21; import pkg20::*; endpackage package pkg30; import pkg1::*; `ifdef T_PACKAGE_EXPORT export pkg1::PARAM2; export pkg1::PARAM3; `endif `ifdef T_PACKAGE_EXPORT_BAD export pkg1::BAD_DOES_NOT_EXIST; `endif parameter PARAM1 = 8; endpackage package pkg31; import pkg30::*; endpackage module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [pkg11::PARAM1 : 0] bus11; reg [pkg11::PARAM2 : 0] bus12; reg [pkg11::PARAM3 : 0] bus13; reg [pkg21::PARAM1 : 0] bus21; reg [pkg21::PARAM2 : 0] bus22; reg [pkg21::PARAM3 : 0] bus23; reg [pkg31::PARAM1 : 0] bus31; reg [pkg31::PARAM2 : 0] bus32; reg [pkg31::PARAM3 : 0] bus33; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_alw_split_rst.pl0000775000177100017500000000136713702133367022255 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["--stats", $Self->wno_unopthreads_for_few_cores()] ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); } execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_preproc_noline.v0000664000177100017500000000056713702133370022227 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define CHECK text \ multiline Hello in t_preproc_psl.v `ifdef NEVER not `else yes `endif Multi `CHECK line // Did we end up right? Line: `__LINE__ verilator-4.038/test_regress/t/t_trace_off_sc.pl0000775000177100017500000000134013702133370021765 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_ena.v"); compile( verilator_flags2 => ['-notrace -sc'], ); execute( check_finished => 1, ); if ($Self->{vlt_all}) { !-r "$Self->{obj_dir}/simx.vcd" or error("Tracing should be off\n"); } ok(1); 1; verilator-4.038/test_regress/t/t_sys_time.pl0000775000177100017500000000105313702133370021205 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_const_dec_mixed_bad.v0000664000177100017500000000044513702133367023147 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); parameter [200:0] MIXED = 32'dx_1; endmodule verilator-4.038/test_regress/t/t_dist_portability.pl0000775000177100017500000000665113702133370022747 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; scenarios(dist => 1); my $root = ".."; my $Debug; if (!-r "$root/.git") { skip("Not in a git repository"); } else { uint(); printfll(); cstr(); vsnprintf(); } ok(1); sub uint { ### Must trim output before and after our file list #my $files = "*/*.c* */*.h test_regress/t/*.c* test_regress/t/*.h"; # src isn't clean, and probably doesn't need to be (yet?) my $files = "include/*.c* include/*.h test_c/*.c* test_regress/t/*.c* test_regress/t/*.h"; my $cmd = "cd $root && fgrep -n int $files | sort"; print "C $cmd\n"; my $grep = `$cmd`; my %names; foreach my $line (split /\n/, $grep) { $line =~ s!//.*$!!; next if $line !~ /uint\d+_t\b/; next if $line =~ /vl[su]int\d+_t/; next if $line =~ /typedef/; next if $line =~ m!include/svdpi.h!; # Not ours if ($line =~ /^([^:]+)/) { $names{$1} = 1; print "$line\n"; } } if (keys %names) { error("Files with uint32*_t instead of vluint32s: ",join(' ',sort keys %names)); } } sub printfll { my $files = "src/*.c* src/*.h include/*.c* include/*.h test_c/*.c* test_regress/t/*.c* test_regress/t/*.h"; my $cmd = "cd $root && fgrep -n ll $files | sort"; print "C $cmd\n"; my $grep = `$cmd`; my %names; foreach my $line (split /\n/, $grep) { next if $line !~ /%[a-z0-9]*ll/; next if $line !~ /\blong\S+long\b/; # Assume a cast print "$line\n"; if ($line =~ /^([^:]+)/) { $names{$1} = 1; } else { $names{UNKNOWN} = 1; } } if (keys %names) { error("Files with %ll instead of VL_PRI64: ",join(' ',sort keys %names)); } } sub cstr { my $files = "src/*.c* src/*.h include/*.c* include/*.h test_c/*.c* test_regress/t/*.c* test_regress/t/*.h"; my $cmd = "cd $root && grep -n -P 'c_str|begin|end' $files | sort"; print "C $cmd\n"; my $grep = `$cmd`; my %names; foreach my $line (split /\n/, $grep) { if ($line =~ /^([^:]+).*\(\)[a-z0-9_().->]*[.->]+(c_str|r?begin|r?end)\(\)/) { next if $line =~ /lintok-begin-on-ref/; print "$line\n"; $names{$1} = 1; } } if (keys %names) { error("Files with potential c_str() lifetime issue: ",join(' ',sort keys %names)); } } sub vsnprintf { # Note do not do test_regress, as VPI files need to compile without verilatedos.h my $files = "src/*.c* src/*.h include/*.c* include/*.h test_c/*.c*"; my $cmd = "cd $root && grep -n -P '(snprintf|vsnprintf)' $files | sort"; print "C $cmd\n"; my $grep = `$cmd`; my %names; foreach my $line (split /\n/, $grep) { if ($line =~ /\b(snprintf|vsnprintf)\b/) { next if $line =~ /# *define\s*VL_V?SNPRINTF/; print "$line\n"; $names{$1} = 1; } } if (keys %names) { error("Files with vsnprintf, use VL_VSNPRINTF: ",join(' ',sort keys %names)); } } 1; verilator-4.038/test_regress/t/t_interface_down_inlb.pl0000775000177100017500000000123413702133370023345 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_down.v"); compile( v_flags2 => ['+define+INLINE_B'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_timescale.v0000664000177100017500000000052013702133370022135 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $printtimescale; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_array_compare.pl0000775000177100017500000000105313702133367022203 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unopt_converge_print_bad.out0000664000177100017500000000042213702133370024620 0ustar wsnyderwsnyder-V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_unopt_converge_print_bad::_change_request -V{t#,#} CHANGE: t/t_unopt_converge.v:19: x %Error: t/t_unopt_converge.v:7: Verilated model didn't converge Aborting... verilator-4.038/test_regress/t/t_assert_elab.pl0000775000177100017500000000105313702133367021643 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_arg_inout_type.cpp0000664000177100017500000010670013702133370023406 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_inout_type__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; #else # error "Unknown simulator for DPI test" #endif //====================================================================== // Implementations of imported functions //====================================================================== #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void check_bvals(const svLogicVecVal* v, unsigned n); void check_bvals(const svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { if (v[i].bval != 0) { printf(__FILE__ ":%d Bad svLogicVecVal bval\n", __LINE__); abort(); } } } void set_bvals(svLogicVecVal* v, unsigned n); void set_bvals(svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { v[i].bval = 0; } } // Basic types as per IEEE 1800-2017 35.5.6 void i_byte(char* x) { static int n = 0; if (*x != 10 - n++) stop(); *x += 100; } void i_byte_unsigned(unsigned char* x) { static int n = 0; if (*x != 20 - n++) stop(); *x += 200; } void i_shortint(short* x) { static int n = 0; if (*x != 30 - n++) stop(); *x += 300; } void i_shortint_unsigned(unsigned short* x) { static int n = 0; if (*x != 40 - n++) stop(); *x += 400; } void i_int(int* x) { static int n = 0; if (*x != 50 - n++) stop(); *x += 500; } void i_int_unsigned(unsigned* x) { static int n = 0; if (*x != 60 - n++) stop(); *x += 600; } void i_longint(sv_longint_t* x) { static int n = 0; if (*x != 70 - n++) stop(); *x += 700; } void i_longint_unsigned(sv_longint_unsigned_t* x) { static int n = 0; if (*x != 80 - n++) stop(); *x += 800; } #ifndef NO_TIME void i_time(svLogicVecVal* x) { static int n = 0; if (x[0].aval != 90 - n++) stop(); if (x[1].aval != 0) stop(); check_bvals(x, 2); x[0].aval += 900; } #endif #ifndef NO_INTEGER void i_integer(svLogicVecVal* x) { static int n = 0; if (x[0].aval != 100 - n++) stop(); check_bvals(x, 1); x[0].aval += 1000; } #endif void i_real(double* x) { static int n = 0; if (*x != (-2.0 * n++ - 1.0) / 2.0) stop(); *x += -100.0; } #ifndef NO_SHORTREAL void i_shortreal(float* x) { static int n = 0; if (*x != (-4.0f * n++ - 1.0f) / 4.0f) stop(); *x += -200.0f; } #endif void i_chandle(void** x) { static int n = 0; printf("i_chandle %d\n", n); if (*x != NULL) stop(); *x = (n % 2) ? reinterpret_cast(&i_chandle) : 0; n++; } void i_string(const char** x) { static int n = 0; printf("i_string %d\n", n); if (n++ % 2 == 0) { if (strcmp(*x, "Hello") != 0) stop(); *x = "Good"; } else { if (strcmp(*x, "World") != 0) stop(); *x = "Bye"; } } void i_bit(svBit* x) { static int n = 0; printf("i_bit %d\n", n); if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_logic(svLogic* x) { static int n = 0; printf("i_logic %d\n", n); if (*x != n++ % 2) stop(); *x ^= 1; } // Basic types via typedefs void i_byte_t(char* x) { static int n = 0; if (*x != 10 - n) stop(); *x += 101; n += 2; } void i_byte_unsigned_t(unsigned char* x) { static int n = 0; if (*x != 20 - n) stop(); *x += 202; n += 2; } void i_shortint_t(short* x) { static int n = 0; if (*x != 30 - n) stop(); *x += 303; n += 2; } void i_shortint_unsigned_t(unsigned short* x) { static int n = 0; if (*x != 40 - n) stop(); *x += 404; n += 2; } void i_int_t(int* x) { static int n = 0; if (*x != 50 - n) stop(); *x += 505; n += 2; } void i_int_unsigned_t(unsigned* x) { static int n = 0; if (*x != 60 - n) stop(); *x += 606; n += 2; } void i_longint_t(sv_longint_t* x) { static int n = 0; if (*x != 70 - n) stop(); *x += 707; n += 2; } void i_longint_unsigned_t(sv_longint_unsigned_t* x) { static int n = 0; if (*x != 80 - n) stop(); *x += 808; n += 2; } #ifndef NO_TIME void i_time_t(svLogicVecVal* x) { static int n = 0; if (x[0].aval != 90 - n) stop(); if (x[1].aval != 0) stop(); check_bvals(x, 2); x[0].aval += 909; n += 2; } #endif #ifndef NO_INTEGER void i_integer_t(svLogicVecVal* x) { static int n = 0; if (x[0].aval != 100 - n) stop(); check_bvals(x, 1); x[0].aval += 1001; n += 2; } #endif void i_real_t(double* x) { static int n = 0; if (*x != (-2.0 * n - 1.0) / 2.0) stop(); *x += -111.0; n += 2; } #ifndef NO_SHORTREAL void i_shortreal_t(float* x) { static int n = 0; if (*x != (-4.0f * n - 1.0f) / 4.0f) stop(); *x += -222.0f; n += 2; } #endif void i_chandle_t(void** x) { static int n = 0; printf("i_chandle_t %d\n", n); if (*x != NULL) stop(); *x = (n % 2) ? 0 : reinterpret_cast(&i_chandle_t); n++; } void i_string_t(const char** x) { static int n = 0; printf("i_string_t %d\n", n); if (n++ % 2 == 0) { if (strcmp(*x, "World") != 0) stop(); *x = "Bye"; } else { if (strcmp(*x, "Hello") != 0) stop(); *x = "Good"; } } void i_bit_t(svBit* x) { static int n = 0; printf("i_bit_t %d\n", n); if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_logic_t(svLogic* x) { static int n = 0; printf("i_logic_t %d\n", n); if (*x != n++ % 2) stop(); *x ^= 1; } // 2-state packed arrays void i_array_2_state_1(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_1 %d\n", n); *x &= 1; if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_array_2_state_32(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_32 %d\n", n); if (*x != 0xffffffffU << n) stop(); *x >>= n; n++; } void i_array_2_state_33(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_33 %d\n", n); x[1] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != 1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_array_2_state_64(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_64 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_array_2_state_65(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_65 %d\n", n); x[2] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != 1) stop(); if (n > 0) { x[0] = -1; x[1] = x[2] << (32 - n) | x[1] >> n; x[2] = x[2] >> n; } n++; } void i_array_2_state_128(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_128 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != -1) stop(); if (x[3] != -1) stop(); if (n > 0) { x[0] = -1; x[2] = x[3] << (32 - n) | x[2] >> n; x[3] = x[3] >> n; } n++; } // 2-state packed structures void i_struct_2_state_1(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_1 %d\n", n); *x &= 1; if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_struct_2_state_32(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_32 %d\n", n); if (*x != 0xffffffffU << n) stop(); *x >>= n; n++; } void i_struct_2_state_33(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_33 %d\n", n); x[1] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != 1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_struct_2_state_64(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_64 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_struct_2_state_65(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_65 %d\n", n); x[2] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != 1) stop(); if (n > 0) { x[0] = -1; x[1] = x[2] << (32 - n) | x[1] >> n; x[2] = x[2] >> n; } n++; } void i_struct_2_state_128(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_128 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != -1) stop(); if (x[3] != -1) stop(); if (n > 0) { x[0] = -1; x[2] = x[3] << (32 - n) | x[2] >> n; x[3] = x[3] >> n; } n++; } // 2-state packed unions void i_union_2_state_1(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_1 %d\n", n); *x &= 1; if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_union_2_state_32(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_32 %d\n", n); if (*x != 0xffffffffU << n) stop(); *x >>= n; n++; } void i_union_2_state_33(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_33 %d\n", n); x[1] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != 1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_union_2_state_64(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_64 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_union_2_state_65(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_65 %d\n", n); x[2] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != 1) stop(); if (n > 0) { x[0] = -1; x[1] = x[2] << (32 - n) | x[1] >> n; x[2] = x[2] >> n; } n++; } void i_union_2_state_128(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_128 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != -1) stop(); if (x[3] != -1) stop(); if (n > 0) { x[0] = -1; x[2] = x[3] << (32 - n) | x[2] >> n; x[3] = x[3] >> n; } n++; } // 4-state packed arrays void i_array_4_state_1(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_1 %d\n", n); x[0].aval &= 1; if (x[0].aval != !(n++ % 2)) stop(); check_bvals(x, 1); x[0].aval ^= 1; } void i_array_4_state_32(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_32 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); check_bvals(x, 1); x[0].aval >>= n; n++; } void i_array_4_state_33(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_33 %d\n", n); x[1].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != 1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_array_4_state_64(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_64 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_array_4_state_65(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_65 %d\n", n); x[2].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != 1) stop(); check_bvals(x, 3); if (n > 0) { x[0].aval = -1; x[1].aval = x[2].aval << (32 - n) | x[1].aval >> n; x[2].aval = x[2].aval >> n; } n++; } void i_array_4_state_128(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_128 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != -1) stop(); if (x[3].aval != -1) stop(); check_bvals(x, 4); if (n > 0) { x[0].aval = -1; x[2].aval = x[3].aval << (32 - n) | x[2].aval >> n; x[3].aval = x[3].aval >> n; } n++; } // 4-state packed structures void i_struct_4_state_1(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_1 %d\n", n); x[0].aval &= 1; if (x[0].aval != !(n++ % 2)) stop(); check_bvals(x, 1); x[0].aval ^= 1; } void i_struct_4_state_32(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_32 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); check_bvals(x, 1); x[0].aval >>= n; n++; } void i_struct_4_state_33(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_33 %d\n", n); x[1].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != 1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_struct_4_state_64(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_64 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_struct_4_state_65(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_65 %d\n", n); x[2].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != 1) stop(); check_bvals(x, 3); if (n > 0) { x[0].aval = -1; x[1].aval = x[2].aval << (32 - n) | x[1].aval >> n; x[2].aval = x[2].aval >> n; } n++; } void i_struct_4_state_128(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_128 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != -1) stop(); if (x[3].aval != -1) stop(); check_bvals(x, 4); if (n > 0) { x[0].aval = -1; x[2].aval = x[3].aval << (32 - n) | x[2].aval >> n; x[3].aval = x[3].aval >> n; } n++; } // 4-state packed unions void i_union_4_state_1(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_1 %d\n", n); x[0].aval &= 1; if (x[0].aval != !(n++ % 2)) stop(); check_bvals(x, 1); x[0].aval ^= 1; } void i_union_4_state_32(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_32 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); check_bvals(x, 1); x[0].aval >>= n; n++; } void i_union_4_state_33(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_33 %d\n", n); x[1].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != 1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_union_4_state_64(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_64 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_union_4_state_65(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_65 %d\n", n); x[2].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != 1) stop(); check_bvals(x, 3); if (n > 0) { x[0].aval = -1; x[1].aval = x[2].aval << (32 - n) | x[1].aval >> n; x[2].aval = x[2].aval >> n; } n++; } void i_union_4_state_128(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_128 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != -1) stop(); if (x[3].aval != -1) stop(); check_bvals(x, 4); if (n > 0) { x[0].aval = -1; x[2].aval = x[3].aval << (32 - n) | x[2].aval >> n; x[3].aval = x[3].aval >> n; } n++; } //====================================================================== // Check exported functions //====================================================================== void check_exports() { static int n = 0; char x_byte; unsigned char x_byte_unsigned; short x_shortint; unsigned short x_shortint_unsigned; int x_int; unsigned x_int_unsigned; sv_longint_t x_longint; sv_longint_unsigned_t x_longint_unsigned; #ifndef NO_TIME svLogicVecVal x_time[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer[1]; #endif double x_real; #ifndef NO_SHORTREAL float x_shortreal; #endif void* x_chandle; const char* x_string; svBit x_bit; svLogic x_logic; char x_byte_t; unsigned char x_byte_unsigned_t; short x_shortint_t; unsigned short x_shortint_unsigned_t; int x_int_t; unsigned x_int_unsigned_t; sv_longint_t x_longint_t; sv_longint_unsigned_t x_longint_unsigned_t; #ifndef NO_TIME svLogicVecVal x_time_t[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer_t[1]; #endif double x_real_t; #ifndef NO_SHORTREAL float x_shortreal_t; #endif void* x_chandle_t; const char* x_string_t; svBit x_bit_t; svLogic x_logic_t; svBitVecVal x_array_2_state_1[1]; svBitVecVal x_array_2_state_32[1]; svBitVecVal x_array_2_state_33[2]; svBitVecVal x_array_2_state_64[2]; svBitVecVal x_array_2_state_65[3]; svBitVecVal x_array_2_state_128[4]; svBitVecVal x_struct_2_state_1[1]; svBitVecVal x_struct_2_state_32[1]; svBitVecVal x_struct_2_state_33[2]; svBitVecVal x_struct_2_state_64[2]; svBitVecVal x_struct_2_state_65[3]; svBitVecVal x_struct_2_state_128[4]; svBitVecVal x_union_2_state_1[1]; svBitVecVal x_union_2_state_32[1]; svBitVecVal x_union_2_state_33[2]; svBitVecVal x_union_2_state_64[2]; svBitVecVal x_union_2_state_65[3]; svBitVecVal x_union_2_state_128[4]; svLogicVecVal x_array_4_state_1[1]; svLogicVecVal x_array_4_state_32[1]; svLogicVecVal x_array_4_state_33[2]; svLogicVecVal x_array_4_state_64[2]; svLogicVecVal x_array_4_state_65[3]; svLogicVecVal x_array_4_state_128[4]; svLogicVecVal x_struct_4_state_1[1]; svLogicVecVal x_struct_4_state_32[1]; svLogicVecVal x_struct_4_state_33[2]; svLogicVecVal x_struct_4_state_64[2]; svLogicVecVal x_struct_4_state_65[3]; svLogicVecVal x_struct_4_state_128[4]; svLogicVecVal x_union_4_state_1[1]; svLogicVecVal x_union_4_state_32[1]; svLogicVecVal x_union_4_state_33[2]; svLogicVecVal x_union_4_state_64[2]; svLogicVecVal x_union_4_state_65[3]; svLogicVecVal x_union_4_state_128[4]; #ifndef NO_TIME set_bvals(x_time, 2); set_bvals(x_time_t, 2); #endif #ifndef NO_INTEGER set_bvals(x_integer, 1); set_bvals(x_integer_t, 1); #endif set_bvals(x_array_4_state_1, 1); set_bvals(x_array_4_state_32, 1); set_bvals(x_array_4_state_33, 2); set_bvals(x_array_4_state_64, 2); set_bvals(x_array_4_state_65, 3); set_bvals(x_array_4_state_128, 4); set_bvals(x_struct_4_state_1, 1); set_bvals(x_struct_4_state_32, 1); set_bvals(x_struct_4_state_33, 2); set_bvals(x_struct_4_state_64, 2); set_bvals(x_struct_4_state_65, 3); set_bvals(x_struct_4_state_128, 4); set_bvals(x_union_4_state_1, 1); set_bvals(x_union_4_state_32, 1); set_bvals(x_union_4_state_33, 2); set_bvals(x_union_4_state_64, 2); set_bvals(x_union_4_state_65, 3); set_bvals(x_union_4_state_128, 4); // Basic types as per IEEE 1800-2017 35.5.6 x_byte = 10 + n; e_byte(&x_byte); if (x_byte != 110 + n) stop(); x_byte_unsigned = 20 + n; e_byte_unsigned(&x_byte_unsigned); if (x_byte_unsigned != 220 + n) stop(); x_shortint = 30 + n; e_shortint(&x_shortint); if (x_shortint != 330 + n) stop(); x_shortint_unsigned = 40 + n; e_shortint_unsigned(&x_shortint_unsigned); if (x_shortint_unsigned != 440 + n) stop(); x_int = 50 + n; e_int(&x_int); if (x_int != 550 + n) stop(); x_int_unsigned = 60 + n; e_int_unsigned(&x_int_unsigned); if (x_int_unsigned != 660 + n) stop(); x_longint = 70 + n; e_longint(&x_longint); if (x_longint != 770 + n) stop(); x_longint_unsigned = 80 + n; e_longint_unsigned(&x_longint_unsigned); if (x_longint_unsigned != 880 + n) stop(); #ifndef NO_TIME x_time[0].aval = 90 + n; x_time[1].aval = 0; e_time(x_time); if (x_time[0].aval != 990 + n || x_time[1].aval != 0) stop(); check_bvals(x_time, 2); #endif #ifndef NO_INTEGER x_integer[0].aval = 100 + n; e_integer(x_integer); if (x_integer[0].aval != 1100 + n) stop(); check_bvals(x_integer, 1); #endif x_real = 1.0 * n + 0.50; e_real(&x_real); if (x_real != 100.0 + 1.0 * n + 0.5) stop(); #ifndef NO_SHORTREAL x_shortreal = 1.0f * n + 0.25f; e_shortreal(&x_shortreal); if (x_shortreal != 200.0f + 1.0f * n + 0.25f) stop(); #endif if ((n % 2) == 0) { x_chandle = reinterpret_cast(&e_chandle); x_string = "Good"; } else { x_chandle = NULL; x_string = "Bye"; } e_chandle(&x_chandle); e_string(&x_string); if ((n % 2) == 0) { if (x_chandle != NULL) stop(); if (strcmp(x_string, "Hello") != 0) stop(); } else { if (x_chandle != NULL) stop(); if (strcmp(x_string, "World") != 0) stop(); } x_bit = n % 2; e_bit(&x_bit); if (x_bit != !(n % 2)) stop(); x_logic = !(n % 2); e_logic(&x_logic); if (x_logic != n % 2) stop(); // Basic types via tyepdef x_byte_t = 10 + 2 * n; e_byte_t(&x_byte_t); if (x_byte_t != 111 + 2 * n) stop(); x_byte_unsigned_t = 20 + 2 * n; e_byte_unsigned_t(&x_byte_unsigned_t); if (x_byte_unsigned_t != 222 + 2 * n) stop(); x_shortint_t = 30 + 2 * n; e_shortint_t(&x_shortint_t); if (x_shortint_t != 333 + 2 * n) stop(); x_shortint_unsigned_t = 40 + 2 * n; e_shortint_unsigned_t(&x_shortint_unsigned_t); if (x_shortint_unsigned_t != 444 + 2 * n) stop(); x_int_t = 50 + 2 * n; e_int_t(&x_int_t); if (x_int_t != 555 + 2 * n) stop(); x_int_unsigned_t = 60 + 2 * n; e_int_unsigned_t(&x_int_unsigned_t); if (x_int_unsigned_t != 666 + 2 * n) stop(); x_longint_t = 70 + 2 * n; e_longint_t(&x_longint_t); if (x_longint_t != 777 + 2 * n) stop(); x_longint_unsigned_t = 80 + 2 * n; e_longint_unsigned_t(&x_longint_unsigned_t); if (x_longint_unsigned_t != 888 + 2 * n) stop(); #ifndef NO_TIME x_time_t[0].aval = 90 + 2 * n; x_time_t[1].aval = 0; e_time_t(x_time_t); if (x_time_t[0].aval != 999 + 2 * n || x_time_t[1].aval != 0) stop(); check_bvals(x_time_t, 2); #endif #ifndef NO_INTEGER x_integer_t[0].aval = 100 + 2 * n; e_integer_t(x_integer_t); if (x_integer_t[0].aval != 1101 + 2 * n) stop(); check_bvals(x_integer_t, 1); #endif x_real_t = 1.0 * (2 * n) + 0.50; e_real_t(&x_real_t); if (x_real_t != 111.0 + 1.0 * (2 * n) + 0.5) stop(); #ifndef NO_SHORTREAL x_shortreal_t = 1.0f * (2 * n) + 0.25f; e_shortreal_t(&x_shortreal_t); if (x_shortreal_t != 222.0f + 1.0f * (2 * n) + 0.25f) stop(); #endif if ((n % 2) == 0) { x_chandle_t = NULL; x_string_t = "Bye"; } else { x_chandle_t = reinterpret_cast(&e_chandle_t); x_string_t = "Good"; } e_chandle_t(&x_chandle_t); e_string_t(&x_string_t); if ((n % 2) == 0) { if (x_chandle_t != NULL) stop(); if (strcmp(x_string_t, "World") != 0) stop(); } else { if (x_chandle_t != NULL) stop(); if (strcmp(x_string_t, "Hello") != 0) stop(); } x_bit_t = n % 2; e_bit_t(&x_bit_t); if (x_bit_t != !(n % 2)) stop(); x_logic_t = !(n % 2); e_logic_t(&x_logic_t); if (x_logic_t != n % 2) stop(); const int m = n == 0 ? 0 : n - 1; // 2-state packed arrays x_array_2_state_1[0] = n % 2; x_array_2_state_32[0] = 0xffffffff >> n; x_array_2_state_33[1] = 1 >> n; x_array_2_state_33[0] = 0xffffffff >> m; x_array_2_state_64[1] = 0xffffffff >> n; x_array_2_state_64[0] = 0xffffffff; x_array_2_state_65[2] = 1 >> n; x_array_2_state_65[1] = 0xffffffff >> m; x_array_2_state_65[0] = 0xffffffff; x_array_2_state_128[3] = 0xffffffff >> n; x_array_2_state_128[2] = x_array_2_state_128[1] = x_array_2_state_128[0] = 0xffffffff; e_array_2_state_1(x_array_2_state_1); if ((x_array_2_state_1[0] & 1) != !(n % 2)) stop(); e_array_2_state_32(x_array_2_state_32); if (x_array_2_state_32[0] != 0xffffffff << n) stop(); e_array_2_state_33(x_array_2_state_33); if ((x_array_2_state_33[1] & 1) != 1) stop(); if (x_array_2_state_33[0] != 0xffffffff << n) stop(); e_array_2_state_64(x_array_2_state_64); if (x_array_2_state_64[1] != 0xffffffff) stop(); if (x_array_2_state_64[0] != 0xffffffff << n) stop(); e_array_2_state_65(x_array_2_state_65); if ((x_array_2_state_65[2] & 1) != 1) stop(); if (x_array_2_state_65[1] != 0xffffffff) stop(); if (x_array_2_state_65[0] != 0xffffffff << n) stop(); e_array_2_state_128(x_array_2_state_128); if (x_array_2_state_128[3] != 0xffffffff) stop(); if (x_array_2_state_128[2] != 0xffffffff) stop(); if (x_array_2_state_128[1] != 0xffffffff) stop(); if (x_array_2_state_128[0] != 0xffffffff << n) stop(); // 2-state packed structures x_struct_2_state_1[0] = n % 2; x_struct_2_state_32[0] = 0xffffffff >> n; x_struct_2_state_33[1] = 1 >> n; x_struct_2_state_33[0] = 0xffffffff >> m; x_struct_2_state_64[1] = 0xffffffff >> n; x_struct_2_state_64[0] = 0xffffffff; x_struct_2_state_65[2] = 1 >> n; x_struct_2_state_65[1] = 0xffffffff >> m; x_struct_2_state_65[0] = 0xffffffff; x_struct_2_state_128[3] = 0xffffffff >> n; x_struct_2_state_128[2] = x_struct_2_state_128[1] = x_struct_2_state_128[0] = 0xffffffff; e_struct_2_state_1(x_struct_2_state_1); if ((x_struct_2_state_1[0] & 1) != !(n % 2)) stop(); e_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32[0] != 0xffffffff << n) stop(); e_struct_2_state_33(x_struct_2_state_33); if ((x_struct_2_state_33[1] & 1) != 1) stop(); if (x_struct_2_state_33[0] != 0xffffffff << n) stop(); e_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64[1] != 0xffffffff) stop(); if (x_struct_2_state_64[0] != 0xffffffff << n) stop(); e_struct_2_state_65(x_struct_2_state_65); if ((x_struct_2_state_65[2] & 1) != 1) stop(); if (x_struct_2_state_65[1] != 0xffffffff) stop(); if (x_struct_2_state_65[0] != 0xffffffff << n) stop(); e_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128[3] != 0xffffffff) stop(); if (x_struct_2_state_128[2] != 0xffffffff) stop(); if (x_struct_2_state_128[1] != 0xffffffff) stop(); if (x_struct_2_state_128[0] != 0xffffffff << n) stop(); // 2-state packed unions x_union_2_state_1[0] = n % 2; x_union_2_state_32[0] = 0xffffffff >> n; x_union_2_state_33[1] = 1 >> n; x_union_2_state_33[0] = 0xffffffff >> m; x_union_2_state_64[1] = 0xffffffff >> n; x_union_2_state_64[0] = 0xffffffff; x_union_2_state_65[2] = 1 >> n; x_union_2_state_65[1] = 0xffffffff >> m; x_union_2_state_65[0] = 0xffffffff; x_union_2_state_128[3] = 0xffffffff >> n; x_union_2_state_128[2] = x_union_2_state_128[1] = x_union_2_state_128[0] = 0xffffffff; e_union_2_state_1(x_union_2_state_1); if ((x_union_2_state_1[0] & 1) != !(n % 2)) stop(); e_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32[0] != 0xffffffff << n) stop(); e_union_2_state_33(x_union_2_state_33); if ((x_union_2_state_33[1] & 1) != 1) stop(); if (x_union_2_state_33[0] != 0xffffffff << n) stop(); e_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64[1] != 0xffffffff) stop(); if (x_union_2_state_64[0] != 0xffffffff << n) stop(); e_union_2_state_65(x_union_2_state_65); if ((x_union_2_state_65[2] & 1) != 1) stop(); if (x_union_2_state_65[1] != 0xffffffff) stop(); if (x_union_2_state_65[0] != 0xffffffff << n) stop(); e_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128[3] != 0xffffffff) stop(); if (x_union_2_state_128[2] != 0xffffffff) stop(); if (x_union_2_state_128[1] != 0xffffffff) stop(); if (x_union_2_state_128[0] != 0xffffffff << n) stop(); // 4-state packed arrays x_array_4_state_1[0].aval = n % 2; x_array_4_state_32[0].aval = 0xffffffff >> n; x_array_4_state_33[1].aval = 1 >> n; x_array_4_state_33[0].aval = 0xffffffff >> m; x_array_4_state_64[1].aval = 0xffffffff >> n; x_array_4_state_64[0].aval = 0xffffffff; x_array_4_state_65[2].aval = 1 >> n; x_array_4_state_65[1].aval = 0xffffffff >> m; x_array_4_state_65[0].aval = 0xffffffff; x_array_4_state_128[3].aval = 0xffffffff >> n; x_array_4_state_128[2].aval = 0xffffffff; x_array_4_state_128[1].aval = 0xffffffff; x_array_4_state_128[0].aval = 0xffffffff; e_array_4_state_1(x_array_4_state_1); if ((x_array_4_state_1[0].aval & 1) != !(n % 2)) stop(); e_array_4_state_32(x_array_4_state_32); if (x_array_4_state_32[0].aval != 0xffffffff << n) stop(); e_array_4_state_33(x_array_4_state_33); if ((x_array_4_state_33[1].aval & 1) != 1) stop(); if (x_array_4_state_33[0].aval != 0xffffffff << n) stop(); e_array_4_state_64(x_array_4_state_64); if (x_array_4_state_64[1].aval != 0xffffffff) stop(); if (x_array_4_state_64[0].aval != 0xffffffff << n) stop(); e_array_4_state_65(x_array_4_state_65); if ((x_array_4_state_65[2].aval & 1) != 1) stop(); if (x_array_4_state_65[1].aval != 0xffffffff) stop(); if (x_array_4_state_65[0].aval != 0xffffffff << n) stop(); e_array_4_state_128(x_array_4_state_128); if (x_array_4_state_128[3].aval != 0xffffffff) stop(); if (x_array_4_state_128[2].aval != 0xffffffff) stop(); if (x_array_4_state_128[1].aval != 0xffffffff) stop(); if (x_array_4_state_128[0].aval != 0xffffffff << n) stop(); check_bvals(x_array_4_state_1, 1); check_bvals(x_array_4_state_32, 1); check_bvals(x_array_4_state_33, 2); check_bvals(x_array_4_state_64, 2); check_bvals(x_array_4_state_65, 3); check_bvals(x_array_4_state_128, 4); // 4-state packed structures x_struct_4_state_1[0].aval = n % 2; x_struct_4_state_32[0].aval = 0xffffffff >> n; x_struct_4_state_33[1].aval = 1 >> n; x_struct_4_state_33[0].aval = 0xffffffff >> m; x_struct_4_state_64[1].aval = 0xffffffff >> n; x_struct_4_state_64[0].aval = 0xffffffff; x_struct_4_state_65[2].aval = 1 >> n; x_struct_4_state_65[1].aval = 0xffffffff >> m; x_struct_4_state_65[0].aval = 0xffffffff; x_struct_4_state_128[3].aval = 0xffffffff >> n; x_struct_4_state_128[2].aval = 0xffffffff; x_struct_4_state_128[1].aval = 0xffffffff; x_struct_4_state_128[0].aval = 0xffffffff; e_struct_4_state_1(x_struct_4_state_1); if ((x_struct_4_state_1[0].aval & 1) != !(n % 2)) stop(); e_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32[0].aval != 0xffffffff << n) stop(); e_struct_4_state_33(x_struct_4_state_33); if ((x_struct_4_state_33[1].aval & 1) != 1) stop(); if (x_struct_4_state_33[0].aval != 0xffffffff << n) stop(); e_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64[1].aval != 0xffffffff) stop(); if (x_struct_4_state_64[0].aval != 0xffffffff << n) stop(); e_struct_4_state_65(x_struct_4_state_65); if ((x_struct_4_state_65[2].aval & 1) != 1) stop(); if (x_struct_4_state_65[1].aval != 0xffffffff) stop(); if (x_struct_4_state_65[0].aval != 0xffffffff << n) stop(); e_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128[3].aval != 0xffffffff) stop(); if (x_struct_4_state_128[2].aval != 0xffffffff) stop(); if (x_struct_4_state_128[1].aval != 0xffffffff) stop(); if (x_struct_4_state_128[0].aval != 0xffffffff << n) stop(); check_bvals(x_struct_4_state_1, 1); check_bvals(x_struct_4_state_32, 1); check_bvals(x_struct_4_state_33, 2); check_bvals(x_struct_4_state_64, 2); check_bvals(x_struct_4_state_65, 3); check_bvals(x_struct_4_state_128, 4); // 4-state packed unions x_union_4_state_1[0].aval = n % 2; x_union_4_state_32[0].aval = 0xffffffff >> n; x_union_4_state_33[1].aval = 1 >> n; x_union_4_state_33[0].aval = 0xffffffff >> m; x_union_4_state_64[1].aval = 0xffffffff >> n; x_union_4_state_64[0].aval = 0xffffffff; x_union_4_state_65[2].aval = 1 >> n; x_union_4_state_65[1].aval = 0xffffffff >> m; x_union_4_state_65[0].aval = 0xffffffff; x_union_4_state_128[3].aval = 0xffffffff >> n; x_union_4_state_128[2].aval = 0xffffffff; x_union_4_state_128[1].aval = 0xffffffff; x_union_4_state_128[0].aval = 0xffffffff; e_union_4_state_1(x_union_4_state_1); if ((x_union_4_state_1[0].aval & 1) != !(n % 2)) stop(); e_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32[0].aval != 0xffffffff << n) stop(); e_union_4_state_33(x_union_4_state_33); if ((x_union_4_state_33[1].aval & 1) != 1) stop(); if (x_union_4_state_33[0].aval != 0xffffffff << n) stop(); e_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64[1].aval != 0xffffffff) stop(); if (x_union_4_state_64[0].aval != 0xffffffff << n) stop(); e_union_4_state_65(x_union_4_state_65); if ((x_union_4_state_65[2].aval & 1) != 1) stop(); if (x_union_4_state_65[1].aval != 0xffffffff) stop(); if (x_union_4_state_65[0].aval != 0xffffffff << n) stop(); e_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128[3].aval != 0xffffffff) stop(); if (x_union_4_state_128[2].aval != 0xffffffff) stop(); if (x_union_4_state_128[1].aval != 0xffffffff) stop(); if (x_union_4_state_128[0].aval != 0xffffffff << n) stop(); check_bvals(x_union_4_state_1, 1); check_bvals(x_union_4_state_32, 1); check_bvals(x_union_4_state_33, 2); check_bvals(x_union_4_state_64, 2); check_bvals(x_union_4_state_65, 3); check_bvals(x_union_4_state_128, 4); n++; } verilator-4.038/test_regress/t/t_var_ref_bad1.out0000664000177100017500000000045113702133370022056 0ustar wsnyderwsnyder%Error: t/t_var_ref_bad1.v:14:8: Ref connection 'bad_sub_ref' requires matching types; ref requires 'real' data type but connection is 'bit' data type. : ... In instance t 14 | (.bad_sub_ref(bad_parent)); | ^~~~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_event_copy.out0000664000177100017500000000065313702133370021722 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_event_copy.v:100:13: Unsupported: assignment of event data type : ... In instance t 100 | e4 = e3; | ^ %Error-UNSUPPORTED: t/t_event_copy.v:101:13: Unsupported: assignment of event data type : ... In instance t 101 | e3 = e2; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_table_fsm.pl0000775000177100017500000000105313702133370021305 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_width_genfor_bad.out0000664000177100017500000000271713702133370024065 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?h10' generates 32 or 5 bits. : ... In instance t 25 | rg = g; | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. : ... In instance t 26 | rp = P; | ^ %Warning-WIDTH: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. : ... In instance t 27 | rw = w; | ^ %Warning-WIDTH: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... In instance t 28 | rc = 64'h1; | ^ %Warning-WIDTH: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. : ... In instance t 33 | ri = i; | ^ %Error: Exiting due to verilator-4.038/test_regress/t/t_wire_beh1800_bad.out0000664000177100017500000000227213702133370022451 0ustar wsnyderwsnyder%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' : ... In instance t 25 | w = '0; | ^ %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 26 | o = '0; | ^ %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' : ... In instance t 27 | oa = '0; | ^~ %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo' : ... In instance t 28 | wo = '0; | ^~ %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa' : ... In instance t 29 | woa = '0; | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_dotted2_inl0.pl0000775000177100017500000000117713702133370022517 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_var_dotted2.v"); compile( v_flags2 => ['+define+NOUSE_INLINE',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_bad_width.v0000664000177100017500000000074213702133370022144 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [3:0] out; reg [38:0] in; initial begin in = 39'h0; out = MUX (in); $write("bad widths %x", out); end function [31:0] MUX; input [39:0] XX ; begin MUX = XX[39:8]; end endfunction endmodule verilator-4.038/test_regress/t/t_lint_width_bad.v0000664000177100017500000000271113702133370022155 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); // See also t_math_width // This shows the uglyness in width warnings across param modules // TODO: Would be nice to also show relevant parameter settings p #(.WIDTH(4)) p4 (.in(4'd0)); p #(.WIDTH(5)) p5 (.in(5'd0)); //==== localparam [3:0] XS = 'hx; // User presumably intended to use 'x //==== wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is //==== localparam WIDTH = 6; wire one_bit; wire [2:0] shifter = 1; wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); //==== // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS wire one = 1; wire [2:0] cnt = (one + one + one + one); // Not harmless > or >= compared with something wider (as different results if "a" wider) localparam [40:0] THREE = 3; int a; initial for (a = 0; a > THREE; ++a) $display(a); initial for (a = 0; a >= THREE; ++a) $display(a); endmodule module p #(parameter WIDTH=64) (input [WIDTH-1:0] in); wire [4:0] out = in; endmodule verilator-4.038/test_regress/t/t_var_bad_hide2.pl0000775000177100017500000000120513702133370022021 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_alw_noreorder.pl0000775000177100017500000000177113702133367022230 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_alw_reorder.v"); compile( verilator_flags2 => ["--stats -Or"], ); file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); # Here we should see some dly vars since reorder is disabled. # (Whereas our twin test, t_alw_reorder, should see no dly vars # since it enables the reorder step.) file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", qr/dly__t__DOT__v1/i); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", qr/dly__t__DOT__v2/i); execute( check_finished=>1, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_wide.pl0000775000177100017500000000113413702133370022026 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_onehot.v0000664000177100017500000000442613702133367021504 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = (crc[1:0]==0 ? 3'd0 : crc[1:0]==0 ? 3'd1 : crc[1:0]==0 ? 3'd2 : 3'd4); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[2:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h704ca23e2a83e1c5 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); // Replace this module with the device under test. // // Change the code in the t module to apply values to the inputs and // merge the output values into the result vector. input clk; input [2:0] in; output reg [31:0] out; localparam ST_0 = 0; localparam ST_1 = 1; localparam ST_2 = 2; always @(posedge clk) begin case (1'b1) // synopsys parallel_case in[ST_0]: out <= 32'h1234; in[ST_1]: out <= 32'h4356; in[ST_2]: out <= 32'h9874; default: out <= 32'h1; endcase end endmodule verilator-4.038/test_regress/t/t_unopt_combo_waive.out0000664000177100017500000000000013702133370023250 0ustar wsnyderwsnyderverilator-4.038/test_regress/t/t_struct_anon.pl0000775000177100017500000000076613702133370021722 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_pp_defkwd_bad.v0000664000177100017500000000034713702133370021756 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define define 1 verilator-4.038/test_regress/t/t_param_value.v0000664000177100017500000000341313702133370021476 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2012 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/); `define ASSERT(x) initial if (!(x)) $stop // See IEEE 6.20.2 on value parameters localparam unsigned [63:0] UNSIGNED =64'h99934567_89abcdef; localparam signed [63:0] SIGNED =64'sh99934567_89abcdef; localparam real REAL=1.234; `ASSERT(UNSIGNED > 0); `ASSERT(SIGNED < 0); // bullet 1 localparam A1_WIDE = UNSIGNED; `ASSERT($bits(A1_WIDE)==64); localparam A2_REAL = REAL; `ASSERT(A2_REAL == 1.234); localparam A3_SIGNED = SIGNED; `ASSERT($bits(A3_SIGNED)==64 && A3_SIGNED < 0); localparam A4_EXPR = (2'b01 + 2'b10); `ASSERT($bits(A4_EXPR)==2 && A4_EXPR==2'b11); // bullet 2 localparam [63:0] B_UNSIGNED = SIGNED; `ASSERT($bits(B_UNSIGNED)==64 && B_UNSIGNED > 0); // bullet 3 localparam signed C_SIGNED = UNSIGNED; `ASSERT($bits(C_SIGNED)==64 && C_SIGNED < 0); localparam unsigned C_UNSIGNED = SIGNED; `ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0); // bullet 4 // verilator lint_off WIDTH localparam signed [59:0] D_SIGNED = UNSIGNED; `ASSERT($bits(D_SIGNED)==60 && D_SIGNED < 0); // verilator lint_on WIDTH // verilator lint_off WIDTH localparam unsigned [59:0] D_UNSIGNED = SIGNED; `ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0); // verilator lint_on WIDTH // bullet 6 localparam UNSIZED = 23; `ASSERT($bits(UNSIZED)>=32); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_interface_wrong_bad.out0000664000177100017500000000040213702133370023521 0ustar wsnyderwsnyder%Error: t/t_interface_wrong_bad.v:32:8: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface : ... In instance t 32 | .foo_port (bar) | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_array_fst.out0000664000177100017500003400126713702133370022730 0ustar wsnyderwsnyder$date Sun Apr 19 04:15:23 2020 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $scope module biggie $end $var logic 1048577 # d $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000000000000000000000000000000 " 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# verilator-4.038/test_regress/t/t_func_under.pl0000775000177100017500000000105313702133370021501 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_comma_inl0.pl0000775000177100017500000000117613702133370022432 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_comma.v"); compile( v_flags2 => ['+define+NOUSE_INLINE',], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_unused_bad.out0000664000177100017500000000266513702133370022713 0ustar wsnyderwsnyder%Warning-UNUSED: t/t_lint_unused_bad.v:17:15: Bits of signal are not used: 'assunu1'[5:1] : ... In instance t.sub 17 | wire [5:0] assunu1 = 0; | ^~~~~~~ ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. %Warning-UNDRIVEN: t/t_lint_unused_bad.v:21:17: Bits of signal are not driven: 'udrb2'[14:13,11] : ... In instance t.sub 21 | wire [15:10] udrb2; | ^~~~~ %Warning-UNUSED: t/t_lint_unused_bad.v:26:15: Signal is not driven, nor used: 'unu3' : ... In instance t.sub 26 | wire unu3; | ^~~~ %Warning-UNUSED: t/t_lint_unused_bad.v:28:15: Bits of signal are not driven, nor used: 'mixed'[3] : ... In instance t.sub 28 | wire [3:0] mixed; | ^~~~~ %Warning-UNUSED: t/t_lint_unused_bad.v:28:15: Bits of signal are not used: 'mixed'[2] : ... In instance t.sub 28 | wire [3:0] mixed; | ^~~~~ %Warning-UNDRIVEN: t/t_lint_unused_bad.v:28:15: Bits of signal are not driven: 'mixed'[1] : ... In instance t.sub 28 | wire [3:0] mixed; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_select_bad_range2.pl0000775000177100017500000000111313702133370022671 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_once_bad.out0000664000177100017500000000113513702133370022323 0ustar wsnyderwsnyder%Warning-UNUSED: t/t_lint_once_bad.v:19:14: Signal is not driven, nor used: 'unus1' : ... In instance t.sub3 19 | reg [A:0] unus1; reg [A:0] unus2; | ^~~~~ ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_lint_once_bad.v:19:34: Signal is not driven, nor used: 'unus2' : ... In instance t.sub3 19 | reg [A:0] unus1; reg [A:0] unus2; | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_mod_interface_array0_noinl.pl0000775000177100017500000000116113702133370024625 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_mod_interface_array0.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_bad_addr.pl0000775000177100017500000000114213702133370023460 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_rand_seed.v0000664000177100017500000000066513702133370022032 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int valuea; int valueb; initial begin valuea = $random(10); valueb = $random(10); if (valuea !== valueb) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_waiveroutput_allgood.vlt0000664000177100017500000000107613702133370024024 0ustar wsnyderwsnyder// DESCRIPTION: Verilator output: Waivers generated with --waiver-output `verilator_config // Below you find suggested waivers. You have three options: // 1. Fix the reason for the linter warning // 2. Keep the waiver permanently if you are sure this is okay // 3. Keep the waiver temporarily to suppress the output lint_off -rule WIDTH -file "*t/t_waiveroutput.v" -match "Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits." lint_off -rule UNUSED -file "*t/t_waiveroutput.v" -match "Signal is not used: 'width_warn'" verilator-4.038/test_regress/t/t_trace_fst.out0000664000177100017500000002536413702133370021527 0ustar wsnyderwsnyder$date Sun Apr 19 04:15:36 2020 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $var wire 5 " state $end $scope module t $end $var wire 1 ! clk $end $var int 32 # cyc $end $var logic 1 $ rstn $end $var wire 5 " state $end $var real_parameter 64 % fst_gparam_real $end $var real_parameter 64 & fst_lparam_real $end $var real 64 % fst_real $end $var integer 32 ' fst_integer $end $var bit 1 ( fst_bit $end $var logic 1 ) fst_logic $end $var int 32 * fst_int $end $var shortint 16 + fst_shortint $end $var longint 64 , fst_longint $end $var byte 8 - fst_byte $end $var parameter 32 . fst_parameter $end $var parameter 32 / fst_lparam $end $var supply0 1 0 fst_supply0 $end $var supply1 1 1 fst_supply1 $end $var tri0 1 2 fst_tri0 $end $var tri1 1 3 fst_tri1 $end $var tri 1 4 fst_tri $end $var wire 1 5 fst_wire $end $scope module test $end $var wire 1 ! clk $end $var wire 1 $ rstn $end $var wire 5 " state $end $var logic 5 6 state_w $end $var logic 5 7 state_array(0) $end $var logic 5 8 state_array(1) $end $var logic 5 9 state_array(2) $end $scope module unnamedblk2 $end $var int 32 : i $end $upscope $end $scope module unnamedblk1 $end $var int 32 ; i $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000 " b00000000000000000000000000000000 # 0$ r1.23 % r4.56 & b00000000000000000000000000000000 ' 0( 0) b00000000000000000000000000000000 * b0000000000000000 + b0000000000000000000000000000000000000000000000000000000000000000 , b00000000 - b00000000000000000000000001111011 . b00000000000000000000000111001000 / 00 11 02 13 04 05 b00000 6 b00000 7 b00000 8 b00000 9 b00000000000000000000000000000000 : b00000000000000000000000000000000 ; #10 b00000000000000000000000000000011 ; b00001 9 b00001 8 b00001 7 b10100 6 b00000000000000000000000000000001 # b00001 " 1! #15 0! #20 1! b00000000000000000000000000000010 # #25 0! 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#620 1! b11110 8 b00000000000000000000000000111110 # b10011 6 b01111 9 b10101 " b10101 7 #625 0! #630 1! b11110 7 b11110 " b10011 9 b11101 6 b00000000000000000000000000111111 # b01111 8 #635 0! #640 1! b10011 8 b00000000000000000000000001000000 # b11010 6 b11101 9 b01111 " b01111 7 #645 0! #650 1! b10011 7 b10011 " b11010 9 b01101 6 b00000000000000000000000001000001 # b11101 8 #655 0! #660 1! b11010 8 b00000000000000000000000001000010 # b10010 6 b01101 9 b11101 " b11101 7 #665 0! #670 1! b11010 7 b11010 " b10010 9 b01001 6 b00000000000000000000000001000011 # b01101 8 #675 0! #680 1! b10010 8 b00000000000000000000000001000100 # b10000 6 b01001 9 b01101 " b01101 7 #685 0! #690 1! b10010 7 b10010 " b10000 9 b01000 6 b00000000000000000000000001000101 # b01001 8 #695 0! #700 1! b10000 8 b00000000000000000000000001000110 # b00100 6 b01000 9 b01001 " b01001 7 #705 0! #710 1! b10000 7 b10000 " b00100 9 b00010 6 b00000000000000000000000001000111 # b01000 8 #715 0! #720 1! b00100 8 b00000000000000000000000001001000 # b00001 6 b00010 9 b01000 " b01000 7 #725 0! #730 1! b00100 7 b00100 " b00001 9 b10100 6 b00000000000000000000000001001001 # b00010 8 #735 0! #740 1! b00001 8 b00000000000000000000000001001010 # b01010 6 b10100 9 b00010 " b00010 7 #745 0! #750 1! b00001 7 b00001 " b01010 9 b00101 6 b00000000000000000000000001001011 # b10100 8 #755 0! #760 1! b01010 8 b00000000000000000000000001001100 # b10110 6 b00101 9 b10100 " b10100 7 #765 0! #770 1! b01010 7 b01010 " b10110 9 b01011 6 b00000000000000000000000001001101 # b00101 8 #775 0! #780 1! b10110 8 b00000000000000000000000001001110 # b10001 6 b01011 9 b00101 " b00101 7 #785 0! #790 1! b10110 7 b10110 " b10001 9 b11100 6 b00000000000000000000000001001111 # b01011 8 #795 0! #800 1! b10001 8 b00000000000000000000000001010000 # b01110 6 b11100 9 b01011 " b01011 7 #805 0! #810 1! b10001 7 b10001 " b01110 9 b00111 6 b00000000000000000000000001010001 # b11100 8 #815 0! #820 1! b01110 8 b00000000000000000000000001010010 # b10111 6 b00111 9 b11100 " b11100 7 #825 0! #830 1! b01110 7 b01110 " b10111 9 b11111 6 b00000000000000000000000001010011 # b00111 8 #835 0! #840 1! b10111 8 b00000000000000000000000001010100 # b11011 6 b11111 9 b00111 " b00111 7 #845 0! #850 1! b10111 7 b10111 " b11011 9 b11001 6 b00000000000000000000000001010101 # b11111 8 #855 0! #860 1! b11011 8 b00000000000000000000000001010110 # b11000 6 b11001 9 b11111 " b11111 7 #865 0! #870 1! b11011 7 b11011 " b11000 9 b01100 6 b00000000000000000000000001010111 # b11001 8 #875 0! #880 1! b11000 8 b00000000000000000000000001011000 # b00110 6 b01100 9 b11001 " b11001 7 #885 0! #890 1! b11000 7 b11000 " b00110 9 b00011 6 b00000000000000000000000001011001 # b01100 8 #895 0! #900 1! b00110 8 b00000000000000000000000001011010 # b10101 6 b00011 9 b01100 " b01100 7 #905 0! #910 1! b00110 7 b00110 " b10101 9 b11110 6 b00000000000000000000000001011011 # b00011 8 #915 0! #920 1! b10101 8 b00000000000000000000000001011100 # b01111 6 b11110 9 b00011 " b00011 7 #925 0! #930 1! b10101 7 b10101 " b01111 9 b10011 6 b00000000000000000000000001011101 # b11110 8 #935 0! #940 1! b01111 8 b00000000000000000000000001011110 # b11101 6 b10011 9 b11110 " b11110 7 #945 0! #950 1! b01111 7 b01111 " b11101 9 b11010 6 b00000000000000000000000001011111 # b10011 8 #955 0! #960 1! b11101 8 b00000000000000000000000001100000 # b01101 6 b11010 9 b10011 " b10011 7 #965 0! #970 1! b11101 7 b11101 " b01101 9 b10010 6 b00000000000000000000000001100001 # b11010 8 #975 0! #980 1! b01101 8 b00000000000000000000000001100010 # b01001 6 b10010 9 b11010 " b11010 7 #985 0! #990 1! b01101 7 b01101 " b01001 9 b10000 6 b00000000000000000000000001100011 # b10010 8 #995 0! #1000 1! b01001 8 b00000000000000000000000001100100 # b01000 6 b10000 9 b10010 " b10010 7 verilator-4.038/test_regress/t/t_param_sel_range.v0000664000177100017500000000176613702133370022332 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug477 module t ( input rst_n, input clk, output out ); submod #(.STAGES(5)) u2(.*); endmodule module submod (/*AUTOARG*/ // Outputs out, // Inputs rst_n, clk ); parameter STAGES = 4; input rst_n; input clk; output out; reg [STAGES-1:0] r_rst; generate // for i=0..5 (5+1-1) for (genvar i=0; i 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem_assoc_w_h.out0000664000177100017500000000034713702133370024104 0ustar wsnyderwsnyder000000000000000000000002 000000000000000000000003 000000000000000000000004 000000000000000000000005 000000000000000000000006 000000000000000000000007 @8 000000000000000000000010 @c 000000000000000000000014 000000000000000000000015 verilator-4.038/test_regress/t/t_gen_for2.v0000664000177100017500000000122113702133370020676 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 parameter N = 5; interface intf; logic [N-1:0] data; endinterface module t ( input logic clk ); intf localinterface [N-1:0](); generate genvar i,j; for(i = 0; i < N; i++) begin logic [N-1:0] dummy; for(j = 0; j < N; j++) begin assign dummy[j] = localinterface[j].data[i]; end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_abort.v0000664000177100017500000000067713702133370021500 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [2:0] cyc = 0; always @(posedge clk) begin cyc <= cyc + 3'd1; // Exit via abort to make sure trace is flushed if (&cyc) $stop; end endmodule verilator-4.038/test_regress/t/t_alias_unsup.pl0000775000177100017500000000111313702133367021677 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_public_sig.cpp0000664000177100017500000000234013702133370023013 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include VM_PREFIX_INCLUDE #ifdef T_TRACE_PUBLIC_SIG_VLT # include "Vt_trace_public_sig_vlt_t.h" # include "Vt_trace_public_sig_vlt_glbl.h" #else # include "Vt_trace_public_sig_t.h" # include "Vt_trace_public_sig_glbl.h" #endif unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const unsigned long long dt_2 = 3; int main(int argc, char** argv, char** env) { VM_PREFIX* top = new VM_PREFIX("top"); Verilated::debug(0); Verilated::traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; top->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); while (main_time <= 20) { top->CLK = (main_time / dt_2) % 2; top->eval(); top->t->glbl->GSR = (main_time < 7); tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); printf("*-* All Finished *-*\n"); return 0; } verilator-4.038/test_regress/t/t_table_fsm.v0000664000177100017500000000776013702133370021147 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; reg reset; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire myevent; // From test of Test.v wire myevent_pending; // From test of Test.v wire [1:0] state; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .state (state[1:0]), .myevent (myevent), .myevent_pending (myevent_pending), // Inputs .clk (clk), .reset (reset)); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, myevent_pending,myevent,state}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n",$time, cyc, crc, result, myevent, myevent_pending); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; reset <= (cyc<2); if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4e93a74bd97b25ef if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs state, myevent, myevent_pending, // Inputs clk, reset ); input clk; input reset; output [1:0] state; output myevent; output myevent_pending; reg [5:0] count = 0; always @ (posedge clk) if (reset) count <= 0; else count <= count + 1; reg myevent = 1'b0; always @ (posedge clk) myevent <= (count == 6'd27); reg myevent_done; reg hickup_ready; reg hickup_done; localparam STATE_ZERO = 0; localparam STATE_ONE = 1; localparam STATE_TWO = 2; reg [1:0] state = STATE_ZERO; reg state_start_myevent = 1'b0; reg state_start_hickup = 1'b0; reg myevent_pending = 1'b0; always @ (posedge clk) begin state <= state; myevent_pending <= myevent_pending || myevent; state_start_myevent <= 1'b0; state_start_hickup <= 1'b0; case (state) STATE_ZERO: if (myevent_pending) begin state <= STATE_ONE; myevent_pending <= 1'b0; state_start_myevent <= 1'b1; end else if (hickup_ready) begin state <= STATE_TWO; state_start_hickup <= 1'b1; end STATE_ONE: if (myevent_done) state <= STATE_ZERO; STATE_TWO: if (hickup_done) state <= STATE_ZERO; default: ; /* do nothing */ endcase end reg [3:0] myevent_count = 0; always @ (posedge clk) if (state_start_myevent) myevent_count <= 9; else if (myevent_count > 0) myevent_count <= myevent_count - 1; initial myevent_done = 1'b0; always @ (posedge clk) myevent_done <= (myevent_count == 0); reg [4:0] hickup_backlog = 2; always @ (posedge clk) if (state_start_myevent) hickup_backlog <= hickup_backlog - 1; else if (state_start_hickup) hickup_backlog <= hickup_backlog + 1; initial hickup_ready = 1'b1; always @ (posedge clk) hickup_ready <= (hickup_backlog < 3); reg [3:0] hickup_count = 0; always @ (posedge clk) if (state_start_hickup) hickup_count <= 10; else if (hickup_count > 0) hickup_count <= hickup_count - 1; initial hickup_done = 1'b0; always @ (posedge clk) hickup_done <= (hickup_count == 1); endmodule verilator-4.038/test_regress/t/t_dpi_2exp_bad.pl0000775000177100017500000000111313702133370021666 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_param_fst.pl0000775000177100017500000000116313702133370022505 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2013 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_trace_param.v"); compile( v_flags2 => ["--trace-fst"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_latch_bad.out0000664000177100017500000000076613702133370022503 0ustar wsnyderwsnyder%Warning-COMBDLY: t/t_lint_latch_bad.v:25:10: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) 25 | bc <= a; | ^~ ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. *** See the manual before disabling this, else you may end up with different sim results. %Error: Exiting due to verilator-4.038/test_regress/t/t_enum_name2.v0000664000177100017500000000121713702133370021230 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 package our_pkg; typedef enum logic [8-1:0] { ADC_IN2IN = 8'h99, ADC_IMMED = 8'h88, ADC_INDIR = 8'h86, ADC_INIDX = 8'h97 } T_Opcode; endpackage : our_pkg module t (); our our (); endmodule module our import our_pkg::*; (); T_Opcode IR = ADC_IN2IN; initial begin $write ("%s (%t)\n", IR.name, $realtime); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_repeat_bad.out0000664000177100017500000000061413702133370022660 0ustar wsnyderwsnyder%Warning-WIDTH: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits. : ... In instance t.sub2 18 | wire [0:0] b = a; | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_trace_cat_reopen_0000.out0000664000177100017500000000533213702133370023502 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Thu Aug 30 16:10:58 2018 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # 1$ #1 0$ #2 b00000000000000000000000000000001 # 1$ #3 0$ #4 b00000000000000000000000000000010 # 1$ #5 0$ #6 b00000000000000000000000000000011 # 1$ #7 0$ #8 b00000000000000000000000000000100 # 1$ #9 0$ #10 b00000000000000000000000000000101 # 1$ #11 0$ #12 b00000000000000000000000000000110 # 1$ #13 0$ #14 b00000000000000000000000000000111 # 1$ #15 0$ #16 b00000000000000000000000000001000 # 1$ #17 0$ #18 b00000000000000000000000000001001 # 1$ #19 0$ #20 b00000000000000000000000000001010 # 1$ #21 0$ #22 b00000000000000000000000000001011 # 1$ #23 0$ #24 b00000000000000000000000000001100 # 1$ #25 0$ #26 b00000000000000000000000000001101 # 1$ #27 0$ #28 b00000000000000000000000000001110 # 1$ #29 0$ #30 b00000000000000000000000000001111 # 1$ #31 0$ #32 b00000000000000000000000000010000 # 1$ #33 0$ #34 b00000000000000000000000000010001 # 1$ #35 0$ #36 b00000000000000000000000000010010 # 1$ #37 0$ #38 b00000000000000000000000000010011 # 1$ #39 0$ #40 b00000000000000000000000000010100 # 1$ #41 0$ #42 b00000000000000000000000000010101 # 1$ #43 0$ #44 b00000000000000000000000000010110 # 1$ #45 0$ #46 b00000000000000000000000000010111 # 1$ #47 0$ #48 b00000000000000000000000000011000 # 1$ #49 0$ #50 b00000000000000000000000000011001 # 1$ #51 0$ #52 b00000000000000000000000000011010 # 1$ #53 0$ #54 b00000000000000000000000000011011 # 1$ #55 0$ #56 b00000000000000000000000000011100 # 1$ #57 0$ #58 b00000000000000000000000000011101 # 1$ #59 0$ #60 b00000000000000000000000000011110 # 1$ #61 0$ #62 b00000000000000000000000000011111 # 1$ #63 0$ #64 b00000000000000000000000000100000 # 1$ #65 0$ #66 b00000000000000000000000000100001 # 1$ #67 0$ #68 b00000000000000000000000000100010 # 1$ #69 0$ #70 b00000000000000000000000000100011 # 1$ #71 0$ #72 b00000000000000000000000000100100 # 1$ #73 0$ #74 b00000000000000000000000000100101 # 1$ #75 0$ #76 b00000000000000000000000000100110 # 1$ #77 0$ #78 b00000000000000000000000000100111 # 1$ #79 0$ #80 b00000000000000000000000000101000 # 1$ #81 0$ #82 b00000000000000000000000000101001 # 1$ #83 0$ #84 b00000000000000000000000000101010 # 1$ #85 0$ #86 b00000000000000000000000000101011 # 1$ #87 0$ #88 b00000000000000000000000000101100 # 1$ #89 0$ #90 b00000000000000000000000000101101 # 1$ #91 0$ #92 b00000000000000000000000000101110 # 1$ #93 0$ #94 b00000000000000000000000000101111 # 1$ #95 0$ #96 b00000000000000000000000000110000 # 1$ #97 0$ #98 b00000000000000000000000000110001 # 1$ #99 0$ verilator-4.038/test_regress/t/t_lint_unused_bad.pl0000775000177100017500000000122513702133370022511 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_member_bad.v0000664000177100017500000000062613702133367022455 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base1; int memb1; endclass class Cls2 extends Base1; int memb2; endclass module t (/*AUTOARG*/); initial begin Cls2 c; c.memb3 = 3; // Not found end endmodule verilator-4.038/test_regress/t/t_dpi_openfirst_c.cpp0000664000177100017500000000453213702133370022671 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # include "Vt_dpi_openfirst__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern int dpii_failure(); extern void dpii_open_i(const svOpenArrayHandle i, const svOpenArrayHandle o); } #endif //====================================================================== int failure = 0; int dpii_failure() { return failure; } #define CHECK_RESULT_HEX(got, exp) \ do { \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << std::hex \ << ": GOT=" << (got) << " EXP=" << (exp) << std::endl; \ failure = __LINE__; \ } \ } while (0) //====================================================================== void dpii_open_i(const svOpenArrayHandle i, const svOpenArrayHandle o) { // Illegal in VCS: // CHECK_RESULT_HEX(svLeft(i, 0), 2); // CHECK_RESULT_HEX(svRight(i, 0), 0); // CHECK_RESULT_HEX(svLow(i, 0), 0); // CHECK_RESULT_HEX(svHigh(i, 0), 2); // CHECK_RESULT_HEX(svDimensions(i), 1); CHECK_RESULT_HEX(svLeft(i, 1), 2); CHECK_RESULT_HEX(svRight(i, 1), 0); CHECK_RESULT_HEX(svLow(i, 1), 0); CHECK_RESULT_HEX(svHigh(i, 1), 2); // CHECK_RESULT_HEX(svIncrement(i, 1), 0); CHECK_RESULT_HEX(svSize(i, 1), 3); for (int a = 0; a < 3; ++a) { svBitVecVal vec[1]; svGetBitArrElemVecVal(vec, i, a); vec[0] = ~vec[0]; svPutBitArrElemVecVal(o, vec, a); } } verilator-4.038/test_regress/t/t_class_enum.pl0000775000177100017500000000105313702133367021510 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_leak.cpp0000664000177100017500000000501713702133370020435 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test driver/expect definition // // Copyright 2003-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #include #include #include #include "Vt_leak.h" unsigned int main_time = 0; double sc_time_stamp() { return main_time; } long long get_memory_usage() { // Return memory usage. Return 0 if the system doesn't look quite right. #if 0 // BSD only. struct rusage usage; getrusage(RUSAGE_SELF, &usage); return usage.ru_ixrss + usage.ru_idrss + usage.ru_isrss; #endif FILE* fp = fopen("/proc/self/stat", "r"); if (!fp) return 0; int ps_ign; vluint64_t ps_vsize, ps_rss; int items = fscanf(fp, ("%d (%*[^) ]) %*1s %d %*d %*d %*d %*d %u" " %u %u %u %u %d %d %d %d" " %*d %*d %*u %*u %d %" VL_PRI64 "u %" VL_PRI64 "u "), &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_vsize, &ps_rss); fclose(fp); if (items >= 14) { return ps_vsize; } else { return 0; } } void make_and_destroy() { Vt_leak* topp = new Vt_leak; Verilated::debug(0); Verilated::gotFinish(0); topp->eval(); topp->clk = true; while (!Verilated::gotFinish()) { main_time += 5; topp->clk = !topp->clk; topp->eval(); } VL_DO_DANGLING(delete topp, topp); } int main(int argc, char* argv[]) { vluint64_t firstUsage = get_memory_usage(); // Warmup phase for (int i = 0; i < 10; i++) { make_and_destroy(); } firstUsage = get_memory_usage(); printf("Memory size %" VL_PRI64 "d bytes\n", firstUsage); int loops = 10; for (int left = loops; left > 0;) { for (int j = 0; j < 1; ++j, --left) { make_and_destroy(); } } vluint64_t leaked = get_memory_usage() - firstUsage; if (leaked > 64*1024) { // Have to allow some slop for this code. printf("Leaked %" VL_PRI64 "d bytes, or ~ %" VL_PRI64 "d bytes/construt\n", leaked, leaked/loops); vl_fatal(__FILE__, __LINE__, "top", "Leaked memory\n"); } printf("*-* All Finished *-*\n"); } verilator-4.038/test_regress/t/t_class_virtual_pure.v0000664000177100017500000000041713702133367023117 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 virtual class VC; pure virtual task hello(); endclass verilator-4.038/test_regress/t/t_lint_infinite.out0000664000177100017500000000110713702133370022375 0ustar wsnyderwsnyder%Warning-INFINITELOOP: t/t_lint_infinite.v:10:7: Infinite loop (condition always true) : ... In instance t 10 | forever begin end | ^~~~~~~ ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. %Warning-INFINITELOOP: t/t_lint_infinite.v:12:7: Infinite loop (condition always true) : ... In instance t 12 | for (reg [31:0] i=0; i>=0; i=i+1) begin end | ^~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_unopt_converge_print_bad.pl0000775000177100017500000000142413702133370024432 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2007 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_unopt_converge.v"); #$Self->{verilated_debug} = 1; compile( v_flags2 => ['+define+ALLOW_UNOPT --output-split 0'], make_flags => 'CPPFLAGS_ADD=-DVL_DEBUG', ); execute( fails => 1, expect_filename => $Self->{golden_filename}, ) if $Self->{vlt_all}; ok(1); 1; verilator-4.038/test_regress/t/t_a3_selftest.pl0000775000177100017500000000123213702133367021572 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_EXAMPLE.v"); compile( verilator_flags2 => ['--debug-self-test'], verilator_make_gmake => 0, make_top_shell => 0, make_main => 0, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_pow2.v0000664000177100017500000000252613702133370021106 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Aggregate outputs into a single result vector //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows wire [3:0] pow4b = crc[7:4]**crc[3:0]; wire [63:0] result = {60'h0, pow4b}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h1fec4b2b71cf8024 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_func_paramed.v0000664000177100017500000000312413702133370021625 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [11:0] in_a; reg [31:0] sel; wire [2:0] out_x; extractor #(4,3) extractor ( // Outputs .out (out_x), // Inputs .in (in_a), .sel (sel)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, in_a, sel, out_x); if (cyc==1) begin in_a <= 12'b001_101_111_010; sel <= 32'd0; end if (cyc==2) begin sel <= 32'd1; if (out_x != 3'b010) $stop; end if (cyc==3) begin sel <= 32'd2; if (out_x != 3'b111) $stop; end if (cyc==4) begin sel <= 32'd3; if (out_x != 3'b101) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module extractor (/*AUTOARG*/ // Outputs out, // Inputs in, sel ); parameter IN_WIDTH=8; parameter OUT_WIDTH=2; input [IN_WIDTH*OUT_WIDTH-1:0] in; output [OUT_WIDTH-1:0] out; input [31:0] sel; wire [OUT_WIDTH-1:0] out = selector(in,sel); function [OUT_WIDTH-1:0] selector; input [IN_WIDTH*OUT_WIDTH-1:0] inv; input [31:0] selv; integer i; begin selector = 0; for (i=0; i 1); top_filename("t/t_castdyn.v"); lint( verilator_flags2 => ['-bbox-unsup'], fails => 0, ); ok(1); 1; verilator-4.038/test_regress/t/t_display_signed.out0000664000177100017500000000201213702133370022534 0ustar wsnyderwsnyder[0] lp %x=0bbccc %x=0bbccc %o=2736314 %b=010111011110011001100 %0d=769228 %d= 769228 %p= 769228 %0p='hbbccc [0] ln %x=1bbccc %x=1bbccc %o=6736314 %b=110111011110011001100 %0d=-279348 %d= -279348 %p=1817804 %0p='h1bbccc [0] qp %x=001bbbbcccc %x=001bbbbcccc %o=00067356746314 %b=00000000110111011101110111100110011001100 %0d=7444614348 %d= 7444614348 %p= 7444614348 %0p='h1bbbbcccc [0] qn %x=101bbbbcccc %x=101bbbbcccc %o=20067356746314 %b=10000000110111011101110111100110011001100 %0d=-1092067013428 %d=-1092067013428 %p=1106956242124 %0p='h101bbbbcccc [0] wp %x=000bc1234567812345678 %x=000bc1234567812345678 %o=000570110642547402215053170 %b=000000000101111000001001000110100010101100111100000010010001101000101011001111000 %p= 3469299654322568844920 %0p='hbc1234567812345678 [0] wn %x=000bc1234577812345678 %x=000bc1234577812345678 %o=000570110642567402215053170 %b=000000000101111000001001000110100010101110111100000010010001101000101011001111000 %p= 3469299655422080472696 %0p='hbc1234577812345678 *-* All Finished *-* verilator-4.038/test_regress/t/t_interface_gen5.pl0000775000177100017500000000106013702133370022225 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_unopt_combo_isolate.pl0000775000177100017500000000343713702133370023425 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_unopt_combo.v"); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; compile( verilator_flags2 => ["+define+ISOLATE --stats"], ); if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); file_grep("$out_filename", qr/\/i); } execute( ); ok(1); 1; verilator-4.038/test_regress/t/t_trace_complex_params_fst.pl0000775000177100017500000000134713702133370024423 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_complex.v"); compile( verilator_flags2 => ['--cc --trace-fst --no-trace-structs --trace-params'], ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_tri_gate_cond.pl0000775000177100017500000000141513702133370022154 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_tri_gate.v"); compile( make_top_shell => 0, make_main => 0, v_flags2 => ['+define+T_COND',], make_flags => 'CPPFLAGS_ADD=-DT_COND', verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_inout.pl0000775000177100017500000000123713702133370021371 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( make_top_shell => 0, make_main => 0, verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_embed1_c.cpp0000664000177100017500000001010013702133370021145 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2011-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include "svdpi.h" #include "../t_embed1_child/Vt_embed1_child.h" //====================================================================== #if defined(VERILATOR) # include "Vt_embed1__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #include "verilated.h" #ifdef NEED_EXTERNS extern "C" { extern void t_embed_child_initial(); extern void t_embed_child_final(); extern void t_embed_child_eval(); extern void t_embed_child_io_eval(); // TODO real function params here } #endif //====================================================================== extern int T_Embed_Child_Unique; int T_Embed_Child_Unique = 0; // Address used for uniqueness Vt_embed1_child* __get_modelp() { svScope scope = svGetScope(); if (!scope) { vl_fatal(__FILE__, __LINE__, __FILE__, "svGetScope failed"); return NULL; } void* __modelp = svGetUserData(scope, &T_Embed_Child_Unique); if (!__modelp) { // Create the model const char* scopenamep = svGetNameFromScope(scope); if (!scopenamep) vl_fatal(__FILE__, __LINE__, __FILE__, "svGetNameFromScope failed"); __modelp = new Vt_embed1_child(scopenamep); if (svPutUserData(scope, &T_Embed_Child_Unique, __modelp)) { vl_fatal(__FILE__, __LINE__, __FILE__, "svPutUserData failed"); } } return (Vt_embed1_child*)(__modelp); } void t_embed_child_initial() { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_initial\n");); Vt_embed1_child* __modelp = __get_modelp(); __modelp->eval(); } void t_embed_child_final() { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_final\n");); Vt_embed1_child* __modelp = __get_modelp(); __modelp->final(); } void t_embed_child_eval() { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_eval\n");); Vt_embed1_child* __modelp = __get_modelp(); __modelp->eval(); } void t_embed_child_io_eval(unsigned char clk, unsigned char bit_in, const svBitVecVal* vec_in, const svBitVecVal* wide_in, unsigned char is_ref, unsigned char* bit_out, svBitVecVal* vec_out, svBitVecVal* wide_out, unsigned char* did_init_out) { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_io_eval\n");); Vt_embed1_child* __modelp = __get_modelp(); VL_DEBUG_IF(VL_PRINTF("[%0ld] in clk=%x b=%x V=%x R=%x\n", (long int) (VL_TIME_Q()), clk, bit_in, vec_in[0], is_ref);); __modelp->clk = clk; __modelp->bit_in = bit_in; __modelp->vec_in = vec_in[0]; __modelp->wide_in[0] = wide_in[0]; __modelp->wide_in[1] = wide_in[1]; __modelp->wide_in[2] = wide_in[2]; __modelp->wide_in[3] = wide_in[3]; __modelp->is_ref = is_ref; // __modelp->eval(); // TODO maybe we should look at a "change detect" to know if we need to copy // out the variables; can return this value to the caller verilog code too // *bit_out = __modelp->bit_out; vec_out[0] = __modelp->vec_out; wide_out[0] = __modelp->wide_out[0]; wide_out[1] = __modelp->wide_out[1]; wide_out[2] = __modelp->wide_out[2]; wide_out[3] = __modelp->wide_out[3]; *did_init_out = __modelp->did_init_out; VL_DEBUG_IF(VL_PRINTF("[%0ld] out b=%x V=%x DI=%x\n", (long int)(VL_TIME_Q()), *bit_out, *vec_out, *did_init_out);); } verilator-4.038/test_regress/t/t_case_wild.v0000664000177100017500000000605013702133367021142 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; reg [63:0] sum; reg out1; reg [4:0] out2; sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2); cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; if (cyc==0) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==90) begin if (sum !== 64'hf0afc2bfa78277c5) $stop; end else if (cyc==91) begin end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, out2, // Inputs in ); input [23:0] in; output reg out1; output reg [4:0] out2; always @* begin // Test empty cases casez (in[0]) endcase casez (in) 24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00}; 24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00}; 24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01}; 24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02}; 24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03}; 24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04}; 24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05}; 24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06}; 24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07}; // Same pattern, but reversed to test we work OK. 24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17}; 24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16}; 24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15}; 24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14}; 24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13}; 24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12}; 24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11}; 24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10}; 24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f}; 24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e}; 24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d}; 24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c}; 24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b}; 24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a}; 24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09}; 24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08}; endcase end endmodule verilator-4.038/test_regress/t/t_interface_dups.v0000664000177100017500000001102213702133370022170 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [4:0] din_data = crc[4:0]; wire [0:0] din_valid = crc[6]; wire [0:0] dout0_ready = crc[16]; wire [0:0] dout1_ready = crc[17]; wire [0:0] dout2_ready = crc[18]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic din_ready; // From test of Test.v logic [0:0] dout0_data; // From test of Test.v logic dout0_valid; // From test of Test.v logic [1:0] dout1_data; // From test of Test.v logic dout1_valid; // From test of Test.v logic [2:0] dout2_data; // From test of Test.v logic dout2_valid; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .din_ready (din_ready), .dout0_valid (dout0_valid), .dout0_data (dout0_data[0:0]), .dout1_valid (dout1_valid), .dout1_data (dout1_data[1:0]), .dout2_valid (dout2_valid), .dout2_data (dout2_data[2:0]), // Inputs .din_valid (din_valid), .din_data (din_data[4:0]), .dout0_ready (dout0_ready), .dout1_ready (dout1_ready), .dout2_ready (dout2_ready)); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, din_ready, 2'd0, dout2_valid, dout2_data, 2'd0, dout1_valid, dout1_data, 2'd0, dout0_valid, dout0_data}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h6fd1bead9df31b07 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule interface dti #(W_DATA = 64 )(); logic [W_DATA-1:0] data; logic valid; logic ready; modport producer (output data, output valid, input ready); modport consumer (input data, input valid, output ready); endinterface : dti module Test ( output logic din_ready, input logic din_valid, input logic [4:0] din_data, input logic dout0_ready, output logic dout0_valid, output logic [0:0] dout0_data, input logic dout1_ready, output logic dout1_valid, output logic [1:0] dout1_data, input logic dout2_ready, output logic dout2_valid, output logic [2:0] dout2_data ); // Interface declarations dti #(.W_DATA(5)) din(); dti #(.W_DATA(1)) dout0(); dti #(.W_DATA(2)) dout1(); dti #(.W_DATA(3)) dout2(); // Interface wiring to top level ports assign din.valid = din_valid; assign din.data = din_data; assign din_ready = din.ready; assign dout0_valid = dout0.valid; assign dout0_data = dout0.data; assign dout0.ready = dout0_ready; assign dout1_valid = dout1.valid; assign dout1_data = dout1.data; assign dout1.ready = dout1_ready; assign dout2_valid = dout2.valid; assign dout2_data = dout2.data; assign dout2.ready = dout2_ready; assign din.ready = 0; assign dout0.data = 0; assign dout1.data = 0; assign dout2.data = 0; typedef struct packed { logic [1:0] ctrl; logic [2:0] data; } din_t; din_t din_s; assign din_s = din.data; always_comb begin dout0.valid = 0; dout1.valid = 0; dout2.valid = 0; case (din_s.ctrl) 0 : dout0.valid = din.valid; 1 : dout1.valid = din.valid; 2 : dout2.valid = din.valid; default: ; endcase end endmodule verilator-4.038/test_regress/t/t_threads_nondeterminism.pl0000775000177100017500000000136113702133370024120 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); top_filename("t/t_threads_counter.v"); compile( verilator_flags2 => ['--cc --threads 2 --debug-nondeterminism --no-skip-identical'], ); execute( check_finished => 1, ); file_grep("$Self->{obj_dir}/vlt_compile.log", qr/hash of shape/i); ok(1); 1; verilator-4.038/test_regress/t/t_vlcov_merge.pl0000775000177100017500000000174613702133370021672 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); run(cmd => ["../bin/verilator_coverage", "--write", "$Self->{obj_dir}/coverage.dat", "t/t_vlcov_data_a.dat", "t/t_vlcov_data_b.dat", "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat", ], verilator_run => 1, ); # Older clib's didn't properly sort maps, but the coverage data doesn't # really care about ordering. So avoid false failures by sorting. files_identical_sorted("$Self->{obj_dir}/coverage.dat", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_trace_two_dumpfst_cc.out0000775000177100017500000000250213702133370023743 0ustar wsnyderwsnyder$date Sun Apr 19 04:15:48 2020 $end $version fstWriter $end $timescale 1ps $end $scope module topa $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $var integer 32 # c_trace_on $end $scope module sub $end $var integer 32 $ inside_sub_a $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars #10 b00000000000000000000000000000001 $ b00000000000000000000000000000000 # b00000000000000000000000000000001 " 1! #15 0! #20 1! b00000000000000000000000000000011 # b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " b00000000000000000000000000000100 # #35 0! #40 1! b00000000000000000000000000000101 # b00000000000000000000000000000100 " #45 0! #50 1! b00000000000000000000000000000101 " b00000000000000000000000000000110 # #55 0! #60 1! b00000000000000000000000000000111 # b00000000000000000000000000000110 " #65 0! #70 1! b00000000000000000000000000000111 " b00000000000000000000000000001000 # #75 0! #80 1! b00000000000000000000000000001001 # b00000000000000000000000000001000 " #85 0! #90 1! b00000000000000000000000000001001 " b00000000000000000000000000001010 # #95 0! #100 1! b00000000000000000000000000001011 # b00000000000000000000000000001010 " #105 0! #110 1! b00000000000000000000000000001100 # b00000000000000000000000000001011 " verilator-4.038/test_regress/t/t_lint_incabspath.pl0000775000177100017500000000076313702133370022522 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_crazy_sel.v0000664000177100017500000000157113702133370021200 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; endinterface function integer the_other_func (input integer val); return val; endfunction module t (/*AUTOARG*/); genvar the_genvar; generate for (the_genvar = 0; the_genvar < 4; the_genvar++) begin: foo_loop foo foo_inst(); end endgenerate bar bar_inst(); logic x; assign x = foo_loop[bar_inst.THE_LP].foo_inst.y; //localparam N = 2; //assign x = foo_loop[N].foo_inst.y; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module foo(); logic y; endmodule module bar(); localparam THE_LP = 2; endmodule verilator-4.038/test_regress/t/t_lint_blksync_loop.v0000664000177100017500000000461713702133370022735 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs data_out, // Inputs wr, wa, rst_l, rd, ra, data_in, clk ); input clk; /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input [31:0] data_in; // To sub of reg_1r1w.v input [7:0] ra; // To sub of reg_1r1w.v input rd; // To sub of reg_1r1w.v input rst_l; // To sub of reg_1r1w.v input [7:0] wa; // To sub of reg_1r1w.v input wr; // To sub of reg_1r1w.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output [31:0] data_out; // From sub of reg_1r1w.v // End of automatics reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8)) sub (/*AUTOINST*/ // Outputs .data_out (data_out[31:0]), // Inputs .data_in (data_in[31:0]), .ra (ra[7:0]), .wa (wa[7:0]), .wr (wr), .rd (rd), .clk (clk), .rst_l (rst_l)); endmodule module reg_1r1w #( parameter WIDTH=32, parameter ADRWID=10, parameter DEPTH=1024, parameter RST=0 ) (/*AUTOARG*/ // Outputs data_out, // Inputs data_in, ra, wa, wr, rd, clk, rst_l ); input [WIDTH-1:0] data_in; input [ADRWID-1:0] ra; input [ADRWID-1:0] wa; input wr; input rd; input clk; input rst_l; output [WIDTH-1:0] data_out; reg [WIDTH-1:0] array [DEPTH-1:0]; reg [ADRWID-1:0] ra_r, wa_r; reg [WIDTH-1:0] data_in_r; reg wr_r; reg rd_r; integer x; // Message 679 always @(posedge clk) begin int tmp = x + 1; if (tmp !== x + 1) $stop; end always @(posedge clk or negedge rst_l) begin if (!rst_l) begin for (x=0; x 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_cellarray.v0000664000177100017500000000427213702133367021172 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 // change these two parameters to see the speed differences `define DATA_WIDTH 8 `define REP_COUNT4 `DATA_WIDTH/4 `define REP_COUNT2 `DATA_WIDTH/2 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] count4 = 0; reg [1:0] count2 = 0; reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}}; reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}}; reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}}; reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}}; reg [`DATA_WIDTH-1:0] res1; reg [`DATA_WIDTH-1:0] res2; reg [`DATA_WIDTH-1:0] res3; reg [`DATA_WIDTH-1:0] res4; drv1 t_drv1 [`DATA_WIDTH-1:0] (.colSelA(a), .datao(res1)); drv2 t_drv2 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .datao(res2)); drv3 t_drv3 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .datao(res3)); drv4 t_drv4 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .colSelD(d), .datao(res4)); always@(posedge clk) begin count2 <= count2 + 1; count4 <= count4 + 1; a <= {`REP_COUNT4{count4}}; b <= {`REP_COUNT4{count4}}; c <= {`REP_COUNT2{count2}}; d <= {`REP_COUNT2{count2}}; if (res1 != (a)) begin $stop; end if (res2 != (a&b)) begin $stop; end if (res3 != (a&b&c)) begin $stop; end if (res4 != (a&b&c&d)) begin $stop; end if (count4 > 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module drv1 (input colSelA, output datao ); assign datao = colSelA; endmodule module drv2 (input colSelA, input colSelB, output datao ); assign datao = colSelB & colSelA; endmodule module drv3 (input colSelA, input colSelB, input colSelC, output datao ); assign datao = colSelB & colSelA & colSelC; endmodule module drv4 (input colSelA, input colSelB, input colSelC, input colSelD, output datao ); assign datao = colSelB & colSelA & colSelC & colSelD; endmodule verilator-4.038/test_regress/t/t_class_method_bad.pl0000775000177100017500000000107413702133367022635 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_wwarn_bad.out0000664000177100017500000000007413702133370022501 0ustar wsnyderwsnyder%Error: Unknown warning specified: -Wwarn-NOSUCHERRORASTHIS verilator-4.038/test_regress/t/t_vlcov_nfound_bad.pl0000775000177100017500000000130313702133370022657 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); run(fails => 1, cmd => ["../bin/verilator_coverage", "t/t_NOT_FOUND",], logfile => $Self->{run_log_filename}, expect_filename => $Self->{golden_filename}, verilator_run => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_interface_array2.pl0000775000177100017500000000105313702133370023430 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_invalid2_bad.out0000664000177100017500000000004613702133370023052 0ustar wsnyderwsnyder%Error: Invalid option: +invalid-plus verilator-4.038/test_regress/t/t_foreach_bad.v0000664000177100017500000000071413702133370021420 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); integer a, b; reg [2:0][2:0] array; initial begin foreach (array); // no index foreach (array.array[a]); // not supported $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_tri_array_pull.v0000664000177100017500000000221113702133370022225 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Rod Steward. // SPDX-License-Identifier: CC0-1.0 module IOBUF ( input T, input I, output O, inout IO ); assign O = IO; assign IO = T ? 1'bz : I; endmodule module t ( input [7:0] inlines, output [7:0] outlines, inout [7:0] iolines, input inctrl ); generate for (genvar i = 4; i < 8; i = i+1) begin: Gen_D IOBUF d ( .T(inctrl), .I(inlines[i]), .O(outlines[i]), .IO(iolines[i]) ); pullup d_pup (iolines[i]); end endgenerate IOBUF d_0 ( .T(inctrl), .I(inlines[0]), .O(outlines[0]), .IO(iolines[0]) ); pullup d_0_pup (iolines[0]); IOBUF d_1 ( .T(inctrl), .I(inlines[1]), .O(outlines[1]), .IO(iolines[1]) ); pullup d_1_pup (iolines[1]); IOBUF d_2 ( .T(inctrl), .I(inlines[2]), .O(outlines[2]), .IO(iolines[2]) ); pullup d_2_pup (iolines[2]); IOBUF d_3 ( .T(inctrl), .I(inlines[3]), .O(outlines[3]), .IO(iolines[3]) ); pullup d_3_pup (iolines[3]); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_syncasyncnet_bad.out0000664000177100017500000000111513702133370024116 0ustar wsnyderwsnyder%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:16:25: Signal flopped as both synchronous and async: 'rst_both_l' t/t_lint_syncasyncnet_bad.v:91:15: ... Location of async usage 91 | q2 <= (~rst_both_l) ? 1'b0 : d; | ^~~~~~~~~~ t/t_lint_syncasyncnet_bad.v:59:14: ... Location of sync usage 59 | q2 <= (rst_both_l) ? d : 1'b0; | ^~~~~~~~~~ ... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_nest_noinl.pl0000775000177100017500000000116013702133370023540 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_nest.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_param_another_bad.out0000664000177100017500000000051113702133370025206 0ustar wsnyderwsnyder%Error: t/t_interface_param_another_bad.v:9:42: Parameter-resolved constants must not use dotted references: 'dummy' : ... In instance t 9 | simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); | ^~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_vpi_module.v0000664000177100017500000000451513702133370021351 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function integer mon_check(); `endif module t (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; integer status; wire a, b, x; A mod_a(/*AUTOINST*/ // Outputs .x (x), // Inputs .clk (clk), .a (a), .b (b)); // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t module A(/*AUTOARG*/ // Outputs x, // Inputs clk, a, b ); input clk; input a, b; output x; wire y, c; B mod_b(/*AUTOINST*/ // Outputs .y (y), // Inputs .b (b), .c (c)); C \mod_c. (/*AUTOINST*/ // Outputs .x (x), // Inputs .clk (clk), .a (a), .y (y)); endmodule : A module B(/*AUTOARG*/ // Outputs y, // Inputs b, c ); /*verilator public_module*/ input b, c; output reg y; always @(*) begin : myproc y = b ^ c; end endmodule module C(/*AUTOARG*/ // Outputs x, // Inputs clk, a, y ); input clk; input a, y; output reg x /* verilator public_flat_rw */; always @(posedge clk) begin x <= a & y; end endmodule verilator-4.038/test_regress/t/t_func_lib_sub.v0000664000177100017500000000424413702133370021637 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define zednkw 200 module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr); input zfghtn; input [4:0] cjtmau; input vipmpg; input [7:0] knquim; input [7:0] kqxkkr; reg covfok; reg [15:0] xwieqw; reg [2:0] ofnjjt; reg [37:0] hdsejo[1:0]; reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq; reg vrqrih, ryyjxy; reg fgzsox; wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr; wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10]; wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10]; wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr; wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr; wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1); wire smxixw = vrqrih | (ryyjxy & ktsveg); wire [7:0] grvsrs, kyxrft, uxhkka; wire [7:0] eianuv = 8'h01 << ofnjjt; wire [7:0] jvpnxn = {8{qnpfus}} & eianuv; wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv; wire [7:0] nahzat = {8{iytyol}} & eianuv; genvar i; generate for (i=0;i<8;i=i+1) begin : dnlpyw DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i], knquim[3:0], covfok, grvsrs[i]); DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i], knquim[7:4], covfok, kyxrft[i]); DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i], kqxkkr[3:0], covfok, uxhkka[i]); end endgenerate endmodule module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh); input clk, fgzsox, fckiyr, covfok; input [3:0] uezcjy; output juvlsh; task Xinit; begin `ifdef TEST_HARNESS khgawe = 1'b0; `endif end endtask function X; input vrdejo; begin `ifdef TEST_HARNESS if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1; `endif X = vrdejo; end endfunction task Xcheck; input vzpwwy; begin end endtask reg [3:0] udbvtl; assign juvlsh = |udbvtl; wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1)); wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox; always @(posedge clk) begin Xinit; if (X(qqibou)) udbvtl <= #`zednkw mppedc; Xcheck(fgzsox); end endmodule verilator-4.038/test_regress/t/t_assoc_wildcard_unsup.v0000664000177100017500000000330013702133367023416 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; integer i; always @ (posedge clk) begin cyc <= cyc + 1; begin // Wildcard string a [*]; int k; string v; a[32'd1234] = "fooed"; a[4'd3] = "bared"; i = a.num(); `checkh(i, 2); i = a.size(); `checkh(i, 2); v = a[32'd1234]; `checks(v, "fooed"); v = a[4'd3]; `checks(v, "bared"); i = a.exists("baz"); `checkh(i, 0); i = a.exists(4'd3); `checkh(i, 1); i = a.first(k); `checkh(i, 1); `checks(k, 4'd3); i = a.next(k); `checkh(i, 1); `checks(k, 32'd1234); i = a.next(k); `checkh(i, 0); i = a.last(k); `checkh(i, 1); `checks(k, 32'd1234); i = a.prev(k); `checkh(i, 1); `checks(k, 4'd3); i = a.prev(k); `checkh(i, 0); a.delete(4'd3); i = a.size(); `checkh(i, 1); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_timescale.v0000664000177100017500000000103013702133370022317 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ms/1ms // See also t_time_sc_*.v/pl module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_final.pl0000775000177100017500000000105313702133370020442 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_orig.v0000664000177100017500000001017513702133367021146 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; reg rnd; reg [2:0] a; reg [2:0] b; reg [31:0] wide; // surefire lint_off STMINI initial _ranit = 0; wire sigone1 = 1'b1; wire sigone2 = 1'b1; reg ok; parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b?? // Large case statements should be well optimizable. reg [2:0] anot; always @ (/*AS*/a) begin casez (a) default: anot = 3'b001; 3'd0: anot = 3'b111; 3'd1: anot = 3'b110; 3'd2: anot = 3'b101; 3'd3: anot = 3'b101; 3'd4: anot = 3'b011; 3'd5: anot = 3'b010; 3'd6: anot = 3'b001; // Same so folds with 7 endcase end always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; rnd <= 1; $write("[%0t] t_case: Running\n", $time); // a = 3'b101; b = 3'b111; // verilator lint_off CASEX casex (a) default: $stop; 3'bx1x: $stop; 3'b100: $stop; 3'bx01: ; endcase casez (a) default: $stop; 3'b?1?: $stop; 3'b100: $stop; 3'b?01: ; endcase casez (a) default: $stop; {1'b0, twounkn}: $stop; {1'b1, twounkn}: ; endcase casez (b) default: $stop; {1'b0, twounkn}: $stop; {1'b1, twounkn}: ; // {1'b0, 2'b??}: $stop; // {1'b1, 2'b??}: ; endcase case(a[0]) default: ; endcase casex(a) default: ; 3'b?0?: ; endcase // verilator lint_off CASEX //This is illegal, the default occurs before the statements. //case(a[0]) // default: $stop; // 1'b1: ; //endcase // wide = 32'h12345678; casez (wide) default: $stop; 32'h12345677, 32'h12345678, 32'h12345679: ; endcase // ok = 0; casez ({sigone1,sigone2}) //2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true... 2'b10, 2'b01: ; 2'b00: ; default: ok=1'b1; endcase if (ok !== 1'b1) $stop; // if (rnd) begin $write(""); end // $write("*-* All Finished *-*\n"); $finish; end end // Check parameters in case statements parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr. parameter DSP_REGISTER_V = 6'h03; reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl reg [5:0] reg_addr_2s; // Delayed version of reg_addr reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases reg [15:10] f_tmp_2s; // Delayed copy of F reg p00_2s; initial begin alu_ctl_2s = 3'h1; reg_addr_2s = 6'h3; ir_slave_2s= 0; f_tmp_2s= 0; casex ({alu_ctl_2s,reg_addr_2s, ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0], f_tmp_2s[11:10]}) default: p00_2s = 1'b0; {ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1; endcase if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused // case ({1'b1, 1'b1}) default: $stop; {1'b1, p00_2s}: ; endcase end // Check wide overlapping cases // surefire lint_off CSEOVR parameter ANY_STATE = 7'h??; reg [19:0] foo; initial begin foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0}; casez (foo) default: $stop; {1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop; {1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop; {1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop; {1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop; {1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ; {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop; {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop; endcase end initial begin foo = 20'b1010; casex (foo[3:0]) default: $stop; 4'b0xxx, 4'b100x, 4'b11xx: $stop; 4'b1010: ; endcase end initial begin foo = 20'b1010; ok = 1'b0; // Test of RANGE(CONCAT reductions... casex ({foo[3:2],foo[1:0],foo[3]}) 5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions 5'bxx00x: $stop; 5'bxx01x: $stop; 5'bxx11x: $stop; endcase if (!ok) $stop; end endmodule verilator-4.038/test_regress/t/t_func_wide_out_bad.pl0000775000177100017500000000107413702133370023014 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_select_lhs_oob2.pl0000775000177100017500000000105313702133370022417 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_protect_ids_c.cpp0000664000177100017500000000224613702133370022343 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # ifdef T_PROTECT_IDS_KEY # include "Vt_protect_ids_key__Dpi.h" # else # include "Vt_protect_ids__Dpi.h" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS # error "Not supported" #endif //====================================================================== int dpii_a_func(int i) { int o = dpix_a_func(i); return o; } int dpii_a_task(int i, int* op) { (void)dpix_a_task(i, op); return 0; } verilator-4.038/test_regress/t/t_var_ref_bad3.pl0000775000177100017500000000107113702133370021666 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_initial_edge.v0000664000177100017500000000443213702133370021621 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: initial edge issue // // The module initial_edge drives the output "res" high when the reset signal, // rst, goes high. // // The module initial_edge_n drives the output "res_n" high when the reset // signal, rst_n, goes low. // // For 4-state simulators, that edge occurs when the initial value of rst_n, // X, goes to zero. However, by default for Verilator, being 2-state, the // initial value is zero, so no edge is seen. // // This is not a bug in verilator (it is bad design to rely on an edge // transition from an unitialized signal), but the problem is that there are // quite a few instances of code out there that seems to be dependent on this // behaviour to get out of reset. // // The Verilator --x-initial-edge flag causes these initial edges to trigger, // thus matching the behaviour of a 4-state simulator. This is reportedly also // the behaviour of commercial cycle accurate modelling tools as well. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns module t (/*AUTOARG*/ // Inputs clk ); input clk; wire res; wire res_n; reg rst; reg rst_n; integer count = 0; initial_edge i_edge (.res (res), .rst (rst)); initial_edge_n i_edge_n (.res_n (res_n), .rst_n (rst_n)); // run for 3 cycles, with one cycle of reset. always @(posedge clk) begin rst <= (count == 0) ? 1 : 0; rst_n <= (count == 0) ? 0 : 1; if (count == 3) begin if ((res == 1) && (res_n == 1)) begin $write ("*-* All Finished *-*\n"); $finish; end else begin `ifdef TEST_VERBOSE $write ("FAILED: res = %b, res_n = %b\n", res, res_n); `endif $stop; end end count = count + 1; end endmodule module initial_edge_n (res_n, rst_n); output res_n; input rst_n; reg res_n = 1'b0; always @(negedge rst_n) begin if (rst_n == 1'b0) begin res_n <= 1'b1; end end endmodule // initial_edge_n module initial_edge (res, rst); output res; input rst; reg res = 1'b0; always @(posedge rst) begin if (rst == 1'b1) begin res <= 1'b1; end end endmodule // initial_edge verilator-4.038/test_regress/t/t_assert_basic_fail.pl0000775000177100017500000000141213702133367023013 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_basic.v"); compile( v_flags2 => ['+define+FAILING_ASSERTIONS', ($Self->{vlt_all} ? '--assert' : ($Self->{nc} ? '+assert' : ''))], fails => $Self->{nc}, ); execute( fails => $Self->{vlt_all}, ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_powerdn.pl0000775000177100017500000000105713702133367021672 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_var_bad_hide.v0000664000177100017500000000076013702133370021573 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Check that the lint_on is obeyed. // verilator lint_off VARHIDDEN // verilator lint_on VARHIDDEN integer top; task x; output top; begin end endtask initial begin begin: lower integer top; end end endmodule verilator-4.038/test_regress/t/t_initial.pl0000775000177100017500000000105313702133370021002 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_struct_param.v0000664000177100017500000000306213702133370021706 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Matt Myers. // SPDX-License-Identifier: CC0-1.0 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); package config_pkg; typedef struct packed { int UPPER0; struct packed { int USE_QUAD0; int USE_QUAD1; int USE_QUAD2; } mac; int UPPER2; } config_struct; function automatic config_struct static_config(int selector); config_struct return_config; return_config = '0; return_config.UPPER0 = 10; return_config.UPPER2 = 20; return_config.mac.USE_QUAD0 = 4; return_config.mac.USE_QUAD2 = 6; case (selector) 1: return_config.mac.USE_QUAD1 = 5; endcase return return_config; endfunction endpackage : config_pkg module t; import config_pkg::*; localparam config_struct MY_CONFIG = static_config(1); struct_submodule #(.MY_CONFIG(MY_CONFIG)) a_submodule_I (); endmodule : t module struct_submodule import config_pkg::*; #(parameter config_struct MY_CONFIG = '0); initial begin `checkd(MY_CONFIG.UPPER0, 10); `checkd(MY_CONFIG.mac.USE_QUAD0, 4); `checkd(MY_CONFIG.mac.USE_QUAD1, 5); `checkd(MY_CONFIG.mac.USE_QUAD2, 6); `checkd(MY_CONFIG.UPPER2, 20); $write("*-* All Finished *-*\n"); $finish; end endmodule : struct_submodule verilator-4.038/test_regress/t/t_class2.out0000664000177100017500000000025713702133367020744 0ustar wsnyderwsnyder%Error: t/t_class2.v:35:16: Can't find definition of variable: 'ENUM_VAL' 35 | if (Cls::ENUM_VAL != 22) $stop; | ^~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_embed1_child.v0000664000177100017500000000177613702133370021514 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_embed1_child (/*AUTOARG*/ // Outputs bit_out, vec_out, wide_out, did_init_out, // Inputs clk, bit_in, vec_in, wide_in, is_ref ); input clk; input bit_in; output bit_out; input [30:0] vec_in; output logic [30:0] vec_out; input [123:0] wide_in; output logic [123:0] wide_out; output did_init_out; input is_ref; reg did_init; initial did_init = 0; initial begin did_init = 1; end reg did_final; initial did_final = 0; final begin did_final = 1; if (!is_ref) $write("*-* All Finished *-*\n"); //$finish is in parent end // Note async use! wire bit_out = bit_in; wire did_init_out = did_init; always @ (posedge clk) begin vec_out <= vec_in; wide_out <= wide_in; end endmodule verilator-4.038/test_regress/t/t_pp_line_bad.out0000664000177100017500000000117113702133370021777 0ustar wsnyderwsnyder%Error: t/t_pp_line_bad.v:100:1: `line was not properly formed with '`line number "filename" level' 100 | `line 100 | ^ %Error: somefile:100:1: `line was not properly formed with '`line number "filename" level' 100 | `line 100 | ^ %Error: somefile:100:1: `line was not properly formed with '`line number "filename" level' %Error: t/t_pp_line_bad.v:7:1: Define or directive not defined: '`line' 7 | `line | ^~~~~ %Error: somefile:100:1: `line was not properly formed with '`line number "filename" level' t/t_pp_line_bad.v:101:1: ... note: In file included from t_pp_line_bad.v %Error: Exiting due to verilator-4.038/test_regress/t/t_lint_always_comb_bad.out0000664000177100017500000000223113702133370023675 0ustar wsnyderwsnyder%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:29:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1' : ... In instance t 29 | temp1 = 'h0; | ^~~~~ %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1' : ... In instance t 31 | temp1 = (temp1_d1r - 'h1); | ^~~~~ %Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:32:7: Always_comb variable driven after use: 'mid' : ... In instance t 32 | mid = (temp1_d1r == 'h0); | ^~~ ... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message. %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:46:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1_d1r' : ... In instance t 46 | temp1_d1r <= temp1; | ^~~~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_var_types.pl0000775000177100017500000000121713702133370021367 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{verilated_randReset} = 1; # allow checking if we initialize vars to zero only when needed compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_plog.pl0000775000177100017500000000105313702133370021325 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_gate_fdup.v0000664000177100017500000000124713702133370021143 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2005 by Thomas Dzetkulic. // SPDX-License-Identifier: CC0-1.0 module fnor2(f, a, b); parameter W = 1; output [W-1:0]f; input [W-1:0] a, b; supply0 gnd; supply1 vcc; generate genvar i; for (i = 0; i < W; i = i + 1) begin wire w; pmos(f[i], w, a[i]); pmos(w, vcc, b[i]); nmos(f[i], gnd, a[i]); nmos(f[i], gnd, b[i]); end endgenerate endmodule module t(f, a, b); output [1:0] f; input [1:0] a, b; fnor2 #(2) n(f, a, b); endmodule verilator-4.038/test_regress/t/t_lint_incabspath_bad.out0000664000177100017500000000051213702133370023511 0ustar wsnyderwsnyder%Warning-INCABSPATH: t/t_lint_incabspath.v:7:10: Suggest `include with absolute path be made relative, and use +include: /dev/null 7 | `include "/dev/null" | ^~~~~~~~~~~ ... Use "/* verilator lint_off INCABSPATH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_alw_reorder.pl0000775000177100017500000000214713702133367021671 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); compile( verilator_flags2 => ["--stats"], ); file_grep($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0); # Important: if reorder succeeded, we should see no dly vars. # Equally important: twin test t_alw_noreorder should see dly vars, # is identical to this test except for disabling the reorder step. foreach my $file ("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", "$Self->{obj_dir}/$Self->{VM_PREFIX}.h") { file_grep_not($file, qr/dly__t__DOT__v1/i); file_grep_not($file, qr/dly__t__DOT__v2/i); file_grep_not($file, qr/dly__t__DOT__v3/i); } execute( check_finished=>1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_skipidentical.pl0000775000177100017500000000213613702133370023170 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); { compile(); print "NOTE: use --debugi, as --debug in driver turns off skip-identical\n"; my $outfile = "$Self->{obj_dir}/V".$Self->{name}.".cpp"; my @oldstats = stat($outfile); print "Old mtime=",$oldstats[9],"\n"; $oldstats[9] or error("No output file found: $outfile\n"); sleep(2); # Or else it might take < 1 second to compile and see no diff. setenv('VERILATOR_DEBUG_SKIP_IDENTICAL', 1); compile(); my @newstats = stat($outfile); print "New mtime=",$newstats[9],"\n"; ($oldstats[9] == $newstats[9]) or error("--skip-identical was ignored -- recompiled\n"); } ok(1); 1; verilator-4.038/test_regress/t/t_math_const.pl0000775000177100017500000000105313702133370021510 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_large_methods.pl0000775000177100017500000000105313702133370023212 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_wire_behp1800_bad.v0000664000177100017500000000136213702133370022266 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output o, output [1:0] oa, output reg ro, output reg [1:0] roa, output wire wo, output wire [1:0] woa, // 1800 only output var vo, output var [1:0] voa ); wire w; reg r; initial begin w = '0; // Error o = '0; // Error oa = '0; // Error wo = '0; // Error woa = '0; // Error r = '0; // Not an error ro = '0; // Not an error roa = '0; // Not an error vo = '0; // Not an error voa = '0; // Not an error end endmodule verilator-4.038/test_regress/t/t_const_bad.v0000664000177100017500000000112313702133367021140 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); initial begin if (32'hxxxxxxxx !== 'hx) $stop; if (32'hzzzzzzzz !== 'hz) $stop; if (32'h???????? !== 'h?) $stop; if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; if (68'h?_????????_???????? !== 'd?) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_struct_unpacked_bad.out0000664000177100017500000000053213702133370023547 0ustar wsnyderwsnyder%Warning-UNPACKED: t/t_struct_unpacked_bad.v:9:12: Unsupported: Unpacked struct/union : ... In instance x 9 | typedef struct { | ^~~~~~ ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_case_write1.v0000664000177100017500000000217413702133367021421 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "verilated.v" `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [63:0] crc; integer fd; integer fdtmp; t_case_write1_tasks tasks (); integer cyc; initial cyc=0; always @ (posedge clk) begin $fwrite(fd, "[%0d] crc=%x ", cyc, crc); tasks.big_case(fd, crc[31:0]); $fwrite(fd, "\n"); end always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc); cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==1) begin crc <= 64'h00000000_00000097; $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"}); fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w"); fd <= fdtmp; end if (cyc==90) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_flag_debug_noleak.v0000664000177100017500000000047113702133370022613 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_flag_ldflags_a.cpp0000664000177100017500000000103613702133370022423 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* extern "C" { void dpii_a_library() {} }; verilator-4.038/test_regress/t/t_randomize.out0000664000177100017500000000167113702133370021540 0ustar wsnyderwsnyder%Error-UNSUPPORTED: t/t_randomize.v:11:4: Unsupported: extern constraint 11 | extern constraint ex; | ^~~~~~ %Error-UNSUPPORTED: t/t_randomize.v:29:29: Unsupported: solve before 29 | constraint order { solve length before header; } | ^~~~~~ %Error-UNSUPPORTED: t/t_randomize.v:32:16: Unsupported: dist :/ 32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5}; | ^ %Error-UNSUPPORTED: t/t_randomize.v:32:32: Unsupported: dist := 32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5}; | ^~~ %Error-UNSUPPORTED: t/t_randomize.v:32:42: Unsupported: dist := 32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5}; | ^~~ %Error-UNSUPPORTED: t/t_randomize.v:32:9: Unsupported: dist 32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5}; | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_tri_gate.cpp0000664000177100017500000000253513702133370021321 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = NULL; double sc_time_stamp() { return 0; } bool check() { bool pass; int c = (tb->A >> tb->SEL) & 0x1; #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif if (tb->W == c && tb->X == c && tb->Y == c && tb->Z == c) { pass = true; if (verbose) printf("- pass: "); } else { pass = false; verbose = true; printf("%%E-FAIL: "); } if (verbose) { printf("SEL=%d A=%d got: W=%d X=%d Y=%d Z=%d exp: WXYZ=%d\n", tb->SEL, tb->A, tb->W, tb->X, tb->Y, tb->Z, c); } return pass; } int main() { bool pass = true; Verilated::debug(0); tb = new VM_PREFIX("tb"); // loop through every possibility and check the result for (tb->SEL = 0; tb->SEL < 2; tb->SEL++) { for (tb->A = 0; tb->A < 4; tb->A++) { tb->eval(); if (!check()) { pass = false; } } } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from tristate test\n"); } return 0; } verilator-4.038/test_regress/t/t_flag_noop_bad.out0000664000177100017500000000014113702133370022311 0ustar wsnyderwsnyder%Error: verilator: Need --cc, --sc, --cdc, --dpi-hdr-only, --lint-only, --xml-only or --E option verilator-4.038/test_regress/t/t_slice_init.v0000664000177100017500000000364213702133370021330 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, d0, d1 ); input clk; input [7:0] d0, d1; logic [7:0] inia [1:0][3:0] = '{ '{ '0, '1, 8'hfe, 8'hed }, '{ '1, '1, 8'h11, 8'h22 }}; logic [7:0] inil [0:1][0:3] = '{ '{ '0, '1, 8'hfe, 8'hed }, '{ '1, '1, 8'h11, 8'h22 }}; logic [7:0] data [1:0][3:0]; logic [7:0] datl [0:1][0:3]; initial begin data = '{ '{ d0, d1, 8'hfe, 8'hed }, '{ d1, d1, 8'h11, 8'h22 }}; data[0] = '{ d0, d1, 8'h19, 8'h39 }; datl = '{ '{ d0, d1, 8'hfe, 8'hed }, '{ d1, d1, 8'h11, 8'h22 }}; datl[0] = '{ d0, d1, 8'h19, 8'h39 }; `ifdef TEST_VERBOSE $display("D=%x %x %x %x -> 39 19 x x", data[0][0], data[0][1], data[0][2], data[0][3]); $display("D=%x %x %x %x -> ed fe x x", data[1][0], data[1][1], data[1][2], data[1][3]); $display("L=%x %x %x %x -> x x 19 39", datl[0][0], datl[0][1], datl[0][2], datl[0][3]); $display("L=%x %x %x %x -> x x 11 12", datl[1][0], datl[1][1], datl[1][2], datl[1][3]); `endif if (inia[0][0] !== 8'h22) $stop; if (inia[0][1] !== 8'h11) $stop; if (inia[1][0] !== 8'hed) $stop; if (inia[1][1] !== 8'hfe) $stop; if (inil[0][2] !== 8'hfe) $stop; if (inil[0][3] !== 8'hed) $stop; if (inil[1][2] !== 8'h11) $stop; if (inil[1][3] !== 8'h22) $stop; if (data[0][0] !== 8'h39) $stop; if (data[0][1] !== 8'h19) $stop; if (data[1][0] !== 8'hed) $stop; if (data[1][1] !== 8'hfe) $stop; if (datl[0][2] !== 8'h19) $stop; if (datl[0][3] !== 8'h39) $stop; if (datl[1][2] !== 8'h11) $stop; if (datl[1][3] !== 8'h22) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_svl2.pl0000775000177100017500000000105313702133370021250 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2006 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_langext_3_bad.pl0000775000177100017500000000115513702133370022046 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); top_filename("t/t_langext_3.v"); # This is a lint only test. lint( v_flags2 => ["+1364-2001ext+v"], fails => 1 ); ok(1); 1; verilator-4.038/test_regress/t/t_math_signed2.v0000664000177100017500000000305213702133370021545 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2007 by Peter Debacker. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [10:0] in; reg signed[7:0] min; reg signed[7:0] max; wire signed[7:0] filtered_data; reg signed[7:0] delay_minmax[31:0]; integer k; initial begin in = 11'b10000001000; for(k=0;k<32;k=k+1) delay_minmax[k] = 0; end assign filtered_data = $signed(in[10:3]); always @(posedge clk) begin in = in + 8; `ifdef TEST_VERBOSE $write("filtered_data: %d\n", filtered_data); `endif // delay line shift for (k=31;k>0;k=k-1) begin delay_minmax[k] = delay_minmax[k-1]; end delay_minmax[0] = filtered_data; `ifdef TEST_VERBOSE $write("delay_minmax[0] = %d\n", delay_minmax[0]); $write("delay_minmax[31] = %d\n", delay_minmax[31]); `endif // find min and max min = 127; max = -128; `ifdef TEST_VERBOSE $write("max init: %d\n", max); $write("min init: %d\n", min); `endif for(k=0;k<32;k=k+1) begin if ((delay_minmax[k]) > $signed(max)) max = delay_minmax[k]; if ((delay_minmax[k]) < $signed(min)) min = delay_minmax[k]; end `ifdef TEST_VERBOSE $write("max: %d\n", max); $write("min: %d\n", min); `endif if (min == 127) begin $stop; end else if (filtered_data >= -61) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_debug_fatalsrc_bad.pl0000775000177100017500000000123513702133370023126 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--debug-fatalsrc"], fails => $Self->{vlt_all}, expect => '%Error: Internal Error: .*: --debug-fatal-src .* See the manual and .*', ); ok(1); 1; verilator-4.038/test_regress/t/t_class_virtual.pl0000775000177100017500000000107113702133367022232 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_mnpipe.pl0000775000177100017500000000106013702133370021674 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_plusargs_bad.pl0000775000177100017500000000105313702133370022715 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_vpi_1ms10ns.out0000664000177100017500000000125413702133370022643 0ustar wsnyderwsnyder:: In top.t Time scale of t is 1ms / 10ns [6000000] time%0d=60 123%0t=12300000 dig%0t=543200000 dig%0d=5432 rdig%0t=543210987 rdig%0f=5432.109877 [60000000.000000ns] time%0d=60 123%0t=123000000.000000ns dig%0t=5432000000.000000ns dig%0d=5432 rdig%0t=5432109876.543210ns rdig%0f=5432.109877 [60000000.000000ns] stime%0t=60000000.000000ns stime%0d=60 stime%0f=60.000000 [60000000.000000ns] rtime%0t=60000000.000000ns rtime%0d=60 rtime%0f=60.000000 global vpiSimTime = 0,6000000 vpiScaledRealTime = 6e+06 global vpiTimeUnit = -3 vpiTimePrecision = -8 top.t vpiSimTime = 0,6000000 vpiScaledRealTime = 60 top.t vpiTimeUnit = -3 vpiTimePrecision = -8 *-* All Finished *-* verilator-4.038/test_regress/t/t_mod_interface_array1.pl0000775000177100017500000000105313702133370023427 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_wire_behp1364_bad.v0000664000177100017500000000137213702133370022274 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output o, output [1:0] oa, output reg ro, output reg [1:0] roa, output wire wo, output wire [1:0] woa //1800 only: //output var vo; //output var [1:0] voa; ); wire w; reg r; initial begin w = '0; // Error o = '0; // Error oa = '0; // Error wo = '0; // Error woa = '0; // Error r = '0; // Not an error ro = '0; // Not an error roa = '0; // Not an error //vo = '0; // Not an error //voa = '0; // Not an error end endmodule verilator-4.038/test_regress/t/t_vpi_time_cb.cpp0000664000177100017500000001523513702133370022004 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #else #include "Vt_vpi_time_cb.h" #include "verilated.h" #include "svdpi.h" #include #include "Vt_vpi_time_cb__Dpi.h" #include "verilated_vpi.h" #include "verilated_vcd_c.h" #endif #include #include #include #include #include "TestSimulator.h" #include "TestVpi.h" #define TEST_MSG \ if (0) printf unsigned int main_time = 0; unsigned int callback_count_time1 = 3; unsigned int callback_count_time2 = 4; unsigned int callback_count_start_of_sim = 0; //====================================================================== #define CHECK_RESULT_VH(got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d: GOT = %p EXP = %p\n", __FILE__, __LINE__, (got), (exp)); \ return __LINE__; \ } #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", __FILE__, __LINE__); \ return __LINE__; \ } // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_HEX(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << hex \ << ": GOT = " << (got) << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", __FILE__, __LINE__, \ (got) ? (got) : "", (exp) ? (exp) : ""); \ return __LINE__; \ } #define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp) // We cannot replace those with VL_STRINGIFY, not available when PLI is build #define STRINGIFY(x) STRINGIFY2(x) #define STRINGIFY2(x) #x //====================================================================== #ifdef IS_VPI static int _time_cb1(p_cb_data cb_data) { s_vpi_time t; t.type = vpiSimTime; vpi_get_time(0, &t); // fprintf(stdout, "time_cb1: %d\n", t.low); CHECK_RESULT(callback_count_time1, t.low); callback_count_time1++; t_cb_data cb_data_n; bzero(&cb_data_n, sizeof(cb_data_n)); cb_data_n.reason = cbAfterDelay; t.type = vpiSimTime; t.high = 0; t.low = 1; cb_data_n.time = &t; cb_data_n.cb_rtn = _time_cb1; vpi_register_cb(&cb_data_n); return 0; } static int _time_cb2(p_cb_data cb_data) { s_vpi_time t; t.type = vpiSimTime; vpi_get_time(0, &t); // fprintf(stdout, "time_cb2: %d\n", t.low); CHECK_RESULT(callback_count_time2, t.low); callback_count_time2++; t_cb_data cb_data_n; bzero(&cb_data_n, sizeof(cb_data_n)); cb_data_n.reason = cbAfterDelay; t.type = vpiSimTime; t.high = 0; t.low = 1; cb_data_n.time = &t; cb_data_n.cb_rtn = _time_cb2; vpi_register_cb(&cb_data_n); return 0; } static int _start_of_sim_cb(p_cb_data cb_data) { t_cb_data cb_data_n1, cb_data_n2; bzero(&cb_data_n1, sizeof(cb_data_n1)); bzero(&cb_data_n2, sizeof(cb_data_n2)); s_vpi_time t1, t2; cb_data_n1.reason = cbAfterDelay; t1.type = vpiSimTime; t1.high = 0; t1.low = 3; cb_data_n1.time = &t1; cb_data_n1.cb_rtn = _time_cb1; vpi_register_cb(&cb_data_n1); cb_data_n2.reason = cbAfterDelay; t2.type = vpiSimTime; t2.high = 0; t2.low = 4; cb_data_n2.time = &t2; cb_data_n2.cb_rtn = _time_cb2; vpi_register_cb(&cb_data_n2); callback_count_start_of_sim++; return 0; } static int _end_of_sim_cb(p_cb_data cb_data) { CHECK_RESULT(callback_count_start_of_sim, 1); fprintf(stdout, "*-* All Finished *-*\n"); return 0; } // cver entry #ifdef __cplusplus extern "C" #endif void vpi_compat_bootstrap(void) { t_cb_data cb_data; bzero(&cb_data, sizeof(cb_data)); // VL_PRINTF("register start-of-sim callback\n"); cb_data.reason = cbStartOfSimulation; cb_data.time = 0; cb_data.cb_rtn = _start_of_sim_cb; vpi_register_cb(&cb_data); cb_data.reason = cbEndOfSimulation; cb_data.time = 0; cb_data.cb_rtn = _end_of_sim_cb; vpi_register_cb(&cb_data); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { double sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out #ifdef VERILATOR # ifdef TEST_VERBOSE Verilated::scopesDump(); # endif #endif #if VM_TRACE Verilated::traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif // Load and initialize the PLI application { const char* filenamep = STRINGIFY(TEST_OBJ_DIR) "/libvpi.so"; void* lib = dlopen(filenamep, RTLD_LAZY); void* bootstrap = dlsym(lib, "vpi_compat_bootstrap"); if (!bootstrap) { std::string msg = std::string("%Error: Could not dlopen ") + filenamep; vl_fatal(__FILE__, __LINE__, "main", msg.c_str()); } ((void (*)(void))bootstrap)(); } VerilatedVpi::callCbs(cbStartOfSimulation); topp->eval(); topp->clk = 0; main_time += 1; while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += 1; topp->eval(); VerilatedVpi::callValueCbs(); VerilatedVpi::callTimedCbs(); CHECK_RESULT(VerilatedVpi::cbNextDeadline(), main_time+1); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } VerilatedVpi::callCbs(cbEndOfSimulation); if (!Verilated::gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete topp, topp); exit(0L); } #endif verilator-4.038/test_regress/t/t_pp_defkwd_bad.pl0000775000177100017500000000107413702133370022125 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_inside_cond_bad.out0000664000177100017500000000026613702133367024222 0ustar wsnyderwsnyder[10] %Error: t_assert_inside_cond.v:39: Assertion failed in top.t: synthesis parallel_case, but multiple matches found %Error: t/t_assert_inside_cond.v:39: Verilog $stop Aborting... verilator-4.038/test_regress/t/t_math_pick.v0000664000177100017500000000433513702133370021145 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire pick1 = crc[0]; wire [13:0][1:0] data1 = crc[27+1:1]; wire [3:0][2:0][1:0] data2 = crc[23+29:29]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [15:0] [1:0] datao; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .datao (datao/*[15:0][1:0]*/), // Inputs .pick1 (pick1), .data1 (data1/*[13:0][1:0]*/), .data2 (data2/*[2:0][3:0][1:0]*/)); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, datao}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3ff4bf0e6407b281 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input logic pick1, input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits output logic [15:0] [1:0] datao // 16 x 2 = 32 bits ); // verilator lint_off WIDTH always_comb datao[13: 0] // 28 bits = (pick1) ? {data1} // 28 bits : {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized // verilator lint_on WIDTH always_comb datao[15:14] = '0; endmodule verilator-4.038/test_regress/t/t_debug_exit_parse.pl0000775000177100017500000000115213702133370022662 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t_EXAMPLE.v"); lint( verilator_flags2 => ["--debug-exit-parse"], expect => '--debug-exit-parse', ); ok(1); 1; verilator-4.038/test_regress/t/t_math_swap.v0000664000177100017500000001022713702133370021166 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] Operand1 = crc[31:0]; wire [15:0] Operand2 = crc[47:32]; wire Unsigned = crc[48]; reg rst; parameter wl = 16; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [wl-1:0] Quotient; // From test of Test.v wire [wl-1:0] Remainder; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .Quotient (Quotient[wl-1:0]), .Remainder (Remainder[wl-1:0]), // Inputs .Operand1 (Operand1[wl*2-1:0]), .Operand2 (Operand2[wl-1:0]), .clk (clk), .rst (rst), .Unsigned (Unsigned)); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, Quotient, Remainder}; // What checksum will we end up with `define EXPECTED_SUM 64'h98d41f89a8be5693 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x it=%x\n",$time, cyc, crc, result, test.Iteration); `endif cyc <= cyc + 1; if (cyc < 20 || test.Iteration==4'd15) begin crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; end sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; rst <= 1'b1; end else if (cyc<20) begin sum <= 64'h0; rst <= 1'b0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'h8dd70a44972ad809) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder); parameter wl = 16; input [wl*2-1:0] Operand1; input [wl-1:0] Operand2; input clk, rst, Unsigned; output [wl-1:0] Quotient, Remainder; reg Cy, Overflow, Sign1, Sign2, Zero, Negative; reg [wl-1:0] ah,al,Quotient, Remainder; reg [3:0] Iteration; reg [wl-1:0] sub_quot,op; reg ah_ext; reg [1:0] a,b,c,d,e; always @(posedge clk) begin if (!rst) begin {a,b,c,d,e} = Operand1[9:0]; {a,b,c,d,e} = {e,d,c,b,a}; if (a != Operand1[1:0]) $stop; if (b != Operand1[3:2]) $stop; if (c != Operand1[5:4]) $stop; if (d != Operand1[7:6]) $stop; if (e != Operand1[9:8]) $stop; end end always @(posedge clk) begin if (rst) begin Iteration <= 0; Quotient <= 0; Remainder <= 0; end else begin if (Iteration == 0) begin {ah,al} = Operand1; op = Operand2; Cy = 0; Overflow = 0; Sign1 = (~Unsigned)&ah[wl-1]; Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]); if (Sign1) {ah,al} = -{ah,al}; end `define BUG1 `ifdef BUG1 {ah_ext,ah,al} = {ah,al,Cy}; `else ah_ext = ah[15]; ah[15:1] = ah[14:0]; ah[0] = al[15]; al[15:1] = al[14:0]; al[0] = Cy; `endif `ifdef TEST_VERBOSE $display("%x %x %x %x %x %x %x %x %x", Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy); `endif {Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op}; if (Cy) begin {ah_ext,ah} = {1'b0,sub_quot}; end if (Iteration != 15 ) begin if (ah_ext) Overflow = 1; end else begin if (al[14] && ~Unsigned) Overflow = 1; Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy}; Remainder <= Sign1 ? -ah : ah; if (Overflow) begin Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}}; Remainder <= Unsigned ? 16'hffff : 16'h8000; Zero = 1; Negative = 1; end end Iteration <= Iteration + 1; // Count number of times this instruction is repeated end end endmodule verilator-4.038/test_regress/t/t_func_named.pl0000775000177100017500000000105313702133370021450 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_param_loop_bad.pl0000775000177100017500000000120113702133370024323 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, bug1626"); scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_gen_assign.v0000664000177100017500000000240613702133370021320 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [63:0] crc; reg [31:0] sum; wire [8:0] Output; wire [8:0] Input = crc[8:0]; assigns assigns (/*AUTOINST*/ // Outputs .Output (Output[8:0]), // Inputs .Input (Input[8:0])); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 32'h0; end else if (cyc>10 && cyc<90) begin sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]}; end else if (cyc==99) begin if (sum !== 32'he8bbd130) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module assigns(Input, Output); input [8:0] Input; output [8:0] Output; genvar i; generate for (i = 0; i < 8; i = i + 1) begin : ap assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8]; end endgenerate endmodule verilator-4.038/test_regress/t/t_interface_typo_bad.v0000664000177100017500000000103713702133370023023 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 //bug1097 interface foo_intf; endinterface module submod ( foo_intf foo ); endmodule module t (/*AUTOARG*/); // Intentional typo, compiler should point this out, or that fo_intf does // not match foo_intf on the submod port map fo_intf the_foo; submod submod_inst ( .foo (the_foo) ); endmodule verilator-4.038/test_regress/t/t_interface_gen.v0000664000177100017500000000353713702133370022002 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing `ifdef VCS `define UNSUPPORTED_MOD_IN_GENS `endif `ifdef VERILATOR `define UNSUPPORTED_MOD_IN_GENS `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc #(1) itopa(); ifc #(2) itopb(); sub #(1) ca (.isub(itopa), .i_value(4)); sub #(2) cb (.isub(itopb), .i_value(5)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin if (itopa.MODE != 1) $stop; if (itopb.MODE != 2) $stop; end if (cyc==20) begin if (itopa.get_value() != 4) $stop; if (itopb.get_value() != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub #(parameter MODE = 0) ( ifc.out_modport isub, input integer i_value ); `ifdef UNSUPPORTED_MOD_IN_GENS always @* isub.value = i_value; `else generate if (MODE == 1) begin always @* isub.valuea = i_value; end else if (MODE == 2) begin always @* isub.valueb = i_value; end endgenerate `endif endmodule interface ifc; parameter MODE = 0; // Modports under generates not supported by all commercial simulators `ifdef UNSUPPORTED_MOD_IN_GENS integer value; modport out_modport (output value); function integer get_value(); return value; endfunction `else generate if (MODE == 0) begin integer valuea; modport out_modport (output valuea); function integer get_valuea(); return valuea; endfunction end else begin integer valueb; modport out_modport (output valueb); function integer get_valueb(); return valueb; endfunction end endgenerate `endif endinterface verilator-4.038/test_regress/t/t_math_shift_over_bad.pl0000775000177100017500000000107413702133370023343 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_cover_sva_trace.pl0000775000177100017500000000136513702133370022524 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_cover_sva_notflat.v"); compile( verilator_flags2 => ['--assert --cc --coverage-user --trace --trace-coverage'], ); execute( check_finished => 1, ); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_trace_packed_struct_fst.pl0000775000177100017500000000127013702133370024237 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_trace_packed_struct.v"); compile( v_flags2 => ["--trace-fst"] ); execute( check_finished => 1, ); fst_identical($Self->trace_filename, $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_uniqueif_fail2.pl0000775000177100017500000000142613702133370022257 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_uniqueif.v"); compile( v_flags2 => ['+define+FAILING_ASSERTION2'], verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], fails => $Self->{nc}, ); execute( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_time_sc_bad.out0000664000177100017500000000030613702133370021773 0ustar wsnyderwsnyder%Error: SystemC's sc_set_time_resolution is 10^-9, which does not match Verilog timeprecision 10^-12. Suggest use 'sc_set_time_resolution(1s)', or Verilator '--timescale-override 1s/1s' Aborting... verilator-4.038/test_regress/t/t_cdc_async_bad.v0000664000177100017500000000420113702133367021740 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs q0, q1, q2, q3, q4, q5, q6a, q6b, // Inputs clk, d, rst0_n ); input clk; input d; // OK -- from primary input rst0_n; output wire q0; Flop flop0 (.q(q0), .rst_n(rst0_n), .clk(clk), .d(d)); // OK -- from flop reg rst1_n; always @ (posedge clk) rst1_n <= rst0_n; output wire q1; Flop flop1 (.q(q1), .rst_n(rst1_n), .clk(clk), .d(d)); // Bad - logic wire rst2_bad_n = rst0_n | rst1_n; output wire q2; Flop flop2 (.q(q2), .rst_n(rst2_bad_n), .clk(clk), .d(d)); // Bad - logic in submodule wire rst3_bad_n; Sub sub (.z(rst3_bad_n), .a(rst0_n), .b(rst1_n)); output wire q3; Flop flop3 (.q(q3), .rst_n(rst3_bad_n), .clk(clk), .d(d)); // OK - bit selection reg [3:0] rst4_n; always @ (posedge clk) rst4_n <= {4{rst0_n}}; output wire q4; Flop flop4 (.q(q4), .rst_n(rst4_n[1]), .clk(clk), .d(d)); // Bad - logic, but waived // verilator lint_off CDCRSTLOGIC wire rst5_waive_n = rst0_n & rst1_n; // verilator lint_on CDCRSTLOGIC output wire q5; Flop flop5 (.q(q5), .rst_n(rst5_waive_n), .clk(clk), .d(d)); // Bad - for graph test - logic feeds two signals, three destinations wire rst6_bad_n = rst0_n ^ rst1_n; wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); // $c prevents optimization wire rst6b_bad_n = rst6_bad_n ^ $c1("1"); output wire q6a; output wire q6b; Flop flop6a (.q(q6a), .rst_n(rst6a_bad_n), .clk(clk), .d(d)); Flop flop6v (.q(q6b), .rst_n(rst6b_bad_n), .clk(clk), .d(d)); initial begin $display("%%Error: Not a runnable test"); $stop; end endmodule module Flop ( input clk, input d, input rst_n, output logic q); always @ (posedge clk or negedge rst_n) begin if (!rst_n) q <= 1'b0; else q <= d; end endmodule module Sub (input a, b, output z); assign z = a|b; endmodule verilator-4.038/test_regress/t/t_gate_array.v0000664000177100017500000000423413702133370021322 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] a = crc[7:0]; wire [7:0] b = crc[15:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [63:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[63:0]), // Inputs .clk (clk), .a (a[7:0]), .b (b[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0908a1f2194d24ee if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, a, b ); input clk; input [7:0] a; input [7:0] b; output reg [63:0] out; and u0[7:0] (out[7:0], a[7:0], b[7:0]); and u1[7:0] (out[15:8], a[0], b[7:0]); and u2[7:0] (out[23:16], a[0], b[0]); nand u3[7:0] (out[31:24], a[0], b[7:0]); or u4[7:0] (out[39:32], a[0], b[7:0]); nor u5[7:0] (out[47:40], a[0], b[7:0]); xor u6[7:0] (out[55:48], a[0], b[7:0]); xnor u7[7:0] (out[63:56], a[0], b[7:0]); endmodule verilator-4.038/test_regress/t/t_display_merge.v0000664000177100017500000000255513702133370022034 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); initial begin $display("Merge:"); $write("This "); $write("should "); $display("merge"); $display("f"); $display(" a=%m"); $display(" b=%m"); $display(" pre"); $display(" t=%0d",$time); $display(" t2=%0d",$time); $display(" post"); $display(" t3=%0d",$time); $display(" t4=%0d t5=%0d",$time,$time,$time); $display("m"); $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time); $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time); $display("mm"); $display(""); $write("f"); $write(" a=%m"); $write(" b=%m"); $write(" pre"); $write(" t=%0d",$time); $write(" t2=%0d",$time); $write(" post"); $write(" t3=%0d",$time); $write(" t4=%0d t5=%0d",$time,$time,$time); $write("m"); $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time); $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d",$time,$time,$time,$time,$time); $display("mm"); $write("\n*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_concat_link_bad.out0000664000177100017500000000155213702133367022646 0ustar wsnyderwsnyder%Error: t/t_concat_link_bad.v:13:20: Syntax Error: Not expecting REPLICATE under a DOT in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ %Error: t/t_concat_link_bad.v:13:26: Syntax Error: Not expecting CONCAT under a REPLICATE in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ %Error: t/t_concat_link_bad.v:13:20: Syntax Error: Not expecting CONST under a REPLICATE in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ %Warning-IMPLICIT: t/t_concat_link_bad.v:13:12: Signal definition not found, creating implicitly: 'bar_s' 13 | assign bar_s = {foo_s, foo_s}.f1; | ^~~~~ ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-4.038/test_regress/t/t_sv_conditional.v0000664000177100017500000003466413702133370022231 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: System Verilog test of case and if // // This code instantiates and runs a simple CPU written in System Verilog. // // This file ONLY is placed into the Public Domain, for any use, without // warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. module t (/*AUTOARG*/ // Inputs clk ); input clk; /*AUTOWIRE*/ // ************************************************************************** // Regs and Wires // ************************************************************************** reg rst; integer rst_count; st3_testbench st3_testbench_i (/*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); // ************************************************************************** // Reset Generation // ************************************************************************** initial begin rst = 1'b1; rst_count = 0; end always @( posedge clk ) begin if (rst_count < 2) begin rst_count++; end else begin rst = 1'b0; end end // ************************************************************************** // Closing message // ************************************************************************** final begin $write("*-* All Finished *-*\n"); end endmodule module st3_testbench (/*AUTOARG*/ // Inputs clk, rst ); input clk; input rst; logic clk; logic rst; logic [8*16-1:0] wide_input_bus; logic decrementA; // 0=Up-counting, 1=down-counting logic dual_countA; // Advance counter by 2 steps at a time logic cntA_en; // Enable Counter A logic decrementB; // 0=Up-counting, 1=down-counting logic dual_countB; // Advance counter by 2 steps at a time logic cntB_en; // Enable counter B logic [47:0] selected_out; integer i; initial begin decrementA = 1'b0; dual_countA = 1'b0; cntA_en = 1'b1; decrementB = 1'b0; dual_countB = 1'b0; cntB_en = 1'b1; wide_input_bus = {8'hf5, 8'hef, 8'hd5, 8'hc5, 8'hb5, 8'ha5, 8'h95, 8'h85, 8'ha7, 8'ha6, 8'ha5, 8'ha4, 8'ha3, 8'ha2, 8'ha1, 8'ha0}; i = 0; end simple_test_3 simple_test_3_i (// Outputs .selected_out (selected_out[47:0]), // Inputs .wide_input_bus (wide_input_bus[8*16-1:0]), .rst (rst), .clk (clk), .decrementA (decrementA), .dual_countA (dual_countA), .cntA_en (cntA_en), .decrementB (decrementB), .dual_countB (dual_countB), .cntB_en (cntB_en)); // Logic to print outputs and then finish. always @(posedge clk) begin if (i < 50) begin `ifdef TEST_VERBOSE $display("%x", simple_test_3_i.cntA_reg ,"%x", simple_test_3_i.cntB_reg ," ", "%x", selected_out); `endif i <= i + 1; end else begin $finish(); end end // always @ (posedge clk) endmodule // Module testing: // - Unique case // - Priority case // - Unique if // - ++, --, =- and =+ operands. module simple_test_3 (input logic [8*16-1:0] wide_input_bus, input logic rst, input logic clk, // Counter A input logic decrementA, // 0=Up-counting, 1=down-counting input logic dual_countA, // Advance counter by 2 steps at a time input logic cntA_en, // Enable Counter A // Counter B input logic decrementB, // 0=Up-counting, 1=down-counting input logic dual_countB, // Advance counter by 2 steps at a time input logic cntB_en, // Enable counter B // Outputs output logic [47:0] selected_out); // Declarations logic [3:0] cntA_reg; // Registered version of cntA logic [3:0] cntB_reg; // Registered version of cntA counterA counterA_inst (/*AUTOINST*/ // Outputs .cntA_reg (cntA_reg[3:0]), // Inputs .decrementA (decrementA), .dual_countA (dual_countA), .cntA_en (cntA_en), .clk (clk), .rst (rst)); counterB counterB_inst (/*AUTOINST*/ // Outputs .cntB_reg (cntB_reg[3:0]), // Inputs .decrementB (decrementB), .dual_countB (dual_countB), .cntB_en (cntB_en), .clk (clk), .rst (rst)); simple_test_3a sta (.wide_input_bus (wide_input_bus), .selector (cntA_reg), .selected_out (selected_out[7:0])); simple_test_3b stb (.wide_input_bus (wide_input_bus), .selector (cntA_reg), .selected_out (selected_out[15:8])); simple_test_3c stc (.wide_input_bus (wide_input_bus), .selector (cntB_reg), .selected_out (selected_out[23:16])); simple_test_3d std (.wide_input_bus (wide_input_bus), .selector (cntB_reg), .selected_out (selected_out[31:24])); simple_test_3e ste (.wide_input_bus (wide_input_bus), .selector (cntB_reg), .selected_out (selected_out[39:32])); simple_test_3f stf (.wide_input_bus (wide_input_bus), .selector (cntB_reg), .selected_out (selected_out[47:40])); endmodule // simple_test_3 module counterA (output logic [3:0] cntA_reg, // Registered version of cntA input logic decrementA, // 0=Up-counting, 1=down-counting input logic dual_countA, // Advance counter by 2 steps at a time input logic cntA_en, // Enable Counter A input logic clk, // Clock input logic rst); // Synchronous reset logic [3:0] cntA; // combinational count variable. // Counter A // Sequential part of counter CntA always_ff @(posedge clk) begin cntA_reg <= cntA; end // Combinational part of counter // Had to be split up to test C-style update, as there are no // non-blocking version like -<= always_comb if (rst) cntA = 0; else begin cntA = cntA_reg; // Necessary to avoid latch if (cntA_en) begin if (decrementA) if (dual_countA) //cntA = cntA - 2; cntA -= 2; else //cntA = cntA - 1; cntA--; else if (dual_countA) //cntA = cntA + 2; cntA += 2; else //cntA = cntA + 1; cntA++; end // if (cntA_en) end endmodule // counterA module counterB (output logic [3:0] cntB_reg, // Registered version of cntA input logic decrementB, // 0=Up-counting, 1=down-counting input logic dual_countB, // Advance counter by 2 steps at a time input logic cntB_en, // Enable counter B input logic clk, // Clock input logic rst); // Synchronous reset // Counter B - tried to write sequential only, but ended up without // SystemVerilog. always_ff @(posedge clk) begin if (rst) cntB_reg <= 0; else if (cntB_en) begin if (decrementB) if (dual_countB) cntB_reg <= cntB_reg - 2; else cntB_reg <= cntB_reg - 1; // Attempts to write in SystemVerilog: else if (dual_countB) cntB_reg <= cntB_reg + 2; else cntB_reg <= cntB_reg + 1; // Attempts to write in SystemVerilog: end end // always_ff @ endmodule // A multiplexor in terms of look-up module simple_test_3a (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb selected_out = {wide_input_bus[selector*8+7], wide_input_bus[selector*8+6], wide_input_bus[selector*8+5], wide_input_bus[selector*8+4], wide_input_bus[selector*8+3], wide_input_bus[selector*8+2], wide_input_bus[selector*8+1], wide_input_bus[selector*8]}; endmodule // simple_test_3a // A multiplexer in terms of standard case module simple_test_3b (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin case (selector) 4'h0: selected_out = wide_input_bus[ 7: 0]; 4'h1: selected_out = wide_input_bus[ 15: 8]; 4'h2: selected_out = wide_input_bus[ 23: 16]; 4'h3: selected_out = wide_input_bus[ 31: 24]; 4'h4: selected_out = wide_input_bus[ 39: 32]; 4'h5: selected_out = wide_input_bus[ 47: 40]; 4'h6: selected_out = wide_input_bus[ 55: 48]; 4'h7: selected_out = wide_input_bus[ 63: 56]; 4'h8: selected_out = wide_input_bus[ 71: 64]; 4'h9: selected_out = wide_input_bus[ 79: 72]; 4'ha: selected_out = wide_input_bus[ 87: 80]; 4'hb: selected_out = wide_input_bus[ 95: 88]; 4'hc: selected_out = wide_input_bus[103: 96]; 4'hd: selected_out = wide_input_bus[111:104]; 4'he: selected_out = wide_input_bus[119:112]; 4'hf: selected_out = wide_input_bus[127:120]; endcase // case (selector) end endmodule // simple_test_3b // A multiplexer in terms of unique case module simple_test_3c (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin unique case (selector) 4'h0: selected_out = wide_input_bus[ 7: 0]; 4'h1: selected_out = wide_input_bus[ 15: 8]; 4'h2: selected_out = wide_input_bus[ 23: 16]; 4'h3: selected_out = wide_input_bus[ 31: 24]; 4'h4: selected_out = wide_input_bus[ 39: 32]; 4'h5: selected_out = wide_input_bus[ 47: 40]; 4'h6: selected_out = wide_input_bus[ 55: 48]; 4'h7: selected_out = wide_input_bus[ 63: 56]; 4'h8: selected_out = wide_input_bus[ 71: 64]; 4'h9: selected_out = wide_input_bus[ 79: 72]; 4'ha: selected_out = wide_input_bus[ 87: 80]; 4'hb: selected_out = wide_input_bus[ 95: 88]; 4'hc: selected_out = wide_input_bus[103: 96]; 4'hd: selected_out = wide_input_bus[111:104]; 4'he: selected_out = wide_input_bus[119:112]; 4'hf: selected_out = wide_input_bus[127:120]; endcase // case (selector) end endmodule // simple_test_3c // A multiplexer in terms of unique if module simple_test_3d (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin unique if (selector == 4'h0) selected_out = wide_input_bus[ 7: 0]; else if (selector == 4'h1) selected_out = wide_input_bus[ 15: 8]; else if (selector == 4'h2) selected_out = wide_input_bus[ 23: 16]; else if (selector == 4'h3) selected_out = wide_input_bus[ 31: 24]; else if (selector == 4'h4) selected_out = wide_input_bus[ 39: 32]; else if (selector == 4'h5) selected_out = wide_input_bus[ 47: 40]; else if (selector == 4'h6) selected_out = wide_input_bus[ 55: 48]; else if (selector == 4'h7) selected_out = wide_input_bus[ 63: 56]; else if (selector == 4'h8) selected_out = wide_input_bus[ 71: 64]; else if (selector == 4'h9) selected_out = wide_input_bus[ 79: 72]; else if (selector == 4'ha) selected_out = wide_input_bus[ 87: 80]; else if (selector == 4'hb) selected_out = wide_input_bus[ 95: 88]; else if (selector == 4'hc) selected_out = wide_input_bus[103: 96]; else if (selector == 4'hd) selected_out = wide_input_bus[111:104]; else if (selector == 4'he) selected_out = wide_input_bus[119:112]; else if (selector == 4'hf) selected_out = wide_input_bus[127:120]; end endmodule // simple_test_3d // Test of priority case // Note: This does NOT try to implement the same function as above. module simple_test_3e (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin priority case (1'b1) selector[0]: selected_out = wide_input_bus[ 7: 0]; // Bit 0 has highets priority selector[2]: selected_out = wide_input_bus[ 39: 32]; // Note 2 higher priority than 1 selector[1]: selected_out = wide_input_bus[ 23: 16]; // Note 1 lower priority than 2 selector[3]: selected_out = wide_input_bus[ 71: 64]; // Bit 3 has lowest priority default: selected_out = wide_input_bus[127:120]; // for selector = 0. endcase // case (selector) end endmodule // simple_test_3e // Test of "inside" // Note: This does NOT try to implement the same function as above. // Note: Support for "inside" is a separate Verilator feature request, so is // not used inside a this version of the test. module simple_test_3f (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin /* -----\/----- EXCLUDED -----\/----- if ( selector[3:0] inside { 4'b?00?, 4'b1100}) // Matching 0000, 0001, 1000, 1100, 1001 // if ( selector[3:2] inside { 2'b?0, selector[1:0]}) selected_out = wide_input_bus[ 7: 0]; else -----/\----- EXCLUDED -----/\----- */ /* verilator lint_off CASEOVERLAP */ priority casez (selector[3:0]) 4'b0?10: selected_out = wide_input_bus[ 15: 8]; // Matching 0010 and 0110 4'b0??0: selected_out = wide_input_bus[ 23: 16]; // Overlap: only 0100 remains (0000 in "if" above) 4'b0100: selected_out = wide_input_bus[ 31: 24]; // Overlap: Will never occur default: selected_out = wide_input_bus[127:120]; // Remaining 0011,0100,0101,0111,1010,1011,1101,1110,1111 endcase // case (selector) /* verilator lint_on CASEOVERLAP */ end endmodule // simple_test_3f verilator-4.038/test_regress/t/t_interface_gen6_noinl.pl0000775000177100017500000000116013702133370023426 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_interface_gen6.v"); compile( v_flags2 => ["-Oi"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_altera_lpm_inv.pl0000775000177100017500000000120613702133367022353 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_math_vliw.v0000664000177100017500000000560713702133370021203 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=0; reg [7:0] crc; reg [223:0] sum; wire [255:0] mglehy = {32{~crc}}; wire [215:0] drricx = {27{crc}}; wire [15:0] apqrli = {2{~crc}}; wire [2:0] szlfpf = crc[2:0]; wire [15:0] dzosui = {2{crc}}; wire [31:0] zndrba = {16{crc[1:0]}}; wire [223:0] bxiouf; vliw vliw ( // Outputs .bxiouf (bxiouf), // Inputs .mglehy (mglehy[255:0]), .drricx (drricx[215:0]), .apqrli (apqrli[15:0]), .szlfpf (szlfpf[2:0]), .dzosui (dzosui[15:0]), .zndrba (zndrba[31:0])); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==0) begin // Setup crc <= 8'hed; sum <= 224'h0; end else if (cyc<90) begin //$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf); sum <= {sum[222:0],sum[223]} ^ bxiouf; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum); if (crc !== 8'b01110000) $stop; if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module vliw ( input[255:0] mglehy, input[215:0] drricx, input[15:0] apqrli, input[2:0] szlfpf, input[15:0] dzosui, input[31:0] zndrba, output wire [223:0] bxiouf ); wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]}) | ({29{apqrli}} & {mglehy[247:0], drricx}); wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128]) | ({21{dzosui}} & zhknfc[335:0]); wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000}; wire [223:0] rzyeut = viuvoc[335:112]; assign bxiouf = {rzyeut[7:0], rzyeut[15:8], rzyeut[23:16], rzyeut[31:24], rzyeut[39:32], rzyeut[47:40], rzyeut[55:48], rzyeut[63:56], rzyeut[71:64], rzyeut[79:72], rzyeut[87:80], rzyeut[95:88], rzyeut[103:96], rzyeut[111:104], rzyeut[119:112], rzyeut[127:120], rzyeut[135:128], rzyeut[143:136], rzyeut[151:144], rzyeut[159:152], rzyeut[167:160], rzyeut[175:168], rzyeut[183:176], rzyeut[191:184], rzyeut[199:192], rzyeut[207:200], rzyeut[215:208], rzyeut[223:216]}; endmodule verilator-4.038/test_regress/t/t_trace_public_sig.vlt0000664000177100017500000000037613702133370023045 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config public -module "glbl" -var "GSR" verilator-4.038/test_regress/t/t_clk_first_bad.pl0000775000177100017500000000121713702133367022147 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_clk_first_deprecated.v"); lint( verilator_flags2 => ["--lint-only"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_udp.pl0000775000177100017500000000122313702133370020140 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_udp.v"); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); execute( ) if !$Self->{vlt_all}; ok(1); 1; verilator-4.038/test_regress/t/t_math_strwidth.pl0000775000177100017500000000110413702133370022227 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => [], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_wfatal.pl0000775000177100017500000000122113702133370021615 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_flag_wfatal.v"); lint( verilator_flags2 => ["--lint-only -Wno-fatal"], fails => 0, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_case_x_bad.v0000664000177100017500000000077113702133367021264 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [3:0] value; always @ (/*AS*/value) begin casex (value) default: $stop; endcase case (value) 4'b0000: $stop; 4'b1xxx: $stop; default: $stop; endcase end endmodule verilator-4.038/test_regress/t/t_lint_latch_bad.pl0000775000177100017500000000120113702133370022273 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wwarn-style -Wno-DECLFILENAME"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_timescale_override2.out0000664000177100017500000000006113702133370024460 0ustar wsnyderwsnyderTime scale of t is 1s / 1us *-* All Finished *-* verilator-4.038/test_regress/t/t_order_b.v0000664000177100017500000000071313702133370020616 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_order_b (/*AUTOARG*/ // Outputs o_subfrom_clk_lev2, // Inputs m_from_clk_lev1_r ); input [7:0] m_from_clk_lev1_r; output [7:0] o_subfrom_clk_lev2; wire [7:0] o_subfrom_clk_lev2 = m_from_clk_lev1_r; endmodule verilator-4.038/test_regress/t/t_pp_line_bad.pl0000775000177100017500000000114113702133370021603 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( verilator_flags2 => ["-Wpedantic"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_tri_array_pull.pl0000775000177100017500000000105313702133370022401 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_asvar_bad.v0000664000177100017500000000111713702133370023143 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); counter_if iface(); source source ( .itf (iface) ); endmodule interface counter_if; logic [3:0] value; endinterface module source ( counter_if itf ); logic [3:0] getter; initial begin getter = itf; // Intended to write itf.value getter = 4'd3 + itf; // Intended to write itf.value end endmodule verilator-4.038/test_regress/t/t_select_little_pack.pl0000775000177100017500000000105313702133370023203 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_subout_bad.v0000664000177100017500000000064513702133370022363 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNDRIVEN module t(); wire sig; sub sub0(.out(33'b0)); sub sub1(.out({32'b0, sig})); sub sub2(.out({32'b1, sig})); endmodule module sub(output reg [32 : 0] out); endmodule verilator-4.038/test_regress/t/t_verilated_all.v0000664000177100017500000000126513702133370022014 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc!=0) begin if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); export "DPI-C" function dpix_f_int; function int dpix_f_int (); return cyc; endfunction endmodule verilator-4.038/test_regress/t/t_case_huge_sub4.v0000664000177100017500000000342213702133367022070 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub4 (/*AUTOARG*/ // Outputs outq, // Inputs index ); input [7:0] index; output [9:0] outq; // ============================= /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [9:0] outq; // End of automatics // ============================= always @(/*AS*/index) begin case (index) // default below: no change 8'h00: begin outq = 10'h001; end 8'he0: begin outq = 10'h05b; end 8'he1: begin outq = 10'h126; end 8'he2: begin outq = 10'h369; end 8'he3: begin outq = 10'h291; end 8'he4: begin outq = 10'h2ca; end 8'he5: begin outq = 10'h25b; end 8'he6: begin outq = 10'h106; end 8'he7: begin outq = 10'h172; end 8'he8: begin outq = 10'h2f7; end 8'he9: begin outq = 10'h2d3; end 8'hea: begin outq = 10'h182; end 8'heb: begin outq = 10'h327; end 8'hec: begin outq = 10'h1d0; end 8'hed: begin outq = 10'h204; end 8'hee: begin outq = 10'h11f; end 8'hef: begin outq = 10'h365; end 8'hf0: begin outq = 10'h2c2; end 8'hf1: begin outq = 10'h2b5; end 8'hf2: begin outq = 10'h1f8; end 8'hf3: begin outq = 10'h2a7; end 8'hf4: begin outq = 10'h1be; end 8'hf5: begin outq = 10'h25e; end 8'hf6: begin outq = 10'h032; end 8'hf7: begin outq = 10'h2ef; end 8'hf8: begin outq = 10'h02f; end 8'hf9: begin outq = 10'h201; end 8'hfa: begin outq = 10'h054; end 8'hfb: begin outq = 10'h013; end 8'hfc: begin outq = 10'h249; end 8'hfd: begin outq = 10'h09a; end 8'hfe: begin outq = 10'h012; end 8'hff: begin outq = 10'h114; end default: ; // No change endcase end endmodule verilator-4.038/test_regress/t/t_math_countbits.pl0000775000177100017500000000105313702133370022374 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_var_rsvd_port.v0000664000177100017500000000071613702133370022077 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs bool ); input bool; // BAD reg vector; // OK, as not public reg switch /*verilator public*/; // Bad initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_class_package.v0000664000177100017500000000206713702133367021774 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkga; int pvar; class MyClass; int member; function int getpvar(); return pvar; endfunction endclass endpackage package pkgb; int pvar; class MyClass; int member; function int getpvar(); return pvar; endfunction function int getavar(); return pkga::pvar; endfunction endclass endpackage module t (/*AUTOARG*/); initial begin pkga::MyClass a; pkgb::MyClass b; pkga::pvar = 100; pkgb::pvar = 200; if (pkga::pvar != 100) $stop; if (pkgb::pvar != 200) $stop; a = new; b = new; a.member = 10; b.member = 20; if (a.member != 10) $stop; if (b.member != 20) $stop; if (a.getpvar() != 100) $stop; if (b.getpvar() != 200) $stop; if (b.getavar() != 100) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_param_wide_io.v0000664000177100017500000000061113702133370021776 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // issue 1991 module t #( parameter[96:0] P = 97'h12344321_12344321_12344327 ) ( input [P&7 - 1:0] in, output [P&7 - 1:0] out ); assign out = in; endmodule verilator-4.038/test_regress/t/t_number_bad.v0000664000177100017500000000117413702133370021302 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); parameter integer FOO2 = 32'd-6; // Minus doesn't go here parameter integer FOO3 = 32'd; parameter integer FOO4 = 32'h; parameter integer FOO5 = 32'b2; parameter integer FOO6 = 32'o8; // See bug2432, this is questionable, some simulators take this, others do not parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; // bug2432 - intentionally no spaces near ? endmodule verilator-4.038/test_regress/t/t_blocking.v0000664000177100017500000000372013702133367021001 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; initial _mode=0; reg [7:0] a; reg [7:0] b; reg [7:0] c; reg [7:0] mode_d1r; reg [7:0] mode_d2r; reg [7:0] mode_d3r; // surefire lint_off ITENST // surefire lint_off STMINI // surefire lint_off NBAJAM always @ (posedge clk) begin // filp-flops with asynchronous reset if (0) begin _mode <= 0; end else begin _mode <= _mode + 1; if (_mode==0) begin $write("[%0t] t_blocking: Running\n", $time); a <= 8'd0; b <= 8'd0; c <= 8'd0; end else if (_mode==1) begin if (a !== 8'd0) $stop; if (b !== 8'd0) $stop; if (c !== 8'd0) $stop; a <= b; b <= 8'd1; c <= b; if (a !== 8'd0) $stop; if (b !== 8'd0) $stop; if (c !== 8'd0) $stop; end else if (_mode==2) begin if (a !== 8'd0) $stop; if (b !== 8'd1) $stop; if (c !== 8'd0) $stop; a <= b; b <= 8'd2; c <= b; if (a !== 8'd0) $stop; if (b !== 8'd1) $stop; if (c !== 8'd0) $stop; end else if (_mode==3) begin if (a !== 8'd1) $stop; if (b !== 8'd2) $stop; if (c !== 8'd1) $stop; end else if (_mode==4) begin if (mode_d3r != 8'd1) $stop; $write("*-* All Finished *-*\n"); $finish; end end end always @ (posedge clk) begin mode_d3r <= mode_d2r; mode_d2r <= mode_d1r; mode_d1r <= _mode[7:0]; end reg [14:10] bits; // surefire lint_off SEQASS always @ (posedge clk) begin if (_mode==1) begin bits[14:13] <= 2'b11; bits[12] <= 1'b1; end if (_mode==2) begin bits[11:10] <= 2'b10; bits[13] <= 0; end if (_mode==3) begin if (bits !== 5'b10110) $stop; end end endmodule verilator-4.038/test_regress/t/t_assert_synth_full_vlt.pl0000775000177100017500000000146013702133367024016 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_synth.v"); compile( v_flags2 => ['+define+FAILING_FULL', "t/t_assert_synth_full.vlt"], verilator_flags2 => ['--assert'], nc_flags2 => ['+assert'], ); execute( check_finished => 0, fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_vlcov_rank.out0000664000177100017500000000041413657603341021717 0ustar wsnyderwsnyderTests: Covered, Rank, RankPts, Filename 2, 2, 1, "t/t_vlcov_data_a.dat" 3, 1, 3, "t/t_vlcov_data_b.dat" 1, 3, 1, "t/t_vlcov_data_c.dat" 1, 0, 0, "t/t_vlcov_data_d.dat" verilator-4.038/test_regress/t/t_trace_timescale.out0000664000177100017500000000155413702133370022674 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Tue Apr 7 21:19:07 2020 $end $timescale 1ms $end $scope module top $end $var wire 1 + clk $end $scope module t $end $var wire 1 + clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # 0+ #10 b00000000000000000000000000000001 # 1+ #15 0+ #20 b00000000000000000000000000000010 # 1+ #25 0+ #30 b00000000000000000000000000000011 # 1+ #35 0+ #40 b00000000000000000000000000000100 # 1+ #45 0+ #50 b00000000000000000000000000000101 # 1+ #55 0+ #60 b00000000000000000000000000000110 # 1+ #65 0+ #70 b00000000000000000000000000000111 # 1+ #75 0+ #80 b00000000000000000000000000001000 # 1+ #85 0+ #90 b00000000000000000000000000001001 # 1+ #95 0+ #100 b00000000000000000000000000001010 # 1+ #105 0+ #110 1+ b00000000000000000000000000001011 # verilator-4.038/test_regress/t/t_interface_array_bad.pl0000775000177100017500000000107413702133370023320 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_slice_dtype_bad.v0000664000177100017500000000162213702133370023152 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Alex Solomatnikov. // SPDX-License-Identifier: CC0-1.0 typedef logic [$clog2(26+1)-1:0] way_cnt_t; module t(/*AUTOARG*/ // Inputs clk ); input logic clk; int cyc; //bug795 way_cnt_t completed_cnt [31:0][1:0]; way_cnt_t completed_cnt_dp [1:0]; assign completed_cnt_dp = completed_cnt[id]; always_ff @(posedge clk) begin completed_cnt[id] <= completed_cnt_dp + 1; end // bug796 logic [4:0] id; logic [39:0] way_mask; logic [39:0] addr[31:0][1:0]; always_ff @(posedge clk) begin cyc <= cyc + 1; id <= cyc[4:0]; if (cyc==1) begin way_mask <= '0; id <= 1; end else if (cyc==2) begin assert((addr[id] & way_mask) == 0); end end endmodule verilator-4.038/test_regress/t/t_bug3180.pl0000775000177100017500000000110613702133367020447 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ['-Wall -Wno-DECLFILENAME --coverage-line'], ); ok(1); 1; verilator-4.038/test_regress/t/t_clk_scope_bad.v0000664000177100017500000000133313702133367021757 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [2:0] in; output [2:0] out; logic [2:0] r_in; always_ff @ (posedge clk) r_in <= in; flop p0 (.clk(clk), .d(r_in[0]), .q(out[0])); flop p2 (.clk(r_in[1]), .d(clk), .q(out[1])); flop p1 (.clk(clk), .d(r_in[2]), .q(out[2])); endmodule module flop ( input d, input clk, output logic q); // verilator no_inline_module always_ff @ (posedge clk) begin q <= d; end endmodule verilator-4.038/test_regress/t/t_lint_repeat_bad.v0000664000177100017500000000063413702133370022320 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); sub #(.Z(0)) sub1 (); sub #(.Z(1)) sub2 (); sub #(.Z(2)) sub3 (); endmodule module sub; parameter Z = 0; wire [1:0] a = 2'b11; wire [0:0] b = a; endmodule verilator-4.038/test_regress/t/t_clk_gate_ext.v0000664000177100017500000000067513702133367021650 0ustar wsnyderwsnydermodule t(/*AUTOARG*/ // Inputs clk ); input clk; reg clk_en = 1'b0; wire clk_gated = clk & clk_en; wire [1:0] clks = {1'b0, clk_gated}; always @(posedge clks[0]) begin $display("ERROR: clks[0] should not be active!"); $stop; end int cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_alw_nosplit.v0000664000177100017500000001013013702133367021535 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [15:0] m_din; // We expect none of these blocks to split. // Blocks that can split should go in t_alw_split.v instead. reg [15:0] b_split_1, b_split_2; always @ (/*AS*/m_din) begin b_split_1 = m_din; b_split_2 = b_split_1; end reg [15:0] c_split_1, c_split_2; always @ (/*AS*/m_din) begin c_split_1 = m_din; c_split_2 = c_split_1; c_split_1 = ~m_din; end always @ (posedge clk) begin $write(" foo %x", m_din); $write(" bar %x\n", m_din); end reg [15:0] e_split_1, e_split_2; always @ (posedge clk) begin e_split_1 = m_din; e_split_2 = e_split_1; end reg [15:0] f_split_1, f_split_2; always @ (posedge clk) begin f_split_2 = f_split_1; f_split_1 = m_din; end reg [15:0] l_split_1, l_split_2; always @ (posedge clk) begin l_split_2 <= l_split_1; l_split_1 <= l_split_2 | m_din; end reg [15:0] z_split_1, z_split_2; always @ (posedge clk) begin z_split_1 <= 0; z_split_1 <= ~m_din; end always @ (posedge clk) begin z_split_2 <= 0; z_split_2 <= z_split_1; end reg [15:0] h_split_1; reg [15:0] h_split_2; reg [15:0] h_foo; always @ (posedge clk) begin // $write(" cyc = %x m_din = %x\n", cyc, m_din); h_foo = m_din; if (cyc > 2) begin // This conditional depends on non-primary-input foo. // Its dependency on foo should not be pruned. As a result, // the dependencies of h_split_1 and h_split_2 on this // conditional will also not be pruned, making them all // weakly connected such that they'll end up in the same graph // and we can't split. if (h_foo == 16'h0) begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end else begin h_split_1 <= m_din; h_split_2 <= ~m_din; end end else begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end end // always @ (posedge clk) always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; end if (cyc==1) begin m_din <= 16'hfeed; end if (cyc==4) begin m_din <= 16'he11e; if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop; if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop; if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; end if (cyc==5) begin m_din <= 16'he22e; if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop; if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop; // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; end if (cyc==6) begin m_din <= 16'he33e; if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop; if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop; // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; if (!(z_split_1==16'h1ee1 && z_split_2==16'h0112)) $stop; end if (cyc==7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_package_ddecl.v0000664000177100017500000000146413702133370021734 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // see bug 474 package functions; localparam LP_PACK = 512; localparam LP_PACK_AND_MOD = 19; task check_param; $display("In %m\n"); // "In functions::check_param" if (LP_PACK_AND_MOD != 19) $stop; endtask endpackage module t (); // synthesis translate off import functions::*; // synthesis translate on localparam LP_PACK_AND_MOD = 20; initial begin // verilator lint_off STMTDLY #10; // verilator lint_on STMTDLY if (LP_PACK_AND_MOD != 20) $stop; check_param(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_arith.v0000664000177100017500000001160613702133370021325 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; reg [2:0] xor3; reg [1:0] xor2; reg [0:0] xor1; reg [2:0] ma, mb; reg [9:0] mc; reg [4:0] mr1; reg [30:0] mr2; reg [67:0] sh1; reg [67:0] shq; wire foo, bar; assign {foo,bar} = 2'b1_0; // surefire lint_off STMINI initial _ranit = 0; wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1 : (xor2 == 2'b00) ? 5'h2 : (xor2 == 2'b01) ? 5'h3 : 5'h4); wire ctrue = 1'b1 ? cond_check[1] : cond_check[0]; wire cfalse = 1'b0 ? cond_check[1] : cond_check[0]; wire cif = cond_check[2] ? cond_check[1] : cond_check[0]; wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0]; wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1}; wire zero = 1'b0; wire one = 1'b1; wire [5:0] rep6 = {6{one}}; // verilator lint_off WIDTH localparam [3:0] bug764_p11 = 1'bx; // verilator lint_on WIDTH always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; if (rep6 != 6'b111111) $stop; if (!one) $stop; if (~one) $stop; if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop; // verilator lint_off WIDTH if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ? // verilator lint_on WIDTH // surefire lint_off SEQASS xor1 = 1'b1; xor2 = 2'b11; xor3 = 3'b111; // verilator lint_off WIDTH if (1'b1 & | (!xor3)) $stop; // verilator lint_on WIDTH if ({1{xor1}} != 1'b1) $stop; if ({4{xor1}} != 4'b1111) $stop; if (!(~xor1) !== ~(!xor1)) $stop; if ((^xor1) !== 1'b1) $stop; if ((^xor2) !== 1'b0) $stop; if ((^xor3) !== 1'b1) $stop; if (~(^xor2) !== 1'b1) $stop; if (~(^xor3) !== 1'b0) $stop; if ((^~xor1) !== 1'b0) $stop; if ((^~xor2) !== 1'b1) $stop; if ((^~xor3) !== 1'b0) $stop; if ((~^xor1) !== 1'b0) $stop; if ((~^xor2) !== 1'b1) $stop; if ((~^xor3) !== 1'b0) $stop; xor1 = 1'b0; xor2 = 2'b10; xor3 = 3'b101; if ((^xor1) !== 1'b0) $stop; if ((^xor2) !== 1'b1) $stop; if ((^xor3) !== 1'b0) $stop; if (~(^xor2) !== 1'b0) $stop; if (~(^xor3) !== 1'b1) $stop; if ((^~xor1) !== 1'b1) $stop; if ((^~xor2) !== 1'b0) $stop; if ((^~xor3) !== 1'b1) $stop; if ((~^xor1) !== 1'b1) $stop; if ((~^xor2) !== 1'b0) $stop; if ((~^xor3) !== 1'b1) $stop; ma = 3'h3; mb = 3'h4; mc = 10'h5; mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch if (mr1 !== 5'd12) $stop; if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch sh1 = 68'hf_def1_9abc_5678_1234; shq = sh1 >> 16; if (shq !== 68'hf_def1_9abc_5678) $stop; shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch if (shq !== 68'h1_9abc_5678_1234_0000) $stop; // surefire lint_on SEQASS // Test display extraction widthing $display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]); // bug736 //verilator lint_off WIDTH if ((~| 4'b0000) != 4'b0001) $stop; if ((~| 4'b0010) != 4'b0000) $stop; if ((~& 4'b1111) != 4'b0000) $stop; if ((~& 4'b1101) != 4'b0001) $stop; //verilator lint_on WIDTH // bug764 //verilator lint_off WIDTH // X does not sign extend if (bug764_p11 !== 4'b000x) $stop; if (~& bug764_p11 !== 1'b1) $stop; //verilator lint_on WIDTH // However IEEE 2017 5.7.1 says for constants that smaller-sizes do extend if (4'bx !== 4'bxxxx) $stop; if (4'bz !== 4'bzzzz) $stop; if (4'b1 !== 4'b0001) $stop; if ((0 -> 0) != 1'b1) $stop; if ((0 -> 1) != 1'b1) $stop; if ((1 -> 0) != 1'b0) $stop; if ((1 -> 1) != 1'b1) $stop; if ((0 <-> 0) != 1'b1) $stop; if ((0 <-> 1) != 1'b0) $stop; if ((1 <-> 0) != 1'b0) $stop; if ((1 <-> 1) != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end end reg [63:0] m_data_pipe2_r; reg [31:0] m_corr_data_w0, m_corr_data_w1; reg [7:0] m_corr_data_b8; initial begin m_data_pipe2_r = 64'h1234_5678_9abc_def0; {m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0] m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0] m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16] m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8] m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4] m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0] }; if (m_corr_data_w0 != 32'haf36de00) $stop; if (m_corr_data_w1 != 32'h1a2b3c4c) $stop; if (m_corr_data_b8 != 8'h12) $stop; end endmodule verilator-4.038/test_regress/t/t_flag_topmod2_bad.v0000664000177100017500000000100513702133370022360 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module a_top; a a (); initial begin $write("Bad top modules\n"); $stop; end endmodule module a; b b (); c c (); d d (); endmodule module b; endmodule module c; endmodule module d; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_trace_cat_reopen_0100.out0000664000177100017500000000510413702133370023500 0ustar wsnyderwsnyder$version Generated by VerilatedVcd $end $date Thu Aug 30 16:10:58 2018 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #100 b00000000000000000000000000110010 # 1$ #101 0$ #102 b00000000000000000000000000110011 # 1$ #103 0$ #104 b00000000000000000000000000110100 # 1$ #105 0$ #106 b00000000000000000000000000110101 # 1$ #107 0$ #108 b00000000000000000000000000110110 # 1$ #109 0$ #110 b00000000000000000000000000110111 # 1$ #111 0$ #112 b00000000000000000000000000111000 # 1$ #113 0$ #114 b00000000000000000000000000111001 # 1$ #115 0$ #116 b00000000000000000000000000111010 # 1$ #117 0$ #118 b00000000000000000000000000111011 # 1$ #119 0$ #120 b00000000000000000000000000111100 # 1$ #121 0$ #122 b00000000000000000000000000111101 # 1$ #123 0$ #124 b00000000000000000000000000111110 # 1$ #125 0$ #126 b00000000000000000000000000111111 # 1$ #127 0$ #128 b00000000000000000000000001000000 # 1$ #129 0$ #130 b00000000000000000000000001000001 # 1$ #131 0$ #132 b00000000000000000000000001000010 # 1$ #133 0$ #134 b00000000000000000000000001000011 # 1$ #135 0$ #136 b00000000000000000000000001000100 # 1$ #137 0$ #138 b00000000000000000000000001000101 # 1$ #139 0$ #140 b00000000000000000000000001000110 # 1$ #141 0$ #142 b00000000000000000000000001000111 # 1$ #143 0$ #144 b00000000000000000000000001001000 # 1$ #145 0$ #146 b00000000000000000000000001001001 # 1$ #147 0$ #148 b00000000000000000000000001001010 # 1$ #149 0$ #150 b00000000000000000000000001001011 # 1$ #151 0$ #152 b00000000000000000000000001001100 # 1$ #153 0$ #154 b00000000000000000000000001001101 # 1$ #155 0$ #156 b00000000000000000000000001001110 # 1$ #157 0$ #158 b00000000000000000000000001001111 # 1$ #159 0$ #160 b00000000000000000000000001010000 # 1$ #161 0$ #162 b00000000000000000000000001010001 # 1$ #163 0$ #164 b00000000000000000000000001010010 # 1$ #165 0$ #166 b00000000000000000000000001010011 # 1$ #167 0$ #168 b00000000000000000000000001010100 # 1$ #169 0$ #170 b00000000000000000000000001010101 # 1$ #171 0$ #172 b00000000000000000000000001010110 # 1$ #173 0$ #174 b00000000000000000000000001010111 # 1$ #175 0$ #176 b00000000000000000000000001011000 # 1$ #177 0$ #178 b00000000000000000000000001011001 # 1$ #179 0$ #180 b00000000000000000000000001011010 # 1$ #181 0$ #182 b00000000000000000000000001011011 # 1$ #183 0$ #184 b00000000000000000000000001011100 # 1$ #185 0$ #186 b00000000000000000000000001011101 # 1$ #187 0$ #188 b00000000000000000000000001011110 # 1$ #189 0$ verilator-4.038/test_regress/t/t_dpi_open.pl0000775000177100017500000000123013702133370021143 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( v_flags2 => ["t/t_dpi_open_c.cpp"], verilator_flags2 => ["-Wall -Wno-DECLFILENAME -unroll-count 1"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_assoc_meth_bad.pl0000775000177100017500000000107113702133367022312 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2019 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_bad_hide.pl0000775000177100017500000000116613702133370022121 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_readmem.v0000664000177100017500000001422413702133370021514 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef WRITEMEM_BIN `define READMEMX $readmemb `define WRITEMEMX $writememb `else `define READMEMX $readmemh `define WRITEMEMX $writememh `endif module t; // verilator lint_off LITENDIAN reg [5:0] binary_string [2:15]; reg [5:0] binary_nostart [2:15]; reg [5:0] binary_start [0:15]; reg [175:0] hex [0:15]; reg [(32*6)-1:0] hex_align [0:15]; string fns; `ifdef WRITEMEM_READ_BACK reg [5:0] binary_string_tmp [2:15]; reg [5:0] binary_nostart_tmp [2:15]; reg [5:0] binary_start_tmp [0:15]; reg [175:0] hex_tmp [0:15]; reg [(32*6)-1:0] hex_align_tmp [0:15]; string fns_tmp; `endif // verilator lint_on LITENDIAN integer i; initial begin begin // Initialize memories to zero, // avoid differences between 2-state and 4-state. for (i=0; i<16; i=i+1) begin binary_start[i] = 6'h0; hex[i] = 176'h0; hex_align[i] = {32*6{1'b0}}; `ifdef WRITEMEM_READ_BACK binary_start_tmp[i] = 6'h0; hex_tmp[i] = 176'h0; hex_align_tmp[i] = {32*6{1'b0}}; `endif end for (i=2; i<16; i=i+1) begin binary_string[i] = 6'h0; binary_nostart[i] = 6'h0; `ifdef WRITEMEM_READ_BACK binary_string_tmp[i] = 6'h0; binary_nostart_tmp[i] = 6'h0; `endif end end begin `ifdef WRITEMEM_READ_BACK $readmemb("t/t_sys_readmem_b.mem", binary_nostart_tmp); // Do a round-trip $writememh(b) and $readmemh(b) cycle. // This covers $writememh and ensures we can read our // own memh output file. // If WRITEMEM_BIN is also defined, use $writememb and // $readmemb, otherwise use $writememh and $readmemh. `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP1); `endif `WRITEMEMX(`OUT_TMP1, binary_nostart_tmp); `READMEMX(`OUT_TMP1, binary_nostart); `else $readmemb("t/t_sys_readmem_b.mem", binary_nostart); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]); `endif if (binary_nostart['h2] != 6'h02) $stop; if (binary_nostart['h3] != 6'h03) $stop; if (binary_nostart['h4] != 6'h04) $stop; if (binary_nostart['h5] != 6'h05) $stop; if (binary_nostart['h6] != 6'h06) $stop; if (binary_nostart['h7] != 6'h07) $stop; if (binary_nostart['h8] != 6'h10) $stop; if (binary_nostart['hc] != 6'h14) $stop; if (binary_nostart['hd] != 6'h15) $stop; end begin binary_start['h0c] = 6'h3f; // Not in read range // `ifdef WRITEMEM_READ_BACK $readmemb("t/t_sys_readmem_b_8.mem", binary_start_tmp, 4, 4+7); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP2); `endif `WRITEMEMX(`OUT_TMP2, binary_start_tmp, 4, 4+7); `READMEMX(`OUT_TMP2, binary_start, 4, 4+7); `else $readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7); // 4-11 `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]); `endif if (binary_start['h04] != 6'h10) $stop; if (binary_start['h05] != 6'h11) $stop; if (binary_start['h06] != 6'h12) $stop; if (binary_start['h07] != 6'h13) $stop; if (binary_start['h08] != 6'h14) $stop; if (binary_start['h09] != 6'h15) $stop; if (binary_start['h0a] != 6'h16) $stop; if (binary_start['h0b] != 6'h17) $stop; // if (binary_start['h0c] != 6'h3f) $stop; end begin // The 'hex' array is a non-exact multiple of word size // (possible corner case) `ifdef WRITEMEM_READ_BACK $readmemh("t/t_sys_readmem_h.mem", hex_tmp, 0); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP3); `endif `WRITEMEMX(`OUT_TMP3, hex_tmp, 0); `READMEMX(`OUT_TMP3, hex, 0); `else $readmemh("t/t_sys_readmem_h.mem", hex, 0); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]); `endif if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop; if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop; if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop; if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop; end begin // The 'hex align' array is similar to 'hex', but it is an // exact multiple of word size -- another possible corner case. `ifdef WRITEMEM_READ_BACK $readmemh("t/t_sys_readmem_align_h.mem", hex_align_tmp, 0); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP4); `endif `WRITEMEMX(`OUT_TMP4, hex_align_tmp, 0); `READMEMX(`OUT_TMP4, hex_align, 0); `else $readmemh("t/t_sys_readmem_align_h.mem", hex_align, 0); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex_align[i]); `endif if (hex_align['h04] != 192'h77554004_37654321_27654321_17654321_07654321_abcdef10) $stop; if (hex_align['h0a] != 192'h7755400a_37654321_27654321_17654321_07654321_abcdef11) $stop; if (hex_align['h0b] != 192'h7755400b_37654321_27654321_17654321_07654321_abcdef12) $stop; if (hex_align['h0c] != 192'h7755400c_37654321_27654321_17654321_07654321_abcdef13) $stop; end begin fns = "t/t_sys_readmem_b.mem"; `ifdef WRITEMEM_READ_BACK fns_tmp = `OUT_TMP5; $readmemb(fns, binary_string_tmp); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP5); `endif `WRITEMEMX(fns_tmp, binary_string_tmp); `READMEMX(fns_tmp, binary_string); `else $readmemb(fns, binary_string); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_string[i]); `endif if (binary_string['h2] != 6'h02) $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_package_dimport.pl0000775000177100017500000000102113702133370022475 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); # Compile only ok(1); 1; verilator-4.038/test_regress/t/t_split_var_0.pl0000775000177100017500000000215613702133370021600 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Travis environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performace wise, but ok. compile( verilator_flags2 => ['--stats' . ($Self->{vltmt} ? ' --threads 6' : ''), "$Self->{t_dir}/t_split_var_0.vlt"], ); execute( check_finished => 1, ); file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 13); file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 23); ok(1); 1; verilator-4.038/test_regress/t/t_interface_gen.pl0000775000177100017500000000106013702133370022140 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_interface_down.v0000664000177100017500000000267713702133370022204 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; endinterface module t (/*AUTOARG*/ // Inputs clk ); `ifdef INLINE_A //verilator inline_module `else //verilator no_inline_module `endif input clk; integer cyc=1; ifc itop1a(); ifc itop1b(); ifc itop2a(); ifc itop2b(); wrapper c1 (.isuba(itop1a), .isubb(itop1b), .i_valuea(14), .i_valueb(15)); wrapper c2 (.isuba(itop2a), .isubb(itop2b), .i_valuea(24), .i_valueb(25)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (itop1a.value != 14) $stop; if (itop1b.value != 15) $stop; if (itop2a.value != 24) $stop; if (itop2b.value != 25) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module wrapper ( ifc isuba, ifc isubb, input integer i_valuea, input integer i_valueb ); `ifdef INLINE_B //verilator inline_module `else //verilator no_inline_module `endif lower subsuba (.isub(isuba), .i_value(i_valuea)); lower subsubb (.isub(isubb), .i_value(i_valueb)); endmodule module lower ( ifc isub, input integer i_value ); `ifdef INLINE_C //verilator inline_module `else //verilator no_inline_module `endif always @* begin isub.value = i_value; end endmodule verilator-4.038/test_regress/t/t_flag_nomod_bad.v0000664000177100017500000000034613702133370022117 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define EMPTY 1 verilator-4.038/test_regress/t/t_class_vparam_unsup.pl0000775000177100017500000000111613702133367023264 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_assert_property_fail_1.pl0000775000177100017500000000137713702133367024050 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_assert_property.v"); compile( v_flags2 => ['+define+FAIL_ASSERT_1'], verilator_flags2 => ['--assert --cc'], ); execute( ); # We expect to get a message when this assert fires: file_grep($Self->{run_log_filename}, qr/cyc != 3/); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_open_query.v0000664000177100017500000002346613702133370022236 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) `define unless(cond,gotv,expv) do if (!(cond)) `check(gotv, expv); while(0) `ifdef VERILATOR `define NO_DYNAMIC `define NO_QUEUE `endif `ifdef VCS `define NO_QUEUE `endif `ifdef NC `define NO_DYNAMIC `define NO_QUEUE `endif `ifdef NC `define ONNC 1 `else `define ONNC 0 `endif `ifdef MS `define ONMS 1 `else `define ONMS 0 `endif module t; // 1 open dimension import "DPI-C" function int cSvLeft1( input bit h [], int d); import "DPI-C" function int cSvRight1( input bit h [], int d); import "DPI-C" function int cSvLow1( input bit h [], int d); import "DPI-C" function int cSvHigh1( input bit h [], int d); import "DPI-C" function int cSvIncrement1( input bit h [], int d); import "DPI-C" function int cSvSize1( input bit h [], int d); import "DPI-C" function int cSvDimensions1( input bit h []); // 2 open dimensions import "DPI-C" function int cSvLeft2( input bit h [][], int d); import "DPI-C" function int cSvRight2( input bit h [][], int d); import "DPI-C" function int cSvLow2( input bit h [][], int d); import "DPI-C" function int cSvHigh2( input bit h [][], int d); import "DPI-C" function int cSvIncrement2( input bit h [][], int d); import "DPI-C" function int cSvSize2( input bit h [][], int d); import "DPI-C" function int cSvDimensions2( input bit h [][]); // 3 open dimensions import "DPI-C" function int cSvLeft3( input bit h [][][], int d); import "DPI-C" function int cSvRight3( input bit h [][][], int d); import "DPI-C" function int cSvLow3( input bit h [][][], int d); import "DPI-C" function int cSvHigh3( input bit h [][][], int d); import "DPI-C" function int cSvIncrement3( input bit h [][][], int d); import "DPI-C" function int cSvSize3( input bit h [][][], int d); import "DPI-C" function int cSvDimensions3( input bit h [][][]); // 4 open dimensions import "DPI-C" function int cSvLeft4( input bit h [][][][], int d); import "DPI-C" function int cSvRight4( input bit h [][][][], int d); import "DPI-C" function int cSvLow4( input bit h [][][][], int d); import "DPI-C" function int cSvHigh4( input bit h [][][][], int d); import "DPI-C" function int cSvIncrement4( input bit h [][][][], int d); import "DPI-C" function int cSvSize4( input bit h [][][][], int d); import "DPI-C" function int cSvDimensions4( input bit h [][][][]); // verilator lint_off UNDRIVEN bit a1 [1:0]; bit a2 [1:0][2:0]; bit a3 [1:0][2:0][3:0]; bit a4 [1:0][2:0][3:0][4:0]; bit b1 [0:1]; bit b2 [0:1][0:2]; bit b3 [0:1][0:2][0:3]; bit b4 [0:1][0:2][0:3][0:4]; bit c1 [-1:1]; bit c2 [-1:1][-2:2]; bit c3 [-1:1][-2:2][-3:3]; bit c4 [-1:1][-2:2][-3:3][-4:4]; `ifndef NO_DYNAMIC bit d1 []; bit d2 [][-2:2]; bit d3 [][-2:2][-3:3]; bit d4 [][-2:2][-3:3][-4:4]; `endif `ifndef NO_QUEUE bit e1 [$]; `endif // verilator lint_on UNDRIVEN initial begin `ifndef NO_DYNAMIC d1 = new[3]; d2 = new[3]; d3 = new[3]; d4 = new[3]; `endif `ifndef NO_QUEUE e1.push_back(0); e1.push_back(0); e1.push_back(0); `endif // 1 open dimension `check(cSvDimensions1(a1), 1); `check(cSvDimensions1(b1), 1); `check(cSvDimensions1(c1), 1); `ifndef NO_DYNAMIC `check(cSvDimensions1(d1), 1); `endif `ifndef NO_QUEUE `check(cSvDimensions1(e1), 1); `endif for (int d = 0 ; d < 2 ; d++) begin if (`ONNC && d == 0) continue; `check(cSvLeft1(a1, d), d); `check(cSvRight1(a1, d), 0); `check(cSvLow1(a1, d), 0); `check(cSvHigh1(a1, d), d); `unless(`ONMS && d == 0, cSvIncrement1(a1, d), 1); `check(cSvSize1(a1, d), d+1); `check(cSvLeft1(b1, d), 0); `check(cSvRight1(b1, d), d); `check(cSvLow1(b1, d), 0); `check(cSvHigh1(b1, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement1(b1, d), d == 0 ? 1 : -1); `endif `check(cSvSize1(b1, d), d+1); `check(cSvLeft1(c1, d), -d); `check(cSvRight1(c1, d), d); `check(cSvLow1(c1, d), -d); `check(cSvHigh1(c1, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement1(c1, d), d == 0 ? 1 : -1); `endif `check(cSvSize1(c1, d), 2*d+1); `ifndef NO_DYNAMIC `check(cSvLeft1(d1, d), d == 1 ? 0 : -d); `check(cSvRight1(d1, d), d == 1 ? 2 : d); `check(cSvLow1(d1, d), d == 1 ? 0 : -d); `check(cSvHigh1(d1, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement1(d1, d), d == 0 ? 1 : -1); `check(cSvSize1(d1, d), 2*d+1); `endif `ifndef NO_QUEUE `check(cSvLeft1(e1, d), d == 1 ? 0 : -d); `check(cSvRight1(e1, d), d == 1 ? 2 : d); `check(cSvLow1(e1, d), d == 1 ? 0 : -d); `check(cSvHigh1(e1, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement1(e1, d), d == 0 ? 1 : -1); `check(cSvSize1(e1, d), 2*d+1); `endif end // 2 open dimensions `check(cSvDimensions2(a2), 2); `check(cSvDimensions2(b2), 2); `check(cSvDimensions2(c2), 2); `ifndef NO_DYNAMIC `check(cSvDimensions2(d2), 2); `endif for (int d = 0 ; d < 3 ; d++) begin if (`ONNC && d == 0) continue; `check(cSvLeft2(a2, d), d); `check(cSvRight2(a2, d), 0); `check(cSvLow2(a2, d), 0); `check(cSvHigh2(a2, d), d); `unless(`ONMS && d == 0, cSvIncrement2(a2, d), 1); `check(cSvSize2(a2, d), d+1); `check(cSvLeft2(b2, d), 0); `check(cSvRight2(b2, d), d); `check(cSvLow2(b2, d), 0); `check(cSvHigh2(b2, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement2(b2, d), d == 0 ? 1 : -1); `endif `check(cSvSize2(b2, d), d+1); `check(cSvLeft2(c2, d), -d); `check(cSvRight2(c2, d), d); `check(cSvLow2(c2, d), -d); `check(cSvHigh2(c2, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement2(c2, d), d == 0 ? 1 : -1); `endif `check(cSvSize2(c2, d), 2*d+1); `ifndef NO_DYNAMIC `check(cSvLeft2(d2, d), d == 1 ? 0 : -d); `check(cSvRight2(d2, d), d == 1 ? 2 : d); `check(cSvLow2(d2, d), d == 1 ? 0 : -d); `check(cSvHigh2(d2, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement2(d2, d), d == 0 ? 1 : -1); `check(cSvSize2(d2, d), 2*d+1); `endif end // 3 open dimensions `check(cSvDimensions3(a3), 3); `check(cSvDimensions3(b3), 3); `check(cSvDimensions3(c3), 3); `ifndef NO_DYNAMIC `check(cSvDimensions3(d3), 3); `endif for (int d = 0 ; d < 4 ; d++) begin if (`ONNC && d == 0) continue; `check(cSvLeft3(a3, d), d); `check(cSvRight3(a3, d), 0); `check(cSvLow3(a3, d), 0); `check(cSvHigh3(a3, d), d); `unless(`ONMS && d == 0, cSvIncrement3(a3, d), 1); `check(cSvSize3(a3, d), d+1); `check(cSvLeft3(b3, d), 0); `check(cSvRight3(b3, d), d); `check(cSvLow3(b3, d), 0); `check(cSvHigh3(b3, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement3(b3, d), d == 0 ? 1 : -1); `endif `check(cSvSize3(b3, d), d+1); `check(cSvLeft3(c3, d), -d); `check(cSvRight3(c3, d), d); `check(cSvLow3(c3, d), -d); `check(cSvHigh3(c3, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement3(c3, d), d == 0 ? 1 : -1); `endif `check(cSvSize3(c3, d), 2*d+1); `ifndef NO_DYNAMIC `check(cSvLeft3(d3, d), d == 1 ? 0 : -d); `check(cSvRight3(d3, d), d == 1 ? 2 : d); `check(cSvLow3(d3, d), d == 1 ? 0 : -d); `check(cSvHigh3(d3, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement3(d3, d), d == 0 ? 1 : -1); `check(cSvSize3(d3, d), 2*d+1); `endif end // 4 open dimension `check(cSvDimensions4(a4), 4); `check(cSvDimensions4(b4), 4); `check(cSvDimensions4(c4), 4); `ifndef NO_DYNAMIC `check(cSvDimensions4(d4), 4); `endif for (int d = 0 ; d < 5 ; d++) begin if (`ONNC && d == 0) continue; `check(cSvLeft4(a4, d), d); `check(cSvRight4(a4, d), 0); `check(cSvLow4(a4, d), 0); `check(cSvHigh4(a4, d), d); `unless(`ONMS && d == 0, cSvIncrement4(a4, d), 1); `check(cSvSize4(a4, d), d+1); `check(cSvLeft4(b4, d), 0); `check(cSvRight4(b4, d), d); `check(cSvLow4(b4, d), 0); `check(cSvHigh4(b4, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement4(b4, d), d == 0 ? 1 : -1); `endif `check(cSvSize4(b4, d), d+1); `check(cSvLeft4(c4, d), -d); `check(cSvRight4(c4, d), d); `check(cSvLow4(c4, d), -d); `check(cSvHigh4(c4, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement4(c4, d), d == 0 ? 1 : -1); `endif `check(cSvSize4(c4, d), 2*d+1); `ifndef NO_DYNAMIC `check(cSvLeft4(d4, d), d == 1 ? 0 : -d); `check(cSvRight4(d4, d), d == 1 ? 2 : d); `check(cSvLow4(d4, d), d == 1 ? 0 : -d); `check(cSvHigh4(d4, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement4(d4, d), d == 0 ? 1 : -1); `check(cSvSize4(d4, d), 2*d+1); `endif end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_math_cond_huge.pl0000775000177100017500000000105313702133370022315 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_dpi_result_type.out0000664000177100017500000000252513702133370022762 0ustar wsnyderwsnyderi_void 0 i_chandle 0 i_string 0 i_bit 0 i_logic 0 i_chandle_t 0 i_string_t 0 i_bit_t 0 i_logic_t 0 i_array_2_state_1 0 i_array_2_state_32 0 i_struct_2_state_1 0 i_struct_2_state_32 0 i_union_2_state_1 0 i_union_2_state_32 0 e_void 0 e_chandle 0 e_string 0 e_bit 0 e_logic 0 e_chandle_t 0 e_string_t 0 e_bit_t 0 e_logic_t 0 e_array_2_state_1 0 e_array_2_state_32 0 e_struct_2_state_1 0 e_struct_2_state_32 0 e_union_2_state_1 0 e_union_2_state_32 0 i_void 1 i_chandle 1 i_string 1 i_bit 1 i_logic 1 i_chandle_t 1 i_string_t 1 i_bit_t 1 i_logic_t 1 i_array_2_state_1 1 i_array_2_state_32 1 i_struct_2_state_1 1 i_struct_2_state_32 1 i_union_2_state_1 1 i_union_2_state_32 1 e_void 1 e_chandle 1 e_string 1 e_bit 1 e_logic 1 e_chandle_t 1 e_string_t 1 e_bit_t 1 e_logic_t 1 e_array_2_state_1 1 e_array_2_state_32 1 e_struct_2_state_1 1 e_struct_2_state_32 1 e_union_2_state_1 1 e_union_2_state_32 1 i_void 2 i_chandle 2 i_string 2 i_bit 2 i_logic 2 i_chandle_t 2 i_string_t 2 i_bit_t 2 i_logic_t 2 i_array_2_state_1 2 i_array_2_state_32 2 i_struct_2_state_1 2 i_struct_2_state_32 2 i_union_2_state_1 2 i_union_2_state_32 2 e_void 2 e_chandle 2 e_string 2 e_bit 2 e_logic 2 e_chandle_t 2 e_string_t 2 e_bit_t 2 e_logic_t 2 e_array_2_state_1 2 e_array_2_state_32 2 e_struct_2_state_1 2 e_struct_2_state_32 2 e_union_2_state_1 2 e_union_2_state_32 2 *-* All Finished *-* verilator-4.038/test_regress/t/t_sys_file_scan.v0000664000177100017500000000203613702133370022023 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "verilated.v" `define STRINGIFY(x) `"x`" module t; integer infile, outfile; integer count, a; initial begin infile = $fopen("t/t_sys_file_scan_input.dat", "r"); outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_scan_test.log"}, "w"); count = 1234; `ifdef TEST_VERBOSE $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); `endif count = $fscanf(infile, "%d\n", a); `ifdef TEST_VERBOSE // Ifdefing this out gave bug248 $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); `endif if (count == 0) $stop; $fwrite(outfile, "# a\n"); $fwrite(outfile, "%d\n", a); $fclose(infile); $fclose(outfile); $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end endmodule verilator-4.038/test_regress/t/t_lint_bsspace_bad.out0000664000177100017500000000064413702133370023023 0ustar wsnyderwsnyder%Warning-BSSPACE: t/t_lint_bsspace_bad.v:10:21: Backslash followed by whitespace, perhaps the whitespace is accidental? 10 | `define FOO blak \ | ^ ... Use "/* verilator lint_off BSSPACE */" and lint_on around source to disable this message. %Error: t/t_lint_bsspace_bad.v:11:4: syntax error, unexpected IDENTIFIER 11 | blak | ^~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_altera_lpm_add_sub.pl0000775000177100017500000000120613702133367023160 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); top_filename("t/t_altera_lpm.v"); (my $module = $Self->{name}) =~ s/.*t_altera_//; compile( verilator_flags2 => ["--top-module ${module}"] ); ok(1); 1; verilator-4.038/test_regress/t/t_mod_recurse1.pl0000775000177100017500000000105313702133370021741 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_class_static_order.pl0000775000177100017500000000117613702133367023234 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); #execute( # check_finished => 1, # ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_dtree_inlb.pl0000775000177100017500000000123013702133370022512 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_inst_dtree.v"); compile( v_flags2 => ['+define+INLINE_B'], verilator_flags2 => ['-trace'], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_math_pow3.pl0000775000177100017500000000105313702133370021252 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_enum_func.pl0000775000177100017500000000105313702133370021330 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_inst_misarray2_bad.pl0000775000177100017500000000107513702133370023131 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint( fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_lint_declfilename_bad.pl0000775000177100017500000000122213702133370023613 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_lint_declfilename.v"); lint( verilator_flags2 => ["--lint-only -Wall"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_pipe_exit_bad.pl0000775000177100017500000000136513702133370022153 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2010-2011 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); top_filename("t/t_pipe_filter.v"); lint( verilator_flags2 => ['-E --pipe-filter \'perl t/t_pipe_exit_bad.pf\' '], stdout_filename => $stdout_filename, fails => 1, expect => '%Error: t_pipe_exit_bad.pf: Intentional bad exit status....*', ); ok(1); 1; verilator-4.038/test_regress/t/t_func_tie_bad.v0000664000177100017500000000070013702133370021600 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); initial begin // verilator lint_off IGNOREDRETURN func(0, 1'b1); end function automatic int func ( input int a, output bit b ); return 0; endfunction endmodule verilator-4.038/test_regress/t/t_assign_inline.pl0000775000177100017500000000112013702133367022174 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( verilator_flags2 => ["-O0 -OG"], ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_flag_ldflags_c.cpp0000664000177100017500000000176413702133370022435 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include "svdpi.h" //====================================================================== #if defined(VERILATOR) # include "Vt_flag_ldflags__Dpi.h" #else # error "Unknown simulator for DPI test" #endif //====================================================================== #ifndef CFLAGS_FROM_CMDLINE # error "CFLAGS_FROM_CMDLINE not set - not passed down?" #endif #ifndef CFLAGS2_FROM_CMDLINE # error "CFLAGS2_FROM_CMDLINE not set - not passed down?" #endif void dpii_c_library() {} verilator-4.038/test_regress/t/t_gen_inc.v0000664000177100017500000001261713702133370020612 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; genvar g; integer i; reg [31:0] v; reg [31:0] gen_pre_PLUSPLUS = 32'h0; reg [31:0] gen_pre_MINUSMINUS = 32'h0; reg [31:0] gen_post_PLUSPLUS = 32'h0; reg [31:0] gen_post_MINUSMINUS = 32'h0; reg [31:0] gen_PLUSEQ = 32'h0; reg [31:0] gen_MINUSEQ = 32'h0; reg [31:0] gen_TIMESEQ = 32'h0; reg [31:0] gen_DIVEQ = 32'h0; reg [31:0] gen_MODEQ = 32'h0; reg [31:0] gen_ANDEQ = 32'h0; reg [31:0] gen_OREQ = 32'h0; reg [31:0] gen_XOREQ = 32'h0; reg [31:0] gen_SLEFTEQ = 32'h0; reg [31:0] gen_SRIGHTEQ = 32'h0; reg [31:0] gen_SSRIGHTEQ = 32'h0; generate for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1; for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1; for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1; for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1; for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1; for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1; for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1; for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1; for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1; for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1; for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1; for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1; for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1; for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1; for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1; endgenerate always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 3) begin `ifdef TEST_VERBOSE $write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS); $write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS); $write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS); $write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS); $write("gen_PLUSEQ %b\n", gen_PLUSEQ); $write("gen_MINUSEQ %b\n", gen_MINUSEQ); $write("gen_TIMESEQ %b\n", gen_TIMESEQ); $write("gen_DIVEQ %b\n", gen_DIVEQ); $write("gen_MODEQ %b\n", gen_MODEQ); $write("gen_ANDEQ %b\n", gen_ANDEQ); $write("gen_OREQ %b\n", gen_OREQ); $write("gen_XOREQ %b\n", gen_XOREQ); $write("gen_SLEFTEQ %b\n", gen_SLEFTEQ); $write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ); $write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ); `endif if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop; if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop; if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop; if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop; if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop; if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop; if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop; if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop; if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop; if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop; if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop; if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop; v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop; v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop; v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-4.038/test_regress/t/t_lint_import_name2_bad.out0000664000177100017500000000072513702133370023777 0ustar wsnyderwsnyder%Error: t/t_lint_import_name2_bad.v:7:8: Package/class 'missing' not found, and needs to be predeclared (IEEE 1800-2017 26.3) 7 | import missing::sigs; | ^~~~~~~ %Error: t/t_lint_import_name2_bad.v:7:8: Importing from missing package 'missing' 7 | import missing::sigs; | ^~~~~~~ %Error: t/t_lint_import_name2_bad.v:9:8: Importing from missing package 'missing' 9 | import missing::*; | ^~~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_enum_recurse_bad.v0000664000177100017500000000034613702133370022506 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 enum {u=u} e_t; verilator-4.038/test_regress/t/t_dpi_result_type.cpp0000664000177100017500000001757213702133370022745 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_result_type__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_REAL_EXPORT #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_STRUCT_OR_UNION # define NO_SHORTREAL #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; # define NO_STRUCT_OR_UNION # define NO_ARRAY #else # error "Unknown simulator for DPI test" #endif //====================================================================== // Implementations of imported functions //====================================================================== // Basic types as per IEEE 1800-2017 35.5.5 void i_void() { static int n = 0; printf("i_void %d\n", n); n++; } char i_byte() { static int n = 0; return 10 - n++; } unsigned char i_byte_unsigned() { static int n = 0; return 20 - n++; } short i_shortint() { static int n = 0; return 30 - n++; } unsigned short i_shortint_unsigned() { static int n = 0; return 40 - n++; } int i_int() { static int n = 0; return 50 - n++; } unsigned i_int_unsigned() { static int n = 0; return 60 - n++; } sv_longint_t i_longint() { static int n = 0; return 70 - n++; } sv_longint_unsigned_t i_longint_unsigned() { static int n = 0; return 80 - n++; } double i_real() { static int n = 0; return (-2.0 * n++ - 1.0) / 2.0; } #ifndef NO_SHORTREAL float i_shortreal() { static int n = 0; return (-4.0f * n++ - 1.0f) / 4.0f; } #endif void* i_chandle() { static int n = 0; printf("i_chandle %d\n", n); return (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } const char* i_string() { static int n = 0; printf("i_string %d\n", n); return (n++ % 2) ? "Hello" : "World"; } svBit i_bit() { static int n = 0; printf("i_bit %d\n", n); return !(n++ % 2); } svLogic i_logic() { static int n = 0; printf("i_logic %d\n", n); return n++ % 2; } // Basic types via typedefs char i_byte_t() { static int n = 0; const char r = 10 - n; n += 2; return r; } unsigned char i_byte_unsigned_t() { static int n = 0; const unsigned char r = 20 - n; n += 2; return r; } short i_shortint_t() { static int n = 0; const short r = 30 - n; n += 2; return r; } unsigned short i_shortint_unsigned_t() { static int n = 0; const unsigned short r = 40 - n; n += 2; return r; } int i_int_t() { static int n = 0; const int r = 50 - n; n += 2; return r; } unsigned i_int_unsigned_t() { static int n = 0; const unsigned r = 60 - n; n += 2; return r; } sv_longint_t i_longint_t() { static int n = 0; const sv_longint_t r = 70 - n; n += 2; return r; } sv_longint_unsigned_t i_longint_unsigned_t() { static int n = 0; const sv_longint_unsigned_t r = 80 - n; n += 2; return r; } double i_real_t() { static int n = 0; const double r = (-2.0 * n - 1.0) / 2.0; n += 2; return r; } #ifndef NO_SHORTREAL float i_shortreal_t() { static int n = 0; const float r = (-4.0f * n - 1.0f) / 4.0f; n += 2; return r; } #endif void* i_chandle_t() { static int n = 0; printf("i_chandle_t %d\n", n); return (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } const char* i_string_t() { static int n = 0; printf("i_string_t %d\n", n); return (n++ % 2) ? "Hello" : "World"; } svBit i_bit_t() { static int n = 0; printf("i_bit_t %d\n", n); return !(n++ % 2); } svLogic i_logic_t() { static int n = 0; printf("i_logic_t %d\n", n); return n++ % 2; } #ifndef NO_ARRAY // 2-state packed arrays of width <= 32 svBitVecVal i_array_2_state_1() { static int n = 0; printf("i_array_2_state_1 %d\n", n); return !(n++ % 2); } svBitVecVal i_array_2_state_32() { static int n = 0; printf("i_array_2_state_32 %d\n", n); return 0xffffffffU << n++; } #endif #ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 svBitVecVal i_struct_2_state_1() { static int n = 0; printf("i_struct_2_state_1 %d\n", n); return !(n++ % 2); } svBitVecVal i_struct_2_state_32() { static int n = 0; printf("i_struct_2_state_32 %d\n", n); return 0xffffffffU << n++; } // 2-state packed unions of width <= 32 svBitVecVal i_union_2_state_1() { static int n = 0; printf("i_union_2_state_1 %d\n", n); return !(n++ % 2); } svBitVecVal i_union_2_state_32() { static int n = 0; printf("i_union_2_state_32 %d\n", n); return 0xffffffffU << n++; } #endif //====================================================================== // Check exported functions //====================================================================== #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void check_exports() { static int n = 0; e_void(); // Basic types as per IEEE 1800-2017 35.5.5 if (e_byte() != 10 + n) stop(); if (e_byte_unsigned() != 20 + n) stop(); if (e_shortint() != 30 + n) stop(); if (e_shortint_unsigned() != 40 + n) stop(); if (e_int() != 50 + n) stop(); if (e_int_unsigned() != 60 + n) stop(); if (e_longint() != 70 + n) stop(); if (e_longint_unsigned() != 80 + n) stop(); #ifndef NO_REAL_EXPORT if (e_real() != 1.0 * n + 0.5) stop(); #endif #ifndef NO_SHORTREAL if (e_shortreal() != 1.0f * n + 0.25f) stop(); #endif if (e_chandle() != NULL) stop(); if ((n % 2) == 0) { if (strcmp(e_string(), "Hello") != 0) stop(); } else { if (strcmp(e_string(), "World") != 0) stop(); } if (e_bit() != (n % 2)) stop(); if (e_logic() != !(n % 2)) stop(); // Basic types via tyepdef if (e_byte_t() != 10 + 2 * n) stop(); if (e_byte_unsigned_t() != 20 + 2 * n) stop(); if (e_shortint_t() != 30 + 2 * n) stop(); if (e_shortint_unsigned_t() != 40 + 2 * n) stop(); if (e_int_t() != 50 + 2 * n) stop(); if (e_int_unsigned_t() != 60 + 2 * n) stop(); if (e_longint_t() != 70 + 2 * n) stop(); if (e_longint_unsigned_t() != 80 + 2 * n) stop(); #ifndef NO_REAL_EXPORT if (e_real_t() != 1.0 * (2 * n) + 0.5) stop(); #endif #ifndef NO_SHORTREAL if (e_shortreal_t() != 1.0f * (2 * n) + 0.25f) stop(); #endif if (e_chandle_t() != NULL) stop(); if ((n % 2) == 0) { if (strcmp(e_string_t(), "Hello") != 0) stop(); } else { if (strcmp(e_string_t(), "World") != 0) stop(); } if (e_bit_t() != (n % 2)) stop(); if (e_logic_t() != !(n % 2)) stop(); #ifndef NO_ARRAY // 2-state packed arrays of width <= 32 if (e_array_2_state_1() != (n % 2)) stop(); if (e_array_2_state_32() != 0xffffffff >> n) stop(); #endif #ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 if (e_struct_2_state_1() != (n % 2)) stop(); if (e_struct_2_state_32() != 0xffffffff >> n) stop(); // 2-state packed unions of width <= 32 if (e_union_2_state_1() != (n % 2)) stop(); if (e_union_2_state_32() != 0xffffffff >> n) stop(); #endif n++; } verilator-4.038/test_regress/t/t_lint_width.v0000664000177100017500000000125513702133370021351 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); // This isn't a width violation, as +/- 1'b1 is a common idiom // that's fairly harmless wire [4:0] five = 5'd5; wire [4:0] suma = five + 1'b1; wire [4:0] sumb = 1'b1 + five; wire [4:0] sumc = five - 1'b1; // Relatively harmless < or <= compared with something less wide localparam [1:0] THREE = 3; int a; initial for (a = 0; a < THREE; ++a) $display(a); initial for (a = 0; a <= THREE; ++a) $display(a); endmodule verilator-4.038/test_regress/t/t_interface_arraymux.pl0000775000177100017500000000076613702133370023253 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); lint(); ok(1); 1; verilator-4.038/test_regress/t/t_select_bad_tri.out0000664000177100017500000000070713702133370022512 0ustar wsnyderwsnyder%Error: t/t_select_bad_tri.v:11:24: Selection index is constantly unknown or tristated: 1'bx 11 | if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; | ^ %Error: Internal Error: t/t_select_bad_tri.v:11:24: ../V3Number.cpp:#: toUInt with 4-state 1'bx : ... In instance t 11 | if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; | ^ verilator-4.038/test_regress/t/t_inside_wild.v0000664000177100017500000000342313702133370021475 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; wire [4:0] in = crc[4:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out), // Inputs .clk (clk), .in (in[4:0])); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h7a7bd4ee927e7cc3 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); //bug718 input clk; input logic [4:0] in; output logic out; always @(posedge clk) begin out <= in inside {5'b1_1?1?}; end endmodule verilator-4.038/test_regress/t/t_flag_timescale_override.pl0000775000177100017500000000122013702133370024203 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); compile( verilator_flags2 => ["-timescale-override 1ms/1us"], ); execute( check_finished => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_unroll_complexcond.v0000664000177100017500000000200213702133370023101 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This files is used to generated the BLKLOOPINIT error which // is actually caused by not being able to unroll the for loop. // // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] tmp [3:0]; initial begin tmp[0] = 4'b0000; tmp[2] = 4'b0010; tmp[3] = 4'b0011; end // Test loop always @ (posedge clk) begin int i; int j; for (i = 0;(i < 4) && (i > 1); i++) begin tmp[i] <= tmp[i-i]; end if (tmp[0] != 4'b0000) $stop; if (tmp[3] != 4'b0011) $stop; j = 0; for (i=$c32("1"); i<3; ++i) j++; if (j!=2) $stop; j = 0; for (i=1; i<$c32("3"); ++i) j++; if (j!=2) $stop; j = 0; for (i=1; i<3; i=i+$c32("1")) j++; if (j!=2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_lint_implicit.v0000664000177100017500000000061513702133370022043 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (a,z); input a; output z; assign b = 1'b1; or OR0 (nt0, a, b); logic [1:0] dummy_ip; assign {dummy1, dummy2} = dummy_ip; assign z = nt0; endmodule verilator-4.038/test_regress/t/t_class_new_bad.out0000664000177100017500000000111113702133367022327 0ustar wsnyderwsnyder%Error: t/t_class_new_bad.v:31:16: Too many arguments in function call to FUNC 'new' 31 | c1 = new(3); | ^ %Error: t/t_class_new_bad.v:32:16: Too many arguments in function call to FUNC 'new' 32 | c2 = new(3); | ^ %Error: t/t_class_new_bad.v:33:12: Missing argument on non-defaulted argument 'i' in function call to FUNC 'new' 33 | c3 = new(); | ^~~ %Error: Internal Error: t/t_class_new_bad.v:33:12: ../V3Broken.cpp:#: Width != WidthMin 33 | c3 = new(); | ^~~ verilator-4.038/test_regress/t/t_cover_line_trace.pl0000775000177100017500000000200013702133370022645 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_cover_line.v"); compile( verilator_flags2 => ['--cc --coverage-line --trace --trace-coverage +define+ATTRIBUTE'], ); execute( check_finished => 1, ); run(cmd => ["../bin/verilator_coverage", "--annotate", "$Self->{obj_dir}/annotated", "$Self->{obj_dir}/coverage.dat", ], verilator_run => 1, ); files_identical("$Self->{obj_dir}/annotated/t_cover_line.v", "t/t_cover_line.out"); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); ok(1); 1; verilator-4.038/test_regress/t/t_gen_upscope.v0000664000177100017500000000403613702133370021513 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 /* Acceptable answer 1 created tag with scope = top.t.tag created tag with scope = top.t.b.gen[0].tag created tag with scope = top.t.b.gen[1].tag mod a has scope = top.t mod a has tag = top.t.tag mod b has scope = top.t.b mod b has tag = top.t.tag mod c has scope = top.t.b.gen[0].c mod c has tag = top.t.b.gen[0].tag mod c has scope = top.t.b.gen[1].c mod c has tag = top.t.b.gen[1].tag */ /* Acceptable answer 2 created tag with scope = top.t.tag created tag with scope = top.t.b.gen[0].tag created tag with scope = top.t.b.gen[1].tag mod a has scope = top.t mod a has tag = top.t.tag mod b has scope = top.t.b mod b has tag = top.t.tag mod c has scope = top.t.b.gen[0].c mod c has tag = top.t.tag mod c has scope = top.t.b.gen[1].c mod c has tag = top.t.tag */ module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; tag tag (); b b (); always @ (t.cyc) begin if (t.cyc == 2) $display("mod a has scope = %m"); if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope); end always @(posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module b (); genvar g; generate for (g=0; g<2; g++) begin : gen tag tag (); c c (); end endgenerate always @ (t.cyc) begin if (t.cyc == 3) $display("mod b has scope = %m"); if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope); end endmodule module c (); always @ (t.cyc) begin if (t.cyc == 4) $display("mod c has scope = %m"); if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope); end endmodule module tag (); bit [100*8-1:0] scope; initial begin $sformat(scope,"%m"); $display("created tag with scope = %0s",scope); end endmodule verilator-4.038/test_regress/t/t_inst_v2k.v0000664000177100017500000000300113702133370020732 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; supply0 [1:0] low; supply1 [1:0] high; reg [7:0] isizedwire; reg ionewire; `ifdef never_just_for_verilog_mode wire oonewire; // From sub of t_inst_v2k__sub.v `endif wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v wire [1:0] tied; wire [3:0] tied_also; hello hsub (.tied_also); // Double underscore tests bug631 t_inst_v2k__sub sub ( // Outputs .osizedreg (osizedreg[7:0]), // verilator lint_off IMPLICIT .oonewire (oonewire), // verilator lint_on IMPLICIT .tied (tied[1:0]), // Inputs .isizedwire (isizedwire[7:0]), .ionewire (ionewire)); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin ionewire <= 1'b1; isizedwire <= 8'd8; end if (cyc==2) begin if (low != 2'b00) $stop; if (high != 2'b11) $stop; if (oonewire !== 1'b1) $stop; if (isizedwire !== 8'd8) $stop; if (tied != 2'b10) $stop; if (tied_also != 4'b1010) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module hello(tied_also); initial $write ("Hello\n"); output reg [3:0] tied_also = 4'b1010; endmodule verilator-4.038/test_regress/t/t_optm_if_array.v0000664000177100017500000000201213702133370022027 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dinitout, // Inputs clk, rstn ); input clk; input rstn; output [31:0] dinitout; wire zero; assign zero = 1'd0; reg [31:0] dinit [0:1]; wire [31:0] dinitout = dinit[0] | dinit[1]; reg rstn_r; // .pl file checks that this signal gets optimized away always @(posedge clk) begin rstn_r <= rstn; end always @(posedge clk) begin if ((rstn_r == 0)) begin // Will optimize away dinit[0] <= '0; end else begin dinit[0] <= {31'd0, zero}; end end always @(posedge clk) begin if ((rstn_r == 0)) begin // Will optimize away dinit[1] <= 1234; end else begin dinit[1] <= 1234; end end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_unopt_converge_initial_run_bad.out0000664000177100017500000000045313702133370026005 0ustar wsnyderwsnyder-V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_unopt_converge_initial_run_bad::_change_request -V{t#,#} CHANGE: t/t_unopt_converge_initial.v:19: x %Error: t/t_unopt_converge_initial.v:7: Verilated model didn't DC converge Aborting... verilator-4.038/test_regress/t/t_flag_ldflags.v0000664000177100017500000000133113702133370021604 0ustar wsnyderwsnyder// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" pure function void dpii_a_library(); import "DPI-C" pure function void dpii_c_library(); import "DPI-C" pure function void dpii_so_library(); module t (); initial begin dpii_a_library(); // From .a file dpii_c_library(); // From .cpp file dpii_so_library(); // From .so file $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-4.038/test_regress/t/t_wire_types.pl0000775000177100017500000000121713702133370021545 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{verilated_randReset} = 1; # allow checking if we initialize vars to zero only when needed compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_const_packed_array_bad.out0000664000177100017500000000161413702133370025221 0ustar wsnyderwsnyder%Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_array_bad.v:12:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t t/t_func_const_packed_array_bad.v:23:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_packed_array_bad.v:31:16: ... Called from f_add() with parameters: params = [0 = 32'h7, 1 = 32'h8] t/t_func_const_packed_array_bad.v:12:21: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 12 | localparam P24 = f_add2(7, 8, 9); | ^~~~~~ %Error: Exiting due to verilator-4.038/test_regress/t/t_interface_twod.pl0000775000177100017500000000106013702133370022344 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2009 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_mem_multi_io3.cpp0000664000177100017500000000076113702133370022264 0ustar wsnyderwsnyder// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = NULL; bool pass = true; double sc_time_stamp() { return 0; } #ifdef SYSTEMC_VERSION int sc_main(int, char**) #else int main() #endif { Verilated::debug(0); tb = new VM_PREFIX("tb"); // Just a constructor test VL_PRINTF("*-* All Finished *-*\n"); return 0; } verilator-4.038/test_regress/t/t_unoptflat_simple_2_bad.pl0000775000177100017500000000131113702133370023762 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_unoptflat_simple_2.v"); # Compile only compile( verilator_flags3 => [], verilator_flags2 => ["--report-unoptflat"], fails => 1, expect_filename => $Self->{golden_filename}, ); ok(1); 1; verilator-4.038/test_regress/t/t_func_types.pl0000775000177100017500000000105313702133370021530 0ustar wsnyderwsnyder#!/usr/bin/env perl if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); compile( ); execute( check_finished => 1, ); ok(1); 1; verilator-4.038/test_regress/t/t_sys_file_basic_mcd_test2_2.dat0000664000177100017500000000020213702133370024641 0ustar wsnyderwsnyderScotland is the greatest country. All other countries are inferior. Woe betide those to stand against the mighty Scottish nation. verilator-4.038/test_regress/input.xsim.vc0000664000177100017500000000016613702133367020705 0ustar wsnyderwsnyder --sourcelibext .v --sourcelibdir t --sourcelibdir obj_dir/ --include t --include ../include --include obj_dir/ verilator-4.038/Makefile.in0000664000177100017500000004517013702133367015575 0ustar wsnyderwsnyder#***************************************************************************** # DESCRIPTION: Verilator top level: Makefile pre-configure version # # This file is part of Verilator. # # Code available from: https://verilator.org # #***************************************************************************** # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ # # make all to compile and build Verilator. # make install to install it. # make TAGS to update tags tables. # # make clean or make mostlyclean # Delete all files from the current directory that are normally # created by building the program. Don't delete the files that # record the configuration. Also preserve files that could be made # by building, but normally aren't because the distribution comes # with them. # # make distclean # Delete all files from the current directory that are created by # configuring or building the program. If you have unpacked the # source and built the program without creating any other files, # `make distclean' should leave only the files that were in the # distribution. # # make maintainer-clean # Delete everything from the current directory that can be # reconstructed with this Makefile. This typically includes # everything deleted by distclean, plus more: C source files # produced by Bison, tags tables, info files, and so on. #### Start of system configuration section. #### srcdir = @srcdir@ VPATH = @srcdir@ HOST = @HOST@ DOXYGEN = doxygen INSTALL = @INSTALL@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_DATA = @INSTALL_DATA@ MAKEINFO = makeinfo POD2TEXT = pod2text POD2LATEXFIX = $(srcdir)/src/pod2latexfix MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs PERL = @PERL@ # Destination prefix for RPMs DESTDIR = #### Don't edit: You're much better using configure switches to set these prefix = @prefix@ exec_prefix = @exec_prefix@ # Directory in which to install scripts. bindir = @bindir@ # Directory in which to install manpages. mandir = @mandir@ # Directory in which to install library files. datadir = @datadir@ # Directory in which to install documentation info files. infodir = @infodir@ # Directory in which to install package specific files # Generally ${prefix}/share/verilator pkgdatadir = @pkgdatadir@ # Directory in which to install pkgconfig file # Generally ${prefix}/share/pkgconfig pkgconfigdir = @pkgconfigdir@ # Directory in which to install data across multiple architectures datarootdir = @datarootdir@ # Compile options CFG_WITH_CCWARN = @CFG_WITH_CCWARN@ CFG_WITH_DEFENV = @CFG_WITH_DEFENV@ CFG_WITH_LONGTESTS = @CFG_WITH_LONGTESTS@ CFG_WITH_THREADED = @CFG_WITH_THREADED@ PACKAGE_VERSION = @PACKAGE_VERSION@ #### End of system configuration section. #### ###################################################################### .SUFFIXES: SHELL = /bin/sh SUBDIRS = docs src test_regress \ examples/cmake_hello_c \ examples/cmake_hello_sc \ examples/cmake_tracing_c \ examples/cmake_tracing_sc \ examples/cmake_protect_lib \ examples/make_hello_c \ examples/make_hello_sc \ examples/make_tracing_c \ examples/make_tracing_sc \ examples/make_protect_lib \ examples/xml_py \ INFOS = verilator.txt verilator.html verilator.pdf INFOS_OLD = README README.html README.pdf # Files that can be generated, but should be up to date for a distribution. DISTDEP = info Makefile DISTFILES_INC = $(INFOS) .gitignore \ *.in *.ac \ Artistic \ Changes \ LICENSE \ MANIFEST.SKIP \ README.adoc \ verilator-config.cmake.in \ verilator-config-version.cmake.in \ bin/verilator \ bin/verilator_coverage \ bin/verilator_difftree \ bin/verilator_gantt \ bin/verilator_includer \ bin/verilator_profcfunc \ docs/.gitignore \ docs/CONTRIBUTING.adoc \ docs/CONTRIBUTORS \ docs/Makefile.in \ docs/TODO \ docs/doxygen-mainpage \ docs/doxygen.config \ docs/install.adoc \ docs/internals.adoc \ docs/verilator_logo.png \ docs/xml.adoc \ install-sh configure *.pod \ include/*.[chv]* \ include/*.in \ include/.*ignore \ include/gtkwave/*.[chv]* \ include/vltstd/*.[chv]* \ .*attributes */.*attributes */*/.*attributes \ src/.*ignore src/*.in src/*.cpp src/*.[chly] \ src/astgen src/bisonpre src/*fix src/cppcheck_filtered \ src/vlcovgen src/mkinstalldirs \ src/.gdbinit \ src/*.pl src/*.pod \ examples/*/.*ignore examples/*/Makefile* \ examples/*/*.[chv]* examples/*/vl_* \ examples/*/CMakeLists.txt \ test_*/.*ignore test_*/Makefile* test_*/*.cpp \ test_*/*.pl test_*/*.v test_*/*.vc test_*/*.vh \ test_regress/*.pl \ test_regress/Makefile \ test_regress/Makefile_obj \ test_regress/input.vc \ test_regress/CMakeLists.txt \ test_regress/t/t*/*.sv* \ test_regress/t/t*/*.v* \ test_regress/t/t*/*/*.sv* \ test_regress/t/t*/*/*.v* \ test_regress/t/*.cpp \ test_regress/t/*.h \ test_regress/t/*.dat \ test_regress/t/*.mem \ test_regress/t/*.out \ test_regress/t/*.pl \ test_regress/t/*.pf \ test_regress/t/*.v* \ INST_PROJ_FILES = \ bin/verilator \ bin/verilator_coverage \ bin/verilator_gantt \ bin/verilator_includer \ bin/verilator_profcfunc \ include/verilated.mk \ include/*.[chv]* \ include/gtkwave/*.[chv]* \ include/vltstd/*.[chv]* \ INST_PROJ_BIN_FILES = \ bin/verilator_bin \ bin/verilator_bin_dbg \ bin/verilator_coverage_bin_dbg \ DISTFILES := $(DISTFILES_INC) EXAMPLES_FIRST = \ examples/make_hello_c \ examples/make_hello_sc \ EXAMPLES = $(EXAMPLES_FIRST) $(filter-out $(EXAMPLES_FIRST), $(sort $(wildcard examples/*))) # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff VL_INST_MAN_FILES = verilator.1 verilator_coverage.1 verilator_gantt.1 verilator_profcfunc.1 default: all all: all_nomsg msg_test all_nomsg: verilator_exe $(VL_INST_MAN_FILES) .PHONY:verilator_exe .PHONY:verilator_bin .PHONY:verilator_bin_dbg .PHONY:verilator_coverage_bin_dbg verilator_exe verilator_bin verilator_bin_dbg verilator_coverage_bin_dbg: @echo ------------------------------------------------------------ @echo "making verilator in src" $(MAKE) -C src $(OBJCACHE_JOBS) .PHONY:msg_test msg_test: all_nomsg @echo "Build complete!" @echo @echo "Now type 'make test' to test." @echo .PHONY: test ifeq ($(CFG_WITH_LONGTESTS),yes) # Local... Else don't burden users test: smoke-test test_regress # examples is part of test_regress's test_regress/t/t_a2_examples.pl # (because that allows it to run in parallel with other test_regress's) else test: smoke-test examples endif @echo "Tests passed!" @echo @echo "Now type 'make install' to install." @echo "Or type 'make' inside an examples subdirectory." @echo smoke-test: all_nomsg test_regress/t/t_a1_first_cc.pl test_regress/t/t_a2_first_sc.pl test_regress: all_nomsg $(MAKE) -C test_regress examples: all_nomsg for p in $(EXAMPLES) ; do \ $(MAKE) -C $$p VERILATOR_ROOT=`pwd` || exit 10; \ done .PHONY: docs docs: info info: $(INFOS) %.1: ${srcdir}/bin/% pod2man $< $@ verilator.txt: ${srcdir}/bin/verilator $(POD2TEXT) $< $@ verilator.html: ${srcdir}/bin/verilator pod2html $< >$@ # PDF needs DIST variables; but having configure.ac as dependency isn't detected verilator.pdf: ${srcdir}/bin/verilator Makefile $(POD2LATEXFIX) pod2latex --full --out verilator.tex $< $(PERL) $(POD2LATEXFIX) "$(DISTTITLE)" "${DISTDATE}" < verilator.tex > verilator2.tex mv verilator2.tex verilator.tex pdflatex verilator.tex pdflatex verilator.tex -rm -f verilator.toc verilator.aux verilator.idx verilator.out # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg verilator_coverage_bin_dbg \ verilator_coverage verilator_gantt verilator_includer verilator_profcfunc # Some scripts go into both the search path and pkgdatadir, # so they can be found by the user, and under $VERILATOR_ROOT. VL_INST_INC_BLDDIR_FILES = \ include/verilated_config.h \ include/verilated.mk \ # Files under srcdir, instead of build time VL_INST_INC_SRCDIR_FILES = \ include/*.[chv]* \ include/gtkwave/*.[chv]* \ include/vltstd/*.[chv]* \ VL_INST_DATA_SRCDIR_FILES = \ examples/*/*.[chv]* examples/*/Makefile* \ examples/*/CMakeLists.txt installbin: $(MKINSTALLDIRS) $(DESTDIR)$(bindir) ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator $(DESTDIR)$(bindir)/verilator ) ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_coverage $(DESTDIR)$(bindir)/verilator_coverage ) ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_gantt $(DESTDIR)$(bindir)/verilator_gantt ) ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_profcfunc $(DESTDIR)$(bindir)/verilator_profcfunc ) ( cd bin ; $(INSTALL_PROGRAM) verilator_bin $(DESTDIR)$(bindir)/verilator_bin ) ( cd bin ; $(INSTALL_PROGRAM) verilator_bin_dbg $(DESTDIR)$(bindir)/verilator_bin_dbg ) ( cd bin ; $(INSTALL_PROGRAM) verilator_coverage_bin_dbg $(DESTDIR)$(bindir)/verilator_coverage_bin_dbg ) $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/bin ( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_includer $(DESTDIR)$(pkgdatadir)/bin/verilator_includer ) # Man files can either be part of the original kit, or built in current directory # So important we use $^ so VPATH is searched installman: $(VL_INST_MAN_FILES) $(MKINSTALLDIRS) $(DESTDIR)$(mandir)/man1 for p in $^ ; do \ $(INSTALL_DATA) $$p $(DESTDIR)$(mandir)/man1/$$p; \ done installdata: $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/include/gtkwave $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/include/vltstd for p in $(VL_INST_INC_BLDDIR_FILES) ; do \ $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \ done cd $(srcdir) \ ; for p in $(VL_INST_INC_SRCDIR_FILES) ; do \ $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \ done $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_hello_c $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_hello_sc $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_tracing_c $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_tracing_sc $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_protect_lib $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_hello_c $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_hello_sc $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_c $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_sc $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_protect_lib $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/xml_py cd $(srcdir) \ ; for p in $(VL_INST_DATA_SRCDIR_FILES) ; do \ $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \ done $(MKINSTALLDIRS) $(DESTDIR)$(pkgconfigdir) $(INSTALL_DATA) verilator.pc $(DESTDIR)$(pkgconfigdir) $(INSTALL_DATA) verilator-config.cmake $(DESTDIR)$(pkgdatadir) $(INSTALL_DATA) verilator-config-version.cmake $(DESTDIR)$(pkgdatadir) # We don't trust rm -rf, so rmdir instead as it will fail if user put in other files uninstall: -cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_BIN_FILES) -cd $(DESTDIR)$(pkgdatadir)/bin && rm -f $(VL_INST_BIN_FILES) -cd $(DESTDIR)$(mandir)/man1 && rm -f $(VL_INST_MAN_FILES) -cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_BLDDIR_FILES) -cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_SRCDIR_FILES) -cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_DATA_SRCDIR_FILES) -rm $(DESTDIR)$(pkgconfigdir)/verilator.pc -rm $(DESTDIR)$(pkgdatadir)/verilator-config.cmake -rm $(DESTDIR)$(pkgdatadir)/verilator-config-version.cmake -rmdir $(DESTDIR)$(pkgdatadir)/bin -rmdir $(DESTDIR)$(pkgdatadir)/include/gtkwave -rmdir $(DESTDIR)$(pkgdatadir)/include/vltstd -rmdir $(DESTDIR)$(pkgdatadir)/include -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_hello_c -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_hello_sc -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_tracing_c -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_tracing_sc -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_protect_lib -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_hello_c -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_hello_sc -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_c -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_sc -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_protect_lib -rmdir $(DESTDIR)$(pkgdatadir)/examples/xml_py -rmdir $(DESTDIR)$(pkgdatadir)/examples -rmdir $(DESTDIR)$(pkgdatadir) -rmdir $(DESTDIR)$(pkgconfigdir) install: all_nomsg install-all install-all: installbin installman installdata install-msg install-here: installman ftp ifeq ($(VERILATOR_AUTHOR_SITE),1) # Local... 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UNLESS REQUIRED BY LAW, NO COPYRIGHT HOLDER OR CONTRIBUTOR WILL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING IN ANY WAY OUT OF THE USE OF THE PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. verilator-4.038/install-sh0000664000177100017500000001271113536675452015537 0ustar wsnyderwsnyder#! /bin/sh # # install - install a program, script, or datafile # This comes from X11R5 (mit/util/scripts/install.sh). # # Copyright 1991 by the Massachusetts Institute of Technology # # Permission to use, copy, modify, distribute, and sell this software and its # documentation for any purpose is hereby granted without fee, provided that # the above copyright notice appear in all copies and that both that # copyright notice and this permission notice appear in supporting # documentation, and that the name of M.I.T. not be used in advertising or # publicity pertaining to distribution of the software without specific, # written prior permission. M.I.T. makes no representations about the # suitability of this software for any purpose. It is provided "as is" # without express or implied warranty. # # Calling this script install-sh is preferred over install.sh, to prevent # `make' implicit rules from creating a file called install from it # when there is no Makefile. # # This script is compatible with the BSD install script, but was written # from scratch. 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If we want to # ignore errors from any of these, just make sure not to ignore # errors from the above "$doit $instcmd $src $dsttmp" command. if [ x"$chowncmd" != x ]; then $doit $chowncmd $dsttmp; else true;fi && if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dsttmp; else true;fi && if [ x"$stripcmd" != x ]; then $doit $stripcmd $dsttmp; else true;fi && if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dsttmp; else true;fi && # Now rename the file to the real destination. $doit $rmcmd -f $dstdir/$dstfile && $doit $mvcmd $dsttmp $dstdir/$dstfile fi && exit 0 verilator-4.038/verilator.html0000664000177100017500000075501013702335700016421 0ustar wsnyderwsnyder Verilator - Translate and simulate SystemVerilog code using C++/SystemC

NAME

Verilator - Translate and simulate SystemVerilog code using C++/SystemC

SYNOPSIS

    verilator --help
    verilator --version
    verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
    verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
    verilator --lint-only -Wall [source_files.v]...

DESCRIPTION

The "Verilator" package converts all synthesizable, and many behavioral, Verilog and SystemVerilog designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler.

Verilator is typically used as follows:

1. The verilator executable is invoked with parameters similar to GCC, Cadence Verilog-XL/NC-Verilog, or Synopsys VCS. verilator reads the specified user's SystemVerilog code, lints it, optionally adds coverage and waveform tracing support, and compiles the design into a source level C++ or SystemC "model". The resulting model's C++ or SystemC code is output as .cpp and .h files. This is referred to as "verilating" and the process is "to verilate"; the output is a "verilated" model.

2. For simulation, a small user written C++ wrapper file is required, the "wrapper". This wrapper defines the C++ function `main()` which instantiates the Verilated model as a C++/SystemC object.

3. The user main wrapper, the files created by Verilator, a "runtime library" provided by Verilator, and if applicable the SystemC libraries are then compiled using a C++ compiler to create a simulation executable.

4. The resulting executable will perform the actual simulation, during "simulation runtime".

To get started, jump down to the "EXAMPLE C++ EXECUTION" section.

ARGUMENT SUMMARY

This is a short summary of the arguments to the "verilator" executable. See "VERILATION ARGUMENTS" for the detailed descriptions of these arguments.

    {file.v}                    Verilog package, module and top module filenames
    {file.c/cc/cpp}             Optional C++ files to compile in
    {file.a/o/so}               Optional C++ files to link in

     +1364-1995ext+<ext>        Use Verilog 1995 with file extension <ext>
     +1364-2001ext+<ext>        Use Verilog 2001 with file extension <ext>
     +1364-2005ext+<ext>        Use Verilog 2005 with file extension <ext>
     +1800-2005ext+<ext>        Use SystemVerilog 2005 with file extension <ext>
     +1800-2009ext+<ext>        Use SystemVerilog 2009 with file extension <ext>
     +1800-2012ext+<ext>        Use SystemVerilog 2012 with file extension <ext>
     +1800-2017ext+<ext>        Use SystemVerilog 2017 with file extension <ext>
    --assert                    Enable all assertions
    --autoflush                 Flush streams after all $displays
    --bbox-sys                  Blackbox unknown $system calls
    --bbox-unsup                Blackbox unsupported language features
    --bin <filename>            Override Verilator binary
    --build                     Build model executable/library after Verilation
     -CFLAGS <flags>            C++ compiler flags for makefile
    --cc                        Create C++ output
    --cdc                       Clock domain crossing analysis
    --clk <signal-name>         Mark specified signal as clock
    --make <build-tool>         Generate scripts for specified build tool
    --compiler <compiler-name>  Tune for specified C++ compiler
    --converge-limit <loops>    Tune convergence settle time
    --coverage                  Enable all coverage
    --coverage-line             Enable line coverage
    --coverage-toggle           Enable toggle coverage
    --coverage-user             Enable SVL user coverage
    --coverage-underscore       Enable coverage of _signals
     -D<var>[=<value>]          Set preprocessor define
    --debug                     Enable debugging
    --debug-check               Enable debugging assertions
    --no-debug-leak             Disable leaking memory in --debug mode
    --debugi <level>            Enable debugging at a specified level
    --debugi-<srcfile> <level>  Enable debugging a source file at a level
    --default-language <lang>   Default language to parse
     +define+<var>=<value>      Set preprocessor define
    --dpi-hdr-only              Only produce the DPI header file
    --dump-defines              Show preprocessor defines with -E
    --dump-tree                 Enable dumping .tree files
    --dump-treei <level>        Enable dumping .tree files at a level
    --dump-treei-<srcfile> <level>  Enable dumping .tree file at a source file at a level
    --dump-tree-addrids         Use short identifiers instead of addresses
     -E                         Preprocess, but do not compile
    --error-limit <value>       Abort after this number of errors
    --exe                       Link to create executable
     -F <file>                  Parse options from a file, relatively
     -f <file>                  Parse options from a file
     -FI <file>                 Force include of a file
    --flatten                   Force inlining of all modules, tasks and functions
     -G<name>=<value>           Overwrite top-level parameter
    --gdb                       Run Verilator under GDB interactively
    --gdbbt                     Run Verilator under GDB for backtrace
    --generate-key              Create random key for --protect-key
    --getenv <var>              Get environment variable with defaults
    --help                      Display this help
     -I<dir>                    Directory to search for includes
     -j <jobs>                  Parallelism for --build
    --gate-stmts <value>        Tune gate optimizer depth
    --if-depth <value>          Tune IFDEPTH warning
     +incdir+<dir>              Directory to search for includes
    --inhibit-sim               Create function to turn off sim
    --inline-mult <value>       Tune module inlining
     -LDFLAGS <flags>           Linker pre-object flags for makefile
    --l2-name <value>           Verilog scope name of the top module
    --language <lang>           Default language standard to parse
     +libext+<ext>+[ext]...     Extensions for finding modules
    --lint-only                 Lint, but do not make output
     -MAKEFLAGS <flags>         Options to make during --build
    --max-num-width <value>     Maximum number width (default: 64K)
    --MMD                       Create .d dependency files
    --MP                        Create phony dependency targets
    --Mdir <directory>          Name of output object directory
    --mod-prefix <topname>      Name to prepend to lower classes
    --no-clk <signal-name>      Prevent marking specified signal as clock
    --no-decoration             Disable comments and symbol decorations
    --no-pins64                 Don't use vluint64_t's for 33-64 bit sigs
    --no-skip-identical         Disable skipping identical output
     +notimingchecks            Ignored
     -O0                        Disable optimizations
     -O3                        High performance optimizations
     -O<optimization-letter>    Selectable optimizations
     -o <executable>            Name of final executable
    --no-order-clock-delay      Disable ordering clock enable assignments
    --no-verilate               Skip verilation and just compile previously Verilated code.
    --output-split <statements>          Split .cpp files into pieces
    --output-split-cfuncs <statements>   Split model functions
    --output-split-ctrace <statements>   Split tracing functions
     -P                         Disable line numbers and blanks with -E
    --pins-bv <bits>            Specify types for top level ports
    --pins-sc-uint              Specify types for top level ports
    --pins-sc-biguint           Specify types for top level ports
    --pins-uint8                Specify types for top level ports
    --pipe-filter <command>     Filter all input through a script
    --pp-comments               Show preprocessor comments with -E
    --prefix <topname>          Name of top level class
    --prof-cfuncs               Name functions for profiling
    --prof-threads              Enable generating gantt chart data for threads
    --protect-key <key>         Key for symbol protection
    --protect-ids               Hash identifier names for obscurity
    --protect-lib <name>        Create a DPI protected library
    --private                   Debugging; see docs
    --public                    Debugging; see docs
    --public-flat-rw            Mark all variables, etc as public_flat_rw
     -pvalue+<name>=<value>     Overwrite toplevel parameter
    --quiet-exit                Don't print the command on failure
    --relative-includes         Resolve includes relative to current file
    --no-relative-cfuncs        Disallow 'this->' in generated functions
    --report-unoptflat          Extra diagnostics for UNOPTFLAT
    --rr                        Run Verilator and record with rr
    --savable                   Enable model save-restore
    --sc                        Create SystemC output
    --stats                     Create statistics file
    --stats-vars                Provide statistics on variables
     -sv                        Enable SystemVerilog parsing
     +systemverilogext+<ext>    Synonym for +1800-2017ext+<ext>
    --threads <threads>         Enable multithreading
    --threads-dpi <mode>        Enable multithreaded DPI
    --threads-max-mtasks <mtasks>  Tune maximum mtask partitioning
    --timescale <timescale>     Sets default timescale
    --timescale-override <timescale>  Overrides all timescales
    --top-module <topname>      Name of top level input module
    --trace                     Enable waveform creation
    --trace-coverage            Enable tracing of coverage
    --trace-depth <levels>      Depth of tracing
    --trace-fst                 Enable FST waveform creation
    --trace-max-array <depth>   Maximum bit width for tracing
    --trace-max-width <width>   Maximum array depth for tracing
    --trace-params              Enable tracing of parameters
    --trace-structs             Enable tracing structure names
    --trace-threads <threads>   Enable waveform creation on separate threads
    --trace-underscore          Enable tracing of _signals
     -U<var>                    Undefine preprocessor define
    --unroll-count <loops>      Tune maximum loop iterations
    --unroll-stmts <stmts>      Tune maximum loop body size
    --unused-regexp <regexp>    Tune UNUSED lint signals
     -V                         Verbose version and config
     -v <filename>              Verilog library
     +verilog1995ext+<ext>      Synonym for +1364-1995ext+<ext>
     +verilog2001ext+<ext>      Synonym for +1364-2001ext+<ext>
    --version                   Displays program version and exits
    --vpi                       Enable VPI compiles
    --waiver-output <filename>  Create a waiver file based on the linter warnings
     -Wall                      Enable all style warnings
     -Werror-<message>          Convert warnings to errors
     -Wfuture-<message>         Disable unknown message warnings
     -Wno-<message>             Disable warning
     -Wno-context               Disable source context on warnings
     -Wno-fatal                 Disable fatal exit on warnings
     -Wno-lint                  Disable all lint warnings
     -Wno-style                 Disable all style warnings
     -Wpedantic                 Warn on compliance-test issues
    --x-assign <mode>           Assign non-initial Xs to this value
    --x-initial <mode>          Assign initial Xs to this value
    --x-initial-edge            Enable initial X->0 and X->1 edge triggers
    --xml-only                  Create XML parser output
    --xml-output                XML output filename
     -y <dir>                   Directory to search for modules

This is a short summary of the simulation runtime arguments, i.e. for the final Verilated simulation runtime models. See "SIMULATION RUNTIME ARGUMENTS" for the detailed description of these arguments.

     +verilator+debug                  Enable debugging
     +verilator+debugi+<value>         Enable debugging at a level
     +verilator+help                   Display help
     +verilator+prof+threads+file+I<filename>  Set profile filename
     +verilator+prof+threads+start+I<value>    Set profile starting point
     +verilator+prof+threads+window+I<value>   Set profile duration
     +verilator+rand+reset+I<value>    Set random reset technique
     +verilator+seed+I<value>          Set random seed
     +verilator+noassert               Disable assert checking
     +verilator+V                      Verbose version and config
     +verilator+version                Show version and exit

VERILATION ARGUMENTS

The following are the arguments that may be passed to the "verilator" executable.

{file.v}

Specifies the Verilog file containing the top module to be Verilated.

{file.c/.cc/.cpp/.cxx}

Used with --exe to specify optional C++ files to be linked in with the Verilog code. The file path should either be absolute, or relative to where the make will be executed from, or add to your makefile's VPATH the appropriate directory to find the file.

See also the -CFLAGS and -LDFLAGS options, which are useful when the C++ files need special compiler flags.

{file.a/.o/.so}

Specifies optional object or library files to be linked in with the Verilog code, as a shorthand for -LDFLAGS "<file>". The file path should either be absolute, or relative to where the make will be executed from, or add to your makefile's VPATH the appropriate directory to find the file.

If any files are specified in this way, Verilator will include a make rule that uses these files when linking the module executable. This generally is only useful when used with the --exe option.

+1364-1995ext+ext
+1364-2001ext+ext
+1364-2005ext+ext
+1800-2005ext+ext
+1800-2009ext+ext
+1800-2012ext+ext
+1800-2017ext+ext

Specifies the language standard to be used with a specific filename extension, ext.

For compatibility with other simulators, see also the synonyms +verilog1995ext+ext, +verilog2001ext+ext, and +systemverilogext+ext.

For any source file, the language specified by these options takes precedence over any language specified by the --default-language or --language options.

These options take effect in the order they are encountered. Thus the following would use Verilog 1995 for a.v and Verilog 2001 for b.v.

    verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v

These flags are only recommended for legacy mixed language designs, as the preferable option is to edit the code to repair new keywords, or add appropriate `begin_keywords.

Note `begin_keywords is a SystemVerilog construct, which specifies only the set of keywords to be recognized. This also controls some error messages that vary between language standards. Note at present Verilator tends to be overly permissive, e.g. it will accept many grammar and other semantic extensions which might not be legal when set to an older standard.

--assert

Enable all assertions.

--autoflush

After every $display or $fdisplay, flush the output stream. This ensures that messages will appear immediately but may reduce performance. For best performance call "fflush(stdout)" occasionally in the C++ main loop. Defaults to off, which will buffer output as provided by the normal C/C++ standard library IO.

--bbox-sys

Black box any unknown $system task or function calls. System tasks will simply become no-operations, and system functions will be replaced with unsized zero. Arguments to such functions will be parsed, but not otherwise checked. This prevents errors when linting in the presence of company specific PLI calls.

Using this argument will likely cause incorrect simulation.

--bbox-unsup

Black box some unsupported language features, currently UDP tables, the cmos and tran gate primitives, deassign statements, and mixed edge errors. This may enable linting the rest of the design even when unsupported constructs are present.

Using this argument will likely cause incorrect simulation.

--bin filename

Rarely needed. Override the default filename for Verilator itself. When a dependency (.d) file is created, this filename will become a source dependency, such that a change in this binary will have make rebuild the output files.

--build

After generating the SystemC/C++ code, Verilator will invoke the toolchain to build the model library (and executable when --exe is also used). Verilator manages the build itself, and for this --build requires GNU Make to be available on the platform.

-CFLAGS flags

Add specified C compiler flag to the generated makefiles. For multiple flags either pass them as a single argument with space separators quoted in the shell (-CFLAGS "-a -b"), or use multiple -CFLAGS arguments (-CFLAGS -a -CFLAGS -b).

When make is run on the generated makefile these will be passed to the C++ compiler (g++/clang++/msvc++).

--cc

Specifies C++ without SystemC output mode; see also --sc.

--cdc

Permanently experimental. Perform some clock domain crossing checks and issue related warnings (CDCRSTLOGIC) and then exit; if warnings other than CDC warnings are needed make a second run with --lint-only. Additional warning information is also written to the file {prefix}__cdc.txt.

Currently only checks some items that other CDC tools missed; if you have interest in adding more traditional CDC checks, please contact the authors.

--clk signal-name

Sometimes it is quite difficult for Verilator to distinguish clock signals from other data signals. Occasionally the clock signals can end up in the checking list of signals which determines if further evaluation is needed. This will heavily degrade the performance of a Verilated model.

With --clk <signal-name>, user can specified root clock into the model, then Verilator will mark the signal as clocker and propagate the clocker attribute automatically to other signals derived from that. In this way, Verilator will try to avoid taking the clocker signal into checking list.

Note signal-name is specified by the RTL hierarchy path. For example, v.foo.bar. If the signal is the input to top-module, the directly the signal name. If you find it difficult to find the exact name, try to use /*verilator clocker*/ in RTL file to mark the signal directly.

If clock signals are assigned to vectors and then later used individually, Verilator will attempt to decompose the vector and connect the single-bit clock signals directly. This should be transparent to the user.

--make build-tool

Generates a script for the specified build tool.

Supported values are gmake for GNU Make and cmake for CMake. Both can be specified together. If no build tool is specified, gmake is assumed. The executable of gmake can be configured via environment variable "MAKE".

When using --build Verilator takes over the responsibility of building the model library/executable. For this reason --make cannot be specified when using --build.

--compiler compiler-name

Enables workarounds for the specified C++ compiler, either clang, gcc, or msvc. Currently this does not change any performance tuning flags, but it may in the future.

clang

Tune for clang. This may reduce execution speed as it enables several workarounds to avoid silly hard-coded limits in clang. This includes breaking deep structures as for msvc as described below.

gcc

Tune for GNU C++, although generated code should work on almost any compliant C++ compiler. Currently the default.

msvc

Tune for Microsoft Visual C++. This may reduce execution speed as it enables several workarounds to avoid silly hard-coded limits in MSVC++. This includes breaking deeply nested parenthesized expressions into sub-expressions to avoid error C1009, and breaking deep blocks into functions to avoid error C1061.

--converge-limit loops

Rarely needed. Specifies the maximum number of runtime iterations before creating a model failed to converge error. Defaults to 100.

--coverage

Enables all forms of coverage, alias for "--coverage-line --coverage-toggle --coverage-user".

--coverage-line

Specifies basic block line coverage analysis code should be inserted.

Coverage analysis adds statements at each code flow change point (e.g. at branches). At each such branch a unique counter is incremented. At the end of a test, the counters along with the filename and line number corresponding to each counter are written into logs/coverage.dat.

Verilator automatically disables coverage of branches that have a $stop in them, as it is assumed $stop branches contain an error check that should not occur. A /*verilator coverage_block_off*/ comment will perform a similar function on any code in that block or below, or /*verilator coverage_on/coverage_off*/ will disable coverage around lines of code.

Note Verilator may over-count combinatorial (non-clocked) blocks when those blocks receive signals which have had the UNOPTFLAT warning disabled; for most accurate results do not disable this warning when using coverage.

--coverage-toggle

Specifies signal toggle coverage analysis code should be inserted.

Every bit of every signal in a module has a counter inserted. The counter will increment on every edge change of the corresponding bit.

Signals that are part of tasks or begin/end blocks are considered local variables and are not covered. Signals that begin with underscores, are integers, or are very wide (>256 bits total storage across all dimensions) are also not covered.

Hierarchy is compressed, such that if a module is instantiated multiple times, coverage will be summed for that bit across ALL instantiations of that module with the same parameter set. A module instantiated with different parameter values is considered a different module, and will get counted separately.

Verilator makes a minimally-intelligent decision about what clock domain the signal goes to, and only looks for edges in that clock domain. This means that edges may be ignored if it is known that the edge could never be seen by the receiving logic. This algorithm may improve in the future. The net result is coverage may be lower than what would be seen by looking at traces, but the coverage is a more accurate representation of the quality of stimulus into the design.

There may be edges counted near time zero while the model stabilizes. It's a good practice to zero all coverage just before releasing reset to prevent counting such behavior.

A /*verilator coverage_off/on */ comment pair can be used around signals that do not need toggle analysis, such as RAMs and register files.

--coverage-underscore

Enable coverage of signals that start with an underscore. Normally, these signals are not covered. See also --trace-underscore.

--coverage-user

Enables user inserted functional coverage. Currently, all functional coverage points are specified using SVA which must be separately enabled with --assert.

For example, the following statement will add a coverage point, with the comment "DefaultClock":

   DefaultClock: cover property (@(posedge clk) cyc==3);
-Dvar=value

Defines the given preprocessor symbol. Similar to +define, but does not allow multiple definitions with a single option using plus signs. +define is fairly standard across Verilog tools while -D is similar to GCC.

--debug

Select the debug executable of Verilator (if available), and enable more internal assertions (equivalent to --debug-check), debugging messages (equivalent to --debugi 4), and intermediate form dump files (equivalent to --dump-treei 3).

--debug-check

Rarely needed. Enable internal debugging assertion checks, without changing debug verbosity. Enabled automatically when --debug specified.

--no-debug-leak

In --debug mode, by default Verilator intentionally leaks AstNode instances instead of freeing them, so that each node pointer is unique in the resulting tree files and dot files.

This option disables the leak. This may avoid out-of-memory errors when Verilating large models in --debug mode.

Outside of --debug mode, AstNode instances should never be leaked and this option has no effect.

--debugi level
--debugi-srcfile level

Rarely needed - for developer use. Set internal debugging level globally to the specified debug level (1-10) or set the specified Verilator source file to the specified level (e.g. --debugi-V3Width 9). Higher levels produce more detailed messages.

--default-language value

Select the language to be used by default when first processing each Verilog file. The language value must be "1364-1995", "1364-2001", "1364-2005", "1800-2005", "1800-2009", "1800-2012" or "1800-2017".

Any language associated with a particular file extension (see the various +langext+ options) will be used in preference to the language specified by --default-language.

The --default-language flag is only recommended for legacy code using the same language in all source files, as the preferable option is to edit the code to repair new keywords, or add appropriate `begin_keywords. For legacy mixed language designs, the various +langext+ options should be used.

If no language is specified, either by this flag or +langext+ options, then the latest SystemVerilog language (IEEE 1800-2017) is used.

+define+var=value
+define+var=value+var2=value2...

Defines the given preprocessor symbol, or multiple symbols if separated by plus signs. Similar to -D; +define is fairly standard across Verilog tools while -D is similar to GCC.

--dpi-hdr-only

Only generate the DPI header file. This option has no effect on the name or location of the emitted DPI header file, it is output in --Mdir as it would be without this option.

--dump-defines

With -E, suppress normal output, and instead print a list of all defines existing at the end of pre-processing the input files. Similar to GCC "-dM" option. This also gives you a way of finding out what is predefined in Verilator using the command:

   touch foo.v ; verilator -E --dump-defines foo.v
--dump-tree

Rarely needed. Enable writing .tree debug files with dumping level 3, which dumps the standard critical stages. For details on the format see the Verilator Internals manual. --dump-tree is enabled automatically with --debug, so "--debug --no-dump-tree" may be useful if the dump files are large and not desired.

--dump-treei level
--dump-treei-srcfile level

Rarely needed - for developer use. Set internal tree dumping level globally to a specific dumping level or set the specified Verilator source file to the specified tree dumping level (e.g. --dump-treei-V3Order 9). Level 0 disables dumps and is equivalent to "--no-dump-tree". Level 9 enables dumping of every stage.

--dump-tree-addrids

Rarely needed - for developer use. Replace AST node addresses with short identifiers in tree dumps to enhance readability. Each unique pointer value is mapped to a unique identifier, but note that this is not necessarily unique per node instance as an address might get reused by a newly allocated node after a node with the same address has been dumped then freed.

-E

Preprocess the source code, but do not compile, as with 'gcc -E'. Output is written to standard out. Beware of enabling debugging messages, as they will also go to standard out.

--error-limit value

After this number of errors are encountered during Verilator run, exit. Warnings are not counted in this limit. Defaults to 50.

Does not affect simulation runtime errors, for those see +verilator+error+limit.

--exe

Generate an executable. You will also need to pass additional .cpp files on the command line that implement the main loop for your simulation.

-F file

Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the directory containing the specified file. See also -f. Note -F is fairly standard across Verilog tools.

-f file

Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the current directory. See also -F. Note -f is fairly standard across Verilog tools.

The file may contain // comments which are ignored to the end of the line. Any $VAR, $(VAR), or ${VAR} will be replaced with the specified environment variable.

-FI file

Force include of the specified C++ header file. All generated C++ files will insert a #include of the specified file before any other includes. The specified file might be used to contain define prototypes of custom VL_VPRINTF functions, and may need to include verilatedos.h as this file is included before any other standard includes.

--flatten

Force flattening of the design's hierarchy, with all modules, tasks and functions inlined. Typically used with --xml-only. Note flattening large designs may require significant CPU time, memory and storage.

-Gname=value

Overwrites the given parameter of the toplevel module. The value is limited to basic data literals:

Verilog integer literals

The standard Verilog integer literals are supported, so values like 32'h8, 2'b00, 4 etc. are allowed. Care must be taken that the single quote (I') is properly escaped in an interactive shell, e.g., as -GWIDTH=8\'hx.

C integer literals

It is also possible to use C integer notation, including hexadecimal (0x..), octal (0..) or binary (0b..) notation.

Double literals

Double literals must be one of the following styles: - contains a dot (.) (e.g. 1.23) - contains an exponent (e/E) (e.g. 12e3) - contains p/P for hexadecimal floating point in C99 (e.g. 0x123.ABCp1)

Strings

Strings must be in double quotes (""). They must be escaped properly on the command line, e.g. as -GSTR="\"My String\"" or -GSTR='"My String"'.

--gate-stmts value

Rarely needed. Set the maximum number of statements that may be present in an equation for the gate substitution optimization to inline that equation.

--gdb

Run Verilator underneath an interactive GDB (or VERILATOR_GDB environment variable value) session. See also --gdbbt.

--gdbbt

If --debug is specified, run Verilator underneath a GDB process and print a backtrace on exit, then exit GDB immediately. Without --debug or if GDB doesn't seem to work, this flag is ignored. Intended for easy creation of backtraces by users; otherwise see the --gdb flag.

--generate-key

Generate a true-random key suitable for use with --protect-key, print it, and exit immediately.

--getenv variable

If the variable is declared in the environment, print it and exit immediately. Otherwise, if it's built into Verilator (e.g. VERILATOR_ROOT), print that and exit immediately. Otherwise, print a newline and exit immediately. This can be useful in makefiles. See also -V, and the various *.mk files.

--help

Displays this message and program version and exits.

-Idir

See -y.

--if-depth value

Rarely needed. Set the depth at which the IFDEPTH warning will fire, defaults to 0 which disables this warning.

+incdir+dir

See -y.

--inhibit-sim

Rarely needed. Create a "inhibitSim(bool)" function to enable and disable evaluation. This allows an upper level testbench to disable modules that are not important in a given simulation, without needing to recompile or change the SystemC modules instantiated.

--inline-mult value

Tune the inlining of modules. The default value of 2000 specifies that up to 2000 new operations may be added to the model by inlining, if more than this number of operations would result, the module is not inlined. Larger values, or a value < 1 will inline everything, will lead to longer compile times, but potentially faster simulation speed. This setting is ignored for very small modules; they will always be inlined, if allowed.

-j <value>

Specify the level of parallelism for --build. <value> must be a positive integer specifying the maximum number of parallel build jobs, or can be omitted. When <value> is omitted, the build will not try to limit the number of parallel build jobs but attempt to execute all independent build steps in parallel.

-LDFLAGS flags

Add specified C linker flags to the generated makefiles. For multiple flags either pass them as a single argument with space separators quoted in the shell (-LDFLAGS "-a -b"), or use multiple -LDFLAGS arguments (-LDFLAGS -a -LDFLAGS -b).

When make is run on the generated makefile these will be passed to the C++ linker (ld) *after* the primary file being linked. This flag is called -LDFLAGS as that's the traditional name in simulators; it's would have been better called LDLIBS as that's the Makefile variable it controls. (In Make, LDFLAGS is before the first object, LDLIBS after. -L libraries need to be in the Make variable LDLIBS, not LDFLAGS.)

--l2-name value

Instead of using the module name when showing Verilog scope, use the name provided. This allows simplifying some Verilator-embedded modeling methodologies. Default is an l2-name matching the top module. The default before 3.884 was "--l2-name v"

For example, the program "module t; initial $display("%m"); endmodule" will show by default "t". With "--l2-name v" it will print "v".

--language value

A synonym for --default-language, for compatibility with other tools and earlier versions of Verilator.

+libext+ext+ext...

Specify the extensions that should be used for finding modules. If for example module x is referenced, look in x.ext. Note +libext+ is fairly standard across Verilog tools. Defaults to .v and .sv.

--lint-only

Check the files for lint violations only, do not create any other output.

You may also want the -Wall option to enable messages that are considered stylistic and not enabled by default.

If the design is not to be completely Verilated see also the --bbox-sys and --bbox-unsup options.

-MAKEFLAGS <string>

When using --build, add the specified flag to the invoked make command line. For multiple flags either pass them as a single argument with space separators quoted in the shell (e.g. -MAKEFLAGS "-a -b"), or use multiple -MAKEFLAGS arguments (e.g. -MAKEFLAGS -l -MAKEFLAGS -k). Use of this option should not be required for simple builds using the host toolchain.

--max-num-width value

Set the maximum number literal width (e.g. in 1024'd22 this it the 1024). Defaults to 64K.

--MMD =item --no-MMD

Enable/disable creation of .d dependency files, used for make dependency detection, similar to gcc -MMD option. By default this option is enabled for --cc or --sc modes.

--MP

When creating .d dependency files with --MMD, make phony targets. Similar to gcc -MP option.

--Mdir directory

Specifies the name of the Make object directory. All generated files will be placed in this directory. If not specified, "obj_dir" is used. The directory is created if it does not exist and the parent directories exist; otherwise manually create the Mdir before calling Verilator.

--mod-prefix topname

Specifies the name to prepend to all lower level classes. Defaults to the same as --prefix.

--no-clk signal-name

Prevent the specified signal from being marked as clock. See --clk.

--no-decoration

When creating output Verilated code, minimize comments, white space, symbol names and other decorative items, at the cost of greatly reduced readability. This may assist C++ compile times. This will not typically change the ultimate model's performance, but may in some cases.

--no-pins64

Backward compatible alias for "--pins-bv 33".

--no-relative-cfuncs

Disable 'this->' references in generated functions, and instead Verilator will generate absolute references starting from 'vlTOPp->'. This prevents V3Combine from merging functions from multiple instances of the same module, so it can grow the instruction stream.

This is a work around for old compilers. Don't set this if your C++ compiler supports __restrict__ properly, as GCC 4.5.x and newer do. For older compilers, test if this switch gives you better performance or not.

Compilers which don't honor __restrict__ will suspect that 'this->' references and 'vlTOPp->' references may alias, and may write slow code with extra loads and stores to handle the (imaginary) aliasing. Using only 'vlTOPp->' references allows these old compilers to produce tight code.

--no-skip-identical =item --skip-identical

Rarely needed. Disables or enables skipping execution of Verilator if all source files are identical, and all output files exist with newer dates. By default this option is enabled for --cc or --sc modes only.

+notimingchecks

Ignored for compatibility with other simulators.

-O0

Disables optimization of the model.

-O3

Enables slow optimizations for the code Verilator itself generates (as opposed to "-CFLAGS -O3" which effects the C compiler's optimization. -O3 may improve simulation performance at the cost of compile time. This currently sets --inline-mult -1.

-Ooptimization-letter

Rarely needed. Enables or disables a specific optimizations, with the optimization selected based on the letter passed. A lowercase letter disables an optimization, an upper case letter enables it. This is intended for debugging use only; see the source code for version-dependent mappings of optimizations to -O letters.

-o executable

Specify the name for the final executable built if using --exe. Defaults to the --prefix if not specified.

--no-order-clock-delay

Rarely needed. Disables a bug fix for ordering of clock enables with delayed assignments. This flag should only be used when suggested by the developers.

--output-split statements

Enables splitting the output .cpp files into multiple outputs. When a C++ file exceeds the specified number of operations, a new file will be created at the next function boundary. In addition, if the total output code size exceeds the specified value, VM_PARALLEL_BUILDS will be set to 1 by default in the generated make files, making parallel compilation possible. Using --output-split should have only a trivial impact on model performance. But can greatly improve C++ compilation speed. The use of ccache (set for you if present at configure time) is also more effective with this option.

This option is on by default with a value of 20000. To disable, pass with a value of 0.

--output-split-cfuncs statements

Enables splitting functions in the output .cpp files into multiple functions. When a generated function exceeds the specified number of operations, a new function will be created. With --output-split, this will enable the C++ compiler to compile faster, at a small loss in performance that gets worse with decreasing split values. Note that this option is stronger than --output-split in the sense that --output-split will not split inside a function.

Defaults to the value of --output-split, unless explicitly specified.

--output-split-ctrace statements

Similar to --output-split-cfuncs, enables splitting trace functions in the output .cpp files into multiple functions.

Defaults to the value of --output-split, unless explicitly specified.

-P

With -E, disable generation of `line markers and blank lines, similar to GCC -P flag.

--pins64

Backward compatible alias for "--pins-bv 65". Note that's a 65, not a 64.

--pins-bv width

Specifies SystemC inputs/outputs of greater than or equal to width bits wide should use sc_bv's instead of uint32/vluint64_t's. The default is "--pins-bv 65", and the value must be less than or equal to 65. Versions before Verilator 3.671 defaulted to "--pins-bv 33". The more sc_bv is used, the worse for performance. Use the "/*verilator sc_bv*/" attribute to select specific ports to be sc_bv.

--pins-sc-uint

Specifies SystemC inputs/outputs of greater than 2 bits wide should use sc_uint between 2 and 64. When combined with the "--pins-sc-biguint" combination, it results in sc_uint being used between 2 and 64 and sc_biguint being used between 65 and 512.

--pins-sc-biguint

Specifies SystemC inputs/outputs of greater than 65 bits wide should use sc_biguint between 65 and 512, and sc_bv from 513 upwards. When combined with the "--pins-sc-uint" combination, it results in sc_uint being used between 2 and 64 and sc_biguint being used between 65 and 512.

--pins-uint8

Specifies SystemC inputs/outputs that are smaller than the --pins-bv setting and 8 bits or less should use uint8_t instead of uint32_t. Likewise pins of width 9-16 will use uint16_t instead of uint32_t.

--pipe-filter command

Rarely needed. Verilator will spawn the specified command as a subprocess pipe, to allow the command to perform custom edits on the Verilog code before it reaches Verilator.

Before reading each Verilog file, Verilator will pass the file name to the subprocess' stdin with 'read "<filename>"'. The filter may then read the file and perform any filtering it desires, and feeds the new file contents back to Verilator on stdout by first emitting a line defining the length in bytes of the filtered output 'Content-Length: <bytes>', followed by the new filtered contents. Output to stderr from the filter feeds through to Verilator's stdout and if the filter exits with non-zero status Verilator terminates. See the t/t_pipe_filter test for an example.

To debug the output of the filter, try using the -E option to see preprocessed output.

--pp-comments

With -E, show comments in preprocessor output.

--prefix topname

Specifies the name of the top level class and makefile. Defaults to V prepended to the name of the --top-module switch, or V prepended to the first Verilog filename passed on the command line.

--prof-cfuncs

Modify the created C++ functions to support profiling. The functions will be minimized to contain one "basic" statement, generally a single always block or wire statement. (Note this will slow down the executable by ~5%.) Furthermore, the function name will be suffixed with the basename of the Verilog module and line number the statement came from. This allows gprof or oprofile reports to be correlated with the original Verilog source statements. See also verilator_profcfunc.

--prof-threads

Enable gantt chart data collection for threaded builds.

Verilator will record the start and end time of each macro-task across a number of calls to eval. (What is a macro-task? See the Verilator internals document.)

When profiling is enabled, the simulation runtime will emit a blurb of profiling data in non-human-friendly form. The verilator_gantt script will transform this into a nicer visual format and produce some related statistics.

--protect-key key

Specifies the private key for --protect-ids. For best security this key should be 16 or more random bytes, a reasonable secure choice is the output of verilator --generate-key. Typically, a key would be created by the user once for a given protected design library, then every Verilator run for subsequent versions of that library would be passed the same --protect-key. Thus, if the input Verilog is similar between library versions (Verilator runs), the Verilated code will likewise be mostly similar.

If --protect-key is not specified and a key is needed, Verilator will generate a new key for every Verilator run. As the key is not saved, this is best for security, but means every Verilator run will give vastly different output even for identical input, perhaps harming compile times (and certainly thrashing any ccache).

--protect-ids

Hash any private identifiers (variable, module, and assertion block names that are not on the top level) into hashed random-looking identifiers, resulting after compilation in protected library binaries that expose less design information. This hashing uses the provided or default --protect-key, see important details there.

Verilator will also create a {prefix}__idmap.xml file which contains the mapping from the hashed identifiers back to the original identifiers. This idmap file is to be kept private, and is to assist mapping any simulation runtime design assertions, coverage, or trace information, which will report the hashed identifiers, back to the original design's identifier names.

Using DPI imports/exports is allowed and generally relatively safe in terms of information disclosed, which is limited to the DPI function prototyptes. Use of the VPI is not recommended as many design details may be exposed, and an INSECURE warning will be issued.

--protect-lib name

Produces C++, Verilog wrappers and a Makefile which can in turn produce a DPI library which can be used by Verilator or other simulators along with the corresponding Verilog wrapper. The Makefile will build both a static and dynamic version of the library named libname.a and libname.so respectively. This is done because some simulators require a dynamic library, but the static library is arguably easier to use if possible. --protect-lib implies --protect-ids.

This allows for the secure delivery of sensitive IP without the need for encrypted RTL (i.e. IEEE P1735). See examples/make_protect_lib in the distribution for a demonstration of how to build and use the DPI library.

When using --protect-lib it is advised to also use --timescale-override /1fs to ensure the model has a time resolution that is always compatible with the time precision of the upper instantiating module.

--private

Opposite of --public. Is the default; this option exists for backwards compatibility.

--public

This is only for historical debug use. Using it may result in mis-simulation of generated clocks.

Declares all signals and modules public. This will turn off signal optimizations as if all signals had a /*verilator public*/ comments and inlining. This will also turn off inlining as if all modules had a /*verilator public_module*/, unless the module specifically enabled it with /*verilator inline_module*/.

--public-flat-rw

Declares all variables, ports and wires public as if they had /*verilator public_flat_rw @ (<variable's_source_process_edge>)*/ comments. This will make them VPI accessible by their flat name, but not turn off module inlining. This is particularly useful in combination with --vpi. This may also in some rare cases result in mis-simulation of generated clocks. Instead of this global switch, marking only those signals that need public_flat_rw is typically significantly better performing.

-pvalue+name=value

Overwrites the given parameter(s) of the toplevel module. See -G for a detailed description.

--quiet-exit

When exiting due to an error, do not display the "Exiting due to Errors" nor "Command Failed" messages.

--relative-includes

When a file references an include file, resolve the filename relative to the path of the referencing file, instead of relative to the current directory.

--report-unoptflat

Extra diagnostics for UNOPTFLAT warnings. This includes for each loop, the 10 widest variables in the loop, and the 10 most fanned out variables in the loop. These are candidates for splitting into multiple variables to break the loop.

In addition produces a GraphViz DOT file of the entire strongly connected components within the source associated with each loop. This is produced irrespective of whether --dump-tree is set. Such graphs may help in analyzing the problem, but can be very large indeed.

Various commands exist for viewing and manipulating DOT files. For example the dot command can be used to convert a DOT file to a PDF for printing. For example:

    dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot

will generate a PDF Vt_unoptflat_simple_2_35_unoptflat.dot.pdf from the DOT file.

As an alternative, the xdot command can be used to view DOT files interactively:

    xdot Vt_unoptflat_simple_2_35_unoptflat.dot
--rr

Run Verilator and record with rr. See: rr-project.org.

--savable

Enable including save and restore functions in the generated model.

The user code must create a VerilatedSerialize or VerilatedDeserialze object then calling the << or >> operators on the generated model and any other data the process needs saved/restored. These functions are not thread safe, and are typically called only by a main thread.

For example:

    void save_model(const char* filenamep) {
        VerilatedSave os;
        os.open(filenamep);
        os << main_time;  // user code must save the timestamp, etc
        os << *topp;
    }
    void restore_model(const char* filenamep) {
        VerilatedRestore os;
        os.open(filenamep);
        os >> main_time;
        os >> *topp;
    }
--sc

Specifies SystemC output mode; see also --cc.

--stats

Creates a dump file with statistics on the design in {prefix}__stats.txt.

--stats-vars

Creates more detailed statistics, including a list of all the variables by size (plain --stats just gives a count). See --stats, which is implied by this.

--structs-packed

Converts all unpacked structures to packed structures and issues a UNPACKED warning. Currently this is the default and --no-structs-packed will not work. Specifying this option allows for forward compatibility when a future version of Verilator no longer always packs unpacked structures.

-sv

Specifies SystemVerilog language features should be enabled; equivalent to "--language 1800-2005". This option is selected by default, it exists for compatibility with other simulators.

+systemverilogext+ext

A synonym for +1800-2017ext+ext.

--threads threads
--no-threads

With --threads 0 or --no-threads, the default, the generated model is not thread safe. With --threads 1, the generated model is single threaded but may run in a multithreaded environment. With --threads N, where N >= 2, the model is generated to run multithreaded on up to N threads. See "MULTITHREADING".

--threads-dpi all
--threads-dpi none
--threads-dpi pure

When using --threads, controls which DPI imported tasks and functions are considered thread safe.

With --threads-dpi all, enable Verilator to assume all DPI imports are threadsafe, and to use thread-local storage for communication with DPI, potentially improving performance. Any DPI libraries need appropriate mutexes to avoid undefined behavior.

With --threads-dpi none, Verilator assume DPI imports are not thread safe, and Verilator will serialize calls to DPI imports by default, potentially harming performance.

With --threads-dpi pure, the default, Verilator assumes DPI pure imports are threadsafe, but non-pure DPI imports are not.

--threads-max-mtasks value

Rarely needed. When using --threads, specify the number of mtasks the model is to be partitioned into. If unspecified, Verilator approximates a good value.

--timescale timeunit/timeprecision

Sets default timescale, timeunit and timeprecision for when `timescale does not occur in sources. Default is "1ps/1ps" (to match SystemC). This is overridden by --timescale-override.

--timescale-override timeunit/timeprecision
--timescale-override /timeprecision

Overrides all `timescales in sources. The timeunit may be left empty to specify only to override the timeprecision, e.g. "/1fs".

The time precision must be consistent with SystemC's sc_set_time_resolution, or the C++ code instantiating the Verilated module. As 1fs is the finest time precision it may be desirable to always use a precision of 1fs.

--top-module topname

When the input Verilog contains more than one top level module, specifies the name of the Verilog module to become the top level module, and sets the default for --prefix if not explicitly specified. This is not needed with standard designs with only one top. See also the MULTITOP warning section.

--trace

Adds waveform tracing code to the model using VCD format. This overrides --trace-fst.

Verilator will generate additional {prefix}__Trace*.cpp files that will need to be compiled. In addition verilated_vcd_sc.cpp (for SystemC traces) or verilated_vcd_c.cpp (for both) must be compiled and linked in. If using the Verilator generated Makefiles, these files will be added to the source file lists for you. If you are not using the Verilator Makefiles, you will need to add these to your Makefile manually.

Having tracing compiled in may result in some small performance losses, even when tracing is not turned on during model execution.

See also --trace-threads.

--trace-coverage

With --trace and --coverage-*, enable tracing to include a traced signal for every --coverage-line or --coverage-user inserted coverage point, to assist in debugging coverage items. Note --coverage-toggle does not get additional signals added, as the original signals being toggle-analyzed are already visible.

The added signal will be a 32-bit value which will increment on each coverage occurrence. Due to this, this option may greatly increase trace file sizes and reduce simulation speed.

--trace-depth levels

Specify the number of levels deep to enable tracing, for example --trace-level 1 to only see the top level's signals. Defaults to the entire model. Using a small number will decrease visibility, but greatly improve simulation performance and trace file size.

--trace-fst

Enable FST waveform tracing in the model. This overrides --trace. See also --trace-threads.

--trace-max-array depth

Rarely needed. Specify the maximum array depth of a signal that may be traced. Defaults to 32, as tracing large arrays may greatly slow traced simulations.

--trace-max-width width

Rarely needed. Specify the maximum bit width of a signal that may be traced. Defaults to 256, as tracing large vectors may greatly slow traced simulations.

--no-trace-params

Disable tracing of parameters.

--trace-structs

Enable tracing to show the name of packed structure, union, and packed array fields, rather than a single combined packed bus. Due to VCD file format constraints this may result in significantly slower trace times and larger trace files.

--trace-threads threads

Enable waveform tracing using separate threads. This is typically faster in simulation runtime but uses more total compute. This option is independent of, and works with, both --trace and --trace-fst. Different trace formats can take advantage of more trace threads to varying degrees. Currently VCD tracing can utilize at most --trace-threads 1, and FST tracing can utilize at most --trace-threads 2. This overrides --no-threads.

--trace-underscore

Enable tracing of signals that start with an underscore. Normally, these signals are not output during tracing. See also --coverage-underscore.

-Uvar

Undefines the given preprocessor symbol.

--unroll-count loops

Rarely needed. Specifies the maximum number of loop iterations that may be unrolled. See also BLKLOOPINIT warning.

--unroll-stmts statements

Rarely needed. Specifies the maximum number of statements in a loop for that loop to be unrolled. See also BLKLOOPINIT warning.

--unused-regexp regexp

Rarely needed. Specifies a simple regexp with * and ? that if a signal name matches will suppress the UNUSED warning. Defaults to "*unused*". Setting it to "" disables matching.

-V

Shows the verbose version, including configuration information compiled into Verilator. (Similar to perl -V.) See also --getenv.

-v filename

Read the filename as a Verilog library. Any modules in the file may be used to resolve cell instantiations in the top level module, else ignored. Note -v is fairly standard across Verilog tools.

--no-verilate

When using --build, disable generation of C++/SystemC code, and execute only the build. This can be useful for rebuilding Verilated code produced by a previous invocation of Verilator.

+verilog1995ext+ext
+verilog2001ext+ext

Synonyms for +1364-1995ext+ext and +1364-2001ext+ext respectively

--version

Displays program version and exits.

--vpi

Enable use of VPI and linking against the verilated_vpi.cpp files.

--waiver-output <filename>

Generate a waiver file which contains all waiver statements to suppress the warnings emitted during this Verilator run. This in particular is useful as a starting point for solving linter warnings or suppressing them systematically.

The generated file is in the Verilator Configuration format, see "CONFIGURATION FILES", and can directly be consumed by Verilator. The standard file extension is .vlt.

-Wall

Enable all code style warnings, including code style warnings that are normally disabled by default. Equivalent to "-Wwarn-lint -Wwarn-style". Excludes some specialty warnings, i.e. IMPERFECTSCH.

-Werror-message

Promote the specified warning message into an error message. This is generally to discourage users from violating important site-wide rules, for example -Werror-NOUNOPTFLAT.

-Wfuture-message

Rarely needed. Suppress unknown Verilator comments or warning messages with the given message code. This is used to allow code written with pragmas for a later version of Verilator to run under a older version; add -Wfuture- arguments for each message code or comment that the new version supports which the older version does not support.

-Wno-message

Disable the specified warning/error message. This will override any lint_on directives in the source, i.e. the warning will still not be printed.

-Wno-context

Disable showing the suspected context of the warning message by quoting the source text at the suspected location. This can be used to appease tools which process the warning messages but may get confused by lines from the original source.

-Wno-fatal

When warnings are detected, print them, but do not terminate Verilator.

Having warning messages in builds is sloppy. It is strongly recommended you cleanup your code, use inline lint_off, or use -Wno-... flags rather than using this option.

-Wno-lint

Disable all lint related warning messages, and all style warnings. This is equivalent to "-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED -Wno-WIDTH" plus the list shown for Wno-style.

It is strongly recommended you cleanup your code rather than using this option, it is only intended to be use when running test-cases of code received from third parties.

-Wno-style

Disable all code style related warning messages (note by default they are already disabled). This is equivalent to "-Wno-DECLFILENAME -Wno-DEFPARAM -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY -Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED -Wno-VARHIDDEN".

-Wpedantic

Warn on any construct demanded by IEEE, and disable all Verilator extensions that may interfere with IEEE compliance to the standard defined with --default-language (etc). Similar to GCC's -Wpedantic. Rarely used, and intended only for strict compliance tests.

-Wwarn-message

Enables the specified warning message.

-Wwarn-lint

Enable all lint related warning messages (note by default they are already enabled), but do not affect style messages. This is equivalent to "-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASEWITHX -Wwarn-CMPCONST -Wwarn-COLONPLUS -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN -Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH".

-Wwarn-style

Enable all code style related warning messages. This is equivalent to "-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN -Wwarn-UNUSED -Wwarn-VARHIDDEN".

--x-assign 0
--x-assign 1
--x-assign fast (default)
--x-assign unique

Controls the two-state value that is substituted when an explicit X value is encountered in the source. --x-assign fast, the default, converts all Xs to whatever is best for performance. --x-assign 0 converts all Xs to 0s, and is also fast. --x-assign 1 converts all Xs to 1s, this is nearly as fast as 0, but more likely to find reset bugs as active high logic will fire. Using --x-assign unique will result in all explicit Xs being replaced by a constant value determined at runtime. The value is determined by calling a function at initialization time. This enables randomization of Xs with different seeds on different executions. This method is the slowest, but safest for finding reset bugs.

If using --x-assign unique, you may want to seed your random number generator such that each regression run gets a different randomization sequence. The simplest is to use the +verilator+seed runtime option. Alternatively use the system's srand48() or for Windows srand() function to do this. You'll probably also want to print any seeds selected, and code to enable rerunning with that same seed so you can reproduce bugs.

Note. This option applies only to values which are explicitly written as X in the Verilog source code. Initial values of clocks are set to 0 unless --x-initial-edge is specified. Initial values of all other state holding variables are controlled with --x-initial.

--x-initial 0
--x-initial fast
--x-initial unique (default)

Controls the two-state value that is used to initialize variables that are not otherwise initialized.

--x-initial 0, initializes all otherwise uninitialized variables to zero.

--x-initial unique, the default, initializes variables using a function, which determines the value to use each initialization. This gives greatest flexibility and allows finding reset bugs. See "Unknown states".

--x-initial fast, is best for performance, and initializes all variables to a state Verilator determines is optimal. This may allow further code optimizations, but will likely hide any code bugs relating to missing resets.

Note. This option applies only to initial values of variables. Initial values of clocks are set to 0 unless --x-initial-edge is specified.

--x-initial-edge

Enables emulation of event driven simulators which generally trigger an edge on a transition from X to 1 (posedge) or X to 0 (negedge). Thus the following code, where rst_n is uninitialized would set res_n to 1'b1 when rst_n is first set to zero:

    reg  res_n = 1'b0;

    always @(negedge rst_n) begin
       if (rst_n == 1'b0) begin
          res_n <= 1'b1;
       end
    end

In Verilator, by default, uninitialized clocks are given a value of zero, so the above always block would not trigger.

While it is not good practice, there are some designs that rely on X → 0 triggering a negedge, particularly in reset sequences. Using --x-initial-edge with Verilator will replicate this behavior. It will also ensure that X → 1 triggers a posedge.

Note. Some users have reported that using this option can affect convergence, and that it may be necessary to use --converge-limit to increase the number of convergence iterations. This may be another indication of problems with the modeled design that should be addressed.

--xml-only

Create XML output only, do not create any other output.

The XML format is intended to be used to leverage Verilator's parser and elaboration to feed to other downstream tools. Be aware that the XML format is still evolving; there will be some changes in future versions.

--xml-output filename

Filename for XML output file. Using this option automatically sets --xml-only.

-y dir

Add the directory to the list of directories that should be searched for include files or libraries. The three flags -y, +incdir and -I have similar effect; +incdir and +y are fairly standard across Verilog tools while -I is used by many C++ compilers.

Verilator defaults to the current directory ("-y .") and any specified --Mdir, though these default paths are used after any user specified directories. This allows '-y "$(pwd)"' to be used if absolute filenames are desired for error messages instead of relative filenames.

SIMULATION RUNTIME ARGUMENTS

The following are the arguments that may be passed to a Verilated executable, provided that executable calls Verilated::commandArgs().

All simulation runtime arguments begin with +verilator, so that the user's executable may skip over all +verilator arguments when parsing its command line.

+verilator+debug

Enable simulation runtime debugging. Equivalent to +verilator+debugi+4.

+verilator+debugi+value

Enable simulation runtime debugging at the provided level.

+verilator+error+limit+value

Set number of non-fatal errors (e.g. assertion failures) before exiting simulation runtime. Also affects number of $stop calls needed before exit. Defaults to 1.

+verilator+help

Display help and exit.

+verilator+prof+threads+file+filename

When a model was Verilated using --prof-threads, sets the simulation runtime filename to dump to. Defaults to "profile_threads.dat".

+verilator+prof+threads+start+value

When a model was Verilated using --prof-threads, the simulation runtime will wait until $time is at this value (expressed in units of the time precision), then start the profiling warmup, then capturing. Generally this should be set to some time that is well within the normal operation of the simulation, i.e. outside of reset. If 0, the dump is disabled. Defaults to 1.

+verilator+prof+threads+window+value

When a model was Verilated using --prof-threads, after $time reaches +verilator+prof+threads+start, Verilator will warm up the profiling for this number of eval() calls, then will capture the profiling of this number of eval() calls. Defaults to 2, which makes sense for a single-clock-domain module where it's typical to want to capture one posedge eval() and one negedge eval().

+verilator+rand+reset+value

When a model was Verilated using "-x-initial unique", sets the simulation runtime initialization technique. 0 = Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See "Unknown states".

+verilator+seed+value

For $random and "-x-initial unique", set the simulation runtime random seed value. If zero or not specified picks a value from the system random number generator.

+verilator+noassert

Disable assert checking per runtime argument. This is the same as calling "Verilated::assertOn(false)" in the model.

+verilator+V

Shows the verbose version, including configuration information.

+verilator+version

Displays program version and exits.

EXAMPLE C++ EXECUTION

We'll compile this example into C++.

    mkdir test_our
    cd test_our

    cat >our.v <<'EOF'
      module our;
         initial begin $display("Hello World"); $finish; end
      endmodule
    EOF

    cat >sim_main.cpp <<'EOF'
      #include "Vour.h"
      #include "verilated.h"
      int main(int argc, char** argv, char** env) {
          Verilated::commandArgs(argc, argv);
          Vour* top = new Vour;
          while (!Verilated::gotFinish()) { top->eval(); }
          delete top;
          exit(0);
      }
    EOF

See the README in the source kit for various ways to install or point to Verilator binaries. In brief, if you installed Verilator using the package manager of your operating system, or did a "make install" to place Verilator into your default path, you do not need anything special in your environment, and should not have VERILATOR_ROOT set. However, if you installed Verilator from sources and want to run Verilator out of where you compiled Verilator, you need to point to the kit:

    # See above; don't do this if using an OS-distributed Verilator
    export VERILATOR_ROOT=/path/to/where/verilator/was/installed
    export PATH=$VERILATOR_ROOT/bin:$PATH

Now we run Verilator on our little example.

    verilator -Wall --cc our.v --exe --build sim_main.cpp

We can see the source code under the "obj_dir" directory. See the FILES section below for descriptions of some of the files that were created.

    ls -l obj_dir

(Verilator included a default compile rule and link rule, since we used --exe and passed a .cpp file on the Verilator command line. Verilator also then used make to build a final executable. You can also write your own compile rules, and run make yourself as we'll show in the SYSTEMC section.)

And now we run it

    obj_dir/Vour

And we get as output

    Hello World
    - our.v:2: Verilog $finish

Really, you're better off writing a Makefile to do all this for you. Then, when your source changes it will automatically run all of these steps; to aid this Verilator can create a makefile dependency file. See the examples directory in the distribution.

EXAMPLE SYSTEMC EXECUTION

This is an example similar to the above, but using SystemC.

    mkdir test_our_sc
    cd test_our_sc

    cat >our.v <<'EOF'
      module our (clk);
         input clk;  // Clock is required to get initial activation
         always @ (posedge clk)
            begin $display("Hello World"); $finish; end
      endmodule
    EOF

    cat >sc_main.cpp <<'EOF'
      #include "Vour.h"
      int sc_main(int argc, char** argv) {
          Verilated::commandArgs(argc, argv);
          sc_clock clk ("clk", 10, 0.5, 3, true);
          Vour* top;
          top = new Vour("top");
          top->clk(clk);
          while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
          delete top;
          exit(0);
      }
    EOF

See the README in the source kit for various ways to install or point to Verilator binaries. In brief, if you installed Verilator using the package manager of your operating system, or did a "make install" to place Verilator into your default path, you do not need anything special in your environment, and should not have VERILATOR_ROOT set. However, if you installed Verilator from sources and want to run Verilator out of where you compiled Verilator, you need to point to the kit:

    # See above; don't do this if using an OS-distributed Verilator
    export VERILATOR_ROOT=/path/to/where/verilator/was/installed
    export PATH=$VERILATOR_ROOT/bin:$PATH

Now we run Verilator on our little example.

    verilator -Wall --sc our.v

We then can compile it

    make -j -C obj_dir -f Vour.mk Vour__ALL.a
    make -j -C obj_dir -f Vour.mk ../sc_main.o verilated.o

And link with SystemC. Note your path to the libraries may vary, depending on the operating system.

    cd obj_dir
    export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists
    export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH
    # Might be needed if SystemC 2.3.0
    export SYSTEMC_CXX_FLAGS=-pthread

    g++ -L$SYSTEMC_LIBDIR ../sc_main.o Vour__ALL.a verilated.o \
              -o Vour -lsystemc

And now we run it

    cd ..
    obj_dir/Vour

And we get the same output as the C++ example:

    Hello World
    - our.v:2: Verilog $finish

Really, you're better off using a Makefile to do all this for you. Then, when your source changes it will automatically run all of these steps. See the examples directory in the distribution.

EVALUATION LOOP

When using SystemC, evaluation of the Verilated model is managed by the SystemC kernel, and for the most part can be ignored. When using C++, the user must call eval(), or eval_step() and eval_end_step().

1. When there is a single design instantiated at the C++ level that needs to evaluate, just call designp->eval().

2. When there are multiple designs instantiated at the C++ level that need to evaluate, call first_designp->eval_step() then ->eval_step() on all other designs. Then call ->eval_end_step() on the first design then all other designs. If there is only a single design, you would call eval_step() then eval_end_step(); in fact eval() described above is just a wrapper which calls these two functions.

When eval() is called Verilator looks for changes in clock signals and evaluates related sequential always blocks, such as computing always_ff @ (posedge...) outputs. Then Verilator evaluates combinatorial logic.

Note combinatorial logic is not computed before sequential always blocks are computed (for speed reasons). Therefore it is best to set any non-clock inputs up with a separate eval() call before changing clocks.

Alternatively, if all always_ff statements use only the posedge of clocks, or all inputs go directly to always_ff statements, as is typical, then you can change non-clock inputs on the negative edge of the input clock, which will be faster as there will be fewer eval() calls.

For more information on evaluation, see docs/internals.adoc in the distribution.

BENCHMARKING & OPTIMIZATION

For best performance, run Verilator with the "-O3 --x-assign fast --x-initial fast --noassert" flags. The -O3 flag will require longer time to run Verilator, and "--x-assign fast --x-initial fast" may increase the risk of reset bugs in trade for performance; see the above documentation for these flags.

If using Verilated multithreaded, use numactl to ensure you are using non-conflicting hardware resources. See "MULTITHREADING".

Minor Verilog code changes can also give big wins. You should not have any UNOPTFLAT warnings from Verilator. Fixing these warnings can result in huge improvements; one user fixed their one UNOPTFLAT warning by making a simple change to a clock latch used to gate clocks and gained a 60% performance improvement.

Beyond that, the performance of a Verilated model depends mostly on your C++ compiler and size of your CPU's caches. Experience shows that large models are often limited by the size of the instruction cache, and as such reducing code size if possible can be beneficial.

The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT, OPT_FAST, OPT_SLOW and OPT_GLOBAL variables to control optimization. You can set these when compiling the output of Verilator with Make, for example:

    make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a

OPT_FAST specifies optimization flags for those parts of the model that are on the fast path. This is mostly code that is executed every cycle. OPT_SLOW applies to slow-path code, which executes rarely, often only once at the beginning or end of simulation. Note that OPT_SLOW is ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code will be compiled in a single compilation unit using OPT_FAST. See also the --output-split option. The OPT_GLOBAL variable applies to common code in the runtime library used by Verilated models (shipped in $VERILATOR_ROOT/include). Additional C++ files passed on the verilator command line use OPT_FAST. The OPT variable applies to all compilation units in addition to the specific OPT_* variables described above.

You can also use the -CFLAGS and/or -LDFLAGS options on the verilator command line to pass flags directly to the compiler or linker.

The default values of the OPT_* variables are chosen to yield good simulation speed with reasonable C++ compilation times. To this end, OPT_FAST is set to "-Os" by default. Higher optimization such as "-O2" or "-O3" may help (though often they provide only a very small performance benefit), but compile times may be excessively large even with medium sized designs. Compilation times can be improved at the expense of simulation speed by reducing optimization, for example with OPT_FAST="-O0". Often good simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing" but with improved compilation times. Files controlled by OPT_SLOW have little effect on performance and therefore OPT_SLOW is empty by default (equivalent to "-O0") for improved compilation speed. In common use-cases there should be little benefit in changing OPT_SLOW. OPT_GLOBAL is set to "-Os" by default and there should rarely be a need to change it. As the runtime library is small in comparison to a lot of Verilated models, disabling optimization on the runtime library should not have a serious effect on overall compilation time, but may have detrimental effect on simulation speed, especially with tracing. In addition to the above, for best results use OPT="-march=native", the latest Clang compiler (about 10% faster than GCC), and link statically.

Generally the answer to which optimization level gives the best user experience depends on the use case and some experimentation can pay dividends. For a speedy debug cycle during development, especially on large designs where C++ compilation speed can dominate, consider using lower optimization to get to an executable faster. For throughput oriented use cases, for example regressions, it is usually worth spending extra compilation time to reduce total CPU time.

If you will be running many simulations on a single model, you can investigate profile guided optimization. With GCC, using -fprofile-arcs, then -fbranch-probabilities will yield another 15% or so.

Modern compilers also support link-time optimization (LTO), which can help especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in both compilation and link. Note LTO may cause excessive compile times on large designs.

Unfortunately, using the optimizer with SystemC files can result in compilation taking several minutes. (The SystemC libraries have many little inlined functions that drive the compiler nuts.)

If you are using your own makefiles, you may want to compile the Verilated code with -DVL_INLINE_OPT=inline. This will inline functions, however this requires that all cpp files be compiled in a single compiler run.

You may uncover further tuning possibilities by profiling the Verilog code. Use Verilator's --prof-cfuncs, then GCC's -g -pg. You can then run either oprofile or gprof to see where in the C++ code the time is spent. Run the gprof output through verilator_profcfunc and it will tell you what Verilog line numbers on which most of the time is being spent.

When done, please let the author know the results. We like to keep tabs on how Verilator compares, and may be able to suggest additional improvements.

FILES

All output files are placed in the output directory specified with the --Mdir option, or "obj_dir" if not specified.

Verilator creates the following files in the output directory:

For --make gmake, it creates:

    {prefix}.mk                         // Make include file for compiling
    {prefix}_classes.mk                 // Make include file with class names

For --make cmake, it creates:

    {prefix}.cmake                      // CMake include script for compiling

For -cc and -sc mode, it also creates:

    {prefix}.cpp                        // Top level C++ file
    {prefix}.h                          // Top level header
    {prefix}__Slow{__n}.cpp             // Constructors and infrequent cold routines
    {prefix}{__n}.cpp                   // Additional top C++ files (--output-split)
    {prefix}{each_verilog_module}.cpp   // Lower level internal C++ files
    {prefix}{each_verilog_module}.h     // Lower level internal header files
    {prefix}{each_verilog_module}{__n}.cpp   // Additional lower C++ files (--output-split)

In certain debug and other modes, it also creates:

    {prefix}.xml                        // XML tree information (--xml)
    {prefix}__Dpi.cpp                   // DPI import and export wrappers
    {prefix}__Dpi.h                     // DPI import and export declarations
    {prefix}__Inlines.h                 // Inline support functions
    {prefix}__Syms.cpp                  // Global symbol table C++
    {prefix}__Syms.h                    // Global symbol table header
    {prefix}__Trace__Slow{__n}.cpp      // Wave file generation code (--trace)
    {prefix}__Trace{__n}.cpp            // Wave file generation code (--trace)
    {prefix}__cdc.txt                   // Clock Domain Crossing checks (--cdc)
    {prefix}__stats.txt                 // Statistics (--stats)
    {prefix}__idmap.txt                 // Symbol demangling (--protect-ids)

It also creates internal files that can be mostly ignored:

    {mod_prefix}_{each_verilog_module}{__n}.vpp  // Pre-processed verilog
    {prefix}__ver.d                     // Make dependencies (-MMD)
    {prefix}__verFiles.dat              // Timestamps for skip-identical
    {prefix}{misc}.dot                  // Debugging graph files (--debug)
    {prefix}{misc}.tree                 // Debugging files (--debug)

After running Make, the C++ compiler may produce the following:

    verilated{misc}.d                   // Intermediate dependencies
    verilated{misc}.o                   // Intermediate objects
    {mod_prefix}{misc}.d                // Intermediate dependencies
    {mod_prefix}{misc}.o                // Intermediate objects
    {prefix}                            // Final executable (w/--exe argument)
    {prefix}__ALL.a                     // Library of all Verilated objects
    {prefix}__ALL.cpp                   // Include of all code for single compile
    {prefix}{misc}.d                    // Intermediate dependencies
    {prefix}{misc}.o                    // Intermediate objects

ENVIRONMENT

LD_LIBRARY_PATH

A generic Linux/OS variable specifying what directories have shared object (.so) files. This path should include SystemC and any other shared objects needed at simulation runtime.

MAKE

Names the executable of the make command invoked when using the --build option. Some operating systems may require "gmake" to this variable to launch GNU make. If this variable is not specified, "make" is used.

OBJCACHE

Optionally specifies a caching or distribution program to place in front of all runs of the C++ compiler. For example, "ccache". If using distcc or icecc/icecream, they would generally be run under cache; see the documentation for those programs. If OBJCACHE is not set, and at configure time ccache was present, ccache will be used as a default.

SYSTEMC

Deprecated. Used only if SYSTEMC_INCLUDE or SYSTEMC_LIBDIR is not set. If set, specifies the directory containing the SystemC distribution. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled).

SYSTEMC_ARCH

Deprecated. Used only if SYSTEMC_LIBDIR is not set. Specifies the architecture name used by the SystemC kit. This is the part after the dash in the lib-{...} directory name created by a 'make' in the SystemC distribution. If not set, Verilator will try to intuit the proper setting, or use the default optionally specified at configure time (before Verilator was compiled).

SYSTEMC_CXX_FLAGS

Specifies additional flags that are required to be passed to GCC when building the SystemC model. System 2.3.0 may need this set to "-pthread".

SYSTEMC_INCLUDE

If set, specifies the directory containing the systemc.h header file. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled), or computed from SYSTEMC/include.

SYSTEMC_LIBDIR

If set, specifies the directory containing the libsystemc.a library. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled), or computed from SYSTEMC/lib-SYSTEMC_ARCH.

VERILATOR_BIN

If set, specifies an alternative name of the verilator binary. May be used for debugging and selecting between multiple operating system builds.

VERILATOR_COVERAGE_BIN

If set, specifies an alternative name of the verilator_coverage binary. May be used for debugging and selecting between multiple operating system builds.

VERILATOR_GDB

If set, the command to run when using the --gdb option, such as "ddd". If not specified, it will use "gdb".

VERILATOR_ROOT

Specifies the directory containing the distribution kit. This is used to find the executable, Perl library, and include files. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled). It should not be specified if using a pre-compiled Verilator package as the hard-coded value should be correct.

CONNECTING TO C++

Verilator creates a prefix.h and prefix.cpp file for the top level module, together with additional .h and .cpp files for internals. See the examples directory in the kit for examples.

After the model is created, there will be a prefix.mk file that may be used with Make to produce a prefix__ALL.a file with all required objects in it. This is then linked with the user's C++ main loop to create the simulation executable.

The user must write the C++ main loop of the simulation. Here is a simple example:

        #include <verilated.h>          // Defines common routines
        #include <iostream>             // Need std::cout
        #include "Vtop.h"               // From Verilating "top.v"

        Vtop *top;                      // Instantiation of module

        vluint64_t main_time = 0;       // Current simulation time
        // This is a 64-bit integer to reduce wrap over issues and
        // allow modulus.  This is in units of the timeprecision
        // used in Verilog (or from --timescale-override)

        double sc_time_stamp () {       // Called by $time in Verilog
            return main_time;           // converts to double, to match
                                        // what SystemC does
        }

        int main(int argc, char** argv) {
            Verilated::commandArgs(argc, argv);   // Remember args

            top = new Vtop;             // Create instance

            top->reset_l = 0;           // Set some inputs

            while (!Verilated::gotFinish()) {
                if (main_time > 10) {
                    top->reset_l = 1;   // Deassert reset
                }
                if ((main_time % 10) == 1) {
                    top->clk = 1;       // Toggle clock
                }
                if ((main_time % 10) == 6) {
                    top->clk = 0;
                }
                top->eval();            // Evaluate model
                cout << top->out << endl;       // Read a output
                main_time++;            // Time passes...
            }

            top->final();               // Done simulating
            //    // (Though this example doesn't get here)
            delete top;
        }

Note signals are read and written as member variables of the model. You call the eval() method to evaluate the model. When the simulation is complete call the final() method to execute any SystemVerilog final blocks, and complete any assertions. See "EVALUATION LOOP".

CONNECTING TO SYSTEMC

Verilator will convert the top level module to a SC_MODULE. This module will plug directly into a SystemC netlist.

The SC_MODULE gets the same pinout as the Verilog module, with the following type conversions: Pins of a single bit become bool. Pins 2-32 bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or vluint64_t's depending on the --no-pins64 switch. Wider pins become sc_bv's. (Uints simulate the fastest so are used where possible.)

Lower modules are not pure SystemC code. This is a feature, as using the SystemC pin interconnect scheme everywhere would reduce performance by an order of magnitude.

DIRECT PROGRAMMING INTERFACE (DPI)

Verilator supports SystemVerilog Direct Programming Interface import and export statements. Only the SystemVerilog form ("DPI-C") is supported, not the original Synopsys-only DPI.

DPI Example

In the SYSTEMC example above, if you wanted to import C++ functions into Verilog, put in our.v:

   import "DPI-C" function int add (input int a, input int b);

   initial begin
      $display("%x + %x = %x", 1, 2, add(1,2));
   endtask

Then after Verilating, Verilator will create a file Vour__Dpi.h with the prototype to call this function:

    extern int add (int a, int b);

From the sc_main.cpp file (or another .cpp file passed to the Verilator command line, or the link), you'd then:

    #include "svdpi.h"
    #include "Vour__Dpi.h"
    int add(int a, int b) { return a+b; }

DPI System Task/Functions

Verilator extends the DPI format to allow using the same scheme to efficiently add system functions. Simply use a dollar-sign prefixed system function name for the import, but note it must be escaped.

   export "DPI-C" function integer \$myRand;

   initial $display("myRand=%d", $myRand());

Going the other direction, you can export Verilog tasks so they can be called from C++:

   export "DPI-C" task publicSetBool;

   task publicSetBool;
      input bit in_bool;
      var_bool = in_bool;
   endtask

Then after Verilating, Verilator will create a file Vour__Dpi.h with the prototype to call this function:

    extern void publicSetBool(svBit in_bool);

From the sc_main.cpp file, you'd then:

    #include "Vour__Dpi.h"
    publicSetBool(value);

Or, alternatively, call the function under the design class. This isn't DPI compatible but is easier to read and better supports multiple designs.

    #include "Vour__Dpi.h"
    Vour::publicSetBool(value);
    // or top->publicSetBool(value);

Note that if the DPI task or function accesses any register or net within the RTL, it will require a scope to be set. This can be done using the standard functions within svdpi.h, after the module is instantiated, but before the task(s) and/or function(s) are called.

For example, if the top level module is instantiated with the name "dut" and the name references within tasks are all hierarchical (dotted) names with respect to that top level module, then the scope could be set with

    #include "svdpi.h"
    ...
    svSetScope(svGetScopeFromName("TOP.dut"));

(Remember that Verilator adds a "TOP" to the top of the module hierarchy.)

Scope can also be set from within a DPI imported C function that has been called from Verilog by querying the scope of that function. See the sections on DPI Context Functions and DPI Header Isolation below and the comments within the svdpi.h header for more information.

DPI Display Functions

Verilator allows writing $display like functions using this syntax:

   import "DPI-C" function void
         \$my_display(input string formatted /*verilator sformat*/ );

The /*verilator sformat*/ indicates that this function accepts a $display like format specifier followed by any number of arguments to satisfy the format.

DPI Context Functions

Verilator supports IEEE DPI Context Functions. Context imports pass the simulator context, including calling scope name, and filename and line number to the C code. For example, in Verilog:

   import "DPI-C" context function int dpic_line();
   initial $display("This is line %d, again, line %d\n", `line, dpic_line());

This will call C++ code which may then use the svGet* functions to read information, in this case the line number of the Verilog statement that invoked the dpic_line function:

   int dpic_line() {
       // Get a scope:  svScope scope = svGetScope();

       const char* scopenamep = svGetNameFromScope(scope);
       assert(scopenamep);

       const char* filenamep = "";
       int lineno = 0;
       if (svGetCallerInfo(&filenamep, &lineno)) {
           printf("dpic_line called from scope %s on line %d\n",
              scopenamep, lineno);
           return lineno;
       } else {
           return 0;
       }
   }

See the IEEE Standard for more information.

DPI Header Isolation

Verilator places the IEEE standard header files such as svdpi.h into a separate include directory, vltstd (VeriLaTor STandarD). When compiling most applications $VERILATOR_ROOT/include/vltstd would be in the include path along with the normal $VERILATOR_ROOT/include. However, when compiling Verilated models into other simulators which have their own svdpi.h and similar standard files with different contents, the vltstd directory should not be included to prevent picking up incompatible definitions.

Public Functions

Instead of DPI exporting, there's also Verilator public functions, which are slightly faster, but less compatible.

VERIFICATION PROCEDURAL INTERFACE (VPI)

Verilator supports a very limited subset of the VPI. This subset allows inspection, examination, value change callbacks, and depositing of values to public signals only.

VPI is enabled with the verilator --vpi switch.

To access signals via the VPI, Verilator must be told exactly which signals are to be accessed. This is done using the Verilator public pragmas documented below.

Verilator has an important difference from an event based simulator; signal values that are changed by the VPI will not immediately propagate their values, instead the top level header file's eval() method must be called. Normally this would be part of the normal evaluation (i.e. the next clock edge), not as part of the value change. This makes the performance of VPI routines extremely fast compared to event based simulators, but can confuse some test-benches that expect immediate propagation.

Note the VPI by its specified implementation will always be much slower than accessing the Verilator values by direct reference (structure->module->signame), as the VPI accessors perform lookup in functions at simulation runtime requiring at best hundreds of instructions, while the direct references are evaluated by the compiler and result in only a couple of instructions.

For signal callbacks to work the main loop of the program must call VerilatedVpi::callValueCbs().

VPI Example

In the below example, we have readme marked read-only, and writeme which if written from outside the model will have the same semantics as if it changed on the specified clock edge.

    cat >our.v <<'EOF'
      module our (input clk);
         reg readme   /*verilator public_flat_rd*/;
         reg writeme  /*verilator public_flat_rw @(posedge clk) */;
         initial $finish;
      endmodule
    EOF

There are many online tutorials and books on the VPI, but an example that accesses the above signal "readme" would be:

    cat >sim_main.cpp <<'<<EOF'
      #include "Vour.h"
      #include "verilated.h"
      #include "verilated_vpi.h"  // Required to get definitions

      vluint64_t main_time = 0;   // See comments in first example
      double sc_time_stamp() { return main_time; }

      void read_and_check() {
          vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL);
          if (!vh1) { vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found"); }
          const char* name = vpi_get_str(vpiName, vh1);
          printf("Module name: %s\n", name);  // Prints "readme"

          s_vpi_value v;
          v.format = vpiIntVal;
          vpi_get_value(vh1, &v);
          printf("Value of v: %d\n", v.value.integer);  // Prints "readme"
      }

      int main(int argc, char** argv, char** env) {
          Verilated::commandArgs(argc, argv);
          Vour* top = new Vour;
          Verilated::internalsDump();  // See scopes to help debug
          while (!Verilated::gotFinish()) {
              top->eval();
              VerilatedVpi::callValueCbs();  // For signal callbacks
              read_and_check();
          }
          delete top;
          exit(0);
      }
    EOF

CROSS COMPILATION

Verilator supports cross-compiling Verilated code. This is generally used to run Verilator on a Linux system and produce C++ code that is then compiled on Windows.

Cross compilation involves up to three different OSes. The build system is where you configured and compiled Verilator, the host system where you run Verilator, and the target system where you compile the Verilated code and run the simulation.

Currently, Verilator requires the build and host system type to be the same, though the target system type may be different. To support this, ./configure and make Verilator on the build system. Then, run Verilator on the host system. Finally, the output of Verilator may be compiled on the different target system.

To support this, none of the files that Verilator produces will reference any configure generated build-system specific files, such as config.h (which is renamed in Verilator to config_build.h to reduce confusion.) The disadvantage of this approach is that include/verilatedos.h must self-detect the requirements of the target system, rather than using configure.

The target system may also require edits to the Makefiles, the simple Makefiles produced by Verilator presume the target system is the same type as the build system.

CMake

Verilator can be run using CMake, which takes care of both running Verilator and compiling the output. There is a CMake example in the examples/ directory. The following is a minimal CMakeLists.txt that would build the code listed in "EXAMPLE C++ EXECUTION":

    project(cmake_example)
    find_package(verilator HINTS $ENV{VERILATOR_ROOT})
    add_executable(Vour sim_main.cpp)
    verilate(Vour SOURCES our.v)

find_package will automatically find an installed copy of Verilator, or use a local build if VERILATOR_ROOT is set.

It is recommended to use CMake >= 3.12 and the Ninja generator, though other combinations should work. To build with CMake, change to the folder containing CMakeLists.txt and run:

    mkdir build
    cd build
    cmake -GNinja ..
    ninja

Or to build with your system default generator:

    mkdir build
    cd build
    cmake ..
    cmake --build .

If you're building the example you should have an executable to run:

    ./Vour

The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and VERILATOR_BIN to the appropriate values, and also creates a verilate() function. verilate() will automatically create custom commands to run Verilator and add the generated C++ sources to the target specified.

    verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name]
             [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE]
             [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...]
             [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...])

Lowercase and ... should be replaced with arguments, the uppercase parts delimit the arguments and can be passed in any order, or left out entirely if optional.

verilate(target ...) can be called multiple times to add other verilog modules to an executable or library target.

When generating Verilated SystemC sources, you should also include the SystemC include directories and link to the SystemC libraries.

Verilator's CMake support provides a convenience function to automatically find and link to the SystemC library. It can be used as:

    verilator_link_systemc(target)

where target is the name of your target.

The search paths can be configured by setting some variables:

- The variables SYSTEMC_INCLUDE and SYSTEMC_LIBDIR to give a direct path to the SystemC include an library path.

- SYSTEMC_ROOT to set the installation prefix of an installed SystemC library.

- SYSTEMC to set the installation prefix of an installed SystemC library (same as above).

- When using Accellera's SystemC with CMake support, a CMake target is available that simplifies the above steps. This will only work if the SystemC installation can be found by CMake. This can be configured by setting the CMAKE_PREFIX_PATH variable during CMake configuration.

Don't forget to set the same C++ standard for the Verilated sources as the SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS environment variable.

target

Name of a target created by add_executable or add_library.

SOURCES

List of Verilog files to Verilate. Must have at least one file.

PREFIX

Optional. Sets the Verilator output prefix. Defaults to the name of the first source file with a "V" prepended. Must be unique in each call to verilate(), so this is necessary if you build a module multiple times with different parameters. Must be a valid C++ identifier, i.e. contains no white space and only characters A-Z, a-z, 0-9 or _.

TOP_MODULE

Optional. Sets the name of the top module. Defaults to the name of the first file in the SOURCES array.

TRACE

Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS --trace".

TRACE_FST

Optional. Enables FST tracing if present, equivalent to "VERILATOR_ARGS --trace-fst".

SYSTEMC

Optional. Enables SystemC mode, defaults to C++ if not specified.

COVERAGE

Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS --coverage"

INCLUDE_DIRS

Optional. Sets directories that Verilator searches (same as -y).

OPT_SLOW

Optional. Set compiler flags for the slow path. You may want to reduce the optimization level to improve compile times with large designs.

OPT_FAST

Optional. Set compiler flags for the fast path.

OPT_GLOBAL

Optional. Set compiler flags for the common runtime library used by Verilated models.

DIRECTORY

Optional. Set the verilator output directory. It is preferable to use the default, which will avoid collisions with other files.

VERILATOR_ARGS

Optional. Extra arguments to Verilator. Do not specify --Mdir or --prefix here, use DIRECTORY or PREFIX.

MULTITHREADING

Verilator supports multithreaded simulation models.

With --no-threads, the default, the model is not thread safe, and any use of more than one thread calling into one or even different Verilated models may result in unpredictable behavior. This gives the highest single thread performance.

With --threads 1, the generated model is single threaded, however the support libraries are multithread safe. This allows different instantiations of model(s) to potentially each be run under a different thread. All threading is the responsibility of the user's C++ testbench.

With --threads N, where N is at least 2, the generated model will be designed to run in parallel on N threads. The thread calling eval() provides one of those threads, and the generated model will create and manage the other N-1 threads. It's the client's responsibility not to oversubscribe the available CPU cores. Under CPU oversubscription, the Verilated model should not livelock nor deadlock, however, you can expect performance to be far worse than it would be with proper ratio of threads and CPU cores.

The remainder of this section describe behavior with --threads 1 or --threads N (not --no-threads).

VL_THREADED is defined when compiling a threaded Verilated module, causing the Verilated support classes become threadsafe.

The thread used for constructing a model must be the same thread that calls eval() into the model, this is called the "eval thread". The thread used to perform certain global operations such as saving and tracing must be done by a "main thread". In most cases the eval thread and main thread are the same thread (i.e. the user's top C++ testbench runs on a single thread), but this is not required.

The --trace-threads options can be used to produce trace dumps using multiple threads. If --trace-threads is set without --threads, then --trace-threads will imply --threads 1, i.e.: the support libraries will be thread safe.

With --trace-threads 0, trace dumps are produced on the main thread. This again gives the highest single thread performance.

With --trace-threads N, where N is at least 1, N additional threads will be created and managed by the trace files (e.g.: VerilatedVcdC or VerilatedFstC), to generate the trace dump. The main thread will be released to proceed with execution as soon as possible, though some blocking of the main thread is still necessary while capturing the trace. Different trace formats can utilize a various number of threads. See the --trace-threads option.

When running a multithreaded model, the default Linux task scheduler often works against the model, by assuming threads are short lived, and thus often schedules threads using multiple hyperthreads within the same physical core. For best performance use the numactl program to (when the threading count fits) select unique physical cores on the same socket. The same applies for --trace-threads as well.

As an example, if a model was Verilated with "--threads 4", we consult

   egrep 'processor|physical id|core id' /proc/cpuinfo

To select cores 0, 1, 2, and 3 that are all located on the same socket (0) but different physical cores. (Also useful is "numactl --hardware", or lscpu but those doesn't show Hyperthreading cores.) Then we execute

   numactl -m 0 -C 0,1,2,3 -- verilated_executable_name

This will limit memory to socket 0, and threads to cores 0, 1, 2, 3, (presumably on socket 0) optimizing performance. Of course this must be adjusted if you want another simulator using e.g. socket 1, or if you Verilated with a different number of threads. To see what CPUs are actually used, use --prof-threads.

Multithreaded Verilog and Library Support

$display/$stop/$finish are delayed until the end of an eval() call in order to maintain ordering between threads. This may result in additional tasks completing after the $stop or $finish.

    If using --coverage, the coverage routines are fully thread safe.

    If using --dpi, Verilator assumes pure DPI imports are thread safe, balancing performance versus safety. See --threads-dpi.

    If using --savable, the save/restore classes are not multithreaded and must be called only by the eval thread.

    If using --sc, the SystemC kernel is not thread safe, therefore the eval thread and main thread must be the same.

    If using --trace, the tracing classes must be constructed and called from the main thread.

    If using --vpi, since SystemVerilog VPI was not architected by IEEE to be multithreaded, Verilator requires all VPI calls are only made from the main thread.

CONFIGURATION FILES

In addition to the command line, warnings and other features may be controlled by configuration files, typically named with the .vlt extension. An example:

  `verilator_config
  lint_off -rule WIDTH
  lint_off -rule CASEX  -file "silly_vendor_code.v"

This disables WIDTH warnings globally, and CASEX for a specific file.

Configuration files are fed through the normal Verilog preprocessor prior to parsing, so `ifdefs, `defines, and comments may be used as if it were normal Verilog code.

Note that file or line-specific configuration only applies to files read after the configuration file. It is therefore recommended to pass the configuration file to Verilator as the first file.

The grammar of configuration commands is as follows:

`verilator_config

Take remaining text and treat it as Verilator configuration commands.

coverage_on [-file "<filename>" [-lines <line> [ - <line> ]]]
coverage_off [-file "<filename>" [-lines <line> [ - <line> ]]]

Enable/disable coverage for the specified filename (or wildcard with '*' or '?', or all files if omitted) and range of line numbers (or all lines if omitted). Often used to ignore an entire module for coverage analysis purposes.

lint_on [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]]
lint_off [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]]
lint_off [-rule <message>] [-file "<filename>"] [-match "<string>"]

Enable/disables the specified lint warning, in the specified filename (or wildcard with '*' or '?', or all files if omitted) and range of line numbers (or all lines if omitted).

With lint_off using '*' will override any lint_on directives in the source, i.e. the warning will still not be printed.

If the -rule is omitted, all lint warnings (see list in -Wno-lint) are enabled/disabled. This will override all later lint warning enables for the specified region.

If -match is set the linter warnings are matched against this (wildcard) string and are waived in case they match and iff rule and file (with wildcard) also match.

In previous versions -rule was named -msg. The latter is deprecated, but still works with a deprecation info, it may be removed in future versions.

tracing_on [-file "<filename>" [-lines <line> [ - <line> ]]]
tracing_off [-file "<filename>" [-lines <line> [ - <line> ]]]

Enable/disable waveform tracing for all future signals declared in the specified filename (or wildcard with '*' or '?', or all files if omitted) and range of line numbers (or all lines if omitted).

For tracing_off, cells below any module in the files/ranges specified will also not be traced.

clock_enable -module "<modulename>" -var "<signame>"

Indicate the signal is used to gate a clock, and the user takes responsibility for insuring there are no races related to it.

Same as /*verilator clock_enable*/, see "LANGUAGE EXTENSIONS" for more information and an example.

clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>"
clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"
no_clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>"
no_clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"

Indicate the signal is used as clock or not. This information is used by Verilator to mark the signal as clocker and propagate the clocker attribute automatically to derived signals. See --clk for more information.

Same as /*verilator clocker*/, see "LANGUAGE EXTENSIONS" for more information.

coverage_block_off -module "<modulename>" -block "<blockname>"
coverage_block_off -file "<filename>" -line <lineno>

Specifies the entire begin/end block should be ignored for coverage analysis purposes. Can either be specified as a named block or as a filename and line number.

Same as /*verilator coverage_block_off*/, see "LANGUAGE EXTENSIONS" for more information.

full_case -file "<filename>" -lines <lineno>
parallel_case -file "<filename>" -lines <lineno>

Same as "//synopsys full_case" and "//synopsys parallel_case". When these synthesis directives are discovered, Verilator will either formally prove the directive to be true, or failing that, will insert the appropriate code to detect failing cases at simulation runtime and print an "Assertion failed" error message.

inline -module "<modulename>"

Specifies the module may be inlined into any modules that use this module. Same as /*verilator inline_module*/, and see that under "LANGUAGE EXTENSIONS" for more information.

isolate_assignments -module "<modulename>" [-task "<taskname>"] -var "<signame>"
isolate_assignments -module "<modulename>" [-function "<funcname>"] -var "<signame>"
isolate_assignments -module "<modulename>" -function "<fname>"

Used to indicate the assignments to this signal in any blocks should be isolated into new blocks. When there is a large combinatorial block that is resulting in a UNOPTFLAT warning, attaching this to the signal causing a false loop may clear up the problem.

Same as /* verilator isolate_assignments */, see "LANGUAGE EXTENSIONS" for more information.

no_inline -module "<modulename>"

Specifies the module should not be inlined into any modules that use this module. Same as /*verilator no_inline_module*/, and see that under "LANGUAGE EXTENSIONS" for more information.

no_inline [-module "<modulename>"] -task "<taskname>"
no_inline [-module "<modulename>"] -function "<funcname>"

Specify the function or task should not be inlined into where it is used. This may reduce the size of the final executable when a task is used a very large number of times. For this flag to work, the task and tasks below it must be pure; they cannot reference any variables outside the task itself.

Same as /*verilator no_inline_task*/, see "LANGUAGE EXTENSIONS" for more information.

public [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>"
public_flat [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>"
public_flat_rd [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>"
public_flat_rw [-module "<modulename>"] [-task/-function "<taskname>"] -var "<signame>" "@(edge)"

Sets the variable to be public. Same as /*verilator public*/ or /*verilator public_flat*/ etc, see those under "LANGUAGE EXTENSIONS" for more information.

sc_bv -module "<modulename>" [-task "<taskname>"] -var "<signame>"
sc_bv -module "<modulename>" [-function "<funcname>"] -var "<signame>"

Sets the port to be of sc_bv<width> type, instead of bool, vluint32_t or vluint64_t. Same as /*verilator sc_bv*/, see that under "LANGUAGE EXTENSIONS" for more information.

sformat [-module "<modulename>"] [-task "<taskname>"] -var "<signame>"
sformat [-module "<modulename>"] [-function "<funcname>"] -var "<signame>"

Must be applied to the final argument of type "input string" of a function or task to indicate the function or task should pass all remaining arguments through $sformatf. This allows creation of DPI functions with $display like behavior. See the test_regress/t/t_dpi_display.v file for an example.

Same as /*verilator sformat*/, see "LANGUAGE EXTENSIONS" for more information.

split_var [-module "<modulename>"] [-task "<taskname>"] -var "<varname>"
split_var [-module "<modulename>"] [-function "<funcname>"] -var "<varname>"

Break the variable into multiple pieces typically to resolve UNOPTFLAT performance issues. Typically the variables to attach this to are recommended by Verilator itself, see UNOPTFLAT.

Same as /*verilator split_var*/, see "LANGUAGE EXTENSIONS" for more information.

LANGUAGE STANDARD SUPPORT

Verilog 2001 (IEEE 1364-2001) Support

Verilator supports most Verilog 2001 language features. This includes signed numbers, "always @*", generate statements, multidimensional arrays, localparam, and C-style declarations inside port lists.

Verilog 2005 (IEEE 1364-2005) Support

Verilator supports most Verilog 2005 language features. This includes the `begin_keywords and `end_keywords compiler directives, $clog2, and the uwire keyword.

SystemVerilog 2005 (IEEE 1800-2005) Support

Verilator supports ==? and !=? operators, ++ and -- in some contexts, $bits, $countbits, $countones, $error, $fatal, $info, $isunknown, $onehot, $onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit, byte, chandle, const, do-while, enum, export, final, import, int, interface, logic, longint, modport, package, program, shortint, struct, time, typedef, union, var, void, priority case/if, and unique case/if.

It also supports .name and .* interconnection.

Verilator partially supports concurrent assert and cover statements; see the enclosed coverage tests for the syntax which is allowed.

SystemVerilog 2012 (IEEE 1800-2012) Support

Verilator implements a full SystemVerilog 2012 preprocessor, including function call-like preprocessor defines, default define arguments, `__FILE__, `__LINE__ and `undefineall.

Verilator currently has some support for SystemVerilog synthesis constructs. As SystemVerilog features enter common usage they are added; please file a bug if a feature you need is missing.

SystemVerilog 2017 (IEEE 1800-2017) Support

Verilator supports the 2017 "for" loop constructs, and several minor cleanups made in 1800-2017.

Verilog AMS Support

Verilator implements a very small subset of Verilog AMS (Verilog Analog and Mixed-Signal Extensions) with the subset corresponding to those VMS keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009 languages.

AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS".

At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt, string, and wreal.

Synthesis Directive Assertion Support

With the --assert switch, Verilator reads any "//synopsys full_case" or "//synopsys parallel_case" directives. The same applies to any "//ambit synthesis", "//cadence" or "//pragma" directives of the same form.

When these synthesis directives are discovered, Verilator will either formally prove the directive to be true, or failing that, will insert the appropriate code to detect failing cases at simulation runtime and print an "Assertion failed" error message.

Verilator likewise also asserts any "unique" or "priority" SystemVerilog keywords on case statement, as well as "unique" on if statements. However, "priority if" is currently simply ignored.

LANGUAGE EXTENSIONS

The following additional constructs are the extensions Verilator supports on top of standard Verilog code. Using these features outside of comments or `ifdef's may break other tools.

`__FILE__

The __FILE__ define expands to the current filename as a string, like C++'s __FILE__. This was incorporated into to the 1800-2009 standard (but supported by Verilator since 2006!)

`__LINE__

The __LINE__ define expands to the current filename as a string, like C++'s __LINE__. This was incorporated into to the 1800-2009 standard (but supported by Verilator since 2006!)

`error string

This will report an error when encountered, like C++'s #error.

$c(string, ...);

The string will be embedded directly in the output C++ code at the point where the surrounding Verilog code is compiled. It may either be a standalone statement (with a trailing ; in the string), or a function that returns up to a 32-bit number (without a trailing ;). This can be used to call C++ functions from your Verilog code.

String arguments will be put directly into the output C++ code. Expression arguments will have the code to evaluate the expression inserted. Thus to call a C++ function, $c("func(",a,")") will result in 'func(a)' in the output C++ code. For input arguments, rather than hard-coding variable names in the string $c("func(a)"), instead pass the variable as an expression $c("func(",a,")"). This will allow the call to work inside Verilog functions where the variable is flattened out, and also enable other optimizations.

If you will be reading or writing any Verilog variables inside the C++ functions, the Verilog signals must be declared with /*verilator public*/.

You may also append an arbitrary number to $c, generally the width of the output. [signal_32_bits = $c32("...");] This allows for compatibility with other simulators which require a differently named PLI function name for each different output width.

$display, $write, $fdisplay, $fwrite, $sformat, $swrite

Format arguments may use C fprintf sizes after the % escape. Per the Verilog standard, %x prints a number with the natural width, and %0x prints a number with minimum width. Verilator extends this so %5x prints 5 digits per the C standard (this is unspecified in Verilog, but was incorporated into the 1800-2009).

`coverage_block_off

Specifies the entire begin/end block should be ignored for coverage analysis. Must be inside a code block, e.g. within a begin/end pair. Same as /* verilator coverage_block_off */ and coverage_block_off in "CONFIGURATION FILES".

`systemc_header

Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the output .h file's header. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code.

`systemc_ctor

Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the C++ class constructor. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code.

`systemc_dtor

Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the C++ class destructor. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code.

`systemc_interface

Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the C++ class interface. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code.

`systemc_imp_header

Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the header of all files for this C++ class implementation. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code.

`systemc_implementation

Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into a single file of the C++ class implementation. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code.

If you will be reading or writing any Verilog variables in the C++ functions, the Verilog signals must be declared with /*verilator public*/. See also the public task feature; writing an accessor may result in cleaner code.

`SYSTEMVERILOG

The SYSTEMVERILOG, SV_COV_START and related standard defines are set by default when --language is 1800-*.

`VERILATOR
`verilator
`verilator3

The VERILATOR, verilator and verilator3 defines are set by default so you may `ifdef around tool specific constructs.

`verilator_config

Take remaining text up to the next `verilog mode switch and treat it as Verilator configuration commands.

`verilog

Switch back to processing Verilog code after a `systemc_... mode switch. The Verilog code returns to the last language mode specified with `begin_keywords, or SystemVerilog if none was specified.

/*verilator clock_enable*/

Used after a signal declaration to indicate the signal is used to gate a clock, and the user takes responsibility for insuring there are no races related to it. (Typically by adding a latch, and running static timing analysis.) For example:

   reg enable_r /*verilator clock_enable*/;
   wire gated_clk = clk & enable_r;
   always_ff @ (posedge clk)
      enable_r <= enable_early;

The clock_enable attribute will cause the clock gate to be ignored in the scheduling algorithm, sometimes required for correct clock behavior, and always improving performance. It's also a good idea to enable the IMPERFECTSCH warning, to ensure all clock enables are properly recognized.

Same as clock_enable in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator clocker*/
/*verilator no_clocker*/

Used after a signal declaration to indicate the signal is used as clock or not. This information is used by Verilator to mark the signal as clocker and propagate the clocker attribute automatically to derived signals. See --clk for more information.

Same as clocker and no_clocker in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator coverage_block_off*/

Specifies the entire begin/end block should be ignored for coverage analysis purposes.

Same as coverage_block_off in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator coverage_off*/

Specifies that following lines of code should have coverage disabled. Often used to ignore an entire module for coverage analysis purposes.

/*verilator coverage_on*/

Specifies that following lines of code should have coverage re-enabled (if appropriate --coverage flags are passed) after being disabled earlier with /*verilator coverage_off*/.

/*verilator inline_module*/

Specifies the module the comment appears in may be inlined into any modules that use this module. This is useful to speed up simulation runtime. Note if using "--public" that signals under inlined submodules will be named submodule__DOT__subsignal as C++ does not allow "." in signal names.

Same as inline in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator isolate_assignments*/

Used after a signal declaration to indicate the assignments to this signal in any blocks should be isolated into new blocks. When there is a large combinatorial block that is resulting in a UNOPTFLAT warning, attaching this to the signal causing a false loop may clear up the problem.

IE, with the following

    reg splitme /* verilator isolate_assignments*/;
    // Note the placement of the semicolon above
    always @* begin
      if (....) begin
         splitme = ....;
         other assignments
      end
    end

Verilator will internally split the block that assigns to "splitme" into two blocks:

It would then internally break it into (sort of):

    // All assignments excluding those to splitme
    always @* begin
      if (....) begin
         other assignments
      end
    end
    // All assignments to splitme
    always @* begin
      if (....) begin
         splitme = ....;
      end
    end

Same as isolate_assignments in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator lint_off msg*/

Disable the specified warning message for any warnings following the comment.

/*verilator lint_on msg*/

Re-enable the specified warning message for any warnings following the comment.

/*verilator lint_restore*/

After a /*verilator lint_save*/, pop the stack containing lint message state. Often this is useful at the bottom of include files.

/*verilator lint_save*/

Push the current state of what lint messages are turned on or turned off to a stack. Later meta-comments may then lint_on or lint_off specific messages, then return to the earlier message state by using /*verilator lint_restore*/. For example:

    // verilator lint_save
    // verilator lint_off SOME_WARNING
    ...  // code needing SOME_WARNING turned off
    // verilator lint_restore

If SOME_WARNING was on before the lint_off, it will now be restored to on, and if it was off before the lint_off it will remain off.

/*verilator no_inline_module*/

Specifies the module the comment appears in should not be inlined into any modules that use this module.

Same as no_inline in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator no_inline_task*/

Used in a function or task variable definition section to specify the function or task should not be inlined into where it is used. This may reduce the size of the final executable when a task is used a very large number of times. For this flag to work, the task and tasks below it must be pure; they cannot reference any variables outside the task itself.

Same as no_inline in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator public*/ (parameter)

Used after a parameter declaration to indicate the emitted C code should have the parameter values visible. Due to C++ language restrictions, this may only be used on 64-bit or narrower integral enumerations.

    parameter [2:0] PARAM /*verilator public*/ = 2'b0;
/*verilator public*/ (typedef enum)

Used after an enum typedef declaration to indicate the emitted C code should have the enum values visible. Due to C++ language restrictions, this may only be used on 64-bit or narrower integral enumerations.

    typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
/*verilator public*/ (variable)

Used after an input, output, register, or wire declaration to indicate the signal should be declared so that C code may read or write the value of the signal. This will also declare this module public, otherwise use /*verilator public_flat*/.

Instead of using public variables, consider instead making a DPI or public function that accesses the variable. This is nicer as it provides an obvious entry point that is also compatible across simulators.

Same as public in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator public*/ (task/function)

Used inside the declaration section of a function or task declaration to indicate the function or task should be made into a C++ function, public to outside callers. Public tasks will be declared as a void C++ function, public functions will get the appropriate non-void (bool, uint32_t, etc) return type. Any input arguments will become C++ arguments to the function. Any output arguments will become C++ reference arguments. Any local registers/integers will become function automatic variables on the stack.

Wide variables over 64 bits cannot be function returns, to avoid exposing complexities. However, wide variables can be input/outputs; they will be passed as references to an array of 32-bit numbers.

Generally, only the values of stored state (flops) should be written, as the model will NOT notice changes made to variables in these functions. (Same as when a signal is declared public.)

You may want to use DPI exports instead, as it's compatible with other simulators.

Same as public in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator public_flat*/ (variable)

Used after an input, output, register, or wire declaration to indicate the signal should be declared so that C code may read or write the value of the signal. This will not declare this module public, which means the name of the signal or path to it may change based upon the module inlining which takes place.

Same as public_flat in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator public_flat_rd*/ (variable)

Used after an input, output, register, or wire declaration to indicate the signal should be declared public_flat (see above), but read-only.

Same as public_flat_rd in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator public_flat_rw @(<edge_list>) */ (variable)

Used after an input, output, register, or wire declaration to indicate the signal should be declared public_flat_rd (see above), and also writable, where writes should be considered to have the timing specified by the given sensitivity edge list. Set for all variables, ports and wires using the --public-flat-rw switch.

Same as public_flat_rw in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator public_module*/

Used after a module statement to indicate the module should not be inlined (unless specifically requested) so that C code may access the module. Verilator automatically sets this attribute when the module contains any public signals or `systemc_ directives. Also set for all modules when using the --public switch.

Same as public in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator sc_clock*/

Deprecated. Used after an input declaration to indicate the signal should be declared in SystemC as a sc_clock instead of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 and later do not require clock pins to be sc_clocks and this is no longer needed.

/*verilator sc_bv*/

Used after a port declaration. It sets the port to be of sc_bv<width> type, instead of bool, vluint32_t or vluint64_t. This may be useful if the port width is parameterized and the instantiating C++ code wants to always have a sc_bv so it can accept any width. In general you should avoid using this attribute when not necessary as with increasing usage of sc_bv the performance decreases significantly.

Same as sc_bv in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator sformat*/

Attached to the final argument of type "input string" of a function or task to indicate the function or task should pass all remaining arguments through $sformatf. This allows creation of DPI functions with $display like behavior. See the test_regress/t/t_dpi_display.v file for an example.

Same as sformat in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator split_var*/

Attached to a variable or a net declaration to break the variable into multiple pieces typically to resolve UNOPTFLAT performance issues. Typically the variables to attach this to are recommended by Verilator itself, see UNOPTFLAT below.

For example, Verilator will internally convert a variable with the metacomment such as:

    logic [7:0] x [0:1]  /*verilator split_var*/;

To:

    logic [7:0] x__BRA__0__KET__ /*verilator split_var*/;
    logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;

Note that the generated packed variables retain the split_var metacomment because they may be split into further smaller pieces according to the access patterns.

This only supports unpacked arrays, packed arrays, and packed structs of integer types (reg, logic, bit, byte, int...); otherwise if a split was requested but cannot occur a SPLITVAR warning is issued. Splitting large arrays may slow down the Verilation speed, so use this only on variables that require it.

Same as split_var in configuration files, see "CONFIGURATION FILES" for more information.

/*verilator tag <text...>*/

Attached after a variable or structure member to indicate opaque (to Verilator) text that should be passed through to the XML output as a tag, for use by downstream applications.

/*verilator tracing_off*/

Disable waveform tracing for all future signals that are declared in this module, or cells below this module. Often this is placed just after a primitive's module statement, so that the entire module and cells below it are not traced.

/*verilator tracing_on*/

Re-enable waveform tracing for all future signals or cells that are declared.

LANGUAGE LIMITATIONS

There are some limitations and lack of features relative to the major closed-source simulators, by intent.

Synthesis Subset

Verilator supports the Synthesis subset with other verification constructs being added over time. Verilator also simulates events as Synopsys's Design Compiler would; namely given a block of the form:

        always @ (x)   y = x & z;

This will recompute y when there is even a potential for change in x or a change in z, that is when the flops computing x or z evaluate (which is what Design Compiler will synthesize.) A compliant simulator would only calculate y if x changes. We recommend using always_comb to make the code run the same everywhere. Also avoid putting $displays in combo blocks, as they may print multiple times when not desired, even on compliant simulators as event ordering is not specified.

Signal Naming

To avoid conflicts with C symbol naming, any character in a signal name that is not alphanumeric nor a single underscore will be replaced by __0hh where hh is the hex code of the character. To avoid conflicts with Verilator's internal symbols, any double underscore are replaced with ___05F (5F is the hex code of an underscore.)

Bind

Verilator only supports "bind" to a target module name, not an instance path.

Class

Verilator class support is limited but in active development. Verilator supports members, and methods. Verilator does not support class static members, class extend, or class parameters.

Dotted cross-hierarchy references

Verilator supports dotted references to variables, functions and tasks in different modules. The portion before the dot must have a constant value; for example a[2].b is acceptable, while a[x].b is generally not.

References into generated and arrayed instances use the instance names specified in the Verilog standard; arrayed instances are named {cellName}[{instanceNumber}] in Verilog, which becomes {cellname}__BRA__{instanceNumber}__KET__ inside the generated C++ code.

Latches

Verilator is optimized for edge sensitive (flop based) designs. It will attempt to do the correct thing for latches, but most performance optimizations will be disabled around the latch.

Structures and Unions

Presently Verilator only supports packed structs and packed unions. Rand and randc tags on members are simply ignored. All structures and unions are represented as a single vector, which means that generating one member of a structure from blocking, and another from non-blocking assignments is unsupported.

Time

All delays (#) are ignored, as they are in synthesis.

Unknown states

Verilator is mostly a two state simulator, not a four state simulator. However, it has two features which uncover most initialization bugs (including many that a four state simulator will miss.)

Identity comparisons (=== or !==) are converted to standard ==/!= when neither side is a constant. This may make the expression yield a different result compared to a four state simulator. An === comparison to X will always be false, so that Verilog code which checks for uninitialized logic will not fire.

Assigning X to a variable will actually assign a constant value as determined by the --x-assign switch. This allows runtime randomization, thus if the value is actually used, the random value should cause downstream errors. Integers also get randomized, even though the Verilog 2001 specification says they initialize to zero. Note however that randomization happens at initialization time and hence during a single simulation run, the same constant (but random) value will be used every time the assignment is executed.

All variables, depending on --x-initial setting, are typically randomly initialized using a function. By running several random simulation runs you can determine that reset is working correctly. On the first run, have the function initialize variables to zero. On the second, have it initialize variables to one. On the third and following runs have it initialize them randomly. If the results match, reset works. (Note this is what the hardware will really do.) In practice, just setting all variables to one at startup finds most problems (since typically control signals are active-high).

--x-assign applies to variables explicitly initialized or assigned an X. Uninitialized clocks are initialized to zero, while all other state holding variables are initialized to a random value. Event driven simulators will generally trigger an edge on a transition from X to 1 (posedge) or X to 0 (negedge). However, by default, since clocks are initialized to zero, Verilator will not trigger an initial negedge. Some code (particularly for reset) may rely on X->0 triggering an edge. The --x-initial-edge switch enables this behavior. Comparing runs with and without this switch will find such problems.

Tri/Inout

Verilator converts some simple tristate structures into two state. Pullup, pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are also supported. Simple comparisons with === 1'bz are also supported.

An assignment of the form:

    inout driver;
    wire driver = (enable) ? output_value : 1'bz;

Will be converted to

    input driver;       // Value being driven in from "external" drivers
    output driver__en;  // True if driven from this module
    output driver__out; // Value being driven from this module

External logic will be needed to combine these signals with any external drivers.

Tristate drivers are not supported inside functions and tasks; an inout there will be considered a two state variable that is read and written instead of a four state variable.

Functions & Tasks

All functions and tasks will be inlined (will not become functions in C.) The only support provided is for simple statements in tasks (which may affect global variables).

Recursive functions and tasks are not supported. All inputs and outputs are automatic, as if they had the Verilog 2001 "automatic" keyword prepended. (If you don't know what this means, Verilator will do what you probably expect -- what C does. The default behavior of Verilog is different.)

Generated Clocks

Verilator attempts to deal with generated and gated clocks correctly, however some cases cause problems in the scheduling algorithm which is optimized for performance. The safest option is to have all clocks as primary inputs to the model, or wires directly attached to primary inputs. For proper behavior clock enables may also need the /*verilator clock_enable*/ attribute.

Gate Primitives

The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are directly converted to behavioral equivalents. The 3-state and MOS gate primitives are not supported. Tables are not supported.

Specify blocks

All specify blocks and timing checks are ignored. All min:typ:max delays use the typical value.

Array Initialization

When initializing a large array, you need to use non-delayed assignments. Verilator will tell you when this needs to be fixed; see the BLKLOOPINIT error for more information.

Array Out of Bounds

Writing a memory element that is outside the bounds specified for the array may cause a different memory element inside the array to be written instead. For power-of-2 sized arrays, Verilator will give a width warning and the address. For non-power-of-2-sizes arrays, index 0 will be written.

Reading a memory element that is outside the bounds specified for the array will give a width warning and wrap around the power-of-2 size. For non-power-of-2 sizes, it will return a unspecified constant of the appropriate width.

Assertions

Verilator is beginning to add support for assertions. Verilator currently only converts assertions to simple "if (...) error" statements, and coverage statements to increment the line counters described in the coverage section.

Verilator does not support SEREs yet. All assertion and coverage statements must be simple expressions that complete in one cycle.

Encrypted Verilog

Open source simulators like Verilator are unable to use encrypted RTL (i.e. IEEE P1735). Talk to your IP vendor about delivering IP blocks via Verilator's --protect-lib feature.

Language Keyword Limitations

This section describes specific limitations for each language keyword.

`__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords, `endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor, `systemc_dtor, `systemc_header, `systemc_imp_header, `systemc_implementation, `systemc_interface, `undef, `verilog

Fully supported.

always, always_comb, always_ff, always_latch, and, assign, begin, buf, byte, case, casex, casez, default, defparam, do-while, else, end, endcase, endfunction, endgenerate, endmodule, endspecify, endtask, final, for, function, generate, genvar, if, initial, inout, input, int, integer, localparam, logic, longint, macromodule, module, nand, negedge, nor, not, or, output, parameter, posedge, reg, scalared, shortint, signed, supply0, supply1, task, time, tri, typedef, var, vectored, while, wire, xnor, xor

Generally supported.

++, -- operators

Increment/decrement can only be used as standalone statements or in certain limited cases.

'{} operator

Assignment patterns with order based, default, constant integer (array) or member identifier (struct/union) keys are supported. Data type keys and keys which are computed from a constant expression are not supported.

`uselib

Uselib, a vendor specific library specification method, is ignored along with anything following it until the end of that line.

cast operator

Casting is supported only between simple scalar types, signed and unsigned, not arrays nor structs.

chandle

Treated as a "longint"; does not yet warn about operations that are specified as illegal on chandles.

disable

Disable statements may be used only if the block being disabled is a block the disable statement itself is inside. This was commonly used to provide loop break and continue functionality before SystemVerilog added the break and continue keywords.

inside

Inside expressions may not include unpacked array traversal or $ as an upper bound. Case inside and case matches are also unsupported.

interface

Interfaces and modports, including with generated data types are supported. Generate blocks around modports are not supported, nor are virtual interfaces nor unnamed interfaces.

shortreal

Short floating point (shortreal) numbers are converted to real. Most other simulators either do not support float, or convert likewise.

specify specparam

All specify blocks and timing checks are ignored.

uwire

Verilator does not perform warning checking on uwires, it treats the uwire keyword as if it were the normal wire keyword.

$bits, $countbits, $countones, $error, $fatal, $finish, $info, $isunknown, $onehot, $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, $time, $unsigned, $warning.

Generally supported.

$dumpfile or $dumpports will create a VCD or FST file (which is based on the --trace argument given when the model was Verilated). This will take effect starting at the next eval() call. If you have multiple Verilated designs under the same C model, then this will dump signals only from the design containing the $dumpvars.

$dumpvars and $dumpports module identifier is ignored; the traced instances will always start at the top of the design. The levels argument is also ignored, use tracing_on/tracing_off pragmas instead.

$dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename argument is ignored, only a single trace file may be active at once.

$dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and $dumplimit/$dumpportlimit are currently ignored.

$finish, $stop

The rarely used optional parameter to $finish and $stop is ignored.

$fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf

Generally supported.

$fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, $setup, $setuphold, $skew, $timeskew, $width

All specify blocks and timing checks are ignored.

$monitor, $strobe

Monitor and strobe are not supported, convert to always_comb $display or similar.

$random

$random does not support the optional argument to set the seed. Use the srand function in C to accomplish this, and note there is only one random number generator (not one per module).

$readmemb, $readmemh

Read memory commands should work properly. Note Verilator and the Verilog specification does not include support for readmem to multi-dimensional arrays.

$test$plusargs, $value$plusargs

Supported, but the instantiating C++/SystemC testbench must call

    Verilated::commandArgs(argc, argv);

to register the command line before calling $test$plusargs or $value$plusargs.

ERRORS AND WARNINGS

Warnings may be disabled in three ways. First, when the warning is printed it will include a warning code. Simply surround the offending line with a lint_off/lint_on pair:

        // verilator lint_off UNSIGNED
        if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop;
        // verilator lint_on UNSIGNED

Second, warnings may be disabled using a configuration file with a lint_off command. This is useful when a script is suppressing warnings and the Verilog source should not be changed.

Warnings may also be globally disabled by invoking Verilator with the -Wno-warning switch. This should be avoided, as it removes all checking across the designs, and prevents other users from compiling your code without knowing the magic set of disables needed to successfully compile your design.

Error and Warning Format

Warnings and errors printed by Verilator always match this regular expression:

        %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.*

Errors and warning start with a percent sign (historical heritage from Digital Equipment Corporation). Some errors or warning have a code attached, with meanings described below. Some errors also have a filename, line number and optional column number (starting at column 1 to match GCC).

Following the error message, Verilator will typically show the user's source code corresponding to the error, prefixed by the line number and a " | ". Following this is typically an arrow and ~ pointing at the error on the source line directly above.

List of all warnings

ALWCOMBORDER

Warns that an always_comb block has a variable which is set after it is used. This may cause simulation-synthesis mismatches, as not all simulators allow this ordering.

    always_comb begin
       a = b;
       b = 1;
    end

Ignoring this warning will only suppress the lint check, it will simulate correctly.

ASSIGNIN

Error that an assignment is being made to an input signal. This is almost certainly a mistake, though technically legal.

    input a;
    assign a = 1'b1;

Ignoring this warning will only suppress the lint check, it will simulate correctly.

ASSIGNDLY

Warns that you have an assignment statement with a delayed time in front of it, for example:

    a <= #100 b;
    assign #100 a = b;

Ignoring this warning may make Verilator simulations differ from other simulators, however at one point this was a common style so disabled by default as a code style warning.

BLKANDNBLK

BLKANDNBLK is an error that a variable comes from a mix of blocking and non-blocking assignments. Generally, this is caused by a register driven by both combo logic and a flop:

      always @ (posedge clk)  foo[0] <= ...
      always @* foo[1] = ...

Simply use a different register for the flop:

      always @ (posedge clk)  foo_flopped[0] <= ...
      always @* foo[0] = foo_flopped[0];
      always @* foo[1] = ...

This is not illegal in SystemVerilog, but a violation of good coding practice. Verilator reports this as an error, because ignoring this warning may make Verilator simulations differ from other simulators.

It is generally safe to disable this error (with a "// verilator lint_off BLKANDNBLK" metacomment or the -Wno-BLKANDNBLK option) when one of the assignments is inside a public task, or when the blocking and non-blocking assignments have non-overlapping bits and structure members.

BLKSEQ

This indicates that a blocking assignment (=) is used in a sequential block. Generally non-blocking/delayed assignments (<=) are used in sequential blocks, to avoid the possibility of simulator races. It can be reasonable to do this if the generated signal is used ONLY later in the same block, however this style is generally discouraged as it is error prone.

      always @ (posedge clk)  foo = ...

Disabled by default as this is a code style warning; it will simulate correctly.

BLKLOOPINIT

This indicates that the initialization of an array needs to use non-delayed assignments. This is done in the interest of speed; if delayed assignments were used, the simulator would have to copy large arrays every cycle. (In smaller loops, loop unrolling allows the delayed assignment to work, though it's a bit slower than a non-delayed assignment.) Here's an example

        always @ (posedge clk)
            if (~reset_l) begin
                for (i=0; i<`ARRAY_SIZE; i++) begin
                    array[i] = 0;  // Non-delayed for verilator
                end

This message is only seen on large or complicated loops because Verilator generally unrolls small loops. You may want to try increasing --unroll-count (and occasionally --unroll-stmts) which will raise the small loop bar to avoid this error.

BOUNDED

This indicates that bounded queues (e.g. "var name[$ : 3]") are unsupported.

Ignoring this warning may make Verilator simulations differ from other simulators.

BSSPACE

Warns that a backslash is followed by a space then a newline. Likely the intent was to have a backslash directly followed by a newline (e.g. when making a `define) and there's accidentally white space at the end of the line. If the space is not accidental, suggest removing the backslash in the code as it serves no function.

Ignoring this warning will only suppress the lint check, it will simulate correctly.

CASEINCOMPLETE

Warns that inside a case statement there is a stimulus pattern for which there is no case item specified. This is bad style, if a case is impossible, it's better to have a "default: $stop;" or just "default: ;" so that any design assumption violations will be discovered in simulation.

Ignoring this warning will only suppress the lint check, it will simulate correctly.

CASEOVERLAP

Warns that inside a case statement you have case values which are detected to be overlapping. This is bad style, as moving the order of case values will cause different behavior. Generally the values can be respecified to not overlap.

Ignoring this warning will only suppress the lint check, it will simulate correctly.

CASEX

Warns that it is simply better style to use casez, and ? in place of x's. See http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf

Ignoring this warning will only suppress the lint check, it will simulate correctly.

CASEWITHX

Warns that a case statement contains a constant with a x. Verilator is two-state so interpret such items as always false. Note a common error is to use a X in a case or casez statement item; often what the user instead intended is to use a casez with ?.

Ignoring this warning will only suppress the lint check, it will simulate correctly.

CDCRSTLOGIC

With --cdc only, warns that asynchronous flop reset terms come from other than primary inputs or flopped outputs, creating the potential for reset glitches.

CLKDATA

Warns that clock signal is mixed used with/as data signal. The checking for this warning is enabled only if user has explicitly marked some signal as clocker using command line option or in-source meta comment (see --clk).

The warning can be disabled without affecting the simulation result. But it is recommended to check the warning as this may degrade the performance of the Verilated model.

CMPCONST

Warns that you are comparing a value in a way that will always be constant. For example "X > 1" will always be true when X is a single bit wide.

Ignoring this warning will only suppress the lint check, it will simulate correctly.

COLONPLUS

Warns that a :+ is seen. Likely the intent was to use +: to select a range of bits. If the intent was a range that is explicitly positive, suggest adding a space, e.g. use ": +".

Ignoring this warning will only suppress the lint check, it will simulate correctly.

COMBDLY

Warns that you have a delayed assignment inside of a combinatorial block. Using delayed assignments in this way is considered bad form, and may lead to the simulator not matching synthesis. If this message is suppressed, Verilator, like synthesis, will convert this to a non-delayed assignment, which may result in logic races or other nasties. See http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf

Ignoring this warning may make Verilator simulations differ from other simulators.

CONTASSREG

Error that a continuous assignment is setting a reg. According to IEEE Verilog, but not SystemVerilog, a wire must be used as the target of continuous assignments.

This error is only reported when "--language 1364-1995", "--language 1364-2001", or "--language 1364-2005" is used.

Ignoring this error will only suppress the lint check, it will simulate correctly.

DECLFILENAME

Warns that a module or other declaration's name doesn't match the filename with path and extension stripped that it is declared in. The filename a modules/interfaces/programs is declared in should match the name of the module etc. so that -y directory searching will work. This warning is printed for only the first mismatching module in any given file, and -v library files are ignored.

Disabled by default as this is a code style warning; it will simulate correctly.

DEFPARAM

Warns that the "defparam" statement was deprecated in Verilog 2001 and all designs should now be using the #(...) format to specify parameters.

Disabled by default as this is a code style warning; it will simulate correctly.

DETECTARRAY

Error when Verilator tries to deal with a combinatorial loop that could not be flattened, and which involves a datatype which Verilator cannot handle, such as an unpacked struct or a large unpacked array. This typically occurs when -Wno-UNOPTFLAT has been used to override an UNOPTFLAT warning (see below).

The solution is to break the loop, as described for UNOPTFLAT.

DIDNOTCONVERGE

Error at simulation runtime when model did not properly settle.

Verilator sometimes has to evaluate combinatorial logic multiple times, usually around code where a UNOPTFLAT warning was issued, but disabled. For example:

   always_comb b = ~a;
   always_comb a = b

This code will toggle forever, and thus to prevent an infinite loop, the executable will give the didn't converge error.

To debug this, first review any UNOPTFLAT warnings that were ignored. Though typically it is safe to ignore UNOPTFLAT (at a performance cost), at the time of issuing a UNOPTFLAT Verilator did not know if the logic would eventually converge and assumed it would.

Next, run Verilator with --prof-cfuncs. Run make on the generated files with "CPP_FLAGS=-DVL_DEBUG", to allow enabling simulation runtime debug messages. Rerun the test. Now just before the convergence error you should see additional output similar to this:

   CHANGE: filename.v:1: b
   CHANGE: filename.v:2: a

This means that signal b and signal a keep changing, inspect the code that modifies these signals. Note if many signals are getting printed then most likely all of them are oscillating. It may also be that e.g. "a" may be oscillating, then "a" feeds signal "c" which then is also reported as oscillating.

Finally, rare, more difficult cases can be debugged like a "C" program; either enter GDB and use its tracing facilities, or edit the generated C++ code to add appropriate prints to see what is going on.

ENDLABEL

Warns that a label attached to a "end"-something statement does not match the label attached to the block start.

Ignoring this warning will only suppress the lint check, it will simulate correctly.

GENCLK

Deprecated and no longer used as a warning. Used to indicate that the specified signal was is generated inside the model, and also being used as a clock.

IFDEPTH

Warns that if/if else statements have exceeded the depth specified with --if-depth, as they are likely to result in slow priority encoders. Statements below unique and priority if statements are ignored. Solutions include changing the code to a case statement, or a SystemVerilog 'unique if' or 'priority if'.

Disabled by default as this is a code style warning; it will simulate correctly.

IGNOREDRETURN

Warns that a non-void function is being called as a task, and hence the return value is being ignored.

This warning is required by IEEE. The portable way to suppress this warning (in SystemVerilog) is to use a void cast, e.g.

    void'(function_being_called_as_task());

Ignoring this warning will only suppress the lint check, it will simulate correctly.

IMPERFECTSCH

Warns that the scheduling of the model is not absolutely perfect, and some manual code edits may result in faster performance. This warning defaults to off, is not part of -Wall, and must be turned on explicitly before the top module statement is processed.

IMPLICIT

Warns that a wire is being implicitly declared (it is a single bit wide output from a sub-module.) While legal in Verilog, implicit declarations only work for single bit wide signals (not buses), do not allow using a signal before it is implicitly declared by a cell, and can lead to dangling nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for Emacs, available from https://www.veripool.org/verilog-mode

Ignoring this warning will only suppress the lint check, it will simulate correctly.

IMPORTSTAR

Warns that an "import package::*" statement is in $unit scope. This causes the imported symbols to pollute the global namespace, defeating much of the purpose of having a package. Generally "import ::*" should only be used inside a lower scope such as a package or module.

Disabled by default as this is a code style warning; it will simulate correctly.

IMPURE

Warns that a task or function that has been marked with /*verilator no_inline_task*/ references variables that are not local to the task. Verilator cannot schedule these variables correctly.

Ignoring this warning may make Verilator simulations differ from other simulators.

INCABSPATH

Warns that an `include filename specifies an absolute path. This means the code will not work on any other system with a different file system layout. Instead of using absolute paths, relative paths (preferably without any directory specified whatsoever) should be used, and +incdir used on the command line to specify the top include source directories.

Disabled by default as this is a code style warning; it will simulate correctly.

INFINITELOOP

Warns that a while or for statement has a condition that is always true. and thus results in an infinite loop if the statement ever executes.

This might be unintended behavior if the loop body contains statements that in other simulators would make time pass, which Verilator is ignoring due to e.g. STMTDLY warnings being disabled.

Ignoring this warning will only suppress the lint check, it will simulate correctly (i.e. hang due to the infinite loop).

INITIALDLY

Warns that you have a delayed assignment inside of an initial or final block. If this message is suppressed, Verilator will convert this to a non-delayed assignment. See also the COMBDLY warning.

Ignoring this warning may make Verilator simulations differ from other simulators.

INSECURE

Warns that the combination of options selected may be defeating the attempt to protect/obscure identifiers or hide information in the model. Correct the options provided, or inspect the output code to see if the information exposed is acceptable.

Ignoring this warning will only suppress the lint check, it will simulate correctly.

LITENDIAN

Warns that a packed vector is declared with little endian bit numbering (i.e. [0:7]). Big endian bit numbering is now the overwhelming standard, and little numbering is now thus often due to simple oversight instead of intent.

Also warns that a cell is declared with little endian range (i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE the bits will likely be backwards from what you expect (i.e. cell [0] will connect to signal bit [N-1] not bit [0]).

Ignoring this warning will only suppress the lint check, it will simulate correctly.

MODDUP

Warns that a module has multiple definitions. Generally this indicates a coding error, or a mistake in a library file and it's good practice to have one module per file (and only put each file once on the command line) to avoid these issues. For some gate level netlists duplicates are sometimes unavoidable, and MODDUP should be disabled.

Ignoring this warning will cause the more recent module definition to be discarded.

MULTIDRIVEN

Warns that the specified signal comes from multiple always blocks. This is often unsupported by synthesis tools, and is considered bad style. It will also cause longer simulation runtimes due to reduced optimizations.

Ignoring this warning will only slow simulations, it will simulate correctly.

MULTITOP

Warns that there are multiple top level modules, that is modules not instantiated by any other module, and both modules were put on the command line (not in a library). Three likely cases:

1. A single module is intended to be the top. This warning then occurs because some low level cell is being read in, but is not really needed as part of the design. The best solution for this situation is to ensure that only the top module is put on the command line without any flags, and all remaining library files are read in as libraries with -v, or are automatically resolved by having filenames that match the module names.

2. A single module is intended to be the top, the name of it is known, and all other modules should be ignored if not part of the design. The best solution is to use the --top-module option to specify the top module's name. All other modules that are not part of the design will be for the most part ignored (they must be clean in syntax and their contents will be removed as part of the Verilog module elaboration process.)

3. Multiple modules are intended to be design tops, e.g. when linting a library file. As multiple modules are desired, disable the MULTITOP warning. All input/outputs will go uniquely to each module, with any conflicting and identical signal names being made unique by adding a prefix based on the top module name followed by __02E (a Verilator-encoded ASCII ".'). This renaming is done even if the two modules' signals seem identical, e.g. multiple modules with a "clk" input.

PINCONNECTEMPTY

Warns that a cell instantiation has a pin which is connected to .pin_name(), e.g. not another signal, but with an explicit mention of the pin. It may be desirable to disable PINCONNECTEMPTY, as this indicates intention to have a no-connect.

Disabled by default as this is a code style warning; it will simulate correctly.

PINMISSING

Warns that a module has a pin which is not mentioned in a cell instantiation. If a pin is not missing it should still be specified on the cell declaration with a empty connection, using "(.pin_name())".

Ignoring this warning will only suppress the lint check, it will simulate correctly.

PINNOCONNECT

Warns that a cell instantiation has a pin which is not connected to another signal.

Disabled by default as this is a code style warning; it will simulate correctly.

PROCASSWIRE

Error that a procedural assignment is setting a wire. According to IEEE, a var/reg must be used as the target of procedural assignments.

REALCVT

Warns that a real number is being implicitly rounded to an integer, with possible loss of precision.

REDEFMACRO

Warns that you have redefined the same macro with a different value, for example:

    `define MACRO def1
    //...
    `define MACRO otherdef

The best solution is to use a different name for the second macro. If this is not possible, add a undef to indicate the code is overriding the value:

    `define MACRO def1
    //...
    `undef MACRO
    `define MACRO otherdef
SELRANGE

Warns that a selection index will go out of bounds:

    wire vec[6:0];
    initial out = vec[7];  // There is no 7

Verilator will assume zero for this value, instead of X. Note that in some cases this warning may be false, when a condition upstream or downstream of the access means the access out of bounds will never execute or be used.

    wire vec[6:0];
    initial begin
        seven = 7;
        ...
        if (seven != 7) out = vec[seven];  // Never will use vec[7]
SHORTREAL

Warns that Verilator does not support "shortreal" and they will be automatically promoted to "real". The recommendation is to replace any "shortreal" in the code with "real", as "shortreal" is not widely supported across industry tools.

Ignoring this warning may make Verilator simulations differ from other simulators, if the increased precision of real affects your model or DPI calls.

SPLITVAR

Warns that a variable with a split_var metacomment was not split. Some possible reasons for this are:

* The datatype of the variable is not supported for splitting. (e.g. is a real).

* The access pattern of the variable can not be determined statically. (e.g. is accessed as a memory).

* The index of the array exceeds the array size.

* The variable is accessed from outside using dotted reference. (e.g. top.instance0.variable0 = 1).

* The variable is not declared in a module, but in a package or an interface.

* The variable is a parameter, localparam, genvar, or queue.

* The variable is tristate or bidirectional. (e.g. inout or ref).

STMTDLY

Warns that you have a statement with a delayed time in front of it, for example:

    #100 $finish;

Ignoring this warning may make Verilator simulations differ from other simulators.

SYMRSVDWORD

Warning that a symbol matches a C++ reserved word and using this as a symbol name would result in odd C++ compiler errors. You may disable this warning, but the symbol will be renamed by Verilator to avoid the conflict.

SYNCASYNCNET

Warns that the specified net is used in at least two different always statements with posedge/negedges (i.e. a flop). One usage has the signal in the sensitivity list and body, probably as an async reset, and the other usage has the signal only in the body, probably as a sync reset. Mixing sync and async resets is usually a mistake. The warning may be disabled with a lint_off pragma around the net, or either flopped block.

Disabled by default as this is a code style warning; it will simulate correctly.

TASKNSVAR

Error when a call to a task or function has a output from that task tied to a non-simple signal. Instead connect the task output to a temporary signal of the appropriate width, and use that signal to set the appropriate expression as the next statement. For example:

      task foo; output sig; ... endtask
      always @* begin
           foo(bus_we_select_from[2]);  // Will get TASKNSVAR error
      end

Change this to:

      reg foo_temp_out;
      always @* begin
           foo(foo_temp_out);
           bus_we_select_from[2] = foo_temp_out;
      end

Verilator doesn't do this conversion for you, as some more complicated cases would result in simulator mismatches.

TICKCOUNT

Warns that the number of ticks to delay a $past variable is greater than 10. At present Verilator effectively creates a flop for each delayed signals, and as such any large counts may lead to large design size increases.

Ignoring this warning will only slow simulations, it will simulate correctly.

TIMESCALEMOD

Error that `timescale is used in some but not all modules. Recommend using --timescale argument, or in front of all modules use:

   `include "timescale.vh"

Then in that file set the timescale.

This is an error due to IEEE specifications, but it may be disabled similar to warnings. Ignoring this error may result in a module having an unexpected timescale.

UNDRIVEN

Warns that the specified signal has no source. Verilator is fairly liberal in the usage calculations; making a signal public, or setting only a single array element marks the entire signal as driven.

Disabled by default as this is a code style warning; it will simulate correctly.

UNOPT

Warns that due to some construct, optimization of the specified signal or block is disabled. The construct should be cleaned up to improve simulation performance.

A less obvious case of this is when a module instantiates two submodules. Inside submodule A, signal I is input and signal O is output. Likewise in submodule B, signal O is an input and I is an output. A loop exists and a UNOPT warning will result if AI & AO both come from and go to combinatorial blocks in both submodules, even if they are unrelated always blocks. This affects performance because Verilator would have to evaluate each submodule multiple times to stabilize the signals crossing between the modules.

Ignoring this warning will only slow simulations, it will simulate correctly.

UNOPTFLAT

Warns that due to some construct, optimization of the specified signal is disabled. The signal reported includes a complete scope to the signal; it may be only one particular usage of a multiply instantiated block. The construct should be cleaned up to improve simulation performance; two times better performance may be possible by fixing these warnings.

Unlike the UNOPT warning, this occurs after flattening the netlist, and indicates a more basic problem, as the less obvious case described under UNOPT does not apply.

Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by synthesis which analyzes interconnection per-bit, but is circular to simulation which analyzes per-bus:

      wire [2:0] x = {x[1:0], shift_in};

This statement needs to be evaluated multiple times, as a change in "shift_in" requires "x" to be computed 3 times before it becomes stable. This is because a change in "x" requires "x" itself to change value, which causes the warning.

For significantly better performance, split this into 2 separate signals:

      wire [2:0] xout = {x[1:0], shift_in};

and change all receiving logic to instead receive "xout". Alternatively, change it to

      wire [2:0] x = {xin[1:0], shift_in};

and change all driving logic to instead drive "xin".

With this change this assignment needs to be evaluated only once. These sort of changes may also speed up your traditional event driven simulator, as it will result in fewer events per cycle.

The most complicated UNOPTFLAT path we've seen was due to low bits of a bus being generated from an always statement that consumed high bits of the same bus processed by another series of always blocks. The fix is the same; split it into two separate signals generated from each block.

Another way to resolve this warning is to add a split_var metacomment described above. This will cause the variable to be split internally, potentially resolving the conflict. If you run with --report-unoptflat Verilator will suggest possible candidates for split_var.

The UNOPTFLAT warning may also be due to clock enables, identified from the reported path going through a clock gating cell. To fix these, use the clock_enable meta comment described above.

The UNOPTFLAT warning may also occur where outputs from a block of logic are independent, but occur in the same always block. To fix this, use the isolate_assignments meta comment described above.

To assist in resolving UNOPTFLAT, the option --report-unoptflat can be used, which will provide suggestions for variables that can be split up, and a graph of all the nodes connected in the loop. See the Arguments section for more details.

Ignoring this warning will only slow simulations, it will simulate correctly.

UNOPTTHREADS

Warns that the thread scheduler was unable to partition the design to fill the requested number of threads.

One workaround is to request fewer threads with --threads.

Another possible workaround is to allow more MTasks in the simulation runtime, by increasing the value of --threads-max-mtasks. More MTasks will result in more communication and synchronization overhead at simulation runtime; the scheduler attempts to minimize the number of MTasks for this reason.

Ignoring this warning will only slow simulations, it will simulate correctly.

UNPACKED

Warns that unpacked structs and unions are not supported.

Ignoring this warning will make Verilator treat the structure as packed, which may make Verilator simulations differ from other simulators. This downgrading may also result what would normally be a legal unpacked struct/array inside an unpacked struct/array becoming an illegal unpacked struct/array inside a packed struct/array.

UNSIGNED

Warns that you are comparing a unsigned value in a way that implies it is signed, for example "X < 0" will always be false when X is unsigned.

Ignoring this warning will only suppress the lint check, it will simulate correctly.

UNSUPPORTED

UNSUPPORTED is an error that the construct might be legal according to IEEE but is not currently supported.

This error may be ignored with --bbox-unsup, however this will make the design simulate incorrectly; see the details under --bbox-unsup.

UNUSED

Warns that the specified signal is never used/consumed. Verilator is fairly liberal in the usage calculations; making a signal public, a signal matching --unused-regexp ("*unused*") or accessing only a single array element marks the entire signal as used.

Disabled by default as this is a code style warning; it will simulate correctly.

A recommended style for unused nets is to put at the bottom of a file code similar to the following:

    wire _unused_ok = &{1'b0,
                        sig_not_used_a,
                        sig_not_used_yet_b,  // To be fixed
                        1'b0};

The reduction AND and constant zeros mean the net will always be zero, so won't use simulation runtime. The redundant leading and trailing zeros avoid syntax errors if there are no signals between them. The magic name "unused" (-unused-regexp) is recognized by Verilator and suppresses warnings; if using other lint tools, either teach it to the tool to ignore signals with "unused" in the name, or put the appropriate lint_off around the wire. Having unused signals in one place makes it easy to find what is unused, and reduces the number of lint_off pragmas, reducing bugs.

USERINFO, USERWARN, USERERROR, USERFATAL

A SystemVerilog elaboration-time assertion print was executed.

VARHIDDEN

Warns that a task, function, or begin/end block is declaring a variable by the same name as a variable in the upper level module or begin/end block (thus hiding the upper variable from being able to be used.) Rename the variable to avoid confusion when reading the code.

Disabled by default as this is a code style warning; it will simulate correctly.

WIDTH

Warns that based on width rules of Verilog, two operands have different widths. Verilator generally can intuit the common usages of widths, and you shouldn't need to disable this message like you do with most lint programs. Generally other than simple mistakes, you have two solutions:

If it's a constant 0 that's 32 bits or less, simply leave it unwidthed. Verilator considers zero to be any width needed.

Concatenate leading zeros when doing arithmetic. In the statement

        wire [5:0] plus_one = from[5:0] + 6'd1 + carry[0];

The best fix, which clarifies intent and will also make all tools happy is:

        wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0, carry[0]};

Ignoring this warning will only suppress the lint check, it will simulate correctly.

WIDTHCONCAT

Warns that based on width rules of Verilog, a concatenate or replication has an indeterminate width. In most cases this violates the Verilog rule that widths inside concatenates and replicates must be sized, and should be fixed in the code.

    wire [63:0] concat = {1, 2};

An example where this is technically legal (though still bad form) is:

    parameter PAR = 1;
    wire [63:0] concat = {PAR, PAR};

The correct fix is to either size the 1 ("32'h1"), or add the width to the parameter definition ("parameter [31:0]"), or add the width to the parameter usage ("{PAR[31:0],PAR[31:0]}".

The following describes the less obvious errors:

Internal Error

This error should never occur first, though may occur if earlier warnings or error messages have corrupted the program. If there are no other warnings or errors, submit a bug report.

Unsupported: ....

This error indicates that you are using a Verilog language construct that is not yet supported in Verilator. See the Limitations chapter.

DEPRECATIONS

The following deprecated items are scheduled for future removal:

Pre-C++11 compiler support

Verilator supports pre-C++11 compilers for non-threaded models when configured with --enable-prec11/--enable-prec11-final. This flag will be removed and C++11 compilers will be required for both compiling Verilator and compiling Verilated models no sooner than September 2020.

SystemC 2.2 and earlier support

Support for SystemC versions 2.2 and earlier including the related sc_clock variable attribute will be removed no sooner than September 2020. The supported versions will be SystemC 2.3.0 (SYSTEMC_VERSION 20111121) and later (presently 2.3.0, 2.3.1, 2.3.2, 2.3.3).

Configuration File -msg

The -msg argument to lint_off has been replaced with -rule. -msg is planned for removal no sooner than January 2021.

XML locations

The XML fl attribute has been replaced with loc. fl is planned for removal no sooner than January 2021.

FAQ/FREQUENTLY ASKED QUESTIONS

Can I contribute?

Please contribute! Just submit a pull request, or raise an issue to discuss if looking for something to help on. For more information see our contributor agreement.

How widely is Verilator used?

Verilator is used by many of the largest silicon design companies, and all the way down to college projects. Verilator is one of the "big 4" simulators, meaning one of the 4 main SystemVerilog simulators available, namely the commercial products Synopsys VCS (tm), Mentor Questa/ModelSim (tm), Cadence Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. The three commercial offerings are often collectively called the "big 3" simulators.

Does Verilator run under Windows?

Yes, using Cygwin. Verilated output also compiles under Microsoft Visual C++, but this is not tested every release.

Can you provide binaries?

You can install Verilator via the system package manager (apt, yum, etc.) on many Linux distributions, including Debian, Ubuntu, SuSE, Fedora, and others. These packages are provided by the Linux distributions and generally will lag the version of the mainline Verilator repository. If no binary package is available for your distribution, how about you set one up? Please contact the authors for assistance.

How can it be faster than (name-a-big-3-closed-source-simulator)?

Generally, the implied part of the question is "... with all of the manpower they can put into developing it."

Most simulators have to be compliant with the complete IEEE 1364 (Verilog) and IEEE 1800 (SystemVerilog) standards, meaning they have to be event driven. This prevents them from being able to reorder blocks and make netlist-style optimizations, which are where most of the gains come from.

You should not be scared by non-compliance. Your synthesis tool isn't compliant with the whole standard to start with, so your simulator need not be either. Verilator is closer to the synthesis interpretation, so this is a good thing for getting working silicon.

Will Verilator output remain under my own license?

Yes, it's just like using GCC on your programs; this is why Verilator uses the "GNU *Lesser* Public License Version 3" instead of the more typical "GNU Public License". See the licenses for details, but in brief, if you change Verilator itself or the header files Verilator includes, you must make the source code available under the GNU Lesser Public License. However, Verilator output (the Verilated code) only "include"s the licensed files, and so you are NOT required to release any output from Verilator.

You also have the option of using the Perl Artistic License, which again does not require you to release your Verilog or generated code, and also allows you to modify Verilator for internal use without distributing the modified version. But please contribute back to the community!

One limit is that you cannot under either license release a commercial Verilog simulation product incorporating Verilator without making the source code available.

As is standard with Open Source, contributions back to Verilator will be placed under the Verilator copyright and LGPL/Artistic license. Small test cases will be released into the public domain so they can be used anywhere, and large tests under the LGPL/Artistic, unless requested otherwise.

Why is running Verilator (to create a model) so slow?

Verilator needs more memory than the resulting simulator will require, as Verilator internally creates all of the state of the resulting generated simulator in order to optimize it. If it takes more than a few minutes or so (and you're not using --debug since debug mode is disk bound), see if your machine is paging; most likely you need to run it on a machine with more memory. Very large designs are known to have topped 16GB resident set size.

How do I generate waveforms (traces) in C++?

See the next question for tracing in SystemC mode.

A. Add the --trace switch to Verilator, and in your top level C code, call Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to enable traces, same as with any Verilog simulator. See examples/make_tracing_c.

B. Or, for finer-grained control, or C++ files with multiple Verilated modules you may also create the trace purely from C++. Create a VerilatedVcdC object, and in your main loop call "trace_object->dump(time)" every time step, and finally call "trace_object->close()". You also need to compile verilated_vcd_c.cpp and add it to your link, preferably by adding the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule. This is done for you if using the Verilator --exe flag. Note you can also call ->trace on multiple Verilated objects with the same trace file if you want all data to land in the same output file.

    #include "verilated_vcd_c.h"
    ...
    int main(int argc, char** argv, char** env) {
        ...
        Verilated::traceEverOn(true);
        VerilatedVcdC* tfp = new VerilatedVcdC;
        topp->trace(tfp, 99);  // Trace 99 levels of hierarchy
        tfp->open("obj_dir/t_trace_ena_cc/simx.vcd");
        ...
        while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
            main_time += #;
            tfp->dump(main_time);
        }
        tfp->close();
    }
How do I generate waveforms (traces) in SystemC?

A. Add the --trace switch to Verilator, and in your top level sc_main, call Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to enable traces, same as with any Verilog simulator, see the non-SystemC example in examples/make_tracing_c. This will trace only the module containing the $dumpvar.

B. Or, you may create a trace purely from SystemC, which may trace all Verilated designs in the SystemC model. Create a VerilatedVcdSc object as you would create a normal SystemC trace file. For an example, see the call to VerilatedVcdSc in the examples/make_tracing_sc/sc_main.cpp file of the distribution, and below.

Alternatively you may use the C++ trace mechanism described in the previous question, note the timescale and timeprecision will be inherited from your SystemC settings.

You also need to compile verilated_vcd_sc.cpp and verilated_vcd_c.cpp and add them to your link, preferably by adding the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule. This is done for you if using the Verilator --exe flag.

Note you can also call ->trace on multiple Verilated objects with the same trace file if you want all data to land in the same output file.

When using SystemC 2.3, the SystemC library must have been built with the experimental simulation phase callback based tracing disabled. This is disabled by default when building SystemC with its configure based build system, but when building SystemC with CMake, you must pass -DENABLE_PHASE_CALLBACKS_TRACING=OFF to disable this feature.

    #include "verilated_vcd_sc.h"
    ...
    int main(int argc, char** argv, char** env) {
        ...
        Verilated::traceEverOn(true);
        VerilatedVcdSc* tfp = new VerilatedVcdSc;
        topp->trace(tfp, 99);  // Trace 99 levels of hierarchy
        tfp->open("obj_dir/t_trace_ena_cc/simx.vcd");
        ...
        sc_start(1);
        ...
        tfp->close();
    }
How do I generate FST waveforms (traces) in C++?

FST is a trace file format developed by GTKWave. Verilator provides basic FST support. To dump traces in FST format, add the --trace-fst switch to Verilator and either A. use $dumpfile/$dumpvars in Verilog as described in the VCD example above, or B. in C++ change the include described in the VCD example above:

    #include "verilated_fst_c.h"
    VerilatedFstC* tfp = new VerilatedFstC;

Note that currently supporting both FST and VCD in a single simulation is impossible, but such requirement should be rare. You can however ifdef around the trace format in your C++ main loop, and select VCD or FST at build time, should you require.

How do I generate FST waveforms (aka dumps or traces) in SystemC?

The FST library from GTKWave does not currently support SystemC; use VCD format instead.

How do I view waveforms (aka dumps or traces)?

Verilator creates standard VCD (Value Change Dump) and FST files. VCD files are viewable with the open source GTKWave (recommended) or Dinotrace (legacy) programs, or any of the many closed-source offerings; FST is supported only by GTKWave.

How do I reduce the size of large waveform (trace) files?

First, instead of calling VerilatedVcdC->open at the beginning of time, delay calling it until the time stamp where you want tracing to begin. Likewise you can also call VerilatedVcdC->open before the end of time (perhaps a short period after you detect a verification error).

Next, add /*verilator tracing_off*/ to any very low level modules you never want to trace (such as perhaps library cells). Finally, use the --trace-depth option to limit the depth of tracing, for example --trace-depth 1 to see only the top level signals.

Also be sure you write your trace files to a local solid-state drive, instead of to a network drive. Network drives are generally far slower.

You can also consider using FST tracing instead of VCD. FST dumps are a fraction of the size of the equivalent VCD. FST tracing can be slower than VCD tracing, but it might be the only option if the VCD file size is prohibitively large.

How do I do coverage analysis?

Verilator supports both block (line) coverage and user inserted functional coverage.

First, run verilator with the --coverage option. If you are using your own makefile, compile the model with the GCC flag -DVM_COVERAGE (if using the makefile provided by Verilator, it will do this for you).

At the end of your test, call VerilatedCov::write passing the name of the coverage data file (typically "logs/coverage.dat").

Run each of your tests in different directories. Each test will create a logs/coverage.dat file.

After running all of your tests, execute the verilator_coverage tool. The verilator_coverage tool reads the logs/coverage.dat file(s), and creates an annotated source code listing showing code coverage details.

For an example, after running 'make test' in the Verilator distribution, see the examples/make_tracing_c/logs directory. Grep for lines starting with '%' to see what lines Verilator believes need more coverage.

Info files can be written by verilator_coverage for import to lcov. This enables use of genhtml for HTML reports and importing reports to sites such as https://codecov.io.

Where is the translate_off command? (How do I ignore a construct?)

Translate on/off pragmas are generally a bad idea, as it's easy to have mismatched pairs, and you can't see what another tool sees by just preprocessing the code. Instead, use the preprocessor; Verilator defines the "VERILATOR" define for you, so just wrap the code in an ifndef region:

   `ifndef VERILATOR
      Something_Verilator_Dislikes;
   `endif

Most synthesis tools similarly define SYNTHESIS for you.

Why do I get "unexpected do" or "unexpected bit" errors?

The words do, bit, ref, return, and others are reserved keywords in SystemVerilog. Older Verilog code might use these as identifiers. You should change your code to not use them to ensure it works with newer tools. Alternatively, surround them by the Verilog 2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code.

   `begin_keywords "1364-2001"
      integer bit; initial bit = 1;
   `end_keywords

If you want the whole design to be parsed as Verilog 2001, please see the --default-language option.

How do I prevent my assertions from firing during reset?

Call Verilated::assertOn(false) before you first call the model, then turn it back on after reset. It defaults to true. When false, all assertions controlled by --assert are disabled.

Why do I get "undefined reference to `sc_time_stamp()'"?

In C++ (non SystemC) code you need to define this function so that the simulator knows the current time. See the "CONNECTING TO C++" examples.

Why do I get "undefined reference to `VL_RAND_RESET_I' or `Verilated::...'"?

You need to link your compiled Verilated code against the verilated.cpp file found in the include directory of the Verilator kit. This is one target in the $(VK_GLOBAL_OBJS) make variable, which should be part of your Makefile's link rule. If you use --exe, this is done for you.

Is the PLI supported?

Only somewhat. More specifically, the common PLI-ish calls $display, $finish, $stop, $time, $write are converted to C++ equivalents. You can also use the "import DPI" SystemVerilog feature to call C code (see the chapter above). There is also limited VPI access to public signals.

If you want something more complex, since Verilator emits standard C++ code, you can simply write your own C++ routines that can access and modify signal values without needing any PLI interface code, and call it with $c("{any_c++_statement}").

How do I make a Verilog module that contain a C++ object?

You need to add the object to the structure that Verilator creates, then use $c to call a method inside your object. The test_regress/t/t_extend_class files show an example of how to do this.

How do I get faster build times?

When running make pass the make variable VM_PARALLEL_BUILDS=1 so that builds occur in parallel. Note this is now set by default if an output file was large enough to be split due to the --output-split option.

Verilator emits any infrequently executed "cold" routines into separate __Slow.cpp files. This can accelerate compilation as optimization can be disabled on these routines. See the OPT_FAST and OPT_SLOW make variables and the BENCHMARKING & OPTIMIZATION section of the manual.

Use a recent compiler. Newer compilers tend to be faster.

Compile in parallel on many machines and use caching; see the web for the ccache, distcc and icecream packages. ccache will skip GCC runs between identical source builds, even across different users. If ccache was installed when Verilator was built it is used, or see OBJCACHE environment variable to override this. Also see the --output-split option.

To reduce the compile time of classes that use a Verilated module (e.g. a top CPP file) you may wish to add /*verilator no_inline_module*/ to your top level module. This will decrease the amount of code in the model's Verilated class, improving compile times of any instantiating top level C++ code, at a relatively small cost of execution performance.

Why do so many files need to recompile when I add a signal?

Adding a new signal requires the symbol table to be recompiled. Verilator uses one large symbol table, as that results in 2-3 less assembly instructions for each signal access. This makes the execution time 10-15% faster, but can result in more compilations when something changes.

How do I access Verilog functions/tasks in C?

Use the SystemVerilog Direct Programming Interface. You write a Verilog function or task with input/outputs that match what you want to call in with C. Then mark that function as a DPI export function. See the DPI chapter in the IEEE Standard.

How do I access C++ functions/tasks in Verilog?

Use the SystemVerilog Direct Programming Interface. You write a Verilog function or task with input/outputs that match what you want to call in with C. Then mark that function as a DPI import function. See the DPI chapter in the IEEE Standard.

How do I access signals in C?

The best thing to do is to make a SystemVerilog "export DPI" task or function that accesses that signal, as described in the DPI chapter in the manual and DPI tutorials on the web. This will allow Verilator to better optimize the model and should be portable across simulators.

If you really want raw access to the signals, declare the signals you will be accessing with a /*verilator public*/ comment before the closing semicolon. Then scope into the C++ class to read the value of the signal, as you would any other member variable.

Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t), 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or 64-bit unsigned long longs (uint64_t) that fits the width of the signal. Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for 1 to 64 bits, and the compiler will properly up-convert smaller entities. Note even signed ports are declared as unsigned; you must sign extend yourself to the appropriate signal width.

Signals wider than 64 bits are stored as an array of 32-bit uint32_t's. Thus to read bits 31:0, access signal[0], and for bits 63:32, access signal[1]. Unused bits (for example bit numbers 65-96 of a 65-bit vector) will always be zero. If you change the value you must make sure to pack zeros in the unused bits or core-dumps may result, because Verilator strips array bound checks where it believes them to be unnecessary to improve performance.

In the SYSTEMC example above, if you had in our.v:

    input clk /*verilator public*/;
    // Note the placement of the semicolon above

From the sc_main.cpp file, you'd then:

    #include "Vour.h"
    #include "Vour_our.h"
    cout << "clock is " << top->our->clk << endl;

In this example, clk is a bool you can read or set as any other variable. The value of normal signals may be set, though clocks shouldn't be changed by your code or you'll get strange results.

Should a module be in Verilog or SystemC?

Sometimes there is a block that just interconnects cells, and have a choice as to if you write it in Verilog or SystemC. Everything else being equal, best performance is when Verilator sees all of the design. So, look at the hierarchy of your design, labeling cells as to if they are SystemC or Verilog. Then:

A module with only SystemC cells below must be SystemC.

A module with a mix of Verilog and SystemC cells below must be SystemC. (As Verilator cannot connect to lower-level SystemC cells.)

A module with only Verilog cells below can be either, but for best performance should be Verilog. (The exception is if you have a design that is instantiated many times; in this case Verilating one of the lower modules and instantiating that Verilated cells multiple times into a SystemC module *may* be faster.)

BUGS

First, check the "LANGUAGE LIMITATIONS" section.

Next, try the --debug switch. This will enable additional internal assertions, and may help identify the problem.

Finally, reduce your code to the smallest possible routine that exhibits the bug. Even better, create a test in the test_regress/t directory, as follows:

    cd test_regress
    cp -p t/t_EXAMPLE.pl t/t_BUG.pl
    cp -p t/t_EXAMPLE.v t/t_BUG.v

There are many hints on how to write a good test in the driver.pl documentation which can be seen by running:

    cd $VERILATOR_ROOT  # Need the original distribution kit
    test_regress/driver.pl --help

Edit t/t_BUG.pl to suit your example; you can do anything you want in the Verilog code there; just make sure it retains the single clk input and no outputs. Now, the following should fail:

    cd $VERILATOR_ROOT  # Need the original distribution kit
    cd test_regress
    t/t_BUG.pl  # Run on Verilator
    t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator
    t/t_BUG.pl --vcs  # Run on VCS simulator
    t/t_BUG.pl --nc|--iv|--ghdl  # Likewise on other simulators

The test driver accepts a number of options, many of which mirror the main Verilator option. For example the previous test could have been run with debugging enabled. The full set of test options can be seen by running driver.pl --help as shown above.

Finally, report the bug using the bug tracker at https://verilator.org/issues. The bug will become publicly visible; if this is unacceptable, mail the bug report to wsnyder@wsnyder.org.

HISTORY

Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at Digital Equipment Corporation. The Verilog code that was converted to C was then merged with a C based CPU model of the Alpha processor and simulated in a C based environment called CCLI.

In 1995 Verilator started being used also for Multimedia and Network Processor development inside Digital. Duane Galbi took over active development of Verilator, and added several performance enhancements. CCLI was still being used as the shell.

In 1998, through the efforts of existing DECies, mainly Duane Galbi, Digital graciously agreed to release the source code. (Subject to the code not being resold, which is compatible with the GNU Public License.)

In 2001, Wilson Snyder took the kit, and added a SystemC mode, and called it Verilator2. This was the first packaged public release.

In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from scratch in C++. This added many optimizations, yielding about a 2-5x performance gain.

In 2009, major SystemVerilog and DPI language support was added.

In 2018, Verilator 4.000 was released with multithreaded support.

Currently, various language features and performance enhancements are added as the need arises. Verilator is now about 3x faster than in 2002, and is faster than most (if not every) other simulator.

AUTHORS

When possible, please instead report bugs to https://verilator.org/issues.

Wilson Snyder <wsnyder@wsnyder.org>

Major concepts by Paul Wasson, Duane Galbi, John Coiner and Jie Xu.

CONTRIBUTORS

Many people have provided ideas and other assistance with Verilator.

Verilator is receiving major development support from the CHIPS Alliance.

Previous major corporate sponsors of Verilator, by providing significant contributions of time or funds included include Atmel Corporation, Cavium Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc., and SiCortex Inc.

The people who have contributed major functionality are Byron Bradley, Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, and Wilson Snyder. Major testers included Jeff Dutton, Jonathon Donaldson, Ralf Karge, David Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van Cauwenberghe, Gene Weber, and Clifford Wolf.

Some of the people who have provided ideas, and feedback for Verilator include: David Addison, Tariq B. Ahmad, Nikana Anastasiadis, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew Barr, Geoff Barrett, Julius Baxter, Jeremy Bennett, Michael Berman, Victor Besyakov, Moinak Bhattacharyya, David Binderman, Piotr Binkowski, Johan Bjork, David Black, Tymoteusz Blazejczyk, Daniel Bone, Gregg Bouchard, Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Maarten De Braekeleer, Charlie Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, Tony Bybell, Ted Campbell, Chris Candler, Lauren Carlson, Donal Casey, Sebastien Van Cauwenberghe, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean Cross, George Cuan, Joe DErrico, Lukasz Dalek, Laurens van Dam, Gunter Dannoritzer, Ashutosh Das, Bernard Deadman, John Demme, Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Leendert van Doorn, Sebastian Dressler, Alex Duller, Jeff Dutton, Tomas Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein, Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner, Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Amir Gonnen, Chitlesh Goorah, Kai Gossner, Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto, Thomas Hawkins, Mitch Hayenga, Robert Henry, Stephen Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki Honda, Alex Hornung, David Horton, Peter Horvath, Jae Hossell, Alan Hunter, James Hutchinson, Jamie Iles, Ben Jackson, Shareef Jalloq, Krzysztof Jankowski, HyungKi Jeong, Iztok Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Ralf Karge, Dan Katz, Sol Katzman, Ian Kennedy, Jonathan Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot Koch, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, Will Korteland, Wojciech Koszek, Varun Koyyalagunta, David Kravitz, Roland Kruse, Sergey Kvachonok, Charles Eric LaForest, Ed Lander, Steve Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor Lesik, John Li, Eivind Liland, Yu Sheng Lin, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan Lussier, Fred Ma, Duraid Madina, Affe Mao, Julien Margetts, Mark Marshall, Alfonso Martinez, Yves Mathieu, Patrick Maupin, Jason McMullan, Elliot Mednick, Wim Michiels, Miodrag Milanovic, Wai Sum Mong, Peter Monsson, Sean Moore, Dennis Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris Nalbantis, Peter Nelson, Bob Newgard, Cong Van Nguyen, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Aleksander Osman, James Pallister, Vassilis Papaefstathiou, Brad Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter, Niranjan Prabhu, Usha Priyadharshini, Mark Jackson Pulver, Prateek Puri, Marshal Qiao, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Odd Magne Reitan, Frederic Requin, Frederick Requin, Dustin Richmond, Alberto Del Rio, Eric Rippey, Oleg Rodionov, Ludwig Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Jan Egil Ruud, Denis Rystsov, John Sanguinetti, Galen Seitz, Salman Sheikh, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Anderson Ignacio Da Silva, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson, Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki, Howard Su, Emerson Suguimoto, Gene Sullivan, Qingyao Sun, Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede, Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, Viktor Tomov, Steve Tong, Michael Tresidder, Neil Turton, Srini Vemuri, Yuri Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene Weber, David Welch, Thomas J Whatson, Marco Widmer, Leon Wildman, Daniel Wilkerson, Gerald Williams, Trevor Williams, Jan Van Winkel, Jeff Winston, Joshua Wise, Clifford Wolf, Tobias Wolfel, Johan Wouters, Junyi Xi, Ding Xiaoliang, Jie Xu, Mandy Xu, Takatsukasa Y, Luke Yang, and Amir Yazdanbakhsh.

Thanks to them, and all those we've missed including above, or wished to remain anonymous.

DISTRIBUTION

The latest version is available from https://verilator.org.

Copyright 2003-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

All Verilog and C++/SystemC code quoted within this documentation file are released as Creative Commons Public Domain (CC0). Many example files and test files are likewise released under CC0 into effectively the Public Domain as described in the files themselves.

SEE ALSO

verilator_coverage, verilator_gantt, verilator_profcfunc, make,

"verilator --help" which is the source for this document,

and docs/internals.adoc in the distribution.

verilator-4.038/bin/0000775000177100017500000000000013702335701014265 5ustar wsnyderwsnyderverilator-4.038/bin/verilator_profcfunc0000775000177100017500000001701213702133367020274 0ustar wsnyderwsnyder#!/usr/bin/env perl # See copyright, etc in below POD section. ###################################################################### require 5.006_001; use warnings; use Getopt::Long; use IO::File; use Pod::Usage; eval { use Data::Dumper; $Data::Dumper::Indent = 1; }; # Debug, ok if missing use strict; use vars qw($Debug); #====================================================================== #====================================================================== # main $Debug = 0; my $Opt_File; autoflush STDOUT 1; autoflush STDERR 1; Getopt::Long::config("no_auto_abbrev"); if (! GetOptions( "help" => \&usage, "debug" => \&debug, "<>" => \¶meter, )) { die "%Error: Bad usage, try 'verilator_profcfunc --help'\n"; } defined $Opt_File or die "%Error: No filename given\n"; profcfunc($Opt_File); #---------------------------------------------------------------------- sub usage { pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT); exit(1); # Unreachable } sub debug { $Debug = 1; } sub parameter { my $param = shift; if (!defined $Opt_File) { $Opt_File = $param; } else { die "%Error: Unknown parameter: $param\n"; } } ####################################################################### sub profcfunc { my $filename = shift; # Remove hex numbers before diffing my $fh = IO::File->new ($filename) or die "%Error: $! $filename,"; my %funcs; while (defined (my $line=$fh->getline())) { # %time cumesec selfsec calls {stuff} name if ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) { my $pct=$1; my $sec=$2; my $calls=$3; my $func=$4; $funcs{$func}{pct} += $pct; $funcs{$func}{sec} += $sec; $funcs{$func}{calls} += $calls; } # Older gprofs have no call column for single-call functions # %time cumesec selfsec {stuff} name elsif ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) { my $pct=$1; my $sec=$2; my $calls=1; my $func=$3; $funcs{$func}{pct} += $pct; $funcs{$func}{sec} += $sec; $funcs{$func}{calls} += $calls; } } $fh->close; # Find modules my %pointer_mods; my %verilated_mods; foreach my $func (keys %funcs) { if ($func =~ /(.*)::_eval\(([a-zA-Z_0-9]+__Syms).*\)$/) { $verilated_mods{$1} = qr/^$1/; $pointer_mods{$2} = $1; } } #print Dumper(\%pointer_mods, \%verilated_mods); # Resort by Verilog name my %vfuncs; my %groups; foreach my $func (keys %funcs) { my $pct = $funcs{$func}{pct}; my $vfunc = $func; my $design; if ($func =~ /\(([a-zA-Z_0-9]+__Syms)/) { $design = $pointer_mods{$1}; } foreach my $vde (keys %verilated_mods) { last if $design; if ($func =~ /$verilated_mods{$vde}/) { $design=$vde; last; } } if ($vfunc =~ /__PROF__([a-zA-Z_0-9]+)__l?([0-9]+)\(/) { $vfunc = sprintf("VBlock %s:%d", $1, $2); $groups{type}{"Verilog Blocks under $design"} += $pct; $groups{design}{$design} += $pct; $groups{module}{$1} += $pct; } else { if ($design) { $vfunc = sprintf("VCommon %s", $func); $groups{type}{"Common code under $design"} += $pct; $groups{design}{$design} += $pct; $groups{module}{$design." common code"} += $pct; } elsif ($func =~ /^VL_[A-Z0-9_]+/ || $func =~ /^_?vl_[a-zA-Z0-9_]+/ || $func =~ /^verilated/i) { $vfunc = sprintf("VLib %s", $func); $groups{type}{'VLib'} += $pct; $groups{design}{'VLib'} += $pct; $groups{module}{'VLib'} += $pct; } elsif ($func =~ /^_mcount_private/) { $vfunc = sprintf("Prof %s", $func); $groups{type}{'Prof'} += $pct; $groups{design}{'Prof'} += $pct; $groups{module}{'Prof'} += $pct; } else { $vfunc = sprintf("C++ %s", $func); $groups{type}{'C++'} += $pct; $groups{design}{'C++'} += $pct; $groups{module}{'C++'} += $pct; } } $vfuncs{$vfunc} = $funcs{$func}; } foreach my $type (qw(type design module)) { my $missing = 100; foreach (sort (keys %{$groups{$type}})) { $missing -= $groups{$type}{$_}; } if ($missing) { $groups{$type}{"\377Unaccounted for/rounding error"} = $missing; } print("Overall summary by $type:\n"); printf(" %-6s %s\n","% time",$type); foreach my $what (sort (keys %{$groups{$type}})) { (my $pwhat = $what) =~ s/^\377//; # Just used to establish sort order printf(" %6.2f %s\n", $groups{$type}{$what}, $pwhat); } print("\n"); } print("Verilog code profile:\n"); print(" These are split into three categories:\n"); print(" C++: Time in non-Verilated C++ code\n"); print(" Prof: Time in profile overhead\n"); print(" VBlock: Time attributable to a block in a Verilog file and line\n"); print(" VCommon: Time in a Verilated module, due to all parts of the design\n"); print(" VLib: Time in Verilated common libraries, called by the Verilated code\n"); print("\n"); print(" % cumulative self \n"); print(" time seconds seconds calls type filename and line number\n"); my $cume = 0; foreach my $func (sort {$vfuncs{$b}{sec} <=> $vfuncs{$a}{sec} || $a cmp $b} (keys %vfuncs)) { $cume += $vfuncs{$func}{sec}; printf +("%6.2f %9.2f %8.2f %8d %s\n", $vfuncs{$func}{pct}, $cume, $vfuncs{$func}{sec}, $vfuncs{$func}{calls}, $func); } } ####################################################################### __END__ =pod =head1 NAME verilator_profcfunc - Read gprof report created with --prof-cfuncs =head1 SYNOPSIS verilator --prof-cfuncs .... gcc --ggdb -pg .... {run executable} gprof verilator_profcfuncs gprof.out =head1 DESCRIPTION Verilator_profcfunc reads a profile report created by gprof. The names of the functions are then transformed, assuming the user used Verilator's --prof-cfuncs, and a report printed showing the percentage of time, etc, in each Verilog block. =head1 ARGUMENTS =over 4 =item --help Displays this message and program version and exits. =back =head1 DISTRIBUTION The latest version is available from L. Copyright 2007-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS Wilson Snyder =head1 SEE ALSO C =cut ###################################################################### ### Local Variables: ### compile-command: "$V4/bin/verilator_profcfunc $V4/test_c/obj_dir/V*_03_*.tree $V4N/test_c/obj_dir/V*_03_*.tree" ### End: verilator-4.038/bin/verilator_coverage0000775000177100017500000002170713702133367020110 0ustar wsnyderwsnyder#!/usr/bin/env perl ###################################################################### # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # ###################################################################### require 5.006_001; use warnings; use Getopt::Long; use FindBin qw($RealBin $RealScript); use IO::File; use Pod::Usage; use Cwd qw(abs_path getcwd); use strict; use vars qw($Debug @Opt_Verilator_Sw); ####################################################################### ####################################################################### # main autoflush STDOUT 1; autoflush STDERR 1; $Debug = 0; # No arguments can't do anything useful. Give help if ($#ARGV < 0) { pod2usage(-exitstatus=>2, -verbose=>0); } # We sneak a look at the flags so we can do some pre-environment checks # All flags will hit verilator... foreach my $sw (@ARGV) { $sw = "'$sw'" if $sw =~ m![^---a-zA-Z0-9_/\\:.+]!; push @Opt_Verilator_Sw, $sw; } Getopt::Long::config("no_auto_abbrev","pass_through"); if (! GetOptions ( # Major operating modes "help" => \&usage, "debug:s" => \&debug, # "version!" => \&version, # Also passthru'ed # Additional parameters "<>" => sub {}, # Ignored )) { pod2usage(-exitstatus=>2, -verbose=>0); } # Normal, non gdb run(verilator_coverage_bin() ." ".join(' ',@Opt_Verilator_Sw)); #---------------------------------------------------------------------- sub usage { pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT); } sub debug { shift; my $level = shift; $Debug = $level||3; } ####################################################################### ####################################################################### # Builds sub verilator_coverage_bin { my $bin = ""; # Use VERILATOR_ROOT if defined, else assume verilator_bin is in the search path my $basename = ($ENV{VERILATOR_COVERAGE_BIN} || "verilator_coverage_bin_dbg"); if (defined($ENV{VERILATOR_ROOT})) { my $dir = $ENV{VERILATOR_ROOT}; if (-x "$dir/bin/$basename" || -x "$dir/bin/$basename.exe") { # From a "make install" into VERILATOR_ROOT $bin = "$dir/bin/$basename"; } else { $bin = "$dir/$basename"; # From pointing to kit directory } } else { if (-x "$RealBin/$basename" || -x "$RealBin/$basename.exe") { $bin = "$RealBin/$basename"; # From path/to/verilator with verilator_bin installed } else { $bin = $basename; # Find in PATH } # Note we don't look under bin/$basename which would be right if running # in the kit dir. Running that would likely break, since # VERILATOR_ROOT wouldn't be set and Verilator won't find internal files. } return $bin; } ####################################################################### ####################################################################### # Utilities sub run { # Run command, check errors my $command = shift; $! = undef; # Cleanup -x print "\t$command\n" if $Debug>=3; system($command); my $status = $?; if ($status) { if ($! =~ /no such file or directory/i) { warn "%Error: verilator_coverage: Misinstalled, or VERILATOR_ROOT might need to be in environment\n"; } if ($Debug) { # For easy rerunning warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n"; warn "%Error: $command\n"; } if ($status & 127) { if (($status & 127) == 8 || ($status & 127) == 11) { # SIGFPA or SIGSEGV warn "%Error: Verilator_coverage internal fault, sorry.\n" if !$Debug; } elsif (($status & 127) == 6) { # SIGABRT warn "%Error: Verilator_coverage aborted.\n" if !$Debug; } else { warn "%Error: Verilator_coverage threw signal $status.\n" if !$Debug; } } if ($status != 256 || $Debug) { # i.e. not normal exit(1) warn "%Error: Command Failed $command\n"; } exit $! if $!; # errno exit $? >> 8 if $? >> 8; # child exit status exit 255; # last resort } } ####################################################################### ####################################################################### package main; __END__ =pod =head1 NAME verilator_coverage - Verilator coverage analyzer =head1 SYNOPSIS verilator_coverage --help verilator_coverage --version verilator_coverage --annotate verilator_coverage -write merged.dat -read ... verilator_coverage -write-info merged.info -read ... Verilator_coverage processes Verilator coverage reports. With --anotate, it reads the specified data file and generates annotated source code with coverage metrics annotated. If multiple coverage points exist on the same line, additional lines will be inserted to report the additional points. Additional Verilog-standard arguments specify the search paths necessary to find the source code that the coverage analysis was performed on. To get correct coverage percentages, you may wish to read logs/coverage.dat into Emacs and do a M-x keep-lines to include only those statistics of interest. For Verilog conditions that should never occur, you should add a $stop statement. This will remove the coverage during the next build. =head1 ARGUMENTS =over 4 =item I Specify input data file, may be repeated to read multiple inputs. If no data file is specified, by default coverage.dat is read. =item --annotate I Sprcifies the directory name that source files with annotated coverage data should be written to. =item --annotate-all Specifies all files should be shown. By default, only those source files which have low coverage are written to the output directory. =item --annotate-min I Specifies the minimum occurrence count that should be flagged if the coverage point does not include a specified threshold. Defaults to 10. =item --help Displays this message and program version and exits. =item --rank Print an experimental report listing the relative importance of each test in covering all of the coverage points. The report shows "Covered" which indicates the number of points that test covers; a test is considered to cover a point if it has a bucket count of at least 1. The "rank" column has a higher number t indicate the test is more important, and rank 0 means the test does not need to be run to cover the points. "RankPts" indicates the number of coverage points this test will contribute to overall coverage if all tests are run in the order of highest to lowest rank. =item --unlink When using --write to combine coverage data, unlink all input files after the output has been created. =item --version Displays program version and exits. =item --write I Specifies the aggregate coverage results, summed across all the files, should be written to the given filename in verilator_coverage data format. This is useful in scripts to combine many sequential runs into one master coverage file. =item --write-info I Specifies the aggregate coverage results, summed across all the files, should be written to the given filename in C .info format. This may be used to use C to aggregate or generate reports. The info format loses data compared to the Verilator coverage data format; the info will all forms of coverage converted to line style coverage, and if there are multiple coverage points on a single line, the minimum coverage across those points will be used to report coverage of the line. =back =head1 VERILOG ARGUMENTS The following arguments are compatible with GCC, VCS and most Verilog programs. =over 4 =item +libext+I+I... Defines the extensions for Verilog files. =item +define+I+I =item -DI=I Defines the given variable. =item +incdir+I =item -II Specifies a directory for finding include files. =item -f I Specifies a file containing additional command line arguments. =item -y I Specifies a module search directory. =back =head1 DISTRIBUTION The latest version is available from L. Copyright 2003-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS Wilson Snyder =head1 SEE ALSO C, C L which is the source for this document. =cut ###################################################################### verilator-4.038/bin/verilator_includer0000775000177100017500000000127513702133367020120 0ustar wsnyderwsnyder#!/usr/bin/env perl # DESCRIPTION: Print include statements for each ARGV # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### require 5.005; use warnings; print "// DESCR"."IPTION: Generated by verilator_includer via makefile\n"; foreach my $param (@ARGV) { if ($param =~ /^-D([^=]+)=(.*)/) { print "#define $1 $2\n" } else { print "#include \"$param\"\n" } } verilator-4.038/bin/verilator_difftree0000775000177100017500000001644413702133367020107 0ustar wsnyderwsnyder#!/usr/bin/env perl # See copyright, etc in below POD section. ###################################################################### use warnings; use Getopt::Long; use IO::File; use Pod::Usage; use strict; use vars qw($Debug); #====================================================================== # Old version 1 dump nodes with no dtypep's our %Ver1_Non_Dtyped = map {$_ => 1} qw( ACTIVE ALWAYS ALWAYSPOST ALWAYSPUBLIC ATTROF BEGIN BREAK CASE CASEITEM CCALL CELL CELLINLINE CFILE CFUNC CHANGEDET CLOCKING COMMENT CONTINUE COVERDECL COVERINC COVERTOGGLE CRETURN CSTMT DEFPARAM DISABLE DISPLAY DOT DPIEXPORT FCLOSE FFLUSH FINAL FINISH FOPEN GENCASE GENERATE GENFOR GENIF IF IMPLICIT INITARRAY INITIAL JUMPGO JUMPLABEL MODULE NETLIST NOTFOUNDMODULE PACKAGE PACKAGEIMPORT PARSEREF PIN PORT PRAGMA PRIMITIVE PSLASSERT PSLCOVER PSLDEFCLOCK PULL RANGE READMEM REPEAT RETURN SCCTOR SCDTOR SCHDR SCIMP SCIMPHDR SCINT SCOPE SELBIT SELEXTRACT SELMINUS SELPLUS SENGATE SENITEM SENTREE SFORMAT SFORMATF STOP SYSIGNORE SYSTEMT TASK TASKREF TEXT TOPSCOPE TYPEDEFFWD TYPETABLE UCSTMT UDPTABLE UDPTABLELINE UNTILSTABLE VASSERT WHILE ); #====================================================================== # main $Debug = 0; my $Opt_A; my $Opt_B; my $Opt_Lineno = 1; autoflush STDOUT 1; autoflush STDERR 1; Getopt::Long::config("no_auto_abbrev"); if (! GetOptions( "help" => \&usage, "debug" => \&debug, "<>" => \¶meter, "lineno!" => \$Opt_Lineno, )) { die "%Error: Bad usage, try 'verilator_difftree --help'\n"; } defined $Opt_A or die "%Error: No old diff filename\n"; defined $Opt_B or die "%Error: No new diff filename\n"; -e $Opt_A or die "%Error: No old diff filename found: $Opt_A\n"; -e $Opt_B or die "%Error: No new diff filename found: $Opt_B\n"; if (-d $Opt_A && -d $Opt_B) { diff_dir($Opt_A, $Opt_B); } elsif (-f $Opt_A && -f $Opt_B) { diff_file($Opt_A, $Opt_B); } else { die "%Error: Mix of files and dirs\n"; } sub diff_dir { my $a = shift; my $b = shift; # Diff all files under two directories my %files; foreach my $fn (glob("$a/*.tree")) { (my $base = $fn) =~ s!.*/!!; $files{$base}{a} = $fn; } foreach my $fn (glob("$b/*.tree")) { (my $base = $fn) =~ s!.*/!!; $files{$base}{b} = $fn; } my $any; foreach my $base (sort (keys %files)) { my $a = $files{$base}{a}; my $b = $files{$base}{b}; next if !$a || !$b; print "="x70,"\n"; print "= $a <-> $b\n"; diff_file($a,$b); $any = 1; } $any or warn("%Warning: No .tree files found that have similar base names:\n " .join("\n ", sort keys %files),"\n"); } sub diff_file { my $a = shift; my $b = shift; # Compare the two tree files (my $short_a = $a) =~ s/[^a-zA-Z0-9.]+/_/g; (my $short_b = $b) =~ s/[^a-zA-Z0-9.]+/_/g; my $tmp_a = "/tmp/${$}_${short_a}.a"; my $tmp_b = "/tmp/${$}_${short_b}.b"; my $vera = version_from($a); my $verb = version_from($b); my $verCvt = (($vera < 0x3900 && $verb >= 0x3900) || ($vera >= 0x3900 && $verb < 0x3900)); filter($a, $tmp_a, $verCvt); filter($b, $tmp_b, $verCvt); system("diff -u $tmp_a $tmp_b"); unlink $tmp_a; unlink $tmp_b; } sub version_from { my $fn = shift; # Return dump format my $f1 = IO::File->new ($fn) or die "%Error: $! $fn,"; while (defined (my $line=$f1->getline())) { last if $. > 10; return hex $1 if $line =~ /\(format (0x[0-9.]+)\)/; } return 1.0; } sub filter { my $fn1 = shift; my $fn2 = shift; my $verCvt = shift; # Remove hex numbers before diffing my $f1 = IO::File->new ($fn1) or die "%Error: $! $fn1,"; my $f2 = IO::File->new ($fn2,"w") or die "%Error: $! $fn2,"; while (defined (my $line=$f1->getline())) { same_line: next if $line =~ / This=/; $line =~ s/0x[a-f0-9]+/0x/g; $line =~ s///g; $line =~ s/{[a-z]*\d+}/{}/g if !$Opt_Lineno; if ($verCvt) { next if $line =~ /^ NETLIST/; $line =~ s!\@dt=0x\(G?/?([^)]+)\)!$1!g; # NEW: @dt -> OLD: non @dt format # # Below Ver1_Non_Dtyped may replace above further if ($line =~ /: ([A-Z]+) /) { my $type = $1; next if $type =~ 'DTYPE'; if ($type eq 'TYPETABLE' || $type eq 'RANGE') { $line =~ /^(\s+\S+:) /; my $prefix = $1; while (defined ($line=$f1->getline())) { next if $line =~ /^\s+[a-z]/; # Table body next if $line =~ /^${prefix}[0-9]:/; goto same_line; } next; } if ($Ver1_Non_Dtyped{$type}) { $line =~ s! w[0-9]+!!g; } } $line =~ s!\@dt=0$!NoW!g; # NEW: dt=null -> common format $line =~ s!\@dt=0 !NoW !g; # NEW: dt=null -> common format $line =~ s! s?w0$! NoW!g; # OLD: no width -> common format $line =~ s! s?w0 ! NoW !g; # OLD: no width -> common format } print $f2 $line; } $f1->close; $f2->close; } #---------------------------------------------------------------------- sub usage { pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT); exit(1); # Unreachable } sub debug { $Debug = 1; } sub parameter { my $param = shift; if (!defined $Opt_A) { $Opt_A = $param; } elsif (!defined $Opt_B) { $Opt_B = $param; } else { die "%Error: Unknown parameter: $param\n"; } } ####################################################################### sub run { # Run a system command, check errors my $command = shift; print "\t$command\n"; system "$command"; my $status = $?; ($status == 0) or die "%Error: Command Failed $command, $status, stopped"; } ####################################################################### __END__ =pod =head1 NAME verilator_difftree - Compare two Verilator debugging trees =head1 SYNOPSIS verilator_difftree .../a/a.tree .../b/a.tree verilator_difftree .../a .../b =head1 DESCRIPTION Verilator_difftree is used for debugging Verilator tree output files. It performs a diff between two files, or all files common between two directories, ignoring irrelevant pointer differences. =head1 ARGUMENTS =over 4 =item --help Displays this message and program version and exits. =item --nolineno Do not show differences in line numbering. =back =head1 DISTRIBUTION The latest version is available from L. Copyright 2005-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS Wilson Snyder =head1 SEE ALSO C =cut ###################################################################### ### Local Variables: ### compile-command: "$V4/bin/verilator_difftree {$V4D,$V4}/test_regress/obj_dir/t_EXAMPLE/V*_03_*.tree" ### End: verilator-4.038/bin/verilator0000775000177100017500000065274713702333327016251 0ustar wsnyderwsnyder#!/usr/bin/env perl ###################################################################### # # Copyright 2003-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### require 5.006_001; use warnings; use Getopt::Long; use FindBin qw($RealBin $RealScript); use IO::File; use Pod::Usage; use strict; use vars qw($Debug @Opt_Verilator_Sw); ####################################################################### ####################################################################### # main autoflush STDOUT 1; autoflush STDERR 1; $Debug = 0; my $opt_gdb; my $opt_rr; my $opt_gdbbt; my $opt_quiet_exit; # No arguments can't do anything useful. Give help if ($#ARGV < 0) { pod2usage(-exitstatus=>2, -verbose=>0); } # Insert debugging options up front push @ARGV, (split ' ',$ENV{VERILATOR_TEST_FLAGS}||""); # We sneak a look at the flags so we can do some pre-environment checks # All flags will hit verilator... foreach my $sw (@ARGV) { push @Opt_Verilator_Sw, $sw; } Getopt::Long::config("no_auto_abbrev","pass_through"); if (! GetOptions( # Major operating modes "help" => \&usage, "debug" => \&debug, # "version!" => \&version, # Also passthru'ed # Switches "gdb!" => \$opt_gdb, "gdbbt!" => \$opt_gdbbt, "quiet-exit!" => \$opt_quiet_exit, "rr!" => \$opt_rr, # Additional parameters "<>" => sub {}, # Ignored )) { pod2usage(-exitstatus=>2, -verbose=>0); } if ($opt_gdbbt && !gdb_works()) { warn "-Info: --gdbbt ignored: gdb doesn't seem to be working\n" if $Debug; $opt_gdbbt = 0; } # Determine runtime flags and run # Opt_Verilator_Sw is what we want verilator to see on its argc/argv. # Starting with that, escape all special chars for the shell; # The shell will undo the escapes and the verilator binary should # then see exactly the contents of @Opt_Verilator_Sw. my @quoted_sw = map {sh_escape($_)} @Opt_Verilator_Sw; if ($opt_gdb) { # Generic GDB interactive run (($ENV{VERILATOR_GDB}||"gdb") ." ".verilator_bin() # Note, uncomment to set breakpoints before running: # ." -ex 'break main'" # Note, we must use double-quotes ("run ") # and not single ('run ') below. Bash swallows # escapes as you would expect in a double-quoted string. # That's not true for a single-quoted string, where \' # actually terminates the string -- not what we want! ." -ex \"run ".join(' ', @quoted_sw)."\"" ." -ex 'set width 0'" ." -ex 'bt'"); } elsif ($opt_rr) { # Record with rr run ("rr record ".verilator_bin() ." ".join(' ', @quoted_sw)); } elsif ($opt_gdbbt && $Debug) { # Run under GDB to get gdbbt run ("gdb" ." ".verilator_bin() ." --batch --quiet --return-child-result" ." -ex \"run ".join(' ', @quoted_sw)."\"" ." -ex 'set width 0'" ." -ex 'bt' -ex 'quit'"); } else { # Normal, non gdb run(verilator_bin()." ".join(' ',@quoted_sw)); } #---------------------------------------------------------------------- sub usage { pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT); } sub debug { shift; my $level = shift; $Debug = $level||3; } ####################################################################### ####################################################################### # Builds sub verilator_bin { my $bin = ""; # Use VERILATOR_ROOT if defined, else assume verilator_bin is in the search path my $basename = ($ENV{VERILATOR_BIN} || ($Debug ? "verilator_bin_dbg" : "verilator_bin")); if (defined($ENV{VERILATOR_ROOT})) { my $dir = $ENV{VERILATOR_ROOT}; if (-x "$dir/bin/$basename" || -x "$dir/bin/$basename.exe") { # From a "make install" into VERILATOR_ROOT $bin = "$dir/bin/$basename"; } else { $bin = "$dir/$basename"; # From pointing to kit directory } } else { if (-x "$RealBin/$basename" || -x "$RealBin/$basename.exe") { $bin = "$RealBin/$basename"; # From path/to/verilator with verilator_bin installed } else { $bin = $basename; # Find in PATH } # Note we don't look under bin/$basename which would be right if running # in the kit dir. Running that would likely break, since # VERILATOR_ROOT wouldn't be set and Verilator won't find internal files. } return $bin; } ####################################################################### ####################################################################### # Utilities sub gdb_works { $! = undef; # Cleanup -x system("gdb /bin/echo" ." --batch-silent --quiet --return-child-result" ." -ex 'run -n'" # `echo -n` ." -ex 'set width 0'" ." -ex 'bt'" ." -ex 'quit'"); my $status = $?; return $status==0; } sub run { # Run command, check errors my $command = shift; $! = undef; # Cleanup -x print "\t$command\n" if $Debug>=3; system($command); my $status = $?; if ($status) { if ($! =~ /no such file or directory/i) { warn "%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in environment\n"; } if ($Debug) { # For easy rerunning warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n"; warn "%Error: $command\n"; } if ($status & 127) { if (($status & 127) == 4 # SIGILL || ($status & 127) == 8 # SIGFPA || ($status & 127) == 11) { # SIGSEGV warn "%Error: Verilator internal fault, sorry. " ."Suggest trying --debug --gdbbt\n" if !$Debug; } elsif (($status & 127) == 6) { # SIGABRT warn "%Error: Verilator aborted. " ."Suggest trying --debug --gdbbt\n" if !$Debug; } else { warn "%Error: Verilator threw signal $status. " ."Suggest trying --debug --gdbbt\n" if !$Debug; } } if (!$opt_quiet_exit && ($status != 256 || $Debug)) { # i.e. not normal exit(1) warn "%Error: Command Failed $command\n"; } exit $! if $!; # errno exit $? >> 8 if $? >> 8; # child exit status exit 255; # last resort } } sub sh_escape { my ($arg) = @_; # This is similar to quotemeta() but less aggressive. # There's no need to escape hyphens, periods, or forward slashes # for the shell as these have no special meaning to the shell. $arg =~ s/([^0-9a-zA-Z_\-\.\/])/\\$1/g; return $arg; } ####################################################################### ####################################################################### package main; __END__ =pod =head1 NAME Verilator - Translate and simulate SystemVerilog code using C++/SystemC =head1 SYNOPSIS verilator --help verilator --version verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] verilator --lint-only -Wall [source_files.v]... =head1 DESCRIPTION The "Verilator" package converts all synthesizable, and many behavioral, Verilog and SystemVerilog designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler. Verilator is typically used as follows: 1. The C executable is invoked with parameters similar to GCC, Cadence Verilog-XL/NC-Verilog, or Synopsys VCS. C reads the specified user's SystemVerilog code, lints it, optionally adds coverage and waveform tracing support, and compiles the design into a source level C++ or SystemC "model". The resulting model's C++ or SystemC code is output as .cpp and .h files. This is referred to as "verilating" and the process is "to verilate"; the output is a "verilated" model. 2. For simulation, a small user written C++ wrapper file is required, the "wrapper". This wrapper defines the C++ function `main()` which instantiates the Verilated model as a C++/SystemC object. 3. The user main wrapper, the files created by Verilator, a "runtime library" provided by Verilator, and if applicable the SystemC libraries are then compiled using a C++ compiler to create a simulation executable. 4. The resulting executable will perform the actual simulation, during "simulation runtime". To get started, jump down to the L section. =head1 ARGUMENT SUMMARY This is a short summary of the arguments to the "verilator" executable. See L for the detailed descriptions of these arguments. {file.v} Verilog package, module and top module filenames {file.c/cc/cpp} Optional C++ files to compile in {file.a/o/so} Optional C++ files to link in +1364-1995ext+ Use Verilog 1995 with file extension +1364-2001ext+ Use Verilog 2001 with file extension +1364-2005ext+ Use Verilog 2005 with file extension +1800-2005ext+ Use SystemVerilog 2005 with file extension +1800-2009ext+ Use SystemVerilog 2009 with file extension +1800-2012ext+ Use SystemVerilog 2012 with file extension +1800-2017ext+ Use SystemVerilog 2017 with file extension --assert Enable all assertions --autoflush Flush streams after all $displays --bbox-sys Blackbox unknown $system calls --bbox-unsup Blackbox unsupported language features --bin Override Verilator binary --build Build model executable/library after Verilation -CFLAGS C++ compiler flags for makefile --cc Create C++ output --cdc Clock domain crossing analysis --clk Mark specified signal as clock --make Generate scripts for specified build tool --compiler Tune for specified C++ compiler --converge-limit Tune convergence settle time --coverage Enable all coverage --coverage-line Enable line coverage --coverage-toggle Enable toggle coverage --coverage-user Enable SVL user coverage --coverage-underscore Enable coverage of _signals -D[=] Set preprocessor define --debug Enable debugging --debug-check Enable debugging assertions --no-debug-leak Disable leaking memory in --debug mode --debugi Enable debugging at a specified level --debugi- Enable debugging a source file at a level --default-language Default language to parse +define+= Set preprocessor define --dpi-hdr-only Only produce the DPI header file --dump-defines Show preprocessor defines with -E --dump-tree Enable dumping .tree files --dump-treei Enable dumping .tree files at a level --dump-treei- Enable dumping .tree file at a source file at a level --dump-tree-addrids Use short identifiers instead of addresses -E Preprocess, but do not compile --error-limit Abort after this number of errors --exe Link to create executable -F Parse options from a file, relatively -f Parse options from a file -FI Force include of a file --flatten Force inlining of all modules, tasks and functions -G= Overwrite top-level parameter --gdb Run Verilator under GDB interactively --gdbbt Run Verilator under GDB for backtrace --generate-key Create random key for --protect-key --getenv Get environment variable with defaults --help Display this help -I Directory to search for includes -j Parallelism for --build --gate-stmts Tune gate optimizer depth --if-depth Tune IFDEPTH warning +incdir+ Directory to search for includes --inhibit-sim Create function to turn off sim --inline-mult Tune module inlining -LDFLAGS Linker pre-object flags for makefile --l2-name Verilog scope name of the top module --language Default language standard to parse +libext++[ext]... Extensions for finding modules --lint-only Lint, but do not make output -MAKEFLAGS Options to make during --build --max-num-width Maximum number width (default: 64K) --MMD Create .d dependency files --MP Create phony dependency targets --Mdir Name of output object directory --mod-prefix Name to prepend to lower classes --no-clk Prevent marking specified signal as clock --no-decoration Disable comments and symbol decorations --no-pins64 Don't use vluint64_t's for 33-64 bit sigs --no-skip-identical Disable skipping identical output +notimingchecks Ignored -O0 Disable optimizations -O3 High performance optimizations -O Selectable optimizations -o Name of final executable --no-order-clock-delay Disable ordering clock enable assignments --no-verilate Skip verilation and just compile previously Verilated code. --output-split Split .cpp files into pieces --output-split-cfuncs Split model functions --output-split-ctrace Split tracing functions -P Disable line numbers and blanks with -E --pins-bv Specify types for top level ports --pins-sc-uint Specify types for top level ports --pins-sc-biguint Specify types for top level ports --pins-uint8 Specify types for top level ports --pipe-filter Filter all input through a script --pp-comments Show preprocessor comments with -E --prefix Name of top level class --prof-cfuncs Name functions for profiling --prof-threads Enable generating gantt chart data for threads --protect-key Key for symbol protection --protect-ids Hash identifier names for obscurity --protect-lib Create a DPI protected library --private Debugging; see docs --public Debugging; see docs --public-flat-rw Mark all variables, etc as public_flat_rw -pvalue+= Overwrite toplevel parameter --quiet-exit Don't print the command on failure --relative-includes Resolve includes relative to current file --no-relative-cfuncs Disallow 'this->' in generated functions --report-unoptflat Extra diagnostics for UNOPTFLAT --rr Run Verilator and record with rr --savable Enable model save-restore --sc Create SystemC output --stats Create statistics file --stats-vars Provide statistics on variables -sv Enable SystemVerilog parsing +systemverilogext+ Synonym for +1800-2017ext+ --threads Enable multithreading --threads-dpi Enable multithreaded DPI --threads-max-mtasks Tune maximum mtask partitioning --timescale Sets default timescale --timescale-override Overrides all timescales --top-module Name of top level input module --trace Enable waveform creation --trace-coverage Enable tracing of coverage --trace-depth Depth of tracing --trace-fst Enable FST waveform creation --trace-max-array Maximum bit width for tracing --trace-max-width Maximum array depth for tracing --trace-params Enable tracing of parameters --trace-structs Enable tracing structure names --trace-threads Enable waveform creation on separate threads --trace-underscore Enable tracing of _signals -U Undefine preprocessor define --unroll-count Tune maximum loop iterations --unroll-stmts Tune maximum loop body size --unused-regexp Tune UNUSED lint signals -V Verbose version and config -v Verilog library +verilog1995ext+ Synonym for +1364-1995ext+ +verilog2001ext+ Synonym for +1364-2001ext+ --version Displays program version and exits --vpi Enable VPI compiles --waiver-output Create a waiver file based on the linter warnings -Wall Enable all style warnings -Werror- Convert warnings to errors -Wfuture- Disable unknown message warnings -Wno- Disable warning -Wno-context Disable source context on warnings -Wno-fatal Disable fatal exit on warnings -Wno-lint Disable all lint warnings -Wno-style Disable all style warnings -Wpedantic Warn on compliance-test issues --x-assign Assign non-initial Xs to this value --x-initial Assign initial Xs to this value --x-initial-edge Enable initial X->0 and X->1 edge triggers --xml-only Create XML parser output --xml-output XML output filename -y Directory to search for modules This is a short summary of the simulation runtime arguments, i.e. for the final Verilated simulation runtime models. See L for the detailed description of these arguments. +verilator+debug Enable debugging +verilator+debugi+ Enable debugging at a level +verilator+help Display help +verilator+prof+threads+file+I Set profile filename +verilator+prof+threads+start+I Set profile starting point +verilator+prof+threads+window+I Set profile duration +verilator+rand+reset+I Set random reset technique +verilator+seed+I Set random seed +verilator+noassert Disable assert checking +verilator+V Verbose version and config +verilator+version Show version and exit =head1 VERILATION ARGUMENTS The following are the arguments that may be passed to the "verilator" executable. =over 4 =item {file.v} Specifies the Verilog file containing the top module to be Verilated. =item {file.c/.cc/.cpp/.cxx} Used with --exe to specify optional C++ files to be linked in with the Verilog code. The file path should either be absolute, or relative to where the make will be executed from, or add to your makefile's VPATH the appropriate directory to find the file. See also the -CFLAGS and -LDFLAGS options, which are useful when the C++ files need special compiler flags. =item {file.a/.o/.so} Specifies optional object or library files to be linked in with the Verilog code, as a shorthand for -LDFLAGS "". The file path should either be absolute, or relative to where the make will be executed from, or add to your makefile's VPATH the appropriate directory to find the file. If any files are specified in this way, Verilator will include a make rule that uses these files when linking the I executable. This generally is only useful when used with the --exe option. =item +1364-1995ext+I =item +1364-2001ext+I =item +1364-2005ext+I =item +1800-2005ext+I =item +1800-2009ext+I =item +1800-2012ext+I =item +1800-2017ext+I Specifies the language standard to be used with a specific filename extension, I. For compatibility with other simulators, see also the synonyms C<+verilog1995ext+>I, C<+verilog2001ext+>I, and C<+systemverilogext+>I. For any source file, the language specified by these options takes precedence over any language specified by the C<--default-language> or C<--language> options. These options take effect in the order they are encountered. Thus the following would use Verilog 1995 for C and Verilog 2001 for C. verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v These flags are only recommended for legacy mixed language designs, as the preferable option is to edit the code to repair new keywords, or add appropriate C<`begin_keywords>. B C<`begin_keywords> is a SystemVerilog construct, which specifies I the set of keywords to be recognized. This also controls some error messages that vary between language standards. Note at present Verilator tends to be overly permissive, e.g. it will accept many grammar and other semantic extensions which might not be legal when set to an older standard. =item --assert Enable all assertions. =item --autoflush After every $display or $fdisplay, flush the output stream. This ensures that messages will appear immediately but may reduce performance. For best performance call "fflush(stdout)" occasionally in the C++ main loop. Defaults to off, which will buffer output as provided by the normal C/C++ standard library IO. =item --bbox-sys Black box any unknown $system task or function calls. System tasks will simply become no-operations, and system functions will be replaced with unsized zero. Arguments to such functions will be parsed, but not otherwise checked. This prevents errors when linting in the presence of company specific PLI calls. Using this argument will likely cause incorrect simulation. =item --bbox-unsup Black box some unsupported language features, currently UDP tables, the cmos and tran gate primitives, deassign statements, and mixed edge errors. This may enable linting the rest of the design even when unsupported constructs are present. Using this argument will likely cause incorrect simulation. =item --bin I Rarely needed. Override the default filename for Verilator itself. When a dependency (.d) file is created, this filename will become a source dependency, such that a change in this binary will have make rebuild the output files. =item --build After generating the SystemC/C++ code, Verilator will invoke the toolchain to build the model library (and executable when C<--exe> is also used). Verilator manages the build itself, and for this --build requires GNU Make to be available on the platform. =item -CFLAGS I Add specified C compiler flag to the generated makefiles. For multiple flags either pass them as a single argument with space separators quoted in the shell (C<-CFLAGS "-a -b">), or use multiple -CFLAGS arguments (C<-CFLAGS -a -CFLAGS -b>). When make is run on the generated makefile these will be passed to the C++ compiler (g++/clang++/msvc++). =item --cc Specifies C++ without SystemC output mode; see also --sc. =item --cdc Permanently experimental. Perform some clock domain crossing checks and issue related warnings (CDCRSTLOGIC) and then exit; if warnings other than CDC warnings are needed make a second run with --lint-only. Additional warning information is also written to the file {prefix}__cdc.txt. Currently only checks some items that other CDC tools missed; if you have interest in adding more traditional CDC checks, please contact the authors. =item --clk I Sometimes it is quite difficult for Verilator to distinguish clock signals from other data signals. Occasionally the clock signals can end up in the checking list of signals which determines if further evaluation is needed. This will heavily degrade the performance of a Verilated model. With --clk , user can specified root clock into the model, then Verilator will mark the signal as clocker and propagate the clocker attribute automatically to other signals derived from that. In this way, Verilator will try to avoid taking the clocker signal into checking list. Note signal-name is specified by the RTL hierarchy path. For example, v.foo.bar. If the signal is the input to top-module, the directly the signal name. If you find it difficult to find the exact name, try to use C in RTL file to mark the signal directly. If clock signals are assigned to vectors and then later used individually, Verilator will attempt to decompose the vector and connect the single-bit clock signals directly. This should be transparent to the user. =item --make I Generates a script for the specified build tool. Supported values are C for GNU Make and C for CMake. Both can be specified together. If no build tool is specified, gmake is assumed. The executable of gmake can be configured via environment variable "MAKE". When using --build Verilator takes over the responsibility of building the model library/executable. For this reason --make cannot be specified when using --build. =item --compiler I Enables workarounds for the specified C++ compiler, either C, C, or C. Currently this does not change any performance tuning flags, but it may in the future. =over 4 =item clang Tune for clang. This may reduce execution speed as it enables several workarounds to avoid silly hard-coded limits in clang. This includes breaking deep structures as for msvc as described below. =item gcc Tune for GNU C++, although generated code should work on almost any compliant C++ compiler. Currently the default. =item msvc Tune for Microsoft Visual C++. This may reduce execution speed as it enables several workarounds to avoid silly hard-coded limits in MSVC++. This includes breaking deeply nested parenthesized expressions into sub-expressions to avoid error C1009, and breaking deep blocks into functions to avoid error C1061. =back =item --converge-limit I Rarely needed. Specifies the maximum number of runtime iterations before creating a model failed to converge error. Defaults to 100. =item --coverage Enables all forms of coverage, alias for "--coverage-line --coverage-toggle --coverage-user". =item --coverage-line Specifies basic block line coverage analysis code should be inserted. Coverage analysis adds statements at each code flow change point (e.g. at branches). At each such branch a unique counter is incremented. At the end of a test, the counters along with the filename and line number corresponding to each counter are written into logs/coverage.dat. Verilator automatically disables coverage of branches that have a $stop in them, as it is assumed $stop branches contain an error check that should not occur. A /*verilator coverage_block_off*/ comment will perform a similar function on any code in that block or below, or /*verilator coverage_on/coverage_off*/ will disable coverage around lines of code. Note Verilator may over-count combinatorial (non-clocked) blocks when those blocks receive signals which have had the UNOPTFLAT warning disabled; for most accurate results do not disable this warning when using coverage. =item --coverage-toggle Specifies signal toggle coverage analysis code should be inserted. Every bit of every signal in a module has a counter inserted. The counter will increment on every edge change of the corresponding bit. Signals that are part of tasks or begin/end blocks are considered local variables and are not covered. Signals that begin with underscores, are integers, or are very wide (>256 bits total storage across all dimensions) are also not covered. Hierarchy is compressed, such that if a module is instantiated multiple times, coverage will be summed for that bit across ALL instantiations of that module with the same parameter set. A module instantiated with different parameter values is considered a different module, and will get counted separately. Verilator makes a minimally-intelligent decision about what clock domain the signal goes to, and only looks for edges in that clock domain. This means that edges may be ignored if it is known that the edge could never be seen by the receiving logic. This algorithm may improve in the future. The net result is coverage may be lower than what would be seen by looking at traces, but the coverage is a more accurate representation of the quality of stimulus into the design. There may be edges counted near time zero while the model stabilizes. It's a good practice to zero all coverage just before releasing reset to prevent counting such behavior. A /*verilator coverage_off/on */ comment pair can be used around signals that do not need toggle analysis, such as RAMs and register files. =item --coverage-underscore Enable coverage of signals that start with an underscore. Normally, these signals are not covered. See also --trace-underscore. =item --coverage-user Enables user inserted functional coverage. Currently, all functional coverage points are specified using SVA which must be separately enabled with --assert. For example, the following statement will add a coverage point, with the comment "DefaultClock": DefaultClock: cover property (@(posedge clk) cyc==3); =item -DI=I Defines the given preprocessor symbol. Similar to +define, but does not allow multiple definitions with a single option using plus signs. +define is fairly standard across Verilog tools while -D is similar to GCC. =item --debug Select the debug executable of Verilator (if available), and enable more internal assertions (equivalent to C<--debug-check>), debugging messages (equivalent to C<--debugi 4>), and intermediate form dump files (equivalent to C<--dump-treei 3>). =item --debug-check Rarely needed. Enable internal debugging assertion checks, without changing debug verbosity. Enabled automatically when --debug specified. =item --no-debug-leak In --debug mode, by default Verilator intentionally leaks AstNode instances instead of freeing them, so that each node pointer is unique in the resulting tree files and dot files. This option disables the leak. This may avoid out-of-memory errors when Verilating large models in --debug mode. Outside of --debug mode, AstNode instances should never be leaked and this option has no effect. =item --debugi I =item --debugi-I I Rarely needed - for developer use. Set internal debugging level globally to the specified debug level (1-10) or set the specified Verilator source file to the specified level (e.g. C<--debugi-V3Width 9>). Higher levels produce more detailed messages. =item --default-language I Select the language to be used by default when first processing each Verilog file. The language value must be "1364-1995", "1364-2001", "1364-2005", "1800-2005", "1800-2009", "1800-2012" or "1800-2017". Any language associated with a particular file extension (see the various +Iext+ options) will be used in preference to the language specified by --default-language. The --default-language flag is only recommended for legacy code using the same language in all source files, as the preferable option is to edit the code to repair new keywords, or add appropriate C<`begin_keywords>. For legacy mixed language designs, the various +Iext+ options should be used. If no language is specified, either by this flag or +Iext+ options, then the latest SystemVerilog language (IEEE 1800-2017) is used. =item +define+I=I =item +define+I=I+I=I... Defines the given preprocessor symbol, or multiple symbols if separated by plus signs. Similar to -D; +define is fairly standard across Verilog tools while -D is similar to GCC. =item --dpi-hdr-only Only generate the DPI header file. This option has no effect on the name or location of the emitted DPI header file, it is output in C<--Mdir> as it would be without this option. =item --dump-defines With -E, suppress normal output, and instead print a list of all defines existing at the end of pre-processing the input files. Similar to GCC "-dM" option. This also gives you a way of finding out what is predefined in Verilator using the command: touch foo.v ; verilator -E --dump-defines foo.v =item --dump-tree Rarely needed. Enable writing .tree debug files with dumping level 3, which dumps the standard critical stages. For details on the format see the Verilator Internals manual. --dump-tree is enabled automatically with --debug, so "--debug --no-dump-tree" may be useful if the dump files are large and not desired. =item --dump-treei I =item --dump-treei-I I Rarely needed - for developer use. Set internal tree dumping level globally to a specific dumping level or set the specified Verilator source file to the specified tree dumping level (e.g. C<--dump-treei-V3Order 9>). Level 0 disables dumps and is equivalent to "--no-dump-tree". Level 9 enables dumping of every stage. =item --dump-tree-addrids Rarely needed - for developer use. Replace AST node addresses with short identifiers in tree dumps to enhance readability. Each unique pointer value is mapped to a unique identifier, but note that this is not necessarily unique per node instance as an address might get reused by a newly allocated node after a node with the same address has been dumped then freed. =item -E Preprocess the source code, but do not compile, as with 'gcc -E'. Output is written to standard out. Beware of enabling debugging messages, as they will also go to standard out. =item --error-limit I After this number of errors are encountered during Verilator run, exit. Warnings are not counted in this limit. Defaults to 50. Does not affect simulation runtime errors, for those see +verilator+error+limit. =item --exe Generate an executable. You will also need to pass additional .cpp files on the command line that implement the main loop for your simulation. =item -F I Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the directory containing the specified file. See also -f. Note -F is fairly standard across Verilog tools. =item -f I Read the specified file, and act as if all text inside it was specified as command line parameters. Any relative paths are relative to the current directory. See also -F. Note -f is fairly standard across Verilog tools. The file may contain // comments which are ignored to the end of the line. Any $VAR, $(VAR), or ${VAR} will be replaced with the specified environment variable. =item -FI I Force include of the specified C++ header file. All generated C++ files will insert a #include of the specified file before any other includes. The specified file might be used to contain define prototypes of custom VL_VPRINTF functions, and may need to include verilatedos.h as this file is included before any other standard includes. =item --flatten Force flattening of the design's hierarchy, with all modules, tasks and functions inlined. Typically used with C<--xml-only>. Note flattening large designs may require significant CPU time, memory and storage. =item -GI=I Overwrites the given parameter of the toplevel module. The value is limited to basic data literals: =over 4 =item Verilog integer literals The standard Verilog integer literals are supported, so values like 32'h8, 2'b00, 4 etc. are allowed. Care must be taken that the single quote (I') is properly escaped in an interactive shell, e.g., as -GWIDTH=8\'hx. =item C integer literals It is also possible to use C integer notation, including hexadecimal (0x..), octal (0..) or binary (0b..) notation. =item Double literals Double literals must be one of the following styles: - contains a dot (.) (e.g. 1.23) - contains an exponent (e/E) (e.g. 12e3) - contains p/P for hexadecimal floating point in C99 (e.g. 0x123.ABCp1) =item Strings Strings must be in double quotes (""). They must be escaped properly on the command line, e.g. as -GSTR="\"My String\"" or -GSTR='"My String"'. =back =item --gate-stmts I Rarely needed. Set the maximum number of statements that may be present in an equation for the gate substitution optimization to inline that equation. =item --gdb Run Verilator underneath an interactive GDB (or VERILATOR_GDB environment variable value) session. See also --gdbbt. =item --gdbbt If --debug is specified, run Verilator underneath a GDB process and print a backtrace on exit, then exit GDB immediately. Without --debug or if GDB doesn't seem to work, this flag is ignored. Intended for easy creation of backtraces by users; otherwise see the --gdb flag. =item --generate-key Generate a true-random key suitable for use with --protect-key, print it, and exit immediately. =item --getenv I If the variable is declared in the environment, print it and exit immediately. Otherwise, if it's built into Verilator (e.g. VERILATOR_ROOT), print that and exit immediately. Otherwise, print a newline and exit immediately. This can be useful in makefiles. See also -V, and the various *.mk files. =item --help Displays this message and program version and exits. =item -II See -y. =item --if-depth I Rarely needed. Set the depth at which the IFDEPTH warning will fire, defaults to 0 which disables this warning. =item +incdir+I See -y. =item --inhibit-sim Rarely needed. Create a "inhibitSim(bool)" function to enable and disable evaluation. This allows an upper level testbench to disable modules that are not important in a given simulation, without needing to recompile or change the SystemC modules instantiated. =item --inline-mult I Tune the inlining of modules. The default value of 2000 specifies that up to 2000 new operations may be added to the model by inlining, if more than this number of operations would result, the module is not inlined. Larger values, or a value < 1 will inline everything, will lead to longer compile times, but potentially faster simulation speed. This setting is ignored for very small modules; they will always be inlined, if allowed. =item -j Specify the level of parallelism for --build. must be a positive integer specifying the maximum number of parallel build jobs, or can be omitted. When is omitted, the build will not try to limit the number of parallel build jobs but attempt to execute all independent build steps in parallel. =item -LDFLAGS I Add specified C linker flags to the generated makefiles. For multiple flags either pass them as a single argument with space separators quoted in the shell (C<-LDFLAGS "-a -b">), or use multiple -LDFLAGS arguments (C<-LDFLAGS -a -LDFLAGS -b>). When make is run on the generated makefile these will be passed to the C++ linker (ld) *after* the primary file being linked. This flag is called -LDFLAGS as that's the traditional name in simulators; it's would have been better called LDLIBS as that's the Makefile variable it controls. (In Make, LDFLAGS is before the first object, LDLIBS after. -L libraries need to be in the Make variable LDLIBS, not LDFLAGS.) =item --l2-name I Instead of using the module name when showing Verilog scope, use the name provided. This allows simplifying some Verilator-embedded modeling methodologies. Default is an l2-name matching the top module. The default before 3.884 was "--l2-name v" For example, the program "module t; initial $display("%m"); endmodule" will show by default "t". With "--l2-name v" it will print "v". =item --language I A synonym for C<--default-language>, for compatibility with other tools and earlier versions of Verilator. =item +libext+I+I... Specify the extensions that should be used for finding modules. If for example module I is referenced, look in I.I. Note +libext+ is fairly standard across Verilog tools. Defaults to .v and .sv. =item --lint-only Check the files for lint violations only, do not create any other output. You may also want the -Wall option to enable messages that are considered stylistic and not enabled by default. If the design is not to be completely Verilated see also the --bbox-sys and --bbox-unsup options. =item -MAKEFLAGS When using --build, add the specified flag to the invoked make command line. For multiple flags either pass them as a single argument with space separators quoted in the shell (e.g. C<-MAKEFLAGS "-a -b">), or use multiple -MAKEFLAGS arguments (e.g. C<-MAKEFLAGS -l -MAKEFLAGS -k>). Use of this option should not be required for simple builds using the host toolchain. =item --max-num-width I Set the maximum number literal width (e.g. in 1024'd22 this it the 1024). Defaults to 64K. =item --MMD =item --no-MMD Enable/disable creation of .d dependency files, used for make dependency detection, similar to gcc -MMD option. By default this option is enabled for --cc or --sc modes. =item --MP When creating .d dependency files with --MMD, make phony targets. Similar to gcc -MP option. =item --Mdir I Specifies the name of the Make object directory. All generated files will be placed in this directory. If not specified, "obj_dir" is used. The directory is created if it does not exist and the parent directories exist; otherwise manually create the Mdir before calling Verilator. =item --mod-prefix I Specifies the name to prepend to all lower level classes. Defaults to the same as --prefix. =item --no-clk I Prevent the specified signal from being marked as clock. See C<--clk>. =item --no-decoration When creating output Verilated code, minimize comments, white space, symbol names and other decorative items, at the cost of greatly reduced readability. This may assist C++ compile times. This will not typically change the ultimate model's performance, but may in some cases. =item --no-pins64 Backward compatible alias for "--pins-bv 33". =item --no-relative-cfuncs Disable 'this->' references in generated functions, and instead Verilator will generate absolute references starting from 'vlTOPp->'. This prevents V3Combine from merging functions from multiple instances of the same module, so it can grow the instruction stream. This is a work around for old compilers. Don't set this if your C++ compiler supports __restrict__ properly, as GCC 4.5.x and newer do. For older compilers, test if this switch gives you better performance or not. Compilers which don't honor __restrict__ will suspect that 'this->' references and 'vlTOPp->' references may alias, and may write slow code with extra loads and stores to handle the (imaginary) aliasing. Using only 'vlTOPp->' references allows these old compilers to produce tight code. =item --no-skip-identical =item --skip-identical Rarely needed. Disables or enables skipping execution of Verilator if all source files are identical, and all output files exist with newer dates. By default this option is enabled for --cc or --sc modes only. =item +notimingchecks Ignored for compatibility with other simulators. =item -O0 Disables optimization of the model. =item -O3 Enables slow optimizations for the code Verilator itself generates (as opposed to "-CFLAGS -O3" which effects the C compiler's optimization. -O3 may improve simulation performance at the cost of compile time. This currently sets --inline-mult -1. =item -OI Rarely needed. Enables or disables a specific optimizations, with the optimization selected based on the letter passed. A lowercase letter disables an optimization, an upper case letter enables it. This is intended for debugging use only; see the source code for version-dependent mappings of optimizations to -O letters. =item -o I Specify the name for the final executable built if using --exe. Defaults to the --prefix if not specified. =item --no-order-clock-delay Rarely needed. Disables a bug fix for ordering of clock enables with delayed assignments. This flag should only be used when suggested by the developers. =item --output-split I Enables splitting the output .cpp files into multiple outputs. When a C++ file exceeds the specified number of operations, a new file will be created at the next function boundary. In addition, if the total output code size exceeds the specified value, VM_PARALLEL_BUILDS will be set to 1 by default in the generated make files, making parallel compilation possible. Using --output-split should have only a trivial impact on model performance. But can greatly improve C++ compilation speed. The use of I (set for you if present at configure time) is also more effective with this option. This option is on by default with a value of 20000. To disable, pass with a value of 0. =item --output-split-cfuncs I Enables splitting functions in the output .cpp files into multiple functions. When a generated function exceeds the specified number of operations, a new function will be created. With --output-split, this will enable the C++ compiler to compile faster, at a small loss in performance that gets worse with decreasing split values. Note that this option is stronger than --output-split in the sense that --output-split will not split inside a function. Defaults to the value of --output-split, unless explicitly specified. =item --output-split-ctrace I Similar to --output-split-cfuncs, enables splitting trace functions in the output .cpp files into multiple functions. Defaults to the value of --output-split, unless explicitly specified. =item -P With -E, disable generation of `line markers and blank lines, similar to GCC -P flag. =item --pins64 Backward compatible alias for "--pins-bv 65". Note that's a 65, not a 64. =item --pins-bv I Specifies SystemC inputs/outputs of greater than or equal to I bits wide should use sc_bv's instead of uint32/vluint64_t's. The default is "--pins-bv 65", and the value must be less than or equal to 65. Versions before Verilator 3.671 defaulted to "--pins-bv 33". The more sc_bv is used, the worse for performance. Use the "/*verilator sc_bv*/" attribute to select specific ports to be sc_bv. =item --pins-sc-uint Specifies SystemC inputs/outputs of greater than 2 bits wide should use sc_uint between 2 and 64. When combined with the "--pins-sc-biguint" combination, it results in sc_uint being used between 2 and 64 and sc_biguint being used between 65 and 512. =item --pins-sc-biguint Specifies SystemC inputs/outputs of greater than 65 bits wide should use sc_biguint between 65 and 512, and sc_bv from 513 upwards. When combined with the "--pins-sc-uint" combination, it results in sc_uint being used between 2 and 64 and sc_biguint being used between 65 and 512. =item --pins-uint8 Specifies SystemC inputs/outputs that are smaller than the --pins-bv setting and 8 bits or less should use uint8_t instead of uint32_t. Likewise pins of width 9-16 will use uint16_t instead of uint32_t. =item --pipe-filter I Rarely needed. Verilator will spawn the specified command as a subprocess pipe, to allow the command to perform custom edits on the Verilog code before it reaches Verilator. Before reading each Verilog file, Verilator will pass the file name to the subprocess' stdin with 'read ""'. The filter may then read the file and perform any filtering it desires, and feeds the new file contents back to Verilator on stdout by first emitting a line defining the length in bytes of the filtered output 'Content-Length: ', followed by the new filtered contents. Output to stderr from the filter feeds through to Verilator's stdout and if the filter exits with non-zero status Verilator terminates. See the t/t_pipe_filter test for an example. To debug the output of the filter, try using the -E option to see preprocessed output. =item --pp-comments With -E, show comments in preprocessor output. =item --prefix I Specifies the name of the top level class and makefile. Defaults to V prepended to the name of the --top-module switch, or V prepended to the first Verilog filename passed on the command line. =item --prof-cfuncs Modify the created C++ functions to support profiling. The functions will be minimized to contain one "basic" statement, generally a single always block or wire statement. (Note this will slow down the executable by ~5%.) Furthermore, the function name will be suffixed with the basename of the Verilog module and line number the statement came from. This allows gprof or oprofile reports to be correlated with the original Verilog source statements. See also L. =item --prof-threads Enable gantt chart data collection for threaded builds. Verilator will record the start and end time of each macro-task across a number of calls to eval. (What is a macro-task? See the Verilator internals document.) When profiling is enabled, the simulation runtime will emit a blurb of profiling data in non-human-friendly form. The C script will transform this into a nicer visual format and produce some related statistics. =item --protect-key I Specifies the private key for --protect-ids. For best security this key should be 16 or more random bytes, a reasonable secure choice is the output of C. Typically, a key would be created by the user once for a given protected design library, then every Verilator run for subsequent versions of that library would be passed the same --protect-key. Thus, if the input Verilog is similar between library versions (Verilator runs), the Verilated code will likewise be mostly similar. If --protect-key is not specified and a key is needed, Verilator will generate a new key for every Verilator run. As the key is not saved, this is best for security, but means every Verilator run will give vastly different output even for identical input, perhaps harming compile times (and certainly thrashing any I). =item --protect-ids Hash any private identifiers (variable, module, and assertion block names that are not on the top level) into hashed random-looking identifiers, resulting after compilation in protected library binaries that expose less design information. This hashing uses the provided or default --protect-key, see important details there. Verilator will also create a {prefix}__idmap.xml file which contains the mapping from the hashed identifiers back to the original identifiers. This idmap file is to be kept private, and is to assist mapping any simulation runtime design assertions, coverage, or trace information, which will report the hashed identifiers, back to the original design's identifier names. Using DPI imports/exports is allowed and generally relatively safe in terms of information disclosed, which is limited to the DPI function prototyptes. Use of the VPI is not recommended as many design details may be exposed, and an INSECURE warning will be issued. =item --protect-lib I Produces C++, Verilog wrappers and a Makefile which can in turn produce a DPI library which can be used by Verilator or other simulators along with the corresponding Verilog wrapper. The Makefile will build both a static and dynamic version of the library named libI.a and libI.so respectively. This is done because some simulators require a dynamic library, but the static library is arguably easier to use if possible. --protect-lib implies --protect-ids. This allows for the secure delivery of sensitive IP without the need for encrypted RTL (i.e. IEEE P1735). See examples/make_protect_lib in the distribution for a demonstration of how to build and use the DPI library. When using --protect-lib it is advised to also use C<--timescale-override /1fs> to ensure the model has a time resolution that is always compatible with the time precision of the upper instantiating module. =item --private Opposite of --public. Is the default; this option exists for backwards compatibility. =item --public This is only for historical debug use. Using it may result in mis-simulation of generated clocks. Declares all signals and modules public. This will turn off signal optimizations as if all signals had a /*verilator public*/ comments and inlining. This will also turn off inlining as if all modules had a /*verilator public_module*/, unless the module specifically enabled it with /*verilator inline_module*/. =item --public-flat-rw Declares all variables, ports and wires public as if they had /*verilator public_flat_rw @ ()*/ comments. This will make them VPI accessible by their flat name, but not turn off module inlining. This is particularly useful in combination with --vpi. This may also in some rare cases result in mis-simulation of generated clocks. Instead of this global switch, marking only those signals that need public_flat_rw is typically significantly better performing. =item -pvalue+I=I Overwrites the given parameter(s) of the toplevel module. See -G for a detailed description. =item --quiet-exit When exiting due to an error, do not display the "Exiting due to Errors" nor "Command Failed" messages. =item --relative-includes When a file references an include file, resolve the filename relative to the path of the referencing file, instead of relative to the current directory. =item --report-unoptflat Extra diagnostics for UNOPTFLAT warnings. This includes for each loop, the 10 widest variables in the loop, and the 10 most fanned out variables in the loop. These are candidates for splitting into multiple variables to break the loop. In addition produces a GraphViz DOT file of the entire strongly connected components within the source associated with each loop. This is produced irrespective of whether --dump-tree is set. Such graphs may help in analyzing the problem, but can be very large indeed. Various commands exist for viewing and manipulating DOT files. For example the I command can be used to convert a DOT file to a PDF for printing. For example: dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot will generate a PDF Vt_unoptflat_simple_2_35_unoptflat.dot.pdf from the DOT file. As an alternative, the I command can be used to view DOT files interactively: xdot Vt_unoptflat_simple_2_35_unoptflat.dot =item --rr Run Verilator and record with rr. See: rr-project.org. =item --savable Enable including save and restore functions in the generated model. The user code must create a VerilatedSerialize or VerilatedDeserialze object then calling the << or >> operators on the generated model and any other data the process needs saved/restored. These functions are not thread safe, and are typically called only by a main thread. For example: void save_model(const char* filenamep) { VerilatedSave os; os.open(filenamep); os << main_time; // user code must save the timestamp, etc os << *topp; } void restore_model(const char* filenamep) { VerilatedRestore os; os.open(filenamep); os >> main_time; os >> *topp; } =item --sc Specifies SystemC output mode; see also --cc. =item --stats Creates a dump file with statistics on the design in {prefix}__stats.txt. =item --stats-vars Creates more detailed statistics, including a list of all the variables by size (plain --stats just gives a count). See --stats, which is implied by this. =item --structs-packed Converts all unpacked structures to packed structures and issues a UNPACKED warning. Currently this is the default and --no-structs-packed will not work. Specifying this option allows for forward compatibility when a future version of Verilator no longer always packs unpacked structures. =item -sv Specifies SystemVerilog language features should be enabled; equivalent to "--language 1800-2005". This option is selected by default, it exists for compatibility with other simulators. =item +systemverilogext+I A synonym for C<+1800-2017ext+>I. =item --threads I =item --no-threads With --threads 0 or --no-threads, the default, the generated model is not thread safe. With --threads 1, the generated model is single threaded but may run in a multithreaded environment. With --threads N, where N >= 2, the model is generated to run multithreaded on up to N threads. See L. =item --threads-dpi all =item --threads-dpi none =item --threads-dpi pure When using --threads, controls which DPI imported tasks and functions are considered thread safe. With --threads-dpi all, enable Verilator to assume all DPI imports are threadsafe, and to use thread-local storage for communication with DPI, potentially improving performance. Any DPI libraries need appropriate mutexes to avoid undefined behavior. With --threads-dpi none, Verilator assume DPI imports are not thread safe, and Verilator will serialize calls to DPI imports by default, potentially harming performance. With --threads-dpi pure, the default, Verilator assumes DPI pure imports are threadsafe, but non-pure DPI imports are not. =item --threads-max-mtasks I Rarely needed. When using --threads, specify the number of mtasks the model is to be partitioned into. If unspecified, Verilator approximates a good value. =item --timescale I/I Sets default timescale, timeunit and timeprecision for when `timescale does not occur in sources. Default is "1ps/1ps" (to match SystemC). This is overridden by C<--timescale-override>. =item --timescale-override I/I =item --timescale-override /I Overrides all `timescales in sources. The timeunit may be left empty to specify only to override the timeprecision, e.g. "/1fs". The time precision must be consistent with SystemC's sc_set_time_resolution, or the C++ code instantiating the Verilated module. As 1fs is the finest time precision it may be desirable to always use a precision of 1fs. =item --top-module I When the input Verilog contains more than one top level module, specifies the name of the Verilog module to become the top level module, and sets the default for --prefix if not explicitly specified. This is not needed with standard designs with only one top. See also the MULTITOP warning section. =item --trace Adds waveform tracing code to the model using VCD format. This overrides C<--trace-fst>. Verilator will generate additional {prefix}__Trace*.cpp files that will need to be compiled. In addition verilated_vcd_sc.cpp (for SystemC traces) or verilated_vcd_c.cpp (for both) must be compiled and linked in. If using the Verilator generated Makefiles, these files will be added to the source file lists for you. If you are not using the Verilator Makefiles, you will need to add these to your Makefile manually. Having tracing compiled in may result in some small performance losses, even when tracing is not turned on during model execution. See also C<--trace-threads>. =item --trace-coverage With --trace and --coverage-*, enable tracing to include a traced signal for every --coverage-line or --coverage-user inserted coverage point, to assist in debugging coverage items. Note --coverage-toggle does not get additional signals added, as the original signals being toggle-analyzed are already visible. The added signal will be a 32-bit value which will increment on each coverage occurrence. Due to this, this option may greatly increase trace file sizes and reduce simulation speed. =item --trace-depth I Specify the number of levels deep to enable tracing, for example --trace-level 1 to only see the top level's signals. Defaults to the entire model. Using a small number will decrease visibility, but greatly improve simulation performance and trace file size. =item --trace-fst Enable FST waveform tracing in the model. This overrides C<--trace>. See also C<--trace-threads>. =item --trace-max-array I Rarely needed. Specify the maximum array depth of a signal that may be traced. Defaults to 32, as tracing large arrays may greatly slow traced simulations. =item --trace-max-width I Rarely needed. Specify the maximum bit width of a signal that may be traced. Defaults to 256, as tracing large vectors may greatly slow traced simulations. =item --no-trace-params Disable tracing of parameters. =item --trace-structs Enable tracing to show the name of packed structure, union, and packed array fields, rather than a single combined packed bus. Due to VCD file format constraints this may result in significantly slower trace times and larger trace files. =item --trace-threads I Enable waveform tracing using separate threads. This is typically faster in simulation runtime but uses more total compute. This option is independent of, and works with, both C<--trace> and C<--trace-fst>. Different trace formats can take advantage of more trace threads to varying degrees. Currently VCD tracing can utilize at most --trace-threads 1, and FST tracing can utilize at most --trace-threads 2. This overrides C<--no-threads>. =item --trace-underscore Enable tracing of signals that start with an underscore. Normally, these signals are not output during tracing. See also --coverage-underscore. =item -UI Undefines the given preprocessor symbol. =item --unroll-count I Rarely needed. Specifies the maximum number of loop iterations that may be unrolled. See also BLKLOOPINIT warning. =item --unroll-stmts I Rarely needed. Specifies the maximum number of statements in a loop for that loop to be unrolled. See also BLKLOOPINIT warning. =item --unused-regexp I Rarely needed. Specifies a simple regexp with * and ? that if a signal name matches will suppress the UNUSED warning. Defaults to "*unused*". Setting it to "" disables matching. =item -V Shows the verbose version, including configuration information compiled into Verilator. (Similar to perl -V.) See also --getenv. =item -v I Read the filename as a Verilog library. Any modules in the file may be used to resolve cell instantiations in the top level module, else ignored. Note -v is fairly standard across Verilog tools. =item --no-verilate When using --build, disable generation of C++/SystemC code, and execute only the build. This can be useful for rebuilding Verilated code produced by a previous invocation of Verilator. =item +verilog1995ext+I =item +verilog2001ext+I Synonyms for C<+1364-1995ext+>I and C<+1364-2001ext+>I respectively =item --version Displays program version and exits. =item --vpi Enable use of VPI and linking against the verilated_vpi.cpp files. =item --waiver-output Generate a waiver file which contains all waiver statements to suppress the warnings emitted during this Verilator run. This in particular is useful as a starting point for solving linter warnings or suppressing them systematically. The generated file is in the Verilator Configuration format, see L, and can directly be consumed by Verilator. The standard file extension is .vlt. =item -Wall Enable all code style warnings, including code style warnings that are normally disabled by default. Equivalent to "-Wwarn-lint -Wwarn-style". Excludes some specialty warnings, i.e. IMPERFECTSCH. =item -Werror-I Promote the specified warning message into an error message. This is generally to discourage users from violating important site-wide rules, for example C<-Werror-NOUNOPTFLAT>. =item -Wfuture-I Rarely needed. Suppress unknown Verilator comments or warning messages with the given message code. This is used to allow code written with pragmas for a later version of Verilator to run under a older version; add -Wfuture- arguments for each message code or comment that the new version supports which the older version does not support. =item -Wno-I Disable the specified warning/error message. This will override any lint_on directives in the source, i.e. the warning will still not be printed. =item -Wno-context Disable showing the suspected context of the warning message by quoting the source text at the suspected location. This can be used to appease tools which process the warning messages but may get confused by lines from the original source. =item -Wno-fatal When warnings are detected, print them, but do not terminate Verilator. Having warning messages in builds is sloppy. It is strongly recommended you cleanup your code, use inline lint_off, or use -Wno-... flags rather than using this option. =item -Wno-lint Disable all lint related warning messages, and all style warnings. This is equivalent to "-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED -Wno-WIDTH" plus the list shown for Wno-style. It is strongly recommended you cleanup your code rather than using this option, it is only intended to be use when running test-cases of code received from third parties. =item -Wno-style Disable all code style related warning messages (note by default they are already disabled). This is equivalent to "-Wno-DECLFILENAME -Wno-DEFPARAM -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY -Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED -Wno-VARHIDDEN". =item -Wpedantic Warn on any construct demanded by IEEE, and disable all Verilator extensions that may interfere with IEEE compliance to the standard defined with --default-language (etc). Similar to GCC's -Wpedantic. Rarely used, and intended only for strict compliance tests. =item -Wwarn-I Enables the specified warning message. =item -Wwarn-lint Enable all lint related warning messages (note by default they are already enabled), but do not affect style messages. This is equivalent to "-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASEWITHX -Wwarn-CMPCONST -Wwarn-COLONPLUS -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN -Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH". =item -Wwarn-style Enable all code style related warning messages. This is equivalent to "-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN -Wwarn-UNUSED -Wwarn-VARHIDDEN". =item --x-assign 0 =item --x-assign 1 =item --x-assign fast (default) =item --x-assign unique Controls the two-state value that is substituted when an explicit X value is encountered in the source. C<--x-assign fast>, the default, converts all Xs to whatever is best for performance. C<--x-assign 0> converts all Xs to 0s, and is also fast. C<--x-assign 1> converts all Xs to 1s, this is nearly as fast as 0, but more likely to find reset bugs as active high logic will fire. Using C<--x-assign unique> will result in all explicit Xs being replaced by a constant value determined at runtime. The value is determined by calling a function at initialization time. This enables randomization of Xs with different seeds on different executions. This method is the slowest, but safest for finding reset bugs. If using --x-assign unique, you may want to seed your random number generator such that each regression run gets a different randomization sequence. The simplest is to use the +verilator+seed runtime option. Alternatively use the system's srand48() or for Windows srand() function to do this. You'll probably also want to print any seeds selected, and code to enable rerunning with that same seed so you can reproduce bugs. B This option applies only to values which are explicitly written as X in the Verilog source code. Initial values of clocks are set to 0 unless --x-initial-edge is specified. Initial values of all other state holding variables are controlled with --x-initial. =item --x-initial 0 =item --x-initial fast =item --x-initial unique (default) Controls the two-state value that is used to initialize variables that are not otherwise initialized. C<--x-initial 0>, initializes all otherwise uninitialized variables to zero. C<--x-initial unique>, the default, initializes variables using a function, which determines the value to use each initialization. This gives greatest flexibility and allows finding reset bugs. See L. C<--x-initial fast>, is best for performance, and initializes all variables to a state Verilator determines is optimal. This may allow further code optimizations, but will likely hide any code bugs relating to missing resets. B This option applies only to initial values of variables. Initial values of clocks are set to 0 unless --x-initial-edge is specified. =item --x-initial-edge Enables emulation of event driven simulators which generally trigger an edge on a transition from X to 1 (C) or X to 0 (C). Thus the following code, where C is uninitialized would set C to C<1'b1> when C is first set to zero: reg res_n = 1'b0; always @(negedge rst_n) begin if (rst_n == 1'b0) begin res_n <= 1'b1; end end In Verilator, by default, uninitialized clocks are given a value of zero, so the above C block would not trigger. While it is not good practice, there are some designs that rely on X E 0 triggering a C, particularly in reset sequences. Using --x-initial-edge with Verilator will replicate this behavior. It will also ensure that X E 1 triggers a C. B Some users have reported that using this option can affect convergence, and that it may be necessary to use --converge-limit to increase the number of convergence iterations. This may be another indication of problems with the modeled design that should be addressed. =item --xml-only Create XML output only, do not create any other output. The XML format is intended to be used to leverage Verilator's parser and elaboration to feed to other downstream tools. Be aware that the XML format is still evolving; there will be some changes in future versions. =item --xml-output I Filename for XML output file. Using this option automatically sets --xml-only. =item -y I Add the directory to the list of directories that should be searched for include files or libraries. The three flags -y, +incdir and -I have similar effect; +incdir and +y are fairly standard across Verilog tools while -I is used by many C++ compilers. Verilator defaults to the current directory ("-y .") and any specified --Mdir, though these default paths are used after any user specified directories. This allows '-y "$(pwd)"' to be used if absolute filenames are desired for error messages instead of relative filenames. =back =head1 SIMULATION RUNTIME ARGUMENTS The following are the arguments that may be passed to a Verilated executable, provided that executable calls Verilated::commandArgs(). All simulation runtime arguments begin with +verilator, so that the user's executable may skip over all +verilator arguments when parsing its command line. =over 4 =item +verilator+debug Enable simulation runtime debugging. Equivalent to +verilator+debugi+4. =item +verilator+debugi+I Enable simulation runtime debugging at the provided level. =item +verilator+error+limit+I Set number of non-fatal errors (e.g. assertion failures) before exiting simulation runtime. Also affects number of $stop calls needed before exit. Defaults to 1. =item +verilator+help Display help and exit. =item +verilator+prof+threads+file+I When a model was Verilated using --prof-threads, sets the simulation runtime filename to dump to. Defaults to "profile_threads.dat". =item +verilator+prof+threads+start+I When a model was Verilated using --prof-threads, the simulation runtime will wait until $time is at this value (expressed in units of the time precision), then start the profiling warmup, then capturing. Generally this should be set to some time that is well within the normal operation of the simulation, i.e. outside of reset. If 0, the dump is disabled. Defaults to 1. =item +verilator+prof+threads+window+I When a model was Verilated using --prof-threads, after $time reaches +verilator+prof+threads+start, Verilator will warm up the profiling for this number of eval() calls, then will capture the profiling of this number of eval() calls. Defaults to 2, which makes sense for a single-clock-domain module where it's typical to want to capture one posedge eval() and one negedge eval(). =item +verilator+rand+reset+I When a model was Verilated using "-x-initial unique", sets the simulation runtime initialization technique. 0 = Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See L. =item +verilator+seed+I For $random and "-x-initial unique", set the simulation runtime random seed value. If zero or not specified picks a value from the system random number generator. =item +verilator+noassert Disable assert checking per runtime argument. This is the same as calling "Verilated::assertOn(false)" in the model. =item +verilator+V Shows the verbose version, including configuration information. =item +verilator+version Displays program version and exits. =back =head1 EXAMPLE C++ EXECUTION We'll compile this example into C++. mkdir test_our cd test_our cat >our.v <<'EOF' module our; initial begin $display("Hello World"); $finish; end endmodule EOF cat >sim_main.cpp <<'EOF' #include "Vour.h" #include "verilated.h" int main(int argc, char** argv, char** env) { Verilated::commandArgs(argc, argv); Vour* top = new Vour; while (!Verilated::gotFinish()) { top->eval(); } delete top; exit(0); } EOF See the README in the source kit for various ways to install or point to Verilator binaries. In brief, if you installed Verilator using the package manager of your operating system, or did a "make install" to place Verilator into your default path, you do not need anything special in your environment, and should not have VERILATOR_ROOT set. However, if you installed Verilator from sources and want to run Verilator out of where you compiled Verilator, you need to point to the kit: # See above; don't do this if using an OS-distributed Verilator export VERILATOR_ROOT=/path/to/where/verilator/was/installed export PATH=$VERILATOR_ROOT/bin:$PATH Now we run Verilator on our little example. verilator -Wall --cc our.v --exe --build sim_main.cpp We can see the source code under the "obj_dir" directory. See the FILES section below for descriptions of some of the files that were created. ls -l obj_dir (Verilator included a default compile rule and link rule, since we used --exe and passed a .cpp file on the Verilator command line. Verilator also then used C to build a final executable. You can also write your own compile rules, and run make yourself as we'll show in the SYSTEMC section.) And now we run it obj_dir/Vour And we get as output Hello World - our.v:2: Verilog $finish Really, you're better off writing a Makefile to do all this for you. Then, when your source changes it will automatically run all of these steps; to aid this Verilator can create a makefile dependency file. See the examples directory in the distribution. =head1 EXAMPLE SYSTEMC EXECUTION This is an example similar to the above, but using SystemC. mkdir test_our_sc cd test_our_sc cat >our.v <<'EOF' module our (clk); input clk; // Clock is required to get initial activation always @ (posedge clk) begin $display("Hello World"); $finish; end endmodule EOF cat >sc_main.cpp <<'EOF' #include "Vour.h" int sc_main(int argc, char** argv) { Verilated::commandArgs(argc, argv); sc_clock clk ("clk", 10, 0.5, 3, true); Vour* top; top = new Vour("top"); top->clk(clk); while (!Verilated::gotFinish()) { sc_start(1, SC_NS); } delete top; exit(0); } EOF See the README in the source kit for various ways to install or point to Verilator binaries. In brief, if you installed Verilator using the package manager of your operating system, or did a "make install" to place Verilator into your default path, you do not need anything special in your environment, and should not have VERILATOR_ROOT set. However, if you installed Verilator from sources and want to run Verilator out of where you compiled Verilator, you need to point to the kit: # See above; don't do this if using an OS-distributed Verilator export VERILATOR_ROOT=/path/to/where/verilator/was/installed export PATH=$VERILATOR_ROOT/bin:$PATH Now we run Verilator on our little example. verilator -Wall --sc our.v We then can compile it make -j -C obj_dir -f Vour.mk Vour__ALL.a make -j -C obj_dir -f Vour.mk ../sc_main.o verilated.o And link with SystemC. Note your path to the libraries may vary, depending on the operating system. cd obj_dir export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH # Might be needed if SystemC 2.3.0 export SYSTEMC_CXX_FLAGS=-pthread g++ -L$SYSTEMC_LIBDIR ../sc_main.o Vour__ALL.a verilated.o \ -o Vour -lsystemc And now we run it cd .. obj_dir/Vour And we get the same output as the C++ example: Hello World - our.v:2: Verilog $finish Really, you're better off using a Makefile to do all this for you. Then, when your source changes it will automatically run all of these steps. See the examples directory in the distribution. =head1 EVALUATION LOOP When using SystemC, evaluation of the Verilated model is managed by the SystemC kernel, and for the most part can be ignored. When using C++, the user must call eval(), or eval_step() and eval_end_step(). 1. When there is a single design instantiated at the C++ level that needs to evaluate, just call designp->eval(). 2. When there are multiple designs instantiated at the C++ level that need to evaluate, call first_designp->eval_step() then ->eval_step() on all other designs. Then call ->eval_end_step() on the first design then all other designs. If there is only a single design, you would call eval_step() then eval_end_step(); in fact eval() described above is just a wrapper which calls these two functions. When eval() is called Verilator looks for changes in clock signals and evaluates related sequential always blocks, such as computing always_ff @ (posedge...) outputs. Then Verilator evaluates combinatorial logic. Note combinatorial logic is not computed before sequential always blocks are computed (for speed reasons). Therefore it is best to set any non-clock inputs up with a separate eval() call before changing clocks. Alternatively, if all always_ff statements use only the posedge of clocks, or all inputs go directly to always_ff statements, as is typical, then you can change non-clock inputs on the negative edge of the input clock, which will be faster as there will be fewer eval() calls. For more information on evaluation, see docs/internals.adoc in the distribution. =head1 BENCHMARKING & OPTIMIZATION For best performance, run Verilator with the "-O3 --x-assign fast --x-initial fast --noassert" flags. The -O3 flag will require longer time to run Verilator, and "--x-assign fast --x-initial fast" may increase the risk of reset bugs in trade for performance; see the above documentation for these flags. If using Verilated multithreaded, use C to ensure you are using non-conflicting hardware resources. See L. Minor Verilog code changes can also give big wins. You should not have any UNOPTFLAT warnings from Verilator. Fixing these warnings can result in huge improvements; one user fixed their one UNOPTFLAT warning by making a simple change to a clock latch used to gate clocks and gained a 60% performance improvement. Beyond that, the performance of a Verilated model depends mostly on your C++ compiler and size of your CPU's caches. Experience shows that large models are often limited by the size of the instruction cache, and as such reducing code size if possible can be beneficial. The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT, OPT_FAST, OPT_SLOW and OPT_GLOBAL variables to control optimization. You can set these when compiling the output of Verilator with Make, for example: make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a OPT_FAST specifies optimization flags for those parts of the model that are on the fast path. This is mostly code that is executed every cycle. OPT_SLOW applies to slow-path code, which executes rarely, often only once at the beginning or end of simulation. Note that OPT_SLOW is ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code will be compiled in a single compilation unit using OPT_FAST. See also the C<--output-split> option. The OPT_GLOBAL variable applies to common code in the runtime library used by Verilated models (shipped in $VERILATOR_ROOT/include). Additional C++ files passed on the verilator command line use OPT_FAST. The OPT variable applies to all compilation units in addition to the specific OPT_* variables described above. You can also use the -CFLAGS and/or -LDFLAGS options on the verilator command line to pass flags directly to the compiler or linker. The default values of the OPT_* variables are chosen to yield good simulation speed with reasonable C++ compilation times. To this end, OPT_FAST is set to "-Os" by default. Higher optimization such as "-O2" or "-O3" may help (though often they provide only a very small performance benefit), but compile times may be excessively large even with medium sized designs. Compilation times can be improved at the expense of simulation speed by reducing optimization, for example with OPT_FAST="-O0". Often good simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing" but with improved compilation times. Files controlled by OPT_SLOW have little effect on performance and therefore OPT_SLOW is empty by default (equivalent to "-O0") for improved compilation speed. In common use-cases there should be little benefit in changing OPT_SLOW. OPT_GLOBAL is set to "-Os" by default and there should rarely be a need to change it. As the runtime library is small in comparison to a lot of Verilated models, disabling optimization on the runtime library should not have a serious effect on overall compilation time, but may have detrimental effect on simulation speed, especially with tracing. In addition to the above, for best results use OPT="-march=native", the latest Clang compiler (about 10% faster than GCC), and link statically. Generally the answer to which optimization level gives the best user experience depends on the use case and some experimentation can pay dividends. For a speedy debug cycle during development, especially on large designs where C++ compilation speed can dominate, consider using lower optimization to get to an executable faster. For throughput oriented use cases, for example regressions, it is usually worth spending extra compilation time to reduce total CPU time. If you will be running many simulations on a single model, you can investigate profile guided optimization. With GCC, using -fprofile-arcs, then -fbranch-probabilities will yield another 15% or so. Modern compilers also support link-time optimization (LTO), which can help especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in both compilation and link. Note LTO may cause excessive compile times on large designs. Unfortunately, using the optimizer with SystemC files can result in compilation taking several minutes. (The SystemC libraries have many little inlined functions that drive the compiler nuts.) If you are using your own makefiles, you may want to compile the Verilated code with -DVL_INLINE_OPT=inline. This will inline functions, however this requires that all cpp files be compiled in a single compiler run. You may uncover further tuning possibilities by profiling the Verilog code. Use Verilator's --prof-cfuncs, then GCC's -g -pg. You can then run either oprofile or gprof to see where in the C++ code the time is spent. Run the gprof output through verilator_profcfunc and it will tell you what Verilog line numbers on which most of the time is being spent. When done, please let the author know the results. We like to keep tabs on how Verilator compares, and may be able to suggest additional improvements. =head1 FILES All output files are placed in the output directory specified with the C<--Mdir> option, or "obj_dir" if not specified. Verilator creates the following files in the output directory: For --make gmake, it creates: {prefix}.mk // Make include file for compiling {prefix}_classes.mk // Make include file with class names For --make cmake, it creates: {prefix}.cmake // CMake include script for compiling For -cc and -sc mode, it also creates: {prefix}.cpp // Top level C++ file {prefix}.h // Top level header {prefix}__Slow{__n}.cpp // Constructors and infrequent cold routines {prefix}{__n}.cpp // Additional top C++ files (--output-split) {prefix}{each_verilog_module}.cpp // Lower level internal C++ files {prefix}{each_verilog_module}.h // Lower level internal header files {prefix}{each_verilog_module}{__n}.cpp // Additional lower C++ files (--output-split) In certain debug and other modes, it also creates: {prefix}.xml // XML tree information (--xml) {prefix}__Dpi.cpp // DPI import and export wrappers {prefix}__Dpi.h // DPI import and export declarations {prefix}__Inlines.h // Inline support functions {prefix}__Syms.cpp // Global symbol table C++ {prefix}__Syms.h // Global symbol table header {prefix}__Trace__Slow{__n}.cpp // Wave file generation code (--trace) {prefix}__Trace{__n}.cpp // Wave file generation code (--trace) {prefix}__cdc.txt // Clock Domain Crossing checks (--cdc) {prefix}__stats.txt // Statistics (--stats) {prefix}__idmap.txt // Symbol demangling (--protect-ids) It also creates internal files that can be mostly ignored: {mod_prefix}_{each_verilog_module}{__n}.vpp // Pre-processed verilog {prefix}__ver.d // Make dependencies (-MMD) {prefix}__verFiles.dat // Timestamps for skip-identical {prefix}{misc}.dot // Debugging graph files (--debug) {prefix}{misc}.tree // Debugging files (--debug) After running Make, the C++ compiler may produce the following: verilated{misc}.d // Intermediate dependencies verilated{misc}.o // Intermediate objects {mod_prefix}{misc}.d // Intermediate dependencies {mod_prefix}{misc}.o // Intermediate objects {prefix} // Final executable (w/--exe argument) {prefix}__ALL.a // Library of all Verilated objects {prefix}__ALL.cpp // Include of all code for single compile {prefix}{misc}.d // Intermediate dependencies {prefix}{misc}.o // Intermediate objects =head1 ENVIRONMENT =over 4 =item LD_LIBRARY_PATH A generic Linux/OS variable specifying what directories have shared object (.so) files. This path should include SystemC and any other shared objects needed at simulation runtime. =item MAKE Names the executable of the make command invoked when using the --build option. Some operating systems may require "gmake" to this variable to launch GNU make. If this variable is not specified, "make" is used. =item OBJCACHE Optionally specifies a caching or distribution program to place in front of all runs of the C++ compiler. For example, "ccache". If using distcc or icecc/icecream, they would generally be run under cache; see the documentation for those programs. If OBJCACHE is not set, and at configure time ccache was present, ccache will be used as a default. =item SYSTEMC Deprecated. Used only if SYSTEMC_INCLUDE or SYSTEMC_LIBDIR is not set. If set, specifies the directory containing the SystemC distribution. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled). =item SYSTEMC_ARCH Deprecated. Used only if SYSTEMC_LIBDIR is not set. Specifies the architecture name used by the SystemC kit. This is the part after the dash in the lib-{...} directory name created by a 'make' in the SystemC distribution. If not set, Verilator will try to intuit the proper setting, or use the default optionally specified at configure time (before Verilator was compiled). =item SYSTEMC_CXX_FLAGS Specifies additional flags that are required to be passed to GCC when building the SystemC model. System 2.3.0 may need this set to "-pthread". =item SYSTEMC_INCLUDE If set, specifies the directory containing the systemc.h header file. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled), or computed from SYSTEMC/include. =item SYSTEMC_LIBDIR If set, specifies the directory containing the libsystemc.a library. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled), or computed from SYSTEMC/lib-SYSTEMC_ARCH. =item VERILATOR_BIN If set, specifies an alternative name of the C binary. May be used for debugging and selecting between multiple operating system builds. =item VERILATOR_COVERAGE_BIN If set, specifies an alternative name of the C. May be used for debugging and selecting between multiple operating system builds. =item VERILATOR_GDB If set, the command to run when using the --gdb option, such as "ddd". If not specified, it will use "gdb". =item VERILATOR_ROOT Specifies the directory containing the distribution kit. This is used to find the executable, Perl library, and include files. If not specified, it will come from a default optionally specified at configure time (before Verilator was compiled). It should not be specified if using a pre-compiled Verilator package as the hard-coded value should be correct. =back =head1 CONNECTING TO C++ Verilator creates a I.h and I.cpp file for the top level module, together with additional .h and .cpp files for internals. See the examples directory in the kit for examples. After the model is created, there will be a I.mk file that may be used with Make to produce a I__ALL.a file with all required objects in it. This is then linked with the user's C++ main loop to create the simulation executable. The user must write the C++ main loop of the simulation. Here is a simple example: #include // Defines common routines #include // Need std::cout #include "Vtop.h" // From Verilating "top.v" Vtop *top; // Instantiation of module vluint64_t main_time = 0; // Current simulation time // This is a 64-bit integer to reduce wrap over issues and // allow modulus. This is in units of the timeprecision // used in Verilog (or from --timescale-override) double sc_time_stamp () { // Called by $time in Verilog return main_time; // converts to double, to match // what SystemC does } int main(int argc, char** argv) { Verilated::commandArgs(argc, argv); // Remember args top = new Vtop; // Create instance top->reset_l = 0; // Set some inputs while (!Verilated::gotFinish()) { if (main_time > 10) { top->reset_l = 1; // Deassert reset } if ((main_time % 10) == 1) { top->clk = 1; // Toggle clock } if ((main_time % 10) == 6) { top->clk = 0; } top->eval(); // Evaluate model cout << top->out << endl; // Read a output main_time++; // Time passes... } top->final(); // Done simulating // // (Though this example doesn't get here) delete top; } Note signals are read and written as member variables of the model. You call the eval() method to evaluate the model. When the simulation is complete call the final() method to execute any SystemVerilog final blocks, and complete any assertions. See L. =head1 CONNECTING TO SYSTEMC Verilator will convert the top level module to a SC_MODULE. This module will plug directly into a SystemC netlist. The SC_MODULE gets the same pinout as the Verilog module, with the following type conversions: Pins of a single bit become bool. Pins 2-32 bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or vluint64_t's depending on the --no-pins64 switch. Wider pins become sc_bv's. (Uints simulate the fastest so are used where possible.) Lower modules are not pure SystemC code. This is a feature, as using the SystemC pin interconnect scheme everywhere would reduce performance by an order of magnitude. =head1 DIRECT PROGRAMMING INTERFACE (DPI) Verilator supports SystemVerilog Direct Programming Interface import and export statements. Only the SystemVerilog form ("DPI-C") is supported, not the original Synopsys-only DPI. =head2 DPI Example In the SYSTEMC example above, if you wanted to import C++ functions into Verilog, put in our.v: import "DPI-C" function int add (input int a, input int b); initial begin $display("%x + %x = %x", 1, 2, add(1,2)); endtask Then after Verilating, Verilator will create a file Vour__Dpi.h with the prototype to call this function: extern int add (int a, int b); From the sc_main.cpp file (or another .cpp file passed to the Verilator command line, or the link), you'd then: #include "svdpi.h" #include "Vour__Dpi.h" int add(int a, int b) { return a+b; } =head2 DPI System Task/Functions Verilator extends the DPI format to allow using the same scheme to efficiently add system functions. Simply use a dollar-sign prefixed system function name for the import, but note it must be escaped. export "DPI-C" function integer \$myRand; initial $display("myRand=%d", $myRand()); Going the other direction, you can export Verilog tasks so they can be called from C++: export "DPI-C" task publicSetBool; task publicSetBool; input bit in_bool; var_bool = in_bool; endtask Then after Verilating, Verilator will create a file Vour__Dpi.h with the prototype to call this function: extern void publicSetBool(svBit in_bool); From the sc_main.cpp file, you'd then: #include "Vour__Dpi.h" publicSetBool(value); Or, alternatively, call the function under the design class. This isn't DPI compatible but is easier to read and better supports multiple designs. #include "Vour__Dpi.h" Vour::publicSetBool(value); // or top->publicSetBool(value); Note that if the DPI task or function accesses any register or net within the RTL, it will require a scope to be set. This can be done using the standard functions within svdpi.h, after the module is instantiated, but before the task(s) and/or function(s) are called. For example, if the top level module is instantiated with the name "dut" and the name references within tasks are all hierarchical (dotted) names with respect to that top level module, then the scope could be set with #include "svdpi.h" ... svSetScope(svGetScopeFromName("TOP.dut")); (Remember that Verilator adds a "TOP" to the top of the module hierarchy.) Scope can also be set from within a DPI imported C function that has been called from Verilog by querying the scope of that function. See the sections on DPI Context Functions and DPI Header Isolation below and the comments within the svdpi.h header for more information. =head2 DPI Display Functions Verilator allows writing $display like functions using this syntax: import "DPI-C" function void \$my_display(input string formatted /*verilator sformat*/ ); The /*verilator sformat*/ indicates that this function accepts a $display like format specifier followed by any number of arguments to satisfy the format. =head2 DPI Context Functions Verilator supports IEEE DPI Context Functions. Context imports pass the simulator context, including calling scope name, and filename and line number to the C code. For example, in Verilog: import "DPI-C" context function int dpic_line(); initial $display("This is line %d, again, line %d\n", `line, dpic_line()); This will call C++ code which may then use the svGet* functions to read information, in this case the line number of the Verilog statement that invoked the dpic_line function: int dpic_line() { // Get a scope: svScope scope = svGetScope(); const char* scopenamep = svGetNameFromScope(scope); assert(scopenamep); const char* filenamep = ""; int lineno = 0; if (svGetCallerInfo(&filenamep, &lineno)) { printf("dpic_line called from scope %s on line %d\n", scopenamep, lineno); return lineno; } else { return 0; } } See the IEEE Standard for more information. =head2 DPI Header Isolation Verilator places the IEEE standard header files such as svdpi.h into a separate include directory, vltstd (VeriLaTor STandarD). When compiling most applications $VERILATOR_ROOT/include/vltstd would be in the include path along with the normal $VERILATOR_ROOT/include. However, when compiling Verilated models into other simulators which have their own svdpi.h and similar standard files with different contents, the vltstd directory should not be included to prevent picking up incompatible definitions. =head2 Public Functions Instead of DPI exporting, there's also Verilator public functions, which are slightly faster, but less compatible. =head1 VERIFICATION PROCEDURAL INTERFACE (VPI) Verilator supports a very limited subset of the VPI. This subset allows inspection, examination, value change callbacks, and depositing of values to public signals only. VPI is enabled with the verilator --vpi switch. To access signals via the VPI, Verilator must be told exactly which signals are to be accessed. This is done using the Verilator public pragmas documented below. Verilator has an important difference from an event based simulator; signal values that are changed by the VPI will not immediately propagate their values, instead the top level header file's eval() method must be called. Normally this would be part of the normal evaluation (i.e. the next clock edge), not as part of the value change. This makes the performance of VPI routines extremely fast compared to event based simulators, but can confuse some test-benches that expect immediate propagation. Note the VPI by its specified implementation will always be much slower than accessing the Verilator values by direct reference (structure->module->signame), as the VPI accessors perform lookup in functions at simulation runtime requiring at best hundreds of instructions, while the direct references are evaluated by the compiler and result in only a couple of instructions. For signal callbacks to work the main loop of the program must call VerilatedVpi::callValueCbs(). =head2 VPI Example In the below example, we have readme marked read-only, and writeme which if written from outside the model will have the same semantics as if it changed on the specified clock edge. cat >our.v <<'EOF' module our (input clk); reg readme /*verilator public_flat_rd*/; reg writeme /*verilator public_flat_rw @(posedge clk) */; initial $finish; endmodule EOF There are many online tutorials and books on the VPI, but an example that accesses the above signal "readme" would be: cat >sim_main.cpp <<'<eval(); VerilatedVpi::callValueCbs(); // For signal callbacks read_and_check(); } delete top; exit(0); } EOF =head1 CROSS COMPILATION Verilator supports cross-compiling Verilated code. This is generally used to run Verilator on a Linux system and produce C++ code that is then compiled on Windows. Cross compilation involves up to three different OSes. The build system is where you configured and compiled Verilator, the host system where you run Verilator, and the target system where you compile the Verilated code and run the simulation. Currently, Verilator requires the build and host system type to be the same, though the target system type may be different. To support this, ./configure and make Verilator on the build system. Then, run Verilator on the host system. Finally, the output of Verilator may be compiled on the different target system. To support this, none of the files that Verilator produces will reference any configure generated build-system specific files, such as config.h (which is renamed in Verilator to config_build.h to reduce confusion.) The disadvantage of this approach is that include/verilatedos.h must self-detect the requirements of the target system, rather than using configure. The target system may also require edits to the Makefiles, the simple Makefiles produced by Verilator presume the target system is the same type as the build system. =head2 CMake Verilator can be run using CMake, which takes care of both running Verilator and compiling the output. There is a CMake example in the examples/ directory. The following is a minimal CMakeLists.txt that would build the code listed in "EXAMPLE C++ EXECUTION": project(cmake_example) find_package(verilator HINTS $ENV{VERILATOR_ROOT}) add_executable(Vour sim_main.cpp) verilate(Vour SOURCES our.v) find_package will automatically find an installed copy of Verilator, or use a local build if VERILATOR_ROOT is set. It is recommended to use CMake >= 3.12 and the Ninja generator, though other combinations should work. To build with CMake, change to the folder containing CMakeLists.txt and run: mkdir build cd build cmake -GNinja .. ninja Or to build with your system default generator: mkdir build cd build cmake .. cmake --build . If you're building the example you should have an executable to run: ./Vour The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and VERILATOR_BIN to the appropriate values, and also creates a verilate() function. verilate() will automatically create custom commands to run Verilator and add the generated C++ sources to the target specified. verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name] [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE] [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...] [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...]) Lowercase and ... should be replaced with arguments, the uppercase parts delimit the arguments and can be passed in any order, or left out entirely if optional. verilate(target ...) can be called multiple times to add other verilog modules to an executable or library target. When generating Verilated SystemC sources, you should also include the SystemC include directories and link to the SystemC libraries. Verilator's CMake support provides a convenience function to automatically find and link to the SystemC library. It can be used as: verilator_link_systemc(target) where target is the name of your target. The search paths can be configured by setting some variables: - The variables SYSTEMC_INCLUDE and SYSTEMC_LIBDIR to give a direct path to the SystemC include an library path. - SYSTEMC_ROOT to set the installation prefix of an installed SystemC library. - SYSTEMC to set the installation prefix of an installed SystemC library (same as above). - When using Accellera's SystemC with CMake support, a CMake target is available that simplifies the above steps. This will only work if the SystemC installation can be found by CMake. This can be configured by setting the CMAKE_PREFIX_PATH variable during CMake configuration. Don't forget to set the same C++ standard for the Verilated sources as the SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS environment variable. =over 4 =item target Name of a target created by add_executable or add_library. =item SOURCES List of Verilog files to Verilate. Must have at least one file. =item PREFIX Optional. Sets the Verilator output prefix. Defaults to the name of the first source file with a "V" prepended. Must be unique in each call to verilate(), so this is necessary if you build a module multiple times with different parameters. Must be a valid C++ identifier, i.e. contains no white space and only characters A-Z, a-z, 0-9 or _. =item TOP_MODULE Optional. Sets the name of the top module. Defaults to the name of the first file in the SOURCES array. =item TRACE Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS --trace". =item TRACE_FST Optional. Enables FST tracing if present, equivalent to "VERILATOR_ARGS --trace-fst". =item SYSTEMC Optional. Enables SystemC mode, defaults to C++ if not specified. =item COVERAGE Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS --coverage" =item INCLUDE_DIRS Optional. Sets directories that Verilator searches (same as -y). =item OPT_SLOW Optional. Set compiler flags for the slow path. You may want to reduce the optimization level to improve compile times with large designs. =item OPT_FAST Optional. Set compiler flags for the fast path. =item OPT_GLOBAL Optional. Set compiler flags for the common runtime library used by Verilated models. =item DIRECTORY Optional. Set the verilator output directory. It is preferable to use the default, which will avoid collisions with other files. =item VERILATOR_ARGS Optional. Extra arguments to Verilator. Do not specify --Mdir or --prefix here, use DIRECTORY or PREFIX. =back =head1 MULTITHREADING Verilator supports multithreaded simulation models. With --no-threads, the default, the model is not thread safe, and any use of more than one thread calling into one or even different Verilated models may result in unpredictable behavior. This gives the highest single thread performance. With --threads 1, the generated model is single threaded, however the support libraries are multithread safe. This allows different instantiations of model(s) to potentially each be run under a different thread. All threading is the responsibility of the user's C++ testbench. With --threads N, where N is at least 2, the generated model will be designed to run in parallel on N threads. The thread calling eval() provides one of those threads, and the generated model will create and manage the other N-1 threads. It's the client's responsibility not to oversubscribe the available CPU cores. Under CPU oversubscription, the Verilated model should not livelock nor deadlock, however, you can expect performance to be far worse than it would be with proper ratio of threads and CPU cores. The remainder of this section describe behavior with --threads 1 or --threads N (not --no-threads). VL_THREADED is defined when compiling a threaded Verilated module, causing the Verilated support classes become threadsafe. The thread used for constructing a model must be the same thread that calls eval() into the model, this is called the "eval thread". The thread used to perform certain global operations such as saving and tracing must be done by a "main thread". In most cases the eval thread and main thread are the same thread (i.e. the user's top C++ testbench runs on a single thread), but this is not required. The --trace-threads options can be used to produce trace dumps using multiple threads. If --trace-threads is set without --threads, then --trace-threads will imply --threads 1, i.e.: the support libraries will be thread safe. With --trace-threads 0, trace dumps are produced on the main thread. This again gives the highest single thread performance. With --trace-threads N, where N is at least 1, N additional threads will be created and managed by the trace files (e.g.: VerilatedVcdC or VerilatedFstC), to generate the trace dump. The main thread will be released to proceed with execution as soon as possible, though some blocking of the main thread is still necessary while capturing the trace. Different trace formats can utilize a various number of threads. See the --trace-threads option. When running a multithreaded model, the default Linux task scheduler often works against the model, by assuming threads are short lived, and thus often schedules threads using multiple hyperthreads within the same physical core. For best performance use the C program to (when the threading count fits) select unique physical cores on the same socket. The same applies for --trace-threads as well. As an example, if a model was Verilated with "--threads 4", we consult egrep 'processor|physical id|core id' /proc/cpuinfo To select cores 0, 1, 2, and 3 that are all located on the same socket (0) but different physical cores. (Also useful is "numactl --hardware", or C but those doesn't show Hyperthreading cores.) Then we execute numactl -m 0 -C 0,1,2,3 -- verilated_executable_name This will limit memory to socket 0, and threads to cores 0, 1, 2, 3, (presumably on socket 0) optimizing performance. Of course this must be adjusted if you want another simulator using e.g. socket 1, or if you Verilated with a different number of threads. To see what CPUs are actually used, use --prof-threads. =head2 Multithreaded Verilog and Library Support $display/$stop/$finish are delayed until the end of an eval() call in order to maintain ordering between threads. This may result in additional tasks completing after the $stop or $finish. =over 4 If using --coverage, the coverage routines are fully thread safe. If using --dpi, Verilator assumes pure DPI imports are thread safe, balancing performance versus safety. See --threads-dpi. If using --savable, the save/restore classes are not multithreaded and must be called only by the eval thread. If using --sc, the SystemC kernel is not thread safe, therefore the eval thread and main thread must be the same. If using --trace, the tracing classes must be constructed and called from the main thread. If using --vpi, since SystemVerilog VPI was not architected by IEEE to be multithreaded, Verilator requires all VPI calls are only made from the main thread. =back =head1 CONFIGURATION FILES In addition to the command line, warnings and other features may be controlled by configuration files, typically named with the .vlt extension. An example: `verilator_config lint_off -rule WIDTH lint_off -rule CASEX -file "silly_vendor_code.v" This disables WIDTH warnings globally, and CASEX for a specific file. Configuration files are fed through the normal Verilog preprocessor prior to parsing, so `ifdefs, `defines, and comments may be used as if it were normal Verilog code. Note that file or line-specific configuration only applies to files read after the configuration file. It is therefore recommended to pass the configuration file to Verilator as the first file. The grammar of configuration commands is as follows: =over 4 =item `verilator_config Take remaining text and treat it as Verilator configuration commands. =item coverage_on [-file "" [-lines [ - ]]] =item coverage_off [-file "" [-lines [ - ]]] Enable/disable coverage for the specified filename (or wildcard with '*' or '?', or all files if omitted) and range of line numbers (or all lines if omitted). Often used to ignore an entire module for coverage analysis purposes. =item lint_on [-rule ] [-file "" [-lines [ - ]]] =item lint_off [-rule ] [-file "" [-lines [ - ]]] =item lint_off [-rule ] [-file ""] [-match ""] Enable/disables the specified lint warning, in the specified filename (or wildcard with '*' or '?', or all files if omitted) and range of line numbers (or all lines if omitted). With lint_off using '*' will override any lint_on directives in the source, i.e. the warning will still not be printed. If the -rule is omitted, all lint warnings (see list in -Wno-lint) are enabled/disabled. This will override all later lint warning enables for the specified region. If -match is set the linter warnings are matched against this (wildcard) string and are waived in case they match and iff rule and file (with wildcard) also match. In previous versions -rule was named -msg. The latter is deprecated, but still works with a deprecation info, it may be removed in future versions. =item tracing_on [-file "" [-lines [ - ]]] =item tracing_off [-file "" [-lines [ - ]]] Enable/disable waveform tracing for all future signals declared in the specified filename (or wildcard with '*' or '?', or all files if omitted) and range of line numbers (or all lines if omitted). For tracing_off, cells below any module in the files/ranges specified will also not be traced. =item clock_enable -module "" -var "" Indicate the signal is used to gate a clock, and the user takes responsibility for insuring there are no races related to it. Same as /*verilator clock_enable*/, see L for more information and an example. =item clocker -module "" [-task ""] -var "" =item clocker -module "" [-function ""] -var "" =item no_clocker -module "" [-task ""] -var "" =item no_clocker -module "" [-function ""] -var "" Indicate the signal is used as clock or not. This information is used by Verilator to mark the signal as clocker and propagate the clocker attribute automatically to derived signals. See C<--clk> for more information. Same as /*verilator clocker*/, see L for more information. =item coverage_block_off -module "" -block "" =item coverage_block_off -file "" -line Specifies the entire begin/end block should be ignored for coverage analysis purposes. Can either be specified as a named block or as a filename and line number. Same as /*verilator coverage_block_off*/, see L for more information. =item full_case -file "" -lines =item parallel_case -file "" -lines Same as "//synopsys full_case" and "//synopsys parallel_case". When these synthesis directives are discovered, Verilator will either formally prove the directive to be true, or failing that, will insert the appropriate code to detect failing cases at simulation runtime and print an "Assertion failed" error message. =item inline -module "" Specifies the module may be inlined into any modules that use this module. Same as /*verilator inline_module*/, and see that under L for more information. =item isolate_assignments -module "" [-task ""] -var "" =item isolate_assignments -module "" [-function ""] -var "" =item isolate_assignments -module "" -function "" Used to indicate the assignments to this signal in any blocks should be isolated into new blocks. When there is a large combinatorial block that is resulting in a UNOPTFLAT warning, attaching this to the signal causing a false loop may clear up the problem. Same as /* verilator isolate_assignments */, see L for more information. =item no_inline -module "" Specifies the module should not be inlined into any modules that use this module. Same as /*verilator no_inline_module*/, and see that under L for more information. =item no_inline [-module ""] -task "" =item no_inline [-module ""] -function "" Specify the function or task should not be inlined into where it is used. This may reduce the size of the final executable when a task is used a very large number of times. For this flag to work, the task and tasks below it must be pure; they cannot reference any variables outside the task itself. Same as /*verilator no_inline_task*/, see L for more information. =item public [-module ""] [-task/-function ""] -var "" =item public_flat [-module ""] [-task/-function ""] -var "" =item public_flat_rd [-module ""] [-task/-function ""] -var "" =item public_flat_rw [-module ""] [-task/-function ""] -var "" "@(edge)" Sets the variable to be public. Same as /*verilator public*/ or /*verilator public_flat*/ etc, see those under L for more information. =item sc_bv -module "" [-task ""] -var "" =item sc_bv -module "" [-function ""] -var "" Sets the port to be of sc_bv> type, instead of bool, vluint32_t or vluint64_t. Same as /*verilator sc_bv*/, see that under L for more information. =item sformat [-module ""] [-task ""] -var "" =item sformat [-module ""] [-function ""] -var "" Must be applied to the final argument of type "input string" of a function or task to indicate the function or task should pass all remaining arguments through $sformatf. This allows creation of DPI functions with $display like behavior. See the test_regress/t/t_dpi_display.v file for an example. Same as /*verilator sformat*/, see L for more information. =item split_var [-module ""] [-task ""] -var "" =item split_var [-module ""] [-function ""] -var "" Break the variable into multiple pieces typically to resolve UNOPTFLAT performance issues. Typically the variables to attach this to are recommended by Verilator itself, see UNOPTFLAT. Same as /*verilator split_var*/, see L for more information. =back =head1 LANGUAGE STANDARD SUPPORT =head2 Verilog 2001 (IEEE 1364-2001) Support Verilator supports most Verilog 2001 language features. This includes signed numbers, "always @*", generate statements, multidimensional arrays, localparam, and C-style declarations inside port lists. =head2 Verilog 2005 (IEEE 1364-2005) Support Verilator supports most Verilog 2005 language features. This includes the `begin_keywords and `end_keywords compiler directives, $clog2, and the uwire keyword. =head2 SystemVerilog 2005 (IEEE 1800-2005) Support Verilator supports ==? and !=? operators, ++ and -- in some contexts, $bits, $countbits, $countones, $error, $fatal, $info, $isunknown, $onehot, $onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit, byte, chandle, const, do-while, enum, export, final, import, int, interface, logic, longint, modport, package, program, shortint, struct, time, typedef, union, var, void, priority case/if, and unique case/if. It also supports .name and .* interconnection. Verilator partially supports concurrent assert and cover statements; see the enclosed coverage tests for the syntax which is allowed. =head2 SystemVerilog 2012 (IEEE 1800-2012) Support Verilator implements a full SystemVerilog 2012 preprocessor, including function call-like preprocessor defines, default define arguments, `__FILE__, `__LINE__ and `undefineall. Verilator currently has some support for SystemVerilog synthesis constructs. As SystemVerilog features enter common usage they are added; please file a bug if a feature you need is missing. =head2 SystemVerilog 2017 (IEEE 1800-2017) Support Verilator supports the 2017 "for" loop constructs, and several minor cleanups made in 1800-2017. =head2 Verilog AMS Support Verilator implements a very small subset of Verilog AMS (Verilog Analog and Mixed-Signal Extensions) with the subset corresponding to those VMS keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009 languages. AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS". At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt, string, and wreal. =head2 Synthesis Directive Assertion Support With the --assert switch, Verilator reads any "//synopsys full_case" or "//synopsys parallel_case" directives. The same applies to any "//ambit synthesis", "//cadence" or "//pragma" directives of the same form. When these synthesis directives are discovered, Verilator will either formally prove the directive to be true, or failing that, will insert the appropriate code to detect failing cases at simulation runtime and print an "Assertion failed" error message. Verilator likewise also asserts any "unique" or "priority" SystemVerilog keywords on case statement, as well as "unique" on if statements. However, "priority if" is currently simply ignored. =head1 LANGUAGE EXTENSIONS The following additional constructs are the extensions Verilator supports on top of standard Verilog code. Using these features outside of comments or `ifdef's may break other tools. =over 4 =item `__FILE__ The __FILE__ define expands to the current filename as a string, like C++'s __FILE__. This was incorporated into to the 1800-2009 standard (but supported by Verilator since 2006!) =item `__LINE__ The __LINE__ define expands to the current filename as a string, like C++'s __LINE__. This was incorporated into to the 1800-2009 standard (but supported by Verilator since 2006!) =item `error I This will report an error when encountered, like C++'s #error. =item $c(I, ...); The string will be embedded directly in the output C++ code at the point where the surrounding Verilog code is compiled. It may either be a standalone statement (with a trailing ; in the string), or a function that returns up to a 32-bit number (without a trailing ;). This can be used to call C++ functions from your Verilog code. String arguments will be put directly into the output C++ code. Expression arguments will have the code to evaluate the expression inserted. Thus to call a C++ function, $c("func(",a,")") will result in 'func(a)' in the output C++ code. For input arguments, rather than hard-coding variable names in the string $c("func(a)"), instead pass the variable as an expression $c("func(",a,")"). This will allow the call to work inside Verilog functions where the variable is flattened out, and also enable other optimizations. If you will be reading or writing any Verilog variables inside the C++ functions, the Verilog signals must be declared with /*verilator public*/. You may also append an arbitrary number to $c, generally the width of the output. [signal_32_bits = $c32("...");] This allows for compatibility with other simulators which require a differently named PLI function name for each different output width. =item $display, $write, $fdisplay, $fwrite, $sformat, $swrite Format arguments may use C fprintf sizes after the % escape. Per the Verilog standard, %x prints a number with the natural width, and %0x prints a number with minimum width. Verilator extends this so %5x prints 5 digits per the C standard (this is unspecified in Verilog, but was incorporated into the 1800-2009). =item `coverage_block_off Specifies the entire begin/end block should be ignored for coverage analysis. Must be inside a code block, e.g. within a begin/end pair. Same as /* verilator coverage_block_off */ and C in L. =item `systemc_header Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the output .h file's header. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. =item `systemc_ctor Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the C++ class constructor. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. =item `systemc_dtor Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the C++ class destructor. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. =item `systemc_interface Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the C++ class interface. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. =item `systemc_imp_header Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into the header of all files for this C++ class implementation. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. =item `systemc_implementation Take remaining text up to the next `verilog or `systemc_... mode switch and place it verbatim into a single file of the C++ class implementation. Must be placed as a module item, e.g. directly inside a module/endmodule pair. Despite the name of this macro, this also works in pure C++ code. If you will be reading or writing any Verilog variables in the C++ functions, the Verilog signals must be declared with /*verilator public*/. See also the public task feature; writing an accessor may result in cleaner code. =item `SYSTEMVERILOG The SYSTEMVERILOG, SV_COV_START and related standard defines are set by default when --language is 1800-*. =item `VERILATOR =item `verilator =item `verilator3 The VERILATOR, verilator and verilator3 defines are set by default so you may `ifdef around tool specific constructs. =item `verilator_config Take remaining text up to the next `verilog mode switch and treat it as Verilator configuration commands. =item `verilog Switch back to processing Verilog code after a `systemc_... mode switch. The Verilog code returns to the last language mode specified with `begin_keywords, or SystemVerilog if none was specified. =item /*verilator clock_enable*/ Used after a signal declaration to indicate the signal is used to gate a clock, and the user takes responsibility for insuring there are no races related to it. (Typically by adding a latch, and running static timing analysis.) For example: reg enable_r /*verilator clock_enable*/; wire gated_clk = clk & enable_r; always_ff @ (posedge clk) enable_r <= enable_early; The clock_enable attribute will cause the clock gate to be ignored in the scheduling algorithm, sometimes required for correct clock behavior, and always improving performance. It's also a good idea to enable the IMPERFECTSCH warning, to ensure all clock enables are properly recognized. Same as C in configuration files, see L for more information. =item /*verilator clocker*/ =item /*verilator no_clocker*/ Used after a signal declaration to indicate the signal is used as clock or not. This information is used by Verilator to mark the signal as clocker and propagate the clocker attribute automatically to derived signals. See C<--clk> for more information. Same as C and C in configuration files, see L for more information. =item /*verilator coverage_block_off*/ Specifies the entire begin/end block should be ignored for coverage analysis purposes. Same as C in configuration files, see L for more information. =item /*verilator coverage_off*/ Specifies that following lines of code should have coverage disabled. Often used to ignore an entire module for coverage analysis purposes. =item /*verilator coverage_on*/ Specifies that following lines of code should have coverage re-enabled (if appropriate --coverage flags are passed) after being disabled earlier with /*verilator coverage_off*/. =item /*verilator inline_module*/ Specifies the module the comment appears in may be inlined into any modules that use this module. This is useful to speed up simulation runtime. Note if using "--public" that signals under inlined submodules will be named I__DOT__I as C++ does not allow "." in signal names. Same as C in configuration files, see L for more information. =item /*verilator isolate_assignments*/ Used after a signal declaration to indicate the assignments to this signal in any blocks should be isolated into new blocks. When there is a large combinatorial block that is resulting in a UNOPTFLAT warning, attaching this to the signal causing a false loop may clear up the problem. IE, with the following reg splitme /* verilator isolate_assignments*/; // Note the placement of the semicolon above always @* begin if (....) begin splitme = ....; other assignments end end Verilator will internally split the block that assigns to "splitme" into two blocks: It would then internally break it into (sort of): // All assignments excluding those to splitme always @* begin if (....) begin other assignments end end // All assignments to splitme always @* begin if (....) begin splitme = ....; end end Same as C in configuration files, see L for more information. =item /*verilator lint_off I*/ Disable the specified warning message for any warnings following the comment. =item /*verilator lint_on I*/ Re-enable the specified warning message for any warnings following the comment. =item /*verilator lint_restore*/ After a /*verilator lint_save*/, pop the stack containing lint message state. Often this is useful at the bottom of include files. =item /*verilator lint_save*/ Push the current state of what lint messages are turned on or turned off to a stack. Later meta-comments may then lint_on or lint_off specific messages, then return to the earlier message state by using /*verilator lint_restore*/. For example: // verilator lint_save // verilator lint_off SOME_WARNING ... // code needing SOME_WARNING turned off // verilator lint_restore If SOME_WARNING was on before the lint_off, it will now be restored to on, and if it was off before the lint_off it will remain off. =item /*verilator no_inline_module*/ Specifies the module the comment appears in should not be inlined into any modules that use this module. Same as C in configuration files, see L for more information. =item /*verilator no_inline_task*/ Used in a function or task variable definition section to specify the function or task should not be inlined into where it is used. This may reduce the size of the final executable when a task is used a very large number of times. For this flag to work, the task and tasks below it must be pure; they cannot reference any variables outside the task itself. Same as C in configuration files, see L for more information. =item /*verilator public*/ (parameter) Used after a parameter declaration to indicate the emitted C code should have the parameter values visible. Due to C++ language restrictions, this may only be used on 64-bit or narrower integral enumerations. parameter [2:0] PARAM /*verilator public*/ = 2'b0; =item /*verilator public*/ (typedef enum) Used after an enum typedef declaration to indicate the emitted C code should have the enum values visible. Due to C++ language restrictions, this may only be used on 64-bit or narrower integral enumerations. typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/; =item /*verilator public*/ (variable) Used after an input, output, register, or wire declaration to indicate the signal should be declared so that C code may read or write the value of the signal. This will also declare this module public, otherwise use /*verilator public_flat*/. Instead of using public variables, consider instead making a DPI or public function that accesses the variable. This is nicer as it provides an obvious entry point that is also compatible across simulators. Same as C in configuration files, see L for more information. =item /*verilator public*/ (task/function) Used inside the declaration section of a function or task declaration to indicate the function or task should be made into a C++ function, public to outside callers. Public tasks will be declared as a void C++ function, public functions will get the appropriate non-void (bool, uint32_t, etc) return type. Any input arguments will become C++ arguments to the function. Any output arguments will become C++ reference arguments. Any local registers/integers will become function automatic variables on the stack. Wide variables over 64 bits cannot be function returns, to avoid exposing complexities. However, wide variables can be input/outputs; they will be passed as references to an array of 32-bit numbers. Generally, only the values of stored state (flops) should be written, as the model will NOT notice changes made to variables in these functions. (Same as when a signal is declared public.) You may want to use DPI exports instead, as it's compatible with other simulators. Same as C in configuration files, see L for more information. =item /*verilator public_flat*/ (variable) Used after an input, output, register, or wire declaration to indicate the signal should be declared so that C code may read or write the value of the signal. This will not declare this module public, which means the name of the signal or path to it may change based upon the module inlining which takes place. Same as C in configuration files, see L for more information. =item /*verilator public_flat_rd*/ (variable) Used after an input, output, register, or wire declaration to indicate the signal should be declared public_flat (see above), but read-only. Same as C in configuration files, see L for more information. =item /*verilator public_flat_rw @() */ (variable) Used after an input, output, register, or wire declaration to indicate the signal should be declared public_flat_rd (see above), and also writable, where writes should be considered to have the timing specified by the given sensitivity edge list. Set for all variables, ports and wires using the --public-flat-rw switch. Same as C in configuration files, see L for more information. =item /*verilator public_module*/ Used after a module statement to indicate the module should not be inlined (unless specifically requested) so that C code may access the module. Verilator automatically sets this attribute when the module contains any public signals or `systemc_ directives. Also set for all modules when using the --public switch. Same as C in configuration files, see L for more information. =item /*verilator sc_clock*/ Deprecated. Used after an input declaration to indicate the signal should be declared in SystemC as a sc_clock instead of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 and later do not require clock pins to be sc_clocks and this is no longer needed. =item /*verilator sc_bv*/ Used after a port declaration. It sets the port to be of sc_bv> type, instead of bool, vluint32_t or vluint64_t. This may be useful if the port width is parameterized and the instantiating C++ code wants to always have a sc_bv so it can accept any width. In general you should avoid using this attribute when not necessary as with increasing usage of sc_bv the performance decreases significantly. Same as C in configuration files, see L for more information. =item /*verilator sformat*/ Attached to the final argument of type "input string" of a function or task to indicate the function or task should pass all remaining arguments through $sformatf. This allows creation of DPI functions with $display like behavior. See the test_regress/t/t_dpi_display.v file for an example. Same as C in configuration files, see L for more information. =item /*verilator split_var*/ Attached to a variable or a net declaration to break the variable into multiple pieces typically to resolve UNOPTFLAT performance issues. Typically the variables to attach this to are recommended by Verilator itself, see UNOPTFLAT below. For example, Verilator will internally convert a variable with the metacomment such as: logic [7:0] x [0:1] /*verilator split_var*/; To: logic [7:0] x__BRA__0__KET__ /*verilator split_var*/; logic [7:0] x__BRA__1__KET__ /*verilator split_var*/; Note that the generated packed variables retain the split_var metacomment because they may be split into further smaller pieces according to the access patterns. This only supports unpacked arrays, packed arrays, and packed structs of integer types (reg, logic, bit, byte, int...); otherwise if a split was requested but cannot occur a SPLITVAR warning is issued. Splitting large arrays may slow down the Verilation speed, so use this only on variables that require it. Same as C in configuration files, see L for more information. =item /*verilator tag */ Attached after a variable or structure member to indicate opaque (to Verilator) text that should be passed through to the XML output as a tag, for use by downstream applications. =item /*verilator tracing_off*/ Disable waveform tracing for all future signals that are declared in this module, or cells below this module. Often this is placed just after a primitive's module statement, so that the entire module and cells below it are not traced. =item /*verilator tracing_on*/ Re-enable waveform tracing for all future signals or cells that are declared. =back =head1 LANGUAGE LIMITATIONS There are some limitations and lack of features relative to the major closed-source simulators, by intent. =head2 Synthesis Subset Verilator supports the Synthesis subset with other verification constructs being added over time. Verilator also simulates events as Synopsys's Design Compiler would; namely given a block of the form: always @ (x) y = x & z; This will recompute y when there is even a potential for change in x or a change in z, that is when the flops computing x or z evaluate (which is what Design Compiler will synthesize.) A compliant simulator would only calculate y if x changes. We recommend using always_comb to make the code run the same everywhere. Also avoid putting $displays in combo blocks, as they may print multiple times when not desired, even on compliant simulators as event ordering is not specified. =head2 Signal Naming To avoid conflicts with C symbol naming, any character in a signal name that is not alphanumeric nor a single underscore will be replaced by __0hh where hh is the hex code of the character. To avoid conflicts with Verilator's internal symbols, any double underscore are replaced with ___05F (5F is the hex code of an underscore.) =head2 Bind Verilator only supports "bind" to a target module name, not an instance path. =head2 Class Verilator class support is limited but in active development. Verilator supports members, and methods. Verilator does not support class static members, class extend, or class parameters. =head2 Dotted cross-hierarchy references Verilator supports dotted references to variables, functions and tasks in different modules. The portion before the dot must have a constant value; for example a[2].b is acceptable, while a[x].b is generally not. References into generated and arrayed instances use the instance names specified in the Verilog standard; arrayed instances are named {cellName}[{instanceNumber}] in Verilog, which becomes {cellname}__BRA__{instanceNumber}__KET__ inside the generated C++ code. =head2 Latches Verilator is optimized for edge sensitive (flop based) designs. It will attempt to do the correct thing for latches, but most performance optimizations will be disabled around the latch. =head2 Structures and Unions Presently Verilator only supports packed structs and packed unions. Rand and randc tags on members are simply ignored. All structures and unions are represented as a single vector, which means that generating one member of a structure from blocking, and another from non-blocking assignments is unsupported. =head2 Time All delays (#) are ignored, as they are in synthesis. =head2 Unknown states Verilator is mostly a two state simulator, not a four state simulator. However, it has two features which uncover most initialization bugs (including many that a four state simulator will miss.) Identity comparisons (=== or !==) are converted to standard ==/!= when neither side is a constant. This may make the expression yield a different result compared to a four state simulator. An === comparison to X will always be false, so that Verilog code which checks for uninitialized logic will not fire. Assigning X to a variable will actually assign a constant value as determined by the --x-assign switch. This allows runtime randomization, thus if the value is actually used, the random value should cause downstream errors. Integers also get randomized, even though the Verilog 2001 specification says they initialize to zero. Note however that randomization happens at initialization time and hence during a single simulation run, the same constant (but random) value will be used every time the assignment is executed. All variables, depending on --x-initial setting, are typically randomly initialized using a function. By running several random simulation runs you can determine that reset is working correctly. On the first run, have the function initialize variables to zero. On the second, have it initialize variables to one. On the third and following runs have it initialize them randomly. If the results match, reset works. (Note this is what the hardware will really do.) In practice, just setting all variables to one at startup finds most problems (since typically control signals are active-high). --x-assign applies to variables explicitly initialized or assigned an X. Uninitialized clocks are initialized to zero, while all other state holding variables are initialized to a random value. Event driven simulators will generally trigger an edge on a transition from X to 1 (C) or X to 0 (C). However, by default, since clocks are initialized to zero, Verilator will not trigger an initial negedge. Some code (particularly for reset) may rely on X->0 triggering an edge. The --x-initial-edge switch enables this behavior. Comparing runs with and without this switch will find such problems. =head2 Tri/Inout Verilator converts some simple tristate structures into two state. Pullup, pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are also supported. Simple comparisons with === 1'bz are also supported. An assignment of the form: inout driver; wire driver = (enable) ? output_value : 1'bz; Will be converted to input driver; // Value being driven in from "external" drivers output driver__en; // True if driven from this module output driver__out; // Value being driven from this module External logic will be needed to combine these signals with any external drivers. Tristate drivers are not supported inside functions and tasks; an inout there will be considered a two state variable that is read and written instead of a four state variable. =head2 Functions & Tasks All functions and tasks will be inlined (will not become functions in C.) The only support provided is for simple statements in tasks (which may affect global variables). Recursive functions and tasks are not supported. All inputs and outputs are automatic, as if they had the Verilog 2001 "automatic" keyword prepended. (If you don't know what this means, Verilator will do what you probably expect -- what C does. The default behavior of Verilog is different.) =head2 Generated Clocks Verilator attempts to deal with generated and gated clocks correctly, however some cases cause problems in the scheduling algorithm which is optimized for performance. The safest option is to have all clocks as primary inputs to the model, or wires directly attached to primary inputs. For proper behavior clock enables may also need the /*verilator clock_enable*/ attribute. =head2 Gate Primitives The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are directly converted to behavioral equivalents. The 3-state and MOS gate primitives are not supported. Tables are not supported. =head2 Specify blocks All specify blocks and timing checks are ignored. All min:typ:max delays use the typical value. =head2 Array Initialization When initializing a large array, you need to use non-delayed assignments. Verilator will tell you when this needs to be fixed; see the BLKLOOPINIT error for more information. =head2 Array Out of Bounds Writing a memory element that is outside the bounds specified for the array may cause a different memory element inside the array to be written instead. For power-of-2 sized arrays, Verilator will give a width warning and the address. For non-power-of-2-sizes arrays, index 0 will be written. Reading a memory element that is outside the bounds specified for the array will give a width warning and wrap around the power-of-2 size. For non-power-of-2 sizes, it will return a unspecified constant of the appropriate width. =head2 Assertions Verilator is beginning to add support for assertions. Verilator currently only converts assertions to simple "if (...) error" statements, and coverage statements to increment the line counters described in the coverage section. Verilator does not support SEREs yet. All assertion and coverage statements must be simple expressions that complete in one cycle. =head2 Encrypted Verilog Open source simulators like Verilator are unable to use encrypted RTL (i.e. IEEE P1735). Talk to your IP vendor about delivering IP blocks via Verilator's --protect-lib feature. =head2 Language Keyword Limitations This section describes specific limitations for each language keyword. =over 4 =item `__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords, `endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor, `systemc_dtor, `systemc_header, `systemc_imp_header, `systemc_implementation, `systemc_interface, `undef, `verilog Fully supported. =item always, always_comb, always_ff, always_latch, and, assign, begin, buf, byte, case, casex, casez, default, defparam, do-while, else, end, endcase, endfunction, endgenerate, endmodule, endspecify, endtask, final, for, function, generate, genvar, if, initial, inout, input, int, integer, localparam, logic, longint, macromodule, module, nand, negedge, nor, not, or, output, parameter, posedge, reg, scalared, shortint, signed, supply0, supply1, task, time, tri, typedef, var, vectored, while, wire, xnor, xor Generally supported. =item ++, -- operators Increment/decrement can only be used as standalone statements or in certain limited cases. =item '{} operator Assignment patterns with order based, default, constant integer (array) or member identifier (struct/union) keys are supported. Data type keys and keys which are computed from a constant expression are not supported. =item `uselib Uselib, a vendor specific library specification method, is ignored along with anything following it until the end of that line. =item cast operator Casting is supported only between simple scalar types, signed and unsigned, not arrays nor structs. =item chandle Treated as a "longint"; does not yet warn about operations that are specified as illegal on chandles. =item disable Disable statements may be used only if the block being disabled is a block the disable statement itself is inside. This was commonly used to provide loop break and continue functionality before SystemVerilog added the break and continue keywords. =item inside Inside expressions may not include unpacked array traversal or $ as an upper bound. Case inside and case matches are also unsupported. =item interface Interfaces and modports, including with generated data types are supported. Generate blocks around modports are not supported, nor are virtual interfaces nor unnamed interfaces. =item shortreal Short floating point (shortreal) numbers are converted to real. Most other simulators either do not support float, or convert likewise. =item specify specparam All specify blocks and timing checks are ignored. =item uwire Verilator does not perform warning checking on uwires, it treats the uwire keyword as if it were the normal wire keyword. =item $bits, $countbits, $countones, $error, $fatal, $finish, $info, $isunknown, $onehot, $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, $time, $unsigned, $warning. Generally supported. =item $dump/$dumpports and related $dumpfile or $dumpports will create a VCD or FST file (which is based on the --trace argument given when the model was Verilated). This will take effect starting at the next eval() call. If you have multiple Verilated designs under the same C model, then this will dump signals only from the design containing the $dumpvars. $dumpvars and $dumpports module identifier is ignored; the traced instances will always start at the top of the design. The levels argument is also ignored, use tracing_on/tracing_off pragmas instead. $dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename argument is ignored, only a single trace file may be active at once. $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and $dumplimit/$dumpportlimit are currently ignored. =item $finish, $stop The rarely used optional parameter to $finish and $stop is ignored. =item $fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf Generally supported. =item $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, $setup, $setuphold, $skew, $timeskew, $width All specify blocks and timing checks are ignored. =item $monitor, $strobe Monitor and strobe are not supported, convert to always_comb $display or similar. =item $random $random does not support the optional argument to set the seed. Use the srand function in C to accomplish this, and note there is only one random number generator (not one per module). =item $readmemb, $readmemh Read memory commands should work properly. Note Verilator and the Verilog specification does not include support for readmem to multi-dimensional arrays. =item $test$plusargs, $value$plusargs Supported, but the instantiating C++/SystemC testbench must call Verilated::commandArgs(argc, argv); to register the command line before calling $test$plusargs or $value$plusargs. =back =head1 ERRORS AND WARNINGS Warnings may be disabled in three ways. First, when the warning is printed it will include a warning code. Simply surround the offending line with a lint_off/lint_on pair: // verilator lint_off UNSIGNED if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop; // verilator lint_on UNSIGNED Second, warnings may be disabled using a configuration file with a lint_off command. This is useful when a script is suppressing warnings and the Verilog source should not be changed. Warnings may also be globally disabled by invoking Verilator with the C<-Wno-I> switch. This should be avoided, as it removes all checking across the designs, and prevents other users from compiling your code without knowing the magic set of disables needed to successfully compile your design. =head2 Error and Warning Format Warnings and errors printed by Verilator always match this regular expression: %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.* Errors and warning start with a percent sign (historical heritage from Digital Equipment Corporation). Some errors or warning have a code attached, with meanings described below. Some errors also have a filename, line number and optional column number (starting at column 1 to match GCC). Following the error message, Verilator will typically show the user's source code corresponding to the error, prefixed by the line number and a " | ". Following this is typically an arrow and ~ pointing at the error on the source line directly above. =head2 List of all warnings =over 4 =item ALWCOMBORDER Warns that an always_comb block has a variable which is set after it is used. This may cause simulation-synthesis mismatches, as not all simulators allow this ordering. always_comb begin a = b; b = 1; end Ignoring this warning will only suppress the lint check, it will simulate correctly. =item ASSIGNIN Error that an assignment is being made to an input signal. This is almost certainly a mistake, though technically legal. input a; assign a = 1'b1; Ignoring this warning will only suppress the lint check, it will simulate correctly. =item ASSIGNDLY Warns that you have an assignment statement with a delayed time in front of it, for example: a <= #100 b; assign #100 a = b; Ignoring this warning may make Verilator simulations differ from other simulators, however at one point this was a common style so disabled by default as a code style warning. =item BLKANDNBLK BLKANDNBLK is an error that a variable comes from a mix of blocking and non-blocking assignments. Generally, this is caused by a register driven by both combo logic and a flop: always @ (posedge clk) foo[0] <= ... always @* foo[1] = ... Simply use a different register for the flop: always @ (posedge clk) foo_flopped[0] <= ... always @* foo[0] = foo_flopped[0]; always @* foo[1] = ... This is not illegal in SystemVerilog, but a violation of good coding practice. Verilator reports this as an error, because ignoring this warning may make Verilator simulations differ from other simulators. It is generally safe to disable this error (with a "// verilator lint_off BLKANDNBLK" metacomment or the -Wno-BLKANDNBLK option) when one of the assignments is inside a public task, or when the blocking and non-blocking assignments have non-overlapping bits and structure members. =item BLKSEQ This indicates that a blocking assignment (=) is used in a sequential block. Generally non-blocking/delayed assignments (<=) are used in sequential blocks, to avoid the possibility of simulator races. It can be reasonable to do this if the generated signal is used ONLY later in the same block, however this style is generally discouraged as it is error prone. always @ (posedge clk) foo = ... Disabled by default as this is a code style warning; it will simulate correctly. =item BLKLOOPINIT This indicates that the initialization of an array needs to use non-delayed assignments. This is done in the interest of speed; if delayed assignments were used, the simulator would have to copy large arrays every cycle. (In smaller loops, loop unrolling allows the delayed assignment to work, though it's a bit slower than a non-delayed assignment.) Here's an example always @ (posedge clk) if (~reset_l) begin for (i=0; i<`ARRAY_SIZE; i++) begin array[i] = 0; // Non-delayed for verilator end This message is only seen on large or complicated loops because Verilator generally unrolls small loops. You may want to try increasing --unroll-count (and occasionally --unroll-stmts) which will raise the small loop bar to avoid this error. =item BOUNDED This indicates that bounded queues (e.g. "var name[$ : 3]") are unsupported. Ignoring this warning may make Verilator simulations differ from other simulators. =item BSSPACE Warns that a backslash is followed by a space then a newline. Likely the intent was to have a backslash directly followed by a newline (e.g. when making a `define) and there's accidentally white space at the end of the line. If the space is not accidental, suggest removing the backslash in the code as it serves no function. Ignoring this warning will only suppress the lint check, it will simulate correctly. =item CASEINCOMPLETE Warns that inside a case statement there is a stimulus pattern for which there is no case item specified. This is bad style, if a case is impossible, it's better to have a "default: $stop;" or just "default: ;" so that any design assumption violations will be discovered in simulation. Ignoring this warning will only suppress the lint check, it will simulate correctly. =item CASEOVERLAP Warns that inside a case statement you have case values which are detected to be overlapping. This is bad style, as moving the order of case values will cause different behavior. Generally the values can be respecified to not overlap. Ignoring this warning will only suppress the lint check, it will simulate correctly. =item CASEX Warns that it is simply better style to use casez, and C in place of C's. See L Ignoring this warning will only suppress the lint check, it will simulate correctly. =item CASEWITHX Warns that a case statement contains a constant with a C. Verilator is two-state so interpret such items as always false. Note a common error is to use a C in a case or casez statement item; often what the user instead intended is to use a casez with C. Ignoring this warning will only suppress the lint check, it will simulate correctly. =item CDCRSTLOGIC With --cdc only, warns that asynchronous flop reset terms come from other than primary inputs or flopped outputs, creating the potential for reset glitches. =item CLKDATA Warns that clock signal is mixed used with/as data signal. The checking for this warning is enabled only if user has explicitly marked some signal as clocker using command line option or in-source meta comment (see C<--clk>). The warning can be disabled without affecting the simulation result. But it is recommended to check the warning as this may degrade the performance of the Verilated model. =item CMPCONST Warns that you are comparing a value in a way that will always be constant. For example "X > 1" will always be true when X is a single bit wide. Ignoring this warning will only suppress the lint check, it will simulate correctly. =item COLONPLUS Warns that a :+ is seen. Likely the intent was to use +: to select a range of bits. If the intent was a range that is explicitly positive, suggest adding a space, e.g. use ": +". Ignoring this warning will only suppress the lint check, it will simulate correctly. =item COMBDLY Warns that you have a delayed assignment inside of a combinatorial block. Using delayed assignments in this way is considered bad form, and may lead to the simulator not matching synthesis. If this message is suppressed, Verilator, like synthesis, will convert this to a non-delayed assignment, which may result in logic races or other nasties. See L Ignoring this warning may make Verilator simulations differ from other simulators. =item CONTASSREG Error that a continuous assignment is setting a reg. According to IEEE Verilog, but not SystemVerilog, a wire must be used as the target of continuous assignments. This error is only reported when "--language 1364-1995", "--language 1364-2001", or "--language 1364-2005" is used. Ignoring this error will only suppress the lint check, it will simulate correctly. =item DECLFILENAME Warns that a module or other declaration's name doesn't match the filename with path and extension stripped that it is declared in. The filename a modules/interfaces/programs is declared in should match the name of the module etc. so that -y directory searching will work. This warning is printed for only the first mismatching module in any given file, and -v library files are ignored. Disabled by default as this is a code style warning; it will simulate correctly. =item DEFPARAM Warns that the "defparam" statement was deprecated in Verilog 2001 and all designs should now be using the #(...) format to specify parameters. Disabled by default as this is a code style warning; it will simulate correctly. =item DETECTARRAY Error when Verilator tries to deal with a combinatorial loop that could not be flattened, and which involves a datatype which Verilator cannot handle, such as an unpacked struct or a large unpacked array. This typically occurs when -Wno-UNOPTFLAT has been used to override an UNOPTFLAT warning (see below). The solution is to break the loop, as described for UNOPTFLAT. =item DIDNOTCONVERGE Error at simulation runtime when model did not properly settle. Verilator sometimes has to evaluate combinatorial logic multiple times, usually around code where a UNOPTFLAT warning was issued, but disabled. For example: always_comb b = ~a; always_comb a = b This code will toggle forever, and thus to prevent an infinite loop, the executable will give the didn't converge error. To debug this, first review any UNOPTFLAT warnings that were ignored. Though typically it is safe to ignore UNOPTFLAT (at a performance cost), at the time of issuing a UNOPTFLAT Verilator did not know if the logic would eventually converge and assumed it would. Next, run Verilator with --prof-cfuncs. Run make on the generated files with "CPP_FLAGS=-DVL_DEBUG", to allow enabling simulation runtime debug messages. Rerun the test. Now just before the convergence error you should see additional output similar to this: CHANGE: filename.v:1: b CHANGE: filename.v:2: a This means that signal b and signal a keep changing, inspect the code that modifies these signals. Note if many signals are getting printed then most likely all of them are oscillating. It may also be that e.g. "a" may be oscillating, then "a" feeds signal "c" which then is also reported as oscillating. Finally, rare, more difficult cases can be debugged like a "C" program; either enter GDB and use its tracing facilities, or edit the generated C++ code to add appropriate prints to see what is going on. =item ENDLABEL Warns that a label attached to a "end"-something statement does not match the label attached to the block start. Ignoring this warning will only suppress the lint check, it will simulate correctly. =item GENCLK Deprecated and no longer used as a warning. Used to indicate that the specified signal was is generated inside the model, and also being used as a clock. =item IFDEPTH Warns that if/if else statements have exceeded the depth specified with --if-depth, as they are likely to result in slow priority encoders. Statements below unique and priority if statements are ignored. Solutions include changing the code to a case statement, or a SystemVerilog 'unique if' or 'priority if'. Disabled by default as this is a code style warning; it will simulate correctly. =item IGNOREDRETURN Warns that a non-void function is being called as a task, and hence the return value is being ignored. This warning is required by IEEE. The portable way to suppress this warning (in SystemVerilog) is to use a void cast, e.g. void'(function_being_called_as_task()); Ignoring this warning will only suppress the lint check, it will simulate correctly. =item IMPERFECTSCH Warns that the scheduling of the model is not absolutely perfect, and some manual code edits may result in faster performance. This warning defaults to off, is not part of -Wall, and must be turned on explicitly before the top module statement is processed. =item IMPLICIT Warns that a wire is being implicitly declared (it is a single bit wide output from a sub-module.) While legal in Verilog, implicit declarations only work for single bit wide signals (not buses), do not allow using a signal before it is implicitly declared by a cell, and can lead to dangling nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for Emacs, available from L Ignoring this warning will only suppress the lint check, it will simulate correctly. =item IMPORTSTAR Warns that an "import I::*" statement is in $unit scope. This causes the imported symbols to pollute the global namespace, defeating much of the purpose of having a package. Generally "import ::*" should only be used inside a lower scope such as a package or module. Disabled by default as this is a code style warning; it will simulate correctly. =item IMPURE Warns that a task or function that has been marked with /*verilator no_inline_task*/ references variables that are not local to the task. Verilator cannot schedule these variables correctly. Ignoring this warning may make Verilator simulations differ from other simulators. =item INCABSPATH Warns that an `include filename specifies an absolute path. This means the code will not work on any other system with a different file system layout. Instead of using absolute paths, relative paths (preferably without any directory specified whatsoever) should be used, and +incdir used on the command line to specify the top include source directories. Disabled by default as this is a code style warning; it will simulate correctly. =item INFINITELOOP Warns that a while or for statement has a condition that is always true. and thus results in an infinite loop if the statement ever executes. This might be unintended behavior if the loop body contains statements that in other simulators would make time pass, which Verilator is ignoring due to e.g. STMTDLY warnings being disabled. Ignoring this warning will only suppress the lint check, it will simulate correctly (i.e. hang due to the infinite loop). =item INITIALDLY Warns that you have a delayed assignment inside of an initial or final block. If this message is suppressed, Verilator will convert this to a non-delayed assignment. See also the COMBDLY warning. Ignoring this warning may make Verilator simulations differ from other simulators. =item INSECURE Warns that the combination of options selected may be defeating the attempt to protect/obscure identifiers or hide information in the model. Correct the options provided, or inspect the output code to see if the information exposed is acceptable. Ignoring this warning will only suppress the lint check, it will simulate correctly. =item LITENDIAN Warns that a packed vector is declared with little endian bit numbering (i.e. [0:7]). Big endian bit numbering is now the overwhelming standard, and little numbering is now thus often due to simple oversight instead of intent. Also warns that a cell is declared with little endian range (i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE the bits will likely be backwards from what you expect (i.e. cell [0] will connect to signal bit [N-1] not bit [0]). Ignoring this warning will only suppress the lint check, it will simulate correctly. =item MODDUP Warns that a module has multiple definitions. Generally this indicates a coding error, or a mistake in a library file and it's good practice to have one module per file (and only put each file once on the command line) to avoid these issues. For some gate level netlists duplicates are sometimes unavoidable, and MODDUP should be disabled. Ignoring this warning will cause the more recent module definition to be discarded. =item MULTIDRIVEN Warns that the specified signal comes from multiple always blocks. This is often unsupported by synthesis tools, and is considered bad style. It will also cause longer simulation runtimes due to reduced optimizations. Ignoring this warning will only slow simulations, it will simulate correctly. =item MULTITOP Warns that there are multiple top level modules, that is modules not instantiated by any other module, and both modules were put on the command line (not in a library). Three likely cases: 1. A single module is intended to be the top. This warning then occurs because some low level cell is being read in, but is not really needed as part of the design. The best solution for this situation is to ensure that only the top module is put on the command line without any flags, and all remaining library files are read in as libraries with -v, or are automatically resolved by having filenames that match the module names. 2. A single module is intended to be the top, the name of it is known, and all other modules should be ignored if not part of the design. The best solution is to use the --top-module option to specify the top module's name. All other modules that are not part of the design will be for the most part ignored (they must be clean in syntax and their contents will be removed as part of the Verilog module elaboration process.) 3. Multiple modules are intended to be design tops, e.g. when linting a library file. As multiple modules are desired, disable the MULTITOP warning. All input/outputs will go uniquely to each module, with any conflicting and identical signal names being made unique by adding a prefix based on the top module name followed by __02E (a Verilator-encoded ASCII ".'). This renaming is done even if the two modules' signals seem identical, e.g. multiple modules with a "clk" input. =item PINCONNECTEMPTY Warns that a cell instantiation has a pin which is connected to .pin_name(), e.g. not another signal, but with an explicit mention of the pin. It may be desirable to disable PINCONNECTEMPTY, as this indicates intention to have a no-connect. Disabled by default as this is a code style warning; it will simulate correctly. =item PINMISSING Warns that a module has a pin which is not mentioned in a cell instantiation. If a pin is not missing it should still be specified on the cell declaration with a empty connection, using "(.pin_name())". Ignoring this warning will only suppress the lint check, it will simulate correctly. =item PINNOCONNECT Warns that a cell instantiation has a pin which is not connected to another signal. Disabled by default as this is a code style warning; it will simulate correctly. =item PROCASSWIRE Error that a procedural assignment is setting a wire. According to IEEE, a var/reg must be used as the target of procedural assignments. =item REALCVT Warns that a real number is being implicitly rounded to an integer, with possible loss of precision. =item REDEFMACRO Warns that you have redefined the same macro with a different value, for example: `define MACRO def1 //... `define MACRO otherdef The best solution is to use a different name for the second macro. If this is not possible, add a undef to indicate the code is overriding the value: `define MACRO def1 //... `undef MACRO `define MACRO otherdef =item SELRANGE Warns that a selection index will go out of bounds: wire vec[6:0]; initial out = vec[7]; // There is no 7 Verilator will assume zero for this value, instead of X. Note that in some cases this warning may be false, when a condition upstream or downstream of the access means the access out of bounds will never execute or be used. wire vec[6:0]; initial begin seven = 7; ... if (seven != 7) out = vec[seven]; // Never will use vec[7] =item SHORTREAL Warns that Verilator does not support "shortreal" and they will be automatically promoted to "real". The recommendation is to replace any "shortreal" in the code with "real", as "shortreal" is not widely supported across industry tools. Ignoring this warning may make Verilator simulations differ from other simulators, if the increased precision of real affects your model or DPI calls. =item SPLITVAR Warns that a variable with a C metacomment was not split. Some possible reasons for this are: * The datatype of the variable is not supported for splitting. (e.g. is a real). * The access pattern of the variable can not be determined statically. (e.g. is accessed as a memory). * The index of the array exceeds the array size. * The variable is accessed from outside using dotted reference. (e.g. top.instance0.variable0 = 1). * The variable is not declared in a module, but in a package or an interface. * The variable is a parameter, localparam, genvar, or queue. * The variable is tristate or bidirectional. (e.g. inout or ref). =item STMTDLY Warns that you have a statement with a delayed time in front of it, for example: #100 $finish; Ignoring this warning may make Verilator simulations differ from other simulators. =item SYMRSVDWORD Warning that a symbol matches a C++ reserved word and using this as a symbol name would result in odd C++ compiler errors. You may disable this warning, but the symbol will be renamed by Verilator to avoid the conflict. =item SYNCASYNCNET Warns that the specified net is used in at least two different always statements with posedge/negedges (i.e. a flop). One usage has the signal in the sensitivity list and body, probably as an async reset, and the other usage has the signal only in the body, probably as a sync reset. Mixing sync and async resets is usually a mistake. The warning may be disabled with a lint_off pragma around the net, or either flopped block. Disabled by default as this is a code style warning; it will simulate correctly. =item TASKNSVAR Error when a call to a task or function has a output from that task tied to a non-simple signal. Instead connect the task output to a temporary signal of the appropriate width, and use that signal to set the appropriate expression as the next statement. For example: task foo; output sig; ... endtask always @* begin foo(bus_we_select_from[2]); // Will get TASKNSVAR error end Change this to: reg foo_temp_out; always @* begin foo(foo_temp_out); bus_we_select_from[2] = foo_temp_out; end Verilator doesn't do this conversion for you, as some more complicated cases would result in simulator mismatches. =item TICKCOUNT Warns that the number of ticks to delay a $past variable is greater than 10. At present Verilator effectively creates a flop for each delayed signals, and as such any large counts may lead to large design size increases. Ignoring this warning will only slow simulations, it will simulate correctly. =item TIMESCALEMOD Error that `timescale is used in some but not all modules. Recommend using --timescale argument, or in front of all modules use: `include "timescale.vh" Then in that file set the timescale. This is an error due to IEEE specifications, but it may be disabled similar to warnings. Ignoring this error may result in a module having an unexpected timescale. =item UNDRIVEN Warns that the specified signal has no source. Verilator is fairly liberal in the usage calculations; making a signal public, or setting only a single array element marks the entire signal as driven. Disabled by default as this is a code style warning; it will simulate correctly. =item UNOPT Warns that due to some construct, optimization of the specified signal or block is disabled. The construct should be cleaned up to improve simulation performance. A less obvious case of this is when a module instantiates two submodules. Inside submodule A, signal I is input and signal O is output. Likewise in submodule B, signal O is an input and I is an output. A loop exists and a UNOPT warning will result if AI & AO both come from and go to combinatorial blocks in both submodules, even if they are unrelated always blocks. This affects performance because Verilator would have to evaluate each submodule multiple times to stabilize the signals crossing between the modules. Ignoring this warning will only slow simulations, it will simulate correctly. =item UNOPTFLAT Warns that due to some construct, optimization of the specified signal is disabled. The signal reported includes a complete scope to the signal; it may be only one particular usage of a multiply instantiated block. The construct should be cleaned up to improve simulation performance; two times better performance may be possible by fixing these warnings. Unlike the UNOPT warning, this occurs after flattening the netlist, and indicates a more basic problem, as the less obvious case described under UNOPT does not apply. Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by synthesis which analyzes interconnection per-bit, but is circular to simulation which analyzes per-bus: wire [2:0] x = {x[1:0], shift_in}; This statement needs to be evaluated multiple times, as a change in "shift_in" requires "x" to be computed 3 times before it becomes stable. This is because a change in "x" requires "x" itself to change value, which causes the warning. For significantly better performance, split this into 2 separate signals: wire [2:0] xout = {x[1:0], shift_in}; and change all receiving logic to instead receive "xout". Alternatively, change it to wire [2:0] x = {xin[1:0], shift_in}; and change all driving logic to instead drive "xin". With this change this assignment needs to be evaluated only once. These sort of changes may also speed up your traditional event driven simulator, as it will result in fewer events per cycle. The most complicated UNOPTFLAT path we've seen was due to low bits of a bus being generated from an always statement that consumed high bits of the same bus processed by another series of always blocks. The fix is the same; split it into two separate signals generated from each block. Another way to resolve this warning is to add a C metacomment described above. This will cause the variable to be split internally, potentially resolving the conflict. If you run with --report-unoptflat Verilator will suggest possible candidates for C. The UNOPTFLAT warning may also be due to clock enables, identified from the reported path going through a clock gating cell. To fix these, use the clock_enable meta comment described above. The UNOPTFLAT warning may also occur where outputs from a block of logic are independent, but occur in the same always block. To fix this, use the isolate_assignments meta comment described above. To assist in resolving UNOPTFLAT, the option C<--report-unoptflat> can be used, which will provide suggestions for variables that can be split up, and a graph of all the nodes connected in the loop. See the L section for more details. Ignoring this warning will only slow simulations, it will simulate correctly. =item UNOPTTHREADS Warns that the thread scheduler was unable to partition the design to fill the requested number of threads. One workaround is to request fewer threads with C<--threads>. Another possible workaround is to allow more MTasks in the simulation runtime, by increasing the value of --threads-max-mtasks. More MTasks will result in more communication and synchronization overhead at simulation runtime; the scheduler attempts to minimize the number of MTasks for this reason. Ignoring this warning will only slow simulations, it will simulate correctly. =item UNPACKED Warns that unpacked structs and unions are not supported. Ignoring this warning will make Verilator treat the structure as packed, which may make Verilator simulations differ from other simulators. This downgrading may also result what would normally be a legal unpacked struct/array inside an unpacked struct/array becoming an illegal unpacked struct/array inside a packed struct/array. =item UNSIGNED Warns that you are comparing a unsigned value in a way that implies it is signed, for example "X < 0" will always be false when X is unsigned. Ignoring this warning will only suppress the lint check, it will simulate correctly. =item UNSUPPORTED UNSUPPORTED is an error that the construct might be legal according to IEEE but is not currently supported. This error may be ignored with --bbox-unsup, however this will make the design simulate incorrectly; see the details under --bbox-unsup. =item UNUSED Warns that the specified signal is never used/consumed. Verilator is fairly liberal in the usage calculations; making a signal public, a signal matching --unused-regexp ("*unused*") or accessing only a single array element marks the entire signal as used. Disabled by default as this is a code style warning; it will simulate correctly. A recommended style for unused nets is to put at the bottom of a file code similar to the following: wire _unused_ok = &{1'b0, sig_not_used_a, sig_not_used_yet_b, // To be fixed 1'b0}; The reduction AND and constant zeros mean the net will always be zero, so won't use simulation runtime. The redundant leading and trailing zeros avoid syntax errors if there are no signals between them. The magic name "unused" (-unused-regexp) is recognized by Verilator and suppresses warnings; if using other lint tools, either teach it to the tool to ignore signals with "unused" in the name, or put the appropriate lint_off around the wire. Having unused signals in one place makes it easy to find what is unused, and reduces the number of lint_off pragmas, reducing bugs. =item USERINFO, USERWARN, USERERROR, USERFATAL A SystemVerilog elaboration-time assertion print was executed. =item VARHIDDEN Warns that a task, function, or begin/end block is declaring a variable by the same name as a variable in the upper level module or begin/end block (thus hiding the upper variable from being able to be used.) Rename the variable to avoid confusion when reading the code. Disabled by default as this is a code style warning; it will simulate correctly. =item WIDTH Warns that based on width rules of Verilog, two operands have different widths. Verilator generally can intuit the common usages of widths, and you shouldn't need to disable this message like you do with most lint programs. Generally other than simple mistakes, you have two solutions: If it's a constant 0 that's 32 bits or less, simply leave it unwidthed. Verilator considers zero to be any width needed. Concatenate leading zeros when doing arithmetic. In the statement wire [5:0] plus_one = from[5:0] + 6'd1 + carry[0]; The best fix, which clarifies intent and will also make all tools happy is: wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0, carry[0]}; Ignoring this warning will only suppress the lint check, it will simulate correctly. =item WIDTHCONCAT Warns that based on width rules of Verilog, a concatenate or replication has an indeterminate width. In most cases this violates the Verilog rule that widths inside concatenates and replicates must be sized, and should be fixed in the code. wire [63:0] concat = {1, 2}; An example where this is technically legal (though still bad form) is: parameter PAR = 1; wire [63:0] concat = {PAR, PAR}; The correct fix is to either size the 1 ("32'h1"), or add the width to the parameter definition ("parameter [31:0]"), or add the width to the parameter usage ("{PAR[31:0],PAR[31:0]}". =back The following describes the less obvious errors: =over 4 =item Internal Error This error should never occur first, though may occur if earlier warnings or error messages have corrupted the program. If there are no other warnings or errors, submit a bug report. =item Unsupported: .... This error indicates that you are using a Verilog language construct that is not yet supported in Verilator. See the Limitations chapter. =back =head1 DEPRECATIONS The following deprecated items are scheduled for future removal: =over 4 =item Pre-C++11 compiler support Verilator supports pre-C++11 compilers for non-threaded models when configured with --enable-prec11/--enable-prec11-final. This flag will be removed and C++11 compilers will be required for both compiling Verilator and compiling Verilated models no sooner than September 2020. =item SystemC 2.2 and earlier support Support for SystemC versions 2.2 and earlier including the related sc_clock variable attribute will be removed no sooner than September 2020. The supported versions will be SystemC 2.3.0 (SYSTEMC_VERSION 20111121) and later (presently 2.3.0, 2.3.1, 2.3.2, 2.3.3). =item Configuration File -msg The -msg argument to lint_off has been replaced with -rule. -msg is planned for removal no sooner than January 2021. =item XML locations The XML C attribute has been replaced with C. C is planned for removal no sooner than January 2021. =back =head1 FAQ/FREQUENTLY ASKED QUESTIONS =over 4 =item Can I contribute? Please contribute! Just submit a pull request, or raise an issue to discuss if looking for something to help on. For more information see our contributor agreement. =item How widely is Verilator used? Verilator is used by many of the largest silicon design companies, and all the way down to college projects. Verilator is one of the "big 4" simulators, meaning one of the 4 main SystemVerilog simulators available, namely the commercial products Synopsys VCS (tm), Mentor Questa/ModelSim (tm), Cadence Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. The three commercial offerings are often collectively called the "big 3" simulators. =item Does Verilator run under Windows? Yes, using Cygwin. Verilated output also compiles under Microsoft Visual C++, but this is not tested every release. =item Can you provide binaries? You can install Verilator via the system package manager (apt, yum, etc.) on many Linux distributions, including Debian, Ubuntu, SuSE, Fedora, and others. These packages are provided by the Linux distributions and generally will lag the version of the mainline Verilator repository. If no binary package is available for your distribution, how about you set one up? Please contact the authors for assistance. =item How can it be faster than (name-a-big-3-closed-source-simulator)? Generally, the implied part of the question is "... with all of the manpower they can put into developing it." Most simulators have to be compliant with the complete IEEE 1364 (Verilog) and IEEE 1800 (SystemVerilog) standards, meaning they have to be event driven. This prevents them from being able to reorder blocks and make netlist-style optimizations, which are where most of the gains come from. You should not be scared by non-compliance. Your synthesis tool isn't compliant with the whole standard to start with, so your simulator need not be either. Verilator is closer to the synthesis interpretation, so this is a good thing for getting working silicon. =item Will Verilator output remain under my own license? Yes, it's just like using GCC on your programs; this is why Verilator uses the "GNU *Lesser* Public License Version 3" instead of the more typical "GNU Public License". See the licenses for details, but in brief, if you change Verilator itself or the header files Verilator includes, you must make the source code available under the GNU Lesser Public License. However, Verilator output (the Verilated code) only "include"s the licensed files, and so you are NOT required to release any output from Verilator. You also have the option of using the Perl Artistic License, which again does not require you to release your Verilog or generated code, and also allows you to modify Verilator for internal use without distributing the modified version. But please contribute back to the community! One limit is that you cannot under either license release a commercial Verilog simulation product incorporating Verilator without making the source code available. As is standard with Open Source, contributions back to Verilator will be placed under the Verilator copyright and LGPL/Artistic license. Small test cases will be released into the public domain so they can be used anywhere, and large tests under the LGPL/Artistic, unless requested otherwise. =item Why is running Verilator (to create a model) so slow? Verilator needs more memory than the resulting simulator will require, as Verilator internally creates all of the state of the resulting generated simulator in order to optimize it. If it takes more than a few minutes or so (and you're not using --debug since debug mode is disk bound), see if your machine is paging; most likely you need to run it on a machine with more memory. Very large designs are known to have topped 16GB resident set size. =item How do I generate waveforms (traces) in C++? See the next question for tracing in SystemC mode. A. Add the --trace switch to Verilator, and in your top level C code, call Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to enable traces, same as with any Verilog simulator. See C. B. Or, for finer-grained control, or C++ files with multiple Verilated modules you may also create the trace purely from C++. Create a VerilatedVcdC object, and in your main loop call "trace_object->dump(time)" every time step, and finally call "trace_object->close()". You also need to compile verilated_vcd_c.cpp and add it to your link, preferably by adding the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule. This is done for you if using the Verilator --exe flag. Note you can also call ->trace on multiple Verilated objects with the same trace file if you want all data to land in the same output file. #include "verilated_vcd_c.h" ... int main(int argc, char** argv, char** env) { ... Verilated::traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); // Trace 99 levels of hierarchy tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); ... while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { main_time += #; tfp->dump(main_time); } tfp->close(); } =item How do I generate waveforms (traces) in SystemC? A. Add the --trace switch to Verilator, and in your top level sc_main, call Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to enable traces, same as with any Verilog simulator, see the non-SystemC example in C. This will trace only the module containing the $dumpvar. B. Or, you may create a trace purely from SystemC, which may trace all Verilated designs in the SystemC model. Create a VerilatedVcdSc object as you would create a normal SystemC trace file. For an example, see the call to VerilatedVcdSc in the examples/make_tracing_sc/sc_main.cpp file of the distribution, and below. Alternatively you may use the C++ trace mechanism described in the previous question, note the timescale and timeprecision will be inherited from your SystemC settings. You also need to compile verilated_vcd_sc.cpp and verilated_vcd_c.cpp and add them to your link, preferably by adding the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule. This is done for you if using the Verilator --exe flag. Note you can also call ->trace on multiple Verilated objects with the same trace file if you want all data to land in the same output file. When using SystemC 2.3, the SystemC library must have been built with the experimental simulation phase callback based tracing disabled. This is disabled by default when building SystemC with its configure based build system, but when building SystemC with CMake, you must pass -DENABLE_PHASE_CALLBACKS_TRACING=OFF to disable this feature. #include "verilated_vcd_sc.h" ... int main(int argc, char** argv, char** env) { ... Verilated::traceEverOn(true); VerilatedVcdSc* tfp = new VerilatedVcdSc; topp->trace(tfp, 99); // Trace 99 levels of hierarchy tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); ... sc_start(1); ... tfp->close(); } =item How do I generate FST waveforms (traces) in C++? FST is a trace file format developed by GTKWave. Verilator provides basic FST support. To dump traces in FST format, add the --trace-fst switch to Verilator and either A. use $dumpfile/$dumpvars in Verilog as described in the VCD example above, or B. in C++ change the include described in the VCD example above: #include "verilated_fst_c.h" VerilatedFstC* tfp = new VerilatedFstC; Note that currently supporting both FST and VCD in a single simulation is impossible, but such requirement should be rare. You can however ifdef around the trace format in your C++ main loop, and select VCD or FST at build time, should you require. =item How do I generate FST waveforms (aka dumps or traces) in SystemC? The FST library from GTKWave does not currently support SystemC; use VCD format instead. =item How do I view waveforms (aka dumps or traces)? Verilator creates standard VCD (Value Change Dump) and FST files. VCD files are viewable with the open source GTKWave (recommended) or Dinotrace (legacy) programs, or any of the many closed-source offerings; FST is supported only by GTKWave. =item How do I reduce the size of large waveform (trace) files? First, instead of calling VerilatedVcdC->open at the beginning of time, delay calling it until the time stamp where you want tracing to begin. Likewise you can also call VerilatedVcdC->open before the end of time (perhaps a short period after you detect a verification error). Next, add /*verilator tracing_off*/ to any very low level modules you never want to trace (such as perhaps library cells). Finally, use the --trace-depth option to limit the depth of tracing, for example --trace-depth 1 to see only the top level signals. Also be sure you write your trace files to a local solid-state drive, instead of to a network drive. Network drives are generally far slower. You can also consider using FST tracing instead of VCD. FST dumps are a fraction of the size of the equivalent VCD. FST tracing can be slower than VCD tracing, but it might be the only option if the VCD file size is prohibitively large. =item How do I do coverage analysis? Verilator supports both block (line) coverage and user inserted functional coverage. First, run verilator with the --coverage option. If you are using your own makefile, compile the model with the GCC flag -DVM_COVERAGE (if using the makefile provided by Verilator, it will do this for you). At the end of your test, call VerilatedCov::write passing the name of the coverage data file (typically "logs/coverage.dat"). Run each of your tests in different directories. Each test will create a logs/coverage.dat file. After running all of your tests, execute the verilator_coverage tool. The verilator_coverage tool reads the logs/coverage.dat file(s), and creates an annotated source code listing showing code coverage details. For an example, after running 'make test' in the Verilator distribution, see the examples/make_tracing_c/logs directory. Grep for lines starting with '%' to see what lines Verilator believes need more coverage. Info files can be written by verilator_coverage for import to C. This enables use of C for HTML reports and importing reports to sites such as L. =item Where is the translate_off command? (How do I ignore a construct?) Translate on/off pragmas are generally a bad idea, as it's easy to have mismatched pairs, and you can't see what another tool sees by just preprocessing the code. Instead, use the preprocessor; Verilator defines the "VERILATOR" define for you, so just wrap the code in an ifndef region: `ifndef VERILATOR Something_Verilator_Dislikes; `endif Most synthesis tools similarly define SYNTHESIS for you. =item Why do I get "unexpected C" or "unexpected C" errors? The words C, C, C, C, and others are reserved keywords in SystemVerilog. Older Verilog code might use these as identifiers. You should change your code to not use them to ensure it works with newer tools. Alternatively, surround them by the Verilog 2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code. `begin_keywords "1364-2001" integer bit; initial bit = 1; `end_keywords If you want the whole design to be parsed as Verilog 2001, please see the C<--default-language> option. =item How do I prevent my assertions from firing during reset? Call Verilated::assertOn(false) before you first call the model, then turn it back on after reset. It defaults to true. When false, all assertions controlled by --assert are disabled. =item Why do I get "undefined reference to `sc_time_stamp()'"? In C++ (non SystemC) code you need to define this function so that the simulator knows the current time. See the "CONNECTING TO C++" examples. =item Why do I get "undefined reference to `VL_RAND_RESET_I' or `Verilated::...'"? You need to link your compiled Verilated code against the verilated.cpp file found in the include directory of the Verilator kit. This is one target in the $(VK_GLOBAL_OBJS) make variable, which should be part of your Makefile's link rule. If you use --exe, this is done for you. =item Is the PLI supported? Only somewhat. More specifically, the common PLI-ish calls $display, $finish, $stop, $time, $write are converted to C++ equivalents. You can also use the "import DPI" SystemVerilog feature to call C code (see the chapter above). There is also limited VPI access to public signals. If you want something more complex, since Verilator emits standard C++ code, you can simply write your own C++ routines that can access and modify signal values without needing any PLI interface code, and call it with $c("{any_c++_statement}"). =item How do I make a Verilog module that contain a C++ object? You need to add the object to the structure that Verilator creates, then use $c to call a method inside your object. The test_regress/t/t_extend_class files show an example of how to do this. =item How do I get faster build times? When running make pass the make variable VM_PARALLEL_BUILDS=1 so that builds occur in parallel. Note this is now set by default if an output file was large enough to be split due to the --output-split option. Verilator emits any infrequently executed "cold" routines into separate __Slow.cpp files. This can accelerate compilation as optimization can be disabled on these routines. See the OPT_FAST and OPT_SLOW make variables and the BENCHMARKING & OPTIMIZATION section of the manual. Use a recent compiler. Newer compilers tend to be faster. Compile in parallel on many machines and use caching; see the web for the ccache, distcc and icecream packages. ccache will skip GCC runs between identical source builds, even across different users. If ccache was installed when Verilator was built it is used, or see OBJCACHE environment variable to override this. Also see the --output-split option. To reduce the compile time of classes that use a Verilated module (e.g. a top CPP file) you may wish to add /*verilator no_inline_module*/ to your top level module. This will decrease the amount of code in the model's Verilated class, improving compile times of any instantiating top level C++ code, at a relatively small cost of execution performance. =item Why do so many files need to recompile when I add a signal? Adding a new signal requires the symbol table to be recompiled. Verilator uses one large symbol table, as that results in 2-3 less assembly instructions for each signal access. This makes the execution time 10-15% faster, but can result in more compilations when something changes. =item How do I access Verilog functions/tasks in C? Use the SystemVerilog Direct Programming Interface. You write a Verilog function or task with input/outputs that match what you want to call in with C. Then mark that function as a DPI export function. See the DPI chapter in the IEEE Standard. =item How do I access C++ functions/tasks in Verilog? Use the SystemVerilog Direct Programming Interface. You write a Verilog function or task with input/outputs that match what you want to call in with C. Then mark that function as a DPI import function. See the DPI chapter in the IEEE Standard. =item How do I access signals in C? The best thing to do is to make a SystemVerilog "export DPI" task or function that accesses that signal, as described in the DPI chapter in the manual and DPI tutorials on the web. This will allow Verilator to better optimize the model and should be portable across simulators. If you really want raw access to the signals, declare the signals you will be accessing with a /*verilator public*/ comment before the closing semicolon. Then scope into the C++ class to read the value of the signal, as you would any other member variable. Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t), 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or 64-bit unsigned long longs (uint64_t) that fits the width of the signal. Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for 1 to 64 bits, and the compiler will properly up-convert smaller entities. Note even signed ports are declared as unsigned; you must sign extend yourself to the appropriate signal width. Signals wider than 64 bits are stored as an array of 32-bit uint32_t's. Thus to read bits 31:0, access signal[0], and for bits 63:32, access signal[1]. Unused bits (for example bit numbers 65-96 of a 65-bit vector) will always be zero. If you change the value you must make sure to pack zeros in the unused bits or core-dumps may result, because Verilator strips array bound checks where it believes them to be unnecessary to improve performance. In the SYSTEMC example above, if you had in our.v: input clk /*verilator public*/; // Note the placement of the semicolon above From the sc_main.cpp file, you'd then: #include "Vour.h" #include "Vour_our.h" cout << "clock is " << top->our->clk << endl; In this example, clk is a bool you can read or set as any other variable. The value of normal signals may be set, though clocks shouldn't be changed by your code or you'll get strange results. =item Should a module be in Verilog or SystemC? Sometimes there is a block that just interconnects cells, and have a choice as to if you write it in Verilog or SystemC. Everything else being equal, best performance is when Verilator sees all of the design. So, look at the hierarchy of your design, labeling cells as to if they are SystemC or Verilog. Then: A module with only SystemC cells below must be SystemC. A module with a mix of Verilog and SystemC cells below must be SystemC. (As Verilator cannot connect to lower-level SystemC cells.) A module with only Verilog cells below can be either, but for best performance should be Verilog. (The exception is if you have a design that is instantiated many times; in this case Verilating one of the lower modules and instantiating that Verilated cells multiple times into a SystemC module *may* be faster.) =back =head1 BUGS First, check the L section. Next, try the --debug switch. This will enable additional internal assertions, and may help identify the problem. Finally, reduce your code to the smallest possible routine that exhibits the bug. Even better, create a test in the test_regress/t directory, as follows: cd test_regress cp -p t/t_EXAMPLE.pl t/t_BUG.pl cp -p t/t_EXAMPLE.v t/t_BUG.v There are many hints on how to write a good test in the driver.pl documentation which can be seen by running: cd $VERILATOR_ROOT # Need the original distribution kit test_regress/driver.pl --help Edit t/t_BUG.pl to suit your example; you can do anything you want in the Verilog code there; just make sure it retains the single clk input and no outputs. Now, the following should fail: cd $VERILATOR_ROOT # Need the original distribution kit cd test_regress t/t_BUG.pl # Run on Verilator t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator t/t_BUG.pl --vcs # Run on VCS simulator t/t_BUG.pl --nc|--iv|--ghdl # Likewise on other simulators The test driver accepts a number of options, many of which mirror the main Verilator option. For example the previous test could have been run with debugging enabled. The full set of test options can be seen by running driver.pl --help as shown above. Finally, report the bug using the bug tracker at L. The bug will become publicly visible; if this is unacceptable, mail the bug report to C. =head1 HISTORY Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at Digital Equipment Corporation. The Verilog code that was converted to C was then merged with a C based CPU model of the Alpha processor and simulated in a C based environment called CCLI. In 1995 Verilator started being used also for Multimedia and Network Processor development inside Digital. Duane Galbi took over active development of Verilator, and added several performance enhancements. CCLI was still being used as the shell. In 1998, through the efforts of existing DECies, mainly Duane Galbi, Digital graciously agreed to release the source code. (Subject to the code not being resold, which is compatible with the GNU Public License.) In 2001, Wilson Snyder took the kit, and added a SystemC mode, and called it Verilator2. This was the first packaged public release. In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from scratch in C++. This added many optimizations, yielding about a 2-5x performance gain. In 2009, major SystemVerilog and DPI language support was added. In 2018, Verilator 4.000 was released with multithreaded support. Currently, various language features and performance enhancements are added as the need arises. Verilator is now about 3x faster than in 2002, and is faster than most (if not every) other simulator. =head1 AUTHORS When possible, please instead report bugs to L. Wilson Snyder Major concepts by Paul Wasson, Duane Galbi, John Coiner and Jie Xu. =head1 CONTRIBUTORS Many people have provided ideas and other assistance with Verilator. Verilator is receiving major development support from the CHIPS Alliance. Previous major corporate sponsors of Verilator, by providing significant contributions of time or funds included include Atmel Corporation, Cavium Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc., and SiCortex Inc. The people who have contributed major functionality are Byron Bradley, Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, and Wilson Snyder. Major testers included Jeff Dutton, Jonathon Donaldson, Ralf Karge, David Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van Cauwenberghe, Gene Weber, and Clifford Wolf. Some of the people who have provided ideas, and feedback for Verilator include: David Addison, Tariq B. Ahmad, Nikana Anastasiadis, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew Barr, Geoff Barrett, Julius Baxter, Jeremy Bennett, Michael Berman, Victor Besyakov, Moinak Bhattacharyya, David Binderman, Piotr Binkowski, Johan Bjork, David Black, Tymoteusz Blazejczyk, Daniel Bone, Gregg Bouchard, Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Maarten De Braekeleer, Charlie Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, Tony Bybell, Ted Campbell, Chris Candler, Lauren Carlson, Donal Casey, Sebastien Van Cauwenberghe, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean Cross, George Cuan, Joe DErrico, Lukasz Dalek, Laurens van Dam, Gunter Dannoritzer, Ashutosh Das, Bernard Deadman, John Demme, Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Leendert van Doorn, Sebastian Dressler, Alex Duller, Jeff Dutton, Tomas Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein, Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner, Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Amir Gonnen, Chitlesh Goorah, Kai Gossner, Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto, Thomas Hawkins, Mitch Hayenga, Robert Henry, Stephen Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki Honda, Alex Hornung, David Horton, Peter Horvath, Jae Hossell, Alan Hunter, James Hutchinson, Jamie Iles, Ben Jackson, Shareef Jalloq, Krzysztof Jankowski, HyungKi Jeong, Iztok Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Ralf Karge, Dan Katz, Sol Katzman, Ian Kennedy, Jonathan Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot Koch, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, Will Korteland, Wojciech Koszek, Varun Koyyalagunta, David Kravitz, Roland Kruse, Sergey Kvachonok, Charles Eric LaForest, Ed Lander, Steve Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor Lesik, John Li, Eivind Liland, Yu Sheng Lin, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan Lussier, Fred Ma, Duraid Madina, Affe Mao, Julien Margetts, Mark Marshall, Alfonso Martinez, Yves Mathieu, Patrick Maupin, Jason McMullan, Elliot Mednick, Wim Michiels, Miodrag Milanovic, Wai Sum Mong, Peter Monsson, Sean Moore, Dennis Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris Nalbantis, Peter Nelson, Bob Newgard, Cong Van Nguyen, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Aleksander Osman, James Pallister, Vassilis Papaefstathiou, Brad Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter, Niranjan Prabhu, Usha Priyadharshini, Mark Jackson Pulver, Prateek Puri, Marshal Qiao, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Odd Magne Reitan, Frederic Requin, Frederick Requin, Dustin Richmond, Alberto Del Rio, Eric Rippey, Oleg Rodionov, Ludwig Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Jan Egil Ruud, Denis Rystsov, John Sanguinetti, Galen Seitz, Salman Sheikh, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Anderson Ignacio Da Silva, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson, Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki, Howard Su, Emerson Suguimoto, Gene Sullivan, Qingyao Sun, Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede, Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, Viktor Tomov, Steve Tong, Michael Tresidder, Neil Turton, Srini Vemuri, Yuri Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene Weber, David Welch, Thomas J Whatson, Marco Widmer, Leon Wildman, Daniel Wilkerson, Gerald Williams, Trevor Williams, Jan Van Winkel, Jeff Winston, Joshua Wise, Clifford Wolf, Tobias Wolfel, Johan Wouters, Junyi Xi, Ding Xiaoliang, Jie Xu, Mandy Xu, Takatsukasa Y, Luke Yang, and Amir Yazdanbakhsh. Thanks to them, and all those we've missed including above, or wished to remain anonymous. =head1 DISTRIBUTION The latest version is available from L. Copyright 2003-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. All Verilog and C++/SystemC code quoted within this documentation file are released as Creative Commons Public Domain (CC0). Many example files and test files are likewise released under CC0 into effectively the Public Domain as described in the files themselves. =head1 SEE ALSO L, L, L, L, L which is the source for this document, and docs/internals.adoc in the distribution. =cut ###################################################################### # Local Variables: # fill-column: 75 # End: verilator-4.038/bin/verilator_gantt0000775000177100017500000004355213702133367017434 0ustar wsnyderwsnyder#!/usr/bin/env perl # See copyright, etc in below POD section. ###################################################################### use warnings; use strict; use Getopt::Long; use IO::File; use Pod::Usage; use vars qw($Debug); $Debug = 0; my $Opt_File; my $Opt_Time_Per_Char = 0; # rdtsc ticks per char in gantt chart, 0=auto my $opt_vcd = "profile_threads.vcd"; our %Threads; our %Mtasks; our %Global; autoflush STDOUT 1; autoflush STDERR 1; Getopt::Long::config("no_auto_abbrev"); if (! GetOptions( "help" => \&usage, "scale=i" => \$Opt_Time_Per_Char, "debug" => sub { $Debug = 1; }, "vcd=s" => \$opt_vcd, "no-vcd!" => sub { $opt_vcd = undef; }, "<>" => \¶meter, )) { die "%Error: Bad usage, try 'verilator_gantt --help'\n"; } $Opt_File = "profile_threads.dat" if !defined $Opt_File; process($Opt_File); write_vcd($opt_vcd) if defined $opt_vcd; exit(0); ####################################################################### sub usage { pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT); exit(1); # Unreachable } sub parameter { my $param = shift; if (!defined $Opt_File) { $Opt_File = $param; } else { die "%Error: Unknown parameter: $param\n"; } } ####################################################################### sub process { my $filename = shift; read_data($filename); report(); } ####################################################################### sub read_data { my $filename = shift; %Global = (rdtsc_cycle_time => 0); my $fh = IO::File->new ($filename) or die "%Error: $! $filename,"; while (my $line = $fh->getline) { if ($line =~ m/VLPROF mtask\s(\d+)\sstart\s(\d+)\send\s(\d+)\selapsed\s(\d+)\spredict_time\s(\d+)\scpu\s(\d+)\son thread (\d+)/) { my $mtask = $1; my $start = $2; my $end = $3; my $elapsed_time = $4; my $predict_time = $5; my $cpu = $6; my $thread = $7; $Threads{$thread}{$start}{mtask} = $mtask; $Threads{$thread}{$start}{end} = $end; $Threads{$thread}{$start}{cpu} = $cpu; if (!exists $Mtasks{$mtask}{elapsed}) { $Mtasks{$mtask}{elapsed} = 0; } $Mtasks{$mtask}{elapsed} += $elapsed_time; $Mtasks{$mtask}{predict} = $predict_time; $Mtasks{$mtask}{end} = max($Mtasks{$mtask}{end}, $end); } elsif ($line =~ /^VLPROFTHREAD/) {} elsif ($line =~ m/VLPROF arg\s+(\S+)\+([0-9.])\s*$/ || $line =~ m/VLPROF arg\s+(\S+)\s+([0-9.])\s*$/) { $Global{args}{$1} = $2; } elsif ($line =~ m/VLPROF stat\s+(\S+)\s+([0-9.]+)/) { $Global{stats}{$1} = $2; } elsif ($line =~ /^#/) {} elsif ($Debug) { chomp $line; print "Unk: $line\n"; } # TODO -- this is parsing text printed by a client. # Really, verilator proper should generate this # if it's useful... if ($line =~ m/rdtsc time = (\d+) ticks/) { $Global{rdtsc_cycle_time} = $1; } } } sub report { print "Verilator Gantt report\n"; print "\nArgument settings:\n"; foreach my $arg (sort keys %{$Global{args}}) { my $plus = ($arg =~ /^\+/) ? "+" : " "; printf " %s%s%d\n", $arg, $plus, $Global{args}{$arg}; } my $nthreads = scalar keys %Threads; $Global{cpus} = {}; foreach my $thread (keys %Threads) { # Make potentially multiple characters per column foreach my $start (keys %{$Threads{$thread}}) { my $cpu = $Threads{$thread}{$start}{cpu}; my $elapsed = $Threads{$thread}{$start}{end} - $start; $Global{cpus}{$cpu}{cpu_time} += $elapsed; } } my $mt_mtask_time = 0; my $long_mtask_time = 0; my $last_end = 0; foreach my $mtask (keys %Mtasks) { $mt_mtask_time += $Mtasks{$mtask}{elapsed}; $last_end = max($last_end, $Mtasks{$mtask}{end}); $long_mtask_time = max($long_mtask_time, $Mtasks{$mtask}{elapsed}); } $Global{last_end} = $last_end; report_graph(); # If we know cycle time in the same (rdtsc) units, # this will give us an actual utilization number, # (how effectively we keep the cores busy.) # # It also gives us a number we can compare against # serial mode, to estimate the overhead of data sharing, # which will show up in the total elapsed time. (Overhead # of synchronization and scheduling should not.) print "\nAnalysis:\n"; printf " Total threads = %d\n", $nthreads; printf " Total mtasks = %d\n", scalar(keys %Mtasks); printf " Total cpus used = %d\n", scalar(keys %{$Global{cpus}}); printf " Total yields = %d\n", $Global{stats}{yields}; printf " Total eval time = %d rdtsc ticks\n", $Global{last_end}; printf " Longest mtask time = %d rdtsc ticks\n", $long_mtask_time; printf " All-thread mtask time = %d rdtsc ticks\n", $mt_mtask_time; my $long_efficiency = $long_mtask_time/($Global{last_end}); printf " Longest-thread efficiency = %0.1f%%\n", $long_efficiency*100; my $mt_efficiency = $mt_mtask_time/($Global{last_end}*$nthreads); printf " All-thread efficiency = %0.1f%%\n", $mt_efficiency*100; printf " All-thread speedup = %0.1f\n", $mt_efficiency*$nthreads; if ($Global{rdtsc_cycle_time} > 0) { my $ut = $mt_mtask_time / $Global{rdtsc_cycle_time}; print "tot_mtask_cpu=$mt_mtask_time cyc=$Global{rdtsc_cycle_time} ut=$ut\n"; } my @p2e_ratios; my $min_p2e = 1000000; my $min_mtask; my $max_p2e = -1000000; my $max_mtask; foreach my $mtask (sort keys %Mtasks) { if ($Mtasks{$mtask}{elapsed} > 0) { if ($Mtasks{$mtask}{predict} == 0) { $Mtasks{$mtask}{predict} = 1; # don't log(0) below } my $p2e_ratio = log( $Mtasks{$mtask}{predict} / $Mtasks{$mtask}{elapsed} ); #print "log(p2e $mtask) = $p2e_ratio (predict $Mtasks{$mtask}{predict}, elapsed $Mtasks{$mtask}{elapsed})\n"; push @p2e_ratios, $p2e_ratio; if ($p2e_ratio > $max_p2e) { $max_p2e = $p2e_ratio; $max_mtask = $mtask; } if ($p2e_ratio < $min_p2e) { $min_p2e = $p2e_ratio; $min_mtask = $mtask; } } } print "\nStatistics:\n"; print " min log(p2e) = $min_p2e from mtask $min_mtask (predict $Mtasks{$min_mtask}{predict}, elapsed $Mtasks{$min_mtask}{elapsed})\n"; print " max log(p2e) = $max_p2e from mtask $max_mtask (predict $Mtasks{$max_mtask}{predict}, elapsed $Mtasks{$max_mtask}{elapsed})\n"; my $stddev = stddev(\@p2e_ratios); my $mean = mean(\@p2e_ratios); print " mean = " . ($mean) . "\n"; print " stddev = " . ($stddev) . "\n"; print " e ^ stddev = " . exp($stddev). "\n"; print "\n"; } sub report_graph { my $time_per = $Opt_Time_Per_Char; if ($time_per == 0) { $time_per = ($Global{last_end} / 40); # Start with 40 columns while ($time_per > 10) { my ($graph, $conflicts) = _make_graph($time_per); last if !$conflicts; $time_per = int($time_per/2); } # One more step so we can fit more labels $time_per = int($time_per/2); } my ($graph, $conflicts) = _make_graph($time_per); print "\nThread gantt graph:\n"; print " Legend: One character width = $time_per rdtsc ticks\n"; print " Legend: '&' = multiple mtasks in this period (character width)\n"; my $scale = " <-".$Global{last_end}." rdtsc total"; for (my $col = length($scale); # -2 for '->' below $col < ($Global{last_end}/$time_per); ++$col) { $scale .= "-"; } print " $scale->\n"; foreach my $thread (sort keys %{$graph}) { print " t: "; _print_graph_line($graph->{$thread}, ''); } } sub _make_graph { my $time_per = shift; my $graph = {}; # {thread}{column}{char=>'x' or chars=>#} my $conflicts = 0; foreach my $thread (keys %Threads) { # Make potentially multiple characters per column foreach my $start (sort {$a <=> $b} keys %{$Threads{$thread}}) { my $end = $Threads{$thread}{$start}{end}; my $mtask = $Threads{$thread}{$start}{mtask}; my $cpu = $Threads{$thread}{$start}{cpu}; my $startcol = _time_col($time_per, $start); my $endcol = _time_col($time_per, $end); my $label = "["; $label .= "$cpu"; # Maybe make optional in future my $width = $endcol - $startcol + 1; while (length($label) < ($width-1)) { # -1 for ']' $label .= "-"; } $label .= "]"; $graph->{$thread}[$startcol]{char} .= $label; } if ($Debug) { print "# Multicol: "; _print_graph_line($graph->{$thread}, '|'); } # Expand line to one char per column for (my $col = 0; $col <= $#{$graph->{$thread}}; ++$col) { if (my $chars = $graph->{$thread}[$col]{char}) { my $ok = 1; for (my $coladd = 1; $coladd{$thread}[$col + $coladd]{char}) { $ok = 0; last; } } if (!$ok) { if ($chars =~ /\[.*\[/) { # Two begins or more $conflicts++; $graph->{$thread}[$col]{char} = "&"; } else { $graph->{$thread}[$col]{char} = "["; } for (my $coladd = 1; $coladd{$thread}[$col + $coladd]{char}) { last; } else { $graph->{$thread}[$col + $coladd]{char} = 'x'; } } } else { my $coladd = 0; foreach my $char (split //, $chars) { $graph->{$thread}[$col+$coladd]{char} = $char; ++$coladd; } } } } if ($Debug) { print "# Singlcol: "; _print_graph_line($graph->{$thread}, '|'); } } print "# Conflicts $conflicts\n" if $Debug; return ($graph, $conflicts); } sub _print_graph_line { my $graph_thread = shift; my $sep = shift; for (my $col = 0; $col <= $#{$graph_thread}; ++$col) { my $c = $graph_thread->[$col]{char}; $c=' ' if !defined $c; print $c, $sep; } print "\n"; } sub _time_col { my $time_per = shift; my $time = shift; return int($time/$time_per); } ####################################################################### sub write_vcd { my $filename = shift; print "Writing $filename\n"; my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,"; my $vcd = {values => {}, # {