verilog-mode-20161124.fd230e6/ 0000775 0000000 0000000 00000000000 13022141775 0015417 5 ustar 00root root 0000000 0000000 verilog-mode-20161124.fd230e6/.gitignore 0000664 0000000 0000000 00000000344 13022141775 0017410 0 ustar 00root root 0000000 0000000 .timestamps
ASSIGNMENT.doc
ChangeLog
ChangeLog.txt
e
emacs-version.h
gnu22
gnuhead
gnutrunk
mmencoded_verilog-mode
skip_for_xemacs
verilog-mode-gnu-want.el
verilog-mode-tognu.el
verilog-mode.elc
verilog.info
x
*.elc
*.old
*.new
verilog-mode-20161124.fd230e6/0test.el 0000664 0000000 0000000 00000016320 13022141775 0017002 0 ustar 00root root 0000000 0000000 ;; DESCRIPTION: Run verilog-mode tests, as part of "make test"
;;
;; Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
;; is free software; you can redistribute it and/or modify it under the
;; terms of either the GNU Lesser General Public License or the Perl
;; Artistic License.
;;
;; VERILOG_MODE_DEBUG=1 # Enable verilog-debug
;; VERILOG_MODE_NO_INDENTS=1 # Disable indent checks
;; VERILOG_MODE_TEST_FILE=filename.v # Run only specified test
;; VERILOG_MODE_START_FILE=filename.v # Start at specified test
;; VERILOG_MODE_THREAD=#of# # Multithreaded testing
;; VERILOG_MODE_PROFILE=1 # Profile - see batch_prof.el
;; HARNESS_UPDATE_GOLDEN=1 # Update golden reference files
(defvar diff-flags "-u")
(defvar vl-threading (and (not (getenv "VERILOG_MODE_TEST_FILE"))
(getenv "VERILOG_MODE_THREAD")))
(defun global-replace-regexp (from to)
(goto-char (point-min))
(while (re-search-forward from nil t)
(replace-match to nil nil)))
(defun verilog-test-file (file temp-file)
(save-excursion
(message (concat file ": finding..."))
(find-file (concat "tests/" file))
(verilog-mode)
(message (concat file ": deleting indent..."))
(global-replace-regexp "[ \t]+$" "")
(message (concat file ": deleting autos..."))
(verilog-delete-auto)
(cond
((string-match "^inject_" file)
(message (concat file ": testing inject-auto..."))
(verilog-inject-auto))
(t
(message (concat file ": testing auto..."))
(verilog-auto)))
(message (concat file ": auto OK..."))
(when (string-match "^label_" file)
(message (concat file ": testing auto labeling of begin/end..."))
(verilog-label-be))
(unless (getenv "VERILOG_MODE_NO_INDENTS")
(verilog-test-indent-buffer file)
(untabify (point-min) (point-max))
)
(write-file (concat "../" temp-file))
(kill-buffer nil))
;;
(vl-diff-file (concat "tests_ok/" file) temp-file))
(defun verilog-test-indent-buffer (file )
(interactive)
(message (concat file ": testing indent..."))
(save-excursion
(goto-char (point-min))
(let* ((ln 0))
(while (not (eobp))
;;(message (format "%d" ln))
;;(message (format "%s : %d - indent" file ln))
(electric-verilog-tab)
;;(message (format "%s : %d - pretty-expr" file ln))
(verilog-pretty-expr t )
;;(message (format "%s : %d - pretty-declaration" file ln))
(verilog-pretty-declarations t)
(forward-line 1)
(setq ln (1+ ln))
)
(message (format "Indented %d lines" ln))
))
(message (concat file ": indents OK...")))
(defun vl-diff-file (golden-file temp-file)
(message (concat golden-file ": running diff of " golden-file " and " temp-file ))
(with-temp-buffer
(let* ((status
(call-process "diff" nil t t diff-flags "--label" "GOLDEN_REFERENCE" golden-file "--label" "CURRENT_BEHAVIOR" temp-file )))
(cond ((and (not (equal status 0))
(getenv "HARNESS_UPDATE_GOLDEN"))
(message "***HARNESS_UPDATE_GOLDEN set - updating Golden Reference File")
(call-process "cp" nil t t temp-file golden-file))
((not (equal status 0))
(message (concat "diff -c " golden-file " " temp-file))
(message "***Golden Reference File\n---Generated Test File")
(message "%s" (buffer-string))
(message "To promote current to golden, in shell buffer hit newline anywhere in next line (^P RETURN):")
(message (concat "cp " temp-file " " golden-file "; VERILOG_MODE_START_FILE=" golden-file " " again ))
(error ""))
(t
(message "Verified %s" golden-file))))))
(defun vl-do-on-thread (file-num)
"Return true to process due to multithreading"
(cond (vl-threading
(or (string-match "\\([0-9]+\\)of\\([0-9]+\\)" vl-threading)
(error "VERILOG_MODE_THREAD not in #of# form"))
(let ((th (string-to-number (match-string 1 vl-threading)))
(numth (string-to-number (match-string 2 vl-threading))))
(equal (1+ (mod file-num numth)) th)))
(t t)))
(defun verilog-test ()
(let ((files (directory-files "tests"))
(tests-run 0)
(file-num 0)
file cf temp-file)
(when (getenv "VERILOG_MODE_DEBUG")
(setq verilog-debug t))
(when (getenv "VERILOG_MODE_TEST_FILE")
(setq files (list (getenv "VERILOG_MODE_TEST_FILE")))
(message "**** Only testing files in $VERILOG_MODE_TEST_FILE"))
(when (getenv "VERILOG_MODE_START_FILE")
(let* ((startfiles (list (getenv "VERILOG_MODE_START_FILE")))
(startfile (car startfiles)))
(message (concat "Starting from file " startfile))
(catch 'done
(while files
(setq file (car files))
(if (or (string-equal file startfile)
(string-equal (concat "tests_ok/" file) startfile))
(progn
(message (concat "matched " file))
(throw 'done 0))
(progn
(setq files (cdr files))))))))
(message "emacs-version %s" emacs-version)
(while files
(setq file (car files))
(setq temp-file (concat (if running-on-xemacs "x/t/" "e/t/")
file))
(cond ((equal "." file))
((equal ".." file))
((string-match "#" file)) ;; Backups
((string-match "~$" file))
((string-match "\.f$" file))
((string-match "\.dontrun$" file))
((file-directory-p (concat "tests/" file)))
((progn (setq file-num (1+ file-num))
(not (vl-do-on-thread file-num))))
(t
(message (concat "Considering test " file ))
(if running-on-xemacs
(progn
(setq cf (concat "skip_for_xemacs/" file))
(if (file-exists-p cf ) ;
(message (concat "Skipping testing " file " on Xemacs because file " cf "exists"))
(progn
(verilog-test-file file temp-file)
(setq tests-run (1+ tests-run))
)
))
(progn
(verilog-test-file file temp-file)
(setq tests-run (1+ tests-run))
))
(message (format " %d tests run so far, %d left... %s"
tests-run (length files)
(if vl-threading (concat "Thread " vl-threading) "")))
))
(setq files (cdr files))))
(message "Tests Passed on %s" (emacs-version))
"Tests Passed")
(defun vl-indent-file ()
"Reindent file"
(interactive)
(save-excursion
(goto-char (point-min))
(while (not (eobp))
(electric-verilog-tab)
(end-of-line)
(delete-char (- (skip-chars-backward " \t")))
(forward-line 1)
)
)
(write-file (buffer-file-name))
)
(progn
(save-excursion
(with-temp-buffer
(verilog-mode)))
;; Setup
(require `compile)
(defun ask-user-about-lock() nil) ;; XEmacs - Disable lock conflicts
(setq running-on-xemacs (string-match "XEmacs" emacs-version))
(setq make-backup-files nil)
(setq-default make-backup-files nil)
(setq diff-flags (if (getenv "VERILOG_MODE_NO_INDENTS") "-wBu" "-u"))
;;(setq verilog-auto-lineup 'all)
(setq enable-local-variables t)
(setq enable-local-eval t)
(setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
(setq-default fill-column 100)
(if running-on-xemacs
(setq again "make test_xemacs")
(setq again "make test_emacs"))
(verilog-test)
)
verilog-mode-20161124.fd230e6/LICENSE 0000664 0000000 0000000 00000104513 13022141775 0016430 0 ustar 00root root 0000000 0000000 GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
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Copyright (C)
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under certain conditions; type `show c' for details.
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The GNU General Public License does not permit incorporating your program
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.
verilog-mode-20161124.fd230e6/Makefile 0000664 0000000 0000000 00000013270 13022141775 0017062 0 ustar 00root root 0000000 0000000 # DESCRIPTION: Run verilog-mode tests, as part of "make test"
#
# Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
# is free software; you can redistribute it and/or modify it under the
# terms of either the GNU Lesser General Public License or the Perl
# Artistic License.
#
######################################################################
# Common targets:
# make # Compile source for GNU and Xemacs
# make test # Run self tests
# # See x/verilog-mode.el for version to install
######################################################################
S=/home/mac/development/www.verilog.com/src/
D=$(S)data
F=/home/mac/external_webpage/src/verilog.com/ftp
# the directory where the .elc files will be installed
XEMACS = xemacs
XEMACS_DEST = /usr/local/lib/xemacs/xemacs-packages/lisp/prog-modes/
EMACS = emacs
EMACS_DEST = /usr/share/emacs/site-lisp/
ELC = -batch -q -f batch-byte-compile
MAKECHANGELOG = perl makechangelog
default : e/verilog-mode.elc x/verilog-mode.elc
release : .timestamps
install : .timestamps ChangeLog test $(D)/mmencoded_verilog-mode $(D)/emacs-version.h\
$(S)ChangeLog.txt email $(S)bits/verilog-mode.el local \
# ftp
@echo Installation up to date
.timestamps:
@mkdir -p $@
test: .timestamps/test
.timestamps/test: x/verilog-mode.elc e/verilog-mode.elc mmencoded_verilog-mode verilog.info 0test.el .timestamps
ifeq ($(VERILOG_MODE_TEST_FILE),)
$(MAKE) test_batch test_errors test_emacs test_xemacs
@touch $@
@echo ======= ALL TESTS PASSED
else
$(MAKE) test_emacs test_xemacs
endif
#Usage: $(call test-emacs_sub,label,threading)
define test_emacs_sub
test_emacs:: $(1)
$(1): e/verilog-mode.elc
@echo
@echo == $(1)
@mkdir -p e/t
VERILOG_MODE_THREAD=$(2) time $(EMACS) --batch -q --no-site-file -l e/verilog-mode.elc -l 0test.el
endef
$(eval $(call test_emacs_sub,test_emacs_1,1of5))
ifeq ($(VERILOG_MODE_TEST_FILE),)
$(eval $(call test_emacs_sub,test_emacs_2,2of5))
$(eval $(call test_emacs_sub,test_emacs_3,3of5))
$(eval $(call test_emacs_sub,test_emacs_4,4of5))
$(eval $(call test_emacs_sub,test_emacs_5,5of5))
endif
#Usage: $(call test_xemacs_sub,label,threading)
define test_xemacs_sub
test_xemacs:: $(1)
$(1): x/verilog-mode.elc
@echo
@echo == $(1)
@mkdir -p x/t
VERILOG_MODE_THREAD=$(2) time $(XEMACS) --batch -vanilla -l x/verilog-mode.elc -l 0test.el
endef
$(eval $(call test_xemacs_sub,test_xemacs_1,1of5))
ifeq ($(VERILOG_MODE_TEST_FILE),)
$(eval $(call test_xemacs_sub,test_xemacs_2,2of5))
$(eval $(call test_xemacs_sub,test_xemacs_3,3of5))
$(eval $(call test_xemacs_sub,test_xemacs_4,4of5))
$(eval $(call test_xemacs_sub,test_xemacs_5,5of5))
endif
test_errors:
@echo
@echo == test_errors
-# The multiline errors must be in one read()s output or the comint may not match it
-cat error_msgs.out
test_batch: e/verilog-mode.elc
@echo == test_batch
mkdir -p e/b
time ./batch_test.pl
local: .timestamps/local
.timestamps/local: verilog-mode.el
cp verilog-mode.el $(XEMACS_DEST)verilog-mode.el
rm -f $(XEMACS_DEST)verilog-mode.elc
$(XEMACS) $(ELC) $(XEMACS_DEST)verilog-mode.el
cp verilog-mode.el $(EMACS_DEST)verilog-mode.el
rm -f $(EMACS_DEST)verilog-mode.elc
$(EMACS) $(ELC) $(EMACS_DEST)verilog-mode.el
@touch $@
ftp: .timestamps/ftp
.timestamps/ftp: $(F) mmencoded_verilog-mode verilog-mode.el README
cp mmencoded_verilog-mode $(F)
cp verilog-mode.el $(F)
cp README $(F)/.message
@touch $@
$(F):
mkdir $(F)
ChangeLog.txt mmencoded_verilog-mode emacs-version.h : make_log.pl verilog-mode.el README
ifneq ($(VERILOGMODE_SKIP_MAKELOG),1)
./make_log.pl
endif
ChangeLog : verilog-mode.el makechangelog
$(MAKECHANGELOG) --git verilog-mode.el > $@
email: .timestamps/email
.timestamps/email: mmencoded_verilog-mode
./make_mail.pl
@touch $@
$(D)/mmencoded_verilog-mode : mmencoded_verilog-mode
cp $? $@
$(D)/emacs-version.h : emacs-version.h
cp $? $@
touch $(S)verilog-mode.html
$(S)ChangeLog.txt : ChangeLog.txt
cp $? $@
$(S)bits/verilog-mode.el : verilog-mode.el
cp $? $@
x/verilog-mode.el : verilog-mode.el ./config_rev.pl
rm -rf x
mkdir x
./config_rev.pl . . x/verilog-mode.el
e/verilog-mode.el : verilog-mode.el ./config_rev.pl
-rm -rf e
-mkdir e
./config_rev.pl . . e/verilog-mode.el
e/verilog-mode.el.gz : e/verilog-mode.el
gzip --best $< --stdout > $@
x/verilog-mode.elc : x/verilog-mode.el
$(XEMACS) $(ELC) x/verilog-mode.el
e/verilog-mode.elc : e/verilog-mode.el
$(EMACS) $(ELC) e/verilog-mode.el
verilog.info : verilog.texinfo
makeinfo verilog.texinfo > verilog.info
######################################################################
# GNU GIT version
gnutrunk:
@echo "gnutrunk needs to be a symlink to a emacs/trunk git checkout"
false
.PHONY: gnu-update gnu-update-trunk
gnu-update: gnu-update-trunk
gnu-update-trunk: gnutrunk
echo "NOT DOING: cd gnutrunk && git pull"
.PHONY: gnu-diff-trunk gnu-diff
gnu-diff: gnu-diff-trunk
gnu-diff-trunk: gnu-update-trunk verilog-mode-tognu.el
diff -u gnutrunk/lisp/progmodes/verilog-mode.el verilog-mode-tognu.el
verilog-mode.patch: gnu-update verilog-mode-tognu.el
diff -u gnutrunk/lisp/progmodes/verilog-mode.el verilog-mode-tognu.el > $@
# Before install, clean to make sure we get proper git ID
gnu-cp:
$(MAKE) clean
$(MAKE) verilog-mode-tognu.el
cp verilog-mode-tognu.el gnutrunk/lisp/progmodes/verilog-mode.el
verilog-mode-tognu.el: e/verilog-mode.el Makefile
cat e/verilog-mode.el \
| sed 's/verilog-mode-version "\(.*\)"/verilog-mode-version "\1-GNU"/g' \
| sed 's/verilog-mode-release-emacs nil/verilog-mode-release-emacs t/g' \
> verilog-mode-tognu.el
######################################################################
# Clean
clean::
/bin/rm -rf .timestamps e x test_dir verilog-mode.patch verilog-mode-tognu.el mmencoded_verilog-mode *.info
verilog-mode-20161124.fd230e6/README 0000664 0000000 0000000 00000002607 13022141775 0016304 0 ustar 00root root 0000000 0000000 This is the source distribution for verilog-mode.
Please see http://www.veripool.org/verilog-mode
for more information.
make
make test
cp e/verilog-mode.el
======================================================================
TESTS
Make sure both emacs and xemacs are installed and "make test". Testing can run on multiple cores with "make -j 10 test".
Under the hood this is (mostly) running 0test.el. This reads in each file
under tests/ directory, autos, reindents, and compares the result to the
matching filename in the tests_ok directory.
Test failures generally look like this:
diff -c tests_ok/autoinout_ma.v e/t/autoinout_ma.v
***Golden Reference File
---Generated Test File
--- GOLDEN_REFERENCE
+++ CURRENT_BEHAVIOR
...
- output sina,
+ output siuna,
To promote current to golden, in shell buffer hit newline anywhere in next line (^P RETURN):
cp e/t/autoinout_ma.v tests_ok/autoinout_ma.v; VERILOG_MODE_START_FILE=tests_ok/autoinout_ma.v make test_emacs
This indicates the generated output doesn't match what is in tests_ok. To
fix this make sure that the change is expected then do the "cp" shown to
update the golden references:
cp e/t/autoinout_ma.v tests_ok/autoinout_ma.v
Then "make test" again. The suggested VERILOG_MODE_START_FILE can also be
used to jump right to that individual test inside the "make test"
verilog-mode-20161124.fd230e6/TODO 0000664 0000000 0000000 00000004404 13022141775 0016111 0 ustar 00root root 0000000 0000000 # DESCRIPTION: To-do list for verilog-mode
######################################################################
Occasionally:
* M-x checkdoc
* Make sure it's as byte compile clean as possible.
Features
Make a hiearchy map of the current module and below in a spare buffer.
;From: Dan Nicolaescu
;Date: Sun, 14 Oct 2007 10:49:43 -0700
; > (defvar verilog-mode-map ()
; > "Keymap used in Verilog mode.")
; > (if verilog-mode-map
; > ()
; > (setq verilog-mode-map (make-sparse-keymap))
; > (define-key verilog-mode-map ";" 'electric-verilog-semi)
; Better use:
; (defvar verilog-mode-map
; (let ((map (make-sparse-keymap)))
; (define-key map ";" 'electric-verilog-semi)
; ... etc etc
From: Stefan Monnier
Date: Sat, 13 Oct 2007 22:41:15 -0400
- Rather than create a new syntax-table in each buffer, just do
(defvar verilog-mode-syntax-table
(let ((st (make-syntax-table)))
(modify-syntax-table ...)
...
st))
once and forall (inlining the only calls to verilog-setup-dual-comments
and verilog-populate-syntax-table).
Regarding verilog-setup-dual-comments, even if you consider the XEmacs
solution cleaner, the Emacs solution is not only equivalent but it also
works under XEmacs, so you can use it everywhere and remove an
emacs-version check.
- You can then remove the verilog-emacs-features abomination.
- The part
(require 'verilog-mode)
is pretty hideous and deserves either to be fixed (i.e. removed), or large
comments justifying each part.
Also some of the subsequent requires are unneeded (e.g. the `imenu' one).
- Use easy-menu-add rather than add-submenu so it works on both Emacs
and XEmacs.
- Emacs-21's comment-region and uncomment-region should work correctly
(including mangling nested comments, although in a different way from the
one you chose).
verilog-comment-regiont and verilog-uncomment-region
can (probably) be dropped when running under Emacs>=21 (and the C-c C-c
binding could also be removed if you assume your users will use M-;)
verilog-mode-20161124.fd230e6/attic/ 0000775 0000000 0000000 00000000000 13022141775 0016523 5 ustar 00root root 0000000 0000000 verilog-mode-20161124.fd230e6/attic/verilog-lex.el 0000664 0000000 0000000 00000015431 13022141775 0021306 0 ustar 00root root 0000000 0000000 ;;
;; Lexical analysis
;;
(defconst verilog-token-comma ?, "Verilog-lex ','.")
(defconst verilog-token-semi ?; "Verilog-lex ';'.")
(defconst verilog-token-equal ?= "Verilog-lex '='.")
(defconst verilog-token-par ?( "Verilog-lex '('.")
(defconst verilog-token-en ?) "Verilog-lex ')'.")
(defconst verilog-token-bra ?{ "Verilog-lex '{'.")
(defconst verilog-token-ce ?} "Verilog-lex '}'.")
;; Lexical tokens specific to verilog-lex-decl
(defconst verilog-token-ASSIGN 300 "Verilog-lex 'KEYWORD'.")
(defconst verilog-token-PARAMETER 306 "Verilog-lex 'KEYWORD'.")
(defconst verilog-token-SIGNED 307 "Verilog-lex 'KEYWORD'.")
(defconst verilog-token-bracketed 311 "Verilog-lex '[...]'; value is what's within brackets.")
(defconst verilog-token-decl-const 301 "Verilog-lex declare constant.")
(defconst verilog-token-decl-wire 302 "Verilog-lex declare wire.")
(defconst verilog-token-direction 303 "Verilog-lex directional.")
(defconst verilog-token-ignore-begin 304 "Verilog-lex block to ignore begin.")
(defconst verilog-token-ignore-end 305 "Verilog-lex block to ignore end.")
(defconst verilog-token-symbol 310 "Verilog-lex symbol.")
(defconst verilog-token-synth-enum 312 "Verilog-lex Synopsys enum token; value is name of enumeration.")
(defconst verilog-token-type 308 "Verilog-lex data type.")
(defconst verilog-token-keyword 313 "Verilog-lex generic keyword.")
(defconst verilog-lex-keywords
'(
("assign" verilog-token-ASSIGN)
("bit" verilog-token-type)
("byte" verilog-token-type)
("class" verilog-token-ignore-begin)
("clocking" verilog-token-ignore-begin)
("covergroup" verilog-token-ignore-begin)
("endclass" verilog-token-ignore-end)
("endclocking" verilog-token-ignore-end)
("endfunction" verilog-token-ignore-end)
("endgroup" verilog-token-ignore-end)
("endproperty" verilog-token-ignore-end)
("endsequence" verilog-token-ignore-end)
("endtask" verilog-token-ignore-end)
("function" verilog-token-ignore-begin)
("genvar" verilog-token-decl-const)
("inout" verilog-token-direction)
("input" verilog-token-direction)
("int" verilog-token-type)
("integer" verilog-token-type)
("localparam" verilog-token-decl-const)
("logic" verilog-token-type)
("longint" verilog-token-type)
("output" verilog-token-direction)
("parameter" verilog-token-PARAMETER)
("property" verilog-token-ignore-begin)
("randsequence" verilog-token-ignore-begin)
("real" verilog-token-type)
("reg" verilog-token-type)
("sequence" verilog-token-ignore-begin)
("shortint" verilog-token-type)
("shortreal" verilog-token-type)
("signed" verilog-token-signing)
("supply" verilog-token-decl-const)
("supply0" verilog-token-decl-const)
("supply1" verilog-token-decl-const)
("task" verilog-token-ignore-begin)
("time" verilog-token-type)
("tri" verilog-token-decl-wire)
("tri0" verilog-token-decl-wire)
("tri1" verilog-token-decl-wire)
("triand" verilog-token-decl-wire)
("trior" verilog-token-decl-wire)
("trireg" verilog-token-type)
("wand" verilog-token-decl-wire)
("wire" verilog-token-decl-wire)
("wor" verilog-token-decl-wire)
)
"Map of keyword and token to return for `verilog-lex'.")
(defun verilog-lex (begin end for-decls)
"Lexically analyze Verilog text between BEGIN to END into tokens.
With FOR-DECL true, parse only for declarations. Returns list of
tokens, with each token a list of the text for that token and the
verilog-token-TYPE."
(let ((functask 0)
tokens token keywd ignore-next-symbol)
(save-excursion
(goto-char begin)
(while (< (point) end)
;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg)))
(cond
;; For performance it's better if frequent cases are first
((looking-at "//")
(when (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
(setq tokens (cons (list (match-string 1) verilog-token-synth-enum) tokens)))
(search-forward "\n"))
((looking-at "/\\*")
(forward-char 2)
(when (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
(setq tokens (cons (list (match-string 1) verilog-token-synth-enum) tokens)))
(or (search-forward "*/")
(error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
((looking-at "(\\*")
(forward-char 2)
(or (looking-at "\\s-*)") ; It's an "always @ (*)"
(search-forward "*)")
(error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
((eq ?\" (following-char))
(or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
(error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
;; []: Grab all text to ending ]. Probably should match bracket pairs and strip comments, but old version didn't
((looking-at "\\[[^]]+\\]")
(goto-char (match-end 0))
(setq tokens (cons (list (match-string 0) verilog-token-bracketed) tokens)))
;; Single character tokens we just pass through
((looking-at "[;,=(){}]")
(setq tokens (cons (list (following-char) (following-char)) tokens))
(forward-char 1))
;; Ifdef, ignore name of define
((looking-at "`ifn?def\\>")
(goto-char (match-end 0))
(setq ignore-next-symbol t))
;; Normal identifier
((looking-at "[`a-zA-Z0-9_$]+")
(goto-char (match-end 0))
;; buffer-substring is faster than match-string, and this is hot code.
(setq keywd (buffer-substring-no-properties (match-beginning 0) (match-end 0)))
(cond (ignore-next-symbol ;; preproc identifier after `ifdef
(setq ignore-next-symbol nil))
((member keywd verilog-keywords)
(setq token (assoc keywd verilog-lex-keywords))
;; Now you'll see why the token list has text first then the token number;
;; we can just return the assoc result directly
(cond ((eq token verilog-token-ignore-begin)
(setq functask (1+ functask)))
((eq token verilog-token-ignore-end)
(setq functask (1- functask)))
(token
(setq tokens (cons token tokens)))
(t
(setq tokens (cons (list keywd verilog-token-keyword) tokens)))))
;; Must be typedef or symbol. For speed, ignore if inside begin/end
((and (eq functask 0)
(verilog-typedef-name-p keywd))
(setq tokens (cons (list keywd verilog-token-typedef) tokens)))
;; Normal user symbol
((eq functask 0)
(setq tokens (cons (list keywd verilog-token-symbol) tokens)))))
;; Escaped identifier -- note we remember the \ if escaped
((looking-at "\\\\[^ \t\n\f]+")
(goto-char (match-end 0))
(when (eq functask 0)
(setq tokens (cons (list (concat (match-string-no-properties 0) " ") ;; Escaped ID needs space at end
verilog-token-symbol)
tokens))))
;; Default
(t
(forward-char 1)))
;; End of parser while
(skip-syntax-forward " "))
tokens)))
verilog-mode-20161124.fd230e6/batch_prof.el 0000664 0000000 0000000 00000004572 13022141775 0020060 0 ustar 00root root 0000000 0000000 ;; DESCRIPTION: Profile driven test as part of "make test"
;;
;; Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
;; is free software; you can redistribute it and/or modify it under the
;; terms of either the GNU Lesser General Public License or the Perl
;; Artistic License.
(require 'elp)
(defun t-make-test (count filename)
(save-excursion
(find-file filename)
(delete-region (point-min) (point-max))
(insert "
module EX_TIME_CONSUME (/*AUTOARG*/);
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
")
(setq i 0)
(while (< i count)
(insert "//----------------------------------------------------------------------\n")
(insert "/* batch_prof_cell AUTO_TEMPLATE (\n")
(insert (format " .Z(Z_%d)); */\n" i))
(insert (format "batch_prof_cell CELL_%d (/*AUTOINST*/);\n" i))
(setq i (+ 1 i)))
(insert "endmodule\n")
(save-buffer)))
(defun t-size-test (count)
;; Note is running in tests_batch_ok directory
(setq filename (format "e/b/batch_prof_%s.v" count))
(t-make-test count filename)
(when profile
(elp-reset-all))
(setq start (current-time))
(save-excursion
(find-file filename)
(verilog-auto))
(setq end (current-time))
(setq delta (time-to-seconds (time-subtract end start)))
(setq msper (/ (* 1000 delta) count))
(message "Count: %5d Time: %6.3f msec/inst: %6.3f File: %s"
count delta msper filename)
(when profile
(elp-results))
(when nil
(save-excursion
(find-file filename)
(save-buffer)))
msper)
;;======================================================================
(setq make-backup-files nil)
(copy-file "tests/batch_prof_cell.v" "e/b/batch_prof_cell.v" t)
(setq verilog-debug t)
(setq verilog-library-flags "-I.")
(setq verilog-auto-star-expand nil)
(setq profile (getenv "VERILOG_MODE_PROFILE"))
(when profile
(elp-restore-all)
(elp-instrument-package "verilog"))
(when t
;; Need to read the templated file
(setq t1 (t-size-test 1))
(setq t10 (t-size-test 10))
(setq t100 (t-size-test 100))
(setq t1000 (t-size-test 1000))
(when (getenv "VERILOG_MODE_10000")
(setq t10000 (t-size-test 10000)))
(setq slope (/ t1000 t100))
(setq order (1+ (/ (log slope)
(log 10))))
(message "Slope: %f Complexity: O(n^%f)" slope order)
(if (> slope 1.3)
(error "Test failed, large modules are too slow compared to small modules"))
)
verilog-mode-20161124.fd230e6/batch_test.el 0000664 0000000 0000000 00000000537 13022141775 0020066 0 ustar 00root root 0000000 0000000 ;; DESCRIPTION: Common Emacs flags needed for batch_test.pl
;;
;; Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
;; is free software; you can redistribute it and/or modify it under the
;; terms of either the GNU Lesser General Public License or the Perl
;; Artistic License.
(setq verilog-library-flags "-I. -I../../tests")
verilog-mode-20161124.fd230e6/batch_test.pl 0000775 0000000 0000000 00000003722 13022141775 0020103 0 ustar 00root root 0000000 0000000 #!/usr/bin/perl -w
# DESCRIPTION: Run batch tests, as part of "make test"
#
# Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
# is free software; you can redistribute it and/or modify it under the
# terms of either the GNU Lesser General Public License or the Perl
# Artistic License.
my $tmpdir = "e";
my @tests = map { s!^.*/!!; $_;} glob("tests_batch_ok/*");
my @tests_args;
foreach my $test (@tests) {
run("/bin/cp tests/$test e/b/$test");
push @tests_args, "e/b/$test";
}
run("emacs --version"
);
run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
." -l ./batch_test.el"
." ".join(' ',@tests_args)
." -f verilog-batch-delete-auto"
);
run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
." -l ./batch_test.el"
." ".join(' ',@tests_args)
." -f verilog-batch-auto"
);
run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
." -l ./batch_test.el"
." e/b/autoinst_lopaz.v"
." -f verilog-batch-diff-auto"
);
run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
." -l ./batch_test.el"
." e/b/autoinst_star.v"
." -f verilog-batch-diff-auto"
);
run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
." -l ./batch_test.el"
." ".join(' ',@tests_args)
." -f verilog-batch-indent"
);
foreach my $test (@tests) {
run("diff tests_batch_ok/$test e/b/$test");
}
run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
." -l ./batch_test.el"
." ".join(' ',@tests_args)
." -f verilog-batch-delete-trailing-whitespace"
);
run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
." -l ./batch_prof.el"
);
#######################################################################
sub run {
# Run a system command, check errors
my $command = shift;
print "\t$command\n";
system "$command";
my $status = $?;
($status == 0) or die "%Error: Command Failed $command, stopped";
}
verilog-mode-20161124.fd230e6/config_rev.pl 0000775 0000000 0000000 00000002217 13022141775 0020102 0 ustar 00root root 0000000 0000000 #!/usr/bin/perl -w
# DESCRIPTION: Query's git to get version number
######################################################################
#
# Copyright 2005-2013 by Wilson Snyder. This is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
#
######################################################################
my $dir = $ARGV[0]; defined $dir or die "%Error: No directory argument,";
chdir $dir;
my $file = $ARGV[1]; defined $file or die "%Error: No file argument,";
my $rev = 'UNKNOWN_REV';
my $data = `git log --pretty=format:'%ad-%h' --date=short -1 $file`;
if ($data =~ /(^20.*)/i) {
$rev = $1;
}
$data = `git status $file`;
if ($data =~ /Changed but not updated/i
|| $data =~ /Changes to be committed/i) {
$rev .= "-mod";
}
# Filter the code
my $wholefile = join('',);
$wholefile =~ s/__VMVERSION__-__VMREVISION__/$rev/mg;
$wholefile =~ s/__VMPACKAGER__/vpo/mg;
print $wholefile;
# Die after the print, so at least the header has good contents
$rev =~ /UNKNOWN/ and warn "%Warning: No git revision found,";
verilog-mode-20161124.fd230e6/error_file.v 0000664 0000000 0000000 00000000334 13022141775 0017736 0 ustar 00root root 0000000 0000000 1;
2;
3;
4;
5;
6;
7;
8;
9;
10;
11;
12;
13;
14;
15;
16;
17;
18;
19;
20;
21;
22;
23;
24;
25;
26;
27;
28;
29;
30;
31;
32;
33;
34;
35;
36;
37;
38;
39;
40;
// Local Variables:
// compile-command: "make test_errors "
// End:
verilog-mode-20161124.fd230e6/error_msgs.out 0000664 0000000 0000000 00000002361 13022141775 0020334 0 ustar 00root root 0000000 0000000 A bunch of error messages that Emacs should
recognize if you type C-x ` and take you to the correct line of error_file.v
Note the 'gnu' compilation-error-regexp-alist in messes some up - to be fixed.
(setq compilation-error-regexp-alist (delete 'gnu compilation-error-regexp-alist))
Warning: code located there (error_file.v line 9) is dangerous
(W1800) error_file.v 21: Problems
f*E,1364 (error_file.v,2) Issues
Error: code located here (error_file.v line 8) is fatal
ERROR : error_file.v, line 1: erroneous
INFO : error_file.v, line 7: informational
WARNING : error_file.v, line 6: curious
nctool: *E,UNDIDN (error_file.v,11|22): 'zz': the message [12.5(IEEE)].
nctool: *W,TRUNCZ (error_file.v,14|0): a W message.
nctool: *W,URDREG[CN_ABSTR] (error_file.v,15|0): another W message in 'foo'.
Verilog-Perl: %Error: error_file.v:16: Some message from Verilog-Perl etc.
Verilog-Perl: %Warning: ./error_file.v:17: Some message from Verilog-Perl etc.
%Warning: ./error_file.v:17: Some message from Verilator etc.
# This must be in one echo, or the comint may not match it
In file error_file.v line 5:
a
b
Failure was obsevred
la di da
syntax error: problems
error_file.v 7: here is where they are
// Local Variables:
// compile-command: "make test_errors "
// End:
verilog-mode-20161124.fd230e6/make_log.pl 0000775 0000000 0000000 00000003302 13022141775 0017533 0 ustar 00root root 0000000 0000000 #!/usr/bin/perl
unlink("log");
$attach_name = "verilog-mode.el.gz";
$encoded_data = `gzip -c9 verilog-mode.el | mmencode `;
if ( -d ".svn") {
system("svn log verilog-mode.el > log");
open(LOG,") {
if (/^r([\d\.]+)/) {
$rev = $1;
last;
}
}
} else {
system("cvs log verilog-mode.el > log");
open(LOG,") {
if (/^head: ([\d\.]+)$/) {
$rev = $1;
}
last if (/^description:$/);
}
}
open(O,">emacs-version.h");
open(C,">ChangeLog.txt");
$release_date = `date +"%D"`;
print O <<"X";
$rev
$release_date
X
close(O);
open(O,">mmencoded_verilog-mode");
print O <<"XX";
MIME-version: 1.0
Content-type: multipart/mixed; boundary="Message-Boundary"
Content-transfer-encoding: 7BIT
X-attachments: verilog-mode.el.gz
--Message-Boundary
Content-type: text/plain; charset=US-ASCII
Content-transfer-encoding: 7BIT
Content-description: Mail message body
+----------------------------------------------------------------+
| Here is version $rev of verilog-mode for emacs! |
+----------------------------------------------------------------+
XX
open(IO, "){
print O $_;
}
print O "\nLast few changes to the verilog-mode:\n";
while() {
$log++ if (/^----------------------------$/);
print C $_;
last if ($log > 10);
print O $_;
}
while() {
print C $_;
}
close(LOG);
print O <<"XX";
--Message-Boundary
Content-type: application/octet-stream; name="$attach_name"
Content-Transfer-Encoding: base64
Content-disposition: attachment; filename="$attach_name"
$encoded_data
--Message-Boundary--
XX
close(O);
unlink("log");
verilog-mode-20161124.fd230e6/make_mail.pl 0000775 0000000 0000000 00000001464 13022141775 0017703 0 ustar 00root root 0000000 0000000 #!/usr/bin/perl
$owner = "mac";
$destination = "mac\@verilog.com";
$verilog = "/home/mac/development/www.verilog.com/src/data/mmencoded_verilog-mode";
if ( -d ".svn") {
open(LOG,") {
if (/^r([\d\.]+)/) {
$rev = $1;
last;
}
}
} else {
open(LOG,") {
if (/^head: ([\d\.]+)$/) {
$rev = $1;
}
last if (/^description:$/);
}
}
open(VM, "< $verilog") || die "Can not open $verilog\n";
open(SM, "|/usr/lib/sendmail -bm -f $owner -F \"Mike McNamara\" -t");
# $destination = "mac\@verilog.com";
# open(SM, "> mail.test");
print SM "To: $destination\nReply-To: mac\@verilog.com\nBCC: mac\@verilog.com\nSubject: SUBSCRIPTION: Emacs Verilog-mode $rev\n";
while() {
print SM $_;
}
close(SM) || die "mailing dies with error: $!\n";
close(VM);
verilog-mode-20161124.fd230e6/makechangelog 0000775 0000000 0000000 00000010633 13022141775 0020135 0 ustar 00root root 0000000 0000000 #!/usr/bin/perl -w # -*- Perl -*-
# See copyright, etc in below POD section.
######################################################################
require 5.006_001;
use Getopt::Long;
#use Data::Dumper; $Data::Dumper::Indent=1; #Debug
use IO::File;
use IO::Dir;
use Pod::Usage;
use strict;
use vars qw ($Debug);
#======================================================================
# main
our $Opt_FileA;
our $Opt_FileB;
our $Opt_Git;
our $Opt_Svn;
autoflush STDOUT 1;
autoflush STDERR 1;
Getopt::Long::config ("no_auto_abbrev");
if (! GetOptions (
"help" => \&usage,
"debug" => sub { $Debug = 1; },
"<>" => \¶meter,
"git!" => \$Opt_Git,
"svn!" => \$Opt_Svn,
)) {
die "%Error: Bad usage, try 'makechangelog --help'\n";
}
if ($Opt_Svn) {
my $now = $Opt_FileA;
$Opt_FileA = ".svn/text-base/${now}.svn-base";
$Opt_FileB = $now;
} elsif ($Opt_Git) {
my $now = $Opt_FileA;
$Opt_FileA = "/tmp/mcl.$$";
$Opt_FileB = $now;
system("git show HEAD:${now} > $Opt_FileA");
}
read_file($Opt_FileA, $Opt_FileB);
if ($Opt_Git) {
unlink($Opt_FileA);
}
#----------------------------------------------------------------------
sub usage {
print '$Id$ ', "\n";
pod2usage(-verbose=>2, -exitval => 2);
exit (1);
}
sub parameter {
my $param = shift;
if (!$Opt_FileA) {
$Opt_FileA = $param;
} elsif (!$Opt_FileB) {
$Opt_FileB = $param;
} else {
die "%Error: Unknown parameter: $param\n";
}
}
#######################################################################
sub read_file {
my $a = shift;
my $b = shift;
my @l = (read_lines($a), read_lines($b));
# Note we ignore whitespace
my $fh = IO::File->new("diff -b -c $a $b |") or die "%Error: $!,";
my @ln = (0,0);
my %difffuncs;
my $mode = 0;
my @difflines;
while (defined(my $line = $fh->getline)) {
my $fn = "";
if ($line =~ /^\*\*\* (\d+)/) {
$mode = 0;
$ln[$mode] = $1 - 1;
} elsif ($line =~ /^\-\-\- (\d+)/) {
$mode = 1;
$ln[$mode] = $1 - 1;
} elsif ($line =~ /^\*\*\*/) {
} elsif ($line =~ /^\-\-\-/) {
} else {
$ln[$mode]++;
if ($line =~ /^[!-+]/) {
my $checkline = substr($line,2);
chomp $checkline;
$checkline =~ s/;.*$//;
$checkline =~ s/[ \t\n]+$//;
if ($checkline ne "") {
$fn = $l[$mode][ $ln[$mode] ] || "Line#".$ln[$mode];
$difffuncs{$fn} = 1;
}
}
}
(my $fnq = $fn||"") =~ s/^verilog-/v-/g;
push @difflines, sprintf ("%05d: %-20s: %s",$ln[$mode],substr($fnq,0,20), $line);
}
$fh->close;
print "-*- Change-Log -*-\n\n";
my ($sec,$min,$hour,$mday,$mon,$year,$wday,$yday,$isdst) = localtime();
printf "\n\n";
print "\t* verilog-mode.el";
my $f="";
my $sep = " (";
foreach my $func (sort keys %difffuncs) {
next if $func eq 'verilog-mode-release-date';
next if $func eq 'verilog-mode-version';
$f .= $sep.$func;
$sep = ", ";
}
$f .= ")" if $f;
print "$f:\n";
print "\n";
print "="x70,"\n";
print join('',@difflines);
}
sub read_lines {
my $filename = shift;
my @lines;
my $func;
my $fh = IO::File->new($filename) or die "%Error: $! $filename\n";
my $ln = 0;
while (defined(my $line = $fh->getline)) {
$ln++;
$func = undef if ($line =~ /^\(/);
$func = $1 if $line =~ /^\(def[---a-z]+\s+\'?(\S+)/;
$lines[$ln] = $func;
printf "%05d %-30s %s", $ln, $func||"", $line if $Debug;
}
$fh->close;
return \@lines;
}
#######################################################################
__END__
=pod
=head1 NAME
makechangelog -
=head1 SYNOPSIS
./makechangelog --svn verilog-mode.el
=head1 DESCRIPTION
dd
=head1 ARGUMENTS
=over 4
=item --help
Displays this message and program version and exits.
=back
=head1 DISTRIBUTION
This is part of the L free Verilog EDA software
tool suite. The latest version is available from CPAN and from
L.
Copyright 2008-2013 by Wilson Snyder. This package is free software; you
can redistribute it and/or modify it under the terms of either the GNU
Lesser General Public License or the Perl Artistic License.
=head1 AUTHORS
Wilson Snyder
=head1 SEE ALSO
=cut
######################################################################
### Local Variables:
### compile-command: "./makechangelog --svn verilog-mode.el"
### End:
verilog-mode-20161124.fd230e6/tests/ 0000775 0000000 0000000 00000000000 13022141775 0016561 5 ustar 00root root 0000000 0000000 verilog-mode-20161124.fd230e6/tests/abc.sv 0000664 0000000 0000000 00000000700 13022141775 0017655 0 ustar 00root root 0000000 0000000
covergroup CB;
a: coverpoint tr.a
{
bins a0 = {0};
bins a1 = {1};
option.weight=0;
}
b: coverpoint tr.b {
bins b0 = {0};
bins b1 = {1};
option.weight=0;
}
ab: cross a,b {
bins a0b0 = binsof(a.a0) && binsof(b.b0);
bins a1b0 = binsof(a.a1) && binsof(b.b0);
bins b0 = binsof(b.b0);
}
endgroup // CB
verilog-mode-20161124.fd230e6/tests/auto_delete_whitespace.v 0000664 0000000 0000000 00000000445 13022141775 0023461 0 ustar 00root root 0000000 0000000 // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
// Note intentional whitespace on following line
// SPACES
module x;
// TAB
endmodule
// Local Variables:
// verilog-auto-delete-trailing-whitespace: t
// End:
verilog-mode-20161124.fd230e6/tests/autoarg_comment.v 0000664 0000000 0000000 00000000357 13022141775 0022141 0 ustar 00root root 0000000 0000000 module autoarg_comment
// Copyright 1997-1998, blah, blah, blah
(/*AUTOARG*/);
//verilint 332 OFF //* Not all possible cases covered, but default case exists
input (* ATTRIB="val" *) income;
output outgo2;
endmodule
verilog-mode-20161124.fd230e6/tests/autoarg_jwells_comment.v 0000664 0000000 0000000 00000000466 13022141775 0023522 0 ustar 00root root 0000000 0000000 module tahoetop(/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
// the pad instance to look like "pads pads (/*AUTOINST*/". Then at
// diff the new against the old. Finally delete /*AUTOINST*/. This will
endmodule
verilog-mode-20161124.fd230e6/tests/autoarg_quote_cmt.v 0000664 0000000 0000000 00000000126 13022141775 0022471 0 ustar 00root root 0000000 0000000 // bug360
module f (/*AUTOARG*/);
always @* r = "test/*";
input x;
endmodule
verilog-mode-20161124.fd230e6/tests/autoarg_single.v 0000664 0000000 0000000 00000000255 13022141775 0021755 0 ustar 00root root 0000000 0000000 // msg1354
module f (/*AUTOARG*/);
output o2;
input z;
input a;
input q;
output o1;
endmodule
// Local Variables:
// verilog-auto-arg-format:single
// End:
verilog-mode-20161124.fd230e6/tests/autoarg_sort_fedeli.v 0000664 0000000 0000000 00000000230 13022141775 0022764 0 ustar 00root root 0000000 0000000 module (/*AUTOARG*/);
output o2;
input z;
input a;
input q;
output o1;
endmodule
// Local Variables:
// verilog-auto-arg-sort:t
// End:
verilog-mode-20161124.fd230e6/tests/autoarg_string_bug259.v 0000664 0000000 0000000 00000001262 13022141775 0023076 0 ustar 00root root 0000000 0000000 module bug_minimal
(input wire GND,
input wire VDD,
inout wire PIN1,
inout wire PIN2,
inout wire PIN3,
inout wire PIN4
/*AUTOARG*/);
// ----------------------------------------------------------------
/*AUTOWIRE*/
// ----------------------------------------------------------------
task force_value_to_1;
begin
$display("Enable test module checking ...");
force `value = 1'b1;
end
endtask
// ---------------------------------------------------------------
task force_value_to_0;
begin
$display("Disable test module checking ...");
force `value = 1'b0;
end
endtask
endmodule
verilog-mode-20161124.fd230e6/tests/autoarg_supply_bug438.v 0000664 0000000 0000000 00000000404 13022141775 0023120 0 ustar 00root root 0000000 0000000 module top
(
/*AUTOINPUT*/
);
/*AUTOWIRE*/
inst_module inst (/*AUTOINST*/);
endmodule
module inst_module (input supply0 VDD,
input supply1 VSS,
input non_supply,
input supply1 VDD_from_child
);
endmodule
verilog-mode-20161124.fd230e6/tests/autoascii_myers.v 0000664 0000000 0000000 00000002667 13022141775 0022163 0 ustar 00root root 0000000 0000000 module testit;
reg clk;
reg a_i;
reg b_i;
reg a_o;
reg b_o;
reg rst_n;
reg [7:0] shreg;
//== State enumeration
parameter [2:0] // synopsys enum state_info
SM_IDLE = 3'b000,
SM_SEND = 3'b001,
SM_WAIT1 = 3'b010;
//== State variables
reg [2:0] /* synopsys enum state_info */
state_r; /* synopsys state_vector state_r */
reg [2:0] /* synopsys enum state_info */
state_e1;
//== ASCII state decoding
/*AUTOASCIIENUM("state_r", "_stateascii_r", "sm_")*/
// Beginning of automatic ASCII enum decoding
reg [39:0] _stateascii_r; // Decode of state_r
always @(state_r) begin
case ({state_r})
SM_IDLE: _stateascii_r = "idle ";
SM_SEND: _stateascii_r = "send ";
SM_WAIT1: _stateascii_r = "wait1";
default: _stateascii_r = "%Erro";
endcase
end
// End of automatics
initial begin
clk = 0;
a_i = 0;
b_i = 0;
rst_n = 0;
#20 rst_n = 1;
end
always #5 clk = ~clk;
always @(posedge clk or rst_n) begin
if (~rst_n) begin
a_o <= 0;
b_o <= 0;
shreg <= 8'b00110011;
end
else begin
a_o <= a_i;
b_o <= b_i;
shreg <= {shreg[6:0], shreg[7]};
end
end
task set_a_i;
begin
a_i = shreg[0];
end
endtask // set_a_i
always @(shreg & a_o) begin
set_a_i;
end
initial begin
$vcdpluson;
#500 $finish;
end
endmodule // testit
verilog-mode-20161124.fd230e6/tests/autoascii_peltan.v 0000664 0000000 0000000 00000001431 13022141775 0022273 0 ustar 00root root 0000000 0000000 module autoascii_peltan
(
input test,
output [1:0] test_out
);
`include "autoascii_peltan_inc.v"
// Duplicate of what's in _inc
localparam [3:0] /* synopsys enum xstate */
state0 = 4'h0;
wire [3:0] /* synopsys enum xstate */
xstate;
/* synopsys translate off */
/*AUTOASCIIENUM("xstate", "v_xstate")*/
// Beginning of automatic ASCII enum decoding
reg [47:0] v_xstate; // Decode of xstate
always @(xstate) begin
case ({xstate})
state0: v_xstate = "state0";
state1: v_xstate = "state1";
default: v_xstate = "%Error";
endcase
end
// End of automatics
/* synopsys translate on */
endmodule // sample
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/autoascii_peltan_inc.v 0000664 0000000 0000000 00000000116 13022141775 0023123 0 ustar 00root root 0000000 0000000 localparam [3:0] /* synopsys enum xstate */
state0 = 4'h0,
state1 = 4'h1;
verilog-mode-20161124.fd230e6/tests/autoasciienum_auto.v 0000664 0000000 0000000 00000000723 13022141775 0022650 0 ustar 00root root 0000000 0000000 // Code ok to distribute
module autoasciienum_auto();
reg [2:0] /* auto enum sm_psm */ sm_psm;
reg [2:0] /* auto enum sm_ps2 */ sm_ps2;
localparam [2:0] // auto enum sm_psm
PSM_IDL = 0,
PSM_RST = 6,
PSM_ZOT = 7;
localparam [2:0] // auto enum sm_ps2
PS2_IDL = 0,
PS2_FOO = 1;
/*AUTOASCIIENUM("sm_psm", "_sm_psm__ascii", "_")*/
/*AUTOASCIIENUM("sm_ps2", "_sm_ps2__ascii", "_")*/
endmodule : autoasciienum_auto
verilog-mode-20161124.fd230e6/tests/autoasciienum_ex.v 0000664 0000000 0000000 00000001457 13022141775 0022321 0 ustar 00root root 0000000 0000000 module sm (/*AUTOARG*/
// Outputs
state_e1, state_r
);
output [2:0] state_e1;
output [2:0] state_r;
//== State enumeration
parameter [2:0] // synopsys enum state_info
SM_IDLE = 3'b000,
SM_ACT = 3'b010;
//== State variables
reg [2:0] /* synopsys enum state_info */
state_r; /* synopsys state_vector state_r */
reg [2:0] /* synopsys enum state_info */
state_e1;
//== ASCII state decoding
/*AUTOASCIIENUM("state_r", "_stateascii_r", "sm_")*/
// Beginning of automatic ASCII enum decoding
reg [31:0] _stateascii_r; // Decode of state_r
always @(state_r) begin
case ({state_r})
SM_IDLE: _stateascii_r = "idle";
SM_ACT: _stateascii_r = "act ";
default: _stateascii_r = "%Err";
endcase
end
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests/autoasciienum_frominc.v 0000664 0000000 0000000 00000002101 13022141775 0023325 0 ustar 00root root 0000000 0000000 module sm (/*AUTOARG*/);
//==================== Constant declarations ==============
`include "autoasciienum_param.v"
//==================== Intermediate Variables =============
reg [3:0] /* synopsys enum En_C14ChipNum */ chip_r;
//==================== DEBUG ASCII CODE =========================
/*AUTOASCIIENUM("chip_r", "chip_r__ascii","Ep_C14ChipNum_")*/
// Beginning of automatic ASCII enum decoding
reg [31:0] chip_r__ascii; // Decode of chip_r
always @(chip_r) begin
case ({chip_r})
EP_C14ChipNum_RNP: chip_r__ascii = "rnp ";
EP_C14ChipNum_SPP: chip_r__ascii = "spp ";
EP_C14ChipNum_SRP: chip_r__ascii = "srp ";
EP_C14ChipNum_SMM2: chip_r__ascii = "smm2";
EP_C14ChipNum_SMM: chip_r__ascii = "smm ";
EP_C14ChipNum_TTE: chip_r__ascii = "tte ";
EP_C14ChipNum_DLE: chip_r__ascii = "dle ";
EP_C14ChipNum_OASP: chip_r__ascii = "oasp";
default: chip_r__ascii = "%Err";
endcase
end
// End of automatics
endmodule
//==== Emacs verilog-mode controls ====
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/autoasciienum_onehot.v 0000664 0000000 0000000 00000001641 13022141775 0023174 0 ustar 00root root 0000000 0000000 // lint_checking MODLNM OFF
module autoasciienum_onehot (
input clk,
input rst_n,
output ack
);
localparam // synopsys enum state_info
IDLE = 0,
S1 = 1,
S2 = 2,
S3 = 3,
DONE = 4;
reg [4:0] // synopsys enum state_info
cur_state, nxt_state;
always @ (*) begin
nxt_state = 5'h0;
case (1'b1)
cur_state[IDLE] : nxt_state[S1] = 1'b1;
cur_state[S1] : nxt_state[S2] = 1'b1;
cur_state[S2] : nxt_state[S3] = 1'b1;
cur_state[S3] : nxt_state[DONE] = 1'b1;
cur_state[DONE] : nxt_state[DONE] = 1'b1;
endcase
end
always @ (posedge clk or negedge rst_n)
if (rst_n == 1'b0) begin
cur_state <= 'h1;
end
else begin
cur_state <= nxt_state;
end
assign ack = cur_state[DONE];
/*AUTOASCIIENUM("cur_state", "cur_state_ascii")*/
endmodule
verilog-mode-20161124.fd230e6/tests/autoasciienum_param.v 0000664 0000000 0000000 00000001037 13022141775 0022777 0 ustar 00root root 0000000 0000000
`ifdef NOTDEFINED
module just_for_proper_indentation ();
`endif
//Verilint 175 off //WARNING: Unused parameter
parameter // synopsys enum En_C14ChipNum
EP_C14ChipNum_OASP = 4'h0,
EP_C14ChipNum_DLE = 4'h2,
EP_C14ChipNum_TTE = 4'h3,
EP_C14ChipNum_SMM = 4'h4,
EP_C14ChipNum_SMM2 = 4'h5,
EP_C14ChipNum_SRP = 4'h6,
EP_C14ChipNum_SPP = 4'h7,
EP_C14ChipNum_RNP = 4'h8;
verilog-mode-20161124.fd230e6/tests/autoasciienum_reed.v 0000664 0000000 0000000 00000001056 13022141775 0022617 0 ustar 00root root 0000000 0000000
module sm ();
localparam STATES = 7;
localparam /* synopsys enum states */
IDLE = 0, // '001
READ = 1, // '002
THINK = 2, // '004
SEND = 3, // '008
WAIT = 4, // '040
GET_ACK = 5, // '080
WAIT_REGBUS = 6; // '100
reg [STATES-1:0] /*synopsys enum states*/
state_i, state_r; /* synopsys state_vector state_r */
/*AUTOASCIIENUM("state_r","state_onehot,ascii_r","","onehot")*/
/*AUTOASCIIENUM("state_r","state_notonehot_ascii_r")*/
endmodule
verilog-mode-20161124.fd230e6/tests/autoasciienum_sm.v 0000664 0000000 0000000 00000004534 13022141775 0022323 0 ustar 00root root 0000000 0000000 module sm (/*AUTOARG*/
// Outputs
state_r,
// Inputs
clk, rst_
);
//==================== Constant declarations ==============
parameter [2:0] // synopsys enum state_info
IDLE = 3'b000,
SEND = 3'b001,
WAIT1 = 3'b010,
UPDATE1 = 3'b011,
WAIT2 = 3'b100;
parameter [2:0] /* synopsys enum state_info */ UPDATE2 = 3'b101;
parameter [2:0] NOT_A_STATE_ELEMENT = 3'b101;
parameter [2:0] /* synopsys enum other */
A_OTHER_STATE_ELEMENT = 3'b101;
//==================== Input Signals ======================
input clk; // System clock signal
input rst_;
//==================== Output Signals =====================
// s_ynopsys requires the enum comment between the keyword and the symbol While this seems silly,
// verilog requires this also to avoid misleading people that also use their tools.
output [2:0] state_r; // SM State information (to GPF)
//==================== Intermediate Variables =============
reg [2:0] /* synopsys enum state_info */ state_r; /* synopsys state_vector state_r */
reg [2:0] /* synopsys enum state_info */ state_e1; // next state of state-machine
//==================== Code Begin =========================
always @(/*AUTOSENSE*/state_r) begin
case(state_r) // synopsys full_case parallel_case
IDLE: begin
state_e1 = SEND;
end
SEND: begin
state_e1 = WAIT1;
end
WAIT1: begin
state_e1 = UPDATE1;
end
UPDATE1: begin
state_e1 = UPDATE2;
end
WAIT2: begin
state_e1 = UPDATE2;
end
UPDATE2: begin
state_e1 = IDLE;
end
default: state_e1 = state_r;
endcase
end
always @(posedge clk or negedge rst_) begin
if (~rst_) begin
state_r <= #0 IDLE;
end
else begin
state_r <= #0 state_e1;
end
end
//==================== DEBUG ASCII CODE =========================
/*AUTOASCIIENUM("state_r", "_stateascii_r")*/
// Beginning of automatic ASCII enum decoding
reg [55:0] _stateascii_r; // Decode of state_r
always @(state_r) begin
case ({state_r})
IDLE: _stateascii_r = "idle ";
SEND: _stateascii_r = "send ";
WAIT1: _stateascii_r = "wait1 ";
UPDATE1: _stateascii_r = "update1";
WAIT2: _stateascii_r = "wait2 ";
UPDATE2: _stateascii_r = "update2";
default: _stateascii_r = "%Error ";
endcase
end
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests/autoconst_gesmith.v 0000664 0000000 0000000 00000000430 13022141775 0022504 0 ustar 00root root 0000000 0000000 module(/*AUTOARG*/)
always @(`ot.BOZ or
/*AUTOSENSE*/b)
begin
/*AUTO_CONSTANT(`ot.BOC) */
i = b;
c = `ot.BOC;
d = `ot.BOZ;
end
always @(/*AUTOSENSE*/b)
begin
/*AUTO_CONSTANT(ot.BOB) */
i = b;
c = ot.BOB;
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoconstant_gooch.v 0000664 0000000 0000000 00000003207 13022141775 0022653 0 ustar 00root root 0000000 0000000 module autoconstant_gooch
(/*AUTOARG*/
// Outputs
out1, out2, out3,
// Inputs
in1, in2, in3
);
input [3:0] in1;
input [3:0] in2;
input [3:0] in3;
output [3:0] out1;
reg [3:0] out1;
output [3:0] out2;
reg [3:0] out2;
output [3:0] out3;
reg [3:0] out3;
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
case (in1)
4'b0001 : begin
out1 = in2;
end
4'b0010 : begin
out1 = in2 + in3;
end
4'b0100 : begin
out1 = in2 - in3;
end
4'b1000 : begin
out1 = in2;
end
default : begin
out1 = {4{1'b0}};
end
endcase
end
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
case (in1)
4'b0001 : begin
out2 = in2;
end
4'b0010 : begin
out2 = in2 + in3;
end
4'b0100 : begin
out2 = in2 - in3;
end
4'b1000 : begin
out2 = in2;
end
default : begin
out2 = {4{1'b0}};
end
endcase
end
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
/* AUTO_CONSTANT( temp )*/
/* AxxxUTO_CONSTANT temp */
out3 = in1 + in2;
temp2 = temp;
// ERROR here - above constant definition is not
// correct - no braces - and so parser keeps looking
// for the first variable it finds between a pair of
// braces - in this case, in2. This in2 is now a
// "constant" and is removed from all sensitivity lists.
// ( in2 )
case (in1)
4'b0001 : begin
out3 = in2;
end
4'b0010 : begin
out3 = in2 + in3;
end
4'b0100 : begin
out3 = in2 - in3;
end
4'b1000 : begin
out3 = in2;
end
default : begin
out3 = {4{1'b0}};
end
endcase
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoinout.v 0000664 0000000 0000000 00000000667 13022141775 0021010 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOINOUT*/
/*AUTOOUTPUT*/
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
instio instio (/*AUTOINST*/);
endmodule
module instio (/*AUTOARG*/);
input lower_ina;
inout lower_io;
output lower_out;
input sec_ina;
inout sec_io;
output sec_out;
wire lower_out = lower_ina | lower_io;
wire sec_out = sec_ina | sec_io;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinout_lovell.v 0000664 0000000 0000000 00000001145 13022141775 0022355 0 ustar 00root root 0000000 0000000 // Matthew Lovell
module top_test(/*AUTOARG*/);
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/* leaf AUTO_TEMPLATE (
// Original reported bug
.a ({aa, test2.test3.no, test3.test4.no2}),
// Others
.b ( ~ ba),
.c ({\c-escaped-nvec , \c-escaped-vec [2:0] }),
.d ({da,~ db [1:0] , dc [2:0]}),
// Msg246
.e ({{4*1{1'b0}},Z_int[15:0],{1'b4{1'b0}},Z0_int[7:0]}),
.f (hi.ear.ial),
);
*/
leaf l1 (/*AUTOINST*/);
endmodule // top_test
module leaf(/*AUTOARG*/);
output a;
output b;
input c;
input d;
input e;
input f;
input z;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinout_ma.v 0000664 0000000 0000000 00000000342 13022141775 0021453 0 ustar 00root root 0000000 0000000 module foo
(
input soutb,
output sina,
/*AUTOINPUT*/
/*AUTOOUTPUT*/
) ;
bar i_bar(/*AUTOINST*/);
endmodule // foo
module bar (/*AUTOARG*/) ;
input sina, sinb;
output souta, soutb;
endmodule // bar
verilog-mode-20161124.fd230e6/tests/autoinout_moller.v 0000664 0000000 0000000 00000001471 13022141775 0022354 0 ustar 00root root 0000000 0000000 module a ( /*AUTOARG*/
// Outputs
o1,
// Inouts
io1,
// Inputs
i1
) ;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input i1; // To b of b.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output o1; // From b of b.v
// End of automatics
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout io1; // To/From b of b.v
// End of automatics
b b
(/*AUTOINST*/
// Outputs
.o1 (o1),
// Inouts
.io1 (io1),
// Inputs
.i1 (i1));
endmodule // a
module b (/*AUTOARG*/
// Outputs
o1,
// Inouts
io1,
// Inputs
i1
) ;
input i1 ;
output o1 ;
inout io1 ;
endmodule // b
verilog-mode-20161124.fd230e6/tests/autoinout_regexp.v 0000664 0000000 0000000 00000000711 13022141775 0022350 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOARG*/);
/*AUTOINPUT("^s")*/
/*AUTOINOUT("^s")*/
/*AUTOOUTPUT("^s")*/
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
instio instio (/*AUTOINST*/);
endmodule
module instio (/*AUTOARG*/);
input lower_ina;
inout lower_io;
output lower_out;
input sec_ina;
inout sec_io;
output sec_out;
wire lower_out = lower_ina | lower_io;
wire sec_out = sec_ina | sec_io;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinout_v2k.v 0000664 0000000 0000000 00000001415 13022141775 0021562 0 ustar 00root root 0000000 0000000 module parent
(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOINOUT*/
);
/*AUTOWIRE*/
child_a sub_module
(/*AUTOINST*/);
child_b sub_module
(/*AUTOINST*/);
endmodule // parent
module child_a
(
input [3:0] a,
input [3:0] a2,
input [3:0] a3,
input [3:0] a4,
inout [5:0] c,
inout [5:0] c2,
inout c3,
output [2:0] b,
output [2:0] b2,
output [2:0] b3,
output [2:0] b4,
input clk,
output d
);
endmodule
module child_b
(
output [3:0] a,
output [3:0] a4,
inout [5:0] c,
inout [5:0] c2,
inout c3,
input [2:0] b,
input [2:0] b2,
input [2:0] b3,
input [2:0] b4,
input clk
);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutcomp.v 0000664 0000000 0000000 00000000326 13022141775 0021657 0 ustar 00root root 0000000 0000000 module autoinoutmodule (/*AUTOARG*/);
output lower_inb;
/*AUTOINOUTCOMP("inst")*/
// Beginning of automatic in/out/inouts (from specific module)
wire lower_out = lower_ina | lower_inb;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutin.v 0000664 0000000 0000000 00000000112 13022141775 0021320 0 ustar 00root root 0000000 0000000 module autoinoutin (/*AUTOARG*/);
/*AUTOINOUTIN("inst")*/
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutmodport_bourduas_type.v 0000664 0000000 0000000 00000001311 13022141775 0025345 0 ustar 00root root 0000000 0000000 //-*- mode: Verilog; verilog-indent-level: 3; indent-tabs-mode: nil; tab-width: 1 -*-
module apl2c_connect(autoinoutmodport_type_intf ctl_i,
/*AUTOINOUTMODPORT("autoinoutmodport_type_intf", "ctl_cb")*/
);
/*AUTOASSIGNMODPORT("autoinoutmodport_type_intf", "ctl_cb", "ctl_i")*/
endmodule
interface autoinoutmodport_type_intf(input logic clk, input logic rst_n);
import uvm_pkg::*;
import ap_defines::*;
logic [4:0] inst;
isel_t isel;
logic replay;
clocking ctl_cb @(posedge clk);
input inst;
input isel;
input replay;
endclocking: ctl_cb
modport ctl_mp(clocking ctl_cb);
endinterface
// Local Variables:
// verilog-typedef-regexp:"_t"
// End:
verilog-mode-20161124.fd230e6/tests/autoinoutmodule.v 0000664 0000000 0000000 00000000641 13022141775 0022206 0 ustar 00root root 0000000 0000000 module autoinoutmodule (/*AUTOARG*/
// Outputs
lower_out,
// Inputs
lower_inb, lower_ina
);
/*AUTOINOUTMODULE("inst")*/
// Beginning of automatic in/out/inouts (from specific module)
output lower_out;
input lower_inb;
input lower_ina;
// End of automatics
// Beginning of automatic in/out/inouts (from specific module)
wire lower_out = lower_ina | lower_inb;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutmodule_iface.v 0000664 0000000 0000000 00000000240 13022141775 0023330 0 ustar 00root root 0000000 0000000 // bug721
module my_core
(
/*AUTOINOUTMODULE("autoinoutmodule_iface_sub")*/
/*AUTOINOUT*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
/*AUTOWIRE*/
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutmodule_iface_sub.v 0000664 0000000 0000000 00000000117 13022141775 0024204 0 ustar 00root root 0000000 0000000 module autoinoutmodule_iface_sub
(my_svi.master my_svi_port,
);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutmodule_ign.v 0000664 0000000 0000000 00000000214 13022141775 0023037 0 ustar 00root root 0000000 0000000 module autoinoutmodule (/*AUTOARG*/);
/*AUTOINOUTMODULE("inst","\(ina\|out\)","","ina")*/
wire lower_out = lower_ina;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutmodule_re2.v 0000664 0000000 0000000 00000000264 13022141775 0022757 0 ustar 00root root 0000000 0000000 module autoinoutmodule_re2 (/*AUTOARG*/);
/*AUTOINOUTMODULE("inst","","input.*")*/
/*AUTOINOUTMODULE("inst","","output.*")*/
wire lower_out = lower_ina;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutmodule_regexp.v 0000664 0000000 0000000 00000000203 13022141775 0023552 0 ustar 00root root 0000000 0000000 module autoinoutmodule (/*AUTOARG*/);
/*AUTOINOUTMODULE("inst","\(ina\|out\)")*/
wire lower_out = lower_ina;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutmodule_v2k.v 0000664 0000000 0000000 00000000170 13022141775 0022765 0 ustar 00root root 0000000 0000000 module autoinoutmodule (
/*AUTOINOUTMODULE("inst")*/
);
wire lower_out = lower_ina | lower_inb;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinoutparam.v 0000664 0000000 0000000 00000000170 13022141775 0022016 0 ustar 00root root 0000000 0000000 module autoinoutparam (/*AUTOARG*/);
/*AUTOINOUTPARAM("inst","param1")*/
/*AUTOINOUTPARAM("inst")*/
endmodule
verilog-mode-20161124.fd230e6/tests/autoinput_array_bug294.v 0000664 0000000 0000000 00000000673 13022141775 0023300 0 ustar 00root root 0000000 0000000 module mod1(input logic [1:0] reg1[4],
input logic reg2[5][6],
input logic [1:0] [3:0] [2:0] reg4);
endmodule
module mod2(output logic [1:0] reg1[4],
output logic [1:0] [3:0] [2:0] reg4);
endmodule
module dut (
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
/*AUTOWIRE*/
mod1 foo_i(/*AUTOINST*/);
/* drv_i AUTO_TEMPLATE (.reg1(reg1[]), );*/
mod2 drv_i(/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinput_asharma.v 0000664 0000000 0000000 00000001206 13022141775 0022473 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOARG*/
// Outputs
lower_out,
// Inputs
lower_ina
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input lower_ina; // To inst of inst.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output lower_out; // From inst of inst.v
// End of automatics
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
inst inst (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
// Inputs
.lower_inb (1'b1), // Templated
.lower_ina (lower_ina));
endmodule
verilog-mode-20161124.fd230e6/tests/autoinput_asharma_v2k.v 0000664 0000000 0000000 00000000237 13022141775 0023260 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
inst inst (/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinput_concat_ignore.v 0000664 0000000 0000000 00000001473 13022141775 0023677 0 ustar 00root root 0000000 0000000 module xyz (/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a ({1'b0, signal_f}),
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/);
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d ({1'b1, signal_c}),
.signal_e ({2'b11, signal_e}));
*/
def u_def
(/*AUTOINST*/);
endmodule // xyz
module abc (/*AUTOARG*/);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/);
input [1:0] signal_d;
input [2:0] signal_e;
output signal_f;
endmodule // def
// Local Variables:
// verilog-auto-ignore-concat: t
// End:
verilog-mode-20161124.fd230e6/tests/autoinput_concat_lau.v 0000664 0000000 0000000 00000000520 13022141775 0023165 0 ustar 00root root 0000000 0000000 module sub1 (/*AUTOARG*/);
input [3:0] bus1;
inout [3:0] busout;
wire busout = bus1;
endmodule
module autoinput_concat_lau
(
/*AUTOINPUT*/
/*AUTOINOUT*/
);
/* sub1 AUTO_TEMPLATE (
.busout ({2'b0,fooout[1:0]}),
.bus1 ({2'b0,~foo[1:0]}),
);
*/
sub1 sub1 (/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinput_concat_lau2.v 0000664 0000000 0000000 00000001375 13022141775 0023260 0 ustar 00root root 0000000 0000000 module xyz (/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a ({1'b0, signal_f}),
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/);
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d ({1'b1, signal_c}),
.signal_e ({2'b11, signal_e}));
*/
def u_def
(/*AUTOINST*/);
endmodule // xyz
module abc (/*AUTOARG*/);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/);
input [1:0] signal_d;
input [2:0] signal_e;
output signal_f;
endmodule // def
verilog-mode-20161124.fd230e6/tests/autoinput_none.v 0000664 0000000 0000000 00000001203 13022141775 0022013 0 ustar 00root root 0000000 0000000 // Julian Gorfajn
`default_nettype none
module top
(
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output wire o, // From sub of Sub.v
// End of automatics
// Beginning of automatic outputs (from unused autoinst outputs)
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input wire i // To sub of Sub.v
// End of automatics
);
Sub sub (/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.i (i));
endmodule
module Sub (input i, output o);
endmodule
// Local Variables:
// verilog-auto-declare-nettype: "wire"
// End:
verilog-mode-20161124.fd230e6/tests/autoinput_paren.v 0000664 0000000 0000000 00000000266 13022141775 0022171 0 ustar 00root root 0000000 0000000 module foo (/*AUTOARG*/) ;
/*AUTOINPUT("ab\(c\|d\)")*/
bar i_bar(/*AUTOINST*/);
endmodule // foo
module bar (/*AUTOARG*/) ;
input abc,abd,bca;
output aaa;
endmodule // bar
verilog-mode-20161124.fd230e6/tests/autoinsertlast_1.v 0000664 0000000 0000000 00000000347 13022141775 0022255 0 ustar 00root root 0000000 0000000 module ExampInsertLisp;
/*AUTOINSERTLAST(my-verilog-insert-hello "world")*/
endmodule
/*
Local Variables:
eval:
(defun my-verilog-insert-hello (who)
(insert (concat "initial $write(\"hello " who "\");\n")))
End:
*/
verilog-mode-20161124.fd230e6/tests/autoinst_2k_fredriksen.v 0000664 0000000 0000000 00000000441 13022141775 0023425 0 ustar 00root root 0000000 0000000 module top ();
sub sub(/*AUTOINST*/
// Outputs
.b (b[PARAM2:0]),
// Inputs
.a (a[PARAM1:0]));
endmodule // top
module sub
#(parameter PARAM1=2,
PARAM2=3,
PARAM3=6)
( input wire [PARAM1:0] a,
output reg [PARAM2:0] b
);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_ams_vorwerk.v 0000664 0000000 0000000 00000001021 13022141775 0023227 0 ustar 00root root 0000000 0000000 module autoinst_ams_vorwerk;
latch latch (/*AUTOINST*/);
endmodule
module latch (/*AUTOARG*/);
`ifdef __VAMS_ENABLE__
output (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) q;
`else
output q;
`endif
`ifdef __VAMS_ENABLE__
input (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) en;
`else
input en;
`endif
`ifdef __VAMS_ENABLE__
input (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) d;
`else
input d;
`endif
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_array.v 0000664 0000000 0000000 00000000753 13022141775 0022021 0 ustar 00root root 0000000 0000000 // bug637
module submod_a
(
//Inputs
input wire signed [15:0] serial_in,
//Outputs
output wire signed [15:0] parallel_out [0:7]
);
endmodule
module submod_b
(
//Inputs
input wire signed [15:0] parallel_out [0:7],
//Outputs
output wire signed [15:0] final_out [0:7]
);
endmodule
module top
(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
/*AUTOLOGIC*/
submod_a a_inst
(/*AUTOINST*/);
submod_b b_inst
(/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_array_braket.v 0000664 0000000 0000000 00000001427 13022141775 0023350 0 ustar 00root root 0000000 0000000 module sub(output logic [1:-1] oned,
output logic [1:-1] [2:-1] twod,
output logic [1:-1] [2:-1] [3:-3] threed);
endmodule
module dut (
);
/*AUTOWIRE*/
/* sub AUTO_TEMPLATE ();
*/
sub sub1 (/*AUTOINST*/);
/* sub AUTO_TEMPLATE (
.oned (b_oned[]),
.twod (b_twod[]),
.threed (b_threed[]));
*/
// NOTE this results in the wrong declaration for b_twod/b_threed
sub subb (/*AUTOINST*/);
/* sub AUTO_TEMPLATE (
.oned (c_oned[]),
.twod (c_twod[x][]),
.threed (c_threed[x][y][]));
*/
sub subc (/*AUTOINST*/);
/* sub AUTO_TEMPLATE (
.oned (d_oned[][]),
.twod (d_twod[][]),
.threed (d_threed[][]));
*/
sub subd (/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_atregexp.v 0000664 0000000 0000000 00000000702 13022141775 0022514 0 ustar 00root root 0000000 0000000 module ex;
/* autoinst_paramover_sub AUTO_TEMPLATE "u_\(.*\)" (
.a(inA_@[]),
.b(outA_@[]),
);*/
autoinst_paramover_sub u_foo(/*AUTOINST*/);
autoinst_paramover_sub u_bar(/*AUTOINST*/);
autoinst_paramover_sub u_baz(/*AUTOINST*/);
/* autoinst_paramover_sub AUTO_TEMPLATE (
.a(inN_@[]),
.b(outN_@[]),
);*/
autoinst_paramover_sub u_0_2(/*AUTOINST*/);
autoinst_paramover_sub u_1_3(/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_belkind_concat.v 0000664 0000000 0000000 00000000656 13022141775 0023644 0 ustar 00root root 0000000 0000000 module aaa (/*AUTOARG*/);
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
wire u0, u1, z0, z1;
/*
bbb AUTO_TEMPLATE (
.xo0 ({(u0), y0}),
.xo1 ({y1, (u1)}),
.xi0 ({(z0), y2}),
.xi1 ({y3, (z1)}),
);
*/
bbb bbb (/*AUTOINST*/);
endmodule // aaa
module bbb (/*AUTOARG*/);
output [1:0] xo0, xo1;
input [1:0] xi0, xi1;
/*AUTOTIEOFF*/
endmodule // bbb
verilog-mode-20161124.fd230e6/tests/autoinst_bits_lba.v 0000664 0000000 0000000 00000001004 13022141775 0022450 0 ustar 00root root 0000000 0000000 module lba
(/*AUTOnotARG*/
// Outputs
);
/* autoinst_bits_lba_gi AUTO_TEMPLATE (
.WWCmdI (WWCmdI[]));
*/
autoinst_bits_lba_gi gi (/*AUTOINST*/
// Outputs
.WWCmdI (WWCmdI[8:0]), // Templated
.WWADI (WWADI[31:0]),
// Inouts
.WWADB (WWADB[31:0]),
.WWCmdB (WWCmdB[8:0]),
// Inputs
.CLK (CLK),
.WWADoe (WWADoe),
.WWCoe (WWCoe),
.WWCmdIfOE (WWCmdIfOE[8:0]),
.WWADHold (WWADHold),
.iWWADO (iWWADO[31:0]));
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_bits_lba_gi.v 0000664 0000000 0000000 00000006321 13022141775 0023136 0 ustar 00root root 0000000 0000000 module autoinst_bits_lba_gi
// ==xxxxxxx==
// xxxxxxxxx 1997-1998, xxxxx xxx.
// xxx xxxxxx xxxxxxxx
// ****************************************************************** /
// ****************************************************************** /
// xxxxx, xxxxxxxxxxxx
// xxxxxxx: xxx-4080
// xxxxxx: xxx xxxxxxx
// xxxxx: xxxxxxx 16, 1998
// ******************************************************************* /
// ******************************************************************* /
// xxxx xxxx: xxx_xx.x
// xxxxxxxx xxxxxxx:
// $xxx: xxx_xx.x,x $
// xxxxxxxx 1.3 1998/03/06 00:27:00 xxx
// -- xxxxx xxxxxxx xx xx.xxxx xxx xxxxxxxx xxxxxxx.
// -- xxxx xxxxxxxxxxxxx xx xx xxxxxxxxxxx xx xx.x xxx xx.x xx xxxxxxx xxx xxxxxxxxxxx.
// -- xxxx xxxxx xxx xxxxxxxxxxxxx xxx1'x (xxxxxxx xx xxxxx) xx xx.x xxx xxxx xxxxxx
// xxxxxxxxxx.
// -- xxxxx xxxxxxxxxx xxxxxxxx xx xxx xx xxxxxxxxxxx xxx xxxx xxxxxx xxxxxxxxxxxx xxxx.
// -- xx xxx xxxxxxxxx xxx xxxxxx xx xx xx xxx xxxxx xxxxx xx xxxx xxxxxxxx xx xxxx.
// -- xx xx xxxx xxxxxxx xxx xxx xxxx xxxxxx xxxxxx (xxx xxx xxxx) xxx xxx xxxx/xxxx
// xxxxxxxxxx xxxx xxxxxxx.
//
// xxxxxxxx 1.2 1998/03/04 18:58:55 xxx
// xxxxx xxxxxxxxx xxx-xx xxxxxxx xxxxxxx xx xxxx xxxxx.
//
// xxxxxxxx 1.1 1998/02/23 19:31:52 xxx
// xxxxx xxxxx xxxxxx xxx xxxx xxxxx xxxxx xxxxxxxxxx.
//
// ---------------------------------------------------------------
//
// xxxxxxx xxx xxxxxxxxx xxx xxxxx xxx xxxxxxx xxx
//
// xxxx xxxxxx xxxxx xxx xxxxx xxxxxx xxxxxxx/xxxx xxx xxxx
// xx.x xxx xx xx xxxxxxxxx xxxx xxxx.x xxxxxx xx
// xxxx xxx xxxxxxx xx xxx. xx xxxx xxxxates the
// bidir Foo Bus into a chip input for use by li.v
//
// This module also isolates for input to lbsm.v, and drives
// (if so indicated by lbsm.v) the bidir Fooileo Cmd bus.
//
//
(
CLK,
WWADoe,
WWCoe,
WWCmdIfOE,
WWADHold,
iWWADO,
WWCmdI,
WWADI,
WWADB,
WWCmdB
);
/////////////////////////////////////////////////////////////////////
// inputs
input CLK; // LBA clk
// inputs from lbsm.v
input WWADoe; // FooBus Addr/Data OE
input WWCoe; // FooBus Cmd OE
input [8:0] WWCmdIfOE; // FooBus Cmd if enabled
input WWADHold; // FooBus Addr hold
// inputs from li.v
input [31:0] iWWADO; // FooBus Address/Data out next cycle
/////////////////////////////////////////////////////////////////////
// outputs
// outputs to lbsm.v
output [8:0] WWCmdI; // FooBus Command in
// outputs to li.v
output [31:0] WWADI; // FooBus Address/Data in
/////////////////////////////////////////////////////////////////////
// bidirs
// bidirs to/from off-chip
inout [31:0] WWADB; // bidir FooBus addr/data
inout [8:0] WWCmdB; // bidir FooBus command
/////////////////////////////////////////////////////////////////////
// reg's for outputs (some flops, some not)
/////////////////////////////////////////////////////////////////////
// other flops
reg [31:0] WWADIfOE; // FooBus Addr/Data Out if enabled
endmodule
// Local Variables:
// eval:(if (fboundp `verilog-enable-indentation) (verilog-enable-indentation))
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_brucet.v 0000664 0000000 0000000 00000001031 13022141775 0022155 0 ustar 00root root 0000000 0000000 module io1_sub(/*AUTOARG*/
// Outputs
x, y, z,
// Inputs
a, b
);
input a;
input b;
output x;
output y;
output z;
andcell c0 (
.c (x),
/*AUTOINST*/
// Inputs
.a (a),
.b (b));
orcell c0 (
.c (y),
/*AUTOINST*/
// Inputs
.a (a),
.b (b));
nandcell c0 (
.c (z),
/*AUTOINST*/
// Inputs
.a (a),
.b (b));
endmodule
// Local Variables:
// verilog-library-files:("autoinst_brucet_library.v")
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_brucet_library.v 0000664 0000000 0000000 00000000657 13022141775 0023716 0 ustar 00root root 0000000 0000000 module andcell (/*AUTOARG*/
// Outputs
c,
// Inputs
a, b
);
input a;
input b;
output c;
wire c = a&b;
endmodule
module nandcell (/*AUTOARG*/
// Outputs
c,
// Inputs
a, b
);
input a;
input b;
output c;
wire c = !(a&b);
endmodule
module orcell (/*AUTOARG*/
// Outputs
c,
// Inputs
a, b
);
input a;
input b;
output c;
wire c = a|b;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_bug373.v 0000664 0000000 0000000 00000002467 13022141775 0021721 0 ustar 00root root 0000000 0000000 typedef struct packed {
logic [7:0] data;
logic wr_ena;
} mystruct_s;
module submod
(input logic a_port,
input logic [4:0] b_bus,
input mystruct_s single_struct_is_fine,
input mystruct_s [2:0] array_of_struct_is_not,
output logic status);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire status = 1'h0;
// End of automatics
endmodule // submod
module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic status; // From submod0 of submod.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
logic a_port; // To submod0 of submod.v
mystruct_s [2:0] array_of_struct_is_not; // To submod0 of submod.v
logic [4:0] b_bus; // To submod0 of submod.v
mystruct_s single_struct_is_fine; // To submod0 of submod.v
// End of automatics
submod submod0
(/*AUTOINST*/
// Outputs
.status (status),
// Inputs
.a_port (a_port),
.b_bus (b_bus[4:0]),
.single_struct_is_fine (single_struct_is_fine),
.array_of_struct_is_not (array_of_struct_is_not[2:0]));
endmodule // top
// Local Variables:
// verilog-typedef-regexp: "_s$"
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_case_chakradhara.v 0000664 0000000 0000000 00000000461 13022141775 0024123 0 ustar 00root root 0000000 0000000 module foo();
/*bar AUTO_TEMPLATE (
.pme\(.*\)_o (pme\1[]),
.PME\(.*\)_o (pMe\1[]),
.pme\(.*\)_o (pme\1[]),
);
*/
bar bar
(/*AUTOINST*/);
endmodule
module bar
(/*AUTOARG*/);
input PME_o;
input pme_o;
input pmE_o;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_casefold_hou.v 0000664 0000000 0000000 00000001426 13022141775 0023334 0 ustar 00root root 0000000 0000000 typedef struct packed {
logic a,b,c;
} tTest;
module test
(
input clk,rst
);
wire [7:0] data_tm;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
tTest q; // From foo of foo.v
// End of automatics
/* foo AUTO_TEMPLATE (
.tm (data_tm),
);
*/
foo foo (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.clk (clk),
.rst (rst),
.tm (data_tm)); // Templated
/*AUTO_LISP(setq verilog-typedef-regexp "^t[A-Z]")*/
endmodule
module foo
(
input clk,
input rst,
input [7:0] tm,
output tTest q
);
endmodule
// Local Variables:
// verilog-case-fold:nil
// verilog-library-directories:(".")
// verilog-typedef-regexp:"^t[A-Z]"
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_cavanaugh_pull.v 0000664 0000000 0000000 00000003155 13022141775 0023673 0 ustar 00root root 0000000 0000000
module fifo(/*AUTOARG*/);
input clk;
input rst_n;
output fifo_full_w;
input enqueue_w;
input [(DATA_WIDTH-1):0] data_in_w;
output data_valid_r;
input dequeue_w;
input [1:0] full_threshold;
output [(DATA_WIDTH-1):0] rdata_r;
endmodule
module req (p_clk, carb_rst_rnp, req_rp, len_rxp, deq_req, deq_len, deq_val);
input p_clk;
input carb_rst_rnp;
input [4:0] len_rxp;
input req_rp;
input deq_req;
output [4:0] deq_len;
output deq_val;
reg [5:0] fifo_entry1_rp;
reg [5:0] fifo_entry2_rp;
reg [4:0] deq_len;
reg deq_val;
endmodule
module pull( /*AUTOARG*/);
input clk;
input rst_rnpha;
input [4:0] lenar_rxp;
input rem_rpd;
input d_rews;
output [4:0] d_len;
output d_val;
/* req AUTO_TEMPLATE "\(g[a-z0-9]+\|g.*[0-9]\)" (
.p_clk (my_clk_@),
.len_rxp (carb_rst_rnp_@),
.carb_rst_rnp (pull_req1));
*/
req test432_gbe5(/*AUTOINST*/);
req gbe9_vreos(/*AUTOINST*/);
/* fifo AUTO_TEMPLATE "gbe[0-9]+_\([^\_]+\)" (
.clk (@_clk),
.\(.*data.*\) (@_\1),
.\(.*\)\(full\)\(.*\) (\1@\3),
.\(en\|de\)\(.\).+ (@_\1\2));
*/
fifo #(5) gbe2_pull_req (/*AUTOINST*/);
fifo #(5)
gbe1_pull_req_fifo( /*AUTOINST*/);
endmodule // pull_arb
verilog-mode-20161124.fd230e6/tests/autoinst_ciu.v 0000664 0000000 0000000 00000000372 13022141775 0021460 0 ustar 00root root 0000000 0000000 module testmux
(
input wire [2:0] a
);
endmodule
module top_test();
/* testmux AUTO_TEMPLATE "\(.*\)$" (
.a (@_a_value[]),
);
*/
testmux foo1_1
(/*AUTOINST*/);
testmux foo1_2
(/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_clog2_bug522.v 0000664 0000000 0000000 00000000672 13022141775 0022777 0 ustar 00root root 0000000 0000000 // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by brad Dobbie.
module mod;
submod #
(.VEC_W(8),
.IDX_W($clog2(VEC_W)))
submod
(/*AUTOINST*/);
endmodule
module submod (/*AUTOARG*/);
parameter VEC_W = 32;
parameter IDX_W = $clog2(VEC_W);
input [VEC_W-1:0] vec;
output [IDX_W-1:0] idx;
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_cmtcell_msg270.v 0000664 0000000 0000000 00000000324 13022141775 0023417 0 ustar 00root root 0000000 0000000 module ex;
subwidth u_a2 // commented
(/*AUTOINST*/
// Outputs
.bus4a (bus4a[0:3]));
endmodule
module subwidth (/*AUTOARG*/
// Outputs
bus4a
);
output [0:3] bus4a;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_cmtinst_bug383.v 0000664 0000000 0000000 00000001415 13022141775 0023453 0 ustar 00root root 0000000 0000000 module t;
/*fifo_s AUTO_TEMPLATE (
.ignored_signal (1'b1),
.out_signal (NC),
.out_bus (out_bus[]),
);
*/
fifo_s data_fifo (
//fifo_s data_fifo (
// Inputs
.clk (fifo_clk),
/*AUTOINST*/);
/*fifo_s AUTO_TEMPLATE (
.ignored_signal (1'b1),
.out_signal (NC),
.out_bus (out_bus[]),
);
*/
//fifo_s data_fifo (
fifo_s data_fifo (
// Inputs
.clk (fifo_clk),
/*AUTOINST*/);
endmodule
module fifo_s;
input ignored_signal;
input reset;
output [31:0] out_bus;
output out_signal;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_cmtparen_tennant.sv 0000664 0000000 0000000 00000007731 13022141775 0024431 0 ustar 00root root 0000000 0000000 typedef node logic;
module top
#(parameter COLS = 4
)
( input logic clk,
input logic rstb,
input logic [COLS-1:0] ival,
input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
input logic [COLS-1:0][7:0] isig1,
input logic [COLS-1:0][6:0] isig2,
input logic [COLS-1:0][5:0] isig3,
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input idata_some_extra_sig_lengt,// To isub1 of sub1.v, ...
input isig, // To isub1 of sub1.v, ...
// End of automatics
output logic [COLS-1:0] oval,
output logic [COLS-1:0][1:0] odata,
output logic [COLS-1:0] s3_oval,
output logic [COLS-1:0][1:0] s3_odata,
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output s1_odat, // From isub1 of sub1.v
output s3_odat // From isub3 of sub3.v
// End of automatics
);
logic [COLS-1:0][1:0] s1_odata; // From isub1 of sub1.v
logic [COLS-1:0] s1_oval; // From isub1 of sub1.v
/*AUTOWIRE*/
/* sub2 AUTO_TEMPLATE(
.idata_some_extra_sig_length ( s1_odata),
.ival ( s1_oval),
);*/
sub2 isub2 (/*AUTOINST*/
// Outputs
.oval (oval[COLS-1:0]),
.odata (odata/*[COLS-1:0][1:0]*/),
// Inputs
.clk (clk),
.rstb (rstb),
.ival ( s1_oval), // Templated
.idata_some_extra_sig_length( s1_odata)); // Templated
genvar column;
/* sub1 AUTO_TEMPLATE(
.i.* ( @"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
.o.* ( s1_@"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
);*/
/* sub3 AUTO_TEMPLATE(
.i.* ( @"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
.o.* ( s3_@"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
);*/
generate for(column=0;column<4;column++) begin : COLUMN
sub1 isub1(/*AUTOINST*/
// Outputs
.oval ( s1_oval[column] ), // Templated
.odata ( s1_odata[column] /* [1:0] */), // Templated
// Inputs
.clk (clk),
.rstb (rstb),
.ival ( ival[column] ), // Templated
.idata_some_extra_sig_length( idata_some_extra_sig_length[column] /* [1:0] */), // Templated
.isig1 ( isig1[column] /* [7:0] */), // Templated
.isig2 ( isig2[column] /* [6:0] */), // Templated
.isig3 ( isig3[column] /* [5:0] */)); // Templated
sub3 isub3(/*AUTOINST*/
// Outputs
.oval ( s3_oval[column] ), // Templated
.odata ( s3_odata[column] /* [1:0] */), // Templated
// Inputs
.clk (clk),
.rstb (rstb),
.ival ( ival[column] ), // Templated
.idata_some_extra_sig_length( idata_some_extra_sig_length[column] /* [1:0] */)); // Templated
end endgenerate
endmodule // top
module sub1
( input logic clk,
input logic rstb,
input logic ival,
input logic [1:0] idata_some_extra_sig_length,
input logic [7:0] isig1,
input logic [6:0] isig2,
input logic [5:0] isig3,
output logic oval,
output logic [1:0] odata
);
endmodule // sub
module sub3
( input logic clk,
input logic rstb,
input logic ival,
input logic [1:0] idata_some_extra_sig_length,
output logic oval,
output logic [1:0] odata
);
endmodule // sub
module sub2
#(parameter COLS = 4
)
( input logic clk,
input logic rstb,
input logic [COLS-1:0] ival,
input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
output logic [COLS-1:0] oval,
output logic [COLS-1:0] [1:0] odata
);
endmodule // sub
// Local Variables:
// verilog-typedef-regexp:"\\(^t_\\)\\|\\(^node$\\)\\|\\(_s$\\)\\|\\(_t$\\)"
// verilog-library-directories:("." )
// verilog-library-extensions:(".v" ".sv" ".h" ".vr" ".vm")
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_crawford_array.v 0000664 0000000 0000000 00000004073 13022141775 0023707 0 ustar 00root root 0000000 0000000 `define AUTO_NBR_A_INST 2
module autoinst_crawford_array(/*AUTOARG*/
// Outputs
a_valid, a_data,
// Inputs
a_ready, clk, rst_n
);
// a interface
output [`AUTO_NBR_A_INST*1-1:0] a_valid;
output [`AUTO_NBR_A_INST*8-1:0] a_data;
input [`AUTO_NBR_A_INST*1-1:0] a_ready;
// clock interface
input clk;
input rst_n;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
// non-arrayed example
autoinst_crawford_array_a auto_a_0
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
autoinst_crawford_array_a auto_a_1
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
// Arrayed instances
// AUTOINST does not work for this one :-(
// Note it is tricky because I want clk and rst_n to fanout to both instances,
// but I want the valid signals to be discreatly tied to each submodule.
//autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
// (/*XXXAUTOINST*/
// // Outputs
// .a_valid (a_valid[1:0]),
// .a_data (a_data[15:0]),
// // Inputs
// .a_ready (a_ready[1:0]),
// .clk (clk),
// .rst_n (rst_n));
autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
autoinst_crawford_array_a #(.a(a),b) par [`AUTO_NBR_A_INST-1:0]
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_crawford_array_a.v 0000664 0000000 0000000 00000001446 13022141775 0024210 0 ustar 00root root 0000000 0000000 `define auto_trq #1 // clock to q delay
`define auto_tcq #1 // reset to q delay
module autoinst_crawford_array_a(/*AUTOARG*/
// Outputs
a_valid, a_data,
// Inputs
a_ready, clk, rst_n
);
// a interface
output a_valid;
output [7:0] a_data;
input a_ready;
// clock interface
input clk;
input rst_n;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] a_data;
reg a_valid;
// End of automatics
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
a_valid <= `auto_trq 0;
a_data <= `auto_trq 0;
end
else begin
if(a_ready) begin
a_valid <= `auto_tcq 1;
a_data <= `auto_tcq 8'hcc;
end
end
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_dedefine.v 0000664 0000000 0000000 00000000626 13022141775 0022445 0 ustar 00root root 0000000 0000000 `define foo 6
`define bar 0
module autoinst_dedefine;
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/* bar AUTO_TEMPLATE (
.\(.*\) (@"(concat vl-name (verilog-symbol-detick-text vl-bits))"),
); */
bar sub
(/*AUTOINST*/);
endmodule
module bar;
output onewide;
output [3:1] fourwide;
output [`foo-1:`bar] varwide;
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_ding.v 0000664 0000000 0000000 00000001600 13022141775 0021614 0 ustar 00root root 0000000 0000000 module AA(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
input wire clock,
input wire reset,
input wire test_enable,
input wire afe_ctrl,
input wire cpu_wr,
input wire [4:0] cpu_addr,
input wire [7:0] cpu_wdata,
output wire [7:0] core_data,
output wire core_code_error,
output wire core_code_idle,
output wire [7:0] cpu_rdata
);
endmodule
module BB(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
input wire clock,
input wire reset,
input wire test_enable,
input wire core_code_idle,
input wire core_code_error,
input wire [7:0] core_data,
input wire [8:0] mbist_done,
input wire [8:0] mbist_fail,
output wire mbist_rst,
output reg mbist_test
);
endmodule
module TOP(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
AA AA_U(/*AUTOINST*/);
BB BB_U(/*AUTOINST*/);
// Local Variables:
// verilog-library-directories:(".")
// End:
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_for_myers.v 0000664 0000000 0000000 00000003107 13022141775 0022704 0 ustar 00root root 0000000 0000000 module InstMod ( ins, outs );
output [INWIDTH-1:0] ins;
output [OUTWIDTH-1:0] outs;
endmodule
module test_top;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [n*INWIDTH +: INWIDTH] ins; // From instName of InstMod.v
wire [n*INWIDTH +: INWIDTH] ins2; // From instName2 of InstMod.v
wire [n*INWIDTH +: INWIDTH] ins3; // From instName3 of InstMod.v, ..., Couldn't Merge
wire [n*OUTWIDTH +: OUTWIDTH] outs; // From instName of InstMod.v
wire [n*OUTWIDTH +: OUTWIDTH] outs2; // From instName2 of InstMod.v
wire [4*OUTWIDTH-1 : 0] outs3; // From instName3 of InstMod.v, ..., Couldn't Merge
// End of automatics
genvar i;
generate
for (i=0; i<4; i=i+1) begin
/*AUTO_LISP(setq vh-n 4)*/
/* InstMod AUTO_TEMPLATE
(.ins (ins [n*INWIDTH +: INWIDTH]),
.outs (outs[n*OUTWIDTH +: OUTWIDTH])); */
InstMod instName (/*AUTOINST*/
// Outputs
.ins (ins [n*INWIDTH +: INWIDTH]), // Templated
.outs (outs[n*OUTWIDTH +: OUTWIDTH])); // Templated
InstMod instName2
(// Inputs
.ins (ins2 [n*INWIDTH +: INWIDTH]),
// Outputs
.outs (outs2[n*OUTWIDTH +: OUTWIDTH])
/*AUTOINST*/);
// This works but is ugly
InstMod instName3
(// Inputs
.ins (ins3 [n*INWIDTH +: INWIDTH]),
// Outputs
.outs (outs3[n*OUTWIDTH +: OUTWIDTH])
`ifdef NEVER
// Inouts
.ins (ins3 [4*INWIDTH-1 : 0]),
.outs (outs3[4*OUTWIDTH-1 : 0])
`endif
/*AUTOINST*/);
end
endgenerate
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_func.v 0000664 0000000 0000000 00000004134 13022141775 0021633 0 ustar 00root root 0000000 0000000 module autoinst_func;
/*AUTO_LISP(defun testfunc (sig bits) (let ((result "{"))
(setq result (concat result sig "[0" bits "]"))
(concat result "}")))*/
/* autoinst_wildcard_sub AUTO_TEMPLATE (
.sd0_adrs@ (myport@"(substring \\"\1\\" 0 1)"),
.\(.*\) (@"(testfunc vl-name vl-bits)"),
); */
autoinst_wildcard_sub sub0
(/*AUTOINST*/
// Inouts
.sd0_adrs0 (myport0), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs1 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs10 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs11 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs2 (myport2), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs3 (myport3), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs4 (myport4), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs5 (myport5), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs6 (myport6), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs7 (myport7), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs8 (myport8), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs9 (myport9), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_ba0 ({sd0_ba0[0]}), // Templated LHS: ^\(.*\)$
.sd0_ba1 ({sd0_ba1[0]}), // Templated LHS: ^\(.*\)$
.sd0_clk ({sd0_clk[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm0_l ({sd0_dqm0_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm1_l ({sd0_dqm1_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm2_l ({sd0_dqm2_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm3_l ({sd0_dqm3_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm4_l ({sd0_dqm4_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm5_l ({sd0_dqm5_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm6_l ({sd0_dqm6_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm7_l ({sd0_dqm7_l[0]}), // Templated LHS: ^\(.*\)$
.sd_ras_ ({sd_ras_[0]})); // Templated LHS: ^\(.*\)$
endmodule
// Local Variables:
// verilog-auto-inst-template-numbers: lhs
// verilog-auto-inst-sort: t
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_gate.v 0000664 0000000 0000000 00000001012 13022141775 0021610 0 ustar 00root root 0000000 0000000 //bug284
module wrapper
(
/*AUTOOUTPUT*/
/*AUTOINPUT*/
);
//--------------------------------------------------------------------------
// Note input/output comments aren't needed, and multiple signals
// per line are ok
or u_or [31:0]
(o[31:0], i0[31:0], i1[31:0], i2[31:0],
// Inputs,
i3[31:0]
/*AUTOINST*/);
// bug676
buf # 1 mybuf[1:0]
(bout[1:0],
// Inputs,
bin[1:0]
/*AUTOINST*/);
//--------------------------------------------------------------------------
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_genvar.v 0000664 0000000 0000000 00000000731 13022141775 0022161 0 ustar 00root root 0000000 0000000 module AA(
input wire clock,
input wire reset,
input wire test_enable,
input wire afe_ctrl,
input wire cpu_wr,
input wire [4:0] cpu_addr,
input wire [7:0] cpu_wdata,
output wire [7:0] core_data,
output wire core_code_error,
output wire core_code_idle,
output wire [7:0] cpu_rdata
);
endmodule
module TOP(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
genvar x;
AA AA_U(
// Inputs
.test_enable (x),
/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_iface270_sub.v 0000664 0000000 0000000 00000000356 13022141775 0023053 0 ustar 00root root 0000000 0000000 // See http://www.veripool.org/issues/show/270
interface autoinst_iface270_sub;
logic a;
logic b;
modport master_mp(input a, output b);
modport slave_mp(output a, input b);
modport monitor (input a, input b);
endinterface
verilog-mode-20161124.fd230e6/tests/autoinst_iface270_top.v 0000664 0000000 0000000 00000000340 13022141775 0023055 0 ustar 00root root 0000000 0000000 // See http://www.veripool.org/issues/show/270
module top;
/*AUTOWIRE*/
autoinst_iface270_sub inst_if (/*AUTOINST*/);
ifio sub (/*AUTOINST*/);
endmodule
module ifio
(autoinst_iface270_sub inst_if);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_iface270_top_bug429.v 0000664 0000000 0000000 00000000450 13022141775 0024153 0 ustar 00root root 0000000 0000000 // See http://www.veripool.org/issues/show/429
module top;
/*AUTOWIRE*/
autoinst_iface270_sub inst_if (/*AUTOINST*/);
ifio sub (/*AUTOINST*/);
endmodule
module ifio
(autoinst_iface270_sub inst_if);
endmodule
// Local Variables:
// verilog-auto-inst-interfaced-ports: nil
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_ifdef_fredrickson_200503_sub.v 0000664 0000000 0000000 00000000350 13022141775 0026024 0 ustar 00root root 0000000 0000000 module autoinst_ifdef_fredrickson_200503_sub
(input a,
`ifdef TEST
input c,
output wire d,
`endif
output wire b
);
assign b = a;
`ifdef TEST
assign d = c;
`endif
endmodule // define_sub
verilog-mode-20161124.fd230e6/tests/autoinst_ifdef_fredrickson_200503_top.v 0000664 0000000 0000000 00000000360 13022141775 0026036 0 ustar 00root root 0000000 0000000 module autoinst_ifdef_fredrickson_200503_top();
autoinst_ifdef_fredrickson_200503_sub sub
(/*AUTOINST*/
// Outputs
.d (d),
.b (b),
// Inputs
.a (a),
.c (c));
endmodule // define_top
verilog-mode-20161124.fd230e6/tests/autoinst_import.v 0000664 0000000 0000000 00000000736 13022141775 0022216 0 ustar 00root root 0000000 0000000 //bug709
module InstModule
(input clk,
svi.master svi_modport,
svi svi_nomodport);
endmodule // InstModule
module InstModule1 import mdp_pkg::*;
(input clk,
svi.master svi_modport,
svi svi_nomodport);
endmodule
module top;
InstModule instName
(/*AUTOINST*/);
InstModule1 instName1
(/*AUTOINST*/);
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v" ".sv")
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_instname_all.v 0000664 0000000 0000000 00000000612 13022141775 0023343 0 ustar 00root root 0000000 0000000 module ex;
/* autoinst_paramover_sub AUTO_TEMPLATE (
.\(.*\)(@"vl-cell-name"_\1),
);*/
autoinst_paramover_sub u_a0(/*AUTOINST*/
// Inouts
.a (u_a0_a), // Templated
.b (u_a0_b)); // Templated
autoinst_paramover_sub u_a1(/*AUTOINST*/
// Inouts
.a (u_a1_a), // Templated
.b (u_a1_b)); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_instname_carlh.v 0000664 0000000 0000000 00000000716 13022141775 0023671 0 ustar 00root root 0000000 0000000 module ex;
/* autoinst_paramover_sub AUTO_TEMPLATE (
.a(@"vl-cell-name"_in[]),
.b(@"(substring inst 2)"_out[]),
);*/
autoinst_paramover_sub u_a0(/*AUTOINST*/
// Inouts
.a (u_a0_in[bitsa:0]), // Templated
.b (a0_out[bitsb:0])); // Templated
autoinst_paramover_sub u_a1(/*AUTOINST*/
// Inouts
.a (u_a1_in[bitsa:0]), // Templated
.b (a1_out[bitsb:0])); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_interface.v 0000664 0000000 0000000 00000002415 13022141775 0022640 0 ustar 00root root 0000000 0000000 // See bug75
module autoinst_interface
(/*AUTOINOUTMODULE("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
logic [7:0] count,
logic clk,
logic reset,
logic start,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module autoinst_interface
(/*AUTOINOUTCOMP("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
logic clk,
logic reset,
logic start,
logic [7:0] count,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [7:0] count; // From submod0 of autoinst_interface_sub.v
// End of automatics
my_svi my_svi_noport_upper_decl ();
autoinst_interface_sub submod0 (/*AUTOINST*/
// Interfaces
.my_svi_port (my_svi_port.master),
.my_svi_noport (my_svi_noport),
.my_svi_noport_upper_decl(my_svi_noport_upper_decl),
// Outputs
.count (count[7:0]),
// Inputs
.clk (clk),
.reset (reset),
.start (start));
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_interface_bug320.v 0000664 0000000 0000000 00000000323 13022141775 0023716 0 ustar 00root root 0000000 0000000 // See bug320
interface intf1;
logic a;
logic b;
modport mp1 (input a, output b);
endinterface
interface intf2 (intf1.mp1 c);
logic e;
endinterface
module top;
intf1 c(.*);
intf2 f(.*);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_interface_star.v 0000664 0000000 0000000 00000002116 13022141775 0023667 0 ustar 00root root 0000000 0000000 // See bug75
module autoinst_interface
(/*AUTOINOUTMODULE("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output [7:0] count,
input clk,
input reset,
input start,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module autoinst_interface
(/*AUTOINOUTCOMP("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output clk,
output reset,
output start,
input [7:0] count,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module top;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] count; // From submod0 of autoinst_interface_sub.v
my_svi my_svi_noport; // To/From submod0 of autoinst_interface_sub.v
my_svi my_svi_noport_upper_decl;// To/From submod0 of autoinst_interface_sub.v
// End of automatics
autoinst_interface_sub submod0 (.*);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_interface_sub.v 0000664 0000000 0000000 00000000661 13022141775 0023512 0 ustar 00root root 0000000 0000000 interface my_svi;
logic enable;
logic error;
logic [7:0] count2;
modport master (
input enable,
output error,
output count2);
endinterface
module autoinst_interface_sub
(input wire clk,
input wire reset,
input wire start,
output reg [7:0] count,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_johnson.v 0000664 0000000 0000000 00000002775 13022141775 0022367 0 ustar 00root root 0000000 0000000 module bfm (/*AUTOARG*/
// Inputs
name
);
input [8*5:1] name ;
endmodule
module tb;
// -------------------------------------------------------------------------
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
// -------------------------------------------------------------------------
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
// -------------------------------------------------------------------------
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
// -------------------------------------------------------------------------
/* AUTO_CONSTANT ( "name0" "name1" "name2" ) */
// -------------------------------------------------------------------------
/* bfm AUTO_TEMPLATE (
// Inputs
.name ("name@"));
*/
// -------------------------------------------------------------------------
bfm bmf0 (/*AUTOINST*/
// Inputs
.name ("name0")); // Templated
// -------------------------------------------------------------------------
bfm bmf1 (/*AUTOINST*/
// Inputs
.name ("name1")); // Templated
// -------------------------------------------------------------------------
bfm bmf2 (/*AUTOINST*/
// Inputs
.name ("name2")); // Templated
// -------------------------------------------------------------------------
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_lopaz.v 0000664 0000000 0000000 00000002241 13022141775 0022022 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOARG*/);
wire [42:0] bscan_data; // boundary scan stitch
parameter bscan_count = 0;
assign bscan_data[0] = bscan_in;
/*
* Emacs template to auto instaniate MD[31:0] pads
*/
/*
autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@]),
.pin_in({SDRAM_DQ_in[@],SDRAM_DQ_in[@]}),
.pin_out(SDRAM_DQ_out[@]),
.pin_outen(SDRAM_DQ_outen),
.sdrmode(SDRAM_single_rate),
.hw_enb(SDRAM_upper_word_enb),
.ff_rptr(SDRAM_ddr_inff_sel),
.ff_wptr(ddr_inff_enbH),
.clk(data_strobeH),
.bscan_so(bscan_data[@ + 1]),
.bscan_si(bscan_data[@]),
.bscan_shift(BScanShift),
.bscan_clock(BScanClock),
.bscan_mode(BScanMode),
.bscan_update(BScanUpdate),
.bscan_outen(SDRAM_DQ_bscan_outen),
);
*/
autoinst_lopaz_srpad MD31_pad (/*AUTOINST*/);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 1)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 2)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_lopaz_srpad.v 0000664 0000000 0000000 00000000437 13022141775 0023220 0 ustar 00root root 0000000 0000000 module autoinst_lopaz_srpad (/*AUTOARG*/
// Outputs
pin_in,
// Inouts
pin,
// Inputs
clk, pin_out, pin_outen
);
parameter w = 1;
input clk;
inout [w-1:0] pin;
output [2*w-1:0] pin_in;
input [w-1:0] pin_out;
input pin_outen;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_ma_io_prefix.v 0000664 0000000 0000000 00000005176 13022141775 0023350 0 ustar 00root root 0000000 0000000 // From: "Ma, Zhenqiang"
module test (
// Ports for module A
input i_A_outsidei,
output o_A_outsideo,
// Ports for module B
input i_B_outsidei,
output o_B_outsideo );
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire A_internal; // From u0 of moduleA.v
wire B_internal; // From u1 of moduleB.v
// End of automatics
//-----------------------------------------------------------------------------
// instantiate module A
//-----------------------------------------------------------------------------
/* moduleA AUTO_TEMPLATE (
.[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
); */
moduleA u0(
/*AUTOINST*/
// Outputs
.o_A_outsideo (o_A_outsideo), // Templated
.o_A_internal (A_internal), // Templated
// Inputs
.i_A_outsidei (i_A_outsidei), // Templated
.i_B_internal (B_internal)); // Templated
//-----------------------------------------------------------------------------
// instantiate module B
//-----------------------------------------------------------------------------
/* moduleB AUTO_TEMPLATE (
.[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
); */
moduleB u1(
/*AUTOINST*/
// Outputs
.o_B_outsideo (o_B_outsideo), // Templated
.o_B_internal (B_internal), // Templated
// Inputs
.i_B_outsidei (i_B_outsidei), // Templated
.i_A_internal (A_internal)); // Templated
endmodule
module moduleA (
input i_A_outsidei,
output o_A_outsideo,
input i_B_internal,
output o_A_internal
);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire o_A_internal = 1'h0;
wire o_A_outsideo = 1'h0;
// End of automatics
endmodule
module moduleB (
input i_B_outsidei,
output o_B_outsideo,
input i_A_internal,
output o_B_internal
);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire o_B_internal = 1'h0;
wire o_B_outsideo = 1'h0;
// End of automatics
endmodule
/*
Local Variables:
eval:
(defun vl-prefix-i-o (basename)
(cond ((assoc (concat "i_" basename)
(verilog-decls-get-inputs moddecls))
"i_")
((assoc (concat "o_" basename)
(verilog-decls-get-outputs moddecls))
"o_")
((assoc (concat "t_" basename)
(verilog-decls-get-inouts moddecls))
"t_")
(t "")))
End:
*/
verilog-mode-20161124.fd230e6/tests/autoinst_mccoy.v 0000664 0000000 0000000 00000001256 13022141775 0022014 0 ustar 00root root 0000000 0000000 module top
// no-connecting unused outputs of an interface and tying only inputs to gnd.
// Requested:
//
// /* xx AUTO_TEMPLATE (
//.TWI_\(.*\) @"(vl-dir (input)" ({@"vl-width"{1'b0}}),
//.TWI_\(.*\) @"(vl-dir (output)" (),
//);
// */
/* xx AUTO_TEMPLATE (
.TWI_\(.*\) (@"(if (equal vl-dir \\"output\\") \\"\\" (concat vl-width \\"'b0\\"))"),
);
*/
xx XX (/*AUTOINST*/
// Outputs
.TWI_qb (), // Templated
// Inputs
.clk (clk),
.TWI_ia (1'b0), // Templated
.TWI_iw (16'b0)); // Templated
endmodule
module xx
(input clk,
input TWI_ia,
input [15:0] TWI_iw,
output TWI_qb);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_moddefine.v 0000664 0000000 0000000 00000001260 13022141775 0022627 0 ustar 00root root 0000000 0000000 // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008-2008 by Wilson Snyder.
module autoinst_moddefine (/*AUTOARG*/);
/*AUTOWIRE*/
`define SUBMOD_A submod_mod
`define SUBNAME_B subname_b
`SUBMOD_A `SUBNAME_B
(/*AUTOINST*/);
`SUBMOD_UNDEFED subundefed
(/*AUTOINST*/);
submod_decl_from_def subundefed
(/*AUTOINST*/);
endmodule
module submod_mod (/*AUTOARG*/);
input a;
output q;
endmodule
module SUBMOD_UNDEFED (/*AUTOARG*/);
output q;
endmodule
`define SUBMOD_DECL submod_decl_from_def
module `SUBMOD_DECL (/*AUTOARG*/);
output q;
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_modport_param.v 0000664 0000000 0000000 00000001357 13022141775 0023550 0 ustar 00root root 0000000 0000000 //bug565
module InstModule
(svi.master svi_modport,
input clk,
svi svi_nomodport);
endmodule
module InstModule1 #
(parameter TCQ = 100)
(svi.master svi_modport,
input clk,
svi svi_nomodport);
endmodule
module top;
InstModule instName
(/*AUTOINST*/
// Interfaces
.svi_modport (svi_modport.master),
.svi_nomodport (svi_nomodport),
// Inputs
.clk (clk));
InstModule1 instName1
(/*AUTOINST*/
// Interfaces
.svi_modport (svi_modport.master),
.svi_nomodport (svi_nomodport),
// Inputs
.clk (clk));
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v" ".sv")
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_mplist.sv 0000664 0000000 0000000 00000002620 13022141775 0022371 0 ustar 00root root 0000000 0000000
// Parent module
// Specifies modport for interfaces in header.
// Has child modules which do the same.
module autoinst_mplist
(
// --------------------------------------------------------------------------
// Port Declarations
// --------------------------------------------------------------------------
input clk,
input reset_n,
// Top-level interfaces
mbl_if.master msg_resp_if
);
mbl_if msg_req_if; // Some internal interface
// --------------------------------------------------------------------------
// Packages and Local Declarations
// --------------------------------------------------------------------------
/*AUTOLOGIC*/
// --------------------------------------------------------------------------
// Module Body
// --------------------------------------------------------------------------
// For the module instance below, interface ports should be
// connected (per standard AUTOINST fashion) but *without*
// explicitly specifying the modport.
//
// VCS (and likely other Synopsys tools) don't expect to see a
// modport being "respecified" here.
autoinst_mplist_child child
(/*AUTOINST*/);
endmodule
/*
Local Variables:
verilog-typedef-regexp:"_t$"
verilog-library-directories:(".")
verilog-library-extensions:(".sv")
End:
*/
verilog-mode-20161124.fd230e6/tests/autoinst_mplist_child.sv 0000664 0000000 0000000 00000001526 13022141775 0023540 0 ustar 00root root 0000000 0000000 // Child module
// ... with interface modport specified in module header
module autoinst_mplist_child
(
// --------------------------------------------------------------------------
// Port Declarations
// --------------------------------------------------------------------------
input clk,
input reset_n,
// Yeah, let's have an interface
autoinst_mplist_mbl_if.slave msg_req_if,
autoinst_mplist_mbl_if.master msg_resp_if,
// There are likely other signals present, too
output logic msg_busy,
output logic mem_rd_req,
input mem_rd_gnt
);
// Really snazzy RTL follows...
endmodule
/*
Local Variables:
verilog-typedef-regexp:"_t$"
verilog-library-directories:(".")
verilog-library-extensions:(".sv")
End:
*/
verilog-mode-20161124.fd230e6/tests/autoinst_mplist_mbl_if.sv 0000664 0000000 0000000 00000001151 13022141775 0023677 0 ustar 00root root 0000000 0000000 // Example interface definition with at least one modport.
interface autoinst_mplist_mbl_if ();
logic sof;
logic eof;
logic [31:0] data;
logic ready;
logic valid;
modport master(
output data,
output sof,
output eof,
output valid,
input ready
);
modport slave(
input data,
input sof,
input eof,
input valid,
output ready
);
endinterface
verilog-mode-20161124.fd230e6/tests/autoinst_multidim.v 0000664 0000000 0000000 00000004407 13022141775 0022527 0 ustar 00root root 0000000 0000000 module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic sig1; // From u_x of x.v
logic [A-1:0] sig2; // From u_x of x.v
logic [A-1:0] [B-1:0] sig3; // From u_x of x.v
logic [A-1:0][B-1:0] [C-1:0] sig4; // From u_x of x.v
logic [A-1:0][B-1:0][C-1:0] [D-1:0] sig5; // From u_x of x.v
logic vsig1; // From u_x of x.v
logic vsig2 [W-1:0]; // From u_x of x.v
logic vsig3 [W-1:0][X-1:0]; // From u_x of x.v
logic vsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
logic vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
logic zsig1; // From u_x of x.v
logic [A-1:0] zsig2 [W-1:0]; // From u_x of x.v
logic [A-1:0] [B-1:0] zsig3 [W-1:0][X-1:0]; // From u_x of x.v
logic [A-1:0][B-1:0] [C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
logic [A-1:0][B-1:0][C-1:0] [D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
// End of automatics
x u_x (/*AUTOINST*/
// Outputs
.sig1 (sig1),
.sig2 (sig2[A-1:0]),
.sig3 (sig3/*[A-1:0][B-1:0]*/),
.sig4 (sig4/*[A-1:0][B-1:0][C-1:0]*/),
.sig5 (sig5/*[A-1:0][B-1:0][C-1:0][D-1:0]*/),
.vsig1 (vsig1),
.vsig2 (vsig2/*.[W-1:0]*/),
.vsig3 (vsig3/*.[W-1:0][X-1:0]*/),
.vsig4 (vsig4/*.[W-1:0][X-1:0][Y-1:0]*/),
.vsig5 (vsig5/*.[W-1:0][X-1:0][Y-1:0][Z-1:0]*/),
.zsig1 (zsig1),
.zsig2 (zsig2/*[A-1:0].[W-1:0]*/),
.zsig3 (zsig3/*[A-1:0][B-1:0].[W-1:0][X-1:0]*/),
.zsig4 (zsig4/*[A-1:0][B-1:0][C-1:0].[W-1:0][X-1:0][Y-1:0]*/),
.zsig5 (zsig5/*[A-1:0][B-1:0][C-1:0][D-1:0].[W-1:0][X-1:0][Y-1:0][Z-1:0]*/));
endmodule // top
module x;
output sig1;
output [A-1:0] sig2;
output [A-1:0][B-1:0] sig3;
output [A-1:0][B-1:0][C-1:0] sig4;
output [A-1:0][B-1:0][C-1:0][D-1:0] sig5;
output vsig1;
output vsig2 [W-1:0];
output vsig3 [W-1:0][X-1:0];
output vsig4 [W-1:0][X-1:0][Y-1:0];
output vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
output zsig1;
output [A-1:0] zsig2 [W-1:0];
output [A-1:0][B-1:0] zsig3 [W-1:0][X-1:0];
output [A-1:0][B-1:0][C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];
output [A-1:0][B-1:0][C-1:0][D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_multitemplate.v 0000664 0000000 0000000 00000002077 13022141775 0023572 0 ustar 00root root 0000000 0000000 // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
// Reported by Julian Gorfajn
module autoinst_multitemplate ();
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input Boo1; // To suba1 of SubA.v
input Boo2; // To suba2 of SubB.v
input Boo3; // To suba3 of SubC.v
input b; // To suba2 of SubB.v
input c; // To suba3 of SubC.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*
SubA AUTO_TEMPLATE
SubB AUTO_TEMPLATE
SubC AUTO_TEMPLATE (
.a (Boo@),
);*/
SubA suba1 (/*AUTOINST*/
// Inputs
.a (Boo1)); // Templated
SubB suba2 (/*AUTOINST*/
// Inputs
.a (Boo2), // Templated
.b (b));
SubC suba3 (/*AUTOINST*/
// Inputs
.a (Boo3), // Templated
.c (c));
endmodule
module SubA (input a);
endmodule
module SubB (input a,input b);
endmodule
module SubC (input a,input c );
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_name_bug245.v 0000664 0000000 0000000 00000003727 13022141775 0022717 0 ustar 00root root 0000000 0000000 module autoinst_name_bug245 (
);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*Sub AUTO_TEMPLATE (
.dtmp_NO (d_NO),
.etmp_dotnamed (etmp_dotnamed),
);*/
Sub sub (
.bign1_dotnamed,
// Outputs
.bign2_dotnamed,
/*AUTOINST*/);
endmodule
module Sub
(
input logic clk,
output [2:0] a_NO,
output [3:0] f4_dotnamed,
output bign1_dotnamed,
output [1:0] bign2_dotnamed,
output c_dotnamed,
output dtmp_NO,
output etmp_dotnamed,
input \escaped*dot*named
);
endmodule
// Local Variables:
// verilog-auto-inst-dot-name: t
// verilog-auto-inst-vector: nil
// End:
module autoinst_name_bug245 (
);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*Sub AUTO_TEMPLATE (
.dtmp_NO (d_NO),
.etmp_dotnamed (etmp_dotnamed),
);*/
Sub sub (
.bign1_dotnamed,
// Outputs
.bign2_dotnamed,
/*AUTOINST*/);
endmodule
module Sub
(
input logic clk,
output [2:0] a_NO,
output [3:0] f4_dotnamed,
output bign1_dotnamed,
output [1:0] bign2_dotnamed,
output c_dotnamed,
output dtmp_NO,
output etmp_dotnamed,
input \escaped*dot*named
);
endmodule
// Local Variables:
// verilog-auto-inst-dot-name: t
// verilog-auto-inst-vector: nil
// End:
module autoinst_name_bug245 (
);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*Sub AUTO_TEMPLATE (
.dtmp_NO (d_NO),
.etmp_dotnamed (etmp_dotnamed),
);*/
Sub sub (
.bign1_dotnamed,
// Outputs
.bign2_dotnamed,
/*AUTOINST*/);
endmodule
module Sub
(
input logic clk,
output [2:0] a_NO,
output [3:0] f4_dotnamed,
output bign1_dotnamed,
output [1:0] bign2_dotnamed,
output c_dotnamed,
output dtmp_NO,
output etmp_dotnamed,
input \escaped*dot*named
);
endmodule
// Local Variables:
// verilog-auto-inst-dot-name: t
// verilog-auto-inst-vector: nil
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_nicholl.v 0000664 0000000 0000000 00000002050 13022141775 0022323 0 ustar 00root root 0000000 0000000 module sub1 (/*AUTOARG*/
// Inputs
bus1
);
input [0:3] bus1;
endmodule
module sub2 (/*AUTOARG*/
// Inputs
bus2
);
input [0:3] bus2;
endmodule
module sub3 (/*AUTOARG*/
// Outputs
bus1, bus2
);
output [0:3] bus1;
output [4:7] bus2;
endmodule
module top (/*AUTOARG*/);
wire [4:7] bus2; // From sub3 of sub3.v
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [0:3] bus1; // From sub3 of sub3.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.bus1 (bus1[0:3]));
sub2 sub2 (/*AUTOINST*/
// Inputs
.bus2 (bus2[0:3]));
sub3 sub3 (/*AUTOINST*/
// Outputs
.bus1 (bus1[0:3]),
.bus2 (bus2));
endmodule
// Local Variables:
// verilog-auto-inst-vector:nil
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_overflow_bug250.v 0000664 0000000 0000000 00000101522 13022141775 0023626 0 ustar 00root root 0000000 0000000 module TEST_TOP (
);
/*TEST AUTO_TEMPLATE
(
.abcd_efgh_ijklmno_f02_out_c(abcdefg_f02_clroilouull[5]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_be_2(abcdefg_f10_eg2_ab_cdefghijklm[49]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fh_2(abcdefg_f08_eg0_ab_a_fghi[6]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ch(abcdefg_f09_eg1_ab_cdefghijklm[36]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ej_1(abcdefg_f10_eg2_ab_cdefghijklm[14]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ga_1(abcdefg_f10_eg2_ab_cdefghijklm[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fe(abcdefg_f09_eg1_ab_cdefghijklm[9]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bi_2(abcdefg_f08_eg0_ab_cdefghijklm[45]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_24_1(abcdefg_f09_eg1_ab_fghijklm[24]),
.abcd_efgh_ijklmno_f01_oilouull_o_0_1(abcdefg_f01_oilouull[0]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cc_2(abcdefg_f10_eg2_ab_cdefghijklm[41]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_e_2(abcdefg_f11_eg3_ab_cdefghijklm[59]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_54_1(abcdefg_f11_eg3_ab_fghijklm[54]),
.abcd_efgh_ijklmno_f03_oilouull_o_3_1(abcdefg_f03_oilouull[3]),
.abcd_efgh_ijklmno_f02_out_h_2(abcdefg_f02_a_zxdf[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_g_1(abcdefg_f11_eg3_ab_a_fghi[57]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_b_2(abcdefg_f08_eg0_ab_cdefghijklm[62]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_9_1(abcdefg_f11_eg3_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_di_1(abcdefg_f09_eg1_ab_a_fghi[25]),
.abcd_efgh_ijklmno_f00_out_h_2(abcdefg_f00_a_zxdf[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_cg_2(abcdefg_f11_eg3_ab_cdefghijklm[37]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_eh_2(abcdefg_f10_eg2_ab_a_fghi[16]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_di_1(abcdefg_f08_eg0_ab_cdefghijklm[25]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ec_2(abcdefg_f11_eg3_ab_cdefghijklm[21]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_d_1(abcdefg_f11_eg3_ab_a_fghi[60]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bh_1(abcdefg_f11_eg3_ab_a_fghi[46]),
.abcd_efgh_ijklmno_f00_out_f(abcdefg_f00_clroilouull[2]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_52_1(abcdefg_f11_eg3_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f02_out_g(abcdefg_f02_clroilouull[1]),
.abcd_efgh_ijklmno_f07_out_e(abcdefg_f07_clroilouull[3]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ff_2(abcdefg_f10_eg2_ab_a_fghi[8]),
.abcd_efgh_ijklmno_f04_out_h(abcdefg_f04_clroilouull[0]),
.abcd_efgh_ijklmno_f04_out_g_2(abcdefg_f04_a_zxdf[1]),
.abcd_efgh_ijklmno_f02_out_c_2(abcdefg_f02_a_zxdf[5]),
.abcd_efgh_ijklmno_f04_out_a_3(abcdefg_f04_a_zxdf[7]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fa_1(abcdefg_f08_eg0_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ed_2(abcdefg_f08_eg0_ab_a_fghi[20]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ea_2(abcdefg_f10_eg2_ab_a_fghi[23]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_c_2(abcdefg_f10_eg2_ab_cdefghijklm[61]),
.abcd_efgh_ijklmno_f03_oilouull_o_0_1(abcdefg_f03_oilouull[0]),
.abcd_efgh_ijklmno_f00_out_e_2(abcdefg_f00_a_zxdf[3]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bg_3(abcdefg_f10_eg2_ab_a_fghi[47]),
.abcd_efgh_ijklmno_f05_oilouull_o_2_1(abcdefg_f05_oilouull[2]),
.abcd_efgh_ijklmno_f01_out_h_2(abcdefg_f01_a_zxdf[0]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_44_1(abcdefg_f10_eg2_ab_fghijklm[44]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_j_3(abcdefg_f08_eg0_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_39_1(abcdefg_f08_eg0_ab_fghijklm[39]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fj_2(abcdefg_f08_eg0_ab_a_fghi[4]),
.abcd_efgh_ijklmno_f05_out_h(abcdefg_f05_clroilouull[0]),
.abcd_efgh_ijklmno_f05_out_d_2(abcdefg_f05_a_zxdf[4]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_gb_2(abcdefg_f10_eg2_ab_a_fghi[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cb_3(abcdefg_f10_eg2_ab_a_fghi[42]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_52_1(abcdefg_f10_eg2_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_be_2(abcdefg_f11_eg3_ab_cdefghijklm[49]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_42_1(abcdefg_f11_eg3_ab_fghijklm[42]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ci_1(abcdefg_f11_eg3_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fh_1(abcdefg_f10_eg2_ab_cdefghijklm[6]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_24_1(abcdefg_f08_eg0_ab_fghijklm[24]),
.abcd_efgh_ijklmno_f02_out_g_2(abcdefg_f02_a_zxdf[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_d_2(abcdefg_f11_eg3_ab_cdefghijklm[60]),
.abcd_efgh_ijklmno_f06_out_d_2(abcdefg_f06_a_zxdf[4]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ea_1(abcdefg_f09_eg1_ab_a_fghi[23]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_dh_2(abcdefg_f11_eg3_ab_cdefghijklm[26]),
.abcd_efgh_ijklmno_f04_oilouull_o_7_2(abcdefg_f04_oilouull[7]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dh_1(abcdefg_f09_eg1_ab_a_fghi[26]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_18_1(abcdefg_f08_eg0_ab_fghijklm[18]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ba_2(abcdefg_f11_eg3_ab_cdefghijklm[53]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ce_1(abcdefg_f11_eg3_ab_a_fghi[39]),
.abcd_efgh_ijklmno_f03_oilouull_o_5_1(abcdefg_f03_oilouull[5]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ef_1(abcdefg_f09_eg1_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cj_2(abcdefg_f08_eg0_ab_cdefghijklm[34]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_j_2(abcdefg_f08_eg0_ab_cdefghijklm[54]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bh_3(abcdefg_f08_eg0_ab_a_fghi[46]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cb_1(abcdefg_f09_eg1_ab_a_fghi[42]),
.abcd_efgh_ijklmno_f01_oilouull_o_6_2(abcdefg_f01_oilouull[6]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ba_3(abcdefg_f10_eg2_ab_a_fghi[53]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_0_1(abcdefg_f11_eg3_ab_fghijklm[0]),
.abcd_efgh_ijklmno_f06_out_h_2(abcdefg_f06_a_zxdf[0]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_51_1(abcdefg_f08_eg0_ab_fghijklm[51]),
.abcd_efgh_ijklmno_f06_oilouull_o_4_1(abcdefg_f06_oilouull[4]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_10_1(abcdefg_f08_eg0_ab_fghijklm[10]),
.abcd_efgh_ijklmno_f01_oilouull_o_7_2(abcdefg_f01_oilouull[7]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_da_2(abcdefg_f11_eg3_ab_cdefghijklm[33]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_e_1(abcdefg_f09_eg1_ab_a_fghi[59]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_22_1(abcdefg_f08_eg0_ab_fghijklm[22]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_db_2(abcdefg_f11_eg3_ab_cdefghijklm[32]),
.abcd_efgh_ijklmno_f01_oilouull_o_2_1(abcdefg_f01_oilouull[2]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ci_3(abcdefg_f08_eg0_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f07_oilouull_o_6_2(abcdefg_f07_oilouull[6]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_62_1(abcdefg_f11_eg3_ab_fghijklm[62]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_34_1(abcdefg_f10_eg2_ab_fghijklm[34]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_9_1(abcdefg_f10_eg2_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_13_1(abcdefg_f10_eg2_ab_fghijklm[13]),
.abcd_efgh_ijklmno_f05_oilouull_o_7_2(abcdefg_f05_oilouull[7]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ch_1(abcdefg_f11_eg3_ab_a_fghi[36]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fd_1(abcdefg_f10_eg2_ab_cdefghijklm[10]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fc_2(abcdefg_f10_eg2_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ei_1(abcdefg_f09_eg1_ab_a_fghi[15]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_37_1(abcdefg_f08_eg0_ab_fghijklm[37]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_gb(abcdefg_f09_eg1_ab_cdefghijklm[2]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_7_1(abcdefg_f10_eg2_ab_fghijklm[7]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_dg_2(abcdefg_f11_eg3_ab_cdefghijklm[27]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ce(abcdefg_f09_eg1_ab_cdefghijklm[39]),
.abcd_efgh_ijklmno_f07_out_d_2(abcdefg_f07_a_zxdf[4]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cd_2(abcdefg_f08_eg0_ab_cdefghijklm[40]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_57_1(abcdefg_f10_eg2_ab_fghijklm[57]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_63_1(abcdefg_f10_eg2_ab_fghijklm[63]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_j_1(abcdefg_f09_eg1_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f00_out_a(abcdefg_f00_clroilouull[7]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_46_1(abcdefg_f09_eg1_ab_fghijklm[46]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_39_1(abcdefg_f10_eg2_ab_fghijklm[39]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_28_1(abcdefg_f08_eg0_ab_fghijklm[28]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_20_1(abcdefg_f08_eg0_ab_fghijklm[20]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_51_1(abcdefg_f11_eg3_ab_fghijklm[51]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ci_1(abcdefg_f09_eg1_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f04_out_h_2(abcdefg_f04_a_zxdf[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_bd(abcdefg_f09_eg1_ab_cdefghijklm[50]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dg_1(abcdefg_f10_eg2_ab_cdefghijklm[27]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_23_1(abcdefg_f09_eg1_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_1_2(abcdefg_f09_eg1_ab_fghijklm[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bc_2(abcdefg_f08_eg0_ab_cdefghijklm[51]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bc_3(abcdefg_f10_eg2_ab_a_fghi[51]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_62_1(abcdefg_f08_eg0_ab_fghijklm[62]),
.abcd_efgh_ijklmno_f01_out_g_2(abcdefg_f01_a_zxdf[1]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_23_1(abcdefg_f11_eg3_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f03_out_e_2(abcdefg_f03_a_zxdf[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_b_1(abcdefg_f09_eg1_ab_a_fghi[62]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eh(abcdefg_f09_eg1_ab_cdefghijklm[16]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dh_1(abcdefg_f10_eg2_ab_cdefghijklm[26]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_34_1(abcdefg_f09_eg1_ab_fghijklm[34]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_gc_1(abcdefg_f10_eg2_ab_cdefghijklm[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cg_2(abcdefg_f08_eg0_ab_cdefghijklm[37]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_13_1(abcdefg_f11_eg3_ab_fghijklm[13]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_2_1(abcdefg_f08_eg0_ab_fghijklm[2]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fb(abcdefg_f09_eg1_ab_cdefghijklm[12]),
.abcd_efgh_ijklmno_f00_oilouull_o_6_2(abcdefg_f00_oilouull[6]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_h_3(abcdefg_f08_eg0_ab_a_fghi[56]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_38_1(abcdefg_f09_eg1_ab_fghijklm[38]),
.abcd_efgh_ijklmno_f00_out_c(abcdefg_f00_clroilouull[5]),
.abcd_efgh_ijklmno_f06_out_a_3(abcdefg_f06_a_zxdf[7]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_60_1(abcdefg_f09_eg1_ab_fghijklm[60]),
.abcd_efgh_ijklmno_f06_oilouull_o_2_1(abcdefg_f06_oilouull[2]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_8_1(abcdefg_f09_eg1_ab_fghijklm[8]),
.abcd_efgh_ijklmno_f03_out_f(abcdefg_f03_clroilouull[2]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dj_1(abcdefg_f08_eg0_ab_cdefghijklm[24]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bg_2(abcdefg_f08_eg0_ab_cdefghijklm[47]),
.abcd_efgh_ijklmno_f01_oilouull_o_4_1(abcdefg_f01_oilouull[4]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ef_2(abcdefg_f10_eg2_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f01_out_a_3(abcdefg_f01_a_zxdf[7]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_12_1(abcdefg_f08_eg0_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f07_out_c_2(abcdefg_f07_a_zxdf[5]),
.abcd_efgh_ijklmno_f00_out_e(abcdefg_f00_clroilouull[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ca_1(abcdefg_f09_eg1_ab_a_fghi[43]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_eg_2(abcdefg_f08_eg0_ab_a_fghi[17]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_be_1(abcdefg_f11_eg3_ab_a_fghi[49]),
.abcd_efgh_ijklmno_f06_out_d(abcdefg_f06_clroilouull[4]),
.abcd_efgh_ijklmno_f00_out_g(abcdefg_f00_clroilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_b(abcdefg_f09_eg1_ab_cdefghijklm[62]),
.abcd_efgh_ijklmno_f00_out_f_2(abcdefg_f00_a_zxdf[2]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_gc_1(abcdefg_f09_eg1_ab_a_fghi[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ca_1(abcdefg_f11_eg3_ab_a_fghi[43]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ea(abcdefg_f09_eg1_ab_cdefghijklm[23]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_12_1(abcdefg_f10_eg2_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gd_2(abcdefg_f11_eg3_ab_cdefghijklm[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_i_1(abcdefg_f09_eg1_ab_a_fghi[55]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_e_2(abcdefg_f08_eg0_ab_cdefghijklm[59]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ff(abcdefg_f09_eg1_ab_cdefghijklm[8]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_17_1(abcdefg_f11_eg3_ab_fghijklm[17]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_be_3(abcdefg_f10_eg2_ab_a_fghi[49]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_20_1(abcdefg_f11_eg3_ab_fghijklm[20]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bc_1(abcdefg_f11_eg3_ab_a_fghi[51]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_43_1(abcdefg_f09_eg1_ab_fghijklm[43]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_54_1(abcdefg_f09_eg1_ab_fghijklm[54]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_be_2(abcdefg_f08_eg0_ab_cdefghijklm[49]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_36_1(abcdefg_f10_eg2_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f05_out_h_2(abcdefg_f05_a_zxdf[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cc(abcdefg_f09_eg1_ab_cdefghijklm[41]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_3_1(abcdefg_f11_eg3_ab_fghijklm[3]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ff_1(abcdefg_f11_eg3_ab_a_fghi[8]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_19_2(abcdefg_f11_eg3_ab_fghijklm[19]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bi_1(abcdefg_f11_eg3_ab_a_fghi[45]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_49_1(abcdefg_f08_eg0_ab_fghijklm[49]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ee_1(abcdefg_f10_eg2_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_29_1(abcdefg_f08_eg0_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_29_1(abcdefg_f09_eg1_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ed(abcdefg_f09_eg1_ab_cdefghijklm[20]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_de(abcdefg_f09_eg1_ab_cdefghijklm[29]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dg_2(abcdefg_f10_eg2_ab_a_fghi[27]),
.abcd_efgh_ijklmno_f04_oilouull_o_2_1(abcdefg_f04_oilouull[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_eb_2(abcdefg_f10_eg2_ab_a_fghi[22]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ea_2(abcdefg_f11_eg3_ab_cdefghijklm[23]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fc_1(abcdefg_f10_eg2_ab_cdefghijklm[11]),
.abcd_efgh_ijklmno_f06_out_g(abcdefg_f06_clroilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_61_1(abcdefg_f09_eg1_ab_fghijklm[61]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ee_2(abcdefg_f10_eg2_ab_a_fghi[19]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_47_1(abcdefg_f11_eg3_ab_fghijklm[47]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_36_1(abcdefg_f08_eg0_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f07_oilouull_o_0_1(abcdefg_f07_oilouull[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_j_1(abcdefg_f11_eg3_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_52_1(abcdefg_f08_eg0_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gd_1(abcdefg_f11_eg3_ab_a_fghi[0]),
.abcd_efgh_ijklmno_f07_out_h_2(abcdefg_f07_a_zxdf[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cg_1(abcdefg_f09_eg1_ab_a_fghi[37]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_8_1(abcdefg_f10_eg2_ab_fghijklm[8]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fh_1(abcdefg_f11_eg3_ab_a_fghi[6]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_52_1(abcdefg_f09_eg1_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ci_2(abcdefg_f11_eg3_ab_cdefghijklm[35]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_15_1(abcdefg_f10_eg2_ab_fghijklm[15]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_df(abcdefg_f09_eg1_ab_cdefghijklm[28]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ee(abcdefg_f09_eg1_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bd_1(abcdefg_f11_eg3_ab_a_fghi[50]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fe_1(abcdefg_f11_eg3_ab_a_fghi[9]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_di_2(abcdefg_f08_eg0_ab_a_fghi[25]),
.abcd_efgh_ijklmno_f00_out_d(abcdefg_f00_clroilouull[4]),
.abcd_efgh_ijklmno_f07_oilouull_o_5_1(abcdefg_f07_oilouull[5]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_41_1(abcdefg_f09_eg1_ab_fghijklm[41]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cf_2(abcdefg_f08_eg0_ab_cdefghijklm[38]),
.abcd_efgh_ijklmno_f05_out_b_3(abcdefg_f05_a_zxdf[6]),
.abcd_efgh_ijklmno_f03_oilouull_o_1_1(abcdefg_f03_oilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dg_1(abcdefg_f09_eg1_ab_a_fghi[27]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eg(abcdefg_f09_eg1_ab_cdefghijklm[17]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ce_1(abcdefg_f09_eg1_ab_a_fghi[39]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fi_2(abcdefg_f11_eg3_ab_cdefghijklm[5]),
.abcd_efgh_ijklmno_f05_out_g(abcdefg_f05_clroilouull[1]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bj_2(abcdefg_f10_eg2_ab_cdefghijklm[44]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_db(abcdefg_f09_eg1_ab_cdefghijklm[32]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_g_1(abcdefg_f09_eg1_ab_a_fghi[57]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bf_2(abcdefg_f08_eg0_ab_cdefghijklm[48]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bh_2(abcdefg_f08_eg0_ab_cdefghijklm[46]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_23_1(abcdefg_f10_eg2_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_61_1(abcdefg_f10_eg2_ab_fghijklm[61]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_db_1(abcdefg_f09_eg1_ab_a_fghi[32]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_f(abcdefg_f09_eg1_ab_cdefghijklm[58]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_57_1(abcdefg_f09_eg1_ab_fghijklm[57]),
.abcd_efgh_ijklmno_f01_oilouull_o_1_1(abcdefg_f01_oilouull[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_eh_2(abcdefg_f08_eg0_ab_a_fghi[16]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_41_1(abcdefg_f11_eg3_ab_fghijklm[41]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_c_2(abcdefg_f08_eg0_ab_cdefghijklm[61]),
.abcd_efgh_ijklmno_f06_out_e(abcdefg_f06_clroilouull[3]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ej_1(abcdefg_f11_eg3_ab_a_fghi[14]),
.abcd_efgh_ijklmno_f02_oilouull_o_1_1(abcdefg_f02_oilouull[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bd_2(abcdefg_f11_eg3_ab_cdefghijklm[50]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_6_1(abcdefg_f08_eg0_ab_fghijklm[6]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ee_1(abcdefg_f09_eg1_ab_a_fghi[19]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fc_2(abcdefg_f11_eg3_ab_cdefghijklm[11]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bd_3(abcdefg_f10_eg2_ab_a_fghi[50]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_df_1(abcdefg_f08_eg0_ab_cdefghijklm[28]),
.abcd_efgh_ijklmno_f03_out_a(abcdefg_f03_clroilouull[7]),
.abcd_efgh_ijklmno_f02_oilouull_o_0_1(abcdefg_f02_oilouull[0]),
.abcd_efgh_ijklmno_f00_out_g_2(abcdefg_f00_a_zxdf[1]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_43_1(abcdefg_f08_eg0_ab_fghijklm[43]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_59_1(abcdefg_f08_eg0_ab_fghijklm[59]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ff_1(abcdefg_f09_eg1_ab_a_fghi[8]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bh_2(abcdefg_f10_eg2_ab_cdefghijklm[46]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_0_1(abcdefg_f09_eg1_ab_fghijklm[0]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ec_2(abcdefg_f08_eg0_ab_a_fghi[21]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_33_1(abcdefg_f09_eg1_ab_fghijklm[33]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fh_1(abcdefg_f09_eg1_ab_a_fghi[6]),
.abcd_efgh_ijklmno_f02_oilouull_o_4_1(abcdefg_f02_oilouull[4]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_31_1(abcdefg_f10_eg2_ab_fghijklm[31]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fa_1(abcdefg_f10_eg2_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f05_out_f(abcdefg_f05_clroilouull[2]),
.abcd_efgh_ijklmno_f04_out_e_2(abcdefg_f04_a_zxdf[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dd_1(abcdefg_f09_eg1_ab_a_fghi[30]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_12_1(abcdefg_f11_eg3_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_bf_1(abcdefg_f09_eg1_ab_a_fghi[48]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_23_1(abcdefg_f08_eg0_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dj_2(abcdefg_f08_eg0_ab_a_fghi[24]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ci_3(abcdefg_f10_eg2_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_17_1(abcdefg_f08_eg0_ab_fghijklm[17]),
.abcd_efgh_ijklmno_f02_out_f_2(abcdefg_f02_a_zxdf[2]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bb_1(abcdefg_f11_eg3_ab_a_fghi[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_cc_1(abcdefg_f11_eg3_ab_a_fghi[41]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_f_1(abcdefg_f11_eg3_ab_a_fghi[58]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fi(abcdefg_f09_eg1_ab_cdefghijklm[5]),
.abcd_efgh_ijklmno_f03_out_h(abcdefg_f03_clroilouull[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_e_1(abcdefg_f11_eg3_ab_a_fghi[59]),
.abcd_efgh_ijklmno_f01_out_b_3(abcdefg_f01_a_zxdf[6]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_55_1(abcdefg_f08_eg0_ab_fghijklm[55]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bj_3(abcdefg_f10_eg2_ab_a_fghi[44]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_d_2(abcdefg_f08_eg0_ab_cdefghijklm[60]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bi_3(abcdefg_f08_eg0_ab_a_fghi[45]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fg_1(abcdefg_f09_eg1_ab_a_fghi[7]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ej_2(abcdefg_f10_eg2_ab_a_fghi[14]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cb_2(abcdefg_f08_eg0_ab_cdefghijklm[42]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fi_1(abcdefg_f10_eg2_ab_cdefghijklm[5]),
.abcd_efgh_ijklmno_f01_out_c(abcdefg_f01_clroilouull[5]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fa_2(abcdefg_f11_eg3_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f07_out_b_3(abcdefg_f07_a_zxdf[6]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_2_1(abcdefg_f09_eg1_ab_fghijklm[2]),
.abcd_efgh_ijklmno_f07_oilouull_o_2_1(abcdefg_f07_oilouull[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ed_2(abcdefg_f10_eg2_ab_a_fghi[20]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_32_1(abcdefg_f08_eg0_ab_fghijklm[32]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_29_1(abcdefg_f10_eg2_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ef_1(abcdefg_f11_eg3_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_15_1(abcdefg_f09_eg1_ab_fghijklm[15]),
.abcd_efgh_ijklmno_f04_out_c_2(abcdefg_f04_a_zxdf[5]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cd(abcdefg_f09_eg1_ab_cdefghijklm[40]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_57_1(abcdefg_f08_eg0_ab_fghijklm[57]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ee_2(abcdefg_f11_eg3_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_3_1(abcdefg_f09_eg1_ab_fghijklm[3]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_20_1(abcdefg_f10_eg2_ab_fghijklm[20]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_16_1(abcdefg_f08_eg0_ab_fghijklm[16]),
.abcd_efgh_ijklmno_f06_oilouull_o_1_1(abcdefg_f06_oilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cg(abcdefg_f09_eg1_ab_cdefghijklm[37]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cd_3(abcdefg_f10_eg2_ab_a_fghi[40]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_35_1(abcdefg_f10_eg2_ab_fghijklm[35]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_j_3(abcdefg_f10_eg2_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dc_2(abcdefg_f10_eg2_ab_a_fghi[31]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_34_1(abcdefg_f08_eg0_ab_fghijklm[34]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bi_2(abcdefg_f10_eg2_ab_cdefghijklm[45]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_48_1(abcdefg_f09_eg1_ab_fghijklm[48]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_1_2(abcdefg_f10_eg2_ab_fghijklm[1]),
.abcd_efgh_ijklmno_f07_out_g(abcdefg_f07_clroilouull[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_c_2(abcdefg_f11_eg3_ab_cdefghijklm[61]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_24_1(abcdefg_f10_eg2_ab_fghijklm[24]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fj_2(abcdefg_f10_eg2_ab_a_fghi[4]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_bi_1(abcdefg_f09_eg1_ab_a_fghi[45]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_eb_2(abcdefg_f11_eg3_ab_cdefghijklm[22]),
.abcd_efgh_ijklmno_f00_oilouull_o_5_1(abcdefg_f00_oilouull[5]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_30_1(abcdefg_f08_eg0_ab_fghijklm[30]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_11_1(abcdefg_f11_eg3_ab_fghijklm[11]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_26_1(abcdefg_f11_eg3_ab_fghijklm[26]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_45_1(abcdefg_f08_eg0_ab_fghijklm[45]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dj_1(abcdefg_f10_eg2_ab_cdefghijklm[24]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_gd_1(abcdefg_f10_eg2_ab_cdefghijklm[0]),
.abcd_efgh_ijklmno_f05_out_b(abcdefg_f05_clroilouull[6]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ef_2(abcdefg_f08_eg0_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dg(abcdefg_f09_eg1_ab_cdefghijklm[27]),
.abcd_efgh_ijklmno_f02_oilouull_o_6_2(abcdefg_f02_oilouull[6]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_39_1(abcdefg_f11_eg3_ab_fghijklm[39]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bh_3(abcdefg_f10_eg2_ab_a_fghi[46]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fc_1(abcdefg_f08_eg0_ab_cdefghijklm[11]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fa(abcdefg_f09_eg1_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f04_out_b_3(abcdefg_f04_a_zxdf[6]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_21_1(abcdefg_f08_eg0_ab_fghijklm[21]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bc_3(abcdefg_f08_eg0_ab_a_fghi[51]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dd_1(abcdefg_f08_eg0_ab_cdefghijklm[30]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fc_1(abcdefg_f09_eg1_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_22_1(abcdefg_f11_eg3_ab_fghijklm[22]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_14_1(abcdefg_f11_eg3_ab_fghijklm[14]),
.abcd_efgh_ijklmno_f02_out_d_2(abcdefg_f02_a_zxdf[4]),
.abcd_efgh_ijklmno_f06_out_h(abcdefg_f06_clroilouull[0]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_37_1(abcdefg_f09_eg1_ab_fghijklm[37]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eh_1(abcdefg_f09_eg1_ab_a_fghi[16]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_12_1(abcdefg_f09_eg1_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cd_1(abcdefg_f09_eg1_ab_a_fghi[40]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_60_1(abcdefg_f11_eg3_ab_fghijklm[60]),
.abcd_efgh_ijklmno_f03_out_f_2(abcdefg_f03_a_zxdf[2]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_43_1(abcdefg_f11_eg3_ab_fghijklm[43]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dc_2(abcdefg_f08_eg0_ab_a_fghi[31]),
.abcd_efgh_ijklmno_f07_out_b(abcdefg_f07_clroilouull[6]),
.abcd_efgh_ijklmno_f03_out_b_3(abcdefg_f03_a_zxdf[6]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ea_1(abcdefg_f10_eg2_ab_cdefghijklm[23]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_eg_1(abcdefg_f08_eg0_ab_cdefghijklm[17]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fc_2(abcdefg_f08_eg0_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_gc_1(abcdefg_f08_eg0_ab_cdefghijklm[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_da(abcdefg_f09_eg1_ab_cdefghijklm[33]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gb_2(abcdefg_f11_eg3_ab_cdefghijklm[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ba_2(abcdefg_f10_eg2_ab_cdefghijklm[53]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fb_2(abcdefg_f10_eg2_ab_a_fghi[12]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ee_1(abcdefg_f11_eg3_ab_a_fghi[19]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_32_1(abcdefg_f09_eg1_ab_fghijklm[32]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gc_2(abcdefg_f11_eg3_ab_cdefghijklm[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ee_1(abcdefg_f08_eg0_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_36_1(abcdefg_f09_eg1_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f02_out_a(abcdefg_f02_clroilouull[7]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_9_1(abcdefg_f08_eg0_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_5_1(abcdefg_f09_eg1_ab_fghijklm[5]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bh_2(abcdefg_f11_eg3_ab_cdefghijklm[46]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_35_1(abcdefg_f09_eg1_ab_fghijklm[35]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ca(abcdefg_f09_eg1_ab_cdefghijklm[43]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_47_1(abcdefg_f08_eg0_ab_fghijklm[47]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gc_1(abcdefg_f11_eg3_ab_a_fghi[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ba_2(abcdefg_f08_eg0_ab_cdefghijklm[53]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_44_1(abcdefg_f11_eg3_ab_fghijklm[44]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_9_1(abcdefg_f09_eg1_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f00_oilouull_o_3_1(abcdefg_f00_oilouull[3]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fe_2(abcdefg_f11_eg3_ab_cdefghijklm[9]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ec_1(abcdefg_f09_eg1_ab_a_fghi[21]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_de_2(abcdefg_f10_eg2_ab_a_fghi[29]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_29_1(abcdefg_f11_eg3_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_g_3(abcdefg_f08_eg0_ab_a_fghi[57]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fi_2(abcdefg_f10_eg2_ab_a_fghi[5]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_27_1(abcdefg_f08_eg0_ab_fghijklm[27]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fc_1(abcdefg_f11_eg3_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_42_1(abcdefg_f10_eg2_ab_fghijklm[42]),
.abcd_efgh_ijklmno_f04_oilouull_o_4_1(abcdefg_f04_oilouull[4]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_30_1(abcdefg_f09_eg1_ab_fghijklm[30]),
.abcd_efgh_ijklmno_f01_oilouull_o_3_1(abcdefg_f01_oilouull[3]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fj_1(abcdefg_f10_eg2_ab_cdefghijklm[4]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_55_1(abcdefg_f11_eg3_ab_fghijklm[55]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_42_1(abcdefg_f08_eg0_ab_fghijklm[42]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_gd(abcdefg_f09_eg1_ab_cdefghijklm[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eg_1(abcdefg_f09_eg1_ab_a_fghi[17]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_8_1(abcdefg_f08_eg0_ab_fghijklm[8]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_50_1(abcdefg_f11_eg3_ab_fghijklm[50]),
.abcd_efgh_ijklmno_f06_out_f_2(abcdefg_f06_a_zxdf[2]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_26_1(abcdefg_f09_eg1_ab_fghijklm[26]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_30_1(abcdefg_f11_eg3_ab_fghijklm[30]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_55_1(abcdefg_f10_eg2_ab_fghijklm[55]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_df_2(abcdefg_f08_eg0_ab_a_fghi[28]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_28_1(abcdefg_f09_eg1_ab_fghijklm[28]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_22_1(abcdefg_f09_eg1_ab_fghijklm[22]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_45_1(abcdefg_f09_eg1_ab_fghijklm[45]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_46_1(abcdefg_f08_eg0_ab_fghijklm[46]),
.abcd_efgh_ijklmno_f01_out_f(abcdefg_f01_clroilouull[2]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_36_1(abcdefg_f11_eg3_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f05_out_f_2(abcdefg_f05_a_zxdf[2]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ch_2(abcdefg_f08_eg0_ab_cdefghijklm[36]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cj_3(abcdefg_f10_eg2_ab_a_fghi[34]),
.abcd_efgh_ijklmno_f04_oilouull_o_3_1(abcdefg_f04_oilouull[3]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cd_3(abcdefg_f08_eg0_ab_a_fghi[40]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_56_1(abcdefg_f08_eg0_ab_fghijklm[56]),
);*/
TEST TEST (/*AUTOINST*/);
endmodule
module TEST (/*AUTOARG*/);
parameter NO = 6456;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_param_2d.v 0000664 0000000 0000000 00000001477 13022141775 0022374 0 ustar 00root root 0000000 0000000 // bug981
module a(
parameter AUM=80;
parameter BUM=70;
parameter VUM=1;
parameter V2=2;
input my_data_z;
input my_data_v[VUM];
input my_data_vv[VUM][V2];
input [AUM-1:0] my_data_av[VUM];
input [AUM-1:0][BUM-1:0] my_data_ab;
input [AUM-1:0][BUM-1:0] my_data_abv[VUM];
input [XUM-1:0][YUM-1:0] my_data_xyz[ZUM];
input PARAMS0__t params0 [1:0];
input PARAMS1__t params1 [1:0];
);
endmodule
module top (/*AUTOARG*/)
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*
a AUTO_TEMPLATE
(
.\(.*\) (TEST@_\1[][]),
);
*/
a #(/*AUTOINSTPARAM*/)
a_0 (/*AUTOINST*/);
a #(/*AUTOINSTPARAM*/)
a_1 (/*AUTOINST*/);
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-typedef-regexp: "_t$"
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_param_cmt.v 0000664 0000000 0000000 00000001010 13022141775 0022631 0 ustar 00root root 0000000 0000000 module InstMod ( ins, outs );
output [INWIDTH-1:0] ins;
endmodule
module test (/*AUTOARG*/) ;
parameter foo=1;
/*
parameter foo=2;
*/
//bug647
/* InstMod AUTO_TEMPLATE
(.ins (a@"vh-foo")); */
InstMod instName (/*AUTOINST*/
// Outputs
.ins (a1)); // Templated
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_param_type.v 0000664 0000000 0000000 00000003612 13022141775 0023041 0 ustar 00root root 0000000 0000000
//bug1061
//typedef logic [7:0] foo_t;
module ptype
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input foo_t a, // To b0 of ptype_buf.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output foo_t y0, // From b0 of ptype_buf.v
output logic [7:0] y1, // From b1 of ptype_buf.v
output TYPE_T y2 // From b2 of ptype_buf.v
// End of automatics
);
ptype_buf #(.TYPE_T(foo_t)) b0
(// Outputs
.y (y0),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.TYPE_T(logic [7:0])) b1
(// Outputs
.y (y1),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.WIDTH(8)) b2
(// Outputs
.y (y2),
/*AUTOINST*/
// Inputs
.a (a));
endmodule
module ptype_buf
#(parameter WIDTH = 1,
parameter type TYPE_T = logic [WIDTH-1:0])
(output TYPE_T y,
input TYPE_T a);
assign y = a;
endmodule
///--------------
// Example in docs
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule
module ExampInst;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [9:0] i; // To instName of InstModule.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output upper_t o; // From instName of InstModule.v
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.i (i[9:0]));
endmodule
// Local Variables:
// verilog-typedef-regexp: "_[tT]$"
// verilog-auto-inst-param-value:t
// verilog-auto-inst-param-value-type:t
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_paramover.v 0000664 0000000 0000000 00000001070 13022141775 0022670 0 ustar 00root root 0000000 0000000 module autoinst_paramover (/*AUTOARG*/
// Inouts
a, b
);
//======================================================================
// Inputs/Outputs
//======================================================================
parameter bitsa = 20;
parameter bitsb = 20;
inout [20:0] a; // SDRAM Channel 0 Row Address Strobe
inout [20:0] b; // SDRAM Channel 0 Row Address Strobe
autoinst_paramover_sub #(bitsa,bitsb ) mod
(/*AUTOINST*/
// Inouts
.a (a[bitsa:0]),
.b (b[bitsb:0]));
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_paramover_sub.v 0000664 0000000 0000000 00000000661 13022141775 0023546 0 ustar 00root root 0000000 0000000 module autoinst_paramover_sub (/*AUTOARG*/
// Inouts
a, b
);
//======================================================================
// Inputs/Outputs
//======================================================================
parameter bitsa;
parameter bitsb;
inout [bitsa:0] a; // SDRAM Channel 0 Row Address Strobe
inout [bitsb:0] b; // SDRAM Channel 0 Row Address Strobe
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_paramvalue.v 0000664 0000000 0000000 00000003130 13022141775 0023030 0 ustar 00root root 0000000 0000000 module testmuxpv();
# (parameter WIDTH = 32)
(
input wire [2:0] /* synopsys enum cur_info */ sel,
input wire [WIDTH-1:0] a,
output reg [WIDTH-1:0] out
);
endmodule
module top_test();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [WIDTH-1:0] out; // From testmuxpv_boo of testmuxpv.v, ..., Couldn't Merge
// End of automatics
//======================================================================
/* testmuxpv AUTO_TEMPLATE (
) */
testmuxpv #(.IGNORE((1)),
.WIDTH( 16 ),
.IGNORE2(2))
testmuxpv_boo
(/*AUTOINST*/
// Outputs
.out (out[15:0]),
// Inputs
.sel (sel[2:0]),
.a (a[15:0]));
//======================================================================
testmuxpv #(.IGNORE((1)),
.WIDTH(WIDTH), // Make sure we don't recurse!
.IGNORE2(2))
testmuxpv_boo
(/*AUTOINST*/
// Outputs
.out (out[WIDTH-1:0]),
// Inputs
.sel (sel[2:0]),
.a (a[WIDTH-1:0]));
//======================================================================
// bug331: vl-width should correct when param values propagating
/* testmuxpv AUTO_TEMPLATE (
.a ({@"vl-width"{1'b0}}),
) */
testmuxpv #(.IGNORE((1)),
.WIDTH(16),
.IGNORE2(2))
testmuxpv_boo
(/*AUTOINST*/
// Outputs
.out (out[15:0]),
// Inputs
.sel (sel[2:0]),
.a ({16{1'b0}})); // Templated
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_podolsky.v 0000664 0000000 0000000 00000000626 13022141775 0022546 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOARG*/);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin_in(),
// Inputs
.pin_out (),
); */
autoinst_lopaz_srpad i_ctrl
(/*AUTOINST*/
// Outputs
.pin_in (), // Templated
// Inouts
.pin (pin[w-1:0]),
// Inputs
.clk (clk),
.pin_out (), // Templated
.pin_outen (pin_outen));
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_precomment.v 0000664 0000000 0000000 00000001771 13022141775 0023055 0 ustar 00root root 0000000 0000000 module autoinst_precomment (
why,
/*AUTOARG*/
// Inputs
nnnot
);
input why;
input nnnot;
autoinst_wildcard_sub sub0
(
.sd_ras_ (foobar_ras_),
//.sd0_dqm7_l (dontdome),
/*AUTOINST*/
// Inouts
.sd0_dqm7_l (sd0_dqm7_l),
.sd0_dqm6_l (sd0_dqm6_l),
.sd0_dqm5_l (sd0_dqm5_l),
.sd0_dqm4_l (sd0_dqm4_l),
.sd0_dqm3_l (sd0_dqm3_l),
.sd0_dqm2_l (sd0_dqm2_l),
.sd0_dqm1_l (sd0_dqm1_l),
.sd0_dqm0_l (sd0_dqm0_l),
.sd0_ba1 (sd0_ba1),
.sd0_ba0 (sd0_ba0),
.sd0_adrs11 (sd0_adrs11),
.sd0_adrs10 (sd0_adrs10),
.sd0_adrs9 (sd0_adrs9),
.sd0_adrs8 (sd0_adrs8),
.sd0_adrs7 (sd0_adrs7),
.sd0_adrs6 (sd0_adrs6),
.sd0_adrs5 (sd0_adrs5),
.sd0_adrs4 (sd0_adrs4),
.sd0_adrs3 (sd0_adrs3),
.sd0_adrs2 (sd0_adrs2),
.sd0_adrs1 (sd0_adrs1),
.sd0_adrs0 (sd0_adrs0),
.sd0_clk (sd0_clk));
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_rao.v 0000664 0000000 0000000 00000001020 13022141775 0021450 0 ustar 00root root 0000000 0000000 module temp2(/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [5:0] out; // From adc_3 of adc.v
// End of automatics
adc adc_3 (
// Outputs
.out (out[5:0]),
// Inputs
.Vi (Vi),
// Inputs
.evalClk (evalClk),
/*AUTOINST*/);
endmodule // temp
module adc(/*AUTOARG*/
// Outputs
out,
// Inputs
Vi, evalClk
);
output [5:0] out;
input Vi;
input evalClk;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_regexp_match.v 0000664 0000000 0000000 00000000766 13022141775 0023355 0 ustar 00root root 0000000 0000000 module autoinst_wildcard;
/*AUTOINOUT*/
/* autoinst_wildcard_sub AUTO_TEMPLATE (
.sd\([0-9]\)_\(.*\)\([0-9]+\)\(.*\) (@"(uc \\"sd_\2\4[\1][\3]\\")"),
); */
/*AUTOOUTPUT*/
autoinst_wildcard_sub sub0
(/*AUTOINST*/);
/* autoinst_wildcard_sub AUTO_TEMPLATE (
.sd\([0-9]\)_\(.*\)\([0-9]+\)\(.*\) (sd_\2\4[\1][\3]),
); */
/*AUTOOUTPUT*/
autoinst_wildcard_sub sub1
(/*AUTOINST*/);
endmodule
// Local Variables:
// eval:(defun uc (x) (upcase x))
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_rogoff.v 0000664 0000000 0000000 00000002113 13022141775 0022155 0 ustar 00root root 0000000 0000000 module testmux();
# (parameter WIDTH = 32)
(
input wire [2:0] /* synopsys enum cur_info */ sel,
input wire [WIDTH-1:0] a,
output reg [WIDTH-1:0] out
);
endmodule
module top_test();
/*AUTOWIRE*/
/*AUTO_LISP(setq verilog-auto-inst-param-value nil)*/
/* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
.a (@_a_symbolic[]),
.out (@_out_symbolic[]),
);
*/
testmux #(.WIDTH( 16 )) testmux_boo
(/*AUTOINST*/);
testmux testmux_defaultwidth
(/*AUTOINST*/);
//======================================================================
/*AUTO_LISP(setq verilog-auto-inst-param-value t)*/
/* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
.a (@_a_value[]),
.out (@_out_value[]),
);
*/
testmux #(.IGNORE((1)),
.WIDTH( 16 ),
.IGNORE2(2))
testmux_boo
(/*AUTOINST*/);
//======================================================================
testmux #(.IGNORE((1)),
.WIDTH(WIDTH), // Make sure we don't recurse!
.IGNORE2(2))
testmux_boo
(/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_rons.v 0000664 0000000 0000000 00000000510 13022141775 0021653 0 ustar 00root root 0000000 0000000 module autoinst_rons;
dwrr dwrr_inst (/*AUTOINST*/);
endmodule
// module declaration
module dwrr (
//Inputs
input [47:0] data_avail,
input [47:0] cell_eof,
//Outputs
output reg [6:0] dwell_count_out,
output reg [47:0] eligible_flag,
output [5:0] dwrr_state );
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_signed.v 0000664 0000000 0000000 00000002661 13022141775 0022154 0 ustar 00root root 0000000 0000000 module autoinst_signed
(/*AUTOARG*/
// Outputs
another_output2, another_output, an_outputpre, an_output2
);
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
output signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
output signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
output [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
wire signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
wire signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
wire [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
// End of automatics
autoinst_signed_fubar u_fubar
(
// Outputs
.an_output (an_outputpre[1:0]),
.plover (plump),
/*AUTOINST*/
// Outputs
.another_output (another_output[1:0]),
// Inputs
.an_input (an_input[1:0]));
autoinst_signed_fubar2 u_fubar2
(
/*AUTOINST*/
// Outputs
.an_output2 (an_output2[1:0]),
.another_output2 (another_output2[1:0]),
// Inputs
.an_input2 (an_input2[1:0]));
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_signed_fubar.v 0000664 0000000 0000000 00000000516 13022141775 0023330 0 ustar 00root root 0000000 0000000
module autoinst_signed_fubar
(
input signed [1:0] an_input,
output signed [1:0] an_output
output signed [1:0] another_output
);
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg signed [1:0] an_output;
reg signed [1:0] another_output;
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_signed_fubar2.v 0000664 0000000 0000000 00000000466 13022141775 0023416 0 ustar 00root root 0000000 0000000
module autoinst_signed_fubar2
(
input [1:0] an_input2,
output [1:0] an_output2
output [1:0] another_output2
);
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [1:0] an_output2;
reg [1:0] another_output2;
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_star.v 0000664 0000000 0000000 00000001060 13022141775 0021644 0 ustar 00root root 0000000 0000000 module io1_sub (/*AUTOARG*/);
/*AUTOWIRE*/
autoinst_lopaz_srpad MD31_pad
(.*,
.foo (touch_this_not_my_pretty));
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
); */
autoinst_lopaz_srpad MD31_pad
(.*);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin (templated));
*/
autoinst_lopaz_srpad MD31_pad
(.*);
// And .name with auto inst
autoinst_lopaz_srpad MD31_pad22
(.pin,
.clk,
/*AUTOINST*/);
always @(posedge clk) begin
$display ("This .* shouldn't expand.\n");
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_sv_kulkarni.v 0000664 0000000 0000000 00000003301 13022141775 0023223 0 ustar 00root root 0000000 0000000 `timescale 1ns/100ps
// -----------------------------------------------------------------------------
// One-level up Hierarchical module
// -----------------------------------------------------------------------------
module a_h
// Verilog 2001 style
#(parameter M=5, N=3)
(
// Outputs
output [N-1:0] [M-1:0]a_o1 // From Ia of autoinst_sv_kulkarni_base.v
// End of automatics
// AUTOINPUT*/
);
/*AUTOWIRE*/
autoinst_sv_kulkarni_base
#(/*AUTOINSTPARAM*/)
Ia
(/*AUTOINST*/); // <---- BUG?
endmodule
// -----------------------------------------------------------------------------
// Top-level module or Testbench
// -----------------------------------------------------------------------------
module top;
parameter M=4;
parameter N=2;
wire [N-1:0] a_o1;
logic [N-1:0][M-1:0] a_i1;
logic temp;
/*AUTOWIRE*/
// Workaround to fix multi-dimensional port problem
// a) Set "verilog-auto-inst-vector = nil"
// b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
a_h #(/*AUTOINSTPARAM*/)
Ua_h
(/*AUTOINST*/); // <---- BUG?
// Stimulus
initial begin
a_i1 = { 4'h0, 4'h2 };
#5;
$display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
a_i1[1], a_i1[0], a_o1);
#5;
for (int i=0; i<1; i++) begin
for (int j=0; j
module autoinst_multitemplate ();
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input Boo2; // To suba2 of SubB.v
input Boo3; // To suba3 of SubB.v
input a; // To suba2 of SubB.v
input b; // To suba3 of SubB.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*
SubB AUTO_TEMPLATE (
.b (Boo@),
);*/
SubB suba2 (/*AUTOINST*/
// Inputs
.a (a),
.b (Boo2)); // Templated
/*
SubB AUTO_TEMPLATE (
.a (Boo@),
);*/
SubB suba3 (/*AUTOINST*/
// Inputs
.a (Boo3), // Templated
.b (b));
// Test harness doesn't support expected errors
// /*
// SubUnused AUTO_TEMPLATE (
// .subunused (Boo@),
// );*/
endmodule
module SubB (input a,input b);
endmodule
// Local Variables:
// verilog-auto-template-warn-unused: t
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_tennant.v 0000664 0000000 0000000 00000003470 13022141775 0022351 0 ustar 00root root 0000000 0000000 typedef logic [3:0][1:0] sometype_t;
module top
#(parameter X=4,
parameter Y=1)
(input clk,
input rstb,
/*AUTOINPUT("^x.*\|v.*")*/
/*AUTOOUTPUT("^c.*\|k.*")*/
/*AUTOOUTPUT("^y.*")*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output foobar, // From XX of xx.v
output [4:0] [2:0] foobar2 // From YY of yy.v
// End of automatics
);
xx (/*AUTOINSTPARAM*/
// Parameters
.X (X),
.Y (Y))
XX(/*AUTOINST*/
// Outputs
.st (st[1:0]),
.foobar (foobar),
// Inputs
.clk (clk),
.rstb (rstb),
.xc (xc/*[X-1:0][1:0]*/),
.xa (xa[X-1:0]),
.xb (xb[X-1:0]),
.cb (cb[X-1:0]),
.yb (yb[X*Y-1:0]));
yy (/*AUTOINSTPARAM*/
// Parameters
.X (X),
.Y (Y))
YY(/*AUTOINST*/
// Outputs
.xc (xc/*[X-1:0][1:0]*/),
.xa (xa[X-1:0]),
.yb (yb[X*Y-1:0]),
.foobar2 (foobar2/*[4:0][2:0]*/),
// Inputs
.clk (clk),
.rstb (rstb),
.xb (xb[X-1:0]),
.cb (cb[X-1:0]),
.st (st[1:0]));
endmodule // top
module xx
#(parameter X=4,
parameter Y=1)
(input clk,
input rstb,
input [X-1:0][1:0] xc,
input [X-1:0] xa,
input [X-1:0] xb,
input [X-1:0] cb,
output sometype_t [1:0] st,
input [X*Y-1:0] yb,
output foobar
);
endmodule // xx
module yy
#(parameter X=4,
parameter Y=1)
(input clk,
input rstb,
output [X-1:0][1:0] xc,
output [X-1:0] xa,
input [X-1:0] xb,
input [X-1:0] cb,
input sometype_t [1:0] st,
output [X*Y-1:0] yb,
output [4:0][2:0] foobar2
);
endmodule // xx
// Local Variables:
// verilog-typedef-regexp:"_t$"
// verilog-library-directories:("." )
// verilog-library-extensions:(".v" ".sv" ".h" ".vr" ".vm")
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_unsigned_bug302.v 0000664 0000000 0000000 00000001030 13022141775 0023566 0 ustar 00root root 0000000 0000000 module autoinst_unsigned_bug302;
Sub #(/*AUTOINSTPARAM*/) u_Abc
(/*AUTOINST*/);
endmodule
module Sub
#(
parameter No1 = 6,
parameter int unsigned No2 // Parameter no. 2
= pa_Abc::No2,
parameter bit No3 [No1:0][No2-1:0] // Parameter no. 3
= pa_Abc::No3
)
(
input logic ck,
input logic [No1-1:0][31:0] abc
input logic [No1-1:0][31:0] abc
);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_vertrees.v 0000664 0000000 0000000 00000000600 13022141775 0022531 0 ustar 00root root 0000000 0000000 module autoinst_vertrees
(/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*
autoinst_vertrees_slv AUTO_TEMPLATE "u_slv_\([a-z]\)"
(.i2c_\(.*\) (i2c_@_\1),
.slv_\(.*\) (slv_@_\1),
.rpt_\(.*\) (rpt_@_\1),
)
*/
autoinst_vertrees_slv u_slv_a
(/*AUTOINST*/);
autoinst_vertrees_slv u_slv_b
(/*AUTOINST*/);
endmodule // ddc
verilog-mode-20161124.fd230e6/tests/autoinst_vertrees_slv.v 0000664 0000000 0000000 00000004273 13022141775 0023427 0 ustar 00root root 0000000 0000000
module autoinst_vertrees_slv
(/*AUTOARG*/
// Outputs
i2c_mst_data, i2c_read, i2c_slv_scl_out, i2c_slv_sda_out, i2c_spc_scl_state, i2c_start,
i2c_strobe, slv_bit_st, slv_put, i2c_spc_scl_fall, i2c_spc_sda_state, i2c_spc_start,
i2c_spc_stop,
// Inputs
ck_ref, i2c_slv_data, i2c_slv_scl_in, i2c_slv_sda_in, r_i2c_spc_scl_low, rpt_hold, rpt_sda,
rst_ref, test_mode
);
input ck_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
input [7:0] i2c_slv_data; // To u_misc of ddc_slv_misc.v
input i2c_slv_scl_in; // To u_spc of i2c_slv_pin_ctrl.v
input i2c_slv_sda_in; // To u_spc of i2c_slv_pin_ctrl.v
input [4:0] r_i2c_spc_scl_low; // To u_spc of i2c_slv_pin_ctrl.v
input rpt_hold; // To u_misc of ddc_slv_misc.v
input rpt_sda; // To u_misc of ddc_slv_misc.v
input rst_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
input test_mode; // To u_spc of i2c_slv_pin_ctrl.v
output [7:0] i2c_mst_data; // From u_misc of ddc_slv_misc.v
output i2c_read; // From u_misc of ddc_slv_misc.v
output i2c_slv_scl_out; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_slv_sda_out; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_scl_state; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_start; // From u_misc of ddc_slv_misc.v
output i2c_strobe; // From u_misc of ddc_slv_misc.v
output slv_bit_st; // From u_misc of ddc_slv_misc.v
output slv_put; // From u_misc of ddc_slv_misc.v
output i2c_spc_scl_fall; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_sda_state; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_start; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_stop; // From u_spc of i2c_slv_pin_ctrl.v
endmodule // ddc_slv
verilog-mode-20161124.fd230e6/tests/autoinst_vkadamby.v 0000664 0000000 0000000 00000000351 13022141775 0022473 0 ustar 00root root 0000000 0000000 module autoinst_vkadamby ( /*AUTOARG*/);
child1 #(.lengthM2(100)) I34 (/*AUTOINST*/
// Inputs
.x (x));
endmodule
module child1 (/*AUTOARG*/
// Inputs
x
);
input x;
parameter lengthM2;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_width.v 0000664 0000000 0000000 00000001235 13022141775 0022016 0 ustar 00root root 0000000 0000000 module ex;
/* subwidth AUTO_TEMPLATE (
.bus1a(@"vl-width"'b0),
.bus1b(@"vl-width"'b0),
.bus4a(@"vl-width"'b0),
.bus4b(@"vl-width"'b0),
.busdef(@"vl-width"'b0),
);*/
subwidth u_a2(/*AUTOINST*/
// Outputs
.bus4a (4'b0), // Templated
.bus4b (4'b0), // Templated
.bus1a (1'b0), // Templated
.bus1b (1'b0), // Templated
.busdef ((1+(`defa)-(`defb))'b0)); // Templated
endmodule
module subwidth (/*AUTOARG*/
// Outputs
bus4a, bus4b, bus1a, bus1b, busdef
);
output [0:3] bus4a;
output [7:4] bus4b;
output bus1a;
output [0:0] bus1b;
output [`defa:`defb] busdef;
endmodule
verilog-mode-20161124.fd230e6/tests/autoinst_wildcard.v 0000664 0000000 0000000 00000003610 13022141775 0022467 0 ustar 00root root 0000000 0000000 module autoinst_wildcard;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
// Newline between AUTO_TEMPLATE and ( gave a templated line number bug
/* autoinst_wildcard_sub AUTO_TEMPLATE
(
.sd0_clk (sd_clk),
.sd0_dqm\(.*\)_l (c@_sd_dqm_[\1]),
.sd0_ba\([0-9]+\) (c@_sd_ba[\1]),
.sd0_adrs@ (c@_sd_adrs[\1]),
.ics@ (c@_ics[\1]),
); */
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
autoinst_wildcard_sub sub0
(/*AUTOINST*/
// Inouts
.sd_ras_ (sd_ras_),
.sd0_dqm7_l (c0_sd_dqm_[7]), // Templated 9
.sd0_dqm6_l (c0_sd_dqm_[6]), // Templated 9
.sd0_dqm5_l (c0_sd_dqm_[5]), // Templated 9
.sd0_dqm4_l (c0_sd_dqm_[4]), // Templated 9
.sd0_dqm3_l (c0_sd_dqm_[3]), // Templated 9
.sd0_dqm2_l (c0_sd_dqm_[2]), // Templated 9
.sd0_dqm1_l (c0_sd_dqm_[1]), // Templated 9
.sd0_dqm0_l (c0_sd_dqm_[0]), // Templated 9
.sd0_ba1 (c0_sd_ba[1]), // Templated 10
.sd0_ba0 (c0_sd_ba[0]), // Templated 10
.sd0_adrs11 (c0_sd_adrs[11]), // Templated 11
.sd0_adrs10 (c0_sd_adrs[10]), // Templated 11
.sd0_adrs9 (c0_sd_adrs[9]), // Templated 11
.sd0_adrs8 (c0_sd_adrs[8]), // Templated 11
.sd0_adrs7 (c0_sd_adrs[7]), // Templated 11
.sd0_adrs6 (c0_sd_adrs[6]), // Templated 11
.sd0_adrs5 (c0_sd_adrs[5]), // Templated 11
.sd0_adrs4 (c0_sd_adrs[4]), // Templated 11
.sd0_adrs3 (c0_sd_adrs[3]), // Templated 11
.sd0_adrs2 (c0_sd_adrs[2]), // Templated 11
.sd0_adrs1 (c0_sd_adrs[1]), // Templated 11
.sd0_adrs0 (c0_sd_adrs[0]), // Templated 11
.sd0_clk (sd_clk)); // Templated 8
endmodule
// Local Variables:
// verilog-auto-inst-template-numbers: t
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v 0000664 0000000 0000000 00000002320 13022141775 0023335 0 ustar 00root root 0000000 0000000 module autoinst_wildcard_sub (/*AUTOARG*/
// Inouts
sd_ras_, sd0_dqm7_l, sd0_dqm6_l, sd0_dqm5_l, sd0_dqm4_l, sd0_dqm3_l,
sd0_dqm2_l, sd0_dqm1_l, sd0_dqm0_l, sd0_ba1, sd0_ba0, sd0_adrs11,
sd0_adrs10, sd0_adrs9, sd0_adrs8, sd0_adrs7, sd0_adrs6, sd0_adrs5,
sd0_adrs4, sd0_adrs3, sd0_adrs2, sd0_adrs1, sd0_adrs0, sd0_clk
);
//======================================================================
// Inputs/Outputs
//======================================================================
inout sd_ras_; // SDRAM Channel 0 Row Address Strobe
inout sd0_dqm7_l; // SDRAM Channel 0 DQM Mask Bits
inout sd0_dqm6_l;
inout sd0_dqm5_l;
inout sd0_dqm4_l;
inout sd0_dqm3_l;
inout sd0_dqm2_l;
inout sd0_dqm1_l;
inout sd0_dqm0_l;
inout sd0_ba1;
inout sd0_ba0;
inout sd0_adrs11; // SDRAM Channel 0 Address
inout sd0_adrs10;
inout sd0_adrs9;
inout sd0_adrs8;
inout sd0_adrs7;
inout sd0_adrs6;
inout sd0_adrs5;
inout sd0_adrs4;
inout sd0_adrs3;
inout sd0_adrs2;
inout sd0_adrs1;
inout sd0_adrs0;
inout sd0_clk; // SDRAM Channel 0 Clocks
endmodule
// Local Variables:
// fill-column: 79
// End:
verilog-mode-20161124.fd230e6/tests/autoinst_wildcell.v 0000664 0000000 0000000 00000001135 13022141775 0022475 0 ustar 00root root 0000000 0000000 module autoinst_wildcard;
/* sub AUTO_TEMPLATE (
.a\(.\)\(.\) (@"(substring vl-cell-name 4 5)"_@"(substring vl-cell-name 6 7)"_a_\1_\2),
); */
sub sub_0_0 (/*AUTOINST*/);
sub sub_0_1 (/*AUTOINST*/);
sub sub_1_0 (/*AUTOINST*/);
sub sub_1_1 (/*AUTOINST*/);
/* sub AUTO_TEMPLATE (
.a\(.\)\(.\) (b_\1_\2),
); */
sub sub_0_0 (/*AUTOINST*/);
sub sub_0_1 (/*AUTOINST*/);
sub sub_1_0 (/*AUTOINST*/);
sub sub_1_1 (/*AUTOINST*/);
endmodule
module sub;
input a33, a34, a44, a43;
endmodule
// Local Variables:
// verilog-auto-inst-template-numbers: t
// End:
verilog-mode-20161124.fd230e6/tests/autoinstparam_belkind.v-dontrun 0000664 0000000 0000000 00000000574 13022141775 0025024 0 ustar 00root root 0000000 0000000 module autoinstparam_belkind (/*AUTOARG*/) ;
parameter X = 8;
/*
autoinstparam_belkind_leaf AUTO_TEMPLATE (
.P (X),
.a (b[]),
);
*/
autoinstparam_belkind_leaf (/*AUTOINSTPARAM*/)
leaf(/*AUTOINST*/);
endmodule // tree
// Local Variables:
// eval:(verilog-read-defines)
// eval:(verilog-read-defines "autoinstparam_belkind_leaf.v")
// End:
verilog-mode-20161124.fd230e6/tests/autoinstparam_belkind_leaf.v 0000664 0000000 0000000 00000000254 13022141775 0024317 0 ustar 00root root 0000000 0000000 module autoinstparam_belkind_leaf (/*AUTOARG*/) ;
parameter P =3D 4;
input [P-1:0] a;
endmodule // leaf
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/autoinstparam_bug287.v 0000664 0000000 0000000 00000000337 13022141775 0022740 0 ustar 00root root 0000000 0000000 module Ptest #(
parameter I_CONTROL = 8'h 00, R_CONTROL = 8'h00)
(
input scanTest,
input scanArst);
endmodule
module t;
Ptest
#(/*AUTOINSTPARAM*/)
u_Ptest
(/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinstparam_first.v 0000664 0000000 0000000 00000001411 13022141775 0023043 0 ustar 00root root 0000000 0000000 module autoinstparam_first ();
parameter BITSCHANGED;
parameter BITSA;
parameter type BITSB_t;
typedef [2:0] my_bitsb_t;
/* autoinstparam_first_sub AUTO_TEMPLATE (
.BITSA (BITSCHANGED),
); */
autoinstparam_first_sub
#(/*AUTOINSTPARAM*/)
sub
(/*AUTOINST*/);
autoinstparam_first_sub
#(
.BITSB_t (my_bitsb_t),
/*AUTOINSTPARAM*/)
sub1
(/*AUTOINST*/);
autoinstparam_first_sub
#(
.BITSA (1),
.BITSB_t (my_bitsb_t)
/*AUTOINSTPARAM*/)
sub2
(/*AUTOINST*/);
autoinstparam_first_sub
#(
/*AUTOINSTPARAM*/)
sub3
(/*AUTOINST*/);
endmodule
// Local Variables:
// verilog-auto-inst-param-value:nil
// verilog-typedef-regexp: "_t$"
// End:
verilog-mode-20161124.fd230e6/tests/autoinstparam_first_sub.v 0000664 0000000 0000000 00000000706 13022141775 0023722 0 ustar 00root root 0000000 0000000 module autoinstparam_first_sub (/*AUTOARG*/
// Inouts
a, b
);
//======================================================================
// Inputs/Outputs
//======================================================================
localparam IGNORED;
parameter BITSA;
parameter type BITSB_t = bit; // See bug340
inout [BITSA:0] a;
inout BITSB_t b;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
verilog-mode-20161124.fd230e6/tests/autoinstparam_iface_bruce.v 0000664 0000000 0000000 00000000422 13022141775 0024144 0 ustar 00root root 0000000 0000000 module top;
/*AUTOWIRE*/
sub0 #(/*AUTOINSTPARAM*/)
s0 (/*AUTOINST*/);
endmodule
module sub0
#(
parameter string testit2 = 0,
int TESTIT = 0
) (
// clk and resets
input logic side_clk,
input logic side_rst_b,
);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinstparam_int.v 0000664 0000000 0000000 00000000661 13022141775 0022514 0 ustar 00root root 0000000 0000000 module xyz
#(parameter int FOO=1, BAR=2,
parameter logic [5:0] BLUP=3, ZOT=4,
parameter LDWRDS=5)
( input x1, x2,
input int i1, i2,
input logic [5:0] i3, i4,
input i5,
output y);
endmodule
module pdq;
input x; output y;
parameter int FOO=1;
endmodule
module abc;
xyz XYZ
#(/*AUTOINSTPARAM*/)
(/*AUTOINST*/);
pdq PDQ
#(/*AUTOINSTPARAM*/)
(/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autoinstparam_local.v 0000664 0000000 0000000 00000000714 13022141775 0023013 0 ustar 00root root 0000000 0000000 //bug889
module leaf #(
parameter DATA_WIDTH = 256,
localparam STRB_WIDTH_SHOULD_BE_HIDDEN = DATA_WIDTH/8 )
();
endmodule
module test;
parameter integer DATA_WIDTH = 256;
parameter integer STRB_WIDTH = DATA_WIDTH/8;
/* leaf AUTO_TEMPLATE (
.DATA_WIDTH( DATA_WIDTH ),
.STRB_WIDTH_SHOULD_BE_HIDDEN ( STRB_WIDTH ),
.\(.*\) ( \1 ),
);*/
leaf
#( /*AUTOINSTPARAM*/)
u_leaf
( /*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autolisp_include.v 0000664 0000000 0000000 00000000657 13022141775 0022323 0 ustar 00root root 0000000 0000000 // See forum topic 176
module autolisp_include (/*AUTOARG*/
// Outputs
foo,
// Inputs
bar
);
//`include "autolisp_include_inc.vh"
/*AUTOINSERTLISP(verilog-library-filenames (insert-file "autolisp_include_inc.vh"))*/
// Beginning of automatic insert lisp
input bar;
output foo;
// End of automatics
assign foo = bar;
// This doesn't need commentary
/*AUTOINSERTLISP(when nil)*/
endmodule
verilog-mode-20161124.fd230e6/tests/autolisp_include_inc.vh 0000664 0000000 0000000 00000000033 13022141775 0023310 0 ustar 00root root 0000000 0000000 input bar;
output foo;
verilog-mode-20161124.fd230e6/tests/autolisp_order_bug356.v 0000664 0000000 0000000 00000002026 13022141775 0023076 0 ustar 00root root 0000000 0000000 module autolisp_top (/*AUTOARG*/);
/* autolisp_inst AUTO_TEMPLATE (
.\(.*\)A (\1_@"(eval tense)"_A),
.\(.*\)B (\1_@"(eval tense)"_B),
);
*/
/* AUTO_LISP(setq tense "is") */
autolisp_inst AUTOLISP_INST_I0
(/*AUTOINST*/
// Outputs
.result (result),
// Inputs
.portA (port_is_A), // Templated
.busA (bus_is_A), // Templated
.portB (port_is_B), // Templated
.busB (bus_is_B)); // Templated
/* AUTO_LISP(setq tense "was") */
autolisp_inst AUTOLISP_INST_I1
(/*AUTOINST*/
// Outputs
.result (result),
// Inputs
.portA (port_was_A), // Templated
.busA (bus_was_A), // Templated
.portB (port_was_B), // Templated
.busB (bus_was_B)); // Templated
endmodule
module autolisp_inst (/*AUTOARG*/
// Outputs
result,
// Inputs
portA, busA, portB, busB
);
input portA;
input [3:0] busA;
input portB;
input [1:0] busB;
output result;
endmodule
verilog-mode-20161124.fd230e6/tests/autolisp_truex.v 0000664 0000000 0000000 00000000577 13022141775 0022050 0 ustar 00root root 0000000 0000000 module ExampInsertLisp;
/*AUTOINSERTLISP(my-verilog-insert-hello "world")*/
// Try an empty insert
/*AUTOINSERTLISP(+ 1)*/
// Try a shell command
/*AUTOINSERTLISP(insert (shell-command-to-string "echo //hello"))*/
endmodule
/*
Local Variables:
eval:
(defun my-verilog-insert-hello (who)
(insert (concat "initial $write(\"hello " who "\");\n")))
End:
*/
verilog-mode-20161124.fd230e6/tests/autologic.sv 0000664 0000000 0000000 00000004710 13022141775 0021123 0 ustar 00root root 0000000 0000000 module top
#(parameter COLS = 4
)
( input logic clk,
input logic rstb,
input logic [COLS-1:0] ival,
input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
output logic reg_assigned
);
// Request: AUTOLOGIC instead of AUTOWIRE
// Request: AUTOLOGIC would substitute all 3 existing macros AUTOWIRE/AUTOREG/AUTOREGINPUT, one would use AUTOLOGIC instead of AUTOWIRE/AUTOREG or AUTOWIRE/AUTOREGINPUT.
// Could use AU-TOLOGIC
// Or AU-TOWIRE(logic)
// And-or (setq verilog-auto-sv t)
// And-or (setq verilog-auto-wire-type 'logic')
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output logic COLS;
output logic in1a; // To isub2 of sub2.v, ...
output logic in1b; // To isub1 of sub1.v
output logic in2b; // To isub2 of sub2.v
output logic out1a; // From isub1 of sub1.v
output logic [1:0] out1b; // From isub1 of sub1.v
output logic [1:0] out2b; // From isub2 of sub2.v
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
logic reg_assigned;
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
logic in1a; // To isub2 of sub2.v, ...
logic in1b; // To isub1 of sub1.v
logic in2b; // To isub2 of sub2.v
// End of automatics
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic out1a; // From isub1 of sub1.v
logic [1:0] out1b; // From isub1 of sub1.v
logic [1:0] out2b; // From isub2 of sub2.v
// End of automatics
/* sub2 AUTO_TEMPLATE(
.idata_some_extra_sig_length ( s1_odata),
.ival ( s1_oval),
);*/
sub2 isub2 (/*AUTOINST*/
// Outputs
.out2b (out2b[1:0]),
// Inputs
.in1a (in1a),
.in2b (in2b),
.out1a (out1a));
sub1 isub1(/*AUTOINST*/
// Outputs
.out1a (out1a),
.out1b (out1b[1:0]),
// Inputs
.in1a (in1a),
.in1b (in1b));
always @(posedge clk) begin
reg_assigned <= 1;
end
endmodule
module sub1
( input logic in1a,
input logic in1b,
output logic out1a,
output logic [1:0] out1b
);
endmodule
module sub2
( input logic in1a,
input logic in2b,
input logic out1a,
output logic [1:0] out2b
);
endmodule
// Local Variables:
// verilog-auto-wire-type: "logic"
// End:
verilog-mode-20161124.fd230e6/tests/automodport_ex.v 0000664 0000000 0000000 00000001176 13022141775 0022026 0 ustar 00root root 0000000 0000000 interface ExampIf
( input logic clk );
logic req_val;
logic [7:0] req_dat;
clocking mon_clkblk @(posedge clk);
input req_val;
input req_dat;
endclocking
modport mp(clocking mon_clkblk);
endinterface
module ExampMain
( input clk,
/*AUTOINOUTMODPORT("ExampIf" "mp")*/
// Beginning of automatic in/out/inouts (from modport)
input req_val,
input [7:0] req_dat
// End of automatics
);
/*AUTOASSIGNMODPORT("ExampIf" "mp" "inst")*/
// Beginning of automatic assignments from modport
assign inst.req_dat = req_dat;
assign inst.req_val = req_val;
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests/automodport_full.v 0000775 0000000 0000000 00000002770 13022141775 0022360 0 ustar 00root root 0000000 0000000
module auto_module
( input my_clk,
input my_rst_n,
output manually_listed,
/*AUTOINOUTMODPORT("automodport_if" "pure_mp")*/
//ex: input in_pure;
//ex: output out_pure;
/*AUTOINOUTMODPORT("automodport_if" "req_mon_mp")*/
//ex: input req_credit, // To auto_i of auto_intf.sv
//ex: input [63:0] req_data, // To auto_i of auto_intf.sv
//ex: input req_val, // To auto_i of auto_intf.sv
/*AUTOINOUTMODPORT("automodport_if" "rsp_drv_mp")*/
//ex: output [1:0] rsp_cmd, // From auto_i of auto_intf.sv
//ex: input rsp_credit, // To auto_i of auto_intf.sv
//ex: output [63:0] rsp_data // From auto_i of auto_intf.sv
);
auto_intf auto_i
(// Inputs
.clk (my_clk),
.rst_n (my_rst_n));
/*AUTOASSIGNMODPORT("automodport_if" "req_mon_mp" "auto_i" )*/
//ex: assign auto_i.req_credit = req_credit;
//ex: assign auto_i.req_data = req_data;
//ex: assign auto_i.req_val = req_val;
/*AUTOASSIGNMODPORT("automodport_if" "rsp_drv_mp" "auto_i" )*/
//ex: assign rsp_cmd = auto_i.rsp_cmd;
//ex: assign rsp_data = auto_i.rsp_data;
//ex: assign auto_i.rsp_credit = rsp_credit;
/*AUTOASSIGNMODPORT("automodport_if" "r.*" "auto_i" )*/
initial begin
`cn_set_intf(virtual auto_intf.req_mon_mp, "auto_pkg::auto_intf", "req_mon_vi", auto_i.req_mon_mp );
`cn_set_intf(virtual auto_intf.rsp_drv_mp, "auto_pkg::auto_intf", "rsp_drv_vi", auto_i.rsp_drv_mp );
end
endmodule
verilog-mode-20161124.fd230e6/tests/automodport_if.v 0000664 0000000 0000000 00000004232 13022141775 0022004 0 ustar 00root root 0000000 0000000 interface automodport_if
( input logic clk,
input logic rst_n
);
//----------------------------------------------------------------------------------------
// Group: Signals
logic req_val;
logic [63:0] req_dat;
logic req_credit;
logic [1:0] rsp_cmd;
logic [63:0] rsp_data;
logic rsp_credit;
logic in_pure;
logic out_pure;
logic manually_listed;
//----------------------------------------------------------------------------------------
// Group: Clocking blocks
clocking req_mon_cb @(posedge clk);
input rst_n;
input req_val;
input req_dat;
input req_credit;
input manually_listed;
endclocking : req_mon_cb
clocking rsp_drv_cb @(posedge clk);
input rst_n;
output rsp_cmd;
output rsp_data;
input rsp_credit;
endclocking : rsp_drv_cb
//----------------------------------------------------------------------------------------
// Group: Modports
modport req_mon_mp(clocking req_mon_cb);
modport rsp_drv_mp(clocking rsp_drv_cb, import rsp_reset);
modport pure_mp(input in_pure, output out_pure);
//----------------------------------------------------------------------------------------
// Group: Methods
function void rsp_reset();
rsp_cmd = 2'b0;
rsp_data = 64'b0;
endfunction : rsp_reset
//----------------------------------------------------------------------------------------
// Group: Assertions
logic [1:0] cmd_m1;
always @(posedge clk) begin
cmd_m1 <= rsp_cmd;
if(rst_n) begin
if($isunknown(req_val)) `cn_err_intf(("Signal req_data_cycle is an X."));
if(req_val==1'b1 & $isunknown(req_data)) `cn_err_intf(("Signal req_data is an X."));
if($isunknown(req_credit)) `cn_err_intf(("Signal req_credit is an X."));
if($isunknown(rsp_cmd)) `cn_err_intf(("Signal rsp_cmd is an X."));
if(cmd_m1!=2'b0 & $isunknown(rsp_data)) `cn_err_intf(("Signal rsp_data is an X."));
if($isunknown(rsp_credit)) `cn_err_intf(("Signal rsp_credit is an X."));
end
end
endinterface
verilog-mode-20161124.fd230e6/tests/autooutput_comma.v 0000664 0000000 0000000 00000001115 13022141775 0022353 0 ustar 00root root 0000000 0000000 module top
(input [(`WIDTH):0] a, /* This comma gets deleted */
/*AUTOOUTPUT*/
/*AUTOINPUT*/
);
child child(/*AUTOINST*/);
endmodule
module nocomma
(/*AUTOOUTPUT*/
/*AUTOINPUT*/
);
child child(/*AUTOINST*/);
endmodule
module ifdefcomma
(
`ifdef a
input foo,
`endif
/*AUTOOUTPUT*/
/*AUTOINPUT*/
);
child child(/*AUTOINST*/);
endmodule
module ifdefnocomma
(
`ifdef a
// It's up to the user to deal with the , themself
input foo,
`endif
/*AUTOOUTPUT*/
);
child child(/*AUTOINST*/);
endmodule
module child(input b);
endmodule
verilog-mode-20161124.fd230e6/tests/autooutput_regexp.v 0000664 0000000 0000000 00000001173 13022141775 0022555 0 ustar 00root root 0000000 0000000 module ex_output_every (/*AUTOARG*/
// Outputs
sub1_out_pixel
)
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output pixel24_t sub1_out_pixel; // From i1 of v2k_typedef_yee_sub1.v
// End of automatics
v2k_typedef_yee_sub1 i1
(/*AUTOINST*/
// Outputs
.sub1_out_pixel (sub1_out_pixel),
.sub1_to_sub2 (sub1_to_sub2),
.sub1_to_sub2_and_top (sub1_to_sub2_and_top),
// Inputs
.sub1_in_pixel (sub1_in_pixel),
.cp (cp),
.reset (reset));
endmodule
// Local Variables:
// verilog-auto-output-ignore-regexp:"^sub1_to_sub2"
// End:
verilog-mode-20161124.fd230e6/tests/autooutputevery_assign.v 0000664 0000000 0000000 00000000504 13022141775 0023617 0 ustar 00root root 0000000 0000000 module ex_output_every (o,i,tempa,tempb)
output o;
input i;
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output tempa;
output tempb;
// End of automatics
wire tempa;
wire tempb;
wire o;
assign tempa = i;
assign tempb = tempa;
assign o = tempb;
endmodule
verilog-mode-20161124.fd230e6/tests/autooutputevery_example.v 0000664 0000000 0000000 00000000425 13022141775 0023770 0 ustar 00root root 0000000 0000000 module ex_output_every (o,i,tempa,tempb)
output o;
input i;
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output tempa;
output tempb;
// End of automatics
wire tempa = i;
wire tempb = tempa;
wire o = tempb;
endmodule
verilog-mode-20161124.fd230e6/tests/autooutputevery_regexp.v 0000664 0000000 0000000 00000000152 13022141775 0023624 0 ustar 00root root 0000000 0000000 module top
(
/*AUTOOUTPUTEVERY("^a")*/
);
wire aa;
wire ab;
wire cc;
endmodule
verilog-mode-20161124.fd230e6/tests/autooutputevery_wire.v 0000664 0000000 0000000 00000002761 13022141775 0023310 0 ustar 00root root 0000000 0000000 module test (/*AUTOARG*/
// Outputs
stage3_bus,
// Inputs
stage1_bus
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output logic [7:0] stage3_bus; // From i_second of sub_module.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic [7:0] stage1_bus; // To i_first of sub_module.v
// End of automatics
/*AUTOOUTPUTEVERY("^stage")*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [7:0] stage2_bus; // From i_first of sub_module.v
// End of automatics
/*AUTOREG*/
/* sub_module AUTO_TEMPLATE
(
.i_\(.*\) (stage1_\1[]),
.o_\(.*\) (stage2_\1[]),
); */
sub_module i_first (/*AUTOINST*/
// Outputs
.o_bus (stage2_bus[7:0]), // Templated
// Inputs
.i_bus (stage1_bus[7:0])); // Templated
/* sub_module AUTO_TEMPLATE
(
.i_\(.*\) (stage2_\1[]),
.o_\(.*\) (stage3_\1[]),
); */
sub_module i_second (/*AUTOINST*/
// Outputs
.o_bus (stage3_bus[7:0]), // Templated
// Inputs
.i_bus (stage2_bus[7:0])); // Templated
endmodule // test
module sub_module (/*AUTOARG*/
// Outputs
o_bus,
// Inputs
i_bus
);
input logic [7:0] i_bus ;
output logic [7:0] o_bus ;
assign o_bus = i_bus;
endmodule // sub_module
verilog-mode-20161124.fd230e6/tests/autoreg_outreg.v 0000664 0000000 0000000 00000001127 13022141775 0022004 0 ustar 00root root 0000000 0000000 module foo
#(parameter
PARAM3_P=99)
(
output sig3,// Here, I've hit "tab" twice and this line is correct
output reg [PARAM2_P-1:0] s4, // Comment here which should be at "comment-column"
output wire [PARAM2_P-1:0] sig5,// Comment here which should be at "comment-column"
input reset_L// module reset: global register
);
/*AUTOWIRE*/
// AUTOREG here is somewhat illegal, as outputs when a type is declared
// in a V2K decl list are automatically "reg'ed".
// However some simulators take it, so be sane and only do undeclared ones...
/*AUTOREG*/
endmodule
verilog-mode-20161124.fd230e6/tests/autoreg_smith_multiassign.v 0000664 0000000 0000000 00000000405 13022141775 0024240 0 ustar 00root root 0000000 0000000 module test(/*AUTOARG*/
// Outputs
a1, b1, c1, one
);
output [5:0] a1;
output [5:0] b1;
output [5:0] c1;
/*AUTOREG*/
//wire [5:0] a2,b2,c2;
assign {a1,b1,c1} = {a2,b2,c2};
output [1:0] one;
assign one = a2[0];
endmodule
verilog-mode-20161124.fd230e6/tests/autoreginput.v 0000664 0000000 0000000 00000001073 13022141775 0021477 0 ustar 00root root 0000000 0000000 module autoreginput;
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg lower_ina; // To inst of inst.v
reg lower_inb; // To inst of inst.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire lower_out; // From inst of inst.v
// End of automatics
inst inst (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
// Inputs
.lower_inb (lower_inb),
.lower_ina (lower_ina));
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_assert.v 0000664 0000000 0000000 00000000542 13022141775 0022345 0 ustar 00root root 0000000 0000000 module foo;
reg [1:0] a;
assert property (@(posedge clk) e |-> f);
reg [1:0] b;
always @(posedge clk, negedge rst)
if (~rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= 2'h0;
b <= 2'h0;
// End of automatics
end
else begin
a<=b;
b<=a;
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_cond.v 0000664 0000000 0000000 00000000742 13022141775 0021771 0 ustar 00root root 0000000 0000000 module x;
reg [1:0] idx_sel_2a;
always @(posedge usclk or negedge srst_0a_n) begin
if (~srst_0a_n) begin
/*AUTORESET*/
end
else begin
foo <= idx_adr_1a[1:0];
bar <= (idx_sel_2a == 2'h0 ? idx_rd_dat0_2a[12:0] :
idx_sel_2a == 2'h1 ? idx_rd_dat1_2a[12:0] :
idx_sel_2a == 2'h2 ? idx_rd_dat2_2a[12:0] :
/**/ idx_rd_dat3_2a[12:0]);
end
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_define_colon.v 0000664 0000000 0000000 00000001131 13022141775 0023463 0 ustar 00root root 0000000 0000000 // bug594
`define TABADR_EGR_MOD_MAP 7:0
module test (
/*AUTOARG*/
// Inputs
clk, rst, addr
);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
input clk;
input rst;
input[`TABADR_EGR_MOD_MAP] addr;
reg [`TABADR_EGR_MOD_MAP] addrD1;
reg [`TABADR_EGR_MOD_MAP] addrD2;
always @(posedge clk or posedge rst) begin
if (rst_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
addrD1 <= `0/*NOWIDTH*/;
addrD2 <= `0/*NOWIDTH*/;
// End of automatics
end
else begin
addrD1 <= addr ;
addrD2 <= addrD1;
end
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_dever.v 0000664 0000000 0000000 00000001545 13022141775 0022155 0 ustar 00root root 0000000 0000000 module x;
always @(posedge piclk) begin
if (k_i_reset) begin
/*AUTORESET*/
end
else begin
idat_ICErrData_i3 <= idat_way0_i2[1*OPCWID-1:0*OPCWID];
end
end
// 2010-04-08
localparam MPND = 5;
always @(posedge usclk)
if (~sso_srst_n) begin
/*AUTORESET*/
end
else begin
sel_s3 <= adr_s2[MIDX];
rd_dat_s4 <= (sel_s3 == 1'h0 ? rd_dat0_s3[MPND:0]
: rd_dat1_s3[MPND:0]);
end
// 2010-04-15
integer i;
always @(posedge usclk)
if (~sso_srst_n) begin
for (int j=0; j<10; j++) blob[j] <= 0;
/*AUTORESET*/
end
else begin
for (i=0; i<10; i++) blob[i] <= blob[i+1];
for (i=0; i<10; i++) zz <= 1;
for (int isv=0; isv<10; isv++) zsv <= 1;
end
always @(/*AS*/) begin
for (i=0; i<10; i++) zz <= in;
for (int isv=0; isv<10; isv++) zsv <= in;
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_eq_bug381.v 0000664 0000000 0000000 00000000762 13022141775 0022546 0 ustar 00root root 0000000 0000000 module t();
logic [31:0] sum;
logic [31:0] a;
logic [31:0] b;
reg [32:0] tmp;
always @(posedge clk or negedge rst) begin
if (!rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
sum <= 32'h0;
// End of automatics
end
else begin
//reg [32:0] tmp;
tmp = a + b;
if (tmp[32])
sum <= 32'hffffffff;
else
sum <= tmp[31:0];
end
end
endmodule
// Local Variables:
// verilog-auto-reset-blocking-in-non: nil
// End:
verilog-mode-20161124.fd230e6/tests/autoreset_eq_bug381_non.v 0000664 0000000 0000000 00000000777 13022141775 0023426 0 ustar 00root root 0000000 0000000 module t();
logic [31:0] sum;
logic [31:0] a;
logic [31:0] b;
reg [32:0] tmp;
always @(posedge clk or negedge rst) begin
if (!rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
sum <= 32'h0;
tmp = 33'h0;
// End of automatics
end
else begin
//reg [32:0] tmp;
tmp = a + b;
if (tmp[32])
sum <= 32'hffffffff;
else
sum <= tmp[31:0];
end
end
endmodule
// Local Variables:
// verilog-auto-reset-blocking-in-non: t
// End:
verilog-mode-20161124.fd230e6/tests/autoreset_equal_extra.v 0000664 0000000 0000000 00000001625 13022141775 0023361 0 ustar 00root root 0000000 0000000 module autoreset_equal_extra ();
always_ff @(posedge csclk) begin
if( ~srst_n | !val_tx_to_csi ) begin
csi.cmd <= ncbo_cmd_t'('0);
// vvvvvv fifo.data.cb_req.req.cmd = '0; should not be below
/*AUTORESET*/
end
else begin
if (fifo.sot) begin
csi.src <= fifo.src;
csi.wr <= (fifo.data.cb_req.req.cmd == ncb_defs::NCBO_RSVD_LMTST
| fifo.data.cb_req.req.cmd == ncb_defs::NCBO_IOBST
);
csi.cmd <= fifo.data.cb_req.req.cmd;
end
end
end
always_ff @(posedge csclk) begin
if (~srst_n) begin
/*AUTORESET*/
end
else begin
sdp__x2p.err <= (x2p_fifo_rdat.err & x2p_fifo_pop_d3_sk)
? x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_RCVERR
: x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_NONE;
sdp__x2p.bval <= x2p_fifo_rdat.bval & {4{x2p_fifo_pop_d3_sk}};
//FOO::bar <= 1; // Legal, though not typically used in RTL
end
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_if.v 0000664 0000000 0000000 00000003031 13022141775 0021436 0 ustar 00root root 0000000 0000000 //From: "Chris Kappler"
//Verilint 440 off // WARNING: Clock is used as a reset
//Verilint 394 off // WARNING: Multiple clocks in the always block
//Verilint 71 off // WARNING: Case statement without default clause
module x (/*AUTOARG*/
// Outputs
a, b, c,
// Inputs
clk, reset_l, in_a, in_b, in_c
);
input clk, reset_l, in_a,in_b,in_c;
output a,b,c;
reg a,b,c;
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
c <= 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= #1 0;
b <= #1 0;
// End of automatics
end
else begin
a <= in_a;
b <= in_b;
c <= in_c;
end
end
always @(posedge clk or negedge reset_l) begin
casex ({reset_l,in_a})
2'b1_x: begin
a <= in_a;
b <= in_b;
c <= in_c;
end
2'b0_x: begin
c <= 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= #1 0;
b <= #1 0;
// End of automatics
end
endcase
end
always @(/*AS*/in_a or in_b or reset_l) begin
casex ({reset_l,in_a})
2'b1_x: begin
a = in_a;
b = in_b;
end
2'b0_x: begin
c = 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a = 0;
b = 0;
// End of automatics
end
endcase
end
endmodule
// Local Variables:
// verilog-auto-reset-widths: nil
// verilog-assignment-delay: "#1 "
// End:
verilog-mode-20161124.fd230e6/tests/autoreset_ifndef_dc.v 0000664 0000000 0000000 00000000421 13022141775 0022741 0 ustar 00root root 0000000 0000000 module x;
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
c <= 1;
/*AUTORESET*/
end
else begin
a <= in_a;
b <= in_b;
c <= in_c;
`ifndef DC
x <= 1'b1;
`endif
end
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_inf_bug325.v 0000664 0000000 0000000 00000000231 13022141775 0022702 0 ustar 00root root 0000000 0000000 module aaa();
always @(a) begin
if (a) begin
/*AUTORESET*/
end
// note missing e-n-d
always @(*) begin
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_label_gorfajn.v 0000664 0000000 0000000 00000000334 13022141775 0023630 0 ustar 00root root 0000000 0000000 module autoreset_label_gorfajn;
always_ff @(posedge clk or negedge reset)
if (~reset) begin
/*AUTORESET*/
end else begin
a<=b;
foo: assert (b==4);
bar: z<=1;
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_latch.v 0000664 0000000 0000000 00000002135 13022141775 0022137 0 ustar 00root root 0000000 0000000 //bug844
module device(
input clk,
output logic [7:0] Q, out0,
output logic pass, fail
input [7:0] D, in0,in1 );
enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
logic ready, next_ready;
logic next_pass, next_fail;
always_ff @(posedge clk, negedge rstn)
if (!rstn) begin
state <= IDLE;
/*AUTORESET*/
end
else begin
state <= next_state;
ready <= next_ready;
pass <= next_pass;
fail <= next_fail;
end
always @* begin
if (!ready) begin
/*AUTORESET*/
end
else begin
out0 = sel ? in1 : in0;
end
end
always_comb begin
next_state = state;
/*AUTORESET*/
case (state)
IDLE : begin
// stuff ...
end
/* Other states */
PASS: begin
next_state = IDLE;
// stuff ...
next_pass = 1'b1;
next_ready = 1'b1;
end
FAIL: begin
next_state = IDLE;
// stuff ...
next_fail = 1'b1;
end
endcase
end
always_latch begin
if (!rstn) begin
/*AUTORESET*/
end
else if (clk) begin
Q <= D;
end
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_reed.v 0000664 0000000 0000000 00000000570 13022141775 0021764 0 ustar 00root root 0000000 0000000 module x;
reg a;
reg b;
reg c;
always @(/*AUTOSENSE*/) begin
if ( rst ) begin
/*AUTORESET*/
end
else begin
if ( a <= b ) begin
c = a;
end
else begin
c = b;
end
end
end
always @ (posedge a) begin
if ( rst ) begin
/*AUTORESET*/
end
else if ( a <= b ) begin
c <= a;
end
end
endmodule
verilog-mode-20161124.fd230e6/tests/autoreset_struct.v 0000664 0000000 0000000 00000002140 13022141775 0022364 0 ustar 00root root 0000000 0000000 //bug906
import gmcupkg::*;
module gminstdecode
(
output instClassType instClass
/*blah blah blah*/);
always_comb begin
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
instClass.sub.bool = 1'b1;
instClass.sub2.sub3.bool = 1'b1;
end
end
always_comb begin
instClass = '{default:0}; // #1 (see below)
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
end
end
always_comb begin
instClass.iFunc = IFUNC_ADD; // #2
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
end
end
always_comb begin
instClass.sub = '0;
instClass.sub2 = '0;
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.sub.bool = 1'b1;
instClass.sub2.sub3.bool = 1'b1;
instClass.sub3.sub4.bool = 1'b1;
end
end
endmodule
// Local Variables:
// verilog-auto-reset-widths: unbased
// verilog-typedef-regexp: "Type$"
// End:
verilog-mode-20161124.fd230e6/tests/autoreset_widths.v 0000664 0000000 0000000 00000002253 13022141775 0022347 0 ustar 00root root 0000000 0000000 // $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: t
// verilog-active-low-regexp: "_l$"
// End:
verilog-mode-20161124.fd230e6/tests/autoreset_widths_unbased.v 0000664 0000000 0000000 00000002261 13022141775 0024047 0 ustar 00root root 0000000 0000000 // $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: unbased
// verilog-active-low-regexp: "_l$"
// End:
verilog-mode-20161124.fd230e6/tests/autosense.v 0000664 0000000 0000000 00000001174 13022141775 0020761 0 ustar 00root root 0000000 0000000 module autosense (/*AUTOARG*/);
input ina;
input inb;
input inc;
output [1:0] out;
output out2;
/*AUTOREG*/
`include "autosense_inc_param.v"
`include "autosense_one.v"
`define Input ina
always @(/*AUTOSENSE*/) begin
case (inc)
1'b1: out = {`Input ? `one : 1'b0, `Input};
default: out = {2{inb}};
endcase
end
always @(/*AUTOSENSE*/) begin
out2 = `Input | PARAM_TWO | PARAM_THREE | PARAM_FOUR;
end
always @(*) begin
// @ (/*AS*/)
out3 = ina;
end
always @* begin
out3 = ina;
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/autosense_aas_ifdef.v 0000664 0000000 0000000 00000002370 13022141775 0022741 0 ustar 00root root 0000000 0000000 module dummy;
parameter [TSTBITS-1:0] // synopsys enum tstate_info
TIDLE = 3'b000,
TCN1 = 3'b001,
TCN2 = TCN1+1, // must be numbered consecutively
TCN3 = TCN2+1,
TCN4 = TCN3+1,
TCN5 = TCN4+1,
IOCLR = TCN5+1,
TUNU1 = 3'b111;
// state and output logic
always @ (`ifdef SIMFSM
ireset or
`endif
/*AUTOSENSE*/fooc2_qual or foocr_we or ioclrinst or tstate) begin
ioclrtmout = 1'b0;
case (tstate)
TIDLE: begin
if (foocr_we)
ntstate = TCN1;
else
ntstate = TIDLE;
end
TCN1,TCN2,TCN3,TCN4,TCN5: begin
if (ioclrinst | fooc2_qual)
ntstate = TIDLE;
else
ntstate = tstate + 1;
end
IOCLR: begin
ntstate = TIDLE;
ioclrtmout = 1'b1;
end
TUNU1: begin
ntstate = TIDLE;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unused state at %t",$time);
`endif
end
default: begin
ntstate = 'bx;
ioclrtmout = 1'bx;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unknown state at %t",$time);
`endif
end
endcase // case(tstate)
end // always @ (...
endmodule // dummy
verilog-mode-20161124.fd230e6/tests/autosense_add_or.v 0000664 0000000 0000000 00000000524 13022141775 0022267 0 ustar 00root root 0000000 0000000 module autosense_or(/*AUTOARG*/
// Outputs
x, y,
// Inputs
a, c
);
input a;
input c;
output x;
output y;
always @(a/*AUTOSENSE*/) begin
x = a;
end
always @(a/*AUTOSENSE*/ or c) begin
x = a | c;
end
// always @(a or/*AUTOSENSE*/c) begin
// x = a | c;
// end
endmodule
verilog-mode-20161124.fd230e6/tests/autosense_chadha.v 0000664 0000000 0000000 00000001072 13022141775 0022246 0 ustar 00root root 0000000 0000000 module test (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
sel, in0, in1, in2
);
input [1:0] sel;
input in0, in1, in2;
output out1;
output out2;
reg out1;
reg out2;
// Missing in2
always @ (/*AS*/in0 or in1 or in2 or sel)
if (sel == 2'b00)
begin
out1 = in1;
out2 = in0;
end
else
begin
out1 = in2;
out2 = in1;
end
// OK
always @ (/*AS*/in1 or in2 or sel)
if (sel == 2'b00)
out1 = in1;
else
out1 = in2;
endmodule // test
verilog-mode-20161124.fd230e6/tests/autosense_define_hang.v 0000664 0000000 0000000 00000000324 13022141775 0023264 0 ustar 00root root 0000000 0000000 //From: Anup Sharma
module x;
always @ (/*AS*/`EC_EXCLU or `EC_SHARE or jpack_share) begin
jb_mc_xact_state_a1[2:0] <= #1 jpack_share[7] ? `EC_SHARE : `EC_EXCLU;
end
endmodule
verilog-mode-20161124.fd230e6/tests/autosense_dittrich.v 0000664 0000000 0000000 00000000770 13022141775 0022654 0 ustar 00root root 0000000 0000000 module testcase
(/*AUTOARG*/
// Outputs
Z,
// Inputs
A, B, C, D, SEL
);
input A, B, C, D;
input [1:0] SEL;
output Z;
`include autosense_dittrich_inc.v
always @(/*AS*/A or B or C or D or SEL) begin
case (SEL)
sel_a: Z = A;
sel_b: Z = B;
sel_c: Z = C;
sel_d: Z = D;
default: Z = D;
endcase // case(SEL)
end // always @ (...
endmodule // testcase
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/autosense_dittrich_inc.v 0000664 0000000 0000000 00000000471 13022141775 0023503 0 ustar 00root root 0000000 0000000 parameter sel_a = {1'b 0, 1'b 0}; // 2'd 0 works fine
parameter sel_b = {1'b 0, 1'b 1}; // 2'd 1 works fine
parameter sel_c = 2'd 2,
sel_d = 2'd 3;
//parameter sel_a = {1'b 0, 1'b 0}, // 2'd 0 works fine
// sel_b = {1'b 0, 1'b 1}, // 2'd 1 works fine
// sel_c = 2'd 2,
// sel_d = 2'd 3;
verilog-mode-20161124.fd230e6/tests/autosense_gifford.v 0000664 0000000 0000000 00000002027 13022141775 0022457 0 ustar 00root root 0000000 0000000 module x (/*AUTOARG*/);
// Which Internal Bank
`define DMC_AG_HADDR_BADDR_BST2_RNG 1:0 // Bank Address Range within Hexabyte Address for 2-Burst
`define DMC_AG_HADDR_BADDR_BST4_RNG 2:1 // Bank Address Range within Hexabyte Address for 4-Burst
`define DMC_AG_HADDR_BADDR_BST8_RNG 3:2 // Bank Address Range within Hexabyte Address for 8-Burst
reg [NumBnks-1:0] ibnk_sel_s; // Muxed internal bank address subfield of
command address
always @(/*AUTOSENSE*/lio_buscfg_brstlen2_sr or lio_buscfg_brstlen4_sr or m_cdq_haddr_sr)
begin : PeelIntBnkAddr
case ({lio_buscfg_brstlen4_sr,lio_buscfg_brstlen2_sr})
2'b01: // 2-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST2_RNG];
end
2'b10: // 4-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST4_RNG];
end
default: // 8-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST8_RNG];
end
endcase
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/autosense_if_else.v 0000664 0000000 0000000 00000000341 13022141775 0022442 0 ustar 00root root 0000000 0000000 module x;
always @ (/*AS*/a or b or c)
if (a) q = b;
else r = c;
always @ (/*AS*/a or b or c or d or e)
if (a) q = b;
else if (c) r = d;
/* skip comments as usual */
else r = e;
endmodule
verilog-mode-20161124.fd230e6/tests/autosense_inandout.v 0000664 0000000 0000000 00000000240 13022141775 0022653 0 ustar 00root root 0000000 0000000 module autosense_inandout(a,b);
input a;
output b;
reg b;
reg c;
always @(/*AUTOSENSE*/a) begin
c=a;
b=c;
end
endmodule
verilog-mode-20161124.fd230e6/tests/autosense_inc_param.v 0000664 0000000 0000000 00000000123 13022141775 0022763 0 ustar 00root root 0000000 0000000
parameter [2:0] PARAM_TWO = 2,
PARAM_THREE = 3;
parameter PARAM_FOUR = 4;
verilog-mode-20161124.fd230e6/tests/autosense_jbrown.v 0000664 0000000 0000000 00000001341 13022141775 0022336 0 ustar 00root root 0000000 0000000 `define LCH_GSWDATWID 3
`define COM_CLDATWID 2
module autosense_jbrown(/*AUTOARG*/
// Outputs
lch_gswdata,
// Inputs
com_cldata
);
output [`LCH_GSWDATWID-1:0] lch_gswdata; // data to switch
input [`COM_CLDATWID-1:0] com_cldata; // data bus to clusters
/*autowire*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
reg tmp;
`define TEST_DEFINE 1'b0
always @ (/*AUTOSENSE*/)
begin
/* AUTO_CONSTANT (`TEST_DEFINE) */
tmp <= `TEST_DEFINE; // test defines
end
// Local Variables:
// verilog-library-directories:("." "../cdp/")
// verilog-library-extensions:(".v" ".vh")
// End:
endmodule
verilog-mode-20161124.fd230e6/tests/autosense_lavinge.v 0000664 0000000 0000000 00000000242 13022141775 0022461 0 ustar 00root root 0000000 0000000 module test
#(parameter FOO=1)
( a, b );
input a;
input b;
reg c;
wire d;
always @(/*AUTOSENSE*/)
begin
c=0;
if (d) c = b;
end
endmodule
verilog-mode-20161124.fd230e6/tests/autosense_mcardle_onehot.v 0000664 0000000 0000000 00000001361 13022141775 0024022 0 ustar 00root root 0000000 0000000 module x;
input [5:0] state;
output [5:0] next;
parameter CYCLEA = 1;
parameter CYCLEC = 2;
parameter MSTRA = 3;
parameter MSTRB = 4;
parameter MSTRC = 5;
// make sure 'state' is listed
always @ (/*AUTOSENSE*/done or nREQA or nREQB or nREQC or state) begin
next = 6'b0;
case (1'b1)
state[CYCLEC] : begin
if (!nREQA && done) next[MSTRA] = 1'b1;
else if (!nREQB && nREQA && done)next[MSTRB] = 1'b1;
else if (!nREQC && nREQA && nREQB && done) next[MSTRC] = 1'b1;
else next[CYCLEC] = 1'b1;
end
state[MSTRA] : begin
if (!nREQB || !nREQC) next[CYCLEA] = 1'b1;
else next[MSTRA] = 1'b1;
end
endcase
end
endmodule
verilog-mode-20161124.fd230e6/tests/autosense_metzger_space.v 0000664 0000000 0000000 00000001064 13022141775 0023667 0 ustar 00root root 0000000 0000000 module x (/*AUTOARG*/
// Outputs
rmsk0, rmsk1, rmsk2,
// Inputs
endbyte0, endbyte1, endbyte2, strtbyte0, strtbyte1, strtbyte2
);
input endbyte0;
input endbyte1;
input endbyte2;
input strtbyte0;
input strtbyte1;
input strtbyte2;
output rmsk0;
output rmsk1;
output rmsk2;
always @ (/*AS*/endbyte0 or strtbyte0) rmsk0 = maskcalc(strtbyte0,endbyte0);
always @ (/*AS*/endbyte1 or strtbyte1) rmsk1 = maskcalc(strtbyte1,endbyte1);
always @ (/*AS*/endbyte2 or strtbyte2) rmsk2 = maskcalc(strtbyte2,endbyte2);
endmodule
verilog-mode-20161124.fd230e6/tests/autosense_one.v 0000664 0000000 0000000 00000000022 13022141775 0021611 0 ustar 00root root 0000000 0000000 `define one 1'b1
verilog-mode-20161124.fd230e6/tests/autosense_peers_func.v 0000664 0000000 0000000 00000002363 13022141775 0023173 0 ustar 00root root 0000000 0000000 module x;
always @(/*AUTOSENSE*/arb_select_f or octet_idx) begin
octet_flag[0] = |arb_select_f[ 7: 0];
octet_flag[1] = |arb_select_f[15: 8];
octet_flag[2] = |arb_select_f[23:16];
octet_flag[3] = |arb_select_f[31:24];
octet_flag[4] = |arb_select_f[39:32];
octet_flag[5] = |arb_select_f[47:40];
octet_flag[6] = |arb_select_f[55:48];
octet_flag[7] = |arb_select_f[63:56];
octet_available = |octet_flag;
shifted8_64 = barrel_shifter(octet_flag, octet_idx[5:3]);
end // always @ (arb_select_f)
endmodule
function [7:0] barrel_shifter;
input [7:0] source;
input [2:0] shift_amt;
begin
case (shift_amt) //synopsys parallel_case full_case
3'b0: barrel_shifter = source;
3'b1: barrel_shifter = {source[0], source[7:1]};
3'b2: barrel_shifter = {source[1:0], source[7:2]};
3'b3: barrel_shifter = {source[2:0], source[7:3]};
3'b4: barrel_shifter = {source[3:0], source[7:4]};
3'b5: barrel_shifter = {source[4:0], source[7:5]};
3'b6: barrel_shifter = {source[5:0], source[7:6]};
3'b7: barrel_shifter = {source[6:0], source[7]};
endcase // case(shift_amt)
end
endfunction // barrel_shifter
verilog-mode-20161124.fd230e6/tests/autosense_rogoff.v 0000664 0000000 0000000 00000000200 13022141775 0022310 0 ustar 00root root 0000000 0000000
module x;
always @ (/*as*/a or ff)
case (a)
1: if (ff[3:0] == 4'd3)
sadfsdff;
endcase
endmodule
verilog-mode-20161124.fd230e6/tests/autosense_smith.v 0000664 0000000 0000000 00000003735 13022141775 0022172 0 ustar 00root root 0000000 0000000 module x;
reg [31:0] mb_reg_output;
// 16 registers max, register 15 is always the version number, so 15 are useable
// NOTE: number_interface_regs must be the maximum (or 16 in this case) to get the version register
parameter NUMBER_INTERFACE_REGS = 16;
parameter MB_REG_START = 3; // start at 4th register location 'h0010
parameter CMD_REG_0_ADDR = MB_REG_START;
parameter CMD_REG_1_ADDR = MB_REG_START+1;
parameter CMD_REG_2_ADDR = MB_REG_START+2;
parameter CMD_REG_3_ADDR = MB_REG_START+3;
parameter CMD_REG_4_ADDR = MB_REG_START+4;
parameter CMD_REG_5_ADDR = MB_REG_START+5;
parameter CMD_REG_6_ADDR = MB_REG_START+6;
parameter CMD_REG_7_ADDR = MB_REG_START+7;
parameter CMD_REG_8_ADDR = MB_REG_START+8;
parameter CMD_REG_9_ADDR = MB_REG_START+9;
parameter CMD_REG_10_ADDR = MB_REG_START+10;
// mode regs
parameter MODE_REG_0_ADDR = CMD_REG_8_ADDR;
// Absolute register 14 is Error counter
parameter CMD_REG_14_ADDR = 14;
parameter CRC_ERROR_REG_ADDR = CMD_REG_14_ADDR;
// ------------ VERSION register is 15
parameter VERSION_REG_ADDR = 15;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_wr;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_rd;
wire [31:0] mb_reg_out_w [NUMBER_INTERFACE_REGS-1:MB_REG_START];
wire [31:0] interface_from_core_fp;
assign
mb_reg_out_w[VERSION_REG_ADDR] = BUILD_VERSION;
integer mb_loop;
always @(/*AUTOSENSE*/)
begin: MB_READ_WRITE_SEL_P
mb_reg_wr = 'h0;
mb_reg_rd = 'h0;
mb_reg_output = interface_from_core_fp;
for(mb_loop = MB_REG_START; mb_loop < NUMBER_INTERFACE_REGS; mb_loop=mb_loop+1)
begin
if(mb_reg_select[mb_loop] == 1'b1)
begin
mb_reg_rd[mb_loop] = mb_reg_select[mb_loop] & mb_reg_rwn;
mb_reg_wr[mb_loop] = mb_reg_select[mb_loop] & !mb_reg_rwn;
mb_reg_output = mb_reg_out_w[mb_loop];
end
end
end
endmodule // x
verilog-mode-20161124.fd230e6/tests/autosense_venkataramanan_begin.v 0000664 0000000 0000000 00000000540 13022141775 0025170 0 ustar 00root root 0000000 0000000
module autosense_venkataramanan_begin(/*AUTOARG*/);
reg a,b;
always @(/*AUTOSENSE*/b or i) // I didn't expect to get "i" in AUTOSENSE
begin : label
integer i, j;
for (i=0; i<= 3; i = i + 1)
vec[i] = b;
end
endmodule
// Local Variables:
// verilog-auto-sense-defines-constant: t
// verilog-auto-sense-include-inputs: t
// End:
verilog-mode-20161124.fd230e6/tests/autotieoff_assign.v 0000664 0000000 0000000 00000000543 13022141775 0022463 0 ustar 00root root 0000000 0000000 module autotieoff_signed (/*AUTOARG*/);
output [2:0] ExtraOut;
output [2:0] SubOut;
output [3:0] active_low_l;
output [3:0] ignored_by_regexp;
/*AUTOTIEOFF*/
endmodule
module sub;
input SubIn;
output SubOut;
endmodule
// Local Variables:
// verilog-auto-tieoff-declaration: "assign"
// End:
verilog-mode-20161124.fd230e6/tests/autotieoff_signed.v 0000664 0000000 0000000 00000001707 13022141775 0022453 0 ustar 00root root 0000000 0000000 module autotieoff_signed (/*AUTOARG*/);
input [2:0] ExtraIn;
input [2:0] SubIn;
output [2:0] ExtraOut;
output [2:0] SubOut;
output [3:0] active_low_l;
output [3:0] ignored_by_regexp;
/*AUTOINOUTMODULE("autoinst_signed")*/
// =============================
// Auto Wires/Regs
// =============================
/*AUTOWIRE*/
/*AUTOREG*/
// =============================
// Tieoffs
// =============================
/*AUTOTIEOFF*/
// =============================
sub sub (/*AUTOINST*/);
// =============================
// Unused signals
// =============================
// lint_checking SCX_UNUSED OFF
wire _unused_ok = &{1'b0,
/*AUTOUNUSED*/
1'b0};
// lint_checking SCX_UNUSED OFF
endmodule
module sub;
input SubIn;
output SubOut;
endmodule
// Local Variables:
// verilog-active-low-regexp: "_l$"
// verilog-auto-tieoff-ignore-regexp: "ignored"
// End:
verilog-mode-20161124.fd230e6/tests/autoundef.v 0000664 0000000 0000000 00000000640 13022141775 0020742 0 ustar 00root root 0000000 0000000 // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module temp;
`define FOO(a)
`define BAR
`define BAZ
.....
`undef BAR
`define BAR
`define BAZ // AGAIN
/*AUTOUNDEF*/
// Make sure this list is empty
/*AUTOUNDEF*/
//======================================================================
`define M_A
`define X_B
/*AUTOUNDEF("^M_")*/
endmodule
verilog-mode-20161124.fd230e6/tests/autounused.v 0000664 0000000 0000000 00000001012 13022141775 0021136 0 ustar 00root root 0000000 0000000 module wbuf
#(parameter width=1)
(output [width-1:0] q,
input [width-1:0] d);
endmodule
module autounused
#(parameter width=3)
(/*AUTOARG*/) ;
/*AUTOOUTPUT*/
input da, db, dc, dd;
/*AUTOINPUT*/
wire _unused_ok = &{/*AUTOUNUSED*/
1'b0};
defparam partbuf.width = width;
wbuf wbuf
(// Inputs
.d ({da,db,dc}),
/*AUTOINST*/);
endmodule // abuf
// Local Variables:
// verilog-auto-unused-ignore-regexp: "^db$"
// End:
verilog-mode-20161124.fd230e6/tests/autowire_godiwala.v 0000664 0000000 0000000 00000023153 13022141775 0022462 0 ustar 00root root 0000000 0000000 module FswArbiter (/*AUTOARG*/) ;
// ========================
// Include parameter File
// ========================
parameter DMAO = 0;
`include "chip_fsw_spec_param.v"
// ===============
// Physical Pins
// ===============
input sclk; // Fabric switch clock
input lreset_l;
input csr_insert_idle;
input csr_arb_enable;
input [3:0] csr_bypass3_enable;
input [3:0] csr_bypass2_enable;
input [3:0] csr_bypass1_enable;
input csr_xb_ecc_enable;
output [3:0] xb_ecc_error_dbit;
output [3:0] xb_ecc_error_1bit;
output insert_idle_ack;
output [2:0] bp_performance_count;
input xb0_obx_ReqPst_s2a;
input [3:0] xb0_obx_NextVc_s2a;
input [1:0] xb0_obx_NextPort_s2a;
input [3:0] xb0_obx_NextXbe_s2a;
input [3:0] xb0_obx_NextXbe_s3a;
input [71:0] xb0_obx_OutDat_s4a;
output obx_xb0_GntPst_s3a;
output obx_xb0_GntByp_s3a;
input xb0_obx_ReqBypS3_s2a;
input xb0_obx_ReqBypS2_s2a;
input xb1_obx_ReqPst_s2a;
input [3:0] xb1_obx_NextVc_s2a;
input [1:0] xb1_obx_NextPort_s2a;
input [3:0] xb1_obx_NextXbe_s2a;
input [3:0] xb1_obx_NextXbe_s3a;
input [71:0] xb1_obx_OutDat_s4a;
output obx_xb1_GntPst_s3a;
output obx_xb1_GntByp_s3a;
input xb1_obx_ReqBypS3_s2a;
input xb1_obx_ReqBypS2_s2a;
input xb2_obx_ReqPst_s2a;
input [3:0] xb2_obx_NextVc_s2a;
input [1:0] xb2_obx_NextPort_s2a;
input [3:0] xb2_obx_NextXbe_s2a;
input [3:0] xb2_obx_NextXbe_s3a;
input [71:0] xb2_obx_OutDat_s4a;
output obx_xb2_GntPst_s3a;
output obx_xb2_GntByp_s3a;
input xb2_obx_ReqBypS3_s2a;
input xb2_obx_ReqBypS2_s2a;
input xb3_obx_ReqPst_s2a;
input [3:0] xb3_obx_NextVc_s2a;
input [1:0] xb3_obx_NextPort_s2a;
input [3:0] xb3_obx_NextXbe_s2a;
input [3:0] xb3_obx_NextXbe_s3a;
input [71:0] xb3_obx_OutDat_s4a;
output obx_xb3_GntPst_s3a;
output obx_xb3_GntByp_s3a;
input xb3_obx_ReqBypS3_s2a;
input xb3_obx_ReqBypS2_s2a;
input ib0_obx_PortSel_s1a;
input [63:0] ib0_obx_InDat_s1a;
input [1:0] ib0_obx_NextPort_s1a;
input [3:0] ib0_obx_NextVc_s1a;
input ib1_obx_PortSel_s1a;
input [63:0] ib1_obx_InDat_s1a;
input [1:0] ib1_obx_NextPort_s1a;
input [3:0] ib1_obx_NextVc_s1a;
input ib2_obx_PortSel_s1a;
input [63:0] ib2_obx_InDat_s1a;
input [1:0] ib2_obx_NextPort_s1a;
input [3:0] ib2_obx_NextVc_s1a;
input ib3_obx_PortSel_s1a;
input [63:0] ib3_obx_InDat_s1a;
input [1:0] ib3_obx_NextPort_s1a;
input [3:0] ib3_obx_NextVc_s1a;
input rp_is_full;
input rp_in_progress;
input [15:0] rp_arb_poolmask;
input [63:0] rp_arb_bufbusy_mask;
output xbx_grant_cycle;
output bp1_grant_cycle;
output set_arbitration_enable_d1;
output [63:0] reset_ackbuf;
output [63:0] wait_for_ack;
output [63:0] ice9_databus;
// =============================
// Auto Wires/Regs
// =============================
/*AUTOWIRE*/
/*AUTOREG*/
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp3_enable_3),
.sop2 (sop2 & xbx_bp3_enable_2),
.sop1 (sop1 & xbx_bp3_enable_1),
.sop0 (sop0 & xbx_bp3_enable_0),
); */
FswBypassArbiter bp3 (/*AUTOINST*/);
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp2_enable_3),
.sop2 (sop2 & xbx_bp2_enable_2),
.sop1 (sop1 & xbx_bp2_enable_1),
.sop0 (sop0 & xbx_bp2_enable_0),
); */
FswBypassArbiter bp2 (/*AUTOINST*/);
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & csr_bp1_enable_3),
.sop2 (sop2 & csr_bp1_enable_2),
.sop1 (sop1 & csr_bp1_enable_1),
.sop0 (sop0 & csr_bp1_enable_0),
); */
FswBypassArbiter bp1 (/*AUTOINST*/);
// =======================================
// Coverage
// =======================================
// psl default clock = negedge sclk;
generate if (DMAO == 0)
begin
// psl cover {lreset_l & (bp1_grant0 |bp1_grant1 |bp1_grant2 |bp1_grant3 )} report "FswPerfRtl::byp1Taken";
// psl cover {lreset_l & (bp2_grant0 |bp2_grant1 |bp2_grant2 |bp2_grant3)} report "FswPerfRtl::byp2Taken";
// psl cover {lreset_l & (bp3_grant0 |bp3_grant1 |bp3_grant2 |bp3_grant3)} report "FswPerfRtl::byp3Taken";
end
endgenerate
// ================
// Unused signals
// ================
// lint_checking SCX_UNUSED off
wire _unused_ok = &{1'b0,
bp_select,
bp3_hold_wait_vector,
bp2_hold_wait_vector_d1,
bp1_hold_wait_vector_d1,
bp3_header,
bp3_header_d1,
bp3_select,
bp3_select_d1,
bp3_next_winner[1:0],
bp3_next_winner_d1[1:0],
bp3_nextxbe[3:0],
bp3_nextxbe_d1[3:0],
bp2_grant_cycle_d2,
bp2_header,
bp2_header_d2,
bp2_select,
bp2_select_d2,
bp2_next_winner[1:0],
bp2_next_winner_d2[1:0],
bp2_nextxbe[3:0],
bp2_nextxbe_d2[3:0],
bp1_header_d1,
bp1_header_d2,
bp1_select_d1,
bp1_select_d2,
bp1_next_winner_d1[1:0],
bp1_next_winner_d2[1:0],
bp1_nextxbe_d1[3:0],
bp1_nextxbe_d2[3:0],
xb0_obx_NextXbe_s3a, // This is unused signal now.
xb1_obx_NextXbe_s3a,
xb2_obx_NextXbe_s3a,
xb3_obx_NextXbe_s3a,
syn64,
dataout64,
1'b0
};
// lint_checking SCX_UNUSED on
endmodule
module FswBypassArbiter (/*AUTOARG*/) ;
input lreset_l;
input sclk;
input bp_arb_enable;
output bp_grant3;
output bp_grant2;
output bp_grant1;
output bp_grant0;
output bp_grant_cycle;
output bp_grant_cycle_d1;
output bp_grant_cycle_d2;
output [1:0] bp_next_winner;
output [1:0] bp_next_winner_d1;
output [1:0] bp_next_winner_d2;
output [3:0] bp_nextxbe;
output [3:0] bp_nextxbe_d1;
output [3:0] bp_nextxbe_d2;
output [5:0] bp_hold_wait_vector;
output [5:0] bp_hold_wait_vector_d1;
output bp_header;
output bp_header_d1;
output bp_header_d2;
output bp_select;
output bp_select_d1;
output bp_select_d2;
input sop3;
input [63:0] sop3_data;
input [5:0] sop3_bpcontext;
input sop2;
input [63:0] sop2_data;
input [5:0] sop2_bpcontext;
input sop1;
input [63:0] sop1_data;
input [5:0] sop1_bpcontext;
input sop0;
input [63:0] sop0_data;
input [5:0] sop0_bpcontext;
input [15:0] poolmask;
input [63:0] bufbusy_mask;
endmodule
verilog-mode-20161124.fd230e6/tests/autowire_import_bug317.v 0000664 0000000 0000000 00000000676 13022141775 0023302 0 ustar 00root root 0000000 0000000 package pkg;
typedef logic [1:0] my_type;
endpackage
module top;
import pkg::*;
/*AUTOWIRE*/
sub_1 sub_1 (.*);
sub_2 sub_2 (.*);
endmodule
module sub_1
import pkg::*; // bug317
(
input pkg::my_type_t a,
output pkg::my_type_t z
);
endmodule
module sub_2
(
input pkg::my_type_t z,
output pkg::my_type_t a
);
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// verilog-auto-star-save: t
// End:
verilog-mode-20161124.fd230e6/tests/autowire_isaacson.v 0000664 0000000 0000000 00000001551 13022141775 0022471 0 ustar 00root root 0000000 0000000 module t;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire w11; // From bp3 of FswBypassArbiter.v
wire w12; // From bp3 of FswBypassArbiter.v
// End of automatics
/*AUTOREG*/
wand w0;
wor w1;
tri0 w2;
tri1 w3;
triand w4;
trior w5;
trireg w6;
tri w7;
wire w8;
supply0 w9;
supply1 w10;
FswBypassArbiter bp3 (/*AUTOINST*/
// Outputs
.w0 (w0),
.w1 (w1),
.w2 (w2),
.w3 (w3),
.w4 (w4),
.w5 (w5),
.w6 (w6),
.w7 (w7),
.w8 (w8),
.w9 (w9),
.w10 (w10),
.w11 (w11),
.w12 (w12));
endmodule
module FswBypassArbiter (/*AUTOARG*/
// Outputs
w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12
) ;
output w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
endmodule
verilog-mode-20161124.fd230e6/tests/autowire_long_yaohung.v 0000664 0000000 0000000 00000000406 13022141775 0023360 0 ustar 00root root 0000000 0000000 module autowire_long_yaohung(/*AUTOARG*/);
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*AUTOREG*/
top top
(/*AUTOINST*/);
endmodule
module top(/*AUTOARG*/);
output [`LONGNAMELONGNAMELONGNAMELONGNAMELONGNAMELONGNAME] data_out;
endmodule
verilog-mode-20161124.fd230e6/tests/autowire_lovell_hiear.v 0000664 0000000 0000000 00000001373 13022141775 0023340 0 ustar 00root root 0000000 0000000 module foo
(/*AUTOARG*/
// Outputs
another_output2
);
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output [1:0] another_output2; // From inst of autoinst_signed_fubar2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] another_output2; // From inst of autoinst_signed_fubar2.v
// End of automatics
/* autoinst_signed_fubar2 AUTO_TEMPLATE (
.an_output2 (hi.ear.ial),
);
*/
autoinst_signed_fubar2 inst
(
/*AUTOINST*/
// Outputs
.an_output2 (hi.ear.ial), // Templated
.another_output2 (another_output2[1:0]),
// Inputs
.an_input2 (an_input2[1:0]));
endmodule
verilog-mode-20161124.fd230e6/tests/autowire_merge_bug303.v 0000664 0000000 0000000 00000001612 13022141775 0023051 0 ustar 00root root 0000000 0000000 module TOP (/*AUTOARG*/
// Outputs
SIG_NAMEB, SIG_NAMEA
)
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [223:0] SIG_NAMEA; // From A of A.v, ...
output [FOO*2:0] SIG_NAMEB; // From C of C.v
// End of automatics
/*AUTOINPUT*/
/*AUTOWIRE*/
A A(/*AUTOINST*/
// Outputs
.SIG_NAMEA (SIG_NAMEA[224*1-1:128*1]));
B B(/*AUTOINST*/
// Outputs
.SIG_NAMEA (SIG_NAMEA[127:0]));
C C(/*AUTOINST*/
// Outputs
.SIG_NAMEB (SIG_NAMEB[FOO*4-2*1:0]));
endmodule
module A(/*AUTOARG*/
// Outputs
SIG_NAMEA
);
output [224*1-1:128*1] SIG_NAMEA;
//output [223:128] SIG_NAMEA;
endmodule
module B(/*AUTOARG*/
// Outputs
SIG_NAMEA
);
output [127:0] SIG_NAMEA;
endmodule
module C(/*AUTOARG*/
// Outputs
SIG_NAMEB
);
output [FOO*4-2*1:0] SIG_NAMEB;
endmodule
verilog-mode-20161124.fd230e6/tests/autowire_misalias_bug295.v 0000664 0000000 0000000 00000000732 13022141775 0023570 0 ustar 00root root 0000000 0000000 interface my_interface ();
logic [2:0] out2;
logic [2:0] out3;
endinterface: my_interface
module foobar (input [2:0] in2, output [2:0] out2);
endmodule
module foo_autowire_fails (my_interface itf);
/*AUTOWIRE*/
assign itf.out2 = out2; // perhaps a namespace collision?
foobar foobar0
(/*AUTOINST*/);
endmodule
module foo_autowire_works (my_interface itf);
/*AUTOWIRE*/
assign itf.out3 = out2;
foobar foobar0
(/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autowire_myers.v 0000664 0000000 0000000 00000000412 13022141775 0022023 0 ustar 00root root 0000000 0000000 module test1 ( wireA, wireB );
output [3:0] wireA;
output [16:0] wireB;
endmodule
module test_top;
/*AUTOWIRE*/
generate
if (1) begin
test1 t1 (/*AUTOINST*/);
end
else begin
assign wireA = 0;
end
endgenerate
endmodule
verilog-mode-20161124.fd230e6/tests/autowire_nocomment.v 0000664 0000000 0000000 00000001314 13022141775 0022665 0 ustar 00root root 0000000 0000000 module top;
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output logic out1a;
output logic [1:0] out1b;
// End of automatics
/*AUTOREG*/
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic out1a;
logic [1:0] out1b;
// End of automatics
sub2 isub2 (/*AUTOINST*/
// Outputs
.out1a (out1a),
.out1b (out1b[1:0]),
// Inputs
.in1a (in1a),
.in1b (in1b));
endmodule
module sub2
( input logic in1a,
input logic in1b,
output logic out1a,
output logic [1:0] out1b
);
endmodule
// Local Variables:
// verilog-auto-wire-comment: nil
// End:
verilog-mode-20161124.fd230e6/tests/autowire_paramvec_bug302.v 0000664 0000000 0000000 00000001666 13022141775 0023560 0 ustar 00root root 0000000 0000000 module Abc_TEST ();
/*AUTOWIRE*/
Abc #(
.No1 (6),
/*AUTOINSTPARAM*/) u_Abc
(
/*AUTOINST*/);
Def #(
.No1 (6)) u_Def
(
// Outputs
.ck (ck),
/*AUTOINST*/);
endmodule
module Abc
#(
parameter No1 = 6,
parameter int unsigned No2 // Parameter no. 2
= pa_Abc::No2,
parameter bit No3 [No1:0][No2-1:0] // Parameter no. 3
= pa_Abc::No3
)
(
input logic ck,
input logic [No1-1:0][31:0] abc
input logic [No1-1:0][31:0] abc
);
endmodule
module Def
#(
parameter No1 = 6
)
(
input logic ck,
output logic [No1-1:0][31:0] abc
);
endmodule
// Local Variables:
// verilog-library-extensions:(".v" ".sv")
// verilog-auto-inst-param-value:t
// End:
verilog-mode-20161124.fd230e6/tests/autowire_pkg_bug195.v 0000664 0000000 0000000 00000002703 13022141775 0022546 0 ustar 00root root 0000000 0000000 `default_nettype none
package testcase_pkg;
typedef int unsigned uint;
localparam uint SIZE = 8;
typedef enum {ENUM1, ENUM2} enum_t;
endpackage
module testcase_top
(
input testcase_pkg::enum_t top_enum,
input logic [testcase_pkg::SIZE-1:0] top_in,
output logic [testcase_pkg::SIZE-1:0] top_out
);
import testcase_pkg::*;
//enum_t sub_enum; // is not declared by AUTOWIRE
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
testcase_pkg::enum_t sub_enum; // From testcase_sub1 of testcase_sub1.v
wire [testcase_pkg::SIZE-1:0] sub_in; // From testcase_sub1 of testcase_sub1.v
wire [testcase_pkg::SIZE-1:0] sub_out; // From testcase_sub2 of testcase_sub2.v
// End of automatics
assign top_out = sub_out;
testcase_sub1 testcase_sub1 (.*);
testcase_sub2 testcase_sub2 (.*);
endmodule
module testcase_sub1
(
input testcase_pkg::enum_t top_enum,
output testcase_pkg::enum_t sub_enum,
output logic [testcase_pkg::SIZE-1:0] sub_in
);
import testcase_pkg::*;
assign sub_enum = top_enum;
assign sub_in = '1;
endmodule
module testcase_sub2
(
input testcase_pkg::enum_t sub_enum,
input logic [testcase_pkg::SIZE-1:0] sub_in,
output logic [testcase_pkg::SIZE-1:0] sub_out
);
import testcase_pkg::*;
assign sub_out = (sub_enum==ENUM1) ? ~sub_in : sub_in;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// verilog-auto-star-save: t
// End:
verilog-mode-20161124.fd230e6/tests/autowire_real.v 0000664 0000000 0000000 00000000547 13022141775 0021620 0 ustar 00root root 0000000 0000000 module sc_top (
input var real Tx_vcm,
input var real i_DAC_in,
input i_Tx_SC_en,
output var real Tx_vsc
);
endmodule
module cm_top (
input i_Tx_CM_en,
output var real Tx_vcm
);
endmodule
module top (
/*AUTOOUTPUT*/
/*AUTOINPUT*/
);
/*AUTOWIRE*/
cm_top cm_buf (/*AUTOINST*/);
sc_top sc_buf (/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autowire_req.v 0000664 0000000 0000000 00000000461 13022141775 0021457 0 ustar 00root root 0000000 0000000
module autowire_req ();
reqcmd_t AReq;
reqcmd_t BReq;
/*AUTOWIRE*/
autowire_req_sw autowire_req_sw (/*AUTOINST*/
// Outputs
.BReq (BReq),
// Inputs
.AReq (AReq));
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-typedef-regexp:"_t$"
// End:
verilog-mode-20161124.fd230e6/tests/autowire_req_sw.v 0000664 0000000 0000000 00000000366 13022141775 0022174 0 ustar 00root root 0000000 0000000 `include "pf_sc.vh"
module autowire_req_sw
(
input reqcmd_t AReq,
output reqcmd_t BReq
/*AUTOINPUT*/
);
assign Bnk0Req = Cpu0Req;
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-typedef-regexp:"_t$"
// End:
verilog-mode-20161124.fd230e6/tests/autowire_thon_selects.v 0000664 0000000 0000000 00000001073 13022141775 0023362 0 ustar 00root root 0000000 0000000 module foo
(/*AUTOARG*/);
/*AUTOOUTPUTEVERY*/
/*AUTOWIRE*/
// Check that if aa is connected differently in a input, it doesn't make conflicts.
autoinst_signed_fubar2 inst
(
// Outputs
.an_output2 (hi.ear.ial),
.another_output2 (aa[FOO:0]),
// Inputs
.an_input2 (an_input2[1:0])
/*AUTOINST*/);
autoinst_signed_fubar2 instx
(
// Outputs
.an_output2 (hi.ear.ial),
// Inputs
.an_input2 (an_input2[1:0]),
.another_output2 (aa[Y:X]),
/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/autowire_totte.v 0000664 0000000 0000000 00000001263 13022141775 0022030 0 ustar 00root root 0000000 0000000 module test1 ( wire2, wire4 );
output [3:0] wire2;
output [16:0] wire4;
endmodule
module test2 ( wire6, wire12 );
input [3:0] wire6;
input [16:0] wire12;
endmodule
module test3 ( wireA, wireB );
input [3:0] wireA;
input [16:0] wireB;
endmodule
module test4 ( wireA, wireB );
output [3:0] wireA;
output [16:0] wireB;
endmodule
module test_top;
/*AUTOWIRE*/
/* test1 AUTO_TEMPLATE (
.wire@(wire_\1_to_@"(* \1 3)"[]),
); */
test1 t1 (/*AUTOINST*/);
/* test2 AUTO_TEMPLATE (
.wire@(wire@"(/ \1 3)"_to_\1[]),
); */
test2 t2 (/*AUTOINST*/);
test3 t3 (/*AUTOINST*/);
test4 t4 (/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests/batch_li_child.v 0000664 0000000 0000000 00000000606 13022141775 0021662 0 ustar 00root root 0000000 0000000 module batch_li_child
#(parameter
WIDTH_0= 'h8,
WIDTH_1 = 'h4
)
(
input rst,
input clk
);
reg [WIDTH_0-1:0] counter_0;
reg [WIDTH_1-1:0] counter_1;
always @(posedge clk) begin
if (rst) begin
counter_0 <= #1 0;
counter_1 <= #1 0;
end
else begin
counter_0 <= #1 counter_0 + 1'b1;
counter_1 <= #1 counter_1 + 1'b1;
end
end
endmodule
verilog-mode-20161124.fd230e6/tests/batch_li_parent.v 0000664 0000000 0000000 00000000453 13022141775 0022070 0 ustar 00root root 0000000 0000000 module batch_li_parent (/*AUTOARG*/);
input rst;
input clk;
parameter WIDTH_0 = 8;
parameter WIDTH_1 = 16;
batch_li_child
#(.WIDTH_1 (WIDTH_0),
.WIDTH_0 (WIDTH_1))
child
(/*AUTOINST*/);
endmodule
// Local Variables:
// verilog-auto-arg-sort: t
// End:
verilog-mode-20161124.fd230e6/tests/batch_prof_cell.v 0000775 0000000 0000000 00000000106 13022141775 0022056 0 ustar 00root root 0000000 0000000 module batch_prof_cell(Z,A,B);
output Z;
input A, B;
endmodule
verilog-mode-20161124.fd230e6/tests/carlson.v 0000664 0000000 0000000 00000001037 13022141775 0020412 0 ustar 00root root 0000000 0000000 module x ();
always @ (/*AUTOSENSE*/bus or in1 or in2 or reset) begin
out4 = | bus;
out7 = 1'b0; // pre-initialize output of case so default not needed
case (bus[1:0])
2'b00: out7 = in1;
2'b01: out7 = in2;
2'b10: out7 = reset;
`ifdef BEH
default: begin
out7 = 1'bX; // force VCS simulation to propagate X's from the bus signal
$display ("\n Error, in module temp, bus[1:0] illegal value of 11\n");
end
`endif
endcase // case(bus[1:0])
end
endmodule
verilog-mode-20161124.fd230e6/tests/case_question.v 0000664 0000000 0000000 00000000337 13022141775 0021615 0 ustar 00root root 0000000 0000000 module test ();
always @(/*AUTOSENSE*/xyz)
begin
casex (xyz)
4'b???0: r = 1;
4'b??01: r = 2;
4'b?001: r = 3;
default: r = 4;
endcase
end
assign x = y;
endmodule
verilog-mode-20161124.fd230e6/tests/comment_strip.v 0000664 0000000 0000000 00000001403 13022141775 0021631 0 ustar 00root root 0000000 0000000 module foo;
initial begin
/* The function verilog-strip-comments should not change this line:*/
$display("INFO :[PIPE LINK %d]: ///////////////////////////////////////////",PIPE_LINK);
// to this:
$display("INFO :[PIPE LINK %d]: ");
/* The function verilog-strip-comments should not change this line:*/
$display("INFO :[PIPE LINK %d]: /* ",PIPE_LINK); /* This comment should go away */
// to this:
$display("INFO :[PIPE LINK %d]: ");
/* also this comment should not get eaten
because of use of slashes // and such like
*/
/*
ugly hidded end comment // */
$display("don't forget me agentina");
// another hidden comment /*
/**/
end
endmodule // foo
verilog-mode-20161124.fd230e6/tests/debug.v 0000664 0000000 0000000 00000000415 13022141775 0020036 0 ustar 00root root 0000000 0000000 `include "some_macros.v"
module z();
$display("%t:", $time);
a = b;
casfasdf = d;
g = r;
fgasdfasdfasdfasfdasfd <= p;
gh := h;
gf <=g;
ssdf = 5;
f = zsfdsdf >= f;
endmodule
verilog-mode-20161124.fd230e6/tests/disable.v 0000664 0000000 0000000 00000000601 13022141775 0020350 0 ustar 00root root 0000000 0000000 module foo;
task my_task;
begin :body_my_task
fork
join
case (a)
endcase // case endcase
if (a) begin
end
begin
end
fork : main_fork
begin : body_main_fork
fork : sub_fork
begin
// st1
end
begin
// st2
end
join_any // first wins
a = b;
disable fork; // kill others
end // block: body_main_fork
end // block: body_main_fork
endtask // my_task
endmodule // foo
verilog-mode-20161124.fd230e6/tests/escape_a.v 0000664 0000000 0000000 00000000324 13022141775 0020507 0 ustar 00root root 0000000 0000000 module escape_a (/*AUTOARG*/
// Outputs
\o[10] , \o[2] ,
// Inputs
\i&e;
);
output \o[10] ;
output \o[2] ;
input \i&e; ;
wire \o[10] = \i&e; ;
wire \o[2] = \i&e; ;
endmodule
verilog-mode-20161124.fd230e6/tests/escape_top.v 0000664 0000000 0000000 00000001300 13022141775 0021064 0 ustar 00root root 0000000 0000000 module escape_top (/*AUTOARG*/
// Outputs
\oren10 , \o[2] ,
// Inputs
\i&e;
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input \i&e; ; // To a of escape_a.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output \o[2] ; // From a of escape_a.v
output \oren10 ; // From a of escape_a.v
// End of automatics
/* escape_a AUTO_TEMPLATE(
.\(.*o.*10.*\) (\\oren10 ),
); */
escape_a a (/*AUTOINST*/
// Outputs
.\o[10] (\oren10 ), // Templated
.\o[2] (\o[2] ),
// Inputs
.\i&e; (\i&e; ));
endmodule
verilog-mode-20161124.fd230e6/tests/example.v 0000664 0000000 0000000 00000001475 13022141775 0020412 0 ustar 00root root 0000000 0000000 module example (/*AUTOARG*/
// Outputs
lower_out, o,
// Inputs
lower_inb, lower_ina, i
);
input i;
output o;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input lower_ina; // To inst of inst.v
input lower_inb; // To inst of inst.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output lower_out; // From inst of inst.v
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg o;
// End of automatics
inst inst (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
// Inputs
.lower_inb (lower_inb),
.lower_ina (lower_ina));
always @ (/*AUTOSENSE*/i) begin
o = i;
end
endmodule
verilog-mode-20161124.fd230e6/tests/flag_f_reeves.v 0000664 0000000 0000000 00000000327 13022141775 0021541 0 ustar 00root root 0000000 0000000
module flag_f_reeves
(/*AUTOARG*/) ;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
flag_f_reeves_IBUF ibuf
(/*AUTOINST*/);
endmodule
// Local Variables:
// verilog-library-flags: ("-f flag_f_reeves.vc")
// End:
verilog-mode-20161124.fd230e6/tests/flag_f_reeves.vc 0000664 0000000 0000000 00000000012 13022141775 0021673 0 ustar 00root root 0000000 0000000 -y subdir
verilog-mode-20161124.fd230e6/tests/for.v 0000664 0000000 0000000 00000000721 13022141775 0017536 0 ustar 00root root 0000000 0000000 module lbm
(/*AUTOARG*/
// Outputs
outgo,
// Inputs
income
);
input [1:0] income;
output [1:0] outgo;
reg [1:0] outgo;
integer i;
always @ (/*AUTOSENSE*/income) begin
for (i=0; i<32; i=i+1) begin
outgo[i] = income[i];
end
end
always @ (/*AUTOSENSE*/income) begin
if (|income) begin
$display("[0%10t] %I-for.v: found %s \"quote\" ",
$time, ((|income)?"in":"out"));
end
end
endmodule
verilog-mode-20161124.fd230e6/tests/gorfajn.v 0000664 0000000 0000000 00000000640 13022141775 0020376 0 ustar 00root root 0000000 0000000 module x;
always @(/*autosense*/d32S_CurCcbH or ramS_CcbBaseH or ramS_ccbsizeH)
begin
case (ramS_ccbsizeH)
2'b00 : ramS_CcbAddH = {2'b00, d32S_CurCcbH };
2'b01 : ramS_CcbAddH = {1'b0, d32S_CurCcbH, 1'b0};
2'b10 : ramS_CcbAddH = {d32S_CurCcbH, 2'b00};
2'b11 : ramS_CcbAddH = {d32S_CurCcbH, 2'b00}; // unused
endcase
ramS_CcbAddresH = {10'h000, ramS_CcbAddH} + ramS_CcbBaseH;
end
endmodule
verilog-mode-20161124.fd230e6/tests/grisamore_twoinone.v 0000664 0000000 0000000 00000002565 13022141775 0022672 0 ustar 00root root 0000000 0000000 module foo (/*AUTOARG*/
// Outputs
d,
// Inputs
b, a
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input a; // To foo2 of foo2.v
input b; // To foo2 of foo2.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output d; // From foo2 of foo2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
// End of automatics
foo2 foo2 (/*AUTOINST*/
// Outputs
.d (d),
// Inputs
.a (a),
.b (b));
endmodule
module foo2 (/*AUTOARG*/
// Outputs
d,
// Inputs
a, b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
// End of automatics
input a;
input b;
output d;
//{ Behavioral verilog code here}
endmodule
verilog-mode-20161124.fd230e6/tests/hangcase.v 0000664 0000000 0000000 00000003570 13022141775 0020526 0 ustar 00root root 0000000 0000000 // See Line 54
module hangcase (/*AUTOARG*/);
//
assign w_rdat_ena = ({16{foo[ 0]}} & bar ) |
({16{foo[ 1]}} & bar ) |
({16{foo[ 2]}} & bar ) |
({16{foo[ 3]}} & bar ) |
({16{foo[ 4]}} & bar ) |
({16{foo[ 5]}} & bar ) |
({16{foo[ 6]}} & bar ) |
({16{foo[ 7]}} & bar ) |
({16{foo[ 8]}} & bar ) |
({16{foo[ 9]}} & bar ) |
({16{foo[10]}} & bar ) |
({16{foo[11]}} & bar ) |
({16{foo[12]}} & bar ) |
({16{foo[13]}} & bar ) |
({16{foo[14]}} & bar ) |
({16{foo[15]}} & bar ) ;
//
assign w_rdat_mrk = ({16{foo[ 0]}} & bar & baz ) |
({16{foo[ 1]}} & bar & baz ) |
({16{foo[ 2]}} & bar & baz ) |
({16{foo[ 3]}} & bar & baz ) |
({16{foo[ 4]}} & bar & baz ) |
({16{foo[ 5]}} & bar & baz ) |
({16{foo[ 6]}} & bar & baz ) |
({16{foo[ 7]}} & bar & baz ) |
({16{foo[ 8]}} & bar & baz ) |
({16{foo[ 9]}} & bar & baz ) |
({16{foo[10]}} & bar & baz ) |
({16{foo[11]}} & bar & baz ) |
({16{foo[12]}} & bar & baz ) |
({16{foo[13]}} & bar & baz ) |
({16{foo[14]}} & bar & baz ) |
({16{foo[15]}} & bar & baz ) ;
//
assign w_wdat_ena_set = ({16{ena_set}} & col_dec );
assign w_wdat_ena_clr = ({16{ena_clr}} & col_dec );
assign w_wdat_mrk_set = ({16{mrk_set}} & w_rdat_ena );
assign w_wdat_mrk_clr = ({16{mrk_clr}} & col_dec );
assign w_wdat_ena = (w_rdat_ena & ~w_wdat_ena_clr) | w_wdat_ena_set;
assign w_wdat_mrk = (w_rdat_mrk & ~w_wdat_mrk_clr) | w_wdat_mrk_set;
//
assign w_dat15_ena = foo[15] ? w_wdat_ena : bar;
//
assign w_dat15_mrk = foo[15] ? w_wdat_mrk : baz;
//^^^^ FIX NEWLINE ABOVE HERE
//
assign w_timeout_mrk = row_check ? w_wdat_mrk : r_timeout_mrk;
endmodule
verilog-mode-20161124.fd230e6/tests/indent_1.v 0000664 0000000 0000000 00000000150 13022141775 0020445 0 ustar 00root root 0000000 0000000 module foo(reg_input_signal_name);
input a;
input reg_input_signal_name;
endmodule // foo
verilog-mode-20161124.fd230e6/tests/indent_2.v 0000664 0000000 0000000 00000000542 13022141775 0020453 0 ustar 00root root 0000000 0000000 module foo(reg_input_signal_name,a,b,c,d,e);
// foo bar
output c;//this is a comment
reg foo;
//a
/* jj
KK */
reg foo;
output reg /* */ signed d;
output reg signed e; /* so is this */
reg [31:0] blather;
endmodule // foo
verilog-mode-20161124.fd230e6/tests/indent_3.v 0000664 0000000 0000000 00000000265 13022141775 0020456 0 ustar 00root root 0000000 0000000 module junk (/*AUTOARG*/) ;
input a_junk;
input wire signed [15:0] b_junk;
output c_junk;
output [15:0][31:0][1024:(`REALLY_BIG_NAME-1)] d_junk;
endmodule // junk
verilog-mode-20161124.fd230e6/tests/indent_4.v 0000664 0000000 0000000 00000000410 13022141775 0020447 0 ustar 00root root 0000000 0000000 module foo;
initial
begin
s1;
end
always @(a)
begin
s1;
end // always @ (a)
always
begin
s1;
end // always begin
always_ff
begin
end // always_ff begin
task
t;
endtask // t
endmodule // foo
verilog-mode-20161124.fd230e6/tests/indent_always_decl.v 0000664 0000000 0000000 00000001750 13022141775 0022603 0 ustar 00root root 0000000 0000000 module foo ();
// Before the always block,
// indents to here: (which I like)
// V
wire [10:0] mux_output0 =
select0[0] ? mux_input0 :
select0[1] ? mux_input1 :
select0[2] ? mux_input2 :
select0[3] ? mux_input3 :
select0[4] ? mux_input4 :
select0[5] ? mux_input5 :
select0[6] ? mux_input6 :
mux_input7;
reg foobar;
always @(posedge clk)
if (reset_n) begin
foobar <= 1'b0;
end
// After the always block,
// indents to here:
// V
wire [10:0] mux_output1 =
select1[0] ? mux_input8 :
select1[1] ? mux_input9 :
select1[2] ? mux_input10 :
select1[3] ? mux_input11 :
select1[4] ? mux_input12 :
select1[5] ? mux_input13 :
select1[6] ? mux_input14 :
mux_input15;
endmodule
verilog-mode-20161124.fd230e6/tests/indent_assert.v 0000664 0000000 0000000 00000000274 13022141775 0021615 0 ustar 00root root 0000000 0000000 module assert_test;
reg [31:0] whatever2;
initial begin
a = b;
assert(std::randomize(whatever2) with { whatever2 inside {[10:100]};});
end
endmodule // assert_test
verilog-mode-20161124.fd230e6/tests/indent_assert_else.v 0000664 0000000 0000000 00000002455 13022141775 0022630 0 ustar 00root root 0000000 0000000 module myassert(input clk,
input reset,
input [15:0] data);
property myproperty;
@(posedge clk)
$rose(reset) |-> data == 16'h0;
endproperty
//Assert, cover, and assume property statements
//support begin/end keywords. The else begin/end
//clause below is getting indented improperly.
myassert0: assert property(myproperty) begin
$display("myassert0 was successful");
a;
b;
c;
d;
end // myassert0: assert property (myproperty)
else begin
$fatal("myassert0 was unsuccessful");
end // else: !assert property(myproperty)
if (a) begin
b;
c;
end // if (a)
else begin
o;
end // else: !if(a)
assert (a) begin
o;
end // assert (a)
else begin
o;
end // else: !assert (a)
assert (statement) begin
$display("assertion passed"); //this code is correctly indented
end // assert (statement)
else begin // this whole section should be moved to the left
$error("assertion failed");
end // else: !assert (statement)
//Also, any statements following the assert,
//cover, and assume property statements get
// indented too far to the right.
always @(posedge clk) begin
a;
end // always @ (posedge clk)
endmodule
verilog-mode-20161124.fd230e6/tests/indent_assert_property.v 0000664 0000000 0000000 00000001221 13022141775 0023552 0 ustar 00root root 0000000 0000000 module myassert(input clk,
input reset,
input [15:0] data);
property myproperty;
@(posedge clk)
$rose(reset) |-> data == 16'h0;
endproperty
//Assert, cover, and assume property statements
//support begin/end keywords. The else begin/end
//clause below is getting indented improperly.
myassert0: assert property(myproperty) begin
$display("myassert0 was successful");
end
else begin
$fatal("myassert0 was unsuccessful");
end
//Also, any statements following the assert,
//cover, and assume property statements get
// indented too far to the right.
always @(posedge clk) begin
end
endmodule
verilog-mode-20161124.fd230e6/tests/indent_assignment.v 0000664 0000000 0000000 00000000462 13022141775 0022463 0 ustar 00root root 0000000 0000000 // Issue 941 : The following operators should not be broken by auto-indents
module m;
initial begin
a = b;
a <= b;
a <<= b;
a <<<= b;
a >= b;
a >>= b;
a >>>= b;
a == b;
a != b;
a === b;
a !== b;
a ==? b;
a !=? b;
a <-> b;
a -> b;
a ->> b;
a |-> b;
a |=> b;
a #-# b;
a #=# b;
a := b;
a :/ b;
end
endmodule
verilog-mode-20161124.fd230e6/tests/indent_attributes.v 0000664 0000000 0000000 00000000337 13022141775 0022502 0 ustar 00root root 0000000 0000000 module example(out1, out2, out3);
(* LOC = "D14" *)
output out1;
/* foobar */ (* LOC = "C15" *) /* jar */ output out2;
(* LOC = "C16" *)
output out3;
out1 = 1'b1;
out2 = 1'b1;
out3 = 1'b1;
endmodule
verilog-mode-20161124.fd230e6/tests/indent_begin_clapp.v 0000664 0000000 0000000 00000000467 13022141775 0022563 0 ustar 00root root 0000000 0000000 // bug 825
module x;
always @*
begin
end
initial
begin
end
final
begin
end
initial forever
begin
end
foreach(1)
begin
end
do
begin
end while (i);
initial @a.b
begin
end
always @E
begin
end
forever @E
begin
end
endmodule
// Local Variables:
// verilog-indent-begin-after-if: nil
// End:
verilog-mode-20161124.fd230e6/tests/indent_bracket.v 0000664 0000000 0000000 00000000417 13022141775 0021726 0 ustar 00root root 0000000 0000000 // bug437: Indentation of continued assignment incorrect if first line ends with ']'
module foo
(input [63:0] data_in,
input ctl_in,
output [63:0] data_out,
output ctl_out);
assign data_out = data_in[1] ? data_in[63:0]
: 64'h0;
endmodule
verilog-mode-20161124.fd230e6/tests/indent_case.v 0000664 0000000 0000000 00000001250 13022141775 0021222 0 ustar 00root root 0000000 0000000 module testcaseindent();
case (a)
1: begin
asdf;
end // case: 1
2: begin
asdfasdf;
end // case: 2
3: begin
asdfasd;
end // case: 3
endcase // case (a)
unique case (a)
1: begin
asdf;
end // case: 1
2: begin
case (d)
2: a;
3: c;
4: begin
priority casex (f)
4: g;
5: h;
endcase // priority casex
end
endcase // case (d)
asdfasdf;
end // case: 2
3: begin
asdfasd;
end // case: 3
endcase // case (a)
unique case (a)
1: asdf;
2: asdfasdf;
3: asdfasd;
endcase // case (a)
endmodule // test_case_indent
verilog-mode-20161124.fd230e6/tests/indent_class.v 0000664 0000000 0000000 00000001765 13022141775 0021427 0 ustar 00root root 0000000 0000000 class foo();
int my_field;
endclass // foo
class temp;
extern function test();
extern function test2();
function foo();
foo = 1;
endfunction // foo
extern function test3();
reg [31:0] b;
endclass // temp
class short extends temp;
logic a;
endclass
`define vmm_channel(A) A+A
module foo;
reg a;
reg [1:0] b;
initial begin
b = `vmm_channel(a);
end // initial begin
endmodule // foo
class A;
extern function int e1();
extern function int e2(int src,int dst);
extern static function int f1();
extern static function int f2(int src,int dst);
extern static function int f3(int src,int dst);
extern static function chandle f10(int src);
extern static function automatic int f11(int mcid);
extern function automatic int f13(int mcid);
static function int s1();
int i = 0;
endfunction
static function int s2();
int i = 0;
endfunction
function int f1();
int i = 0;
endfunction
function int f2();
int i = 0;
endfunction
endclass
verilog-mode-20161124.fd230e6/tests/indent_clocking.v 0000664 0000000 0000000 00000000626 13022141775 0022106 0 ustar 00root root 0000000 0000000 module t;
default clocking @(posedge clk);
begin
a = 8;
end
property foo (a)
a = b;
endproperty
cover property (prop) $display("**COVERAGE**");
assert property (foo) a;
assume property (bar) b;
b1: assume property (bar) b;
B2: assert property (foo) a;
B2: cover property (foo) a;
assume property (bar) b;
a;
endmodule
verilog-mode-20161124.fd230e6/tests/indent_clockingblock.v 0000664 0000000 0000000 00000001433 13022141775 0023116 0 ustar 00root root 0000000 0000000 class mipsbfm_trans extends vmm_data;
static vmm_log log = new ("mipsbfm_trans", "class") ;
logic [31:0] addr, data, mask, op;
function new();
super.new(this.log);
endfunction: new
endclass // mipsbfm_trans
interface mipsbfm_if(input clk);
logic [31:0] data;
logic [31:0] addr;
logic [31:0] mask;
logic [31:0] op;
logic valid;
clocking cb @(posedge clk);
output data;
output addr;
output mask;
output op;
output valid;
endclocking // cb
endinterface // mipsbfm_if
`vmm_channel(mipsbfm_trans);
//--------------------------------------------------------------
// MIPS BFM Master Xactor Class
//--------------------------------------------------------------
class mipsbfm_master extends vmm_xactor;
// Transaction channels
mipsbfm_trans_channel in_chan ;
endclass // mipsbfm_master
verilog-mode-20161124.fd230e6/tests/indent_comments.v 0000664 0000000 0000000 00000000256 13022141775 0022141 0 ustar 00root root 0000000 0000000 module dummy (
input wire xx,
output wire yy, // comment with paren ) adsfasdf
ouput wire zz); // oops - matched paren in comment!!
endmodule // dummy
verilog-mode-20161124.fd230e6/tests/indent_constraint.v 0000664 0000000 0000000 00000006226 13022141775 0022503 0 ustar 00root root 0000000 0000000 // my simple if else example, indented by verilog-mode
if (x == 1)
begin
test1 <= 1;
test2 <= 2;
end
else
begin
test1 <= 2;
test2 <= 1;
end
// code from IEEE spec, pg. 164
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 3
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 0
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
endclass // MyBus
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a {
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
b : coverpoint v_b {
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
//
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
// here is the same code with verilog-mode indenting
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a
{
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
// foo
b : coverpoint v_b
{
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
module fool;
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case (condition[1 :0])
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case (condition[1:0])
end
// But not this :
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case ({M_seqAddr,OPB_xferAck})
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case ({M_seqAddr,OPB_xferAck})
end // always @ (posedge clk)
endmodule // fool
module foo;
initial begin
k = 10;
std::randomize(delay) with { (delay>=1000 && delay<=3000); };
j = 9;
end
endmodule // foo
// Issue 324 - constraint indentation is not correct
// This checks for indentation around { and } inside constraint contents
class myclass;
constraint c {
foreach(items[i]) {
if(write) {
items[i].op_code == WRITE;
} else if(read) {
items[i].op_code == READ;
}
}
}
endclass // myclass
verilog-mode-20161124.fd230e6/tests/indent_constraint2.v 0000664 0000000 0000000 00000001305 13022141775 0022556 0 ustar 00root root 0000000 0000000
constraint Cepon_gate_random::grant_relations_c {
foreach (grant_relation_m[index]) {
if ((index == 0) && (last_start_time_m < time_stamp_m+`MINIMUM_TIME_TO_GATE)) grant_relation_m[index] == EPON_GATE_IN_ORDER;
else {
grant_relation_m[index] dist {
EPON_GATE_IN_ORDER :/55,
EPON_GATE_1ST_CONTAINS_2ND :/5,
EPON_GATE_2ND_CONTAINS_1ST :/5,
EPON_GATE_1ST_START_2ND_START :/5,
EPON_GATE_2ND_START_1ST_START :/5,
EPON_GATE_NO_GAP_1ST :/5,
EPON_GATE_NO_GAP_2ND :/5,
EPON_GATE_1CC_GAP :/5,
EPON_GATE_1CC_INTERLEAVE :/5,
EQUAL :/5
};
}
}
}
verilog-mode-20161124.fd230e6/tests/indent_constraint3.v 0000664 0000000 0000000 00000001001 13022141775 0022550 0 ustar 00root root 0000000 0000000 //bug433
class data;
rand integer data1;
rand integer data2,data3;
rand reg [31:0] foo;
constraint basic_c {
//empty constraint
}
constraint complex_c {
data1 <= 100;
foo inside {[40:999]};
if(foo < 87)
data2 == 10;
if(data2 == 76) {
data3 == 8;
}
}
constraint implication_c {
data1 == 10 -> data3 >= -1;
}
function new();
data1 = 0;
data2 = 78;
endfunction // new
endclass // data
verilog-mode-20161124.fd230e6/tests/indent_covergroup.v 0000664 0000000 0000000 00000001344 13022141775 0022506 0 ustar 00root root 0000000 0000000 module coverage;
enum { red, green, blue } color;
covergroup foo @(posedge clk);
c : coverpoint color;
c : coverpoint color;
c : coverpoint color;
c : coverpoint color;
endgroup // foo
foo = bar;
sequence bar
b = c;
endsequence // bar
j = taskt;
function foo;
begin
foo = 1;
end
endfunction // foo
randsequence bar
b = c;
endsequence // bar
case (foo)
1: a;
2:b;
endcase // case (foo)
casex (foo)
1: a;
2:b;
endcase // case (foo)
casez (foo)
1: a;
2:b;
endcase // case (foo)
randcase (foo)
1: a;
2:b;
endcase // case (foo)
endmodule // coverage
verilog-mode-20161124.fd230e6/tests/indent_coverpoint.v 0000664 0000000 0000000 00000001266 13022141775 0022506 0 ustar 00root root 0000000 0000000
// here is the same code with verilog-mode indenting
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk);
a: coverpoint v_a {
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
b: coverpoint v_b iff ( g )
{
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
c: coverpoint v_c iff ( !g ) {
bins c1 = {0};
bins c2 = { [1:84] };
bins c3 = { [85:169] };
bins c4 = { [170:255] };
}
d: cross a , b, c {
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
verilog-mode-20161124.fd230e6/tests/indent_decl-1.v 0000664 0000000 0000000 00000001200 13022141775 0021347 0 ustar 00root root 0000000 0000000 module soft_rst
(
// System clock and reset
input clk,
input rst_n,
// Interface to software land
input req_soft_rst, // Soft reset request
output soft_rst_dne, // Soft reset done
// Interface to other modules
output dma_halt, // Reset pending, halt activity
input tx_quiet, // TX side is dormant
input rx_quiet, // RX side is dormant
input c,
output soft_rst, // Soft (sync) reset to VC3 side
output hs_async_rst_n // Async reset to host side
);
reg [1:0] state;
reg [1:0] IDLE = 2'h0,
HALT = 2'h1,
RST = 2'h2,
DONE = 2'h3;
endmodule // soft_rst
verilog-mode-20161124.fd230e6/tests/indent_decl.v 0000664 0000000 0000000 00000000416 13022141775 0021221 0 ustar 00root root 0000000 0000000 module foo;
input a;
input b;
input [1:0] cfg_dev_i; // Config Device: 0b00 = Pangu, 0b01 = Switch
output switch_idsel_o; // Switch PCI IDSEL
output pangu_idsel_o; // Pangu PCI IDSEL
output wire g;
inout wire h;
endmodule // foo
verilog-mode-20161124.fd230e6/tests/indent_directives.v 0000664 0000000 0000000 00000002755 13022141775 0022463 0 ustar 00root root 0000000 0000000 module foo;
`ifdef LABEL_A
CHIP CPU (
.clkin(clkin),
`ifdef LABEL_B
.bclko(bclko),
`endif
.cmode(cmode),
);
input sysclk;
`ifdef LABEL_B
input bclko;
`endif
input cmode;
`endif
// instead of:
`ifdef LABEL_A
CHIP CPU (
.clkin(clkin),
`ifdef LABEL_B
.bclko(bclko),
`endif
.cmode(cmode),
);
input sysclk;
`ifdef LABEL_B
input bclko;
`endif
input cmode;
`endif // `ifdef LABEL_A
reg a,b;
`ifdef A
always @(a) begin
b = a; // asfSDfsdfsasa
b = a; // asfSDfsdfsasa
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
end
`elsif B
always @(b) begin
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
end
`else // !`elsif B
always @(a or b) begin
a <= b;
b <= a;
end
`endif // !`elsif B
endmodule // foo
verilog-mode-20161124.fd230e6/tests/indent_dpi.v 0000664 0000000 0000000 00000002154 13022141775 0021067 0 ustar 00root root 0000000 0000000 import "DPI-C" function string fna (input string str1);
export "DPI" c_identifier = task task_identifier;
import "DPI" context function string fnb (input string str1);
module testbench;
import "DPI" function string fn1 (input string str1);
import "DPI-C" function void dpiWriteArray (input bit[7:0] data[]);
import "DPI-C" pure function void dpiReadArray (output bit[7:0] data[]);
import "DPI-C" function void dpiAesSetKey ( int key_high_u int key_high_l,
int key_low_u, int key_low_l );
import "DPI-C" function void dpiAesSetIV (int iv_high_u, int iv_high_l,
int iv_low_u, int iv_low_l);
import "DPI-C" function void dpiAesSetSkip (int skip);
import "DPI-C" function void dpiAesCBCEncrypt ();
logic a;
endmodule // testbench
/*
package ref_model;
import "DPI-C" xx_write_bmp_file =
function void write_bmp_file(input string filename);
import "DPI-C" xx_demosaic =
function void demosaic(regs regs,
inout pix_buf imgR, imgG, imgB);
endpackage
*/
verilog-mode-20161124.fd230e6/tests/indent_foreach.v 0000664 0000000 0000000 00000000411 13022141775 0021714 0 ustar 00root root 0000000 0000000 `ifndef FOO
`define FOO
module foo;
reg [31:0] payload [255:0];
reg [7:0] index;
always @ (b) begin
foreach (1) begin
@(router.cb);
end // foreach (1)
end // always @ (b)
endmodule // foo
`else // !`ifndef FOO
`endif // !`ifndef FOO
verilog-mode-20161124.fd230e6/tests/indent_fork_join_any.v 0000664 0000000 0000000 00000000676 13022141775 0023151 0 ustar 00root root 0000000 0000000 module fork_join_any;
initial begin
fork
begin
fork
begin
end
join_any
a = b;
disable fork;
blah;
wait fork;
blah;
end
join_any
foo = bar;
end // initial fork
endmodule // fork_join_any
class x;
task y;
a = b;
wait fork;
$display("I'm indented too far");
endtask // y
endclass // x
verilog-mode-20161124.fd230e6/tests/indent_formfeed.v 0000664 0000000 0000000 00000000072 13022141775 0022077 0 ustar 00root root 0000000 0000000
module x;
foo;
endmodule
bar;
module z;
endmodule
verilog-mode-20161124.fd230e6/tests/indent_function.v 0000664 0000000 0000000 00000003004 13022141775 0022133 0 ustar 00root root 0000000 0000000 module t;
endmodule
class C;
function int f();
f = 17;
endfunction
extern function int g();
virtual function int f();
a;
endfunction // int
// pure virtual functions have no endfunction.
C a;
initial begin
$display("hello world");
$display("a of f is %d, g is %d", a.f(),a.g());
end
function int C::g();
g = 18;
endfunction // g
// pure virtual functions have no endfunction.
endclass // C
class pure_virt_func_class;
pure virtual function string pure_virt_func();
pure virtual function string pure_virt_func();
pure virtual function string pure_virt_func();
extern pure virtual task t();
pure virtual task t();
virtual task t();
/* body */
endtask // t
virtual function f();
/* body */
endfunction // f
endclass // pure_virt_func_class
class base_test extends uvm_test;
`uvm_component_utils(base_test)
typedef virtual my_if my_vif_t;
// A function definition starting with the virtual keyword should not be
// detected as a declaration. This issue is seen when an attempt to indent
// each declaration is done (when the verilog-auto-lineup variable is set
// to 'declarations).
// In other words, the "function" in "virtual function" below must not be
// aligned with "my_if" in the "typedef virtual my_if.." line above.
virtual function void start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
endfunction : start_of_simulation_phase
endclass : base_test
verilog-mode-20161124.fd230e6/tests/indent_generate.v 0000664 0000000 0000000 00000000271 13022141775 0022103 0 ustar 00root root 0000000 0000000 module test();
reg [3:0] x;
genvar i;
generate
for(i=0; i<4; i=i+1) begin:a
always @(*) begin
x[i] = 1;
end
wire y = 0;
end
endgenerate
endmodule // test
verilog-mode-20161124.fd230e6/tests/indent_if.v 0000664 0000000 0000000 00000000174 13022141775 0020711 0 ustar 00root root 0000000 0000000 module foo;
initial
if (cond1) begin
sig1 <= {4'h0, 4'hc};
sig2 <= 8'hff;
end // if (cond1)
endmodule // foo
verilog-mode-20161124.fd230e6/tests/indent_if2.v 0000664 0000000 0000000 00000000472 13022141775 0020774 0 ustar 00root root 0000000 0000000 module foo;
always@(*)
begin
if(state==LBT_STATE)
begin
if(something)
begin
end
else
begin
end
end
else if(state==HS_0_STATE)
begin
end
else if(state==STATE_4)
begin
end
else
begin
end
end // always@ (*)
endmodule // foo
verilog-mode-20161124.fd230e6/tests/indent_ifdef.v 0000664 0000000 0000000 00000002157 13022141775 0021373 0 ustar 00root root 0000000 0000000 module test(out);
output out;
`define wow
`define nest_one
`define second_nest
`define nest_two
`ifdef wow
initial $display("wow is defined");
`ifdef nest_one
initial $display("nest_one is defined");
`ifdef nest_two
initial $display("nest_two is defined");
`else
initial $display("nest_two is not defined");
`endif
`else
initial $display("nest_one is not defined");
`endif
`else
initial $display("wow is not defined");
`ifdef second_nest
initial $display("second_nest is defined");
`else
initial $display("second_nest is not defined");
`endif
`endif
endmodule
// Local Variables:
// verilog-auto-lineup: all
// verilog-auto-endcomments: t
// verilog-auto-indent-on-newline: t
// verilog-auto-lineup: all
// verilog-auto-newline: nil
// verilog-case-indent: 2
// verilog-highlight-p1800-keywords: nil
// verilog-indent-begin-after-if: t
// verilog-indent-level: 2
// verilog-indent-level-behavioral: 2
// verilog-indent-level-declaration: 2
// verilog-indent-level-directive: 2
// verilog-indent-level-module: 2
// verilog-minimum-comment-distance: 40
// verilog-tab-always-indent: t
// End:
verilog-mode-20161124.fd230e6/tests/indent_ifdef_generate.v 0000664 0000000 0000000 00000002107 13022141775 0023240 0 ustar 00root root 0000000 0000000 // Issue 559 - nested ifdef with generate indentation bug
module m;
`ifndef DDR_PT_GATE_SIM
generate
/***************** Assertions for DP HM signals ***************************************************************/
for (dp_id=0; dp_id = 0 ? 0 : 1)
// Incorrect indentation (v1) *strangely, not yet affected by the >= chars above*
`define DEF2 { "a" \
, "b" \
}
// Incorrect indentation (v2) *NOW aligns to the
// >= sign in `define TEMPB above (which it should not)
// Looks like the multi-line macro definition DEF2
// above caused this second version of incorrect
// indentation*
`define TEMPC ((`TEMPA + 1_000_000) >= 0 ? 0 : 1)
// BACK TO Incorrect indentation (v1)!
`define DEF3 { "a" \
, "b" \
}
// BACK TO Incorrect indentation (v2)! Surprisingly
// the >= sign in `define TEMPC macro did not affect
// the indentation this time; but the indentation
// returned to (v2) as set by that sign in `define TEMPB
`endif
verilog-mode-20161124.fd230e6/tests/indent_mailbox.v 0000664 0000000 0000000 00000000423 13022141775 0021743 0 ustar 00root root 0000000 0000000 class Driver;
mailbox mbox; // <= not highlighted.
semaphore smtx;
int id;
virtual Rx_if Rx;
function new(mailbox mbox, int id, virtual Rx_if.TB Rx);
this.mbox = mbox;
this.id = i;
this.Rx = Rx;
endfunction // new
endclass // Driver
verilog-mode-20161124.fd230e6/tests/indent_modansi.v 0000664 0000000 0000000 00000000545 13022141775 0021747 0 ustar 00root root 0000000 0000000 module testmodule(
input wire [1:0] pin1,
input wire pin2,
input wire [1:0] pin3,
input wire pin4,
output wire pin5,
output wire [10:0] pin6,
output reg pin7,
output reg [1:0] pin8
);
initial begin
$display("alls well that ends well");
end
endmodule // testmodule
verilog-mode-20161124.fd230e6/tests/indent_modport.v 0000664 0000000 0000000 00000000162 13022141775 0021774 0 ustar 00root root 0000000 0000000 module foo;
modport foo_mp;
modport foo_mp1(a);
modport foo_mp2(clocking bar_cb);
a;
endmodule // foo
verilog-mode-20161124.fd230e6/tests/indent_named_assert.v 0000664 0000000 0000000 00000000316 13022141775 0022756 0 ustar 00root root 0000000 0000000 module test;
property p_test;
a |-> b;
endproperty : p_test
assert property (p_test);
a_test : assert property (p_test);
a = b; // this and following lines are not properly indented
foo;
endmodule // test
verilog-mode-20161124.fd230e6/tests/indent_ovm.v 0000664 0000000 0000000 00000004046 13022141775 0021116 0 ustar 00root root 0000000 0000000 module ovm;
class simple_item extends ovm_sequence_item;
rand int unsigned addr;
rand int unsigned data;
rand int unsigned delay;
constraint c1 { addr < 16'h2000; }
constraint c2 { data < 16'h1000; }
// OVM automation macros for general objects
`ovm_object_utils_begin(simple_item)
a = b;
c = d;
`ovm_field_int(addr, OVM_ALL_ON)
`ovm_field_int(data, OVM_ALL_ON)
`ovm_field_int(delay, OVM_ALL_ON)
`ovm_object_utils_end
// Constructor
function new (string name = "simple_item");
super.new(name);
endfunction : new
endclass : simple_item
class mydata extends ovm_object;
string str;
mydata subdata;
int field;
myenum e1;
int queue[$];
`ovm_object_utils(mydata)
`ovm_object_utils_begin(mydata) //requires ctor with default args
`ovm_field_string(str, OVM_DEFAULT)
`ovm_field_object(subdata, OVM_DEFAULT)
`ovm_field_int(field, OVM_DEC) //use decimal radix
`ovm_field_enum(myenum, e1, OVM_DEFAULT)
`ovm_field_queue_int(queue, OVM_DEFAULT)
`ovm_object_utils_end
`ovm_object_param_utils_begin(mydata) //requires ctor with default args
`ovm_field_string(str, OVM_DEFAULT)
`ovm_field_object(subdata, OVM_DEFAULT)
`ovm_field_int(field, OVM_DEC) //use decimal radix
`ovm_field_enum(myenum, e1, OVM_DEFAULT)
`ovm_field_queue_int(queue, OVM_DEFAULT)
`ovm_object_utils_end
endclass
class my_trans extends ovm_sequence_item;
rand bit [127:0] data [];
//---> Configuration
`ovm_object_utils_begin(my_trans)
`ovm_field_array_int ( data, OVM_ALL_ON)
`ovm_object_utils_end
function new (string name = "my_trans", ovm_sequencer_base sequencer = null, ovm_sequence parent_seq = null);
super.new(name, sequencer, parent_seq);
endfunction : new
endclass : my_trans
endmodule // ovm
module tt;
initial begin
while (1) begin
`ovm_do_with(aa, {bb == 0;})
`ovm_do(cc)
`ovm_do(cc)
end // while (1)
end // initial begin
endmodule // tt
verilog-mode-20161124.fd230e6/tests/indent_param.v 0000664 0000000 0000000 00000000274 13022141775 0021414 0 ustar 00root root 0000000 0000000 module example_block
#(
parameter PARAM = 1,
FOO = 2,
BARFLUG = 4,
G = 5,
)
(// I/O
input reset_n,
input clk
input a, b,
output reg c
);
endmodule
verilog-mode-20161124.fd230e6/tests/indent_preproc.v 0000664 0000000 0000000 00000000464 13022141775 0021767 0 ustar 00root root 0000000 0000000
aa;
`__FILE__
`__LINE__
`celldefine
`end_keywords
`resetall
`unconnected_drive
`undefineall
`ifdef AA
`else
`endif
`ifndef AA
`elsif FOO
`endif
`begin_keywords "FOO"
`undef FOO
`line 2 "xx" 2
`include "YY"
`include
`pragma endofline
`timescale 10ns/10ps
`define foo bar
verilog-mode-20161124.fd230e6/tests/indent_preproc_label.v 0000664 0000000 0000000 00000000542 13022141775 0023123 0 ustar 00root root 0000000 0000000 // bug861/862 - named coverpoint inside/near pre-processor macro confuses indentation
module m;
`ifdef ASSERT_ON
asrt_001: assert property(p_001);
asrt_002: assert property(p_002);
asrt_003: assert property(p_003);
`endif
`ifdef COVER_ON
chk_001: cover property(p_001);
chk_002: cover property(p_002);
chk_003: cover property(p_003);
`endif
endmodule
verilog-mode-20161124.fd230e6/tests/indent_property.v 0000664 0000000 0000000 00000002175 13022141775 0022202 0 ustar 00root root 0000000 0000000 module foo();
initial begin
a;
end
always @(a) begin
b;
end
task a (a);
begin
a = f;
a = f;
d <= 89;
sdf = sdf;
adada => asda;
d ->> g;
aasd <<<= 3;
ccc %= 6;
d *= b;
g -= c;
end
endtask // a
property p_3;
a => ##3 !a;
a |=> ##1 !a;
a |-> ##2 !a;
endproperty
property p_2;
@(posedge clk) b |-> ##1 c;
endproperty
property p_1;
@(posedge clk) a |-> b;
endproperty
initial d;
// ap_1 assert property (p_1); FIXME
// ap_2 assert property (p_2);
property p_lane_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(lane_inputs) |-> !$stable(lane_outputs);
endproperty
// Issue #940 - '=' in |=> , #=#, and [=n] operators should not mis-indent next line of continued expression
property p_nonSequential;
a |-> b[=n] ##0
c;
endproperty
property p_nonOverlapFollowedBy;
a #=#
c;
endproperty
property p_nonBlockingImplication;
a |=> b[*n] ##0
c;
endproperty
endmodule
verilog-mode-20161124.fd230e6/tests/indent_randcase.v 0000664 0000000 0000000 00000000344 13022141775 0022072 0 ustar 00root root 0000000 0000000 module aa;
int a,b,c;
initial begin
randcase
10 : begin
a = 1;
end
15 : begin
b = 0;
c = 5;
end
endcase // randcase
end // initial begin
endmodule // a
verilog-mode-20161124.fd230e6/tests/indent_random.v 0000664 0000000 0000000 00000001402 13022141775 0021566 0 ustar 00root root 0000000 0000000 module top;
initial begin
// Test
$display("Hello world");
void'(std::randomize(foo) with {foo < 10;}; );
end
endmodule // top
/*
--------------------------
It also appears to have indentation problems with the following variation:
== The code: ==
*/
module top;
initial begin
// Test
$display("Hello world");
assert(std::randomize(foo) with {foo < 10;}; )
else $error("ERROR randomizing foo");
end
endmodule // top
/*
------------------------------
Also tried the following (removed semicolon after closing-curly-brace), and got same result:
*/
module top;
initial begin
// Test
$display("Hello world");
void'(std::randomize(foo) with {foo < 10;} );
end
endmodule // top
verilog-mode-20161124.fd230e6/tests/indent_struct.v 0000664 0000000 0000000 00000001620 13022141775 0021634 0 ustar 00root root 0000000 0000000 module foo;
a = { g + c; };
a = c;
typedef struct {
reg r;
ahb_op_t op; // Read, write, etc.
ahb_cycle_type_t cti; // Cycle type for bursts
ahb_incr_type_t incr; // Increment type (for bursts)
bit b;
reg r;
ahb_thingy a;
bit [31:2] addr; // Starting address
bit [3:0] byte_sel; // Byte lane select
int len; // Length of transfer
bit [31:0] data[0:7]; // Write data
} ahb_req_t;
struct {
reg f;
xyzzy b;
};
struct packed {
int a; // ok
};
struct packed signed {
int a; // woops
};
struct packed unsigned {
int a; // woops
};
endmodule // foo
module foo (
input a;
input c;
output d;
);
always @(a) g;
endmodule // foo
verilog-mode-20161124.fd230e6/tests/indent_task.v 0000664 0000000 0000000 00000004422 13022141775 0021255 0 ustar 00root root 0000000 0000000 module foo;
// for each additional in-air txmacphy byte
task nextTxByte();
TxByteCnt++;
TxLastByteTime = $time;
endtask // nextTxByte
task automatic blah();
t;
endtask // blah
function static foo();
foo = 1;
endfunction // foo
// start counting when txmacphy sees first in-air byte
task firstTxByte();
TxByteCnt = 1;
TxFirstByteTime = $time;
TxLastByteTime = $time;
endtask // firstTxByte
// outputs the overall performance of the RX path in Mbps (MBits per second)
task printRxPerformance();
integer ibps;
real Mbps;
if( RxByteCnt && systemTop.intMonitor.frgRxedCnt >= 2 ) begin
ibps =
(RxByteCnt*8*1000000000)/(RxLastByteTime-RxFirstByteTime);
Mbps = ibps/1000000;
$display("%t: %s - RX average performance: %fMbps (Mbits/sec)",
$time, myName, Mbps );
end
else
$display("%t: %s - Requires >= 2 RX frames in order to measure performance", $time, myName);
endtask // printRxPerformance
endmodule // foo
class a;
virtual function void foo();
foo = 2;
endfunction // void
extern function void bar();
function fred();
aaa;
endfunction // fred
task foo;
endtask // endtask
virtual task foo;
endtask // endtask
generate g;
endgenerate
covergroup g;
endgroup // g
property p;
endproperty
sequence s;
endsequence // s
clocking c;
endclocking // c
function f;
endfunction //
virtual function f;
endfunction //
protected function f;
endfunction //
endclass // a
class base_test extends uvm_test;
`uvm_component_utils(base_test)
typedef virtual my_if my_vif_t;
// A task definition starting with the virtual keyword should not be
// detected as a declaration. This issue is seen when an attempt to indent
// each declaration is done (when the verilog-auto-lineup variable is set
// to 'declarations).
// In other words, the "task" in "virtual task" below must not be
// aligned with "my_if" in the "typedef virtual my_if.." line above.
virtual task run_phase(uvm_phase phase);
super.run_phase(phase);
endtask // run_phase
endclass // base_test
verilog-mode-20161124.fd230e6/tests/indent_task_func_decl.sv 0000664 0000000 0000000 00000004256 13022141775 0023447 0 ustar 00root root 0000000 0000000 typedef class burst_drv;
class burst_drv extends vmm_xactor;
int EXECUTING;
int OBSERVED;
int SUB_OBSERVED;
protected burst_drv_cfg cfg;
local burst_drv_cfg reset_cfg;
protected burst_xn rx_factory;
local burst_xn reset_rx_factory;
burst_xn_channel in_chan;
burst_xn_channel obs_chan;
burst_xn tr_main; // Current transaction in main()
/* could have [extern] [virtual] [protected|local] task [static|automatic|] name (); */
/* If extern -> then it is complete; other wise it is not complete */
/* class could have:
class c
extern virtual static protected task t ();
endclass
task declaration could have
task static t();
endtask
*/
class c;
endclass // c
function f();
g;
endfunction // f
generate g;
/* a lot of stuff */
endgenerate
task t();
/**/
/**/
endtask // t
protected virtual task pv_t();
/**/
endtask // pv_t
protected task p_t();
/* ACK*/
endtask // p_t
virtual task v_t();
/**/
endtask // v_t
virtual protected task vp_t();
/**/
endtask // vp_t
protected virtual task pv_t();
/**/
endtask // pv_t
extern task e_t();
extern virtual task ev_t();
extern protected task ep_t();
extern protected virtual task epv_t();
extern protected virtual task main();
generate g;
/**/
endgenerate
extern virtual function void reconfigure(burst_drv_cfg cfg);
extern virtual function void reset_xactor(reset_e rst_type = SOFT_RST);
extern virtual function new (
string inst,
int stream_id,
burst_drv_cfg cfg = null,
burst_xn_channel in_chan = null,
burst_xn_channel obs_chan = null,
burst_xn rx_factory = null);
virtual task start();
super.start();
this.tx_dma.start();
this.rx_dma.start();
endtask // start
task start();
super.start();
this.tx_dma.start();
this.rx_dma.start();
endtask // start
task static start();
super.start();
this.tx_dma.start();
this.rx_dma.start();
endtask // static
endclass : burst_drv
verilog-mode-20161124.fd230e6/tests/indent_typedef.sv 0000664 0000000 0000000 00000000175 13022141775 0022137 0 ustar 00root root 0000000 0000000 package p;
typedef enum {a, b} type_t;
typedef enum {TASK, TASK2} type2_t;
typedef enum {Package, Class} type3_t;
endpackage
verilog-mode-20161124.fd230e6/tests/indent_unique_case-1.v 0000664 0000000 0000000 00000017634 13022141775 0022763 0 ustar 00root root 0000000 0000000 module xxx_xxxxxx (input wire clk, input wire reset);
typedef enum reg [4:0] {IDLE, IIII, HHHHH,
AA_OP, AA_CMRD, AA_CMRD_WAIT, AA_RMW, AA_RMW_WAIT, AA_CMLLL, AA_CMLLL_WAIT, AA_NEXT,
BB_OP, BB_CMLLL, BB_CMLLL_WAIT, BB_NEXT,
CC_OP, CC_NEXT_OOOO,
DD_OP, DD_CMRD, DD_CMRD_WAIT, DD_ACCUM, DD_CMLLL, DD_CMLLL_WAIT,
EE_OP, EE_NEXT_OOOO,
FF_OP,
zxcvzxcv, cvbncvbn} xxxxxx_state_e;
xxxxxx_state_e current_state;
always_ff @ (posedge clk) begin
if (reset) begin
current_state <= IDLE;
end
else begin
unique case (current_state)
IDLE : begin
qwerty <= '0;
if (~qqq_empty)
current_state <= HHHHH;
end
AA_CMLLL : begin
lll_start <= 1'b1;
if (jjjj_left < 4)
lll_wcnt <= jjjj_left[2:0];
else
lll_wcnt <= FOUR[2:0];
current_state <= AA_CMLLL_WAIT;
end
HHHHH : begin
qqq_opiuy <= 1'b1;
if (qqq_opiuy) begin
qqq_opiuy <= '0;
current_state <= IIII;
end
end
AA_OP : begin
if (aa_pgm_err) begin
current_state <= zxcvzxcv;
end
else begin
jjjj_left <= tgbyhn;
current_state <= AA_CMRD;
end
end
AA_CMRD : begin
uuuuu <= 1'b1;
current_state <= AA_CMRD_WAIT;
end
IIII : begin
qqq_opiuy <= '0;
if (err_iiii) begin
current_state <= zxcvzxcv;
end
else begin
unique0 case (opm_cur)
`XXXCP : current_state <= AA_OP;
`XXXZR : current_state <= BB_OP;
default : current_state <= zxcvzxcv;
endcase // unique0 case
end // else: !if(err_iiii)
end // case: IIII
AA_CMRD_WAIT : begin
uuuuu <= '0;
if (kjkjkjkjk) begin
if (err_cmrd_par) begin
current_state <= zxcvzxcv;
end
else begin
if (err_cmrd_csel) begin
current_state <= zxcvzxcv;
end
else begin : assign_writecvbn
lllcvbn <= asdf ? ghjk : rdcvbn;
lll_par <= asdf ? cvbn : rd_par;
current_state <= AA_CMLLL;
end
end // else: !if(err_cmrd_par)
end // if (kjkjkjkjk)
end // case: AA_CMRD_WAIT
AA_CMLLL_WAIT : begin
lll_start <= '0;
if (lll_done) begin
if (alalala) begin
current_state <= zxcvzxcv;
end
else begin
current_state <= AA_NEXT;
end
end
end // case: AA_CMLLL_WAIT
AA_NEXT : begin
if (qwerty) begin
qwerty <= '0;
unique case (opm_cur)
`XXXCP : current_state <= cvbncvbn;
`XXXSG : current_state <= CC_NEXT_OOOO;
default : current_state <= zxcvzxcv;
endcase // unique case
end // if (qwerty)
else begin
jjjj_left <= jjjj_left - 4;
current_state <= AA_CMRD;
end // else: !if(qwerty)
end // case: AA_NEXT
BB_OP : begin
if (bb_pgm_err) begin
current_state <= zxcvzxcv;
end
else begin
lllcvbn <= '0;
lll_par <= '0;
jjjj_left <= tgbyhn;
current_state <= BB_CMLLL;
end
end // case: BB_OP
BB_CMLLL : begin
lll_start <= 1'b1;
if (jjjj_left <= 4) begin
lll_wcnt <= jjjj_left[2:0];
qwerty <= 1'b1;
end
else begin
lll_wcnt <= FOUR[2:0];
end
current_state <= BB_CMLLL_WAIT;
end // case: BB_CMLLL
BB_CMLLL_WAIT : begin
lll_start <= '0;
if (lll_done) begin
if (alalala) begin
current_state <= zxcvzxcv;
end
else begin
current_state <= BB_NEXT;
end
end
end // case: BB_CMLLL_WAIT
BB_NEXT : begin
if (qwerty) begin
qwerty <= '0;
current_state <= cvbncvbn;
end
else begin
jjjj_left <= jjjj_left - 4;
current_state <= BB_CMLLL;
end
end
CC_OP : begin
jjjj_left_oooo <= tgbyhn;
if (tgbyhn <= oooo_cur) begin
last_oooo <= 1'b1;
jjjj_left <= tgbyhn;
end
else begin
jjjj_left <= oooo_cur;
end
current_state <= AA_CMRD;
end // case: CC_OP
CC_NEXT_OOOO : begin
if (last_oooo) begin
current_state <= cvbncvbn;
end
else begin
rd_rrrr <= rd_rrrr + ttttt_cur;
lll_rrrr <= lll_rrrr + oooo_cur;
if (jjjj_left_oooo <= oooo_cur) begin
last_oooo <= 1'b1;
jjjj_left <= jjjj_left_oooo;
end
else begin
jjjj_left <= oooo_cur;
end
current_state <= AA_CMRD;
end // else: !if(last_oooo)
end // case: CC_NEXT_OOOO
DD_OP : begin
accumulate_sum <= '0;
jjjj_left <= tgbyhn;
current_state <= DD_CMRD;
end
DD_CMRD : begin
uuuuu <= 1'b1;
if (jjjj_left <= 4) begin
qwerty <= 1'b1;
end
current_state <= DD_CMRD_WAIT;
end
DD_CMRD_WAIT : begin
uuuuu <= '0;
if (kjkjkjkjk) begin
if (zazaz) begin
current_state <= zxcvzxcv;
end
else begin
current_state <= DD_ACCUM;
end
end
end // case: DD_CMRD_WAIT
DD_ACCUM : begin
if (qwerty) begin
current_state <= DD_CMLLL;
end
else begin
current_state <= DD_CMRD;
end
end
DD_CMLLL : begin
lll_start <= 1'b1;
current_state <= DD_CMLLL_WAIT;
end
DD_CMLLL_WAIT : begin
lll_start <= '0;
end
EE_OP : begin
jjjj_left_oooo <= tgbyhn;
current_state <= AA_CMRD;
end
EE_NEXT_OOOO : begin
if (last_oooo) begin
current_state <= cvbncvbn;
end
else begin
end
end
FF_OP : begin
asdf <= 1'b1;
current_state <= CC_OP;
end
zxcvzxcv : begin
current_state <= cvbncvbn;
end
cvbncvbn : begin
if (dci_cur) begin
current_state <= IDLE;
cmd_proc_done <= 1'b1;
end
else if (crq_ready) begin
crq_start <= 1'b1;
crqcvbn <= complcvbn;
crq_proc_id <= proc_id_cur;
current_state <= IDLE;
cmd_proc_done <= 1'b1;
end
end // case: cvbncvbn
default : begin
current_state <= IDLE;
cmd_proc_done <= 1'b1;
end
endcase // unique case
end // else: !if(reset)
end // always _ff
endmodule // xxx_xxxxxx
verilog-mode-20161124.fd230e6/tests/indent_unique_case-2.v 0000664 0000000 0000000 00000002202 13022141775 0022745 0 ustar 00root root 0000000 0000000 module testmod ();
always_comb begin
unique case (eeee)
ZERO[1:0] : begin
a = 1;
end // case: ZERO[1:0]
ONE[1:0] : begin
a = 1;
end // case: ONE[1:0]
TWO[1:0] : begin
a = 1;
end // case: TWO[1:0]
THREE[1:0] : begin
a = 1;
end // case: THREE[1:0]
endcase // unique case (eeee)
end // always_comb
always_ff @ (posedge clk) begin
if (reset) begin
current_state <= `TQ STATE0;
end // if (reset)
else begin
priority case (current_state)
STATE0 : begin
current_state <= `TQ STATE3;
end // case: STATE0
STATE1 : begin
current_state <= `TQ STATE3;
end // case: STATE1
STATE2 : begin
current_state <= `TQ STATE3;
end // case: STATE2
STATE3 : begin
current_state <= `TQ STATE0;
end // case: STATE3
default : current_state <= `TQ STATE0;
endcase // priority case (current_state)
end // else: !if(reset)
end // always_ff @
endmodule // testmod
verilog-mode-20161124.fd230e6/tests/indent_unique_case.v 0000664 0000000 0000000 00000001616 13022141775 0022616 0 ustar 00root root 0000000 0000000 module foo;
// syntaxify the unique keyword correctly please...
always_comb (*) begin
case (f)
1 : 2;
endcase // case (f)
unique case(vlcnum)
0 : unique case(in.value1)
0 : out = 1; 1 : out = 3; 2 : out = 3; 3 : out = 4;
4 : out = 4; 5 : out = 5; 6 : out = 5; 7 : out = 6;
8 : out = 6; 9 : out = 7; 10: out = 7; 11: out = 8;
12 : out = 8; 13: out = 9; 14: out = 9; 15: out = 9;
endcase
1 :
unique
case(in.value1)
0 : out = 3;
1 : out = 3;
2 : out = 3;
3 : out = 3;
4 : out = 3;
5 : out = 4;
6 : out = 4;
7 : out = 4;
8 : out = 4;
9 : out = 5;
10 : out = 5;
11 : out = 6;
12 : out = 6;
13 : out = 6;
14 : out = 6;
endcase // case (in.value1)
endcase // case (in.value1)
end
endmodule
verilog-mode-20161124.fd230e6/tests/indent_uvm.v 0000664 0000000 0000000 00000004046 13022141775 0021124 0 ustar 00root root 0000000 0000000 module uvm;
class simple_item extends uvm_sequence_item;
rand int unsigned addr;
rand int unsigned data;
rand int unsigned delay;
constraint c1 { addr < 16'h2000; }
constraint c2 { data < 16'h1000; }
// UVM automation macros for general objects
`uvm_object_utils_begin(simple_item)
a = b;
c = d;
`uvm_field_int(addr, UVM_ALL_ON)
`uvm_field_int(data, UVM_ALL_ON)
`uvm_field_int(delay, UVM_ALL_ON)
`uvm_object_utils_end
// Constructor
function new (string name = "simple_item");
super.new(name);
endfunction : new
endclass : simple_item
class mydata extends uvm_object;
string str;
mydata subdata;
int field;
myenum e1;
int queue[$];
`uvm_object_utils(mydata)
`uvm_object_utils_begin(mydata) //requires ctor with default args
`uvm_field_string(str, UVM_DEFAULT)
`uvm_field_object(subdata, UVM_DEFAULT)
`uvm_field_int(field, UVM_DEC) //use decimal radix
`uvm_field_enum(myenum, e1, UVM_DEFAULT)
`uvm_field_queue_int(queue, UVM_DEFAULT)
`uvm_object_utils_end
`uvm_object_param_utils_begin(mydata) //requires ctor with default args
`uvm_field_string(str, UVM_DEFAULT)
`uvm_field_object(subdata, UVM_DEFAULT)
`uvm_field_int(field, UVM_DEC) //use decimal radix
`uvm_field_enum(myenum, e1, UVM_DEFAULT)
`uvm_field_queue_int(queue, UVM_DEFAULT)
`uvm_object_utils_end
endclass
class my_trans extends uvm_sequence_item;
rand bit [127:0] data [];
//---> Configuration
`uvm_object_utils_begin(my_trans)
`uvm_field_array_int ( data, UVM_ALL_ON)
`uvm_object_utils_end
function new (string name = "my_trans", uvm_sequencer_base sequencer = null, uvm_sequence parent_seq = null);
super.new(name, sequencer, parent_seq);
endfunction : new
endclass : my_trans
endmodule // uvm
module tt;
initial begin
while (1) begin
`uvm_do_with(aa, {bb == 0;})
`uvm_do(cc)
`uvm_do(cc)
end // while (1)
end // initial begin
endmodule // tt
verilog-mode-20161124.fd230e6/tests/indent_virtual_class.sv 0000664 0000000 0000000 00000000340 13022141775 0023344 0 ustar 00root root 0000000 0000000 // issue 928 - 'pure virtual' items in classes break indentation
package p:
virtual class c extends parent;
pure virtual protected task t(type_t a, type_t b);
function f(string s="");
blah;
endfunction:f
endclass
endpackage
verilog-mode-20161124.fd230e6/tests/indent_warren.v 0000664 0000000 0000000 00000000111 13022141775 0021600 0 ustar 00root root 0000000 0000000 `include "x.h"
//
module x;
////
reg y;
endmodule // x
verilog-mode-20161124.fd230e6/tests/inject_first.v 0000664 0000000 0000000 00000000454 13022141775 0021436 0 ustar 00root root 0000000 0000000 module ex_inject (i, o);
input i;
input j;
output o;
// Ok:
always @ (j or i)
o = i | j;
// No change:
always @ (j) o = i | j;
always @ (j or i or p) o = i | j;
// Instant
autoinst_lopaz_srpad pad
(.pin(pin),
.foo(bar),
.clk(newclk));
endmodule
verilog-mode-20161124.fd230e6/tests/inject_inst_empty_ports.v 0000664 0000000 0000000 00000000755 13022141775 0023735 0 ustar 00root root 0000000 0000000 module inject_inst_empty_ports;
logic [7:0] q;
logic [7:0] d;
logic clk, rst_n;
register r1 (.q(q),
.qb(), // unconnect output
.d(d),
.clk(clk),
.rst_n(rst_n)
);
endmodule
module register (
output logic [7:0] q, qb,
input logic [7:0] d,
input logic clk, rst_n
);
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;
assign qb = ~q;
endmodule
verilog-mode-20161124.fd230e6/tests/inject_inst_endparen.v 0000664 0000000 0000000 00000001306 13022141775 0023135 0 ustar 00root root 0000000 0000000 module inject_inst_endparen;
logic [7:0] q;
logic [7:0] d;
logic clk, nreset;
register r1 (.q(q),
.d(d),
.clk(clk),
// This is the
// asynchronous reset
.rst_n(nreset)
);
`if NEVER
register r1 (.q(qKEEP),
.d(dKEEP),
.clk(clkKEEP),
// This is the
// asynchronous reset
.rst_n(nreset)
);
`endif
endmodule
module register (
output logic [7:0] q,
input logic [7:0] d,
input logic clk, rst_n
);
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;
endmodule
verilog-mode-20161124.fd230e6/tests/inject_inst_net_case.v 0000664 0000000 0000000 00000001264 13022141775 0023125 0 ustar 00root root 0000000 0000000 module inject_inst_net_case (
output logic [7:0] q2,
input logic [7:0] d,
input logic clk, rst_n
);
logic [7:0] Q1;
register2 r2 (.q2(q2), .q1(Q1), .ck(clk), .rst_n(rst_n));
register1 r1 (.q1(Q1), .d(d), .ck(clk), .rst_n(rst_n));
endmodule
module register2 (
output logic [7:0] q2,
input logic [7:0] q1,
input logic ck, rst_n
);
always_ff @(posedge ck or negedge rst_n)
if (!rst_n) q2 <= '0;
else q2 <= q1;
endmodule
module register1 (
output logic [7:0] q1,
input logic [7:0] d,
input logic ck, rst_n
);
always_ff @(posedge ck or negedge rst_n)
if (!rst_n) q1 <= '0;
else q1 <= d;
endmodule
verilog-mode-20161124.fd230e6/tests/inject_inst_param.v 0000664 0000000 0000000 00000000714 13022141775 0022443 0 ustar 00root root 0000000 0000000 module inject_inst_param;
parameter WIDTH = 8;
logic [WIDTH-1:0] q;
logic [WIDTH-1:0] d;
logic clk, rst_n;
register #(.WIDTH(WIDTH)) r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n));
endmodule
module register #(parameter WIDTH=4) (
output logic [WIDTH-1:0] q,
input logic [WIDTH-1:0] d,
input logic clk, rst_n
);
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;
endmodule
verilog-mode-20161124.fd230e6/tests/inject_path.f 0000664 0000000 0000000 00000000043 13022141775 0021215 0 ustar 00root root 0000000 0000000 inject_path.v
inject_path_sub.v
verilog-mode-20161124.fd230e6/tests/inject_path.v 0000664 0000000 0000000 00000000357 13022141775 0021245 0 ustar 00root root 0000000 0000000 module inject_path;
logic [7:0] q;
logic [7:0] d;
logic clk, rst_n;
register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n));
endmodule
// Local Variables:
// mode: Verilog
// verilog-library-flags:("-f inject_path.f")
// End:
verilog-mode-20161124.fd230e6/tests/inject_path_cmt.v 0000664 0000000 0000000 00000000574 13022141775 0022111 0 ustar 00root root 0000000 0000000 module comments_test;
logic [7:0] q1;
logic [7:0] d;
logic clk, rst_n;
register r1 (.q(q1),
.d(d),
// 100MHz clk signal
.clk100(clk),
// Asynchronous reset
.rst_n(rst_n)
);
endmodule
// Local Variables:
// mode: Verilog
// verilog-library-flags:("-f inject_path.f")
// End:
verilog-mode-20161124.fd230e6/tests/inject_path_sub.v 0000664 0000000 0000000 00000000710 13022141775 0022107 0 ustar 00root root 0000000 0000000 // Note module names don't match, this is intentional to check the .f file
module reg_core (
output logic [7:0] q,
input logic [7:0] d,
input logic clk, rst_n
);
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;
endmodule
module register (
output logic [7:0] q,
input logic [7:0] d,
input logic clk, rst_n
);
reg_core c1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n));
endmodule
verilog-mode-20161124.fd230e6/tests/inst.v 0000664 0000000 0000000 00000000403 13022141775 0017722 0 ustar 00root root 0000000 0000000 module inst (/*AUTOARG*/
// Outputs
lower_out,
// Inputs
lower_inb, lower_ina
);
parameter param1;
parameter param2;
input lower_inb;
input lower_ina;
output lower_out;
wire lower_out = lower_ina | lower_inb;
endmodule
verilog-mode-20161124.fd230e6/tests/label_always.v 0000664 0000000 0000000 00000000675 13022141775 0021417 0 ustar 00root root 0000000 0000000 // bug 895 - labeling of always constructs
module example;
always
begin
end
always @(posedge clk)
begin
end
always @*
begin
end
always @(*)
begin
end // always @ (*)
always_comb
begin
end
always_latch
begin
end
always @( *)
begin
end
always @(* )
begin
end
always_ff @(posedge clk)
begin
end
always @(*)
begin
end // garbage
endmodule
// Local Variables:
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// End:
verilog-mode-20161124.fd230e6/tests/label_class.sv 0000664 0000000 0000000 00000000173 13022141775 0021400 0 ustar 00root root 0000000 0000000 // Bug 888 -- verilog-label-be should remove existing comment labels before adding new ones
class c;
endclass // delete-me
verilog-mode-20161124.fd230e6/tests/label_do.v 0000664 0000000 0000000 00000000232 13022141775 0020506 0 ustar 00root root 0000000 0000000 // bug 842
module x;
do begin
end while();
endmodule
// Local Variables:
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// End:
verilog-mode-20161124.fd230e6/tests/label_function.v 0000664 0000000 0000000 00000002455 13022141775 0021742 0 ustar 00root root 0000000 0000000 module test();
// function with no lifetime, return-type, or port-list
function f0;
blah0;
endfunction
// empty port-list
function f1();
blah1;
endfunction
// non-empty portlist
function f2(stuff2);
blah2;
endfunction
// test that ": function_identifier" remains unscathed
function f3;
endfunction : f3
// return type
function void f4;
blah4;
endfunction
// return type with empty port-list.
function void f5();
int i;
begin
blah4;
end
endfunction
// return type, non-empty portlist
// also check that a stale auto-comment gets removed
function void f6(stuff,
that,
spans,
lines);
blah5;
endfunction // fX
// test lifetime keywords 'automatic' and 'static'
function automatic f7();
endfunction
// test a crazy-long function declaration
function static union packed signed {bit[1:0] a, bit[2:0] b} [5:0] f8(input ports, input ports, output ports);
endfunction
// port-list that doesn't start on the same line as the function declaration
function automatic void f9
(int a,
int b);
endfunction
// mismatched keyword
function f10;
endtask
// make sure previous screw-up doesn't affect future functions
function f11;
endfunction
endmodule
verilog-mode-20161124.fd230e6/tests/label_macro.v 0000664 0000000 0000000 00000000614 13022141775 0021211 0 ustar 00root root 0000000 0000000 // Bug 859 -- 'end' should label after a user/library-defined macro
// that isn't terminated with a semi-colon
class c;
`uvm_info(get_type_name(), "Digital power up.", UVM_MEDIUM)
fork
begin
end
join
`made_up_macro (a, \
b, \
c)
begin: named_block
end
endclass
// Local Variables:
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// End:
verilog-mode-20161124.fd230e6/tests/label_no_indent.v 0000664 0000000 0000000 00000000340 13022141775 0022061 0 ustar 00root root 0000000 0000000 // bug 841
module x;
always @*
begin
end
endmodule
// Local Variables:
// verilog-indent-level-module: 0
// verilog-indent-begin-after-if: nil
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// End:
verilog-mode-20161124.fd230e6/tests/label_task.v 0000664 0000000 0000000 00000001645 13022141775 0021057 0 ustar 00root root 0000000 0000000 module test();
// task with no lifetime, return-type, or port-list
task t0;
blah0;
endtask
// empty port-list
task t1();
blah1;
endtask
// non-empty portlist
task t2(stuff2);
blah2;
endtask
// test that ": task_identifier" remains unscathed
task t3;
endtask : t3
// check that stale auto-label is overwritten
task t4(input port1, output port2, inout port3);
begin
blah blah blah;
end
endtask // tX
// test lifetime keywords 'automatic' and 'static'
task static t7();
endtask
// test a more complete example
task automatic t8(input ports, input ports, output ports);
endtask
// port-list that doesn't start on the same line as the task declaration
task automatic t9
(int a,
int b);
endtask
// mismatched keyword
task t10;
endfunction
// make sure even the simplest test works after all the insanity
task t11;
endtask
endmodule
verilog-mode-20161124.fd230e6/tests/lavigne_instpath.v 0000664 0000000 0000000 00000000772 13022141775 0022315 0 ustar 00root root 0000000 0000000 module lavigne_instpath ();
/* lavigne_t1 AUTO_TEMPLATE (
.a(a1),
);
*/
lavigne_t1 m1 (/*AUTOINST*/
// Inputs
.a (a1)); // Templated
/* lavigne_t2 AUTO_TEMPLATE (
.b(b2),
);
*/
lavigne_t2 m2 (/*AUTOINST*/
// Inputs
.b (b2)); // Templated
endmodule
// verilkkkkkkkog-library-directories:("*/")
//(load-file "/usr/local/common/site-lisp/local/verilog-mode.el")
// Local Variables:
// verilog-library-flags:("-y lavigne_instpath/")
// End:
verilog-mode-20161124.fd230e6/tests/lavigne_instpath/ 0000775 0000000 0000000 00000000000 13022141775 0022120 5 ustar 00root root 0000000 0000000 verilog-mode-20161124.fd230e6/tests/lavigne_instpath/lavigne_t1.v 0000664 0000000 0000000 00000000052 13022141775 0024335 0 ustar 00root root 0000000 0000000 module lavigne_t1 (a);
input a;
endmodule
verilog-mode-20161124.fd230e6/tests/lavigne_instpath/lavigne_t2.v 0000664 0000000 0000000 00000000052 13022141775 0024336 0 ustar 00root root 0000000 0000000 module lavigne_t2 (b);
input b;
endmodule
verilog-mode-20161124.fd230e6/tests/lineup.v 0000664 0000000 0000000 00000000144 13022141775 0020243 0 ustar 00root root 0000000 0000000 module ocnSwitchClockGen(output reg ocnSwitchClock);
parameter ocnSwitchClockPeriod = 2000;
verilog-mode-20161124.fd230e6/tests/local_vmode.x 0000664 0000000 0000000 00000000240 13022141775 0021232 0 ustar 00root root 0000000 0000000 module local_vmode ();
local_vmode_sub sub (/*AUTOINST*/);
endmodule
// Local Variables:
// mode: Verilog
// verilog-library-flags:("+libext+.x")
// End:
verilog-mode-20161124.fd230e6/tests/local_vmode_sub.x 0000664 0000000 0000000 00000000133 13022141775 0022104 0 ustar 00root root 0000000 0000000 module local_vmode_sub (input in);
endmodule
// Local Variables:
// mode: Verilog
// End:
verilog-mode-20161124.fd230e6/tests/mac_autosense_dot.v 0000664 0000000 0000000 00000000423 13022141775 0022443 0 ustar 00root root 0000000 0000000 //From: Michael McNamara
//Date: Tue, 27 Jun 2000 04:38:32 -0700 (PDT)
module x;
always @ (/*AS*/top.agc_tool.adc_dta_i or top.agc_tool.adc_preagc_dta_i) begin
agctoolerr = top.agc_tool.adc_dta_i / top.agc_tool.adc_preagc_dta_i;
end
endmodule
verilog-mode-20161124.fd230e6/tests/mac_test2.sv 0000664 0000000 0000000 00000000406 13022141775 0021014 0 ustar 00root root 0000000 0000000 module foobar;
sequence s_1;
{txd, txdk} && (ppd == 3'b000) && !txe;
endsequence // s_1
sequence s_phy_transmitting;
{rxd, rxdk} &&
((ppd == 3'b000) || (ppd == 3'b001))
&& rxv;
endsequence // s_phy_transmitting
endmodule
verilog-mode-20161124.fd230e6/tests/mac_test2.v 0000664 0000000 0000000 00000000406 13022141775 0020631 0 ustar 00root root 0000000 0000000 module foobar;
sequence s_1;
{txd, txdk} && (ppd == 3'b000) && !txe;
endsequence // s_1
sequence s_phy_transmitting;
{rxd, rxdk} &&
((ppd == 3'b000) || (ppd == 3'b001))
&& rxv;
endsequence // s_phy_transmitting
endmodule
verilog-mode-20161124.fd230e6/tests/more_params.v 0000664 0000000 0000000 00000002022 13022141775 0021251 0 ustar 00root root 0000000 0000000 module InstName (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [7:0] in;
output [7:0] out;
wire [7:0] out = ~in;
endmodule // bottm
module top (/*AUTOARG*/
// Outputs
outgo,
// Inputs
incom
);
input [31:0] incom;
output [31:0] outgo;
/* AUTO_LISP(defun getparam2 (strg)
(string-match "[^0-9]*[0-9]+[^0-9]*\\([0-9]+\\)" strg)
(match-string 1 strg))*/
/* InstName AUTO_TEMPLATE (
.out (@),
.in (@"(getparam2 vl-cell-name)"),
);
*/
InstName BT0_2 (/*AUTOINST*/
// Outputs
.out (0), // Templated
// Inputs
.in (2)); // Templated
InstName BT1_3 (/*AUTOINST*/
// Outputs
.out (1), // Templated
// Inputs
.in (3)); // Templated
InstName BT2_5 (/*AUTOINST*/
// Outputs
.out (2), // Templated
// Inputs
.in (5)); // Templated
InstName BT3_9 (/*AUTOINST*/
// Outputs
.out (3), // Templated
// Inputs
.in (9)); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests/morrison.v 0000664 0000000 0000000 00000000334 13022141775 0020620 0 ustar 00root root 0000000 0000000 `define XYZ 4'ha
module test ();
always @(/*AUTOSENSE*/r or x)
begin
casex(x)
5: d = {r, `XYZ };
endcase
end
endmodule // test
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/params_multiline_msg618.v 0000664 0000000 0000000 00000000606 13022141775 0023424 0 ustar 00root root 0000000 0000000 module testMultiLineParams (/*AUTOARG*/) ;
`include "params_multiline_msg618_inc.vh"
reg comboIn, comboOut;
// expect AUTOSENSE to be comboIn only, no params
always @ ( /*AUTOSENSE*/comboIn) begin
comboOout = param1 & param2 & param3 & comboIn;
end
endmodule // foo
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/params_multiline_msg618_inc.vh 0000664 0000000 0000000 00000000224 13022141775 0024421 0 ustar 00root root 0000000 0000000 parameter
// full line comment
param1 = 1'b1, // trailing comment
param2 = 1'b0, /* trailing comment */
// full line comment
param3 = 1'b1;
verilog-mode-20161124.fd230e6/tests/property_test.v 0000664 0000000 0000000 00000003663 13022141775 0021703 0 ustar 00root root 0000000 0000000
//////////////////////////////////////////////////////////////////////////////
//
// Main
//
//////////////////////////////////////////////////////////////////////////////
module test();
integer count;
bit test_clk;
// Create a test clock
always #01.8 test_clk = ~test_clk;
//**********************************************************************
// Testing.
// Shift a moving set of ones up the input vector. At each shift
// the outputs should change, which is checked by the assertions
// below. This test doesnt care which output changes, as that was
// checked to be accurate by formal means.
//**********************************************************************
initial begin
count=0;
end
always @(posedge test_clk) begin
count++;
end
//**********************************************************************
// SV assertions
//**********************************************************************
property p_lane_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(lane_inputs) |-> !$stable(lane_outputs);
endproperty
a_lane_output_change_on_input_change: assert property (p_lane_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (lane)",
lane_inputs);
end // UNMATCHED !!
endproperty //FIXME
property p_sup_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(sup_inputs) |-> !$stable(sup_outputs);
endproperty
a_sup_output_change_on_input_change: assert property (p_sup_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (sup)",
sup_inputs);
end
endproperty
endmodule // test
verilog-mode-20161124.fd230e6/tests/reversed_bits.v 0000664 0000000 0000000 00000001017 13022141775 0021607 0 ustar 00root root 0000000 0000000 module lbnsub
(/*AUTOARG*/
// Outputs
outgo,
// Inputs
income
);
input [7:4] income;
output [7:4] outgo;
wire [7:4] outgo = income;
endmodule
module lbm
(/*AUTOARG*/
// Outputs
outgo,
// Inputs
income
);
input [7:4] income;
output [7:4] outgo;
/*
lbnsub AUTO_TEMPLATE (
// Inputs
.income (income[4:7]));
*/
lbnsub lbnsub (/*AUTOINST*/
// Outputs
.outgo (outgo[7:4]),
// Inputs
.income (income[4:7])); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests/set_membership.sv 0000664 0000000 0000000 00000001452 13022141775 0022143 0 ustar 00root root 0000000 0000000 import avm_pkg::*;
import tinyalu_pkg::*;
module top;
alu_operation req;
string msg;
integer i;
initial begin
$display ("---- A or B inside {0,8'hFF} ----");
for (i = 1; i<=5; i++) begin
req = new();
assert( a() with {A} );
req.randomize()
with
{
A inside {0,8'hFF};
B inside {0,8'hFF};
};
$sformat (msg,"ALU Request: %s", req.convert2string());
avm_report_message("TOP",msg);
$display;
$display ("---- op inside [add_op : mul_op] ----");
for (i = 1; i<=10; i++) begin
req = new();
assert(
req.randomize() with
{
op inside {[add_op : mul_op]};
}
);
$sformat (msg,"ALU Request: %s", req.convert2string());
avm_report_message("TOP",msg);
end // for (i = 1; i<=10; i++)
end // initial begin
endmodule // req_reader
verilog-mode-20161124.fd230e6/tests/singh.v 0000664 0000000 0000000 00000002032 13022141775 0020055 0 ustar 00root root 0000000 0000000 // HERE IS THE TEST CASE
module bt (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [7:0] in;
output [7:0] out;
wire [7:0] out = ~in;
endmodule // bottm
module top (/*AUTOARG*/
// Outputs
outgo,
// Inputs
incom
);
input [31:0] incom;
output [31:0] outgo;
/* bt AUTO_TEMPLATE (
.in (incom[@"(+ (* 8 @) 7)":@"(* 8 @)"]),
.out (outgo[@"(concat (int-to-string (+ (* 8 @) 7)) \":\" (int-to-string ( * 8 @)))"]));
*/
bt BT0 (/*AUTOINST*/
// Outputs
.out (outgo[7:0]), // Templated
// Inputs
.in (incom[7:0])); // Templated
bt BT1 (/*AUTOINST*/
// Outputs
.out (outgo[15:8]), // Templated
// Inputs
.in (incom[15:8])); // Templated
bt BT2 (/*AUTOINST*/
// Outputs
.out (outgo[23:16]), // Templated
// Inputs
.in (incom[23:16])); // Templated
bt BT3 (/*AUTOINST*/
// Outputs
.out (outgo[31:24]), // Templated
// Inputs
.in (incom[31:24])); // Templated
endmodule // top
verilog-mode-20161124.fd230e6/tests/sol_asense.v 0000664 0000000 0000000 00000005063 13022141775 0021107 0 ustar 00root root 0000000 0000000 module x (/*AUTOARG*/
// Inputs
MIERHW, MBOOTH_P, CEIopMADH_E_D2_R, CEIopMAZH_E_D2_R, DDATAH, DIV2HI, HI_R, MCLA, MCLASH,
MULTSHCYC, MULTUSCYC, HI_P
);
input [18:0] MIERHW;
integer i;
integer MTEMP1;
integer MTEMP2;
input MBOOTH_P;
input CEIopMADH_E_D2_R;
input CEIopMAZH_E_D2_R;
input DDATAH;
input DIV2HI;
input HI_R;
input MCLA;
input MCLASH;
input MULTSHCYC;
input MULTUSCYC;
input HI_P;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
always @(/*AUTOSENSE*/MIERHW) begin
for (i=0; i<=5; i=i+1) begin
MTEMP1[3:0] = {MIERHW[i*3+3],
MIERHW[i*3+2],
MIERHW[i*3+1],
MIERHW[i*3+0]};
casex (MTEMP1)
4'b0000: MTEMP2 = 4'b0101; // +0
4'b0001: MTEMP2 = 4'b0001; // +1
4'b0010: MTEMP2 = 4'b0001; // +1
4'b0011: MTEMP2 = 4'b0010; // +2
4'b0100: MTEMP2 = 4'b0010; // +2
4'b0101: MTEMP2 = 4'b0100; // +3
4'b0110: MTEMP2 = 4'b0100; // +3
4'b0111: MTEMP2 = 4'b1000; // +4
4'b1000: MTEMP2 = 4'b0111; // -4
4'b1001: MTEMP2 = 4'b1011; // -3
4'b1010: MTEMP2 = 4'b1011; // -3
4'b1011: MTEMP2 = 4'b1101; // -2
4'b1100: MTEMP2 = 4'b1101; // -2
4'b1101: MTEMP2 = 4'b1110; // -1
4'b1110: MTEMP2 = 4'b1110; // -1
4'b1111: MTEMP2 = 4'b1010; // -0
endcase
end
{MBOOTH_P[i*4+3],
MBOOTH_P[i*4+2],
MBOOTH_P[i*4+1],
MBOOTH_P[i*4+0]} = MTEMP2[3:0];
end
// always @(/*AUTOnotSENSE*/
// __CEIopMADH_E_D2_R or __CEIopMAZH_E_D2_R or __DIV2HI or
// __MULTUSCYC or __MULTSHCYC or
// __DDATAH or __HI_R or __MCLA or __MCLASH) begin
// always @(/*AUTOSENSE*/DDATAH or HI_R or MCLA or MCLASH) begin
`define DMCLASH MCLASH
`define DCONST 1'b1
always @(/*AUTOSENSE*/CEIopMADH_E_D2_R or CEIopMAZH_E_D2_R or DDATAH or DIV2HI or MCLA or MCLASH
or MULTSHCYC or MULTUSCYC) begin
case (1'b1)
CEIopMADH_E_D2_R: HI_P = MCLA;
CEIopMAZH_E_D2_R: HI_P = MCLA;
DIV2HI: HI_P = DDATAH;
MULTUSCYC: HI_P = MCLA;
MULTSHCYC: HI_P = `DMCLASH;
default: HI_P = `DCONST;
endcase
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests/src_frag.vs 0000664 0000000 0000000 00000003453 13022141775 0020726 0 ustar 00root root 0000000 0000000 module src_frag (
input logic inp_signal_0, // Input Signal 0
input logic inp_signal_1, // Input Signal 1
input logic inp_signal_2, // Input Signal 2
input logic [10:0] inp_signal_3; // Input Signal 3
input logic inp_signal_4, // Input Signal 4
output logic outp_signal_0, // Output Signal 0
inout logic test,
output logic outp_signal_1 // Output Signal 1
);
logic [7:0] local_0; // Local Signal 0
logic local_1; // Local Signal 1
logic local_3; // Local Signal 3
var logic local_4; // Local Signal 4
var logic local_5; // Local Signal 5
logic signed [1:0] local_6;
logic local_1; // Local Signal 1
input logic in_lg;
inout logic io_lg;
output logic o_lg;
ref logic r_lg;
const logic c_rg;
static logic s_rg;
protected logic p_lg;
local logic l_lg;
localparam logic lp_lg = 23;
parameter logic p_lg = 32;
typedef logic td_lg;
input wire foo;
logic local_3; // Local Signal 3
var logic local_5; // Local Signal 5
byte B;
shortint si;
int f;
longint li;
integer I;
int unsigned uI;
time t;
bit b;
logic l;
reg r;
shortreal sR;
real R;
realtime Rt;
supply0 s0;
supply1 s1;
tri tr;
triand tra;
trior tro;
trireg trr;
tri0 tr0;
tri1 tr1;
uwire uw;
wire w;
wand wa;
wor wo;
string s;
event e;
chandle ch;
virtual v;
enum en;
genvar g;
struct st;
union u;
mailbox mb;
semaphore sm;
defparam v_lg = 56;
endmodule // src_frag
// Local Variables:
// mode: Verilog
// End:
verilog-mode-20161124.fd230e6/tests/subdir/ 0000775 0000000 0000000 00000000000 13022141775 0020051 5 ustar 00root root 0000000 0000000 verilog-mode-20161124.fd230e6/tests/subdir/flag_f_reeves_IBUF.v 0000664 0000000 0000000 00000000071 13022141775 0023632 0 ustar 00root root 0000000 0000000 module flag_f_reeves_IBUF (input a, output q);
endmodule
verilog-mode-20161124.fd230e6/tests/sv_import.v 0000664 0000000 0000000 00000000266 13022141775 0020776 0 ustar 00root root 0000000 0000000 module dpi_test ();
/* FIXME
import "DPI-C" context task c_task (input int i,
output int o);
logic [7:0] byte_array[1:20];
*/
endmodule // dpi_test
verilog-mode-20161124.fd230e6/tests/t_autoinst_def_clk.v 0000664 0000000 0000000 00000001330 13022141775 0022605 0 ustar 00root root 0000000 0000000 module t_autoinst_def_clk
(/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input a, // To sub of sub.v
input b, // To sub of sub.v
input clk, // To sub of sub.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output c // From sub of sub.v
// End of automatics
);
sub sub
(/*AUTOINST*/
// Outputs
.c (c),
// Inputs
.clk (clk),
.a (a),
.b (b));
endmodule // sdc_wombat
module sub
(input clk,
input a,
input b,
output c
);
clocking cb
@(posedge clk);
endclocking
default clocking cb;
endmodule
verilog-mode-20161124.fd230e6/tests/task.v 0000664 0000000 0000000 00000000440 13022141775 0017710 0 ustar 00root root 0000000 0000000 module foo(input bit [3:0] def,
input bit ghi,
input bit [1:0] jkl);
task cba(input bit [3:0] a,
input b,
c);
endtask // cba
task abc(input bit [3:0] def,
input bit ghi,
input bit [1:0] jkl);
endtask // abc
endmodule // foo
verilog-mode-20161124.fd230e6/tests/testcase.sv 0000664 0000000 0000000 00000000401 13022141775 0020741 0 ustar 00root root 0000000 0000000 `define moo 1
class foo;
extern function void bar();
endclass: foo
function void foo::bar();
int variable;
endfunction: bar
`define moo 1
class fu;
extern function void br();
endclass: fu
function void fu::br();
int variable;
endfunction: br
verilog-mode-20161124.fd230e6/tests/testcases.v 0000664 0000000 0000000 00000011552 13022141775 0020752 0 ustar 00root root 0000000 0000000 //Verilint 182 off // WARNING: Illegal statement for synthesis: $realtobits (in1)
//Verilint 311 off // WARNING: Converting real to unsigned: $realtobits (in1)
//Verilint 20 off // WARNING: Assign statement may not be synthesizable: assign out7[i] = ...;
//Verilint 599 off // WARNING: This construct is not supported by Synopsys
//Verilint 433 off // WARNING: More than one top level module
//Verilint 71 off // WARNING: Case statement without default clause
module testmodule (/*AUTOARG*/
// Outputs
out1, out2, out3, out4, out5, out7, out8, outb2, outb3, outb4, outb6, outb7, outb8, outb9,
outb10, outw1, outw2, outw3,
// Inputs
in1, in2, in3, in4, in5
);
function [2:0] ffs;
input [2:0] in;
ffs = in & 3'b010;
endfunction
task show;
input [2:0] in;
begin
$display ("Hi %x", in);
end
endtask
input [2:0] in1,in2,in3,in4,in5;
output [2:0] out1, out2,out3,out4,out5,out7,out8;
output outb2,outb3,outb4,outb6,outb7,outb8,outb9,outb10;
output [7:0] outw1,outw2,outw3;
reg [2:0] memarry [0:2];
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0] out1;
reg [2:0] out2;
reg [2:0] out3;
reg [2:0] out4;
reg [2:0] out5;
reg [2:0] out8;
reg outb2;
reg outb3;
reg outb4;
reg outb6;
reg outb7;
reg [7:0] outw1;
reg [7:0] outw2;
reg [7:0] outw3;
// End of automatics
wire outb8=1'b1, outb9=|{in1[0],in2[0]}, outb10=1'b0;
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
:ignore_label
out1 = $realtobits(in1);
out2 = ffs(in1 | (in2) );
out3 = ffs /*check*/ (in2);
$display ("chk ", in1);
show (in4);
if (|in3) out4=1; else out4=0;
end
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in5) begin
casex ({in5[1:0], (3'b010==in2)})
3'bx_1_0: out5=3'b000;
3'bx_1_1: out5=3'b010;
3'bx_0_x: out5=3'b100;
endcase
casex ({in3[in1]})
1'bx: out5=3'b000;
endcase
end
/*AUTO_CONSTANT (`temp) */
`define temp 3'b010
always @(/*AUTOSENSE*/in3) begin
outb6 = (in3 == `temp);
end
integer i;
reg [2:0] out7;
always @ (/*AUTOSENSE*/in1) begin
for (i=0; i<3; i=i+1) begin
assign out7[i] = ~in1[i];
end
end
always @ (/*AUTOSENSE*/in1 or in2 or in3) begin
{outw1 [ffs(in1)], outw2 [ffs(in2)]} = 2'b10;
{outw3[(|in1)?in2:in3], outb2} = 2'b10;
end
initial memarry[0] = in2;
always @ (/*AUTOSENSE*/ /*memory or*/ in1) begin
$display (memarry[in1]);
end
always @(/*AUTOSENSE*/in1 or in2)
casex(in1[1:0]) // synopsys full_case parallel_case
2'b01 : out8 = 3'b001;
2'b10 : out8 = 3'b010;
default
out8 = in2;
endcase
parameter READ = 3'b111,
//WRITE = 3'b111,
CFG = 3'b010;
//supply1 one;
always @(/*AUTOSENSE*/in1 or in2) begin
outb7 = (in1==READ) || (in2==CFG);
end
always @(/*AUTOSENSE*/in1) begin
if (|in1) $display("We're at %t\n",$time);
end // case: default
`define shift_instr 5'b01011
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4 or in5 or outw1)
/*AUTO_CONSTANT(`shift_instr)*/
begin: label_no_sense
casex (outw1) // synopsys full_case parallel_case
{`shift_instr,3'bxxx}:
outb3 = in3[0];
8'b00001x10: outb3 = in4[0];
8'b00110011:
if (in5[0])
outb3 = in1[0];
else
outb3 = in2[1];
default
outb3 = in4[0];
endcase
end
parameter WIDLE = 0; // No Manual Write Burst
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
case(1'b1)
in2[WIDLE]:
outb4 = in1[0];
in3[in4]:
outb4 = in1[0];
default:
outb4 = 1'bx;
endcase
end
endmodule
module darren_jones_2 (/*AUTOARG*/
// Outputs
next_WSTATE,
// Inputs
WSTATE
);
input [1:0] WSTATE;
output [1:0] next_WSTATE;
reg [1:0] next_WSTATE;
parameter
WIDLE = 0, // No Manual Write Burst
WCB0 = 1; // 1st of the 4 Manual Write Burst
always @ (/*AUTOSENSE*/WSTATE) begin
next_WSTATE = 2'b0;
case (1'b1)
WSTATE[WIDLE]:
next_WSTATE[1'b0] = 1'b1;
WSTATE[WCB0]:
next_WSTATE[WCB0] = 1'b1;
endcase
end
endmodule
module darren_jones_3 (/*AUTOARG*/
// Outputs
var1,
// Inputs
state
);
input [2:1] state;
output var1;
reg var1;
parameter
IDLE = 1,
CAS1 = 2;
always @(/*AUTOSENSE*/state) begin
case (1'b1)
state[IDLE] : begin
var1 = 1'b1;
end
state[CAS1] : begin
var1 = 1'b1;
end
default : begin
var1 = 1'b1;
end
endcase
end
always @(/*AUTOSENSE*/add or lo or mc_32pff or mc_losel or slo or var1) begin
case(mc_losel)
6'b000001: lo_mux = mc_32pff ? {add[39:0],lo[31:8]} :
{add[7:0],lo[63:8]};
6'b010000: lo_mux = lo;
6'b100000: lo_mux = var1 ? IDLE : slo;
endcase
end // always @ (...
endmodule
verilog-mode-20161124.fd230e6/tests/tss_max32.v 0000664 0000000 0000000 00000002614 13022141775 0020576 0 ustar 00root root 0000000 0000000 // $Id: tss_max32.v,v 1.6 1999/01/20 17:34:54 wsnyder Exp $
//============================================================================
`time_scale
module tss_max32 (/*AUTOARG*/
// Outputs
max,
// Inputs
a, b
);
//======================================================================
// Inputs/Outputs
//======================================================================
input [31:0] a; // Time a
input [31:0] b; // Time b
output [31:0] max; // MAX (a,b)
//======================================================================
// Automatic Wire/Register Declarations
//======================================================================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
//======================================================================
// Comparison
//======================================================================
wire alessb; // a
module top_test(/*AUTOARG*/
// Outputs
ba, aa,
// Inputs
z, dc, db, da, \c-escaped-vec , \c-escaped-nvec , Z_int, Z0_int
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output aa; // From l1 of leaf.v
output ba; // From l1 of leaf.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0] Z0_int; // To l1 of leaf.v
input [15:0] Z_int; // To l1 of leaf.v
input \c-escaped-nvec ; // To l1 of leaf.v
input [2:0] \c-escaped-vec ; // To l1 of leaf.v
input da; // To l1 of leaf.v
input [1:0] db; // To l1 of leaf.v
input [2:0] dc; // To l1 of leaf.v
input z; // To l1 of leaf.v
// End of automatics
/* leaf AUTO_TEMPLATE (
// Original reported bug
.a ({aa, test2.test3.no, test3.test4.no2}),
// Others
.b ( ~ ba),
.c ({\c-escaped-nvec , \c-escaped-vec [2:0] }),
.d ({da,~ db [1:0] , dc [2:0]}),
// Msg246
.e ({{4*1{1'b0}},Z_int[15:0],{1'b4{1'b0}},Z0_int[7:0]}),
.f (hi.ear.ial),
);
*/
leaf l1 (/*AUTOINST*/
// Outputs
.a ({aa, test2.test3.no, test3.test4.no2}), // Templated
.b ( ~ ba), // Templated
// Inputs
.c ({\c-escaped-nvec , \c-escaped-vec [2:0] }), // Templated
.d ({da,~ db [1:0] , dc [2:0]}), // Templated
.e ({{4*1{1'b0}},Z_int[15:0],{1'b4{1'b0}},Z0_int[7:0]}), // Templated
.f (hi.ear.ial), // Templated
.z (z));
endmodule // top_test
module leaf(/*AUTOARG*/
// Outputs
a, b,
// Inputs
c, d, e, f, z
);
output a;
output b;
input c;
input d;
input e;
input f;
input z;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinout_ma.v 0000664 0000000 0000000 00000001527 13022141775 0022152 0 ustar 00root root 0000000 0000000 module foo
(
input soutb,
output sina,
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input sinb, // To i_bar of bar.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output souta // From i_bar of bar.v
// End of automatics
) ;
bar i_bar(/*AUTOINST*/
// Outputs
.souta (souta),
.soutb (soutb),
// Inputs
.sina (sina),
.sinb (sinb));
endmodule // foo
module bar (/*AUTOARG*/
// Outputs
souta, soutb,
// Inputs
sina, sinb
) ;
input sina, sinb;
output souta, soutb;
endmodule // bar
verilog-mode-20161124.fd230e6/tests_ok/autoinout_moller.v 0000664 0000000 0000000 00000002022 13022141775 0023036 0 ustar 00root root 0000000 0000000 module a ( /*AUTOARG*/
// Outputs
o1,
// Inouts
io1,
// Inputs
i1
) ;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input i1; // To b of b.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output o1; // From b of b.v
// End of automatics
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout io1; // To/From b of b.v
// End of automatics
b b
(/*AUTOINST*/
// Outputs
.o1 (o1),
// Inouts
.io1 (io1),
// Inputs
.i1 (i1));
endmodule // a
module b (/*AUTOARG*/
// Outputs
o1,
// Inouts
io1,
// Inputs
i1
) ;
input i1 ;
output o1 ;
inout io1 ;
endmodule // b
verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v 0000664 0000000 0000000 00000003217 13022141775 0023045 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOARG*/
// Outputs
sec_out,
// Inouts
sec_io,
// Inputs
sec_ina
);
/*AUTOINPUT("^s")*/
// Beginning of automatic inputs (from unused autoinst inputs)
input sec_ina; // To instio of instio.v
// End of automatics
/*AUTOINOUT("^s")*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout sec_io; // To/From instio of instio.v
// End of automatics
/*AUTOOUTPUT("^s")*/
// Beginning of automatic outputs (from unused autoinst outputs)
output sec_out; // From instio of instio.v
// End of automatics
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
instio instio (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
.sec_out (sec_out),
// Inouts
.lower_io (lower_io),
.sec_io (sec_io),
// Inputs
.lower_ina (lower_ina),
.sec_ina (sec_ina));
endmodule
module instio (/*AUTOARG*/
// Outputs
lower_out, sec_out,
// Inouts
lower_io, sec_io,
// Inputs
lower_ina, sec_ina
);
input lower_ina;
inout lower_io;
output lower_out;
input sec_ina;
inout sec_io;
output sec_out;
wire lower_out = lower_ina | lower_io;
wire sec_out = sec_ina | sec_io;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v 0000664 0000000 0000000 00000006117 13022141775 0022257 0 ustar 00root root 0000000 0000000 module parent
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [3:0] a2, // To sub_module of child_a.v
input [3:0] a3, // To sub_module of child_a.v
input clk, // To sub_module of child_a.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output d, // From sub_module of child_a.v
// End of automatics
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout [5:0] c, // To/From sub_module of child_a.v, ...
inout [5:0] c2, // To/From sub_module of child_a.v, ...
inout c3 // To/From sub_module of child_a.v, ...
// End of automatics
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] a; // From sub_module of child_b.v
wire [3:0] a4; // From sub_module of child_b.v
wire [2:0] b; // From sub_module of child_a.v
wire [2:0] b2; // From sub_module of child_a.v
wire [2:0] b3; // From sub_module of child_a.v
wire [2:0] b4; // From sub_module of child_a.v
// End of automatics
child_a sub_module
(/*AUTOINST*/
// Outputs
.b (b[2:0]),
.b2 (b2[2:0]),
.b3 (b3[2:0]),
.b4 (b4[2:0]),
.d (d),
// Inouts
.c (c[5:0]),
.c2 (c2[5:0]),
.c3 (c3),
// Inputs
.a (a[3:0]),
.a2 (a2[3:0]),
.a3 (a3[3:0]),
.a4 (a4[3:0]),
.clk (clk));
child_b sub_module
(/*AUTOINST*/
// Outputs
.a (a[3:0]),
.a4 (a4[3:0]),
// Inouts
.c (c[5:0]),
.c2 (c2[5:0]),
.c3 (c3),
// Inputs
.b (b[2:0]),
.b2 (b2[2:0]),
.b3 (b3[2:0]),
.b4 (b4[2:0]),
.clk (clk));
endmodule // parent
module child_a
(
input [3:0] a,
input [3:0] a2,
input [3:0] a3,
input [3:0] a4,
inout [5:0] c,
inout [5:0] c2,
inout c3,
output [2:0] b,
output [2:0] b2,
output [2:0] b3,
output [2:0] b4,
input clk,
output d
);
endmodule
module child_b
(
output [3:0] a,
output [3:0] a4,
inout [5:0] c,
inout [5:0] c2,
inout c3,
input [2:0] b,
input [2:0] b2,
input [2:0] b3,
input [2:0] b4,
input clk
);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutcomp.v 0000664 0000000 0000000 00000001024 13022141775 0022344 0 ustar 00root root 0000000 0000000 module autoinoutmodule (/*AUTOARG*/
// Outputs
lower_ina, lower_inb,
// Inputs
lower_out
);
output lower_inb;
/*AUTOINOUTCOMP("inst")*/
// Beginning of automatic in/out/inouts (from specific module)
output lower_ina;
input lower_out;
// End of automatics
// Beginning of automatic in/out/inouts (from specific module)
wire lower_out = lower_ina | lower_inb;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutin.v 0000664 0000000 0000000 00000000515 13022141775 0022020 0 ustar 00root root 0000000 0000000 module autoinoutin (/*AUTOARG*/
// Inputs
lower_inb, lower_ina, lower_out
);
/*AUTOINOUTIN("inst")*/
// Beginning of automatic in/out/inouts (from specific module)
input lower_inb;
input lower_ina;
input lower_out;
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodport_bourduas_type.v 0000664 0000000 0000000 00000002231 13022141775 0026040 0 ustar 00root root 0000000 0000000 //-*- mode: Verilog; verilog-indent-level: 3; indent-tabs-mode: nil; tab-width: 1 -*-
module apl2c_connect(autoinoutmodport_type_intf ctl_i,
/*AUTOINOUTMODPORT("autoinoutmodport_type_intf", "ctl_cb")*/
// Beginning of automatic in/out/inouts (from modport)
input [4:0] inst,
input isel_t isel,
input replay
// End of automatics
);
/*AUTOASSIGNMODPORT("autoinoutmodport_type_intf", "ctl_cb", "ctl_i")*/
// Beginning of automatic assignments from modport
assign ctl_i.inst = inst;
assign ctl_i.isel = isel;
assign ctl_i.replay = replay;
// End of automatics
endmodule
interface autoinoutmodport_type_intf(input logic clk, input logic rst_n);
import uvm_pkg::*;
import ap_defines::*;
logic [4:0] inst;
isel_t isel;
logic replay;
clocking ctl_cb @(posedge clk);
input inst;
input isel;
input replay;
endclocking: ctl_cb
modport ctl_mp(clocking ctl_cb);
endinterface
// Local Variables:
// verilog-typedef-regexp:"_t"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule.v 0000664 0000000 0000000 00000001022 13022141775 0022671 0 ustar 00root root 0000000 0000000 module autoinoutmodule (/*AUTOARG*/
// Outputs
lower_out,
// Inputs
lower_inb, lower_ina
);
/*AUTOINOUTMODULE("inst")*/
// Beginning of automatic in/out/inouts (from specific module)
output lower_out;
input lower_inb;
input lower_ina;
// End of automatics
// Beginning of automatic in/out/inouts (from specific module)
wire lower_out = lower_ina | lower_inb;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_iface.v 0000664 0000000 0000000 00000000447 13022141775 0024032 0 ustar 00root root 0000000 0000000 // bug721
module my_core
(
/*AUTOINOUTMODULE("autoinoutmodule_iface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
my_svi.master my_svi_port
// End of automatics
/*AUTOINOUT*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
/*AUTOWIRE*/
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_iface_sub.v 0000664 0000000 0000000 00000000117 13022141775 0024675 0 ustar 00root root 0000000 0000000 module autoinoutmodule_iface_sub
(my_svi.master my_svi_port,
);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_ign.v 0000664 0000000 0000000 00000000542 13022141775 0023534 0 ustar 00root root 0000000 0000000 module autoinoutmodule (/*AUTOARG*/
// Outputs
lower_out
);
/*AUTOINOUTMODULE("inst","\(ina\|out\)","","ina")*/
// Beginning of automatic in/out/inouts (from specific module)
output lower_out;
// End of automatics
wire lower_out = lower_ina;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_re2.v 0000664 0000000 0000000 00000001164 13022141775 0023450 0 ustar 00root root 0000000 0000000 module autoinoutmodule_re2 (/*AUTOARG*/
// Outputs
lower_out,
// Inputs
lower_inb, lower_ina
);
/*AUTOINOUTMODULE("inst","","input.*")*/
// Beginning of automatic in/out/inouts (from specific module)
input lower_inb;
input lower_ina;
// End of automatics
/*AUTOINOUTMODULE("inst","","output.*")*/
// Beginning of automatic in/out/inouts (from specific module)
output lower_out;
// End of automatics
wire lower_out = lower_ina;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_regexp.v 0000664 0000000 0000000 00000000663 13022141775 0024255 0 ustar 00root root 0000000 0000000 module autoinoutmodule (/*AUTOARG*/
// Outputs
lower_out,
// Inputs
lower_ina
);
/*AUTOINOUTMODULE("inst","\(ina\|out\)")*/
// Beginning of automatic in/out/inouts (from specific module)
output lower_out;
input lower_ina;
// End of automatics
wire lower_out = lower_ina;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_v2k.v 0000664 0000000 0000000 00000000647 13022141775 0023467 0 ustar 00root root 0000000 0000000 module autoinoutmodule (
/*AUTOINOUTMODULE("inst")*/
// Beginning of automatic in/out/inouts (from specific module)
output lower_out,
input lower_inb,
input lower_ina
// End of automatics
);
wire lower_out = lower_ina | lower_inb;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinoutparam.v 0000664 0000000 0000000 00000000557 13022141775 0022520 0 ustar 00root root 0000000 0000000 module autoinoutparam (/*AUTOARG*/);
/*AUTOINOUTPARAM("inst","param1")*/
// Beginning of automatic parameters (from specific module)
parameter param1;
// End of automatics
/*AUTOINOUTPARAM("inst")*/
// Beginning of automatic parameters (from specific module)
parameter param2;
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinput_array_bug294.v 0000664 0000000 0000000 00000002342 13022141775 0023764 0 ustar 00root root 0000000 0000000 module mod1(input logic [1:0] reg1[4],
input logic reg2[5][6],
input logic [1:0] [3:0] [2:0] reg4);
endmodule
module mod2(output logic [1:0] reg1[4],
output logic [1:0] [3:0] [2:0] reg4);
endmodule
module dut (
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic reg2 [5][6] // To foo_i of mod1.v
// End of automatics
/*AUTOOUTPUT*/
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [1:0] reg1 [4]; // From drv_i of mod2.v
logic [1:0][3:0] [2:0] reg4; // From drv_i of mod2.v
// End of automatics
mod1 foo_i(/*AUTOINST*/
// Inputs
.reg1 (reg1/*[1:0].[4]*/),
.reg2 (reg2/*.[5][6]*/),
.reg4 (reg4/*[1:0][3:0][2:0]*/));
/* drv_i AUTO_TEMPLATE (.reg1(reg1[]), );*/
mod2 drv_i(/*AUTOINST*/
// Outputs
.reg1 (reg1/*[1:0].[4]*/),
.reg4 (reg4/*[1:0][3:0][2:0]*/));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinput_asharma.v 0000664 0000000 0000000 00000001503 13022141775 0023164 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOARG*/
// Outputs
lower_out,
// Inputs
lower_ina
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input lower_ina; // To inst of inst.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output lower_out; // From inst of inst.v
// End of automatics
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
inst inst (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
// Inputs
.lower_inb (1'b1), // Templated
.lower_ina (lower_ina));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinput_asharma_v2k.v 0000664 0000000 0000000 00000001432 13022141775 0023747 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input lower_ina, // To inst of inst.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output lower_out // From inst of inst.v
// End of automatics
);
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
inst inst (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
// Inputs
.lower_inb (1'b1), // Templated
.lower_ina (lower_ina));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_ignore.v 0000664 0000000 0000000 00000004207 13022141775 0024366 0 ustar 00root root 0000000 0000000 module xyz (/*AUTOARG*/
// Outputs
signal_f, signal_c,
// Inputs
signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output signal_c; // From u_abc of abc.v
output signal_f; // From u_def of def.v
// End of automatics
/*AUTOWIRE*/
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a ({1'b0, signal_f}),
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a ({1'b0, signal_f}), // Templated
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d ({1'b1, signal_c}),
.signal_e ({2'b11, signal_e}));
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d ({1'b1, signal_c}), // Templated
.signal_e ({2'b11, signal_e})); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e
);
input [1:0] signal_d;
input [2:0] signal_e;
output signal_f;
endmodule // def
// Local Variables:
// verilog-auto-ignore-concat: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau.v 0000664 0000000 0000000 00000001670 13022141775 0023665 0 ustar 00root root 0000000 0000000 module sub1 (/*AUTOARG*/
// Inouts
busout,
// Inputs
bus1
);
input [3:0] bus1;
inout [3:0] busout;
wire busout = bus1;
endmodule
module autoinput_concat_lau
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [1:0] foo, // To sub1 of sub1.v
// End of automatics
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout [1:0] fooout // To/From sub1 of sub1.v
// End of automatics
);
/* sub1 AUTO_TEMPLATE (
.busout ({2'b0,fooout[1:0]}),
.bus1 ({2'b0,~foo[1:0]}),
);
*/
sub1 sub1 (/*AUTOINST*/
// Inouts
.busout ({2'b0,fooout[1:0]}), // Templated
// Inputs
.bus1 ({2'b0,~foo[1:0]})); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau2.v 0000664 0000000 0000000 00000004126 13022141775 0023746 0 ustar 00root root 0000000 0000000 module xyz (/*AUTOARG*/
// Inputs
signal_e, signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
input signal_e; // To u_def of def.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire signal_c; // From u_abc of abc.v
wire signal_f; // From u_def of def.v
// End of automatics
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a ({1'b0, signal_f}),
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a ({1'b0, signal_f}), // Templated
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d ({1'b1, signal_c}),
.signal_e ({2'b11, signal_e}));
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d ({1'b1, signal_c}), // Templated
.signal_e ({2'b11, signal_e})); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e
);
input [1:0] signal_d;
input [2:0] signal_e;
output signal_f;
endmodule // def
verilog-mode-20161124.fd230e6/tests_ok/autoinput_none.v 0000664 0000000 0000000 00000001335 13022141775 0022512 0 ustar 00root root 0000000 0000000 // Julian Gorfajn
`default_nettype none
module top
(
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output wire o, // From sub of Sub.v
// End of automatics
// Beginning of automatic outputs (from unused autoinst outputs)
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input wire i // To sub of Sub.v
// End of automatics
);
Sub sub (/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.i (i));
endmodule
module Sub (input i, output o);
endmodule
// Local Variables:
// verilog-auto-declare-nettype: "wire"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinput_paren.v 0000664 0000000 0000000 00000001367 13022141775 0022665 0 ustar 00root root 0000000 0000000 module foo (/*AUTOARG*/
// Inputs
abd, abc
) ;
/*AUTOINPUT("ab\(c\|d\)")*/
// Beginning of automatic inputs (from unused autoinst inputs)
input abc; // To i_bar of bar.v
input abd; // To i_bar of bar.v
// End of automatics
bar i_bar(/*AUTOINST*/
// Outputs
.aaa (aaa),
// Inputs
.abc (abc),
.abd (abd),
.bca (bca));
endmodule // foo
module bar (/*AUTOARG*/
// Outputs
aaa,
// Inputs
abc, abd, bca
) ;
input abc,abd,bca;
output aaa;
endmodule // bar
verilog-mode-20161124.fd230e6/tests_ok/autoinsertlast_1.v 0000664 0000000 0000000 00000000513 13022141775 0022741 0 ustar 00root root 0000000 0000000 module ExampInsertLisp;
/*AUTOINSERTLAST(my-verilog-insert-hello "world")*/
// Beginning of automatic insert lisp
initial $write("hello world");
// End of automatics
endmodule
/*
Local Variables:
eval:
(defun my-verilog-insert-hello (who)
(insert (concat "initial $write(\"hello " who "\");\n")))
End:
*/
verilog-mode-20161124.fd230e6/tests_ok/autoinst_2k_fredriksen.v 0000664 0000000 0000000 00000000563 13022141775 0024123 0 ustar 00root root 0000000 0000000 module top ();
sub sub(/*AUTOINST*/
// Outputs
.b (b[PARAM2:0]),
// Inputs
.a (a[PARAM1:0]));
endmodule // top
module sub
#(parameter PARAM1=2,
PARAM2=3,
PARAM3=6)
( input wire [PARAM1:0] a,
output reg [PARAM2:0] b
);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_ams_vorwerk.v 0000664 0000000 0000000 00000002056 13022141775 0023731 0 ustar 00root root 0000000 0000000 module autoinst_ams_vorwerk;
latch latch (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.en (en),
.d (d));
endmodule
module latch (/*AUTOARG*/
// Outputs
q,
// Inputs
en, d
);
`ifdef __VAMS_ENABLE__
output (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) q;
`else
output q;
`endif
`ifdef __VAMS_ENABLE__
input (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) en;
`else
input en;
`endif
`ifdef __VAMS_ENABLE__
input (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) d;
`else
input d;
`endif
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_array.v 0000664 0000000 0000000 00000002500 13022141775 0022502 0 ustar 00root root 0000000 0000000 // bug637
module submod_a
(
//Inputs
input wire signed [15:0] serial_in,
//Outputs
output wire signed [15:0] parallel_out [0:7]
);
endmodule
module submod_b
(
//Inputs
input wire signed [15:0] parallel_out [0:7],
//Outputs
output wire signed [15:0] final_out [0:7]
);
endmodule
module top
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic signed [15:0] serial_in, // To a_inst of submod_a.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output logic signed [15:0] final_out [0:7] // From b_inst of submod_b.v
// End of automatics
);
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic signed [15:0] parallel_out [0:7]; // From a_inst of submod_a.v
// End of automatics
submod_a a_inst
(/*AUTOINST*/
// Outputs
.parallel_out (parallel_out/*[15:0].[0:7]*/),
// Inputs
.serial_in (serial_in[15:0]));
submod_b b_inst
(/*AUTOINST*/
// Outputs
.final_out (final_out/*[15:0].[0:7]*/),
// Inputs
.parallel_out (parallel_out/*[15:0].[0:7]*/));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_array_braket.v 0000664 0000000 0000000 00000005401 13022141775 0024035 0 ustar 00root root 0000000 0000000 module sub(output logic [1:-1] oned,
output logic [1:-1] [2:-1] twod,
output logic [1:-1] [2:-1] [3:-3] threed);
endmodule
module dut (
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [1:-1] b_oned; // From subb of sub.v
logic [3:-3] b_threed; // From subb of sub.v
logic [2:-1] b_twod; // From subb of sub.v
logic [1:-1] c_oned; // From subc of sub.v
logic [x][y] [3:-3] c_threed; // From subc of sub.v
logic [x] [2:-1] c_twod; // From subc of sub.v
logic [1:-1] d_oned; // From subd of sub.v
logic [1:-1][2:-1] [3:-3] d_threed; // From subd of sub.v
logic [1:-1] [2:-1] d_twod; // From subd of sub.v
logic [1:-1] oned; // From sub1 of sub.v
logic [1:-1][2:-1] [3:-3] threed; // From sub1 of sub.v
logic [1:-1] [2:-1] twod; // From sub1 of sub.v
// End of automatics
/* sub AUTO_TEMPLATE ();
*/
sub sub1 (/*AUTOINST*/
// Outputs
.oned (oned[1:-1]),
.twod (twod/*[1:-1][2:-1]*/),
.threed (threed/*[1:-1][2:-1][3:-3]*/));
/* sub AUTO_TEMPLATE (
.oned (b_oned[]),
.twod (b_twod[]),
.threed (b_threed[]));
*/
// NOTE this results in the wrong declaration for b_twod/b_threed
sub subb (/*AUTOINST*/
// Outputs
.oned (b_oned[1:-1]), // Templated
.twod (b_twod[2:-1]), // Templated
.threed (b_threed[3:-3])); // Templated
/* sub AUTO_TEMPLATE (
.oned (c_oned[]),
.twod (c_twod[x][]),
.threed (c_threed[x][y][]));
*/
sub subc (/*AUTOINST*/
// Outputs
.oned (c_oned[1:-1]), // Templated
.twod (c_twod[x][2:-1]), // Templated
.threed (c_threed[x][y][3:-3])); // Templated
/* sub AUTO_TEMPLATE (
.oned (d_oned[][]),
.twod (d_twod[][]),
.threed (d_threed[][]));
*/
sub subd (/*AUTOINST*/
// Outputs
.oned (d_oned[1:-1]), // Templated
.twod (d_twod/*[1:-1][2:-1]*/), // Templated
.threed (d_threed/*[1:-1][2:-1][3:-3]*/)); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_atregexp.v 0000664 0000000 0000000 00000002705 13022141775 0023212 0 ustar 00root root 0000000 0000000 module ex;
/* autoinst_paramover_sub AUTO_TEMPLATE "u_\(.*\)" (
.a(inA_@[]),
.b(outA_@[]),
);*/
autoinst_paramover_sub u_foo(/*AUTOINST*/
// Inouts
.a (inA_foo[bitsa:0]), // Templated
.b (outA_foo[bitsb:0])); // Templated
autoinst_paramover_sub u_bar(/*AUTOINST*/
// Inouts
.a (inA_bar[bitsa:0]), // Templated
.b (outA_bar[bitsb:0])); // Templated
autoinst_paramover_sub u_baz(/*AUTOINST*/
// Inouts
.a (inA_baz[bitsa:0]), // Templated
.b (outA_baz[bitsb:0])); // Templated
/* autoinst_paramover_sub AUTO_TEMPLATE (
.a(inN_@[]),
.b(outN_@[]),
);*/
autoinst_paramover_sub u_0_2(/*AUTOINST*/
// Inouts
.a (inN_0[bitsa:0]), // Templated
.b (outN_0[bitsb:0])); // Templated
autoinst_paramover_sub u_1_3(/*AUTOINST*/
// Inouts
.a (inN_1[bitsa:0]), // Templated
.b (outN_1[bitsb:0])); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_belkind_concat.v 0000664 0000000 0000000 00000002636 13022141775 0024335 0 ustar 00root root 0000000 0000000 module aaa (/*AUTOARG*/
// Outputs
y1, y0,
// Inputs
y3, y2
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output y0; // From bbb of bbb.v
output y1; // From bbb of bbb.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input y2; // To bbb of bbb.v
input y3; // To bbb of bbb.v
// End of automatics
/*AUTOWIRE*/
wire u0, u1, z0, z1;
/*
bbb AUTO_TEMPLATE (
.xo0 ({(u0), y0}),
.xo1 ({y1, (u1)}),
.xi0 ({(z0), y2}),
.xi1 ({y3, (z1)}),
);
*/
bbb bbb (/*AUTOINST*/
// Outputs
.xo0 ({(u0), y0}), // Templated
.xo1 ({y1, (u1)}), // Templated
// Inputs
.xi0 ({(z0), y2}), // Templated
.xi1 ({y3, (z1)})); // Templated
endmodule // aaa
module bbb (/*AUTOARG*/
// Outputs
xo0, xo1,
// Inputs
xi0, xi1
);
output [1:0] xo0, xo1;
input [1:0] xi0, xi1;
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire [1:0] xo0 = 2'h0;
wire [1:0] xo1 = 2'h0;
// End of automatics
endmodule // bbb
verilog-mode-20161124.fd230e6/tests_ok/autoinst_bits_lba.v 0000664 0000000 0000000 00000002030 13022141775 0023141 0 ustar 00root root 0000000 0000000 module lba
(/*AUTOnotARG*/
// Outputs
);
/* autoinst_bits_lba_gi AUTO_TEMPLATE (
.WWCmdI (WWCmdI[]));
*/
autoinst_bits_lba_gi gi (/*AUTOINST*/
// Outputs
.WWCmdI (WWCmdI[8:0]), // Templated
.WWADI (WWADI[31:0]),
// Inouts
.WWADB (WWADB[31:0]),
.WWCmdB (WWCmdB[8:0]),
// Inputs
.CLK (CLK),
.WWADoe (WWADoe),
.WWCoe (WWCoe),
.WWCmdIfOE (WWCmdIfOE[8:0]),
.WWADHold (WWADHold),
.iWWADO (iWWADO[31:0]));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_bits_lba_gi.v 0000664 0000000 0000000 00000006510 13022141775 0023627 0 ustar 00root root 0000000 0000000 module autoinst_bits_lba_gi
// ==xxxxxxx==
// xxxxxxxxx 1997-1998, xxxxx xxx.
// xxx xxxxxx xxxxxxxx
// ****************************************************************** /
// ****************************************************************** /
// xxxxx, xxxxxxxxxxxx
// xxxxxxx: xxx-4080
// xxxxxx: xxx xxxxxxx
// xxxxx: xxxxxxx 16, 1998
// ******************************************************************* /
// ******************************************************************* /
// xxxx xxxx: xxx_xx.x
// xxxxxxxx xxxxxxx:
// $xxx: xxx_xx.x,x $
// xxxxxxxx 1.3 1998/03/06 00:27:00 xxx
// -- xxxxx xxxxxxx xx xx.xxxx xxx xxxxxxxx xxxxxxx.
// -- xxxx xxxxxxxxxxxxx xx xx xxxxxxxxxxx xx xx.x xxx xx.x xx xxxxxxx xxx xxxxxxxxxxx.
// -- xxxx xxxxx xxx xxxxxxxxxxxxx xxx1'x (xxxxxxx xx xxxxx) xx xx.x xxx xxxx xxxxxx
// xxxxxxxxxx.
// -- xxxxx xxxxxxxxxx xxxxxxxx xx xxx xx xxxxxxxxxxx xxx xxxx xxxxxx xxxxxxxxxxxx xxxx.
// -- xx xxx xxxxxxxxx xxx xxxxxx xx xx xx xxx xxxxx xxxxx xx xxxx xxxxxxxx xx xxxx.
// -- xx xx xxxx xxxxxxx xxx xxx xxxx xxxxxx xxxxxx (xxx xxx xxxx) xxx xxx xxxx/xxxx
// xxxxxxxxxx xxxx xxxxxxx.
//
// xxxxxxxx 1.2 1998/03/04 18:58:55 xxx
// xxxxx xxxxxxxxx xxx-xx xxxxxxx xxxxxxx xx xxxx xxxxx.
//
// xxxxxxxx 1.1 1998/02/23 19:31:52 xxx
// xxxxx xxxxx xxxxxx xxx xxxx xxxxx xxxxx xxxxxxxxxx.
//
// ---------------------------------------------------------------
//
// xxxxxxx xxx xxxxxxxxx xxx xxxxx xxx xxxxxxx xxx
//
// xxxx xxxxxx xxxxx xxx xxxxx xxxxxx xxxxxxx/xxxx xxx xxxx
// xx.x xxx xx xx xxxxxxxxx xxxx xxxx.x xxxxxx xx
// xxxx xxx xxxxxxx xx xxx. xx xxxx xxxxates the
// bidir Foo Bus into a chip input for use by li.v
//
// This module also isolates for input to lbsm.v, and drives
// (if so indicated by lbsm.v) the bidir Fooileo Cmd bus.
//
//
(
CLK,
WWADoe,
WWCoe,
WWCmdIfOE,
WWADHold,
iWWADO,
WWCmdI,
WWADI,
WWADB,
WWCmdB
);
/////////////////////////////////////////////////////////////////////
// inputs
input CLK; // LBA clk
// inputs from lbsm.v
input WWADoe; // FooBus Addr/Data OE
input WWCoe; // FooBus Cmd OE
input [8:0] WWCmdIfOE; // FooBus Cmd if enabled
input WWADHold; // FooBus Addr hold
// inputs from li.v
input [31:0] iWWADO; // FooBus Address/Data out next cycle
/////////////////////////////////////////////////////////////////////
// outputs
// outputs to lbsm.v
output [8:0] WWCmdI; // FooBus Command in
// outputs to li.v
output [31:0] WWADI; // FooBus Address/Data in
/////////////////////////////////////////////////////////////////////
// bidirs
// bidirs to/from off-chip
inout [31:0] WWADB; // bidir FooBus addr/data
inout [8:0] WWCmdB; // bidir FooBus command
/////////////////////////////////////////////////////////////////////
// reg's for outputs (some flops, some not)
/////////////////////////////////////////////////////////////////////
// other flops
reg [31:0] WWADIfOE; // FooBus Addr/Data Out if enabled
endmodule
// Local Variables:
// eval:(if (fboundp `verilog-enable-indentation) (verilog-enable-indentation))
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_brucet.v 0000664 0000000 0000000 00000001646 13022141775 0022662 0 ustar 00root root 0000000 0000000 module io1_sub(/*AUTOARG*/
// Outputs
x, y, z,
// Inputs
a, b
);
input a;
input b;
output x;
output y;
output z;
andcell c0 (
.c (x),
/*AUTOINST*/
// Inputs
.a (a),
.b (b));
orcell c0 (
.c (y),
/*AUTOINST*/
// Inputs
.a (a),
.b (b));
nandcell c0 (
.c (z),
/*AUTOINST*/
// Inputs
.a (a),
.b (b));
endmodule
// Local Variables:
// verilog-library-files:("autoinst_brucet_library.v")
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_brucet_library.v 0000664 0000000 0000000 00000001201 13022141775 0024371 0 ustar 00root root 0000000 0000000 module andcell (/*AUTOARG*/
// Outputs
c,
// Inputs
a, b
);
input a;
input b;
output c;
wire c = a&b;
endmodule
module nandcell (/*AUTOARG*/
// Outputs
c,
// Inputs
a, b
);
input a;
input b;
output c;
wire c = !(a&b);
endmodule
module orcell (/*AUTOARG*/
// Outputs
c,
// Inputs
a, b
);
input a;
input b;
output c;
wire c = a|b;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_bug373.v 0000664 0000000 0000000 00000002735 13022141775 0022410 0 ustar 00root root 0000000 0000000 typedef struct packed {
logic [7:0] data;
logic wr_ena;
} mystruct_s;
module submod
(input logic a_port,
input logic [4:0] b_bus,
input mystruct_s single_struct_is_fine,
input mystruct_s [2:0] array_of_struct_is_not,
output logic status);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire status = 1'h0;
// End of automatics
endmodule // submod
module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic status; // From submod0 of submod.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
logic a_port; // To submod0 of submod.v
mystruct_s [2:0] array_of_struct_is_not; // To submod0 of submod.v
logic [4:0] b_bus; // To submod0 of submod.v
mystruct_s single_struct_is_fine; // To submod0 of submod.v
// End of automatics
submod submod0
(/*AUTOINST*/
// Outputs
.status (status),
// Inputs
.a_port (a_port),
.b_bus (b_bus[4:0]),
.single_struct_is_fine (single_struct_is_fine),
.array_of_struct_is_not (array_of_struct_is_not[2:0]));
endmodule // top
// Local Variables:
// verilog-typedef-regexp: "_s$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_case_chakradhara.v 0000664 0000000 0000000 00000001076 13022141775 0024617 0 ustar 00root root 0000000 0000000 module foo();
/*bar AUTO_TEMPLATE (
.pme\(.*\)_o (pme\1[]),
.PME\(.*\)_o (pMe\1[]),
.pme\(.*\)_o (pme\1[]),
);
*/
bar bar
(/*AUTOINST*/
// Inputs
.PME_o (pMe), // Templated
.pme_o (pme), // Templated
.pmE_o (pmE_o));
endmodule
module bar
(/*AUTOARG*/
// Inputs
PME_o, pme_o, pmE_o
);
input PME_o;
input pme_o;
input pmE_o;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_casefold_hou.v 0000664 0000000 0000000 00000001732 13022141775 0024025 0 ustar 00root root 0000000 0000000 typedef struct packed {
logic a,b,c;
} tTest;
module test
(
input clk,rst
);
wire [7:0] data_tm;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
tTest q; // From foo of foo.v
// End of automatics
/* foo AUTO_TEMPLATE (
.tm (data_tm),
);
*/
foo foo (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.clk (clk),
.rst (rst),
.tm (data_tm)); // Templated
/*AUTO_LISP(setq verilog-typedef-regexp "^t[A-Z]")*/
endmodule
module foo
(
input clk,
input rst,
input [7:0] tm,
output tTest q
);
endmodule
// Local Variables:
// verilog-case-fold:nil
// verilog-library-directories:(".")
// verilog-typedef-regexp:"^t[A-Z]"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_cavanaugh_pull.v 0000664 0000000 0000000 00000010467 13022141775 0024370 0 ustar 00root root 0000000 0000000
module fifo(/*AUTOARG*/
// Outputs
fifo_full_w, data_valid_r, rdata_r,
// Inputs
clk, rst_n, enqueue_w, data_in_w, dequeue_w, full_threshold
);
input clk;
input rst_n;
output fifo_full_w;
input enqueue_w;
input [(DATA_WIDTH-1):0] data_in_w;
output data_valid_r;
input dequeue_w;
input [1:0] full_threshold;
output [(DATA_WIDTH-1):0] rdata_r;
endmodule
module req (p_clk, carb_rst_rnp, req_rp, len_rxp, deq_req, deq_len, deq_val);
input p_clk;
input carb_rst_rnp;
input [4:0] len_rxp;
input req_rp;
input deq_req;
output [4:0] deq_len;
output deq_val;
reg [5:0] fifo_entry1_rp;
reg [5:0] fifo_entry2_rp;
reg [4:0] deq_len;
reg deq_val;
endmodule
module pull( /*AUTOARG*/
// Outputs
d_len, d_val,
// Inputs
clk, rst_rnpha, lenar_rxp, rem_rpd, d_rews
);
input clk;
input rst_rnpha;
input [4:0] lenar_rxp;
input rem_rpd;
input d_rews;
output [4:0] d_len;
output d_val;
/* req AUTO_TEMPLATE "\(g[a-z0-9]+\|g.*[0-9]\)" (
.p_clk (my_clk_@),
.len_rxp (carb_rst_rnp_@),
.carb_rst_rnp (pull_req1));
*/
req test432_gbe5(/*AUTOINST*/
// Outputs
.deq_len (deq_len[4:0]),
.deq_val (deq_val),
// Inputs
.p_clk (my_clk_gbe5), // Templated
.carb_rst_rnp (pull_req1), // Templated
.len_rxp (carb_rst_rnp_gbe5), // Templated
.req_rp (req_rp),
.deq_req (deq_req));
req gbe9_vreos(/*AUTOINST*/
// Outputs
.deq_len (deq_len[4:0]),
.deq_val (deq_val),
// Inputs
.p_clk (my_clk_gbe9), // Templated
.carb_rst_rnp (pull_req1), // Templated
.len_rxp (carb_rst_rnp_gbe9), // Templated
.req_rp (req_rp),
.deq_req (deq_req));
/* fifo AUTO_TEMPLATE "gbe[0-9]+_\([^\_]+\)" (
.clk (@_clk),
.\(.*data.*\) (@_\1),
.\(.*\)\(full\)\(.*\) (\1@\3),
.\(en\|de\)\(.\).+ (@_\1\2));
*/
fifo #(5) gbe2_pull_req (/*AUTOINST*/
// Outputs
.fifo_full_w (fifo_pull_w), // Templated
.data_valid_r (pull_data_valid_r), // Templated
.rdata_r (pull_rdata_r), // Templated
// Inputs
.clk (pull_clk), // Templated
.rst_n (rst_n),
.enqueue_w (pull_enq), // Templated
.data_in_w (pull_data_in_w), // Templated
.dequeue_w (pull_deq), // Templated
.full_threshold (pull_threshold)); // Templated
fifo #(5)
gbe1_pull_req_fifo( /*AUTOINST*/
// Outputs
.fifo_full_w (fifo_pull_w), // Templated
.data_valid_r (pull_data_valid_r), // Templated
.rdata_r (pull_rdata_r), // Templated
// Inputs
.clk (pull_clk), // Templated
.rst_n (rst_n),
.enqueue_w (pull_enq), // Templated
.data_in_w (pull_data_in_w), // Templated
.dequeue_w (pull_deq), // Templated
.full_threshold (pull_threshold)); // Templated
endmodule // pull_arb
verilog-mode-20161124.fd230e6/tests_ok/autoinst_ciu.v 0000664 0000000 0000000 00000000673 13022141775 0022155 0 ustar 00root root 0000000 0000000 module testmux
(
input wire [2:0] a
);
endmodule
module top_test();
/* testmux AUTO_TEMPLATE "\(.*\)$" (
.a (@_a_value[]),
);
*/
testmux foo1_1
(/*AUTOINST*/
// Inputs
.a (foo1_1_a_value[2:0])); // Templated
testmux foo1_2
(/*AUTOINST*/
// Inputs
.a (foo1_2_a_value[2:0])); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_clog2_bug522.v 0000664 0000000 0000000 00000001252 13022141775 0023463 0 ustar 00root root 0000000 0000000 // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by brad Dobbie.
module mod;
submod #
(.VEC_W(8),
.IDX_W($clog2(VEC_W)))
submod
(/*AUTOINST*/
// Outputs
.idx (idx[2:0]),
// Inputs
.vec (vec[7:0]));
endmodule
module submod (/*AUTOARG*/
// Outputs
idx,
// Inputs
vec
);
parameter VEC_W = 32;
parameter IDX_W = $clog2(VEC_W);
input [VEC_W-1:0] vec;
output [IDX_W-1:0] idx;
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_cmtcell_msg270.v 0000664 0000000 0000000 00000000443 13022141775 0024112 0 ustar 00root root 0000000 0000000 module ex;
subwidth u_a2 // commented
(/*AUTOINST*/
// Outputs
.bus4a (bus4a[0:3]));
endmodule
module subwidth (/*AUTOARG*/
// Outputs
bus4a
);
output [0:3] bus4a;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_cmtinst_bug383.v 0000664 0000000 0000000 00000002754 13022141775 0024153 0 ustar 00root root 0000000 0000000 module t;
/*fifo_s AUTO_TEMPLATE (
.ignored_signal (1'b1),
.out_signal (NC),
.out_bus (out_bus[]),
);
*/
fifo_s data_fifo (
//fifo_s data_fifo (
// Inputs
.clk (fifo_clk),
/*AUTOINST*/
// Outputs
.out_bus (out_bus[31:0]), // Templated
.out_signal (NC), // Templated
// Inputs
.ignored_signal (1'b1), // Templated
.reset (reset));
/*fifo_s AUTO_TEMPLATE (
.ignored_signal (1'b1),
.out_signal (NC),
.out_bus (out_bus[]),
);
*/
//fifo_s data_fifo (
fifo_s data_fifo (
// Inputs
.clk (fifo_clk),
/*AUTOINST*/
// Outputs
.out_bus (out_bus[31:0]), // Templated
.out_signal (NC), // Templated
// Inputs
.ignored_signal (1'b1), // Templated
.reset (reset));
endmodule
module fifo_s;
input ignored_signal;
input reset;
output [31:0] out_bus;
output out_signal;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_cmtparen_tennant.sv 0000664 0000000 0000000 00000010534 13022141775 0025115 0 ustar 00root root 0000000 0000000 typedef node logic;
module top
#(parameter COLS = 4
)
( input logic clk,
input logic rstb,
input logic [COLS-1:0] ival,
input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
input logic [COLS-1:0][7:0] isig1,
input logic [COLS-1:0][6:0] isig2,
input logic [COLS-1:0][5:0] isig3,
/*AUTOINPUT*/
output logic [COLS-1:0] oval,
output logic [COLS-1:0][1:0] odata,
output logic [COLS-1:0] s3_oval,
output logic [COLS-1:0][1:0] s3_odata
/*AUTOOUTPUT*/
);
logic [COLS-1:0][1:0] s1_odata; // From isub1 of sub1.v
logic [COLS-1:0] s1_oval; // From isub1 of sub1.v
/*AUTOWIRE*/
/* sub2 AUTO_TEMPLATE(
.idata_some_extra_sig_length ( s1_odata),
.ival ( s1_oval),
);*/
sub2 isub2 (/*AUTOINST*/
// Outputs
.oval (oval[COLS-1:0]),
.odata (odata/*[COLS-1:0][1:0]*/),
// Inputs
.clk (clk),
.rstb (rstb),
.ival ( s1_oval), // Templated
.idata_some_extra_sig_length( s1_odata)); // Templated
genvar column;
/* sub1 AUTO_TEMPLATE(
.i.* ( @"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
.o.* ( s1_@"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
);*/
/* sub3 AUTO_TEMPLATE(
.i.* ( @"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
.o.* ( s3_@"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
);*/
generate for(column=0;column<4;column++) begin : COLUMN
sub1 isub1(/*AUTOINST*/
// Outputs
.oval ( s1_oval[column] ), // Templated
.odata ( s1_odata[column] /* [1:0] */), // Templated
// Inputs
.clk (clk),
.rstb (rstb),
.ival ( ival[column] ), // Templated
.idata_some_extra_sig_length( idata_some_extra_sig_length[column] /* [1:0] */), // Templated
.isig1 ( isig1[column] /* [7:0] */), // Templated
.isig2 ( isig2[column] /* [6:0] */), // Templated
.isig3 ( isig3[column] /* [5:0] */)); // Templated
sub3 isub3(/*AUTOINST*/
// Outputs
.oval ( s3_oval[column] ), // Templated
.odata ( s3_odata[column] /* [1:0] */), // Templated
// Inputs
.clk (clk),
.rstb (rstb),
.ival ( ival[column] ), // Templated
.idata_some_extra_sig_length( idata_some_extra_sig_length[column] /* [1:0] */)); // Templated
end endgenerate
endmodule // top
module sub1
( input logic clk,
input logic rstb,
input logic ival,
input logic [1:0] idata_some_extra_sig_length,
input logic [7:0] isig1,
input logic [6:0] isig2,
input logic [5:0] isig3,
output logic oval,
output logic [1:0] odata
);
endmodule // sub
module sub3
( input logic clk,
input logic rstb,
input logic ival,
input logic [1:0] idata_some_extra_sig_length,
output logic oval,
output logic [1:0] odata
);
endmodule // sub
module sub2
#(parameter COLS = 4
)
( input logic clk,
input logic rstb,
input logic [COLS-1:0] ival,
input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
output logic [COLS-1:0] oval,
output logic [COLS-1:0] [1:0] odata
);
endmodule // sub
// Local Variables:
// verilog-typedef-regexp:"\\(^t_\\)\\|\\(^node$\\)\\|\\(_s$\\)\\|\\(_t$\\)"
// verilog-library-directories:("." )
// verilog-library-extensions:(".v" ".sv" ".h" ".vr" ".vm")
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_crawford_array.v 0000664 0000000 0000000 00000005171 13022141775 0024400 0 ustar 00root root 0000000 0000000 `define AUTO_NBR_A_INST 2
module autoinst_crawford_array(/*AUTOARG*/
// Outputs
a_valid, a_data,
// Inputs
a_ready, clk, rst_n
);
// a interface
output [`AUTO_NBR_A_INST*1-1:0] a_valid;
output [`AUTO_NBR_A_INST*8-1:0] a_data;
input [`AUTO_NBR_A_INST*1-1:0] a_ready;
// clock interface
input clk;
input rst_n;
/*AUTOWIRE*/
// non-arrayed example
autoinst_crawford_array_a auto_a_0
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
autoinst_crawford_array_a auto_a_1
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
// Arrayed instances
// AUTOINST does not work for this one :-(
// Note it is tricky because I want clk and rst_n to fanout to both instances,
// but I want the valid signals to be discreatly tied to each submodule.
//autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
// (/*XXXAUTOINST*/
// // Outputs
// .a_valid (a_valid[1:0]),
// .a_data (a_data[15:0]),
// // Inputs
// .a_ready (a_ready[1:0]),
// .clk (clk),
// .rst_n (rst_n));
autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
autoinst_crawford_array_a #(.a(a),b) par [`AUTO_NBR_A_INST-1:0]
(/*AUTOINST*/
// Outputs
.a_valid (a_valid),
.a_data (a_data[7:0]),
// Inputs
.a_ready (a_ready),
.clk (clk),
.rst_n (rst_n));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_crawford_array_a.v 0000664 0000000 0000000 00000001756 13022141775 0024705 0 ustar 00root root 0000000 0000000 `define auto_trq #1 // clock to q delay
`define auto_tcq #1 // reset to q delay
module autoinst_crawford_array_a(/*AUTOARG*/
// Outputs
a_valid, a_data,
// Inputs
a_ready, clk, rst_n
);
// a interface
output a_valid;
output [7:0] a_data;
input a_ready;
// clock interface
input clk;
input rst_n;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] a_data;
reg a_valid;
// End of automatics
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
a_valid <= `auto_trq 0;
a_data <= `auto_trq 0;
end
else begin
if(a_ready) begin
a_valid <= `auto_tcq 1;
a_data <= `auto_tcq 8'hcc;
end
end
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_dedefine.v 0000664 0000000 0000000 00000001653 13022141775 0023137 0 ustar 00root root 0000000 0000000 `define foo 6
`define bar 0
module autoinst_dedefine;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [3:1] fourwide; // From sub of bar.v
output onewide; // From sub of bar.v
output [5:0] varwide; // From sub of bar.v
// End of automatics
/*AUTOWIRE*/
/* bar AUTO_TEMPLATE (
.\(.*\) (@"(concat vl-name (verilog-symbol-detick-text vl-bits))"),
); */
bar sub
(/*AUTOINST*/
// Outputs
.onewide (onewide), // Templated
.fourwide (fourwide[3:1]), // Templated
.varwide (varwide[6-1:0])); // Templated
endmodule
module bar;
output onewide;
output [3:1] fourwide;
output [`foo-1:`bar] varwide;
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_ding.v 0000664 0000000 0000000 00000006506 13022141775 0022317 0 ustar 00root root 0000000 0000000 module AA(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
input wire clock,
input wire reset,
input wire test_enable,
input wire afe_ctrl,
input wire cpu_wr,
input wire [4:0] cpu_addr,
input wire [7:0] cpu_wdata,
output wire [7:0] core_data,
output wire core_code_error,
output wire core_code_idle,
output wire [7:0] cpu_rdata
);
endmodule
module BB(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
input wire clock,
input wire reset,
input wire test_enable,
input wire core_code_idle,
input wire core_code_error,
input wire [7:0] core_data,
input wire [8:0] mbist_done,
input wire [8:0] mbist_fail,
output wire mbist_rst,
output reg mbist_test
);
endmodule
module TOP(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input afe_ctrl, // To AA_U of AA.v
input clock, // To AA_U of AA.v, ...
input [4:0] cpu_addr, // To AA_U of AA.v
input [7:0] cpu_wdata, // To AA_U of AA.v
input cpu_wr, // To AA_U of AA.v
input [8:0] mbist_done, // To BB_U of BB.v
input [8:0] mbist_fail, // To BB_U of BB.v
input reset, // To AA_U of AA.v, ...
input test_enable, // To AA_U of AA.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [7:0] cpu_rdata, // From AA_U of AA.v
output mbist_rst, // From BB_U of BB.v
output mbist_test // From BB_U of BB.v
// End of automatics
);
AA AA_U(/*AUTOINST*/
// Outputs
.core_data (core_data[7:0]),
.core_code_error (core_code_error),
.core_code_idle (core_code_idle),
.cpu_rdata (cpu_rdata[7:0]),
// Inputs
.clock (clock),
.reset (reset),
.test_enable (test_enable),
.afe_ctrl (afe_ctrl),
.cpu_wr (cpu_wr),
.cpu_addr (cpu_addr[4:0]),
.cpu_wdata (cpu_wdata[7:0]));
BB BB_U(/*AUTOINST*/
// Outputs
.mbist_rst (mbist_rst),
.mbist_test (mbist_test),
// Inputs
.clock (clock),
.reset (reset),
.test_enable (test_enable),
.core_code_idle (core_code_idle),
.core_code_error (core_code_error),
.core_data (core_data[7:0]),
.mbist_done (mbist_done[8:0]),
.mbist_fail (mbist_fail[8:0]));
// Local Variables:
// verilog-library-directories:(".")
// End:
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_for_myers.v 0000664 0000000 0000000 00000003527 13022141775 0023403 0 ustar 00root root 0000000 0000000 module InstMod ( ins, outs );
output [INWIDTH-1:0] ins;
output [OUTWIDTH-1:0] outs;
endmodule
module test_top;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [n*INWIDTH +: INWIDTH] ins; // From instName of InstMod.v
wire [n*INWIDTH +: INWIDTH] ins2; // From instName2 of InstMod.v
wire [n*INWIDTH +: INWIDTH] ins3; // From instName3 of InstMod.v, ..., Couldn't Merge
wire [n*OUTWIDTH +: OUTWIDTH] outs; // From instName of InstMod.v
wire [n*OUTWIDTH +: OUTWIDTH] outs2; // From instName2 of InstMod.v
wire [4*OUTWIDTH-1 : 0] outs3; // From instName3 of InstMod.v, ..., Couldn't Merge
// End of automatics
genvar i;
generate
for (i=0; i<4; i=i+1) begin
/*AUTO_LISP(setq vh-n 4)*/
/* InstMod AUTO_TEMPLATE
(.ins (ins [n*INWIDTH +: INWIDTH]),
.outs (outs[n*OUTWIDTH +: OUTWIDTH])); */
InstMod instName (/*AUTOINST*/
// Outputs
.ins (ins [n*INWIDTH +: INWIDTH]), // Templated
.outs (outs[n*OUTWIDTH +: OUTWIDTH])); // Templated
InstMod instName2
(// Inputs
.ins (ins2 [n*INWIDTH +: INWIDTH]),
// Outputs
.outs (outs2[n*OUTWIDTH +: OUTWIDTH])
/*AUTOINST*/);
// This works but is ugly
InstMod instName3
(// Inputs
.ins (ins3 [n*INWIDTH +: INWIDTH]),
// Outputs
.outs (outs3[n*OUTWIDTH +: OUTWIDTH])
`ifdef NEVER
// Inouts
.ins (ins3 [4*INWIDTH-1 : 0]),
.outs (outs3[4*OUTWIDTH-1 : 0])
`endif
/*AUTOINST*/);
end
endgenerate
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_func.v 0000664 0000000 0000000 00000005517 13022141775 0022332 0 ustar 00root root 0000000 0000000 module autoinst_func;
/*AUTO_LISP(defun testfunc (sig bits) (let ((result "{"))
(setq result (concat result sig "[0" bits "]"))
(concat result "}")))*/
/* autoinst_wildcard_sub AUTO_TEMPLATE (
.sd0_adrs@ (myport@"(substring \\"\1\\" 0 1)"),
.\(.*\) (@"(testfunc vl-name vl-bits)"),
); */
autoinst_wildcard_sub sub0
(/*AUTOINST*/
// Inouts
.sd0_adrs0 (myport0), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs1 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs10 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs11 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs2 (myport2), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs3 (myport3), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs4 (myport4), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs5 (myport5), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs6 (myport6), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs7 (myport7), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs8 (myport8), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_adrs9 (myport9), // Templated LHS: ^sd0_adrs\([0-9]+\)$
.sd0_ba0 ({sd0_ba0[0]}), // Templated LHS: ^\(.*\)$
.sd0_ba1 ({sd0_ba1[0]}), // Templated LHS: ^\(.*\)$
.sd0_clk ({sd0_clk[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm0_l ({sd0_dqm0_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm1_l ({sd0_dqm1_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm2_l ({sd0_dqm2_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm3_l ({sd0_dqm3_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm4_l ({sd0_dqm4_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm5_l ({sd0_dqm5_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm6_l ({sd0_dqm6_l[0]}), // Templated LHS: ^\(.*\)$
.sd0_dqm7_l ({sd0_dqm7_l[0]}), // Templated LHS: ^\(.*\)$
.sd_ras_ ({sd_ras_[0]})); // Templated LHS: ^\(.*\)$
endmodule
// Local Variables:
// verilog-auto-inst-template-numbers: lhs
// verilog-auto-inst-sort: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_gate.v 0000664 0000000 0000000 00000002031 13022141775 0022303 0 ustar 00root root 0000000 0000000 //bug284
module wrapper
(
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [1:0] bout, // From mybuf of buf
output [31:0] o, // From u_or of or
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [1:0] bin, // To mybuf of buf
input [31:0] i0, // To u_or of or
input [31:0] i1, // To u_or of or
input [31:0] i2, // To u_or of or
input [31:0] i3 // To u_or of or
// End of automatics
);
//--------------------------------------------------------------------------
// Note input/output comments aren't needed, and multiple signals
// per line are ok
or u_or [31:0]
(o[31:0], i0[31:0], i1[31:0], i2[31:0],
// Inputs,
i3[31:0]
/*AUTOINST*/);
// bug676
buf # 1 mybuf[1:0]
(bout[1:0],
// Inputs,
bin[1:0]
/*AUTOINST*/);
//--------------------------------------------------------------------------
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_genvar.v 0000664 0000000 0000000 00000004035 13022141775 0022653 0 ustar 00root root 0000000 0000000 module AA(
input wire clock,
input wire reset,
input wire test_enable,
input wire afe_ctrl,
input wire cpu_wr,
input wire [4:0] cpu_addr,
input wire [7:0] cpu_wdata,
output wire [7:0] core_data,
output wire core_code_error,
output wire core_code_idle,
output wire [7:0] cpu_rdata
);
endmodule
module TOP(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input afe_ctrl, // To AA_U of AA.v
input clock, // To AA_U of AA.v
input [4:0] cpu_addr, // To AA_U of AA.v
input [7:0] cpu_wdata, // To AA_U of AA.v
input cpu_wr, // To AA_U of AA.v
input reset, // To AA_U of AA.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output core_code_error, // From AA_U of AA.v
output core_code_idle, // From AA_U of AA.v
output [7:0] core_data, // From AA_U of AA.v
output [7:0] cpu_rdata // From AA_U of AA.v
// End of automatics
);
genvar x;
AA AA_U(
// Inputs
.test_enable (x),
/*AUTOINST*/
// Outputs
.core_data (core_data[7:0]),
.core_code_error (core_code_error),
.core_code_idle (core_code_idle),
.cpu_rdata (cpu_rdata[7:0]),
// Inputs
.clock (clock),
.reset (reset),
.afe_ctrl (afe_ctrl),
.cpu_wr (cpu_wr),
.cpu_addr (cpu_addr[4:0]),
.cpu_wdata (cpu_wdata[7:0]));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_iface270_sub.v 0000664 0000000 0000000 00000000356 13022141775 0023544 0 ustar 00root root 0000000 0000000 // See http://www.veripool.org/issues/show/270
interface autoinst_iface270_sub;
logic a;
logic b;
modport master_mp(input a, output b);
modport slave_mp(output a, input b);
modport monitor (input a, input b);
endinterface
verilog-mode-20161124.fd230e6/tests_ok/autoinst_iface270_top.v 0000664 0000000 0000000 00000000466 13022141775 0023557 0 ustar 00root root 0000000 0000000 // See http://www.veripool.org/issues/show/270
module top;
/*AUTOWIRE*/
autoinst_iface270_sub inst_if (/*AUTOINST*/);
ifio sub (/*AUTOINST*/
// Interfaces
.inst_if (inst_if));
endmodule
module ifio
(autoinst_iface270_sub inst_if);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_iface270_top_bug429.v 0000664 0000000 0000000 00000000576 13022141775 0024655 0 ustar 00root root 0000000 0000000 // See http://www.veripool.org/issues/show/429
module top;
/*AUTOWIRE*/
autoinst_iface270_sub inst_if (/*AUTOINST*/);
ifio sub (/*AUTOINST*/
// Interfaces
.inst_if (inst_if));
endmodule
module ifio
(autoinst_iface270_sub inst_if);
endmodule
// Local Variables:
// verilog-auto-inst-interfaced-ports: nil
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_ifdef_fredrickson_200503_sub.v 0000664 0000000 0000000 00000000344 13022141775 0026520 0 ustar 00root root 0000000 0000000 module autoinst_ifdef_fredrickson_200503_sub
(input a,
`ifdef TEST
input c,
output wire d,
`endif
output wire b
);
assign b = a;
`ifdef TEST
assign d = c;
`endif
endmodule // define_sub
verilog-mode-20161124.fd230e6/tests_ok/autoinst_ifdef_fredrickson_200503_top.v 0000664 0000000 0000000 00000000546 13022141775 0026535 0 ustar 00root root 0000000 0000000 module autoinst_ifdef_fredrickson_200503_top();
autoinst_ifdef_fredrickson_200503_sub sub
(/*AUTOINST*/
// Outputs
.d (d),
.b (b),
// Inputs
.a (a),
.c (c));
endmodule // define_top
verilog-mode-20161124.fd230e6/tests_ok/autoinst_import.v 0000664 0000000 0000000 00000001570 13022141775 0022704 0 ustar 00root root 0000000 0000000 //bug709
module InstModule
(input clk,
svi.master svi_modport,
svi svi_nomodport);
endmodule // InstModule
module InstModule1 import mdp_pkg::*;
(input clk,
svi.master svi_modport,
svi svi_nomodport);
endmodule
module top;
InstModule instName
(/*AUTOINST*/
// Interfaces
.svi_modport (svi_modport.master),
.svi_nomodport (svi_nomodport),
// Inputs
.clk (clk));
InstModule1 instName1
(/*AUTOINST*/
// Interfaces
.svi_modport (svi_modport.master),
.svi_nomodport (svi_nomodport),
// Inputs
.clk (clk));
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v" ".sv")
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_instname_all.v 0000664 0000000 0000000 00000001136 13022141775 0024036 0 ustar 00root root 0000000 0000000 module ex;
/* autoinst_paramover_sub AUTO_TEMPLATE (
.\(.*\)(@"vl-cell-name"_\1),
);*/
autoinst_paramover_sub u_a0(/*AUTOINST*/
// Inouts
.a (u_a0_a), // Templated
.b (u_a0_b)); // Templated
autoinst_paramover_sub u_a1(/*AUTOINST*/
// Inouts
.a (u_a1_a), // Templated
.b (u_a1_b)); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_instname_carlh.v 0000664 0000000 0000000 00000001214 13022141775 0024354 0 ustar 00root root 0000000 0000000 module ex;
/* autoinst_paramover_sub AUTO_TEMPLATE (
.a(@"vl-cell-name"_in[]),
.b(@"(substring inst 2)"_out[]),
);*/
autoinst_paramover_sub u_a0(/*AUTOINST*/
// Inouts
.a (u_a0_in[bitsa:0]), // Templated
.b (a0_out[bitsb:0])); // Templated
autoinst_paramover_sub u_a1(/*AUTOINST*/
// Inouts
.a (u_a1_in[bitsa:0]), // Templated
.b (a1_out[bitsb:0])); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface.v 0000664 0000000 0000000 00000003337 13022141775 0023335 0 ustar 00root root 0000000 0000000 // See bug75
module autoinst_interface
(/*AUTOINOUTMODULE("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output logic [7:0] count,
input logic clk,
input logic reset,
input logic start,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module autoinst_interface
(/*AUTOINOUTCOMP("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output logic clk,
output logic reset,
output logic start,
input logic [7:0] count,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [7:0] count; // From submod0 of autoinst_interface_sub.v
// End of automatics
my_svi my_svi_noport_upper_decl ();
autoinst_interface_sub submod0 (/*AUTOINST*/
// Interfaces
.my_svi_port (my_svi_port.master),
.my_svi_noport (my_svi_noport),
.my_svi_noport_upper_decl(my_svi_noport_upper_decl),
// Outputs
.count (count[7:0]),
// Inputs
.clk (clk),
.reset (reset),
.start (start));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface_bug320.v 0000664 0000000 0000000 00000000331 13022141775 0024406 0 ustar 00root root 0000000 0000000 // See bug320
interface intf1;
logic a;
logic b;
modport mp1 (input a, output b);
endinterface
interface intf2 (intf1.mp1 c);
logic e;
endinterface
module top;
intf1 c(.*);
intf2 f(.*);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface_star.v 0000664 0000000 0000000 00000001746 13022141775 0024370 0 ustar 00root root 0000000 0000000 // See bug75
module autoinst_interface
(/*AUTOINOUTMODULE("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output [7:0] count,
input clk,
input reset,
input start,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module autoinst_interface
(/*AUTOINOUTCOMP("autoinst_interface_sub")*/
// Beginning of automatic in/out/inouts (from specific module)
output clk,
output reset,
output start,
input [7:0] count,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
// End of automatics
);
endmodule
module top;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] count; // From submod0 of autoinst_interface_sub.v
// End of automatics
autoinst_interface_sub submod0 (.*);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface_sub.v 0000664 0000000 0000000 00000000712 13022141775 0024200 0 ustar 00root root 0000000 0000000 interface my_svi;
logic enable;
logic error;
logic [7:0] count2;
modport master (
input enable,
output error,
output count2);
endinterface
module autoinst_interface_sub
(input wire clk,
input wire reset,
input wire start,
output reg [7:0] count,
my_svi.master my_svi_port,
my_svi my_svi_noport,
my_svi my_svi_noport_upper_decl
);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_johnson.v 0000664 0000000 0000000 00000002576 13022141775 0023057 0 ustar 00root root 0000000 0000000 module bfm (/*AUTOARG*/
// Inputs
name
);
input [8*5:1] name ;
endmodule
module tb;
// -------------------------------------------------------------------------
/*AUTOOUTPUT*/
// -------------------------------------------------------------------------
/*AUTOINPUT*/
// -------------------------------------------------------------------------
/*AUTOWIRE*/
// -------------------------------------------------------------------------
/* AUTO_CONSTANT ( "name0" "name1" "name2" ) */
// -------------------------------------------------------------------------
/* bfm AUTO_TEMPLATE (
// Inputs
.name ("name@"));
*/
// -------------------------------------------------------------------------
bfm bmf0 (/*AUTOINST*/
// Inputs
.name ("name0")); // Templated
// -------------------------------------------------------------------------
bfm bmf1 (/*AUTOINST*/
// Inputs
.name ("name1")); // Templated
// -------------------------------------------------------------------------
bfm bmf2 (/*AUTOINST*/
// Inputs
.name ("name2")); // Templated
// -------------------------------------------------------------------------
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_lopaz.v 0000664 0000000 0000000 00000005413 13022141775 0022517 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOARG*/);
wire [42:0] bscan_data; // boundary scan stitch
parameter bscan_count = 0;
assign bscan_data[0] = bscan_in;
/*
* Emacs template to auto instaniate MD[31:0] pads
*/
/*
autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@]),
.pin_in({SDRAM_DQ_in[@],SDRAM_DQ_in[@]}),
.pin_out(SDRAM_DQ_out[@]),
.pin_outen(SDRAM_DQ_outen),
.sdrmode(SDRAM_single_rate),
.hw_enb(SDRAM_upper_word_enb),
.ff_rptr(SDRAM_ddr_inff_sel),
.ff_wptr(ddr_inff_enbH),
.clk(data_strobeH),
.bscan_so(bscan_data[@ + 1]),
.bscan_si(bscan_data[@]),
.bscan_shift(BScanShift),
.bscan_clock(BScanClock),
.bscan_mode(BScanMode),
.bscan_update(BScanUpdate),
.bscan_outen(SDRAM_DQ_bscan_outen),
);
*/
autoinst_lopaz_srpad MD31_pad (/*AUTOINST*/
// Outputs
.pin_in ({SDRAM_DQ_in[31],SDRAM_DQ_in[31]}), // Templated
// Inouts
.pin (MD[31]), // Templated
// Inputs
.clk (data_strobeH), // Templated
.pin_out (SDRAM_DQ_out[31]), // Templated
.pin_outen (SDRAM_DQ_outen)); // Templated
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 1)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inouts
.pin (MD[1]), // Templated
// Inputs
.clk (clk),
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 2)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inouts
.pin (MD[2]), // Templated
// Inputs
.clk (clk),
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_lopaz_srpad.v 0000664 0000000 0000000 00000000754 13022141775 0023713 0 ustar 00root root 0000000 0000000 module autoinst_lopaz_srpad (/*AUTOARG*/
// Outputs
pin_in,
// Inouts
pin,
// Inputs
clk, pin_out, pin_outen
);
parameter w = 1;
input clk;
inout [w-1:0] pin;
output [2*w-1:0] pin_in;
input [w-1:0] pin_out;
input pin_outen;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_ma_io_prefix.v 0000664 0000000 0000000 00000005760 13022141775 0024040 0 ustar 00root root 0000000 0000000 // From: "Ma, Zhenqiang"
module test (
// Ports for module A
input i_A_outsidei,
output o_A_outsideo,
// Ports for module B
input i_B_outsidei,
output o_B_outsideo );
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire A_internal; // From u0 of moduleA.v
wire B_internal; // From u1 of moduleB.v
// End of automatics
//-----------------------------------------------------------------------------
// instantiate module A
//-----------------------------------------------------------------------------
/* moduleA AUTO_TEMPLATE (
.[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
); */
moduleA u0(
/*AUTOINST*/
// Outputs
.o_A_outsideo (o_A_outsideo), // Templated
.o_A_internal (A_internal), // Templated
// Inputs
.i_A_outsidei (i_A_outsidei), // Templated
.i_B_internal (B_internal)); // Templated
//-----------------------------------------------------------------------------
// instantiate module B
//-----------------------------------------------------------------------------
/* moduleB AUTO_TEMPLATE (
.[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
); */
moduleB u1(
/*AUTOINST*/
// Outputs
.o_B_outsideo (o_B_outsideo), // Templated
.o_B_internal (B_internal), // Templated
// Inputs
.i_B_outsidei (i_B_outsidei), // Templated
.i_A_internal (A_internal)); // Templated
endmodule
module moduleA (
input i_A_outsidei,
output o_A_outsideo,
input i_B_internal,
output o_A_internal
);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire o_A_internal = 1'h0;
wire o_A_outsideo = 1'h0;
// End of automatics
endmodule
module moduleB (
input i_B_outsidei,
output o_B_outsideo,
input i_A_internal,
output o_B_internal
);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire o_B_internal = 1'h0;
wire o_B_outsideo = 1'h0;
// End of automatics
endmodule
/*
Local Variables:
eval:
(defun vl-prefix-i-o (basename)
(cond ((assoc (concat "i_" basename)
(verilog-decls-get-inputs moddecls))
"i_")
((assoc (concat "o_" basename)
(verilog-decls-get-outputs moddecls))
"o_")
((assoc (concat "t_" basename)
(verilog-decls-get-inouts moddecls))
"t_")
(t "")))
End:
*/
verilog-mode-20161124.fd230e6/tests_ok/autoinst_mccoy.v 0000664 0000000 0000000 00000001541 13022141775 0022502 0 ustar 00root root 0000000 0000000 module top
// no-connecting unused outputs of an interface and tying only inputs to gnd.
// Requested:
//
// /* xx AUTO_TEMPLATE (
//.TWI_\(.*\) @"(vl-dir (input)" ({@"vl-width"{1'b0}}),
//.TWI_\(.*\) @"(vl-dir (output)" (),
//);
// */
/* xx AUTO_TEMPLATE (
.TWI_\(.*\) (@"(if (equal vl-dir \\"output\\") \\"\\" (concat vl-width \\"'b0\\"))"),
);
*/
xx XX (/*AUTOINST*/
// Outputs
.TWI_qb (), // Templated
// Inputs
.clk (clk),
.TWI_ia (1'b0), // Templated
.TWI_iw (16'b0)); // Templated
endmodule
module xx
(input clk,
input TWI_ia,
input [15:0] TWI_iw,
output TWI_qb);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_moddefine.v 0000664 0000000 0000000 00000002600 13022141775 0023317 0 ustar 00root root 0000000 0000000 // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008-2008 by Wilson Snyder.
module autoinst_moddefine (/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire q; // From `SUBNAME_B of `SUBMOD_A.v, ...
// End of automatics
`define SUBMOD_A submod_mod
`define SUBNAME_B subname_b
`SUBMOD_A `SUBNAME_B
(/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a));
`SUBMOD_UNDEFED subundefed
(/*AUTOINST*/
// Outputs
.q (q));
submod_decl_from_def subundefed
(/*AUTOINST*/
// Outputs
.q (q));
endmodule
module submod_mod (/*AUTOARG*/
// Outputs
q,
// Inputs
a
);
input a;
output q;
endmodule
module SUBMOD_UNDEFED (/*AUTOARG*/
// Outputs
q
);
output q;
endmodule
`define SUBMOD_DECL submod_decl_from_def
module `SUBMOD_DECL (/*AUTOARG*/
// Outputs
q
);
output q;
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_modport_param.v 0000664 0000000 0000000 00000001531 13022141775 0024233 0 ustar 00root root 0000000 0000000 //bug565
module InstModule
(svi.master svi_modport,
input clk,
svi svi_nomodport);
endmodule
module InstModule1 #
(parameter TCQ = 100)
(svi.master svi_modport,
input clk,
svi svi_nomodport);
endmodule
module top;
InstModule instName
(/*AUTOINST*/
// Interfaces
.svi_modport (svi_modport.master),
.svi_nomodport (svi_nomodport),
// Inputs
.clk (clk));
InstModule1 instName1
(/*AUTOINST*/
// Interfaces
.svi_modport (svi_modport.master),
.svi_nomodport (svi_nomodport),
// Inputs
.clk (clk));
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v" ".sv")
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_mplist.sv 0000664 0000000 0000000 00000004025 13022141775 0023063 0 ustar 00root root 0000000 0000000
// Parent module
// Specifies modport for interfaces in header.
// Has child modules which do the same.
module autoinst_mplist
(
// --------------------------------------------------------------------------
// Port Declarations
// --------------------------------------------------------------------------
input clk,
input reset_n,
// Top-level interfaces
mbl_if.master msg_resp_if
);
mbl_if msg_req_if; // Some internal interface
// --------------------------------------------------------------------------
// Packages and Local Declarations
// --------------------------------------------------------------------------
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic mem_rd_req; // From child of autoinst_mplist_child.v
logic msg_busy; // From child of autoinst_mplist_child.v
// End of automatics
// --------------------------------------------------------------------------
// Module Body
// --------------------------------------------------------------------------
// For the module instance below, interface ports should be
// connected (per standard AUTOINST fashion) but *without*
// explicitly specifying the modport.
//
// VCS (and likely other Synopsys tools) don't expect to see a
// modport being "respecified" here.
autoinst_mplist_child child
(/*AUTOINST*/
// Interfaces
.msg_req_if (msg_req_if.slave),
.msg_resp_if (msg_resp_if),
// Outputs
.msg_busy (msg_busy),
.mem_rd_req (mem_rd_req),
// Inputs
.clk (clk),
.reset_n (reset_n),
.mem_rd_gnt (mem_rd_gnt));
endmodule
/*
Local Variables:
verilog-typedef-regexp:"_t$"
verilog-library-directories:(".")
verilog-library-extensions:(".sv")
End:
*/
verilog-mode-20161124.fd230e6/tests_ok/autoinst_mplist_child.sv 0000664 0000000 0000000 00000001526 13022141775 0024231 0 ustar 00root root 0000000 0000000 // Child module
// ... with interface modport specified in module header
module autoinst_mplist_child
(
// --------------------------------------------------------------------------
// Port Declarations
// --------------------------------------------------------------------------
input clk,
input reset_n,
// Yeah, let's have an interface
autoinst_mplist_mbl_if.slave msg_req_if,
autoinst_mplist_mbl_if.master msg_resp_if,
// There are likely other signals present, too
output logic msg_busy,
output logic mem_rd_req,
input mem_rd_gnt
);
// Really snazzy RTL follows...
endmodule
/*
Local Variables:
verilog-typedef-regexp:"_t$"
verilog-library-directories:(".")
verilog-library-extensions:(".sv")
End:
*/
verilog-mode-20161124.fd230e6/tests_ok/autoinst_mplist_mbl_if.sv 0000664 0000000 0000000 00000001151 13022141775 0024370 0 ustar 00root root 0000000 0000000 // Example interface definition with at least one modport.
interface autoinst_mplist_mbl_if ();
logic sof;
logic eof;
logic [31:0] data;
logic ready;
logic valid;
modport master(
output data,
output sof,
output eof,
output valid,
input ready
);
modport slave(
input data,
input sof,
input eof,
input valid,
output ready
);
endinterface
verilog-mode-20161124.fd230e6/tests_ok/autoinst_multidim.v 0000664 0000000 0000000 00000006245 13022141775 0023222 0 ustar 00root root 0000000 0000000 module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic sig1; // From u_x of x.v
logic [A-1:0] sig2; // From u_x of x.v
logic [A-1:0] [B-1:0] sig3; // From u_x of x.v
logic [A-1:0][B-1:0] [C-1:0] sig4; // From u_x of x.v
logic [A-1:0][B-1:0][C-1:0] [D-1:0] sig5; // From u_x of x.v
logic vsig1; // From u_x of x.v
logic vsig2 [W-1:0]; // From u_x of x.v
logic vsig3 [W-1:0][X-1:0]; // From u_x of x.v
logic vsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
logic vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
logic zsig1; // From u_x of x.v
logic [A-1:0] zsig2 [W-1:0]; // From u_x of x.v
logic [A-1:0] [B-1:0] zsig3 [W-1:0][X-1:0]; // From u_x of x.v
logic [A-1:0][B-1:0] [C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
logic [A-1:0][B-1:0][C-1:0] [D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
// End of automatics
x u_x (/*AUTOINST*/
// Outputs
.sig1 (sig1),
.sig2 (sig2[A-1:0]),
.sig3 (sig3/*[A-1:0][B-1:0]*/),
.sig4 (sig4/*[A-1:0][B-1:0][C-1:0]*/),
.sig5 (sig5/*[A-1:0][B-1:0][C-1:0][D-1:0]*/),
.vsig1 (vsig1),
.vsig2 (vsig2/*.[W-1:0]*/),
.vsig3 (vsig3/*.[W-1:0][X-1:0]*/),
.vsig4 (vsig4/*.[W-1:0][X-1:0][Y-1:0]*/),
.vsig5 (vsig5/*.[W-1:0][X-1:0][Y-1:0][Z-1:0]*/),
.zsig1 (zsig1),
.zsig2 (zsig2/*[A-1:0].[W-1:0]*/),
.zsig3 (zsig3/*[A-1:0][B-1:0].[W-1:0][X-1:0]*/),
.zsig4 (zsig4/*[A-1:0][B-1:0][C-1:0].[W-1:0][X-1:0][Y-1:0]*/),
.zsig5 (zsig5/*[A-1:0][B-1:0][C-1:0][D-1:0].[W-1:0][X-1:0][Y-1:0][Z-1:0]*/));
endmodule // top
module x;
output sig1;
output [A-1:0] sig2;
output [A-1:0][B-1:0] sig3;
output [A-1:0][B-1:0][C-1:0] sig4;
output [A-1:0][B-1:0][C-1:0][D-1:0] sig5;
output vsig1;
output vsig2 [W-1:0];
output vsig3 [W-1:0][X-1:0];
output vsig4 [W-1:0][X-1:0][Y-1:0];
output vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
output zsig1;
output [A-1:0] zsig2 [W-1:0];
output [A-1:0][B-1:0] zsig3 [W-1:0][X-1:0];
output [A-1:0][B-1:0][C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];
output [A-1:0][B-1:0][C-1:0][D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_multitemplate.v 0000664 0000000 0000000 00000002445 13022141775 0024262 0 ustar 00root root 0000000 0000000 // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
// Reported by Julian Gorfajn
module autoinst_multitemplate ();
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input Boo1; // To suba1 of SubA.v
input Boo2; // To suba2 of SubB.v
input Boo3; // To suba3 of SubC.v
input b; // To suba2 of SubB.v
input c; // To suba3 of SubC.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*
SubA AUTO_TEMPLATE
SubB AUTO_TEMPLATE
SubC AUTO_TEMPLATE (
.a (Boo@),
);*/
SubA suba1 (/*AUTOINST*/
// Inputs
.a (Boo1)); // Templated
SubB suba2 (/*AUTOINST*/
// Inputs
.a (Boo2), // Templated
.b (b));
SubC suba3 (/*AUTOINST*/
// Inputs
.a (Boo3), // Templated
.c (c));
endmodule
module SubA (input a);
endmodule
module SubB (input a,input b);
endmodule
module SubC (input a,input c );
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_name_bug245.v 0000664 0000000 0000000 00000011746 13022141775 0023410 0 ustar 00root root 0000000 0000000 module autoinst_name_bug245 (
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input \escaped*dot*named ; // To sub of Sub.v
input logic clk; // To sub of Sub.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2:0] a_NO; // From sub of Sub.v
output [1:0] bign2_dotnamed; // From sub of Sub.v
output c_dotnamed; // From sub of Sub.v
output d_NO; // From sub of Sub.v
output etmp_dotnamed; // From sub of Sub.v
output [3:0] f4_dotnamed; // From sub of Sub.v
// End of automatics
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*Sub AUTO_TEMPLATE (
.dtmp_NO (d_NO),
.etmp_dotnamed (etmp_dotnamed),
);*/
Sub sub (
.bign1_dotnamed,
// Outputs
.bign2_dotnamed,
/*AUTOINST*/
// Outputs
.a_NO (a_NO[2:0]),
.f4_dotnamed,
.c_dotnamed,
.dtmp_NO (d_NO), // Templated
.etmp_dotnamed, // Templated
// Inputs
.clk,
.\escaped*dot*named );
endmodule
module Sub
(
input logic clk,
output [2:0] a_NO,
output [3:0] f4_dotnamed,
output bign1_dotnamed,
output [1:0] bign2_dotnamed,
output c_dotnamed,
output dtmp_NO,
output etmp_dotnamed,
input \escaped*dot*named
);
endmodule
// Local Variables:
// verilog-auto-inst-dot-name: t
// verilog-auto-inst-vector: nil
// End:
module autoinst_name_bug245 (
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input \escaped*dot*named ; // To sub of Sub.v
input logic clk; // To sub of Sub.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2:0] a_NO; // From sub of Sub.v
output [1:0] bign2_dotnamed; // From sub of Sub.v
output c_dotnamed; // From sub of Sub.v
output d_NO; // From sub of Sub.v
output etmp_dotnamed; // From sub of Sub.v
output [3:0] f4_dotnamed; // From sub of Sub.v
// End of automatics
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*Sub AUTO_TEMPLATE (
.dtmp_NO (d_NO),
.etmp_dotnamed (etmp_dotnamed),
);*/
Sub sub (
.bign1_dotnamed,
// Outputs
.bign2_dotnamed,
/*AUTOINST*/
// Outputs
.a_NO (a_NO[2:0]),
.f4_dotnamed,
.c_dotnamed,
.dtmp_NO (d_NO), // Templated
.etmp_dotnamed, // Templated
// Inputs
.clk,
.\escaped*dot*named );
endmodule
module Sub
(
input logic clk,
output [2:0] a_NO,
output [3:0] f4_dotnamed,
output bign1_dotnamed,
output [1:0] bign2_dotnamed,
output c_dotnamed,
output dtmp_NO,
output etmp_dotnamed,
input \escaped*dot*named
);
endmodule
// Local Variables:
// verilog-auto-inst-dot-name: t
// verilog-auto-inst-vector: nil
// End:
module autoinst_name_bug245 (
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input \escaped*dot*named ; // To sub of Sub.v
input logic clk; // To sub of Sub.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2:0] a_NO; // From sub of Sub.v
output [1:0] bign2_dotnamed; // From sub of Sub.v
output c_dotnamed; // From sub of Sub.v
output d_NO; // From sub of Sub.v
output etmp_dotnamed; // From sub of Sub.v
output [3:0] f4_dotnamed; // From sub of Sub.v
// End of automatics
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*Sub AUTO_TEMPLATE (
.dtmp_NO (d_NO),
.etmp_dotnamed (etmp_dotnamed),
);*/
Sub sub (
.bign1_dotnamed,
// Outputs
.bign2_dotnamed,
/*AUTOINST*/
// Outputs
.a_NO (a_NO[2:0]),
.f4_dotnamed,
.c_dotnamed,
.dtmp_NO (d_NO), // Templated
.etmp_dotnamed, // Templated
// Inputs
.clk,
.\escaped*dot*named );
endmodule
module Sub
(
input logic clk,
output [2:0] a_NO,
output [3:0] f4_dotnamed,
output bign1_dotnamed,
output [1:0] bign2_dotnamed,
output c_dotnamed,
output dtmp_NO,
output etmp_dotnamed,
input \escaped*dot*named
);
endmodule
// Local Variables:
// verilog-auto-inst-dot-name: t
// verilog-auto-inst-vector: nil
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_nicholl.v 0000664 0000000 0000000 00000002167 13022141775 0023025 0 ustar 00root root 0000000 0000000 module sub1 (/*AUTOARG*/
// Inputs
bus1
);
input [0:3] bus1;
endmodule
module sub2 (/*AUTOARG*/
// Inputs
bus2
);
input [0:3] bus2;
endmodule
module sub3 (/*AUTOARG*/
// Outputs
bus1, bus2
);
output [0:3] bus1;
output [4:7] bus2;
endmodule
module top (/*AUTOARG*/);
wire [4:7] bus2; // From sub3 of sub3.v
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [0:3] bus1; // From sub3 of sub3.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.bus1 (bus1[0:3]));
sub2 sub2 (/*AUTOINST*/
// Inputs
.bus2 (bus2[0:3]));
sub3 sub3 (/*AUTOINST*/
// Outputs
.bus1 (bus1[0:3]),
.bus2 (bus2));
endmodule
// Local Variables:
// verilog-auto-inst-vector:nil
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_overflow_bug250.v 0000664 0000000 0000000 00000075544 13022141775 0024335 0 ustar 00root root 0000000 0000000 module TEST_TOP (
);
/*TEST AUTO_TEMPLATE
(
.abcd_efgh_ijklmno_f02_out_c(abcdefg_f02_clroilouull[5]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_be_2(abcdefg_f10_eg2_ab_cdefghijklm[49]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fh_2(abcdefg_f08_eg0_ab_a_fghi[6]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ch(abcdefg_f09_eg1_ab_cdefghijklm[36]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ej_1(abcdefg_f10_eg2_ab_cdefghijklm[14]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ga_1(abcdefg_f10_eg2_ab_cdefghijklm[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fe(abcdefg_f09_eg1_ab_cdefghijklm[9]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bi_2(abcdefg_f08_eg0_ab_cdefghijklm[45]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_24_1(abcdefg_f09_eg1_ab_fghijklm[24]),
.abcd_efgh_ijklmno_f01_oilouull_o_0_1(abcdefg_f01_oilouull[0]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cc_2(abcdefg_f10_eg2_ab_cdefghijklm[41]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_e_2(abcdefg_f11_eg3_ab_cdefghijklm[59]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_54_1(abcdefg_f11_eg3_ab_fghijklm[54]),
.abcd_efgh_ijklmno_f03_oilouull_o_3_1(abcdefg_f03_oilouull[3]),
.abcd_efgh_ijklmno_f02_out_h_2(abcdefg_f02_a_zxdf[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_g_1(abcdefg_f11_eg3_ab_a_fghi[57]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_b_2(abcdefg_f08_eg0_ab_cdefghijklm[62]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_9_1(abcdefg_f11_eg3_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_di_1(abcdefg_f09_eg1_ab_a_fghi[25]),
.abcd_efgh_ijklmno_f00_out_h_2(abcdefg_f00_a_zxdf[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_cg_2(abcdefg_f11_eg3_ab_cdefghijklm[37]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_eh_2(abcdefg_f10_eg2_ab_a_fghi[16]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_di_1(abcdefg_f08_eg0_ab_cdefghijklm[25]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ec_2(abcdefg_f11_eg3_ab_cdefghijklm[21]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_d_1(abcdefg_f11_eg3_ab_a_fghi[60]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bh_1(abcdefg_f11_eg3_ab_a_fghi[46]),
.abcd_efgh_ijklmno_f00_out_f(abcdefg_f00_clroilouull[2]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_52_1(abcdefg_f11_eg3_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f02_out_g(abcdefg_f02_clroilouull[1]),
.abcd_efgh_ijklmno_f07_out_e(abcdefg_f07_clroilouull[3]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ff_2(abcdefg_f10_eg2_ab_a_fghi[8]),
.abcd_efgh_ijklmno_f04_out_h(abcdefg_f04_clroilouull[0]),
.abcd_efgh_ijklmno_f04_out_g_2(abcdefg_f04_a_zxdf[1]),
.abcd_efgh_ijklmno_f02_out_c_2(abcdefg_f02_a_zxdf[5]),
.abcd_efgh_ijklmno_f04_out_a_3(abcdefg_f04_a_zxdf[7]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fa_1(abcdefg_f08_eg0_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ed_2(abcdefg_f08_eg0_ab_a_fghi[20]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ea_2(abcdefg_f10_eg2_ab_a_fghi[23]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_c_2(abcdefg_f10_eg2_ab_cdefghijklm[61]),
.abcd_efgh_ijklmno_f03_oilouull_o_0_1(abcdefg_f03_oilouull[0]),
.abcd_efgh_ijklmno_f00_out_e_2(abcdefg_f00_a_zxdf[3]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bg_3(abcdefg_f10_eg2_ab_a_fghi[47]),
.abcd_efgh_ijklmno_f05_oilouull_o_2_1(abcdefg_f05_oilouull[2]),
.abcd_efgh_ijklmno_f01_out_h_2(abcdefg_f01_a_zxdf[0]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_44_1(abcdefg_f10_eg2_ab_fghijklm[44]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_j_3(abcdefg_f08_eg0_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_39_1(abcdefg_f08_eg0_ab_fghijklm[39]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fj_2(abcdefg_f08_eg0_ab_a_fghi[4]),
.abcd_efgh_ijklmno_f05_out_h(abcdefg_f05_clroilouull[0]),
.abcd_efgh_ijklmno_f05_out_d_2(abcdefg_f05_a_zxdf[4]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_gb_2(abcdefg_f10_eg2_ab_a_fghi[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cb_3(abcdefg_f10_eg2_ab_a_fghi[42]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_52_1(abcdefg_f10_eg2_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_be_2(abcdefg_f11_eg3_ab_cdefghijklm[49]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_42_1(abcdefg_f11_eg3_ab_fghijklm[42]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ci_1(abcdefg_f11_eg3_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fh_1(abcdefg_f10_eg2_ab_cdefghijklm[6]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_24_1(abcdefg_f08_eg0_ab_fghijklm[24]),
.abcd_efgh_ijklmno_f02_out_g_2(abcdefg_f02_a_zxdf[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_d_2(abcdefg_f11_eg3_ab_cdefghijklm[60]),
.abcd_efgh_ijklmno_f06_out_d_2(abcdefg_f06_a_zxdf[4]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ea_1(abcdefg_f09_eg1_ab_a_fghi[23]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_dh_2(abcdefg_f11_eg3_ab_cdefghijklm[26]),
.abcd_efgh_ijklmno_f04_oilouull_o_7_2(abcdefg_f04_oilouull[7]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dh_1(abcdefg_f09_eg1_ab_a_fghi[26]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_18_1(abcdefg_f08_eg0_ab_fghijklm[18]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ba_2(abcdefg_f11_eg3_ab_cdefghijklm[53]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ce_1(abcdefg_f11_eg3_ab_a_fghi[39]),
.abcd_efgh_ijklmno_f03_oilouull_o_5_1(abcdefg_f03_oilouull[5]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ef_1(abcdefg_f09_eg1_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cj_2(abcdefg_f08_eg0_ab_cdefghijklm[34]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_j_2(abcdefg_f08_eg0_ab_cdefghijklm[54]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bh_3(abcdefg_f08_eg0_ab_a_fghi[46]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cb_1(abcdefg_f09_eg1_ab_a_fghi[42]),
.abcd_efgh_ijklmno_f01_oilouull_o_6_2(abcdefg_f01_oilouull[6]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ba_3(abcdefg_f10_eg2_ab_a_fghi[53]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_0_1(abcdefg_f11_eg3_ab_fghijklm[0]),
.abcd_efgh_ijklmno_f06_out_h_2(abcdefg_f06_a_zxdf[0]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_51_1(abcdefg_f08_eg0_ab_fghijklm[51]),
.abcd_efgh_ijklmno_f06_oilouull_o_4_1(abcdefg_f06_oilouull[4]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_10_1(abcdefg_f08_eg0_ab_fghijklm[10]),
.abcd_efgh_ijklmno_f01_oilouull_o_7_2(abcdefg_f01_oilouull[7]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_da_2(abcdefg_f11_eg3_ab_cdefghijklm[33]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_e_1(abcdefg_f09_eg1_ab_a_fghi[59]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_22_1(abcdefg_f08_eg0_ab_fghijklm[22]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_db_2(abcdefg_f11_eg3_ab_cdefghijklm[32]),
.abcd_efgh_ijklmno_f01_oilouull_o_2_1(abcdefg_f01_oilouull[2]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ci_3(abcdefg_f08_eg0_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f07_oilouull_o_6_2(abcdefg_f07_oilouull[6]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_62_1(abcdefg_f11_eg3_ab_fghijklm[62]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_34_1(abcdefg_f10_eg2_ab_fghijklm[34]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_9_1(abcdefg_f10_eg2_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_13_1(abcdefg_f10_eg2_ab_fghijklm[13]),
.abcd_efgh_ijklmno_f05_oilouull_o_7_2(abcdefg_f05_oilouull[7]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ch_1(abcdefg_f11_eg3_ab_a_fghi[36]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fd_1(abcdefg_f10_eg2_ab_cdefghijklm[10]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fc_2(abcdefg_f10_eg2_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ei_1(abcdefg_f09_eg1_ab_a_fghi[15]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_37_1(abcdefg_f08_eg0_ab_fghijklm[37]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_gb(abcdefg_f09_eg1_ab_cdefghijklm[2]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_7_1(abcdefg_f10_eg2_ab_fghijklm[7]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_dg_2(abcdefg_f11_eg3_ab_cdefghijklm[27]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ce(abcdefg_f09_eg1_ab_cdefghijklm[39]),
.abcd_efgh_ijklmno_f07_out_d_2(abcdefg_f07_a_zxdf[4]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cd_2(abcdefg_f08_eg0_ab_cdefghijklm[40]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_57_1(abcdefg_f10_eg2_ab_fghijklm[57]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_63_1(abcdefg_f10_eg2_ab_fghijklm[63]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_j_1(abcdefg_f09_eg1_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f00_out_a(abcdefg_f00_clroilouull[7]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_46_1(abcdefg_f09_eg1_ab_fghijklm[46]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_39_1(abcdefg_f10_eg2_ab_fghijklm[39]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_28_1(abcdefg_f08_eg0_ab_fghijklm[28]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_20_1(abcdefg_f08_eg0_ab_fghijklm[20]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_51_1(abcdefg_f11_eg3_ab_fghijklm[51]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ci_1(abcdefg_f09_eg1_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f04_out_h_2(abcdefg_f04_a_zxdf[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_bd(abcdefg_f09_eg1_ab_cdefghijklm[50]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dg_1(abcdefg_f10_eg2_ab_cdefghijklm[27]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_23_1(abcdefg_f09_eg1_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_1_2(abcdefg_f09_eg1_ab_fghijklm[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bc_2(abcdefg_f08_eg0_ab_cdefghijklm[51]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bc_3(abcdefg_f10_eg2_ab_a_fghi[51]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_62_1(abcdefg_f08_eg0_ab_fghijklm[62]),
.abcd_efgh_ijklmno_f01_out_g_2(abcdefg_f01_a_zxdf[1]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_23_1(abcdefg_f11_eg3_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f03_out_e_2(abcdefg_f03_a_zxdf[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_b_1(abcdefg_f09_eg1_ab_a_fghi[62]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eh(abcdefg_f09_eg1_ab_cdefghijklm[16]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dh_1(abcdefg_f10_eg2_ab_cdefghijklm[26]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_34_1(abcdefg_f09_eg1_ab_fghijklm[34]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_gc_1(abcdefg_f10_eg2_ab_cdefghijklm[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cg_2(abcdefg_f08_eg0_ab_cdefghijklm[37]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_13_1(abcdefg_f11_eg3_ab_fghijklm[13]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_2_1(abcdefg_f08_eg0_ab_fghijklm[2]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fb(abcdefg_f09_eg1_ab_cdefghijklm[12]),
.abcd_efgh_ijklmno_f00_oilouull_o_6_2(abcdefg_f00_oilouull[6]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_h_3(abcdefg_f08_eg0_ab_a_fghi[56]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_38_1(abcdefg_f09_eg1_ab_fghijklm[38]),
.abcd_efgh_ijklmno_f00_out_c(abcdefg_f00_clroilouull[5]),
.abcd_efgh_ijklmno_f06_out_a_3(abcdefg_f06_a_zxdf[7]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_60_1(abcdefg_f09_eg1_ab_fghijklm[60]),
.abcd_efgh_ijklmno_f06_oilouull_o_2_1(abcdefg_f06_oilouull[2]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_8_1(abcdefg_f09_eg1_ab_fghijklm[8]),
.abcd_efgh_ijklmno_f03_out_f(abcdefg_f03_clroilouull[2]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dj_1(abcdefg_f08_eg0_ab_cdefghijklm[24]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bg_2(abcdefg_f08_eg0_ab_cdefghijklm[47]),
.abcd_efgh_ijklmno_f01_oilouull_o_4_1(abcdefg_f01_oilouull[4]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ef_2(abcdefg_f10_eg2_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f01_out_a_3(abcdefg_f01_a_zxdf[7]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_12_1(abcdefg_f08_eg0_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f07_out_c_2(abcdefg_f07_a_zxdf[5]),
.abcd_efgh_ijklmno_f00_out_e(abcdefg_f00_clroilouull[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ca_1(abcdefg_f09_eg1_ab_a_fghi[43]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_eg_2(abcdefg_f08_eg0_ab_a_fghi[17]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_be_1(abcdefg_f11_eg3_ab_a_fghi[49]),
.abcd_efgh_ijklmno_f06_out_d(abcdefg_f06_clroilouull[4]),
.abcd_efgh_ijklmno_f00_out_g(abcdefg_f00_clroilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_b(abcdefg_f09_eg1_ab_cdefghijklm[62]),
.abcd_efgh_ijklmno_f00_out_f_2(abcdefg_f00_a_zxdf[2]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_gc_1(abcdefg_f09_eg1_ab_a_fghi[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ca_1(abcdefg_f11_eg3_ab_a_fghi[43]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ea(abcdefg_f09_eg1_ab_cdefghijklm[23]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_12_1(abcdefg_f10_eg2_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gd_2(abcdefg_f11_eg3_ab_cdefghijklm[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_i_1(abcdefg_f09_eg1_ab_a_fghi[55]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_e_2(abcdefg_f08_eg0_ab_cdefghijklm[59]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ff(abcdefg_f09_eg1_ab_cdefghijklm[8]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_17_1(abcdefg_f11_eg3_ab_fghijklm[17]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_be_3(abcdefg_f10_eg2_ab_a_fghi[49]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_20_1(abcdefg_f11_eg3_ab_fghijklm[20]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bc_1(abcdefg_f11_eg3_ab_a_fghi[51]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_43_1(abcdefg_f09_eg1_ab_fghijklm[43]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_54_1(abcdefg_f09_eg1_ab_fghijklm[54]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_be_2(abcdefg_f08_eg0_ab_cdefghijklm[49]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_36_1(abcdefg_f10_eg2_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f05_out_h_2(abcdefg_f05_a_zxdf[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cc(abcdefg_f09_eg1_ab_cdefghijklm[41]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_3_1(abcdefg_f11_eg3_ab_fghijklm[3]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ff_1(abcdefg_f11_eg3_ab_a_fghi[8]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_19_2(abcdefg_f11_eg3_ab_fghijklm[19]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bi_1(abcdefg_f11_eg3_ab_a_fghi[45]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_49_1(abcdefg_f08_eg0_ab_fghijklm[49]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ee_1(abcdefg_f10_eg2_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_29_1(abcdefg_f08_eg0_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_29_1(abcdefg_f09_eg1_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ed(abcdefg_f09_eg1_ab_cdefghijklm[20]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_de(abcdefg_f09_eg1_ab_cdefghijklm[29]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dg_2(abcdefg_f10_eg2_ab_a_fghi[27]),
.abcd_efgh_ijklmno_f04_oilouull_o_2_1(abcdefg_f04_oilouull[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_eb_2(abcdefg_f10_eg2_ab_a_fghi[22]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ea_2(abcdefg_f11_eg3_ab_cdefghijklm[23]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fc_1(abcdefg_f10_eg2_ab_cdefghijklm[11]),
.abcd_efgh_ijklmno_f06_out_g(abcdefg_f06_clroilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_61_1(abcdefg_f09_eg1_ab_fghijklm[61]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ee_2(abcdefg_f10_eg2_ab_a_fghi[19]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_47_1(abcdefg_f11_eg3_ab_fghijklm[47]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_36_1(abcdefg_f08_eg0_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f07_oilouull_o_0_1(abcdefg_f07_oilouull[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_j_1(abcdefg_f11_eg3_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_52_1(abcdefg_f08_eg0_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gd_1(abcdefg_f11_eg3_ab_a_fghi[0]),
.abcd_efgh_ijklmno_f07_out_h_2(abcdefg_f07_a_zxdf[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cg_1(abcdefg_f09_eg1_ab_a_fghi[37]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_8_1(abcdefg_f10_eg2_ab_fghijklm[8]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fh_1(abcdefg_f11_eg3_ab_a_fghi[6]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_52_1(abcdefg_f09_eg1_ab_fghijklm[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ci_2(abcdefg_f11_eg3_ab_cdefghijklm[35]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_15_1(abcdefg_f10_eg2_ab_fghijklm[15]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_df(abcdefg_f09_eg1_ab_cdefghijklm[28]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ee(abcdefg_f09_eg1_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bd_1(abcdefg_f11_eg3_ab_a_fghi[50]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fe_1(abcdefg_f11_eg3_ab_a_fghi[9]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_di_2(abcdefg_f08_eg0_ab_a_fghi[25]),
.abcd_efgh_ijklmno_f00_out_d(abcdefg_f00_clroilouull[4]),
.abcd_efgh_ijklmno_f07_oilouull_o_5_1(abcdefg_f07_oilouull[5]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_41_1(abcdefg_f09_eg1_ab_fghijklm[41]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cf_2(abcdefg_f08_eg0_ab_cdefghijklm[38]),
.abcd_efgh_ijklmno_f05_out_b_3(abcdefg_f05_a_zxdf[6]),
.abcd_efgh_ijklmno_f03_oilouull_o_1_1(abcdefg_f03_oilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dg_1(abcdefg_f09_eg1_ab_a_fghi[27]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eg(abcdefg_f09_eg1_ab_cdefghijklm[17]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ce_1(abcdefg_f09_eg1_ab_a_fghi[39]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fi_2(abcdefg_f11_eg3_ab_cdefghijklm[5]),
.abcd_efgh_ijklmno_f05_out_g(abcdefg_f05_clroilouull[1]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bj_2(abcdefg_f10_eg2_ab_cdefghijklm[44]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_db(abcdefg_f09_eg1_ab_cdefghijklm[32]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_g_1(abcdefg_f09_eg1_ab_a_fghi[57]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bf_2(abcdefg_f08_eg0_ab_cdefghijklm[48]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bh_2(abcdefg_f08_eg0_ab_cdefghijklm[46]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_23_1(abcdefg_f10_eg2_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_61_1(abcdefg_f10_eg2_ab_fghijklm[61]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_db_1(abcdefg_f09_eg1_ab_a_fghi[32]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_f(abcdefg_f09_eg1_ab_cdefghijklm[58]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_57_1(abcdefg_f09_eg1_ab_fghijklm[57]),
.abcd_efgh_ijklmno_f01_oilouull_o_1_1(abcdefg_f01_oilouull[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_eh_2(abcdefg_f08_eg0_ab_a_fghi[16]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_41_1(abcdefg_f11_eg3_ab_fghijklm[41]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_c_2(abcdefg_f08_eg0_ab_cdefghijklm[61]),
.abcd_efgh_ijklmno_f06_out_e(abcdefg_f06_clroilouull[3]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ej_1(abcdefg_f11_eg3_ab_a_fghi[14]),
.abcd_efgh_ijklmno_f02_oilouull_o_1_1(abcdefg_f02_oilouull[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bd_2(abcdefg_f11_eg3_ab_cdefghijklm[50]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_6_1(abcdefg_f08_eg0_ab_fghijklm[6]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ee_1(abcdefg_f09_eg1_ab_a_fghi[19]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fc_2(abcdefg_f11_eg3_ab_cdefghijklm[11]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bd_3(abcdefg_f10_eg2_ab_a_fghi[50]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_df_1(abcdefg_f08_eg0_ab_cdefghijklm[28]),
.abcd_efgh_ijklmno_f03_out_a(abcdefg_f03_clroilouull[7]),
.abcd_efgh_ijklmno_f02_oilouull_o_0_1(abcdefg_f02_oilouull[0]),
.abcd_efgh_ijklmno_f00_out_g_2(abcdefg_f00_a_zxdf[1]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_43_1(abcdefg_f08_eg0_ab_fghijklm[43]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_59_1(abcdefg_f08_eg0_ab_fghijklm[59]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ff_1(abcdefg_f09_eg1_ab_a_fghi[8]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bh_2(abcdefg_f10_eg2_ab_cdefghijklm[46]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_0_1(abcdefg_f09_eg1_ab_fghijklm[0]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ec_2(abcdefg_f08_eg0_ab_a_fghi[21]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_33_1(abcdefg_f09_eg1_ab_fghijklm[33]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fh_1(abcdefg_f09_eg1_ab_a_fghi[6]),
.abcd_efgh_ijklmno_f02_oilouull_o_4_1(abcdefg_f02_oilouull[4]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_31_1(abcdefg_f10_eg2_ab_fghijklm[31]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fa_1(abcdefg_f10_eg2_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f05_out_f(abcdefg_f05_clroilouull[2]),
.abcd_efgh_ijklmno_f04_out_e_2(abcdefg_f04_a_zxdf[3]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dd_1(abcdefg_f09_eg1_ab_a_fghi[30]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_12_1(abcdefg_f11_eg3_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_bf_1(abcdefg_f09_eg1_ab_a_fghi[48]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_23_1(abcdefg_f08_eg0_ab_fghijklm[23]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dj_2(abcdefg_f08_eg0_ab_a_fghi[24]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ci_3(abcdefg_f10_eg2_ab_a_fghi[35]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_17_1(abcdefg_f08_eg0_ab_fghijklm[17]),
.abcd_efgh_ijklmno_f02_out_f_2(abcdefg_f02_a_zxdf[2]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bb_1(abcdefg_f11_eg3_ab_a_fghi[52]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_cc_1(abcdefg_f11_eg3_ab_a_fghi[41]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_f_1(abcdefg_f11_eg3_ab_a_fghi[58]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fi(abcdefg_f09_eg1_ab_cdefghijklm[5]),
.abcd_efgh_ijklmno_f03_out_h(abcdefg_f03_clroilouull[0]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_e_1(abcdefg_f11_eg3_ab_a_fghi[59]),
.abcd_efgh_ijklmno_f01_out_b_3(abcdefg_f01_a_zxdf[6]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_55_1(abcdefg_f08_eg0_ab_fghijklm[55]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bj_3(abcdefg_f10_eg2_ab_a_fghi[44]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_d_2(abcdefg_f08_eg0_ab_cdefghijklm[60]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bi_3(abcdefg_f08_eg0_ab_a_fghi[45]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fg_1(abcdefg_f09_eg1_ab_a_fghi[7]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ej_2(abcdefg_f10_eg2_ab_a_fghi[14]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cb_2(abcdefg_f08_eg0_ab_cdefghijklm[42]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fi_1(abcdefg_f10_eg2_ab_cdefghijklm[5]),
.abcd_efgh_ijklmno_f01_out_c(abcdefg_f01_clroilouull[5]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fa_2(abcdefg_f11_eg3_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f07_out_b_3(abcdefg_f07_a_zxdf[6]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_2_1(abcdefg_f09_eg1_ab_fghijklm[2]),
.abcd_efgh_ijklmno_f07_oilouull_o_2_1(abcdefg_f07_oilouull[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ed_2(abcdefg_f10_eg2_ab_a_fghi[20]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_32_1(abcdefg_f08_eg0_ab_fghijklm[32]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_29_1(abcdefg_f10_eg2_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ef_1(abcdefg_f11_eg3_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_15_1(abcdefg_f09_eg1_ab_fghijklm[15]),
.abcd_efgh_ijklmno_f04_out_c_2(abcdefg_f04_a_zxdf[5]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cd(abcdefg_f09_eg1_ab_cdefghijklm[40]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_57_1(abcdefg_f08_eg0_ab_fghijklm[57]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ee_2(abcdefg_f11_eg3_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_3_1(abcdefg_f09_eg1_ab_fghijklm[3]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_20_1(abcdefg_f10_eg2_ab_fghijklm[20]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_16_1(abcdefg_f08_eg0_ab_fghijklm[16]),
.abcd_efgh_ijklmno_f06_oilouull_o_1_1(abcdefg_f06_oilouull[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cg(abcdefg_f09_eg1_ab_cdefghijklm[37]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cd_3(abcdefg_f10_eg2_ab_a_fghi[40]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_35_1(abcdefg_f10_eg2_ab_fghijklm[35]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_j_3(abcdefg_f10_eg2_ab_a_fghi[54]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dc_2(abcdefg_f10_eg2_ab_a_fghi[31]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_34_1(abcdefg_f08_eg0_ab_fghijklm[34]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bi_2(abcdefg_f10_eg2_ab_cdefghijklm[45]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_48_1(abcdefg_f09_eg1_ab_fghijklm[48]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_1_2(abcdefg_f10_eg2_ab_fghijklm[1]),
.abcd_efgh_ijklmno_f07_out_g(abcdefg_f07_clroilouull[1]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_c_2(abcdefg_f11_eg3_ab_cdefghijklm[61]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_24_1(abcdefg_f10_eg2_ab_fghijklm[24]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fj_2(abcdefg_f10_eg2_ab_a_fghi[4]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_bi_1(abcdefg_f09_eg1_ab_a_fghi[45]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_eb_2(abcdefg_f11_eg3_ab_cdefghijklm[22]),
.abcd_efgh_ijklmno_f00_oilouull_o_5_1(abcdefg_f00_oilouull[5]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_30_1(abcdefg_f08_eg0_ab_fghijklm[30]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_11_1(abcdefg_f11_eg3_ab_fghijklm[11]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_26_1(abcdefg_f11_eg3_ab_fghijklm[26]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_45_1(abcdefg_f08_eg0_ab_fghijklm[45]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_dj_1(abcdefg_f10_eg2_ab_cdefghijklm[24]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_gd_1(abcdefg_f10_eg2_ab_cdefghijklm[0]),
.abcd_efgh_ijklmno_f05_out_b(abcdefg_f05_clroilouull[6]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ef_2(abcdefg_f08_eg0_ab_a_fghi[18]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_dg(abcdefg_f09_eg1_ab_cdefghijklm[27]),
.abcd_efgh_ijklmno_f02_oilouull_o_6_2(abcdefg_f02_oilouull[6]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_39_1(abcdefg_f11_eg3_ab_fghijklm[39]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_bh_3(abcdefg_f10_eg2_ab_a_fghi[46]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fc_1(abcdefg_f08_eg0_ab_cdefghijklm[11]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fa(abcdefg_f09_eg1_ab_cdefghijklm[13]),
.abcd_efgh_ijklmno_f04_out_b_3(abcdefg_f04_a_zxdf[6]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_21_1(abcdefg_f08_eg0_ab_fghijklm[21]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_bc_3(abcdefg_f08_eg0_ab_a_fghi[51]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dd_1(abcdefg_f08_eg0_ab_cdefghijklm[30]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_fc_1(abcdefg_f09_eg1_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_22_1(abcdefg_f11_eg3_ab_fghijklm[22]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_14_1(abcdefg_f11_eg3_ab_fghijklm[14]),
.abcd_efgh_ijklmno_f02_out_d_2(abcdefg_f02_a_zxdf[4]),
.abcd_efgh_ijklmno_f06_out_h(abcdefg_f06_clroilouull[0]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_37_1(abcdefg_f09_eg1_ab_fghijklm[37]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eh_1(abcdefg_f09_eg1_ab_a_fghi[16]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_12_1(abcdefg_f09_eg1_ab_fghijklm[12]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_cd_1(abcdefg_f09_eg1_ab_a_fghi[40]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_60_1(abcdefg_f11_eg3_ab_fghijklm[60]),
.abcd_efgh_ijklmno_f03_out_f_2(abcdefg_f03_a_zxdf[2]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_43_1(abcdefg_f11_eg3_ab_fghijklm[43]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_dc_2(abcdefg_f08_eg0_ab_a_fghi[31]),
.abcd_efgh_ijklmno_f07_out_b(abcdefg_f07_clroilouull[6]),
.abcd_efgh_ijklmno_f03_out_b_3(abcdefg_f03_a_zxdf[6]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ea_1(abcdefg_f10_eg2_ab_cdefghijklm[23]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_eg_1(abcdefg_f08_eg0_ab_cdefghijklm[17]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_fc_2(abcdefg_f08_eg0_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_gc_1(abcdefg_f08_eg0_ab_cdefghijklm[1]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_da(abcdefg_f09_eg1_ab_cdefghijklm[33]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gb_2(abcdefg_f11_eg3_ab_cdefghijklm[2]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_ba_2(abcdefg_f10_eg2_ab_cdefghijklm[53]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fb_2(abcdefg_f10_eg2_ab_a_fghi[12]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_ee_1(abcdefg_f11_eg3_ab_a_fghi[19]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_32_1(abcdefg_f09_eg1_ab_fghijklm[32]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gc_2(abcdefg_f11_eg3_ab_cdefghijklm[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ee_1(abcdefg_f08_eg0_ab_cdefghijklm[19]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_36_1(abcdefg_f09_eg1_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f02_out_a(abcdefg_f02_clroilouull[7]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_9_1(abcdefg_f08_eg0_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_5_1(abcdefg_f09_eg1_ab_fghijklm[5]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_bh_2(abcdefg_f11_eg3_ab_cdefghijklm[46]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_35_1(abcdefg_f09_eg1_ab_fghijklm[35]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ca(abcdefg_f09_eg1_ab_cdefghijklm[43]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_47_1(abcdefg_f08_eg0_ab_fghijklm[47]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_gc_1(abcdefg_f11_eg3_ab_a_fghi[1]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ba_2(abcdefg_f08_eg0_ab_cdefghijklm[53]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_44_1(abcdefg_f11_eg3_ab_fghijklm[44]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_9_1(abcdefg_f09_eg1_ab_fghijklm[9]),
.abcd_efgh_ijklmno_f00_oilouull_o_3_1(abcdefg_f00_oilouull[3]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fe_2(abcdefg_f11_eg3_ab_cdefghijklm[9]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_ec_1(abcdefg_f09_eg1_ab_a_fghi[21]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_de_2(abcdefg_f10_eg2_ab_a_fghi[29]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_29_1(abcdefg_f11_eg3_ab_fghijklm[29]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_g_3(abcdefg_f08_eg0_ab_a_fghi[57]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fi_2(abcdefg_f10_eg2_ab_a_fghi[5]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_27_1(abcdefg_f08_eg0_ab_fghijklm[27]),
.abcd_efgh_ijklmno_f11_eg3_ge_out_fc_1(abcdefg_f11_eg3_ab_a_fghi[11]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_42_1(abcdefg_f10_eg2_ab_fghijklm[42]),
.abcd_efgh_ijklmno_f04_oilouull_o_4_1(abcdefg_f04_oilouull[4]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_30_1(abcdefg_f09_eg1_ab_fghijklm[30]),
.abcd_efgh_ijklmno_f01_oilouull_o_3_1(abcdefg_f01_oilouull[3]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_fj_1(abcdefg_f10_eg2_ab_cdefghijklm[4]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_55_1(abcdefg_f11_eg3_ab_fghijklm[55]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_42_1(abcdefg_f08_eg0_ab_fghijklm[42]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_gd(abcdefg_f09_eg1_ab_cdefghijklm[0]),
.abcd_efgh_ijklmno_f09_eg1_ge_out_eg_1(abcdefg_f09_eg1_ab_a_fghi[17]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_8_1(abcdefg_f08_eg0_ab_fghijklm[8]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_50_1(abcdefg_f11_eg3_ab_fghijklm[50]),
.abcd_efgh_ijklmno_f06_out_f_2(abcdefg_f06_a_zxdf[2]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_26_1(abcdefg_f09_eg1_ab_fghijklm[26]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_30_1(abcdefg_f11_eg3_ab_fghijklm[30]),
.abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_55_1(abcdefg_f10_eg2_ab_fghijklm[55]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_df_2(abcdefg_f08_eg0_ab_a_fghi[28]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_28_1(abcdefg_f09_eg1_ab_fghijklm[28]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_22_1(abcdefg_f09_eg1_ab_fghijklm[22]),
.abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_45_1(abcdefg_f09_eg1_ab_fghijklm[45]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_46_1(abcdefg_f08_eg0_ab_fghijklm[46]),
.abcd_efgh_ijklmno_f01_out_f(abcdefg_f01_clroilouull[2]),
.abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_36_1(abcdefg_f11_eg3_ab_fghijklm[36]),
.abcd_efgh_ijklmno_f05_out_f_2(abcdefg_f05_a_zxdf[2]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_ch_2(abcdefg_f08_eg0_ab_cdefghijklm[36]),
.abcd_efgh_ijklmno_f10_eg2_ge_out_cj_3(abcdefg_f10_eg2_ab_a_fghi[34]),
.abcd_efgh_ijklmno_f04_oilouull_o_3_1(abcdefg_f04_oilouull[3]),
.abcd_efgh_ijklmno_f08_eg0_ge_out_cd_3(abcdefg_f08_eg0_ab_a_fghi[40]),
.abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_56_1(abcdefg_f08_eg0_ab_fghijklm[56]),
);*/
TEST TEST (/*AUTOINST*/);
endmodule
module TEST (/*AUTOARG*/);
parameter NO = 6456;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_param_2d.v 0000664 0000000 0000000 00000012407 13022141775 0023060 0 ustar 00root root 0000000 0000000 // bug981
module a(
parameter AUM=80;
parameter BUM=70;
parameter VUM=1;
parameter V2=2;
input my_data_z;
input my_data_v[VUM];
input my_data_vv[VUM][V2];
input [AUM-1:0] my_data_av[VUM];
input [AUM-1:0][BUM-1:0] my_data_ab;
input [AUM-1:0][BUM-1:0] my_data_abv[VUM];
input [XUM-1:0][YUM-1:0] my_data_xyz[ZUM];
input PARAMS0__t params0 [1:0];
input PARAMS1__t params1 [1:0];
);
endmodule
module top (/*AUTOARG*/
// Inputs
TEST1_params1, TEST1_params0, TEST1_my_data_z, TEST1_my_data_xyz, TEST1_my_data_vv,
TEST1_my_data_v, TEST1_my_data_av, TEST1_my_data_abv, TEST1_my_data_ab, TEST0_params1,
TEST0_params0, TEST0_my_data_z, TEST0_my_data_xyz, TEST0_my_data_vv, TEST0_my_data_v,
TEST0_my_data_av, TEST0_my_data_abv, TEST0_my_data_ab
)
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [TEST0_AUM-1:0] [TEST0_BUM-1:0] TEST0_my_data_ab;// To a_0 of a.v
input [TEST0_AUM-1:0] [TEST0_BUM-1:0] TEST0_my_data_abv [TEST0_VUM];// To a_0 of a.v
input [TEST0_AUM-1:0] TEST0_my_data_av [TEST0_VUM];// To a_0 of a.v
input TEST0_my_data_v [VUM]; // To a_0 of a.v
input TEST0_my_data_vv [VUM][V2];// To a_0 of a.v
input [XUM-1:0] [YUM-1:0] TEST0_my_data_xyz [ZUM];// To a_0 of a.v
input TEST0_my_data_z; // To a_0 of a.v
input PARAMS0__t TEST0_params0 [1:0]; // To a_0 of a.v
input PARAMS1__t TEST0_params1 [1:0]; // To a_0 of a.v
input [TEST1_AUM-1:0] [TEST1_BUM-1:0] TEST1_my_data_ab;// To a_1 of a.v
input [TEST1_AUM-1:0] [TEST1_BUM-1:0] TEST1_my_data_abv [TEST1_VUM];// To a_1 of a.v
input [TEST1_AUM-1:0] TEST1_my_data_av [TEST1_VUM];// To a_1 of a.v
input TEST1_my_data_v [VUM]; // To a_1 of a.v
input TEST1_my_data_vv [VUM][V2];// To a_1 of a.v
input [XUM-1:0] [YUM-1:0] TEST1_my_data_xyz [ZUM];// To a_1 of a.v
input TEST1_my_data_z; // To a_1 of a.v
input PARAMS0__t TEST1_params0 [1:0]; // To a_1 of a.v
input PARAMS1__t TEST1_params1 [1:0]; // To a_1 of a.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*
a AUTO_TEMPLATE
(
.\(.*\) (TEST@_\1[][]),
);
*/
a #(/*AUTOINSTPARAM*/
// Parameters
.AUM (TEST0_AUM), // Templated
.BUM (TEST0_BUM), // Templated
.VUM (TEST0_VUM), // Templated
.V2 (TEST0_V2)) // Templated
a_0 (/*AUTOINST*/
// Inputs
.my_data_z (TEST0_my_data_z), // Templated
.my_data_v (TEST0_my_data_v/*.[VUM]*/), // Templated
.my_data_vv (TEST0_my_data_vv/*.[VUM][V2]*/), // Templated
.my_data_av (TEST0_my_data_av/*[TEST0_AUM-1:0].[TEST0_VUM]*/), // Templated
.my_data_ab (TEST0_my_data_ab/*[TEST0_AUM-1:0][TEST0_BUM-1:0]*/), // Templated
.my_data_abv (TEST0_my_data_abv/*[TEST0_AUM-1:0][TEST0_BUM-1:0].[TEST0_VUM]*/), // Templated
.my_data_xyz (TEST0_my_data_xyz/*[XUM-1:0][YUM-1:0].[ZUM]*/), // Templated
.params0 (TEST0_params0/*.[1:0]*/), // Templated
.params1 (TEST0_params1/*.[1:0]*/)); // Templated
a #(/*AUTOINSTPARAM*/
// Parameters
.AUM (TEST1_AUM), // Templated
.BUM (TEST1_BUM), // Templated
.VUM (TEST1_VUM), // Templated
.V2 (TEST1_V2)) // Templated
a_1 (/*AUTOINST*/
// Inputs
.my_data_z (TEST1_my_data_z), // Templated
.my_data_v (TEST1_my_data_v/*.[VUM]*/), // Templated
.my_data_vv (TEST1_my_data_vv/*.[VUM][V2]*/), // Templated
.my_data_av (TEST1_my_data_av/*[TEST1_AUM-1:0].[TEST1_VUM]*/), // Templated
.my_data_ab (TEST1_my_data_ab/*[TEST1_AUM-1:0][TEST1_BUM-1:0]*/), // Templated
.my_data_abv (TEST1_my_data_abv/*[TEST1_AUM-1:0][TEST1_BUM-1:0].[TEST1_VUM]*/), // Templated
.my_data_xyz (TEST1_my_data_xyz/*[XUM-1:0][YUM-1:0].[ZUM]*/), // Templated
.params0 (TEST1_params0/*.[1:0]*/), // Templated
.params1 (TEST1_params1/*.[1:0]*/)); // Templated
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-typedef-regexp: "_t$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_param_cmt.v 0000664 0000000 0000000 00000000706 13022141775 0023335 0 ustar 00root root 0000000 0000000 module InstMod ( ins, outs );
output [INWIDTH-1:0] ins;
endmodule
module test (/*AUTOARG*/) ;
parameter foo=1;
/*
parameter foo=2;
*/
//bug647
/* InstMod AUTO_TEMPLATE
(.ins (a@"vh-foo")); */
InstMod instName (/*AUTOINST*/
// Outputs
.ins (a1)); // Templated
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_param_type.v 0000664 0000000 0000000 00000004136 13022141775 0023534 0 ustar 00root root 0000000 0000000
//bug1061
//typedef logic [7:0] foo_t;
module ptype
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input foo_t a, // To b0 of ptype_buf.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output foo_t y0, // From b0 of ptype_buf.v
output logic [7:0] y1, // From b1 of ptype_buf.v
output TYPE_T y2 // From b2 of ptype_buf.v
// End of automatics
);
ptype_buf #(.TYPE_T(foo_t)) b0
(// Outputs
.y (y0),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.TYPE_T(logic [7:0])) b1
(// Outputs
.y (y1),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.WIDTH(8)) b2
(// Outputs
.y (y2),
/*AUTOINST*/
// Inputs
.a (a));
endmodule
module ptype_buf
#(parameter WIDTH = 1,
parameter type TYPE_T = logic [WIDTH-1:0])
(output TYPE_T y,
input TYPE_T a);
assign y = a;
endmodule
///--------------
// Example in docs
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule
module ExampInst;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [9:0] i; // To instName of InstModule.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output upper_t o; // From instName of InstModule.v
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.i (i[9:0]));
endmodule
// Local Variables:
// verilog-typedef-regexp: "_[tT]$"
// verilog-auto-inst-param-value:t
// verilog-auto-inst-param-value-type:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover.v 0000664 0000000 0000000 00000001301 13022141775 0023356 0 ustar 00root root 0000000 0000000 module autoinst_paramover (/*AUTOARG*/
// Inouts
a, b
);
//======================================================================
// Inputs/Outputs
//======================================================================
parameter bitsa = 20;
parameter bitsb = 20;
inout [20:0] a; // SDRAM Channel 0 Row Address Strobe
inout [20:0] b; // SDRAM Channel 0 Row Address Strobe
autoinst_paramover_sub #(bitsa,bitsb ) mod
(/*AUTOINST*/
// Inouts
.a (a[bitsa:0]),
.b (b[bitsb:0]));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover_sub.v 0000664 0000000 0000000 00000001011 13022141775 0024225 0 ustar 00root root 0000000 0000000 module autoinst_paramover_sub (/*AUTOARG*/
// Inouts
a, b
);
//======================================================================
// Inputs/Outputs
//======================================================================
parameter bitsa;
parameter bitsb;
inout [bitsa:0] a; // SDRAM Channel 0 Row Address Strobe
inout [bitsb:0] b; // SDRAM Channel 0 Row Address Strobe
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramvalue.v 0000664 0000000 0000000 00000003660 13022141775 0023531 0 ustar 00root root 0000000 0000000 module testmuxpv();
# (parameter WIDTH = 32)
(
input wire [2:0] /* synopsys enum cur_info */ sel,
input wire [WIDTH-1:0] a,
output reg [WIDTH-1:0] out
);
endmodule
module top_test();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [WIDTH-1:0] out; // From testmuxpv_boo of testmuxpv.v, ..., Couldn't Merge
// End of automatics
//======================================================================
/* testmuxpv AUTO_TEMPLATE (
) */
testmuxpv #(.IGNORE((1)),
.WIDTH( 16 ),
.IGNORE2(2))
testmuxpv_boo
(/*AUTOINST*/
// Outputs
.out (out[15:0]),
// Inputs
.sel (sel[2:0]),
.a (a[15:0]));
//======================================================================
testmuxpv #(.IGNORE((1)),
.WIDTH(WIDTH), // Make sure we don't recurse!
.IGNORE2(2))
testmuxpv_boo
(/*AUTOINST*/
// Outputs
.out (out[WIDTH-1:0]),
// Inputs
.sel (sel[2:0]),
.a (a[WIDTH-1:0]));
//======================================================================
// bug331: vl-width should correct when param values propagating
/* testmuxpv AUTO_TEMPLATE (
.a ({@"vl-width"{1'b0}}),
) */
testmuxpv #(.IGNORE((1)),
.WIDTH(16),
.IGNORE2(2))
testmuxpv_boo
(/*AUTOINST*/
// Outputs
.out (out[15:0]),
// Inputs
.sel (sel[2:0]),
.a ({16{1'b0}})); // Templated
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_podolsky.v 0000664 0000000 0000000 00000001100 13022141775 0023223 0 ustar 00root root 0000000 0000000 module io1_sub(
/*AUTOARG*/);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin_in(),
// Inputs
.pin_out (),
); */
autoinst_lopaz_srpad i_ctrl
(/*AUTOINST*/
// Outputs
.pin_in (), // Templated
// Inouts
.pin (pin[w-1:0]),
// Inputs
.clk (clk),
.pin_out (), // Templated
.pin_outen (pin_outen));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_precomment.v 0000664 0000000 0000000 00000003170 13022141775 0023541 0 ustar 00root root 0000000 0000000 module autoinst_precomment (
why,
/*AUTOARG*/
// Inputs
nnnot
);
input why;
input nnnot;
autoinst_wildcard_sub sub0
(
.sd_ras_ (foobar_ras_),
//.sd0_dqm7_l (dontdome),
/*AUTOINST*/
// Inouts
.sd0_dqm7_l (sd0_dqm7_l),
.sd0_dqm6_l (sd0_dqm6_l),
.sd0_dqm5_l (sd0_dqm5_l),
.sd0_dqm4_l (sd0_dqm4_l),
.sd0_dqm3_l (sd0_dqm3_l),
.sd0_dqm2_l (sd0_dqm2_l),
.sd0_dqm1_l (sd0_dqm1_l),
.sd0_dqm0_l (sd0_dqm0_l),
.sd0_ba1 (sd0_ba1),
.sd0_ba0 (sd0_ba0),
.sd0_adrs11 (sd0_adrs11),
.sd0_adrs10 (sd0_adrs10),
.sd0_adrs9 (sd0_adrs9),
.sd0_adrs8 (sd0_adrs8),
.sd0_adrs7 (sd0_adrs7),
.sd0_adrs6 (sd0_adrs6),
.sd0_adrs5 (sd0_adrs5),
.sd0_adrs4 (sd0_adrs4),
.sd0_adrs3 (sd0_adrs3),
.sd0_adrs2 (sd0_adrs2),
.sd0_adrs1 (sd0_adrs1),
.sd0_adrs0 (sd0_adrs0),
.sd0_clk (sd0_clk));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_rao.v 0000664 0000000 0000000 00000001277 13022141775 0022157 0 ustar 00root root 0000000 0000000 module temp2(/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [5:0] out; // From adc_3 of adc.v
// End of automatics
adc adc_3 (
// Outputs
.out (out[5:0]),
// Inputs
.Vi (Vi),
// Inputs
.evalClk (evalClk),
/*AUTOINST*/);
endmodule // temp
module adc(/*AUTOARG*/
// Outputs
out,
// Inputs
Vi, evalClk
);
output [5:0] out;
input Vi;
input evalClk;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v 0000664 0000000 0000000 00000011676 13022141775 0024050 0 ustar 00root root 0000000 0000000 module autoinst_wildcard;
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout [0] [9:0] SD_ADRS; // To/From sub0 of autoinst_wildcard_sub.v, ...
inout [0] [1:0] SD_ADRS1; // To/From sub0 of autoinst_wildcard_sub.v, ...
inout [0] [1:0] SD_BA; // To/From sub0 of autoinst_wildcard_sub.v, ...
inout [0] [7:0] SD_DQM_L; // To/From sub0 of autoinst_wildcard_sub.v, ...
inout sd0_clk; // To/From sub0 of autoinst_wildcard_sub.v, ...
inout [0] [9:0] sd_adrs; // To/From sub1 of autoinst_wildcard_sub.v, ...
inout [0] [1:0] sd_adrs1; // To/From sub1 of autoinst_wildcard_sub.v, ...
inout [0] [1:0] sd_ba; // To/From sub1 of autoinst_wildcard_sub.v, ...
inout [0] [7:0] sd_dqm_l; // To/From sub1 of autoinst_wildcard_sub.v, ...
inout sd_ras_; // To/From sub0 of autoinst_wildcard_sub.v, ...
// End of automatics
/* autoinst_wildcard_sub AUTO_TEMPLATE (
.sd\([0-9]\)_\(.*\)\([0-9]+\)\(.*\) (@"(uc \\"sd_\2\4[\1][\3]\\")"),
); */
/*AUTOOUTPUT*/
autoinst_wildcard_sub sub0
(/*AUTOINST*/
// Inouts
.sd_ras_ (sd_ras_),
.sd0_dqm7_l (SD_DQM_L[0][7]), // Templated
.sd0_dqm6_l (SD_DQM_L[0][6]), // Templated
.sd0_dqm5_l (SD_DQM_L[0][5]), // Templated
.sd0_dqm4_l (SD_DQM_L[0][4]), // Templated
.sd0_dqm3_l (SD_DQM_L[0][3]), // Templated
.sd0_dqm2_l (SD_DQM_L[0][2]), // Templated
.sd0_dqm1_l (SD_DQM_L[0][1]), // Templated
.sd0_dqm0_l (SD_DQM_L[0][0]), // Templated
.sd0_ba1 (SD_BA[0][1]), // Templated
.sd0_ba0 (SD_BA[0][0]), // Templated
.sd0_adrs11 (SD_ADRS1[0][1]), // Templated
.sd0_adrs10 (SD_ADRS1[0][0]), // Templated
.sd0_adrs9 (SD_ADRS[0][9]), // Templated
.sd0_adrs8 (SD_ADRS[0][8]), // Templated
.sd0_adrs7 (SD_ADRS[0][7]), // Templated
.sd0_adrs6 (SD_ADRS[0][6]), // Templated
.sd0_adrs5 (SD_ADRS[0][5]), // Templated
.sd0_adrs4 (SD_ADRS[0][4]), // Templated
.sd0_adrs3 (SD_ADRS[0][3]), // Templated
.sd0_adrs2 (SD_ADRS[0][2]), // Templated
.sd0_adrs1 (SD_ADRS[0][1]), // Templated
.sd0_adrs0 (SD_ADRS[0][0]), // Templated
.sd0_clk (sd0_clk));
/* autoinst_wildcard_sub AUTO_TEMPLATE (
.sd\([0-9]\)_\(.*\)\([0-9]+\)\(.*\) (sd_\2\4[\1][\3]),
); */
/*AUTOOUTPUT*/
autoinst_wildcard_sub sub1
(/*AUTOINST*/
// Inouts
.sd_ras_ (sd_ras_),
.sd0_dqm7_l (sd_dqm_l[0][7]), // Templated
.sd0_dqm6_l (sd_dqm_l[0][6]), // Templated
.sd0_dqm5_l (sd_dqm_l[0][5]), // Templated
.sd0_dqm4_l (sd_dqm_l[0][4]), // Templated
.sd0_dqm3_l (sd_dqm_l[0][3]), // Templated
.sd0_dqm2_l (sd_dqm_l[0][2]), // Templated
.sd0_dqm1_l (sd_dqm_l[0][1]), // Templated
.sd0_dqm0_l (sd_dqm_l[0][0]), // Templated
.sd0_ba1 (sd_ba[0][1]), // Templated
.sd0_ba0 (sd_ba[0][0]), // Templated
.sd0_adrs11 (sd_adrs1[0][1]), // Templated
.sd0_adrs10 (sd_adrs1[0][0]), // Templated
.sd0_adrs9 (sd_adrs[0][9]), // Templated
.sd0_adrs8 (sd_adrs[0][8]), // Templated
.sd0_adrs7 (sd_adrs[0][7]), // Templated
.sd0_adrs6 (sd_adrs[0][6]), // Templated
.sd0_adrs5 (sd_adrs[0][5]), // Templated
.sd0_adrs4 (sd_adrs[0][4]), // Templated
.sd0_adrs3 (sd_adrs[0][3]), // Templated
.sd0_adrs2 (sd_adrs[0][2]), // Templated
.sd0_adrs1 (sd_adrs[0][1]), // Templated
.sd0_adrs0 (sd_adrs[0][0]), // Templated
.sd0_clk (sd0_clk));
endmodule
// Local Variables:
// eval:(defun uc (x) (upcase x))
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_rogoff.v 0000664 0000000 0000000 00000004677 13022141775 0022667 0 ustar 00root root 0000000 0000000 module testmux();
# (parameter WIDTH = 32)
(
input wire [2:0] /* synopsys enum cur_info */ sel,
input wire [WIDTH-1:0] a,
output reg [WIDTH-1:0] out
);
endmodule
module top_test();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [WIDTH-1:0] boo_out_symbolic; // From testmux_boo of testmux.v
wire [WIDTH-1:0] boo_out_value; // From testmux_boo of testmux.v, ...
wire [WIDTH-1:0] defaultwidth_out_symbolic;// From testmux_defaultwidth of testmux.v
// End of automatics
/*AUTO_LISP(setq verilog-auto-inst-param-value nil)*/
/* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
.a (@_a_symbolic[]),
.out (@_out_symbolic[]),
);
*/
testmux #(.WIDTH( 16 )) testmux_boo
(/*AUTOINST*/
// Outputs
.out (boo_out_symbolic[WIDTH-1:0]), // Templated
// Inputs
.sel (sel[2:0]),
.a (boo_a_symbolic[WIDTH-1:0])); // Templated
testmux testmux_defaultwidth
(/*AUTOINST*/
// Outputs
.out (defaultwidth_out_symbolic[WIDTH-1:0]), // Templated
// Inputs
.sel (sel[2:0]),
.a (defaultwidth_a_symbolic[WIDTH-1:0])); // Templated
//======================================================================
/*AUTO_LISP(setq verilog-auto-inst-param-value t)*/
/* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
.a (@_a_value[]),
.out (@_out_value[]),
);
*/
testmux #(.IGNORE((1)),
.WIDTH( 16 ),
.IGNORE2(2))
testmux_boo
(/*AUTOINST*/
// Outputs
.out (boo_out_value[15:0]), // Templated
// Inputs
.sel (sel[2:0]),
.a (boo_a_value[15:0])); // Templated
//======================================================================
testmux #(.IGNORE((1)),
.WIDTH(WIDTH), // Make sure we don't recurse!
.IGNORE2(2))
testmux_boo
(/*AUTOINST*/
// Outputs
.out (boo_out_value[WIDTH-1:0]), // Templated
// Inputs
.sel (sel[2:0]),
.a (boo_a_value[WIDTH-1:0])); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_rons.v 0000664 0000000 0000000 00000001371 13022141775 0022352 0 ustar 00root root 0000000 0000000 module autoinst_rons;
dwrr dwrr_inst (/*AUTOINST*/
// Outputs
.dwell_count_out (dwell_count_out[6:0]),
.eligible_flag (eligible_flag[47:0]),
.dwrr_state (dwrr_state[5:0]),
// Inputs
.data_avail (data_avail[47:0]),
.cell_eof (cell_eof[47:0]));
endmodule
// module declaration
module dwrr (
//Inputs
input [47:0] data_avail,
input [47:0] cell_eof,
//Outputs
output reg [6:0] dwell_count_out,
output reg [47:0] eligible_flag,
output [5:0] dwrr_state );
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_signed.v 0000664 0000000 0000000 00000003114 13022141775 0022637 0 ustar 00root root 0000000 0000000 module autoinst_signed
(/*AUTOARG*/
// Outputs
another_output2, another_output, an_outputpre, an_output2
);
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
output signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
output signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
output [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
wire signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
wire signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
wire [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
// End of automatics
autoinst_signed_fubar u_fubar
(
// Outputs
.an_output (an_outputpre[1:0]),
.plover (plump),
/*AUTOINST*/
// Outputs
.another_output (another_output[1:0]),
// Inputs
.an_input (an_input[1:0]));
autoinst_signed_fubar2 u_fubar2
(
/*AUTOINST*/
// Outputs
.an_output2 (an_output2[1:0]),
.another_output2 (another_output2[1:0]),
// Inputs
.an_input2 (an_input2[1:0]));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_signed_fubar.v 0000664 0000000 0000000 00000000525 13022141775 0024021 0 ustar 00root root 0000000 0000000
module autoinst_signed_fubar
(
input signed [1:0] an_input,
output signed [1:0] an_output
output signed [1:0] another_output
);
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg signed [1:0] an_output;
reg signed [1:0] another_output;
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_signed_fubar2.v 0000664 0000000 0000000 00000000470 13022141775 0024102 0 ustar 00root root 0000000 0000000
module autoinst_signed_fubar2
(
input [1:0] an_input2,
output [1:0] an_output2
output [1:0] another_output2
);
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [1:0] an_output2;
reg [1:0] another_output2;
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_star.v 0000664 0000000 0000000 00000002336 13022141775 0022344 0 ustar 00root root 0000000 0000000 module io1_sub (/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [w-1:0] pin; // To/From MD31_pad of autoinst_lopaz_srpad.v
wire [2*w-1:0] pin_in; // From MD31_pad of autoinst_lopaz_srpad.v, ...
wire templated; // To/From MD31_pad of autoinst_lopaz_srpad.v
// End of automatics
autoinst_lopaz_srpad MD31_pad
(.*,
.foo (touch_this_not_my_pretty));
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
); */
autoinst_lopaz_srpad MD31_pad
(.*);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin (templated));
*/
autoinst_lopaz_srpad MD31_pad
(.*,
// Outputs
// Inouts
.pin (templated) // Templated
);
// And .name with auto inst
autoinst_lopaz_srpad MD31_pad22
(.pin,
.clk,
/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inputs
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
always @(posedge clk) begin
$display ("This .* shouldn't expand.\n");
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_sv_kulkarni.v 0000664 0000000 0000000 00000004271 13022141775 0023723 0 ustar 00root root 0000000 0000000 `timescale 1ns/100ps
// -----------------------------------------------------------------------------
// One-level up Hierarchical module
// -----------------------------------------------------------------------------
module a_h
// Verilog 2001 style
#(parameter M=5, N=3)
(
// Outputs
output [N-1:0] [M-1:0] a_o1 // From Ia of autoinst_sv_kulkarni_base.v
// End of automatics
// AUTOINPUT*/
);
/*AUTOWIRE*/
autoinst_sv_kulkarni_base
#(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ia
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/),
// Inputs
.a_i1 (a_i1/*[N-1:0][M-1:0]*/)); // <---- BUG?
endmodule
// -----------------------------------------------------------------------------
// Top-level module or Testbench
// -----------------------------------------------------------------------------
module top;
parameter M=4;
parameter N=2;
wire [N-1:0] a_o1;
logic [N-1:0][M-1:0] a_i1;
logic temp;
/*AUTOWIRE*/
// Workaround to fix multi-dimensional port problem
// a) Set "verilog-auto-inst-vector = nil"
// b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
a_h #(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ua_h
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/)); // <---- BUG?
// Stimulus
initial begin
a_i1 = { 4'h0, 4'h2 };
#5;
$display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
a_i1[1], a_i1[0], a_o1);
#5;
for (int i=0; i<1; i++) begin
for (int j=0; j
module autoinst_multitemplate ();
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input Boo2; // To suba2 of SubB.v
input Boo3; // To suba3 of SubB.v
input a; // To suba2 of SubB.v
input b; // To suba3 of SubB.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*
SubB AUTO_TEMPLATE (
.b (Boo@),
);*/
SubB suba2 (/*AUTOINST*/
// Inputs
.a (a),
.b (Boo2)); // Templated
/*
SubB AUTO_TEMPLATE (
.a (Boo@),
);*/
SubB suba3 (/*AUTOINST*/
// Inputs
.a (Boo3), // Templated
.b (b));
// Test harness doesn't support expected errors
// /*
// SubUnused AUTO_TEMPLATE (
// .subunused (Boo@),
// );*/
endmodule
module SubB (input a,input b);
endmodule
// Local Variables:
// verilog-auto-template-warn-unused: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_tennant.v 0000664 0000000 0000000 00000005705 13022141775 0023045 0 ustar 00root root 0000000 0000000 typedef logic [3:0][1:0] sometype_t;
module top
#(parameter X=4,
parameter Y=1)
(input clk,
input rstb,
/*AUTOINPUT("^x.*\|v.*")*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [X-1:0] xb, // To XX of xx.v, ...
// End of automatics
/*AUTOOUTPUT("^c.*\|k.*")*/
/*AUTOOUTPUT("^y.*")*/
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [X-1:0] cb, // To XX of xx.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output foobar, // From XX of xx.v
output [4:0] [2:0] foobar2 // From YY of yy.v
// End of automatics
);
xx (/*AUTOINSTPARAM*/
// Parameters
.X (X),
.Y (Y))
XX(/*AUTOINST*/
// Outputs
.st (st[1:0]),
.foobar (foobar),
// Inputs
.clk (clk),
.rstb (rstb),
.xc (xc/*[X-1:0][1:0]*/),
.xa (xa[X-1:0]),
.xb (xb[X-1:0]),
.cb (cb[X-1:0]),
.yb (yb[X*Y-1:0]));
yy (/*AUTOINSTPARAM*/
// Parameters
.X (X),
.Y (Y))
YY(/*AUTOINST*/
// Outputs
.xc (xc/*[X-1:0][1:0]*/),
.xa (xa[X-1:0]),
.yb (yb[X*Y-1:0]),
.foobar2 (foobar2/*[4:0][2:0]*/),
// Inputs
.clk (clk),
.rstb (rstb),
.xb (xb[X-1:0]),
.cb (cb[X-1:0]),
.st (st[1:0]));
endmodule // top
module xx
#(parameter X=4,
parameter Y=1)
(input clk,
input rstb,
input [X-1:0][1:0] xc,
input [X-1:0] xa,
input [X-1:0] xb,
input [X-1:0] cb,
output sometype_t [1:0] st,
input [X*Y-1:0] yb,
output foobar
);
endmodule // xx
module yy
#(parameter X=4,
parameter Y=1)
(input clk,
input rstb,
output [X-1:0][1:0] xc,
output [X-1:0] xa,
input [X-1:0] xb,
input [X-1:0] cb,
input sometype_t [1:0] st,
output [X*Y-1:0] yb,
output [4:0][2:0] foobar2
);
endmodule // xx
// Local Variables:
// verilog-typedef-regexp:"_t$"
// verilog-library-directories:("." )
// verilog-library-extensions:(".v" ".sv" ".h" ".vr" ".vm")
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_unsigned_bug302.v 0000664 0000000 0000000 00000001412 13022141775 0024263 0 ustar 00root root 0000000 0000000 module autoinst_unsigned_bug302;
Sub #(/*AUTOINSTPARAM*/
// Parameters
.No1 (No1),
.No2 (No2),
.No3 (No3/*.[No1:0][No2-1:0]*/)) u_Abc
(/*AUTOINST*/
// Inputs
.ck (ck),
.abc (abc/*[No1-1:0][31:0]*/));
endmodule
module Sub
#(
parameter No1 = 6,
parameter int unsigned No2 // Parameter no. 2
= pa_Abc::No2,
parameter bit No3 [No1:0][No2-1:0] // Parameter no. 3
= pa_Abc::No3
)
(
input logic ck,
input logic [No1-1:0][31:0] abc
input logic [No1-1:0][31:0] abc
);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_vertrees.v 0000664 0000000 0000000 00000016664 13022141775 0023243 0 ustar 00root root 0000000 0000000 module autoinst_vertrees
(/*AUTOARG*/
// Outputs
slv_b_put, slv_b_bit_st, slv_a_put, slv_a_bit_st, i2c_b_strobe, i2c_b_start, i2c_b_spc_stop,
i2c_b_spc_start, i2c_b_spc_sda_state, i2c_b_spc_scl_state, i2c_b_spc_scl_fall, i2c_b_slv_sda_out,
i2c_b_slv_scl_out, i2c_b_read, i2c_b_mst_data, i2c_a_strobe, i2c_a_start, i2c_a_spc_stop,
i2c_a_spc_start, i2c_a_spc_sda_state, i2c_a_spc_scl_state, i2c_a_spc_scl_fall, i2c_a_slv_sda_out,
i2c_a_slv_scl_out, i2c_a_read, i2c_a_mst_data,
// Inputs
test_mode, rst_ref, rpt_b_sda, rpt_b_hold, rpt_a_sda, rpt_a_hold, r_i2c_spc_scl_low,
i2c_b_slv_sda_in, i2c_b_slv_scl_in, i2c_b_slv_data, i2c_a_slv_sda_in, i2c_a_slv_scl_in,
i2c_a_slv_data, ck_ref
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input ck_ref; // To u_slv_a of autoinst_vertrees_slv.v, ...
input i2c_a_slv_data; // To u_slv_a of autoinst_vertrees_slv.v
input i2c_a_slv_scl_in; // To u_slv_a of autoinst_vertrees_slv.v
input i2c_a_slv_sda_in; // To u_slv_a of autoinst_vertrees_slv.v
input i2c_b_slv_data; // To u_slv_b of autoinst_vertrees_slv.v
input i2c_b_slv_scl_in; // To u_slv_b of autoinst_vertrees_slv.v
input i2c_b_slv_sda_in; // To u_slv_b of autoinst_vertrees_slv.v
input [4:0] r_i2c_spc_scl_low; // To u_slv_a of autoinst_vertrees_slv.v, ...
input rpt_a_hold; // To u_slv_a of autoinst_vertrees_slv.v
input rpt_a_sda; // To u_slv_a of autoinst_vertrees_slv.v
input rpt_b_hold; // To u_slv_b of autoinst_vertrees_slv.v
input rpt_b_sda; // To u_slv_b of autoinst_vertrees_slv.v
input rst_ref; // To u_slv_a of autoinst_vertrees_slv.v, ...
input test_mode; // To u_slv_a of autoinst_vertrees_slv.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output i2c_a_mst_data; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_read; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_slv_scl_out; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_slv_sda_out; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_spc_scl_fall; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_spc_scl_state; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_spc_sda_state; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_spc_start; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_spc_stop; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_start; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_a_strobe; // From u_slv_a of autoinst_vertrees_slv.v
output i2c_b_mst_data; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_read; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_slv_scl_out; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_slv_sda_out; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_spc_scl_fall; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_spc_scl_state; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_spc_sda_state; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_spc_start; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_spc_stop; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_start; // From u_slv_b of autoinst_vertrees_slv.v
output i2c_b_strobe; // From u_slv_b of autoinst_vertrees_slv.v
output slv_a_bit_st; // From u_slv_a of autoinst_vertrees_slv.v
output slv_a_put; // From u_slv_a of autoinst_vertrees_slv.v
output slv_b_bit_st; // From u_slv_b of autoinst_vertrees_slv.v
output slv_b_put; // From u_slv_b of autoinst_vertrees_slv.v
// End of automatics
/*AUTOWIRE*/
/*
autoinst_vertrees_slv AUTO_TEMPLATE "u_slv_\([a-z]\)"
(.i2c_\(.*\) (i2c_@_\1),
.slv_\(.*\) (slv_@_\1),
.rpt_\(.*\) (rpt_@_\1),
)
*/
autoinst_vertrees_slv u_slv_a
(/*AUTOINST*/
// Outputs
.i2c_mst_data (i2c_a_mst_data), // Templated
.i2c_read (i2c_a_read), // Templated
.i2c_slv_scl_out (i2c_a_slv_scl_out), // Templated
.i2c_slv_sda_out (i2c_a_slv_sda_out), // Templated
.i2c_spc_scl_state (i2c_a_spc_scl_state), // Templated
.i2c_start (i2c_a_start), // Templated
.i2c_strobe (i2c_a_strobe), // Templated
.slv_bit_st (slv_a_bit_st), // Templated
.slv_put (slv_a_put), // Templated
.i2c_spc_scl_fall (i2c_a_spc_scl_fall), // Templated
.i2c_spc_sda_state (i2c_a_spc_sda_state), // Templated
.i2c_spc_start (i2c_a_spc_start), // Templated
.i2c_spc_stop (i2c_a_spc_stop), // Templated
// Inputs
.ck_ref (ck_ref),
.i2c_slv_data (i2c_a_slv_data), // Templated
.i2c_slv_scl_in (i2c_a_slv_scl_in), // Templated
.i2c_slv_sda_in (i2c_a_slv_sda_in), // Templated
.r_i2c_spc_scl_low (r_i2c_spc_scl_low[4:0]),
.rpt_hold (rpt_a_hold), // Templated
.rpt_sda (rpt_a_sda), // Templated
.rst_ref (rst_ref),
.test_mode (test_mode));
autoinst_vertrees_slv u_slv_b
(/*AUTOINST*/
// Outputs
.i2c_mst_data (i2c_b_mst_data), // Templated
.i2c_read (i2c_b_read), // Templated
.i2c_slv_scl_out (i2c_b_slv_scl_out), // Templated
.i2c_slv_sda_out (i2c_b_slv_sda_out), // Templated
.i2c_spc_scl_state (i2c_b_spc_scl_state), // Templated
.i2c_start (i2c_b_start), // Templated
.i2c_strobe (i2c_b_strobe), // Templated
.slv_bit_st (slv_b_bit_st), // Templated
.slv_put (slv_b_put), // Templated
.i2c_spc_scl_fall (i2c_b_spc_scl_fall), // Templated
.i2c_spc_sda_state (i2c_b_spc_sda_state), // Templated
.i2c_spc_start (i2c_b_spc_start), // Templated
.i2c_spc_stop (i2c_b_spc_stop), // Templated
// Inputs
.ck_ref (ck_ref),
.i2c_slv_data (i2c_b_slv_data), // Templated
.i2c_slv_scl_in (i2c_b_slv_scl_in), // Templated
.i2c_slv_sda_in (i2c_b_slv_sda_in), // Templated
.r_i2c_spc_scl_low (r_i2c_spc_scl_low[4:0]),
.rpt_hold (rpt_b_hold), // Templated
.rpt_sda (rpt_b_sda), // Templated
.rst_ref (rst_ref),
.test_mode (test_mode));
endmodule // ddc
verilog-mode-20161124.fd230e6/tests_ok/autoinst_vertrees_slv.v 0000664 0000000 0000000 00000003462 13022141775 0024117 0 ustar 00root root 0000000 0000000
module autoinst_vertrees_slv
(/*AUTOARG*/
// Outputs
i2c_mst_data, i2c_read, i2c_slv_scl_out, i2c_slv_sda_out, i2c_spc_scl_state, i2c_start,
i2c_strobe, slv_bit_st, slv_put, i2c_spc_scl_fall, i2c_spc_sda_state, i2c_spc_start,
i2c_spc_stop,
// Inputs
ck_ref, i2c_slv_data, i2c_slv_scl_in, i2c_slv_sda_in, r_i2c_spc_scl_low, rpt_hold, rpt_sda,
rst_ref, test_mode
);
input ck_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
input [7:0] i2c_slv_data; // To u_misc of ddc_slv_misc.v
input i2c_slv_scl_in; // To u_spc of i2c_slv_pin_ctrl.v
input i2c_slv_sda_in; // To u_spc of i2c_slv_pin_ctrl.v
input [4:0] r_i2c_spc_scl_low; // To u_spc of i2c_slv_pin_ctrl.v
input rpt_hold; // To u_misc of ddc_slv_misc.v
input rpt_sda; // To u_misc of ddc_slv_misc.v
input rst_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
input test_mode; // To u_spc of i2c_slv_pin_ctrl.v
output [7:0] i2c_mst_data; // From u_misc of ddc_slv_misc.v
output i2c_read; // From u_misc of ddc_slv_misc.v
output i2c_slv_scl_out; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_slv_sda_out; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_scl_state; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_start; // From u_misc of ddc_slv_misc.v
output i2c_strobe; // From u_misc of ddc_slv_misc.v
output slv_bit_st; // From u_misc of ddc_slv_misc.v
output slv_put; // From u_misc of ddc_slv_misc.v
output i2c_spc_scl_fall; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_sda_state; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_start; // From u_spc of i2c_slv_pin_ctrl.v
output i2c_spc_stop; // From u_spc of i2c_slv_pin_ctrl.v
endmodule // ddc_slv
verilog-mode-20161124.fd230e6/tests_ok/autoinst_vkadamby.v 0000664 0000000 0000000 00000000542 13022141775 0023166 0 ustar 00root root 0000000 0000000 module autoinst_vkadamby ( /*AUTOARG*/);
child1 #(.lengthM2(100)) I34 (/*AUTOINST*/
// Inputs
.x (x));
endmodule
module child1 (/*AUTOARG*/
// Inputs
x
);
input x;
parameter lengthM2;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_width.v 0000664 0000000 0000000 00000001710 13022141775 0022505 0 ustar 00root root 0000000 0000000 module ex;
/* subwidth AUTO_TEMPLATE (
.bus1a(@"vl-width"'b0),
.bus1b(@"vl-width"'b0),
.bus4a(@"vl-width"'b0),
.bus4b(@"vl-width"'b0),
.busdef(@"vl-width"'b0),
);*/
subwidth u_a2(/*AUTOINST*/
// Outputs
.bus4a (4'b0), // Templated
.bus4b (4'b0), // Templated
.bus1a (1'b0), // Templated
.bus1b (1'b0), // Templated
.busdef ((1+(`defa)-(`defb))'b0)); // Templated
endmodule
module subwidth (/*AUTOARG*/
// Outputs
bus4a, bus4b, bus1a, bus1b, busdef
);
output [0:3] bus4a;
output [7:4] bus4b;
output bus1a;
output [0:0] bus1b;
output [`defa:`defb] busdef;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard.v 0000664 0000000 0000000 00000004615 13022141775 0023166 0 ustar 00root root 0000000 0000000 module autoinst_wildcard;
/*AUTOOUTPUT*/
// Newline between AUTO_TEMPLATE and ( gave a templated line number bug
/* autoinst_wildcard_sub AUTO_TEMPLATE
(
.sd0_clk (sd_clk),
.sd0_dqm\(.*\)_l (c@_sd_dqm_[\1]),
.sd0_ba\([0-9]+\) (c@_sd_ba[\1]),
.sd0_adrs@ (c@_sd_adrs[\1]),
.ics@ (c@_ics[\1]),
); */
/*AUTOOUTPUT*/
autoinst_wildcard_sub sub0
(/*AUTOINST*/
// Inouts
.sd_ras_ (sd_ras_),
.sd0_dqm7_l (c0_sd_dqm_[7]), // Templated 9
.sd0_dqm6_l (c0_sd_dqm_[6]), // Templated 9
.sd0_dqm5_l (c0_sd_dqm_[5]), // Templated 9
.sd0_dqm4_l (c0_sd_dqm_[4]), // Templated 9
.sd0_dqm3_l (c0_sd_dqm_[3]), // Templated 9
.sd0_dqm2_l (c0_sd_dqm_[2]), // Templated 9
.sd0_dqm1_l (c0_sd_dqm_[1]), // Templated 9
.sd0_dqm0_l (c0_sd_dqm_[0]), // Templated 9
.sd0_ba1 (c0_sd_ba[1]), // Templated 10
.sd0_ba0 (c0_sd_ba[0]), // Templated 10
.sd0_adrs11 (c0_sd_adrs[11]), // Templated 11
.sd0_adrs10 (c0_sd_adrs[10]), // Templated 11
.sd0_adrs9 (c0_sd_adrs[9]), // Templated 11
.sd0_adrs8 (c0_sd_adrs[8]), // Templated 11
.sd0_adrs7 (c0_sd_adrs[7]), // Templated 11
.sd0_adrs6 (c0_sd_adrs[6]), // Templated 11
.sd0_adrs5 (c0_sd_adrs[5]), // Templated 11
.sd0_adrs4 (c0_sd_adrs[4]), // Templated 11
.sd0_adrs3 (c0_sd_adrs[3]), // Templated 11
.sd0_adrs2 (c0_sd_adrs[2]), // Templated 11
.sd0_adrs1 (c0_sd_adrs[1]), // Templated 11
.sd0_adrs0 (c0_sd_adrs[0]), // Templated 11
.sd0_clk (sd_clk)); // Templated 8
endmodule
// Local Variables:
// verilog-auto-inst-template-numbers: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v 0000664 0000000 0000000 00000002515 13022141775 0024034 0 ustar 00root root 0000000 0000000 module autoinst_wildcard_sub (/*AUTOARG*/
// Inouts
sd_ras_, sd0_dqm7_l, sd0_dqm6_l, sd0_dqm5_l, sd0_dqm4_l, sd0_dqm3_l,
sd0_dqm2_l, sd0_dqm1_l, sd0_dqm0_l, sd0_ba1, sd0_ba0, sd0_adrs11,
sd0_adrs10, sd0_adrs9, sd0_adrs8, sd0_adrs7, sd0_adrs6, sd0_adrs5,
sd0_adrs4, sd0_adrs3, sd0_adrs2, sd0_adrs1, sd0_adrs0, sd0_clk
);
//======================================================================
// Inputs/Outputs
//======================================================================
inout sd_ras_; // SDRAM Channel 0 Row Address Strobe
inout sd0_dqm7_l; // SDRAM Channel 0 DQM Mask Bits
inout sd0_dqm6_l;
inout sd0_dqm5_l;
inout sd0_dqm4_l;
inout sd0_dqm3_l;
inout sd0_dqm2_l;
inout sd0_dqm1_l;
inout sd0_dqm0_l;
inout sd0_ba1;
inout sd0_ba0;
inout sd0_adrs11; // SDRAM Channel 0 Address
inout sd0_adrs10;
inout sd0_adrs9;
inout sd0_adrs8;
inout sd0_adrs7;
inout sd0_adrs6;
inout sd0_adrs5;
inout sd0_adrs4;
inout sd0_adrs3;
inout sd0_adrs2;
inout sd0_adrs1;
inout sd0_adrs0;
inout sd0_clk; // SDRAM Channel 0 Clocks
endmodule
// Local Variables:
// fill-column: 79
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcell.v 0000664 0000000 0000000 00000006474 13022141775 0023201 0 ustar 00root root 0000000 0000000 module autoinst_wildcard;
/* sub AUTO_TEMPLATE (
.a\(.\)\(.\) (@"(substring vl-cell-name 4 5)"_@"(substring vl-cell-name 6 7)"_a_\1_\2),
); */
sub sub_0_0 (/*AUTOINST*/
// Inputs
.a33 (0_0_a_3_3), // Templated 4
.a34 (0_0_a_3_4), // Templated 4
.a44 (0_0_a_4_4), // Templated 4
.a43 (0_0_a_4_3)); // Templated 4
sub sub_0_1 (/*AUTOINST*/
// Inputs
.a33 (0_1_a_3_3), // Templated 4
.a34 (0_1_a_3_4), // Templated 4
.a44 (0_1_a_4_4), // Templated 4
.a43 (0_1_a_4_3)); // Templated 4
sub sub_1_0 (/*AUTOINST*/
// Inputs
.a33 (1_0_a_3_3), // Templated 4
.a34 (1_0_a_3_4), // Templated 4
.a44 (1_0_a_4_4), // Templated 4
.a43 (1_0_a_4_3)); // Templated 4
sub sub_1_1 (/*AUTOINST*/
// Inputs
.a33 (1_1_a_3_3), // Templated 4
.a34 (1_1_a_3_4), // Templated 4
.a44 (1_1_a_4_4), // Templated 4
.a43 (1_1_a_4_3)); // Templated 4
/* sub AUTO_TEMPLATE (
.a\(.\)\(.\) (b_\1_\2),
); */
sub sub_0_0 (/*AUTOINST*/
// Inputs
.a33 (b_3_3), // Templated 33
.a34 (b_3_4), // Templated 33
.a44 (b_4_4), // Templated 33
.a43 (b_4_3)); // Templated 33
sub sub_0_1 (/*AUTOINST*/
// Inputs
.a33 (b_3_3), // Templated 33
.a34 (b_3_4), // Templated 33
.a44 (b_4_4), // Templated 33
.a43 (b_4_3)); // Templated 33
sub sub_1_0 (/*AUTOINST*/
// Inputs
.a33 (b_3_3), // Templated 33
.a34 (b_3_4), // Templated 33
.a44 (b_4_4), // Templated 33
.a43 (b_4_3)); // Templated 33
sub sub_1_1 (/*AUTOINST*/
// Inputs
.a33 (b_3_3), // Templated 33
.a34 (b_3_4), // Templated 33
.a44 (b_4_4), // Templated 33
.a43 (b_4_3)); // Templated 33
endmodule
module sub;
input a33, a34, a44, a43;
endmodule
// Local Variables:
// verilog-auto-inst-template-numbers: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_belkind.v 0000664 0000000 0000000 00000001134 13022141775 0024017 0 ustar 00root root 0000000 0000000 module autoinstparam_belkind (/*AUTOARG*/) ;
parameter X = 8;
/*
autoinstparam_belkind_leaf AUTO_TEMPLATE (
.P (X),
.a (b[]),
);
*/
autoinstparam_belkind_leaf (/*AUTOINSTPARAM*/
// Parameters
.P (X)) // Templated
leaf(/*AUTOINST*/
// Inputs
.a (b[P-1:0])); // Templated
endmodule // tree
// Local Variables:
// eval:(verilog-read-defines)
// eval:(verilog-read-defines "autoinstparam_belkind_leaf.v")
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_belkind_leaf.v 0000664 0000000 0000000 00000000450 13022141775 0025006 0 ustar 00root root 0000000 0000000 module autoinstparam_belkind_leaf (/*AUTOARG*/
// Inputs
a
) ;
parameter P =3D 4;
input [P-1:0] a;
endmodule // leaf
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_bug287.v 0000664 0000000 0000000 00000000745 13022141775 0023434 0 ustar 00root root 0000000 0000000 module Ptest #(
parameter I_CONTROL = 8'h 00, R_CONTROL = 8'h00)
(
input scanTest,
input scanArst);
endmodule
module t;
Ptest
#(/*AUTOINSTPARAM*/
// Parameters
.I_CONTROL (I_CONTROL),
.R_CONTROL (R_CONTROL))
u_Ptest
(/*AUTOINST*/
// Inputs
.scanTest (scanTest),
.scanArst (scanArst));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_first.v 0000664 0000000 0000000 00000003270 13022141775 0023541 0 ustar 00root root 0000000 0000000 module autoinstparam_first ();
parameter BITSCHANGED;
parameter BITSA;
parameter type BITSB_t;
typedef [2:0] my_bitsb_t;
/* autoinstparam_first_sub AUTO_TEMPLATE (
.BITSA (BITSCHANGED),
); */
autoinstparam_first_sub
#(/*AUTOINSTPARAM*/
// Parameters
.BITSA (BITSCHANGED), // Templated
.BITSB_t (BITSB_t))
sub
(/*AUTOINST*/
// Inouts
.a (a[BITSA:0]),
.b (b));
autoinstparam_first_sub
#(
.BITSB_t (my_bitsb_t),
/*AUTOINSTPARAM*/
// Parameters
.BITSA (BITSCHANGED)) // Templated
sub1
(/*AUTOINST*/
// Inouts
.a (a[BITSA:0]),
.b (b));
autoinstparam_first_sub
#(
.BITSA (1),
.BITSB_t (my_bitsb_t)
/*AUTOINSTPARAM*/)
sub2
(/*AUTOINST*/
// Inouts
.a (a[BITSA:0]),
.b (b));
autoinstparam_first_sub
#(
/*AUTOINSTPARAM*/
// Parameters
.BITSA (BITSCHANGED), // Templated
.BITSB_t (BITSB_t))
sub3
(/*AUTOINST*/
// Inouts
.a (a[BITSA:0]),
.b (b));
endmodule
// Local Variables:
// verilog-auto-inst-param-value:nil
// verilog-typedef-regexp: "_t$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_first_sub.v 0000664 0000000 0000000 00000001064 13022141775 0024411 0 ustar 00root root 0000000 0000000 module autoinstparam_first_sub (/*AUTOARG*/
// Inouts
a, b
);
//======================================================================
// Inputs/Outputs
//======================================================================
localparam IGNORED;
parameter BITSA;
parameter type BITSB_t = bit; // See bug340
inout [BITSA:0] a;
inout BITSB_t b;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_iface_bruce.v 0000664 0000000 0000000 00000001030 13022141775 0024631 0 ustar 00root root 0000000 0000000 module top;
/*AUTOWIRE*/
sub0 #(/*AUTOINSTPARAM*/
// Parameters
.testit2 (testit2),
.TESTIT (TESTIT))
s0 (/*AUTOINST*/
// Inputs
.side_clk (side_clk),
.side_rst_b (side_rst_b));
endmodule
module sub0
#(
parameter string testit2 = 0,
int TESTIT = 0
) (
// clk and resets
input logic side_clk,
input logic side_rst_b,
);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_int.v 0000664 0000000 0000000 00000002454 13022141775 0023207 0 ustar 00root root 0000000 0000000 module xyz
#(parameter int FOO=1, BAR=2,
parameter logic [5:0] BLUP=3, ZOT=4,
parameter LDWRDS=5)
( input x1, x2,
input int i1, i2,
input logic [5:0] i3, i4,
input i5,
output y);
endmodule
module pdq;
input x; output y;
parameter int FOO=1;
endmodule
module abc;
xyz XYZ
#(/*AUTOINSTPARAM*/
// Parameters
.FOO (FOO),
.BAR (BAR),
.BLUP (BLUP[5:0]),
.ZOT (ZOT[5:0]),
.LDWRDS (LDWRDS))
(/*AUTOINST*/
// Outputs
.y (y),
// Inputs
.x1 (x1),
.x2 (x2),
.i1 (i1),
.i2 (i2),
.i3 (i3[5:0]),
.i4 (i4[5:0]),
.i5 (i5));
pdq PDQ
#(/*AUTOINSTPARAM*/
// Parameters
.FOO (FOO))
(/*AUTOINST*/
// Outputs
.y (y),
// Inputs
.x (x));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_local.v 0000664 0000000 0000000 00000001106 13022141775 0023500 0 ustar 00root root 0000000 0000000 //bug889
module leaf #(
parameter DATA_WIDTH = 256,
localparam STRB_WIDTH_SHOULD_BE_HIDDEN = DATA_WIDTH/8 )
();
endmodule
module test;
parameter integer DATA_WIDTH = 256;
parameter integer STRB_WIDTH = DATA_WIDTH/8;
/* leaf AUTO_TEMPLATE (
.DATA_WIDTH( DATA_WIDTH ),
.STRB_WIDTH_SHOULD_BE_HIDDEN ( STRB_WIDTH ),
.\(.*\) ( \1 ),
);*/
leaf
#( /*AUTOINSTPARAM*/
// Parameters
.DATA_WIDTH ( DATA_WIDTH )) // Templated
u_leaf
( /*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autolisp_include.v 0000664 0000000 0000000 00000001055 13022141775 0023005 0 ustar 00root root 0000000 0000000 // See forum topic 176
module autolisp_include (/*AUTOARG*/
// Outputs
foo,
// Inputs
bar
);
//`include "autolisp_include_inc.vh"
/*AUTOINSERTLISP(verilog-library-filenames (insert-file "autolisp_include_inc.vh"))*/
// Beginning of automatic insert lisp
input bar;
output foo;
// End of automatics
assign foo = bar;
// This doesn't need commentary
/*AUTOINSERTLISP(when nil)*/
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autolisp_include_inc.vh 0000664 0000000 0000000 00000000030 13022141775 0023776 0 ustar 00root root 0000000 0000000 input bar;
output foo;
verilog-mode-20161124.fd230e6/tests_ok/autolisp_order_bug356.v 0000664 0000000 0000000 00000002722 13022141775 0023572 0 ustar 00root root 0000000 0000000 module autolisp_top (/*AUTOARG*/);
/* autolisp_inst AUTO_TEMPLATE (
.\(.*\)A (\1_@"(eval tense)"_A),
.\(.*\)B (\1_@"(eval tense)"_B),
);
*/
/* AUTO_LISP(setq tense "is") */
autolisp_inst AUTOLISP_INST_I0
(/*AUTOINST*/
// Outputs
.result (result),
// Inputs
.portA (port_is_A), // Templated
.busA (bus_is_A), // Templated
.portB (port_is_B), // Templated
.busB (bus_is_B)); // Templated
/* AUTO_LISP(setq tense "was") */
autolisp_inst AUTOLISP_INST_I1
(/*AUTOINST*/
// Outputs
.result (result),
// Inputs
.portA (port_was_A), // Templated
.busA (bus_was_A), // Templated
.portB (port_was_B), // Templated
.busB (bus_was_B)); // Templated
endmodule
module autolisp_inst (/*AUTOARG*/
// Outputs
result,
// Inputs
portA, busA, portB, busB
);
input portA;
input [3:0] busA;
input portB;
input [1:0] busB;
output result;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autolisp_truex.v 0000664 0000000 0000000 00000001065 13022141775 0022532 0 ustar 00root root 0000000 0000000 module ExampInsertLisp;
/*AUTOINSERTLISP(my-verilog-insert-hello "world")*/
// Beginning of automatic insert lisp
initial $write("hello world");
// End of automatics
// Try an empty insert
/*AUTOINSERTLISP(+ 1)*/
// Try a shell command
/*AUTOINSERTLISP(insert (shell-command-to-string "echo //hello"))*/
// Beginning of automatic insert lisp
//hello
// End of automatics
endmodule
/*
Local Variables:
eval:
(defun my-verilog-insert-hello (who)
(insert (concat "initial $write(\"hello " who "\");\n")))
End:
*/
verilog-mode-20161124.fd230e6/tests_ok/autologic.sv 0000664 0000000 0000000 00000005334 13022141775 0021617 0 ustar 00root root 0000000 0000000 module top
#(parameter COLS = 4
)
( input logic clk,
input logic rstb,
input logic [COLS-1:0] ival,
input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
output logic reg_assigned
);
// Request: AUTOLOGIC instead of AUTOWIRE
// Request: AUTOLOGIC would substitute all 3 existing macros AUTOWIRE/AUTOREG/AUTOREGINPUT, one would use AUTOLOGIC instead of AUTOWIRE/AUTOREG or AUTOWIRE/AUTOREGINPUT.
// Could use AU-TOLOGIC
// Or AU-TOWIRE(logic)
// And-or (setq verilog-auto-sv t)
// And-or (setq verilog-auto-wire-type 'logic')
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output logic COLS;
output logic in1a; // To isub2 of sub2.v, ...
output logic in1b; // To isub1 of sub1.v
output logic in2b; // To isub2 of sub2.v
output logic out1a; // From isub1 of sub1.v
output logic [1:0] out1b; // From isub1 of sub1.v
output logic [1:0] out2b; // From isub2 of sub2.v
// End of automatics
/*AUTOREG*/
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
logic in1a; // To isub2 of sub2.v, ...
logic in1b; // To isub1 of sub1.v
logic in2b; // To isub2 of sub2.v
// End of automatics
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic out1a; // From isub1 of sub1.v
logic [1:0] out1b; // From isub1 of sub1.v
logic [1:0] out2b; // From isub2 of sub2.v
// End of automatics
/* sub2 AUTO_TEMPLATE(
.idata_some_extra_sig_length ( s1_odata),
.ival ( s1_oval),
);*/
sub2 isub2 (/*AUTOINST*/
// Outputs
.out2b (out2b[1:0]),
// Inputs
.in1a (in1a),
.in2b (in2b),
.out1a (out1a));
sub1 isub1(/*AUTOINST*/
// Outputs
.out1a (out1a),
.out1b (out1b[1:0]),
// Inputs
.in1a (in1a),
.in1b (in1b));
always @(posedge clk) begin
reg_assigned <= 1;
end
endmodule
module sub1
( input logic in1a,
input logic in1b,
output logic out1a,
output logic [1:0] out1b
);
endmodule
module sub2
( input logic in1a,
input logic in2b,
input logic out1a,
output logic [1:0] out2b
);
endmodule
// Local Variables:
// verilog-auto-wire-type: "logic"
// End:
verilog-mode-20161124.fd230e6/tests_ok/automodport_ex.v 0000664 0000000 0000000 00000001226 13022141775 0022513 0 ustar 00root root 0000000 0000000 interface ExampIf
( input logic clk );
logic req_val;
logic [7:0] req_dat;
clocking mon_clkblk @(posedge clk);
input req_val;
input req_dat;
endclocking
modport mp(clocking mon_clkblk);
endinterface
module ExampMain
( input clk,
/*AUTOINOUTMODPORT("ExampIf" "mp")*/
// Beginning of automatic in/out/inouts (from modport)
input req_val,
input [7:0] req_dat
// End of automatics
);
/*AUTOASSIGNMODPORT("ExampIf" "mp" "inst")*/
// Beginning of automatic assignments from modport
assign inst.req_dat = req_dat;
assign inst.req_val = req_val;
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests_ok/automodport_full.v 0000775 0000000 0000000 00000006000 13022141775 0023037 0 ustar 00root root 0000000 0000000
module auto_module
( input my_clk,
input my_rst_n,
output manually_listed,
/*AUTOINOUTMODPORT("automodport_if" "pure_mp")*/
// Beginning of automatic in/out/inouts (from modport)
output out_pure,
input in_pure,
// End of automatics
//ex: input in_pure;
//ex: output out_pure;
/*AUTOINOUTMODPORT("automodport_if" "req_mon_mp")*/
// Beginning of automatic in/out/inouts (from modport)
input req_val,
input [63:0] req_dat,
input req_credit,
// End of automatics
//ex: input req_credit, // To auto_i of auto_intf.sv
//ex: input [63:0] req_data, // To auto_i of auto_intf.sv
//ex: input req_val, // To auto_i of auto_intf.sv
/*AUTOINOUTMODPORT("automodport_if" "rsp_drv_mp")*/
// Beginning of automatic in/out/inouts (from modport)
output [1:0] rsp_cmd,
output [63:0] rsp_data,
input rsp_credit
// End of automatics
//ex: output [1:0] rsp_cmd, // From auto_i of auto_intf.sv
//ex: input rsp_credit, // To auto_i of auto_intf.sv
//ex: output [63:0] rsp_data // From auto_i of auto_intf.sv
);
auto_intf auto_i
(// Inputs
.clk (my_clk),
.rst_n (my_rst_n));
/*AUTOASSIGNMODPORT("automodport_if" "req_mon_mp" "auto_i" )*/
// Beginning of automatic assignments from modport
assign auto_i.manually_listed = manually_listed;
assign auto_i.req_credit = req_credit;
assign auto_i.req_dat = req_dat;
assign auto_i.req_val = req_val;
// End of automatics
//ex: assign auto_i.req_credit = req_credit;
//ex: assign auto_i.req_data = req_data;
//ex: assign auto_i.req_val = req_val;
/*AUTOASSIGNMODPORT("automodport_if" "rsp_drv_mp" "auto_i" )*/
// Beginning of automatic assignments from modport
assign rsp_cmd = auto_i.rsp_cmd;
assign rsp_data = auto_i.rsp_data;
assign auto_i.rsp_credit = rsp_credit;
// End of automatics
//ex: assign rsp_cmd = auto_i.rsp_cmd;
//ex: assign rsp_data = auto_i.rsp_data;
//ex: assign auto_i.rsp_credit = rsp_credit;
/*AUTOASSIGNMODPORT("automodport_if" "r.*" "auto_i" )*/
// Beginning of automatic assignments from modport
assign rsp_cmd = auto_i.rsp_cmd;
assign rsp_data = auto_i.rsp_data;
assign auto_i.manually_listed = manually_listed;
assign auto_i.req_credit = req_credit;
assign auto_i.req_dat = req_dat;
assign auto_i.req_val = req_val;
assign auto_i.rsp_credit = rsp_credit;
// End of automatics
initial begin
`cn_set_intf(virtual auto_intf.req_mon_mp, "auto_pkg::auto_intf", "req_mon_vi", auto_i.req_mon_mp );
`cn_set_intf(virtual auto_intf.rsp_drv_mp, "auto_pkg::auto_intf", "rsp_drv_vi", auto_i.rsp_drv_mp );
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/automodport_if.v 0000664 0000000 0000000 00000004323 13022141775 0022476 0 ustar 00root root 0000000 0000000 interface automodport_if
( input logic clk,
input logic rst_n
);
//----------------------------------------------------------------------------------------
// Group: Signals
logic req_val;
logic [63:0] req_dat;
logic req_credit;
logic [1:0] rsp_cmd;
logic [63:0] rsp_data;
logic rsp_credit;
logic in_pure;
logic out_pure;
logic manually_listed;
//----------------------------------------------------------------------------------------
// Group: Clocking blocks
clocking req_mon_cb @(posedge clk);
input rst_n;
input req_val;
input req_dat;
input req_credit;
input manually_listed;
endclocking : req_mon_cb
clocking rsp_drv_cb @(posedge clk);
input rst_n;
output rsp_cmd;
output rsp_data;
input rsp_credit;
endclocking : rsp_drv_cb
//----------------------------------------------------------------------------------------
// Group: Modports
modport req_mon_mp(clocking req_mon_cb);
modport rsp_drv_mp(clocking rsp_drv_cb, import rsp_reset);
modport pure_mp(input in_pure, output out_pure);
//----------------------------------------------------------------------------------------
// Group: Methods
function void rsp_reset();
rsp_cmd = 2'b0;
rsp_data = 64'b0;
endfunction : rsp_reset
//----------------------------------------------------------------------------------------
// Group: Assertions
logic [1:0] cmd_m1;
always @(posedge clk) begin
cmd_m1 <= rsp_cmd;
if(rst_n) begin
if($isunknown(req_val)) `cn_err_intf(("Signal req_data_cycle is an X."));
if(req_val==1'b1 & $isunknown(req_data)) `cn_err_intf(("Signal req_data is an X."));
if($isunknown(req_credit)) `cn_err_intf(("Signal req_credit is an X."));
if($isunknown(rsp_cmd)) `cn_err_intf(("Signal rsp_cmd is an X."));
if(cmd_m1!=2'b0 & $isunknown(rsp_data)) `cn_err_intf(("Signal rsp_data is an X."));
if($isunknown(rsp_credit)) `cn_err_intf(("Signal rsp_credit is an X."));
end
end
endinterface
verilog-mode-20161124.fd230e6/tests_ok/autooutput_comma.v 0000664 0000000 0000000 00000002424 13022141775 0023050 0 ustar 00root root 0000000 0000000 module top
(input [(`WIDTH):0] a, /* This comma gets deleted */
/*AUTOOUTPUT*/
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input b // To child of child.v
// End of automatics
);
child child(/*AUTOINST*/
// Inputs
.b (b));
endmodule
module nocomma
(/*AUTOOUTPUT*/
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input b // To child of child.v
// End of automatics
);
child child(/*AUTOINST*/
// Inputs
.b (b));
endmodule
module ifdefcomma
(
`ifdef a
input foo,
`endif
/*AUTOOUTPUT*/
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input b // To child of child.v
// End of automatics
);
child child(/*AUTOINST*/
// Inputs
.b (b));
endmodule
module ifdefnocomma
(
`ifdef a
// It's up to the user to deal with the , themself
input foo,
`endif
/*AUTOOUTPUT*/
);
child child(/*AUTOINST*/
// Inputs
.b (b));
endmodule
module child(input b);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autooutput_regexp.v 0000664 0000000 0000000 00000001542 13022141775 0023246 0 ustar 00root root 0000000 0000000 module ex_output_every (/*AUTOARG*/
// Outputs
sub1_out_pixel
)
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output pixel24_t sub1_out_pixel; // From i1 of v2k_typedef_yee_sub1.v
// End of automatics
v2k_typedef_yee_sub1 i1
(/*AUTOINST*/
// Outputs
.sub1_out_pixel (sub1_out_pixel),
.sub1_to_sub2 (sub1_to_sub2),
.sub1_to_sub2_and_top (sub1_to_sub2_and_top),
// Inputs
.sub1_in_pixel (sub1_in_pixel),
.cp (cp),
.reset (reset));
endmodule
// Local Variables:
// verilog-auto-output-ignore-regexp:"^sub1_to_sub2"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autooutputevery_assign.v 0000664 0000000 0000000 00000000522 13022141775 0024310 0 ustar 00root root 0000000 0000000 module ex_output_every (o,i,tempa,tempb)
output o;
input i;
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output tempa;
output tempb;
// End of automatics
wire tempa;
wire tempb;
wire o;
assign tempa = i;
assign tempb = tempa;
assign o = tempb;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autooutputevery_example.v 0000664 0000000 0000000 00000000440 13022141775 0024456 0 ustar 00root root 0000000 0000000 module ex_output_every (o,i,tempa,tempb)
output o;
input i;
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output tempa;
output tempb;
// End of automatics
wire tempa = i;
wire tempb = tempa;
wire o = tempb;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autooutputevery_regexp.v 0000664 0000000 0000000 00000000313 13022141775 0024314 0 ustar 00root root 0000000 0000000 module top
(
/*AUTOOUTPUTEVERY("^a")*/
// Beginning of automatic outputs (every signal)
output aa,
output ab
// End of automatics
);
wire aa;
wire ab;
wire cc;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autooutputevery_wire.v 0000664 0000000 0000000 00000003663 13022141775 0024003 0 ustar 00root root 0000000 0000000 module test (/*AUTOARG*/
// Outputs
stage2_bus, stage3_bus,
// Inputs
stage1_bus
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output logic [7:0] stage3_bus; // From i_second of sub_module.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic [7:0] stage1_bus; // To i_first of sub_module.v
// End of automatics
/*AUTOOUTPUTEVERY("^stage")*/
// Beginning of automatic outputs (every signal)
output logic [7:0] stage2_bus; // From i_first of sub_module.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [7:0] stage2_bus; // From i_first of sub_module.v
// End of automatics
/*AUTOREG*/
/* sub_module AUTO_TEMPLATE
(
.i_\(.*\) (stage1_\1[]),
.o_\(.*\) (stage2_\1[]),
); */
sub_module i_first (/*AUTOINST*/
// Outputs
.o_bus (stage2_bus[7:0]), // Templated
// Inputs
.i_bus (stage1_bus[7:0])); // Templated
/* sub_module AUTO_TEMPLATE
(
.i_\(.*\) (stage2_\1[]),
.o_\(.*\) (stage3_\1[]),
); */
sub_module i_second (/*AUTOINST*/
// Outputs
.o_bus (stage3_bus[7:0]), // Templated
// Inputs
.i_bus (stage2_bus[7:0])); // Templated
endmodule // test
module sub_module (/*AUTOARG*/
// Outputs
o_bus,
// Inputs
i_bus
);
input logic [7:0] i_bus ;
output logic [7:0] o_bus ;
assign o_bus = i_bus;
endmodule // sub_module
verilog-mode-20161124.fd230e6/tests_ok/autoreg_outreg.v 0000664 0000000 0000000 00000001377 13022141775 0022504 0 ustar 00root root 0000000 0000000 module foo
#(parameter
PARAM3_P=99)
(
output sig3,// Here, I've hit "tab" twice and this line is correct
output reg [PARAM2_P-1:0] s4, // Comment here which should be at "comment-column"
output wire [PARAM2_P-1:0] sig5,// Comment here which should be at "comment-column"
input reset_L// module reset: global register
);
/*AUTOWIRE*/
// AUTOREG here is somewhat illegal, as outputs when a type is declared
// in a V2K decl list are automatically "reg'ed".
// However some simulators take it, so be sane and only do undeclared ones...
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg sig3;
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreg_smith_multiassign.v 0000664 0000000 0000000 00000000464 13022141775 0024736 0 ustar 00root root 0000000 0000000 module test(/*AUTOARG*/
// Outputs
a1, b1, c1, one
);
output [5:0] a1;
output [5:0] b1;
output [5:0] c1;
/*AUTOREG*/
//wire [5:0] a2,b2,c2;
assign {a1,b1,c1} = {a2,b2,c2};
output [1:0] one;
assign one = a2[0];
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreginput.v 0000664 0000000 0000000 00000001227 13022141775 0022171 0 ustar 00root root 0000000 0000000 module autoreginput;
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg lower_ina; // To inst of inst.v
reg lower_inb; // To inst of inst.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire lower_out; // From inst of inst.v
// End of automatics
inst inst (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
// Inputs
.lower_inb (lower_inb),
.lower_ina (lower_ina));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_assert.v 0000664 0000000 0000000 00000000603 13022141775 0023034 0 ustar 00root root 0000000 0000000 module foo;
reg [1:0] a;
assert property (@(posedge clk) e |-> f);
reg [1:0] b;
always @(posedge clk, negedge rst)
if (~rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= 2'h0;
b <= 2'h0;
// End of automatics
end
else begin
a<=b;
b<=a;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_cond.v 0000664 0000000 0000000 00000001215 13022141775 0022456 0 ustar 00root root 0000000 0000000 module x;
reg [1:0] idx_sel_2a;
always @(posedge usclk or negedge srst_0a_n) begin
if (~srst_0a_n) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
bar <= 1'h0;
foo <= 1'h0;
// End of automatics
end
else begin
foo <= idx_adr_1a[1:0];
bar <= (idx_sel_2a == 2'h0 ? idx_rd_dat0_2a[12:0] :
idx_sel_2a == 2'h1 ? idx_rd_dat1_2a[12:0] :
idx_sel_2a == 2'h2 ? idx_rd_dat2_2a[12:0] :
/**/ idx_rd_dat3_2a[12:0]);
end
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_define_colon.v 0000664 0000000 0000000 00000001346 13022141775 0024164 0 ustar 00root root 0000000 0000000 // bug594
`define TABADR_EGR_MOD_MAP 7:0
module test (
/*AUTOARG*/
// Inputs
clk, rst, addr
);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
input clk;
input rst;
input [`TABADR_EGR_MOD_MAP] addr;
reg [`TABADR_EGR_MOD_MAP] addrD1;
reg [`TABADR_EGR_MOD_MAP] addrD2;
always @(posedge clk or posedge rst) begin
if (rst_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
addrD1 <= `0/*NOWIDTH*/;
addrD2 <= `0/*NOWIDTH*/;
// End of automatics
end
else begin
addrD1 <= addr ;
addrD2 <= addrD1;
end
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_dever.v 0000664 0000000 0000000 00000002540 13022141775 0022642 0 ustar 00root root 0000000 0000000 module x;
always @(posedge piclk) begin
if (k_i_reset) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
idat_ICErrData_i3 <= 1'h0;
// End of automatics
end
else begin
idat_ICErrData_i3 <= idat_way0_i2[1*OPCWID-1:0*OPCWID];
end
end
// 2010-04-08
localparam MPND = 5;
always @(posedge usclk)
if (~sso_srst_n) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rd_dat_s4 <= 1'h0;
sel_s3 <= 1'h0;
// End of automatics
end
else begin
sel_s3 <= adr_s2[MIDX];
rd_dat_s4 <= (sel_s3 == 1'h0 ? rd_dat0_s3[MPND:0]
: rd_dat1_s3[MPND:0]);
end
// 2010-04-15
integer i;
always @(posedge usclk)
if (~sso_srst_n) begin
for (int j=0; j<10; j++) blob[j] <= 0;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
zsv <= 1'h0;
zz <= 1'h0;
// End of automatics
end
else begin
for (i=0; i<10; i++) blob[i] <= blob[i+1];
for (i=0; i<10; i++) zz <= 1;
for (int isv=0; isv<10; isv++) zsv <= 1;
end
always @(/*AS*/in) begin
for (i=0; i<10; i++) zz <= in;
for (int isv=0; isv<10; isv++) zsv <= in;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_eq_bug381.v 0000664 0000000 0000000 00000001104 13022141775 0023226 0 ustar 00root root 0000000 0000000 module t();
logic [31:0] sum;
logic [31:0] a;
logic [31:0] b;
reg [32:0] tmp;
always @(posedge clk or negedge rst) begin
if (!rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
sum <= 32'h0;
// End of automatics
end
else begin
//reg [32:0] tmp;
tmp = a + b;
if (tmp[32])
sum <= 32'hffffffff;
else
sum <= tmp[31:0];
end
end
endmodule
// Local Variables:
// verilog-auto-reset-blocking-in-non: nil
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoreset_eq_bug381_non.v 0000664 0000000 0000000 00000001131 13022141775 0024100 0 ustar 00root root 0000000 0000000 module t();
logic [31:0] sum;
logic [31:0] a;
logic [31:0] b;
reg [32:0] tmp;
always @(posedge clk or negedge rst) begin
if (!rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
sum <= 32'h0;
tmp = 33'h0;
// End of automatics
end
else begin
//reg [32:0] tmp;
tmp = a + b;
if (tmp[32])
sum <= 32'hffffffff;
else
sum <= tmp[31:0];
end
end
endmodule
// Local Variables:
// verilog-auto-reset-blocking-in-non: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoreset_equal_extra.v 0000664 0000000 0000000 00000002655 13022141775 0024056 0 ustar 00root root 0000000 0000000 module autoreset_equal_extra ();
always_ff @(posedge csclk) begin
if( ~srst_n | !val_tx_to_csi ) begin
csi.cmd <= ncbo_cmd_t'('0);
// vvvvvv fifo.data.cb_req.req.cmd = '0; should not be below
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
csi.src <= 1'h0;
csi.wr <= 1'h0;
// End of automatics
end
else begin
if (fifo.sot) begin
csi.src <= fifo.src;
csi.wr <= (fifo.data.cb_req.req.cmd == ncb_defs::NCBO_RSVD_LMTST
| fifo.data.cb_req.req.cmd == ncb_defs::NCBO_IOBST
);
csi.cmd <= fifo.data.cb_req.req.cmd;
end
end
end
always_ff @(posedge csclk) begin
if (~srst_n) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
sdp__x2p.bval <= 1'h0;
sdp__x2p.err <= 1'h0;
// End of automatics
end
else begin
sdp__x2p.err <= (x2p_fifo_rdat.err & x2p_fifo_pop_d3_sk)
? x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_RCVERR
: x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_NONE;
sdp__x2p.bval <= x2p_fifo_rdat.bval & {4{x2p_fifo_pop_d3_sk}};
//FOO::bar <= 1; // Legal, though not typically used in RTL
end
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_if.v 0000664 0000000 0000000 00000003301 13022141775 0022127 0 ustar 00root root 0000000 0000000 //From: "Chris Kappler"
//Verilint 440 off // WARNING: Clock is used as a reset
//Verilint 394 off // WARNING: Multiple clocks in the always block
//Verilint 71 off // WARNING: Case statement without default clause
module x (/*AUTOARG*/
// Outputs
a, b, c,
// Inputs
clk, reset_l, in_a, in_b, in_c
);
input clk, reset_l, in_a,in_b,in_c;
output a,b,c;
reg a,b,c;
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
c <= 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= #1 0;
b <= #1 0;
// End of automatics
end
else begin
a <= in_a;
b <= in_b;
c <= in_c;
end
end
always @(posedge clk or negedge reset_l) begin
casex ({reset_l,in_a})
2'b1_x: begin
a <= in_a;
b <= in_b;
c <= in_c;
end
2'b0_x: begin
c <= 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= #1 0;
b <= #1 0;
// End of automatics
end
endcase
end
always @(/*AS*/in_a or in_b or reset_l) begin
casex ({reset_l,in_a})
2'b1_x: begin
a = in_a;
b = in_b;
end
2'b0_x: begin
c = 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a = 0;
b = 0;
// End of automatics
end
endcase
end
endmodule
// Local Variables:
// verilog-auto-reset-widths: nil
// verilog-assignment-delay: "#1 "
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoreset_ifndef_dc.v 0000664 0000000 0000000 00000000653 13022141775 0023441 0 ustar 00root root 0000000 0000000 module x;
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
c <= 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= 1'h0;
b <= 1'h0;
x <= 1'h0;
// End of automatics
end
else begin
a <= in_a;
b <= in_b;
c <= in_c;
`ifndef DC
x <= 1'b1;
`endif
end
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_inf_bug325.v 0000664 0000000 0000000 00000000237 13022141775 0023401 0 ustar 00root root 0000000 0000000 module aaa();
always @(a) begin
if (a) begin
/*AUTORESET*/
end
// note missing e-n-d
always @(*) begin
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_label_gorfajn.v 0000664 0000000 0000000 00000000543 13022141775 0024323 0 ustar 00root root 0000000 0000000 module autoreset_label_gorfajn;
always_ff @(posedge clk or negedge reset)
if (~reset) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= 1'h0;
z <= 1'h0;
// End of automatics
end else begin
a<=b;
foo: assert (b==4);
bar: z<=1;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_latch.v 0000664 0000000 0000000 00000003551 13022141775 0022633 0 ustar 00root root 0000000 0000000 //bug844
module device(
input clk,
output logic [7:0] Q, out0,
output logic pass, fail
input [7:0] D, in0,in1 );
enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
logic ready, next_ready;
logic next_pass, next_fail;
always_ff @(posedge clk, negedge rstn)
if (!rstn) begin
state <= IDLE;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
fail <= 1'h0;
pass <= 1'h0;
ready <= 1'h0;
// End of automatics
end
else begin
state <= next_state;
ready <= next_ready;
pass <= next_pass;
fail <= next_fail;
end
always @* begin
if (!ready) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
out0 = 8'h0;
// End of automatics
end
else begin
out0 = sel ? in1 : in0;
end
end
always_comb begin
next_state = state;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
next_fail = 1'h0;
next_pass = 1'h0;
next_ready = 1'h0;
// End of automatics
case (state)
IDLE : begin
// stuff ...
end
/* Other states */
PASS: begin
next_state = IDLE;
// stuff ...
next_pass = 1'b1;
next_ready = 1'b1;
end
FAIL: begin
next_state = IDLE;
// stuff ...
next_fail = 1'b1;
end
endcase
end
always_latch begin
if (!rstn) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
Q <= 8'h0;
// End of automatics
end
else if (clk) begin
Q <= D;
end
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_reed.v 0000664 0000000 0000000 00000001246 13022141775 0022456 0 ustar 00root root 0000000 0000000 module x;
reg a;
reg b;
reg c;
always @(/*AUTOSENSE*/a or b or rst) begin
if ( rst ) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
c = 1'h0;
// End of automatics
end
else begin
if ( a <= b ) begin
c = a;
end
else begin
c = b;
end
end
end
always @ (posedge a) begin
if ( rst ) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
c <= 1'h0;
// End of automatics
end
else if ( a <= b ) begin
c <= a;
end
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autoreset_struct.v 0000664 0000000 0000000 00000003347 13022141775 0023067 0 ustar 00root root 0000000 0000000 //bug906
import gmcupkg::*;
module gminstdecode
(
output instClassType instClass
/*blah blah blah*/);
always_comb begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
instClass.iFunc = '0;
instClass.isBool = '0;
instClass.sub.bool = '0;
instClass.sub2.sub3.bool = '0;
// End of automatics
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
instClass.sub.bool = 1'b1;
instClass.sub2.sub3.bool = 1'b1;
end
end
always_comb begin
instClass = '{default:0}; // #1 (see below)
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
end
end
always_comb begin
instClass.iFunc = IFUNC_ADD; // #2
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
instClass.isBool = '0;
// End of automatics
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
end
end
always_comb begin
instClass.sub = '0;
instClass.sub2 = '0;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
instClass.sub3.sub4.bool = '0;
// End of automatics
if (ldBitFromIo | stBitToIo) begin
instClass.sub.bool = 1'b1;
instClass.sub2.sub3.bool = 1'b1;
instClass.sub3.sub4.bool = 1'b1;
end
end
endmodule
// Local Variables:
// verilog-auto-reset-widths: unbased
// verilog-typedef-regexp: "Type$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoreset_widths.v 0000664 0000000 0000000 00000003427 13022141775 0023044 0 ustar 00root root 0000000 0000000 // $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
logic_four <= 4'h0;
m_def2_r <= {(1+(`M)-(`L)){1'b0}};
m_param_r <= {(1+(MS)-(LS)){1'b0}};
m_wid1_r <= 1'h0;
m_wid3_r <= 3'h0;
m_wid4_r_l <= ~4'h0;
paramed <= {PARAM{1'b0}};
// End of automatics
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: t
// verilog-active-low-regexp: "_l$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoreset_widths_unbased.v 0000664 0000000 0000000 00000003344 13022141775 0024543 0 ustar 00root root 0000000 0000000 // $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
logic_four <= '0;
m_def2_r <= '0;
m_param_r <= '0;
m_wid1_r <= '0;
m_wid3_r <= '0;
m_wid4_r_l <= ~'0;
paramed <= '0;
// End of automatics
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: unbased
// verilog-active-low-regexp: "_l$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autosense.v 0000664 0000000 0000000 00000001760 13022141775 0021453 0 ustar 00root root 0000000 0000000 module autosense (/*AUTOARG*/
// Outputs
out, out2,
// Inputs
ina, inb, inc
);
input ina;
input inb;
input inc;
output [1:0] out;
output out2;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [1:0] out;
reg out2;
// End of automatics
`include "autosense_inc_param.v"
`include "autosense_one.v"
`define Input ina
always @(/*AUTOSENSE*/ina or inb or inc) begin
case (inc)
1'b1: out = {`Input ? `one : 1'b0, `Input};
default: out = {2{inb}};
endcase
end
always @(/*AUTOSENSE*/ina) begin
out2 = `Input | PARAM_TWO | PARAM_THREE | PARAM_FOUR;
end
always @(*) begin
// @ (/*AS*/)
out3 = ina;
end
always @* begin
out3 = ina;
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autosense_aas_ifdef.v 0000664 0000000 0000000 00000002522 13022141775 0023431 0 ustar 00root root 0000000 0000000 module dummy;
parameter [TSTBITS-1:0] // synopsys enum tstate_info
TIDLE = 3'b000,
TCN1 = 3'b001,
TCN2 = TCN1+1, // must be numbered consecutively
TCN3 = TCN2+1,
TCN4 = TCN3+1,
TCN5 = TCN4+1,
IOCLR = TCN5+1,
TUNU1 = 3'b111;
// state and output logic
always @ (`ifdef SIMFSM
ireset or
`endif
/*AUTOSENSE*/fooc2_qual or foocr_we or ioclrinst or tstate) begin
ioclrtmout = 1'b0;
case (tstate)
TIDLE: begin
if (foocr_we)
ntstate = TCN1;
else
ntstate = TIDLE;
end
TCN1,TCN2,TCN3,TCN4,TCN5: begin
if (ioclrinst | fooc2_qual)
ntstate = TIDLE;
else
ntstate = tstate + 1;
end
IOCLR: begin
ntstate = TIDLE;
ioclrtmout = 1'b1;
end
TUNU1: begin
ntstate = TIDLE;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unused state at %t",$time);
`endif
end
default: begin
ntstate = 'bx;
ioclrtmout = 1'bx;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unknown state at %t",$time);
`endif
end
endcase // case(tstate)
end // always @ (...
endmodule // dummy
verilog-mode-20161124.fd230e6/tests_ok/autosense_add_or.v 0000664 0000000 0000000 00000000666 13022141775 0022767 0 ustar 00root root 0000000 0000000 module autosense_or(/*AUTOARG*/
// Outputs
x, y,
// Inputs
a, c
);
input a;
input c;
output x;
output y;
always @(a/*AUTOSENSE*/) begin
x = a;
end
always @(a/*AUTOSENSE*/ or c) begin
x = a | c;
end
// always @(a or/*AUTOSENSE*/c) begin
// x = a | c;
// end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autosense_chadha.v 0000664 0000000 0000000 00000001245 13022141775 0022741 0 ustar 00root root 0000000 0000000 module test (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
sel, in0, in1, in2
);
input [1:0] sel;
input in0, in1, in2;
output out1;
output out2;
reg out1;
reg out2;
// Missing in2
always @ (/*AS*/in0 or in1 or in2 or sel)
if (sel == 2'b00)
begin
out1 = in1;
out2 = in0;
end
else
begin
out1 = in2;
out2 = in1;
end
// OK
always @ (/*AS*/in1 or in2 or sel)
if (sel == 2'b00)
out1 = in1;
else
out1 = in2;
endmodule // test
verilog-mode-20161124.fd230e6/tests_ok/autosense_define_hang.v 0000664 0000000 0000000 00000000327 13022141775 0023760 0 ustar 00root root 0000000 0000000 //From: Anup Sharma
module x;
always @ (/*AS*/`EC_EXCLU or `EC_SHARE or jpack_share) begin
jb_mc_xact_state_a1[2:0] <= #1 jpack_share[7] ? `EC_SHARE : `EC_EXCLU;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autosense_dittrich.v 0000664 0000000 0000000 00000001021 13022141775 0023333 0 ustar 00root root 0000000 0000000 module testcase
(/*AUTOARG*/
// Outputs
Z,
// Inputs
A, B, C, D, SEL
);
input A, B, C, D;
input [1:0] SEL;
output Z;
`include autosense_dittrich_inc.v
always @(/*AS*/A or B or C or D or SEL) begin
case (SEL)
sel_a: Z = A;
sel_b: Z = B;
sel_c: Z = C;
sel_d: Z = D;
default: Z = D;
endcase // case(SEL)
end // always @ (...
endmodule // testcase
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autosense_dittrich_inc.v 0000664 0000000 0000000 00000000472 13022141775 0024175 0 ustar 00root root 0000000 0000000 parameter sel_a = {1'b 0, 1'b 0}; // 2'd 0 works fine
parameter sel_b = {1'b 0, 1'b 1}; // 2'd 1 works fine
parameter sel_c = 2'd 2,
sel_d = 2'd 3;
//parameter sel_a = {1'b 0, 1'b 0}, // 2'd 0 works fine
// sel_b = {1'b 0, 1'b 1}, // 2'd 1 works fine
// sel_c = 2'd 2,
// sel_d = 2'd 3;
verilog-mode-20161124.fd230e6/tests_ok/autosense_gifford.v 0000664 0000000 0000000 00000002246 13022141775 0023153 0 ustar 00root root 0000000 0000000 module x (/*AUTOARG*/);
// Which Internal Bank
`define DMC_AG_HADDR_BADDR_BST2_RNG 1:0 // Bank Address Range within Hexabyte Address for 2-Burst
`define DMC_AG_HADDR_BADDR_BST4_RNG 2:1 // Bank Address Range within Hexabyte Address for 4-Burst
`define DMC_AG_HADDR_BADDR_BST8_RNG 3:2 // Bank Address Range within Hexabyte Address for 8-Burst
reg [NumBnks-1:0] ibnk_sel_s; // Muxed internal bank address subfield of
command address
always @(/*AUTOSENSE*/lio_buscfg_brstlen2_sr or lio_buscfg_brstlen4_sr or m_cdq_haddr_sr)
begin : PeelIntBnkAddr
case ({lio_buscfg_brstlen4_sr,lio_buscfg_brstlen2_sr})
2'b01: // 2-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST2_RNG];
end
2'b10: // 4-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST4_RNG];
end
default: // 8-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST8_RNG];
end
endcase
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autosense_if_else.v 0000664 0000000 0000000 00000000351 13022141775 0023134 0 ustar 00root root 0000000 0000000 module x;
always @ (/*AS*/a or b or c)
if (a) q = b;
else r = c;
always @ (/*AS*/a or b or c or d or e)
if (a) q = b;
else if (c) r = d;
/* skip comments as usual */
else r = e;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autosense_inandout.v 0000664 0000000 0000000 00000000252 13022141775 0023347 0 ustar 00root root 0000000 0000000 module autosense_inandout(a,b);
input a;
output b;
reg b;
reg c;
always @(/*AUTOSENSE*/a) begin
c=a;
b=c;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autosense_inc_param.v 0000664 0000000 0000000 00000000120 13022141775 0023451 0 ustar 00root root 0000000 0000000
parameter [2:0] PARAM_TWO = 2,
PARAM_THREE = 3;
parameter PARAM_FOUR = 4;
verilog-mode-20161124.fd230e6/tests_ok/autosense_jbrown.v 0000664 0000000 0000000 00000001370 13022141775 0023031 0 ustar 00root root 0000000 0000000 `define LCH_GSWDATWID 3
`define COM_CLDATWID 2
module autosense_jbrown(/*AUTOARG*/
// Outputs
lch_gswdata,
// Inputs
com_cldata
);
output [`LCH_GSWDATWID-1:0] lch_gswdata; // data to switch
input [`COM_CLDATWID-1:0] com_cldata; // data bus to clusters
/*autowire*/
reg tmp;
`define TEST_DEFINE 1'b0
always @ (/*AUTOSENSE*/)
begin
/* AUTO_CONSTANT (`TEST_DEFINE) */
tmp <= `TEST_DEFINE; // test defines
end
// Local Variables:
// verilog-library-directories:("." "../cdp/")
// verilog-library-extensions:(".v" ".vh")
// End:
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autosense_lavinge.v 0000664 0000000 0000000 00000000311 13022141775 0023147 0 ustar 00root root 0000000 0000000 module test
#(parameter FOO=1)
( a, b );
input a;
input b;
reg c;
wire d;
always @(/*AUTOSENSE*/b or d)
begin
c=0;
if (d) c = b;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autosense_mcardle_onehot.v 0000664 0000000 0000000 00000001511 13022141775 0024510 0 ustar 00root root 0000000 0000000 module x;
input [5:0] state;
output [5:0] next;
parameter CYCLEA = 1;
parameter CYCLEC = 2;
parameter MSTRA = 3;
parameter MSTRB = 4;
parameter MSTRC = 5;
// make sure 'state' is listed
always @ (/*AUTOSENSE*/done or nREQA or nREQB or nREQC or state) begin
next = 6'b0;
case (1'b1)
state[CYCLEC] : begin
if (!nREQA && done) next[MSTRA] = 1'b1;
else if (!nREQB && nREQA && done)next[MSTRB] = 1'b1;
else if (!nREQC && nREQA && nREQB && done) next[MSTRC] = 1'b1;
else next[CYCLEC] = 1'b1;
end
state[MSTRA] : begin
if (!nREQB || !nREQC) next[CYCLEA] = 1'b1;
else next[MSTRA] = 1'b1;
end
endcase
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autosense_metzger_space.v 0000664 0000000 0000000 00000001146 13022141775 0024361 0 ustar 00root root 0000000 0000000 module x (/*AUTOARG*/
// Outputs
rmsk0, rmsk1, rmsk2,
// Inputs
endbyte0, endbyte1, endbyte2, strtbyte0, strtbyte1, strtbyte2
);
input endbyte0;
input endbyte1;
input endbyte2;
input strtbyte0;
input strtbyte1;
input strtbyte2;
output rmsk0;
output rmsk1;
output rmsk2;
always @ (/*AS*/endbyte0 or strtbyte0) rmsk0 = maskcalc(strtbyte0,endbyte0);
always @ (/*AS*/endbyte1 or strtbyte1) rmsk1 = maskcalc(strtbyte1,endbyte1);
always @ (/*AS*/endbyte2 or strtbyte2) rmsk2 = maskcalc(strtbyte2,endbyte2);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autosense_one.v 0000664 0000000 0000000 00000000022 13022141775 0022302 0 ustar 00root root 0000000 0000000 `define one 1'b1
verilog-mode-20161124.fd230e6/tests_ok/autosense_peers_func.v 0000664 0000000 0000000 00000002430 13022141775 0023657 0 ustar 00root root 0000000 0000000 module x;
always @(/*AUTOSENSE*/arb_select_f or octet_idx) begin
octet_flag[0] = |arb_select_f[ 7: 0];
octet_flag[1] = |arb_select_f[15: 8];
octet_flag[2] = |arb_select_f[23:16];
octet_flag[3] = |arb_select_f[31:24];
octet_flag[4] = |arb_select_f[39:32];
octet_flag[5] = |arb_select_f[47:40];
octet_flag[6] = |arb_select_f[55:48];
octet_flag[7] = |arb_select_f[63:56];
octet_available = |octet_flag;
shifted8_64 = barrel_shifter(octet_flag, octet_idx[5:3]);
end // always @ (arb_select_f)
endmodule
function [7:0] barrel_shifter;
input [7:0] source;
input [2:0] shift_amt;
begin
case (shift_amt) //synopsys parallel_case full_case
3'b0: barrel_shifter = source;
3'b1: barrel_shifter = {source[0], source[7:1]};
3'b2: barrel_shifter = {source[1:0], source[7:2]};
3'b3: barrel_shifter = {source[2:0], source[7:3]};
3'b4: barrel_shifter = {source[3:0], source[7:4]};
3'b5: barrel_shifter = {source[4:0], source[7:5]};
3'b6: barrel_shifter = {source[5:0], source[7:6]};
3'b7: barrel_shifter = {source[6:0], source[7]};
endcase // case(shift_amt)
end
endfunction // barrel_shifter
verilog-mode-20161124.fd230e6/tests_ok/autosense_rogoff.v 0000664 0000000 0000000 00000000206 13022141775 0023007 0 ustar 00root root 0000000 0000000
module x;
always @ (/*as*/a or ff)
case (a)
1: if (ff[3:0] == 4'd3)
sadfsdff;
endcase
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autosense_smith.v 0000664 0000000 0000000 00000004647 13022141775 0022666 0 ustar 00root root 0000000 0000000 module x;
reg [31:0] mb_reg_output;
// 16 registers max, register 15 is always the version number, so 15 are useable
// NOTE: number_interface_regs must be the maximum (or 16 in this case) to get the version register
parameter NUMBER_INTERFACE_REGS = 16;
parameter MB_REG_START = 3; // start at 4th register location 'h0010
parameter CMD_REG_0_ADDR = MB_REG_START;
parameter CMD_REG_1_ADDR = MB_REG_START+1;
parameter CMD_REG_2_ADDR = MB_REG_START+2;
parameter CMD_REG_3_ADDR = MB_REG_START+3;
parameter CMD_REG_4_ADDR = MB_REG_START+4;
parameter CMD_REG_5_ADDR = MB_REG_START+5;
parameter CMD_REG_6_ADDR = MB_REG_START+6;
parameter CMD_REG_7_ADDR = MB_REG_START+7;
parameter CMD_REG_8_ADDR = MB_REG_START+8;
parameter CMD_REG_9_ADDR = MB_REG_START+9;
parameter CMD_REG_10_ADDR = MB_REG_START+10;
// mode regs
parameter MODE_REG_0_ADDR = CMD_REG_8_ADDR;
// Absolute register 14 is Error counter
parameter CMD_REG_14_ADDR = 14;
parameter CRC_ERROR_REG_ADDR = CMD_REG_14_ADDR;
// ------------ VERSION register is 15
parameter VERSION_REG_ADDR = 15;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_wr;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_rd;
wire [31:0] mb_reg_out_w [NUMBER_INTERFACE_REGS-1:MB_REG_START];
wire [31:0] interface_from_core_fp;
assign
mb_reg_out_w[VERSION_REG_ADDR] = BUILD_VERSION;
integer mb_loop;
always @(/*AUTOSENSE*/ /*memory or*/ interface_from_core_fp or mb_reg_rwn or mb_reg_select)
begin: MB_READ_WRITE_SEL_P
mb_reg_wr = 'h0;
mb_reg_rd = 'h0;
mb_reg_output = interface_from_core_fp;
for(mb_loop = MB_REG_START; mb_loop < NUMBER_INTERFACE_REGS; mb_loop=mb_loop+1)
begin
if(mb_reg_select[mb_loop] == 1'b1)
begin
mb_reg_rd[mb_loop] = mb_reg_select[mb_loop] & mb_reg_rwn;
mb_reg_wr[mb_loop] = mb_reg_select[mb_loop] & !mb_reg_rwn;
mb_reg_output = mb_reg_out_w[mb_loop];
end
end
end
endmodule // x
verilog-mode-20161124.fd230e6/tests_ok/autosense_venkataramanan_begin.v 0000664 0000000 0000000 00000000601 13022141775 0025657 0 ustar 00root root 0000000 0000000
module autosense_venkataramanan_begin(/*AUTOARG*/);
reg a,b;
always @(/*AUTOSENSE*/b) // I didn't expect to get "i" in AUTOSENSE
begin : label
integer i, j;
for (i=0; i< = 3; i = i + 1)
vec[i] = b;
end
endmodule
// Local Variables:
// verilog-auto-sense-defines-constant: t
// verilog-auto-sense-include-inputs: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autotieoff_assign.v 0000664 0000000 0000000 00000001264 13022141775 0023155 0 ustar 00root root 0000000 0000000 module autotieoff_signed (/*AUTOARG*/
// Outputs
ExtraOut, SubOut, active_low_l, ignored_by_regexp
);
output [2:0] ExtraOut;
output [2:0] SubOut;
output [3:0] active_low_l;
output [3:0] ignored_by_regexp;
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
assign ExtraOut = 3'h0;
assign SubOut = 3'h0;
assign active_low_l = 4'h0;
assign ignored_by_regexp = 4'h0;
// End of automatics
endmodule
module sub;
input SubIn;
output SubOut;
endmodule
// Local Variables:
// verilog-auto-tieoff-declaration: "assign"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autotieoff_signed.v 0000664 0000000 0000000 00000004537 13022141775 0023150 0 ustar 00root root 0000000 0000000 module autotieoff_signed (/*AUTOARG*/
// Outputs
an_output2, an_outputpre, another_output, another_output2, ExtraOut, SubOut, active_low_l,
ignored_by_regexp,
// Inputs
ExtraIn, SubIn
);
input [2:0] ExtraIn;
input [2:0] SubIn;
output [2:0] ExtraOut;
output [2:0] SubOut;
output [3:0] active_low_l;
output [3:0] ignored_by_regexp;
/*AUTOINOUTMODULE("autoinst_signed")*/
// Beginning of automatic in/out/inouts (from specific module)
output [1:0] an_output2;
output signed [1:0] an_outputpre;
output signed [1:0] another_output;
output [1:0] another_output2;
// End of automatics
// =============================
// Auto Wires/Regs
// =============================
/*AUTOWIRE*/
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [3:0] ignored_by_regexp;
// End of automatics
// =============================
// Tieoffs
// =============================
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire [2:0] ExtraOut = 3'h0;
wire [3:0] active_low_l = ~4'h0;
wire [1:0] an_output2 = 2'h0;
wire signed [1:0] an_outputpre = 2'sh0;
wire signed [1:0] another_output = 2'sh0;
wire [1:0] another_output2 = 2'h0;
// End of automatics
// =============================
sub sub (/*AUTOINST*/
// Outputs
.SubOut (SubOut),
// Inputs
.SubIn (SubIn));
// =============================
// Unused signals
// =============================
// lint_checking SCX_UNUSED OFF
wire _unused_ok = &{1'b0,
/*AUTOUNUSED*/
// Beginning of automatic unused inputs
ExtraIn,
// End of automatics
1'b0 } ;
// lint_checking SCX_UNUSED OFF
endmodule
module sub;
input SubIn;
output SubOut;
endmodule
// Local Variables:
// verilog-active-low-regexp: "_l$"
// verilog-auto-tieoff-ignore-regexp: "ignored"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autoundef.v 0000664 0000000 0000000 00000001135 13022141775 0021433 0 ustar 00root root 0000000 0000000 // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module temp;
`define FOO(a)
`define BAR
`define BAZ
.....
`undef BAR
`define BAR
`define BAZ // AGAIN
/*AUTOUNDEF*/
// Beginning of automatic undefs
`undef BAR
`undef BAZ
`undef FOO
// End of automatics
// Make sure this list is empty
/*AUTOUNDEF*/
//======================================================================
`define M_A
`define X_B
/*AUTOUNDEF("^M_")*/
// Beginning of automatic undefs
`undef M_A
// End of automatics
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autounused.v 0000664 0000000 0000000 00000001777 13022141775 0021651 0 ustar 00root root 0000000 0000000 module wbuf
#(parameter width=1)
(output [width-1:0] q,
input [width-1:0] d);
endmodule
module autounused
#(parameter width=3)
(/*AUTOARG*/
// Outputs
q,
// Inputs
da, db, dc, dd
) ;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [width-1:0] q; // From wbuf of wbuf.v
// End of automatics
input da, db, dc, dd;
/*AUTOINPUT*/
wire _unused_ok = &{/*AUTOUNUSED*/
// Beginning of automatic unused inputs
dd,
// End of automatics
1'b0};
defparam partbuf.width = width;
wbuf wbuf
(// Inputs
.d ({da,db,dc}),
/*AUTOINST*/
// Outputs
.q (q[width-1:0]));
endmodule // abuf
// Local Variables:
// verilog-auto-unused-ignore-regexp: "^db$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autowire_godiwala.v 0000664 0000000 0000000 00000067642 13022141775 0023166 0 ustar 00root root 0000000 0000000 module FswArbiter (/*AUTOARG*/
// Outputs
xb_ecc_error_dbit, xb_ecc_error_1bit, insert_idle_ack, bp_performance_count, obx_xb0_GntPst_s3a,
obx_xb0_GntByp_s3a, obx_xb1_GntPst_s3a, obx_xb1_GntByp_s3a, obx_xb2_GntPst_s3a,
obx_xb2_GntByp_s3a, obx_xb3_GntPst_s3a, obx_xb3_GntByp_s3a, xbx_grant_cycle, bp1_grant_cycle,
set_arbitration_enable_d1, reset_ackbuf, wait_for_ack, ice9_databus,
// Inputs
sclk, lreset_l, csr_insert_idle, csr_arb_enable, csr_bypass3_enable, csr_bypass2_enable,
csr_bypass1_enable, csr_xb_ecc_enable, xb0_obx_ReqPst_s2a, xb0_obx_NextVc_s2a,
xb0_obx_NextPort_s2a, xb0_obx_NextXbe_s2a, xb0_obx_NextXbe_s3a, xb0_obx_OutDat_s4a,
xb0_obx_ReqBypS3_s2a, xb0_obx_ReqBypS2_s2a, xb1_obx_ReqPst_s2a, xb1_obx_NextVc_s2a,
xb1_obx_NextPort_s2a, xb1_obx_NextXbe_s2a, xb1_obx_NextXbe_s3a, xb1_obx_OutDat_s4a,
xb1_obx_ReqBypS3_s2a, xb1_obx_ReqBypS2_s2a, xb2_obx_ReqPst_s2a, xb2_obx_NextVc_s2a,
xb2_obx_NextPort_s2a, xb2_obx_NextXbe_s2a, xb2_obx_NextXbe_s3a, xb2_obx_OutDat_s4a,
xb2_obx_ReqBypS3_s2a, xb2_obx_ReqBypS2_s2a, xb3_obx_ReqPst_s2a, xb3_obx_NextVc_s2a,
xb3_obx_NextPort_s2a, xb3_obx_NextXbe_s2a, xb3_obx_NextXbe_s3a, xb3_obx_OutDat_s4a,
xb3_obx_ReqBypS3_s2a, xb3_obx_ReqBypS2_s2a, ib0_obx_PortSel_s1a, ib0_obx_InDat_s1a,
ib0_obx_NextPort_s1a, ib0_obx_NextVc_s1a, ib1_obx_PortSel_s1a, ib1_obx_InDat_s1a,
ib1_obx_NextPort_s1a, ib1_obx_NextVc_s1a, ib2_obx_PortSel_s1a, ib2_obx_InDat_s1a,
ib2_obx_NextPort_s1a, ib2_obx_NextVc_s1a, ib3_obx_PortSel_s1a, ib3_obx_InDat_s1a,
ib3_obx_NextPort_s1a, ib3_obx_NextVc_s1a, rp_is_full, rp_in_progress, rp_arb_poolmask,
rp_arb_bufbusy_mask
) ;
// ========================
// Include parameter File
// ========================
parameter DMAO = 0;
`include "chip_fsw_spec_param.v"
// ===============
// Physical Pins
// ===============
input sclk; // Fabric switch clock
input lreset_l;
input csr_insert_idle;
input csr_arb_enable;
input [3:0] csr_bypass3_enable;
input [3:0] csr_bypass2_enable;
input [3:0] csr_bypass1_enable;
input csr_xb_ecc_enable;
output [3:0] xb_ecc_error_dbit;
output [3:0] xb_ecc_error_1bit;
output insert_idle_ack;
output [2:0] bp_performance_count;
input xb0_obx_ReqPst_s2a;
input [3:0] xb0_obx_NextVc_s2a;
input [1:0] xb0_obx_NextPort_s2a;
input [3:0] xb0_obx_NextXbe_s2a;
input [3:0] xb0_obx_NextXbe_s3a;
input [71:0] xb0_obx_OutDat_s4a;
output obx_xb0_GntPst_s3a;
output obx_xb0_GntByp_s3a;
input xb0_obx_ReqBypS3_s2a;
input xb0_obx_ReqBypS2_s2a;
input xb1_obx_ReqPst_s2a;
input [3:0] xb1_obx_NextVc_s2a;
input [1:0] xb1_obx_NextPort_s2a;
input [3:0] xb1_obx_NextXbe_s2a;
input [3:0] xb1_obx_NextXbe_s3a;
input [71:0] xb1_obx_OutDat_s4a;
output obx_xb1_GntPst_s3a;
output obx_xb1_GntByp_s3a;
input xb1_obx_ReqBypS3_s2a;
input xb1_obx_ReqBypS2_s2a;
input xb2_obx_ReqPst_s2a;
input [3:0] xb2_obx_NextVc_s2a;
input [1:0] xb2_obx_NextPort_s2a;
input [3:0] xb2_obx_NextXbe_s2a;
input [3:0] xb2_obx_NextXbe_s3a;
input [71:0] xb2_obx_OutDat_s4a;
output obx_xb2_GntPst_s3a;
output obx_xb2_GntByp_s3a;
input xb2_obx_ReqBypS3_s2a;
input xb2_obx_ReqBypS2_s2a;
input xb3_obx_ReqPst_s2a;
input [3:0] xb3_obx_NextVc_s2a;
input [1:0] xb3_obx_NextPort_s2a;
input [3:0] xb3_obx_NextXbe_s2a;
input [3:0] xb3_obx_NextXbe_s3a;
input [71:0] xb3_obx_OutDat_s4a;
output obx_xb3_GntPst_s3a;
output obx_xb3_GntByp_s3a;
input xb3_obx_ReqBypS3_s2a;
input xb3_obx_ReqBypS2_s2a;
input ib0_obx_PortSel_s1a;
input [63:0] ib0_obx_InDat_s1a;
input [1:0] ib0_obx_NextPort_s1a;
input [3:0] ib0_obx_NextVc_s1a;
input ib1_obx_PortSel_s1a;
input [63:0] ib1_obx_InDat_s1a;
input [1:0] ib1_obx_NextPort_s1a;
input [3:0] ib1_obx_NextVc_s1a;
input ib2_obx_PortSel_s1a;
input [63:0] ib2_obx_InDat_s1a;
input [1:0] ib2_obx_NextPort_s1a;
input [3:0] ib2_obx_NextVc_s1a;
input ib3_obx_PortSel_s1a;
input [63:0] ib3_obx_InDat_s1a;
input [1:0] ib3_obx_NextPort_s1a;
input [3:0] ib3_obx_NextVc_s1a;
input rp_is_full;
input rp_in_progress;
input [15:0] rp_arb_poolmask;
input [63:0] rp_arb_bufbusy_mask;
output xbx_grant_cycle;
output bp1_grant_cycle;
output set_arbitration_enable_d1;
output [63:0] reset_ackbuf;
output [63:0] wait_for_ack;
output [63:0] ice9_databus;
// =============================
// Auto Wires/Regs
// =============================
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire bp1_grant0; // From bp1 of FswBypassArbiter.v
wire bp1_grant1; // From bp1 of FswBypassArbiter.v
wire bp1_grant2; // From bp1 of FswBypassArbiter.v
wire bp1_grant3; // From bp1 of FswBypassArbiter.v
wire bp1_grant_cycle_d1; // From bp1 of FswBypassArbiter.v
wire bp1_grant_cycle_d2; // From bp1 of FswBypassArbiter.v
wire bp1_header; // From bp1 of FswBypassArbiter.v
wire bp1_header_d1; // From bp1 of FswBypassArbiter.v
wire bp1_header_d2; // From bp1 of FswBypassArbiter.v
wire [5:0] bp1_hold_wait_vector; // From bp1 of FswBypassArbiter.v
wire [5:0] bp1_hold_wait_vector_d1;// From bp1 of FswBypassArbiter.v
wire [1:0] bp1_next_winner; // From bp1 of FswBypassArbiter.v
wire [1:0] bp1_next_winner_d1; // From bp1 of FswBypassArbiter.v
wire [1:0] bp1_next_winner_d2; // From bp1 of FswBypassArbiter.v
wire [3:0] bp1_nextxbe; // From bp1 of FswBypassArbiter.v
wire [3:0] bp1_nextxbe_d1; // From bp1 of FswBypassArbiter.v
wire [3:0] bp1_nextxbe_d2; // From bp1 of FswBypassArbiter.v
wire bp1_select; // From bp1 of FswBypassArbiter.v
wire bp1_select_d1; // From bp1 of FswBypassArbiter.v
wire bp1_select_d2; // From bp1 of FswBypassArbiter.v
wire bp2_grant0; // From bp2 of FswBypassArbiter.v
wire bp2_grant1; // From bp2 of FswBypassArbiter.v
wire bp2_grant2; // From bp2 of FswBypassArbiter.v
wire bp2_grant3; // From bp2 of FswBypassArbiter.v
wire bp2_grant_cycle; // From bp2 of FswBypassArbiter.v
wire bp2_grant_cycle_d1; // From bp2 of FswBypassArbiter.v
wire bp2_grant_cycle_d2; // From bp2 of FswBypassArbiter.v
wire bp2_header; // From bp2 of FswBypassArbiter.v
wire bp2_header_d1; // From bp2 of FswBypassArbiter.v
wire bp2_header_d2; // From bp2 of FswBypassArbiter.v
wire [5:0] bp2_hold_wait_vector; // From bp2 of FswBypassArbiter.v
wire [5:0] bp2_hold_wait_vector_d1;// From bp2 of FswBypassArbiter.v
wire [1:0] bp2_next_winner; // From bp2 of FswBypassArbiter.v
wire [1:0] bp2_next_winner_d1; // From bp2 of FswBypassArbiter.v
wire [1:0] bp2_next_winner_d2; // From bp2 of FswBypassArbiter.v
wire [3:0] bp2_nextxbe; // From bp2 of FswBypassArbiter.v
wire [3:0] bp2_nextxbe_d1; // From bp2 of FswBypassArbiter.v
wire [3:0] bp2_nextxbe_d2; // From bp2 of FswBypassArbiter.v
wire bp2_select; // From bp2 of FswBypassArbiter.v
wire bp2_select_d1; // From bp2 of FswBypassArbiter.v
wire bp2_select_d2; // From bp2 of FswBypassArbiter.v
wire bp3_grant0; // From bp3 of FswBypassArbiter.v
wire bp3_grant1; // From bp3 of FswBypassArbiter.v
wire bp3_grant2; // From bp3 of FswBypassArbiter.v
wire bp3_grant3; // From bp3 of FswBypassArbiter.v
wire bp3_grant_cycle; // From bp3 of FswBypassArbiter.v
wire bp3_grant_cycle_d1; // From bp3 of FswBypassArbiter.v
wire bp3_grant_cycle_d2; // From bp3 of FswBypassArbiter.v
wire bp3_header; // From bp3 of FswBypassArbiter.v
wire bp3_header_d1; // From bp3 of FswBypassArbiter.v
wire bp3_header_d2; // From bp3 of FswBypassArbiter.v
wire [5:0] bp3_hold_wait_vector; // From bp3 of FswBypassArbiter.v
wire [5:0] bp3_hold_wait_vector_d1;// From bp3 of FswBypassArbiter.v
wire [1:0] bp3_next_winner; // From bp3 of FswBypassArbiter.v
wire [1:0] bp3_next_winner_d1; // From bp3 of FswBypassArbiter.v
wire [1:0] bp3_next_winner_d2; // From bp3 of FswBypassArbiter.v
wire [3:0] bp3_nextxbe; // From bp3 of FswBypassArbiter.v
wire [3:0] bp3_nextxbe_d1; // From bp3 of FswBypassArbiter.v
wire [3:0] bp3_nextxbe_d2; // From bp3 of FswBypassArbiter.v
wire bp3_select; // From bp3 of FswBypassArbiter.v
wire bp3_select_d1; // From bp3 of FswBypassArbiter.v
wire bp3_select_d2; // From bp3 of FswBypassArbiter.v
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0] bp_performance_count;
reg [63:0] ice9_databus;
reg insert_idle_ack;
reg obx_xb0_GntByp_s3a;
reg obx_xb0_GntPst_s3a;
reg obx_xb1_GntByp_s3a;
reg obx_xb1_GntPst_s3a;
reg obx_xb2_GntByp_s3a;
reg obx_xb2_GntPst_s3a;
reg obx_xb3_GntByp_s3a;
reg obx_xb3_GntPst_s3a;
reg [63:0] reset_ackbuf;
reg set_arbitration_enable_d1;
reg [63:0] wait_for_ack;
reg [3:0] xb_ecc_error_1bit;
reg [3:0] xb_ecc_error_dbit;
reg xbx_grant_cycle;
// End of automatics
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp3_enable_3),
.sop2 (sop2 & xbx_bp3_enable_2),
.sop1 (sop1 & xbx_bp3_enable_1),
.sop0 (sop0 & xbx_bp3_enable_0),
); */
FswBypassArbiter bp3 (/*AUTOINST*/
// Outputs
.bp_grant3 (bp3_grant3), // Templated
.bp_grant2 (bp3_grant2), // Templated
.bp_grant1 (bp3_grant1), // Templated
.bp_grant0 (bp3_grant0), // Templated
.bp_grant_cycle (bp3_grant_cycle), // Templated
.bp_grant_cycle_d1 (bp3_grant_cycle_d1), // Templated
.bp_grant_cycle_d2 (bp3_grant_cycle_d2), // Templated
.bp_next_winner (bp3_next_winner[1:0]), // Templated
.bp_next_winner_d1 (bp3_next_winner_d1[1:0]), // Templated
.bp_next_winner_d2 (bp3_next_winner_d2[1:0]), // Templated
.bp_nextxbe (bp3_nextxbe[3:0]), // Templated
.bp_nextxbe_d1 (bp3_nextxbe_d1[3:0]), // Templated
.bp_nextxbe_d2 (bp3_nextxbe_d2[3:0]), // Templated
.bp_hold_wait_vector (bp3_hold_wait_vector[5:0]), // Templated
.bp_hold_wait_vector_d1(bp3_hold_wait_vector_d1[5:0]), // Templated
.bp_header (bp3_header), // Templated
.bp_header_d1 (bp3_header_d1), // Templated
.bp_header_d2 (bp3_header_d2), // Templated
.bp_select (bp3_select), // Templated
.bp_select_d1 (bp3_select_d1), // Templated
.bp_select_d2 (bp3_select_d2), // Templated
// Inputs
.lreset_l (bp3_lreset_l), // Templated
.sclk (sclk),
.bp_arb_enable (bp3_arb_enable), // Templated
.sop3 (sop3 & xbx_bp3_enable_3), // Templated
.sop3_data (sop3_data[63:0]),
.sop3_bpcontext (sop3_bpcontext[5:0]),
.sop2 (sop2 & xbx_bp3_enable_2), // Templated
.sop2_data (sop2_data[63:0]),
.sop2_bpcontext (sop2_bpcontext[5:0]),
.sop1 (sop1 & xbx_bp3_enable_1), // Templated
.sop1_data (sop1_data[63:0]),
.sop1_bpcontext (sop1_bpcontext[5:0]),
.sop0 (sop0 & xbx_bp3_enable_0), // Templated
.sop0_data (sop0_data[63:0]),
.sop0_bpcontext (sop0_bpcontext[5:0]),
.poolmask (poolmask[15:0]),
.bufbusy_mask (bufbusy_mask[63:0]));
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp2_enable_3),
.sop2 (sop2 & xbx_bp2_enable_2),
.sop1 (sop1 & xbx_bp2_enable_1),
.sop0 (sop0 & xbx_bp2_enable_0),
); */
FswBypassArbiter bp2 (/*AUTOINST*/
// Outputs
.bp_grant3 (bp2_grant3), // Templated
.bp_grant2 (bp2_grant2), // Templated
.bp_grant1 (bp2_grant1), // Templated
.bp_grant0 (bp2_grant0), // Templated
.bp_grant_cycle (bp2_grant_cycle), // Templated
.bp_grant_cycle_d1 (bp2_grant_cycle_d1), // Templated
.bp_grant_cycle_d2 (bp2_grant_cycle_d2), // Templated
.bp_next_winner (bp2_next_winner[1:0]), // Templated
.bp_next_winner_d1 (bp2_next_winner_d1[1:0]), // Templated
.bp_next_winner_d2 (bp2_next_winner_d2[1:0]), // Templated
.bp_nextxbe (bp2_nextxbe[3:0]), // Templated
.bp_nextxbe_d1 (bp2_nextxbe_d1[3:0]), // Templated
.bp_nextxbe_d2 (bp2_nextxbe_d2[3:0]), // Templated
.bp_hold_wait_vector (bp2_hold_wait_vector[5:0]), // Templated
.bp_hold_wait_vector_d1(bp2_hold_wait_vector_d1[5:0]), // Templated
.bp_header (bp2_header), // Templated
.bp_header_d1 (bp2_header_d1), // Templated
.bp_header_d2 (bp2_header_d2), // Templated
.bp_select (bp2_select), // Templated
.bp_select_d1 (bp2_select_d1), // Templated
.bp_select_d2 (bp2_select_d2), // Templated
// Inputs
.lreset_l (bp2_lreset_l), // Templated
.sclk (sclk),
.bp_arb_enable (bp2_arb_enable), // Templated
.sop3 (sop3 & xbx_bp2_enable_3), // Templated
.sop3_data (sop3_data[63:0]),
.sop3_bpcontext (sop3_bpcontext[5:0]),
.sop2 (sop2 & xbx_bp2_enable_2), // Templated
.sop2_data (sop2_data[63:0]),
.sop2_bpcontext (sop2_bpcontext[5:0]),
.sop1 (sop1 & xbx_bp2_enable_1), // Templated
.sop1_data (sop1_data[63:0]),
.sop1_bpcontext (sop1_bpcontext[5:0]),
.sop0 (sop0 & xbx_bp2_enable_0), // Templated
.sop0_data (sop0_data[63:0]),
.sop0_bpcontext (sop0_bpcontext[5:0]),
.poolmask (poolmask[15:0]),
.bufbusy_mask (bufbusy_mask[63:0]));
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & csr_bp1_enable_3),
.sop2 (sop2 & csr_bp1_enable_2),
.sop1 (sop1 & csr_bp1_enable_1),
.sop0 (sop0 & csr_bp1_enable_0),
); */
FswBypassArbiter bp1 (/*AUTOINST*/
// Outputs
.bp_grant3 (bp1_grant3), // Templated
.bp_grant2 (bp1_grant2), // Templated
.bp_grant1 (bp1_grant1), // Templated
.bp_grant0 (bp1_grant0), // Templated
.bp_grant_cycle (bp1_grant_cycle), // Templated
.bp_grant_cycle_d1 (bp1_grant_cycle_d1), // Templated
.bp_grant_cycle_d2 (bp1_grant_cycle_d2), // Templated
.bp_next_winner (bp1_next_winner[1:0]), // Templated
.bp_next_winner_d1 (bp1_next_winner_d1[1:0]), // Templated
.bp_next_winner_d2 (bp1_next_winner_d2[1:0]), // Templated
.bp_nextxbe (bp1_nextxbe[3:0]), // Templated
.bp_nextxbe_d1 (bp1_nextxbe_d1[3:0]), // Templated
.bp_nextxbe_d2 (bp1_nextxbe_d2[3:0]), // Templated
.bp_hold_wait_vector (bp1_hold_wait_vector[5:0]), // Templated
.bp_hold_wait_vector_d1(bp1_hold_wait_vector_d1[5:0]), // Templated
.bp_header (bp1_header), // Templated
.bp_header_d1 (bp1_header_d1), // Templated
.bp_header_d2 (bp1_header_d2), // Templated
.bp_select (bp1_select), // Templated
.bp_select_d1 (bp1_select_d1), // Templated
.bp_select_d2 (bp1_select_d2), // Templated
// Inputs
.lreset_l (bp1_lreset_l), // Templated
.sclk (sclk),
.bp_arb_enable (bp1_arb_enable), // Templated
.sop3 (sop3 & csr_bp1_enable_3), // Templated
.sop3_data (sop3_data[63:0]),
.sop3_bpcontext (sop3_bpcontext[5:0]),
.sop2 (sop2 & csr_bp1_enable_2), // Templated
.sop2_data (sop2_data[63:0]),
.sop2_bpcontext (sop2_bpcontext[5:0]),
.sop1 (sop1 & csr_bp1_enable_1), // Templated
.sop1_data (sop1_data[63:0]),
.sop1_bpcontext (sop1_bpcontext[5:0]),
.sop0 (sop0 & csr_bp1_enable_0), // Templated
.sop0_data (sop0_data[63:0]),
.sop0_bpcontext (sop0_bpcontext[5:0]),
.poolmask (poolmask[15:0]),
.bufbusy_mask (bufbusy_mask[63:0]));
// =======================================
// Coverage
// =======================================
// psl default clock = negedge sclk;
generate if (DMAO == 0)
begin
// psl cover {lreset_l & (bp1_grant0 |bp1_grant1 |bp1_grant2 |bp1_grant3 )} report "FswPerfRtl::byp1Taken";
// psl cover {lreset_l & (bp2_grant0 |bp2_grant1 |bp2_grant2 |bp2_grant3)} report "FswPerfRtl::byp2Taken";
// psl cover {lreset_l & (bp3_grant0 |bp3_grant1 |bp3_grant2 |bp3_grant3)} report "FswPerfRtl::byp3Taken";
end
endgenerate
// ================
// Unused signals
// ================
// lint_checking SCX_UNUSED off
wire _unused_ok = &{1'b0,
bp_select,
bp3_hold_wait_vector,
bp2_hold_wait_vector_d1,
bp1_hold_wait_vector_d1,
bp3_header,
bp3_header_d1,
bp3_select,
bp3_select_d1,
bp3_next_winner[1:0],
bp3_next_winner_d1[1:0],
bp3_nextxbe[3:0],
bp3_nextxbe_d1[3:0],
bp2_grant_cycle_d2,
bp2_header,
bp2_header_d2,
bp2_select,
bp2_select_d2,
bp2_next_winner[1:0],
bp2_next_winner_d2[1:0],
bp2_nextxbe[3:0],
bp2_nextxbe_d2[3:0],
bp1_header_d1,
bp1_header_d2,
bp1_select_d1,
bp1_select_d2,
bp1_next_winner_d1[1:0],
bp1_next_winner_d2[1:0],
bp1_nextxbe_d1[3:0],
bp1_nextxbe_d2[3:0],
xb0_obx_NextXbe_s3a, // This is unused signal now.
xb1_obx_NextXbe_s3a,
xb2_obx_NextXbe_s3a,
xb3_obx_NextXbe_s3a,
syn64,
dataout64,
1'b0
};
// lint_checking SCX_UNUSED on
endmodule
module FswBypassArbiter (/*AUTOARG*/
// Outputs
bp_grant3, bp_grant2, bp_grant1, bp_grant0, bp_grant_cycle, bp_grant_cycle_d1, bp_grant_cycle_d2,
bp_next_winner, bp_next_winner_d1, bp_next_winner_d2, bp_nextxbe, bp_nextxbe_d1, bp_nextxbe_d2,
bp_hold_wait_vector, bp_hold_wait_vector_d1, bp_header, bp_header_d1, bp_header_d2, bp_select,
bp_select_d1, bp_select_d2,
// Inputs
lreset_l, sclk, bp_arb_enable, sop3, sop3_data, sop3_bpcontext, sop2, sop2_data, sop2_bpcontext,
sop1, sop1_data, sop1_bpcontext, sop0, sop0_data, sop0_bpcontext, poolmask, bufbusy_mask
) ;
input lreset_l;
input sclk;
input bp_arb_enable;
output bp_grant3;
output bp_grant2;
output bp_grant1;
output bp_grant0;
output bp_grant_cycle;
output bp_grant_cycle_d1;
output bp_grant_cycle_d2;
output [1:0] bp_next_winner;
output [1:0] bp_next_winner_d1;
output [1:0] bp_next_winner_d2;
output [3:0] bp_nextxbe;
output [3:0] bp_nextxbe_d1;
output [3:0] bp_nextxbe_d2;
output [5:0] bp_hold_wait_vector;
output [5:0] bp_hold_wait_vector_d1;
output bp_header;
output bp_header_d1;
output bp_header_d2;
output bp_select;
output bp_select_d1;
output bp_select_d2;
input sop3;
input [63:0] sop3_data;
input [5:0] sop3_bpcontext;
input sop2;
input [63:0] sop2_data;
input [5:0] sop2_bpcontext;
input sop1;
input [63:0] sop1_data;
input [5:0] sop1_bpcontext;
input sop0;
input [63:0] sop0_data;
input [5:0] sop0_bpcontext;
input [15:0] poolmask;
input [63:0] bufbusy_mask;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autowire_import_bug317.v 0000664 0000000 0000000 00000002154 13022141775 0023764 0 ustar 00root root 0000000 0000000 package pkg;
typedef logic [1:0] my_type;
endpackage
module top;
import pkg::*;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pkg::my_type_t a; // From sub_2 of sub_2.v
pkg::my_type_t z; // From sub_1 of sub_1.v
// End of automatics
sub_1 sub_1 (.*,
// Outputs
.z (z), // Implicit .*
// Inputs
.a (a)); // Implicit .*
sub_2 sub_2 (.*,
// Outputs
.a (a), // Implicit .*
// Inputs
.z (z)); // Implicit .*
endmodule
module sub_1
import pkg::*; // bug317
(
input pkg::my_type_t a,
output pkg::my_type_t z
);
endmodule
module sub_2
(
input pkg::my_type_t z,
output pkg::my_type_t a
);
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// verilog-auto-star-save: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autowire_isaacson.v 0000664 0000000 0000000 00000002662 13022141775 0023166 0 ustar 00root root 0000000 0000000 module t;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire w11; // From bp3 of FswBypassArbiter.v
wire w12; // From bp3 of FswBypassArbiter.v
// End of automatics
/*AUTOREG*/
wand w0;
wor w1;
tri0 w2;
tri1 w3;
triand w4;
trior w5;
trireg w6;
tri w7;
wire w8;
supply0 w9;
supply1 w10;
FswBypassArbiter bp3 (/*AUTOINST*/
// Outputs
.w0 (w0),
.w1 (w1),
.w2 (w2),
.w3 (w3),
.w4 (w4),
.w5 (w5),
.w6 (w6),
.w7 (w7),
.w8 (w8),
.w9 (w9),
.w10 (w10),
.w11 (w11),
.w12 (w12));
endmodule
module FswBypassArbiter (/*AUTOARG*/
// Outputs
w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12
) ;
output w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autowire_long_yaohung.v 0000664 0000000 0000000 00000001327 13022141775 0024054 0 ustar 00root root 0000000 0000000 module autowire_long_yaohung(/*AUTOARG*/
// Outputs
data_out
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [`LONGNAMELONGNAMELONGNAMELONGNAMELONGNAMELONGNAME] data_out;// From top of top.v
// End of automatics
/*AUTOWIRE*/
/*AUTOREG*/
top top
(/*AUTOINST*/
// Outputs
.data_out (data_out[`LONGNAMELONGNAMELONGNAMELONGNAMELONGNAMELONGNAME]));
endmodule
module top(/*AUTOARG*/
// Outputs
data_out
);
output [`LONGNAMELONGNAMELONGNAMELONGNAMELONGNAMELONGNAME] data_out;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autowire_lovell_hiear.v 0000664 0000000 0000000 00000001525 13022141775 0024030 0 ustar 00root root 0000000 0000000 module foo
(/*AUTOARG*/
// Outputs
another_output2
);
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output [1:0] another_output2; // From inst of autoinst_signed_fubar2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] another_output2; // From inst of autoinst_signed_fubar2.v
// End of automatics
/* autoinst_signed_fubar2 AUTO_TEMPLATE (
.an_output2 (hi.ear.ial),
);
*/
autoinst_signed_fubar2 inst
(
/*AUTOINST*/
// Outputs
.an_output2 (hi.ear.ial), // Templated
.another_output2 (another_output2[1:0]),
// Inputs
.an_input2 (an_input2[1:0]));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autowire_merge_bug303.v 0000664 0000000 0000000 00000002052 13022141775 0023541 0 ustar 00root root 0000000 0000000 module TOP (/*AUTOARG*/
// Outputs
SIG_NAMEB, SIG_NAMEA
)
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [223:0] SIG_NAMEA; // From A of A.v, ...
output [FOO*4-2:0] SIG_NAMEB; // From C of C.v
// End of automatics
/*AUTOINPUT*/
/*AUTOWIRE*/
A A(/*AUTOINST*/
// Outputs
.SIG_NAMEA (SIG_NAMEA[224*1-1:128*1]));
B B(/*AUTOINST*/
// Outputs
.SIG_NAMEA (SIG_NAMEA[127:0]));
C C(/*AUTOINST*/
// Outputs
.SIG_NAMEB (SIG_NAMEB[FOO*4-2*1:0]));
endmodule
module A(/*AUTOARG*/
// Outputs
SIG_NAMEA
);
output [224*1-1:128*1] SIG_NAMEA;
//output [223:128] SIG_NAMEA;
endmodule
module B(/*AUTOARG*/
// Outputs
SIG_NAMEA
);
output [127:0] SIG_NAMEA;
endmodule
module C(/*AUTOARG*/
// Outputs
SIG_NAMEB
);
output [FOO*4-2*1:0] SIG_NAMEB;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autowire_misalias_bug295.v 0000664 0000000 0000000 00000002103 13022141775 0024253 0 ustar 00root root 0000000 0000000 interface my_interface ();
logic [2:0] out2;
logic [2:0] out3;
endinterface: my_interface
module foobar (input [2:0] in2, output [2:0] out2);
endmodule
module foo_autowire_fails (my_interface itf);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] out2; // From foobar0 of foobar.v
// End of automatics
assign itf.out2 = out2; // perhaps a namespace collision?
foobar foobar0
(/*AUTOINST*/
// Outputs
.out2 (out2[2:0]),
// Inputs
.in2 (in2[2:0]));
endmodule
module foo_autowire_works (my_interface itf);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] out2; // From foobar0 of foobar.v
// End of automatics
assign itf.out3 = out2;
foobar foobar0
(/*AUTOINST*/
// Outputs
.out2 (out2[2:0]),
// Inputs
.in2 (in2[2:0]));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autowire_myers.v 0000664 0000000 0000000 00000001172 13022141775 0022520 0 ustar 00root root 0000000 0000000 module test1 ( wireA, wireB );
output [3:0] wireA;
output [16:0] wireB;
endmodule
module test_top;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] wireA; // From t1 of test1.v
wire [16:0] wireB; // From t1 of test1.v
// End of automatics
generate
if (1) begin
test1 t1 (/*AUTOINST*/
// Outputs
.wireA (wireA[3:0]),
.wireB (wireB[16:0]));
end
else begin
assign wireA = 0;
end
endgenerate
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autowire_nocomment.v 0000664 0000000 0000000 00000001553 13022141775 0023363 0 ustar 00root root 0000000 0000000 module top;
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output logic out1a;
output logic [1:0] out1b;
// End of automatics
/*AUTOREG*/
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic out1a;
logic [1:0] out1b;
// End of automatics
sub2 isub2 (/*AUTOINST*/
// Outputs
.out1a (out1a),
.out1b (out1b[1:0]),
// Inputs
.in1a (in1a),
.in1b (in1b));
endmodule
module sub2
( input logic in1a,
input logic in1b,
output logic out1a,
output logic [1:0] out1b
);
endmodule
// Local Variables:
// verilog-auto-wire-comment: nil
// End:
verilog-mode-20161124.fd230e6/tests_ok/autowire_paramvec_bug302.v 0000664 0000000 0000000 00000002703 13022141775 0024242 0 ustar 00root root 0000000 0000000 module Abc_TEST ();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [5:0] [31:0] abc; // From u_Def of Def.v
// End of automatics
Abc #(
.No1 (6),
/*AUTOINSTPARAM*/
// Parameters
.No2 (No2),
.No3 (No3/*.[No1:0][No2-1:0]*/)) u_Abc
(
/*AUTOINST*/
// Inputs
.ck (ck),
.abc (abc/*[5:0][31:0]*/));
Def #(
.No1 (6)) u_Def
(
// Outputs
.ck (ck),
/*AUTOINST*/
// Outputs
.abc (abc/*[5:0][31:0]*/));
endmodule
module Abc
#(
parameter No1 = 6,
parameter int unsigned No2 // Parameter no. 2
= pa_Abc::No2,
parameter bit No3 [No1:0][No2-1:0] // Parameter no. 3
= pa_Abc::No3
)
(
input logic ck,
input logic [No1-1:0][31:0] abc
input logic [No1-1:0][31:0] abc
);
endmodule
module Def
#(
parameter No1 = 6
)
(
input logic ck,
output logic [No1-1:0][31:0] abc
);
endmodule
// Local Variables:
// verilog-library-extensions:(".v" ".sv")
// verilog-auto-inst-param-value:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autowire_pkg_bug195.v 0000664 0000000 0000000 00000004475 13022141775 0023247 0 ustar 00root root 0000000 0000000 `default_nettype none
package testcase_pkg;
typedef int unsigned uint;
localparam uint SIZE = 8;
typedef enum {ENUM1, ENUM2} enum_t;
endpackage
module testcase_top
(
input testcase_pkg::enum_t top_enum,
input logic [testcase_pkg::SIZE-1:0] top_in,
output logic [testcase_pkg::SIZE-1:0] top_out
);
import testcase_pkg::*;
//enum_t sub_enum; // is not declared by AUTOWIRE
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
testcase_pkg::enum_t sub_enum; // From testcase_sub1 of testcase_sub1.v
logic [testcase_pkg::SIZE-1:0] sub_in; // From testcase_sub1 of testcase_sub1.v
logic [testcase_pkg::SIZE-1:0] sub_out; // From testcase_sub2 of testcase_sub2.v
// End of automatics
assign top_out = sub_out;
testcase_sub1 testcase_sub1 (.*,
// Outputs
.sub_enum (sub_enum), // Implicit .*
.sub_in (sub_in[testcase_pkg::SIZE-1:0]), // Implicit .*
// Inputs
.top_enum (top_enum)); // Implicit .*
testcase_sub2 testcase_sub2 (.*,
// Outputs
.sub_out (sub_out[testcase_pkg::SIZE-1:0]), // Implicit .*
// Inputs
.sub_enum (sub_enum), // Implicit .*
.sub_in (sub_in[testcase_pkg::SIZE-1:0])); // Implicit .*
endmodule
module testcase_sub1
(
input testcase_pkg::enum_t top_enum,
output testcase_pkg::enum_t sub_enum,
output logic [testcase_pkg::SIZE-1:0] sub_in
);
import testcase_pkg::*;
assign sub_enum = top_enum;
assign sub_in = '1;
endmodule
module testcase_sub2
(
input testcase_pkg::enum_t sub_enum,
input logic [testcase_pkg::SIZE-1:0] sub_in,
output logic [testcase_pkg::SIZE-1:0] sub_out
);
import testcase_pkg::*;
assign sub_out = (sub_enum==ENUM1) ? ~sub_in : sub_in;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// verilog-auto-star-save: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/autowire_real.v 0000664 0000000 0000000 00000003067 13022141775 0022311 0 ustar 00root root 0000000 0000000 module sc_top (
input var real Tx_vcm,
input var real i_DAC_in,
input i_Tx_SC_en,
output var real Tx_vsc
);
endmodule
module cm_top (
input i_Tx_CM_en,
output var real Tx_vcm
);
endmodule
module top (
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output real Tx_vsc, // From sc_buf of sc_top.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input real i_DAC_in, // To sc_buf of sc_top.v
input i_Tx_CM_en, // To cm_buf of cm_top.v
input i_Tx_SC_en // To sc_buf of sc_top.v
// End of automatics
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
real Tx_vcm; // From cm_buf of cm_top.v
// End of automatics
cm_top cm_buf (/*AUTOINST*/
// Outputs
.Tx_vcm (Tx_vcm),
// Inputs
.i_Tx_CM_en (i_Tx_CM_en));
sc_top sc_buf (/*AUTOINST*/
// Outputs
.Tx_vsc (Tx_vsc),
// Inputs
.Tx_vcm (Tx_vcm),
.i_DAC_in (i_DAC_in),
.i_Tx_SC_en (i_Tx_SC_en));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autowire_req.v 0000664 0000000 0000000 00000000753 13022141775 0022154 0 ustar 00root root 0000000 0000000
module autowire_req ();
reqcmd_t AReq;
reqcmd_t BReq;
/*AUTOWIRE*/
autowire_req_sw autowire_req_sw (/*AUTOINST*/
// Outputs
.BReq (BReq),
// Inputs
.AReq (AReq));
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-typedef-regexp:"_t$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autowire_req_sw.v 0000664 0000000 0000000 00000000417 13022141775 0022662 0 ustar 00root root 0000000 0000000 `include "pf_sc.vh"
module autowire_req_sw
(
input reqcmd_t AReq,
output reqcmd_t BReq
/*AUTOINPUT*/
);
assign Bnk0Req = Cpu0Req;
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-typedef-regexp:"_t$"
// End:
verilog-mode-20161124.fd230e6/tests_ok/autowire_thon_selects.v 0000664 0000000 0000000 00000002104 13022141775 0024047 0 ustar 00root root 0000000 0000000 module foo
(/*AUTOARG*/
// Outputs
aa
);
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output [Y:X] aa; // From inst of autoinst_signed_fubar2.v, ..., Couldn't Merge
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [Y:X] aa; // From inst of autoinst_signed_fubar2.v, ..., Couldn't Merge
// End of automatics
// Check that if aa is connected differently in a input, it doesn't make conflicts.
autoinst_signed_fubar2 inst
(
// Outputs
.an_output2 (hi.ear.ial),
.another_output2 (aa[FOO:0]),
// Inputs
.an_input2 (an_input2[1:0])
/*AUTOINST*/);
autoinst_signed_fubar2 instx
(
// Outputs
.an_output2 (hi.ear.ial),
// Inputs
.an_input2 (an_input2[1:0]),
.another_output2 (aa[Y:X]),
/*AUTOINST*/);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/autowire_totte.v 0000664 0000000 0000000 00000003122 13022141775 0022515 0 ustar 00root root 0000000 0000000 module test1 ( wire2, wire4 );
output [3:0] wire2;
output [16:0] wire4;
endmodule
module test2 ( wire6, wire12 );
input [3:0] wire6;
input [16:0] wire12;
endmodule
module test3 ( wireA, wireB );
input [3:0] wireA;
input [16:0] wireB;
endmodule
module test4 ( wireA, wireB );
output [3:0] wireA;
output [16:0] wireB;
endmodule
module test_top;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] wireA; // From t4 of test4.v
wire [16:0] wireB; // From t4 of test4.v
wire [3:0] wire_2_to_6; // From t1 of test1.v
wire [16:0] wire_4_to_12; // From t1 of test1.v
// End of automatics
/* test1 AUTO_TEMPLATE (
.wire@(wire_\1_to_@"(* \1 3)"[]),
); */
test1 t1 (/*AUTOINST*/
// Outputs
.wire2 (wire_2_to_6[3:0]), // Templated
.wire4 (wire_4_to_12[16:0])); // Templated
/* test2 AUTO_TEMPLATE (
.wire@(wire@"(/ \1 3)"_to_\1[]),
); */
test2 t2 (/*AUTOINST*/
// Inputs
.wire6 (wire2_to_6[3:0]), // Templated
.wire12 (wire4_to_12[16:0])); // Templated
test3 t3 (/*AUTOINST*/
// Inputs
.wireA (wireA[3:0]),
.wireB (wireB[16:0]));
test4 t4 (/*AUTOINST*/
// Outputs
.wireA (wireA[3:0]),
.wireB (wireB[16:0]));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/batch_li_child.v 0000664 0000000 0000000 00000000701 13022141775 0022347 0 ustar 00root root 0000000 0000000 module batch_li_child
#(parameter
WIDTH_0= 'h8,
WIDTH_1 = 'h4
)
(
input rst,
input clk
);
reg [WIDTH_0-1:0] counter_0;
reg [WIDTH_1-1:0] counter_1;
always @(posedge clk) begin
if (rst) begin
counter_0 <= #1 0;
counter_1 <= #1 0;
end
else begin
counter_0 <= #1 counter_0 + 1'b1;
counter_1 <= #1 counter_1 + 1'b1;
end
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/batch_li_parent.v 0000664 0000000 0000000 00000000773 13022141775 0022566 0 ustar 00root root 0000000 0000000 module batch_li_parent (/*AUTOARG*/
// Inputs
clk, rst
);
input rst;
input clk;
parameter WIDTH_0 = 8;
parameter WIDTH_1 = 16;
batch_li_child
#(.WIDTH_1 (WIDTH_0),
.WIDTH_0 (WIDTH_1))
child
(/*AUTOINST*/
// Inputs
.rst (rst),
.clk (clk));
endmodule
// Local Variables:
// verilog-auto-arg-sort: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/batch_prof_cell.v 0000664 0000000 0000000 00000000106 13022141775 0022544 0 ustar 00root root 0000000 0000000 module batch_prof_cell(Z,A,B);
output Z;
input A, B;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/carlson.v 0000664 0000000 0000000 00000001063 13022141775 0021102 0 ustar 00root root 0000000 0000000 module x ();
always @ (/*AUTOSENSE*/bus or in1 or in2 or reset) begin
out4 = | bus;
out7 = 1'b0; // pre-initialize output of case so default not needed
case (bus[1:0])
2'b00: out7 = in1;
2'b01: out7 = in2;
2'b10: out7 = reset;
`ifdef BEH
default: begin
out7 = 1'bX; // force VCS simulation to propagate X's from the bus signal
$display ("\n Error, in module temp, bus[1:0] illegal value of 11\n");
end
`endif
endcase // case(bus[1:0])
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/case_question.v 0000664 0000000 0000000 00000000373 13022141775 0022306 0 ustar 00root root 0000000 0000000 module test ();
always @(/*AUTOSENSE*/xyz)
begin
casex (xyz)
4'b???0: r = 1;
4'b??01: r = 2;
4'b?001: r = 3;
default: r = 4;
endcase
end
assign x = y;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/comment_strip.v 0000664 0000000 0000000 00000001421 13022141775 0022322 0 ustar 00root root 0000000 0000000 module foo;
initial begin
/* The function verilog-strip-comments should not change this line:*/
$display("INFO :[PIPE LINK %d]: ///////////////////////////////////////////",PIPE_LINK);
// to this:
$display("INFO :[PIPE LINK %d]: ");
/* The function verilog-strip-comments should not change this line:*/
$display("INFO :[PIPE LINK %d]: /* ",PIPE_LINK); /* This comment should go away */
// to this:
$display("INFO :[PIPE LINK %d]: ");
/* also this comment should not get eaten
because of use of slashes // and such like
*/
/*
ugly hidded end comment // */
$display("don't forget me agentina");
// another hidden comment /*
/**/
end
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/debug.v 0000664 0000000 0000000 00000000474 13022141775 0020534 0 ustar 00root root 0000000 0000000 `include "some_macros.v"
module z();
$display("%t:", $time);
a = b;
casfasdf = d;
g = r;
fgasdfasdfasdfasfdasfd <= p;
gh := h;
gf <=g;
ssdf = 5;
f = zsfdsdf >= f;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/disable.v 0000664 0000000 0000000 00000001224 13022141775 0021043 0 ustar 00root root 0000000 0000000 module foo;
task my_task;
begin :body_my_task
fork
join
case (a)
endcase // case endcase
if (a) begin
end
begin
end
fork : main_fork
begin : body_main_fork
fork : sub_fork
begin
// st1
end
begin
// st2
end
join_any // first wins
a = b;
disable fork; // kill others
end // block: body_main_fork
end // block: body_main_fork
endtask // my_task
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/escape_a.v 0000664 0000000 0000000 00000000435 13022141775 0021203 0 ustar 00root root 0000000 0000000 module escape_a (/*AUTOARG*/
// Outputs
\o[10] , \o[2] ,
// Inputs
\i&e;
);
output \o[10] ;
output \o[2] ;
input \i&e; ;
wire \o[10] = \i&e; ;
wire \o[2] = \i&e; ;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/escape_top.v 0000664 0000000 0000000 00000001631 13022141775 0021564 0 ustar 00root root 0000000 0000000 module escape_top (/*AUTOARG*/
// Outputs
\oren10 , \o[2] ,
// Inputs
\i&e;
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input \i&e; ; // To a of escape_a.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output \o[2] ; // From a of escape_a.v
output \oren10 ; // From a of escape_a.v
// End of automatics
/* escape_a AUTO_TEMPLATE(
.\(.*o.*10.*\) (\\oren10 ),
); */
escape_a a (/*AUTOINST*/
// Outputs
.\o[10] (\oren10 ), // Templated
.\o[2] (\o[2] ),
// Inputs
.\i&e; (\i&e; ));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/example.v 0000664 0000000 0000000 00000001712 13022141775 0021075 0 ustar 00root root 0000000 0000000 module example (/*AUTOARG*/
// Outputs
lower_out, o,
// Inputs
lower_inb, lower_ina, i
);
input i;
output o;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input lower_ina; // To inst of inst.v
input lower_inb; // To inst of inst.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output lower_out; // From inst of inst.v
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg o;
// End of automatics
inst inst (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
// Inputs
.lower_inb (lower_inb),
.lower_ina (lower_ina));
always @ (/*AUTOSENSE*/i) begin
o = i;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/flag_f_reeves.v 0000664 0000000 0000000 00000001262 13022141775 0022231 0 ustar 00root root 0000000 0000000
module flag_f_reeves
(/*AUTOARG*/
// Outputs
q,
// Inputs
a
) ;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output q; // From ibuf of flag_f_reeves_IBUF.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input a; // To ibuf of flag_f_reeves_IBUF.v
// End of automatics
flag_f_reeves_IBUF ibuf
(/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a));
endmodule
// Local Variables:
// verilog-library-flags: ("-f flag_f_reeves.vc")
// End:
verilog-mode-20161124.fd230e6/tests_ok/flag_f_reeves.vc 0000664 0000000 0000000 00000000012 13022141775 0022364 0 ustar 00root root 0000000 0000000 -y subdir
verilog-mode-20161124.fd230e6/tests_ok/for.v 0000664 0000000 0000000 00000001007 13022141775 0020225 0 ustar 00root root 0000000 0000000 module lbm
(/*AUTOARG*/
// Outputs
outgo,
// Inputs
income
);
input [1:0] income;
output [1:0] outgo;
reg [1:0] outgo;
integer i;
always @ (/*AUTOSENSE*/income) begin
for (i=0; i<32; i=i+1) begin
outgo[i] = income[i];
end
end
always @ (/*AUTOSENSE*/income) begin
if (|income) begin
$display("[0%10t] %I-for.v: found %s \"quote\" ",
$time, ((|income)?"in":"out"));
end
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/gorfajn.v 0000664 0000000 0000000 00000000726 13022141775 0021074 0 ustar 00root root 0000000 0000000 module x;
always @(/*autosense*/d32S_CurCcbH or ramS_CcbBaseH or ramS_ccbsizeH)
begin
case (ramS_ccbsizeH)
2'b00 : ramS_CcbAddH = {2'b00, d32S_CurCcbH };
2'b01 : ramS_CcbAddH = {1'b0, d32S_CurCcbH, 1'b0};
2'b10 : ramS_CcbAddH = {d32S_CurCcbH, 2'b00};
2'b11 : ramS_CcbAddH = {d32S_CurCcbH, 2'b00}; // unused
endcase
ramS_CcbAddresH = {10'h000, ramS_CcbAddH} + ramS_CcbBaseH;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/grisamore_twoinone.v 0000664 0000000 0000000 00000001754 13022141775 0023362 0 ustar 00root root 0000000 0000000 module foo (/*AUTOARG*/
// Outputs
d,
// Inputs
b, a
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input a; // To foo2 of foo2.v
input b; // To foo2 of foo2.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output d; // From foo2 of foo2.v
// End of automatics
/*AUTOWIRE*/
/*AUTOREGINPUT*/
foo2 foo2 (/*AUTOINST*/
// Outputs
.d (d),
// Inputs
.a (a),
.b (b));
endmodule
module foo2 (/*AUTOARG*/
// Outputs
d,
// Inputs
a, b
);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*AUTOREGINPUT*/
input a;
input b;
output d;
//{ Behavioral verilog code here}
endmodule
verilog-mode-20161124.fd230e6/tests_ok/hangcase.v 0000664 0000000 0000000 00000004522 13022141775 0021215 0 ustar 00root root 0000000 0000000 // See Line 54
module hangcase (/*AUTOARG*/);
//
assign w_rdat_ena = ({16{foo[ 0]}} & bar ) |
({16{foo[ 1]}} & bar ) |
({16{foo[ 2]}} & bar ) |
({16{foo[ 3]}} & bar ) |
({16{foo[ 4]}} & bar ) |
({16{foo[ 5]}} & bar ) |
({16{foo[ 6]}} & bar ) |
({16{foo[ 7]}} & bar ) |
({16{foo[ 8]}} & bar ) |
({16{foo[ 9]}} & bar ) |
({16{foo[10]}} & bar ) |
({16{foo[11]}} & bar ) |
({16{foo[12]}} & bar ) |
({16{foo[13]}} & bar ) |
({16{foo[14]}} & bar ) |
({16{foo[15]}} & bar ) ;
//
assign w_rdat_mrk = ({16{foo[ 0]}} & bar & baz ) |
({16{foo[ 1]}} & bar & baz ) |
({16{foo[ 2]}} & bar & baz ) |
({16{foo[ 3]}} & bar & baz ) |
({16{foo[ 4]}} & bar & baz ) |
({16{foo[ 5]}} & bar & baz ) |
({16{foo[ 6]}} & bar & baz ) |
({16{foo[ 7]}} & bar & baz ) |
({16{foo[ 8]}} & bar & baz ) |
({16{foo[ 9]}} & bar & baz ) |
({16{foo[10]}} & bar & baz ) |
({16{foo[11]}} & bar & baz ) |
({16{foo[12]}} & bar & baz ) |
({16{foo[13]}} & bar & baz ) |
({16{foo[14]}} & bar & baz ) |
({16{foo[15]}} & bar & baz ) ;
//
assign w_wdat_ena_set = ({16{ena_set}} & col_dec );
assign w_wdat_ena_clr = ({16{ena_clr}} & col_dec );
assign w_wdat_mrk_set = ({16{mrk_set}} & w_rdat_ena );
assign w_wdat_mrk_clr = ({16{mrk_clr}} & col_dec );
assign w_wdat_ena = (w_rdat_ena & ~w_wdat_ena_clr) | w_wdat_ena_set;
assign w_wdat_mrk = (w_rdat_mrk & ~w_wdat_mrk_clr) | w_wdat_mrk_set;
//
assign w_dat15_ena = foo[15] ? w_wdat_ena : bar;
//
assign w_dat15_mrk = foo[15] ? w_wdat_mrk : baz;
//^^^^ FIX NEWLINE ABOVE HERE
//
assign w_timeout_mrk = row_check ? w_wdat_mrk : r_timeout_mrk;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_1.v 0000664 0000000 0000000 00000000145 13022141775 0021142 0 ustar 00root root 0000000 0000000 module foo(reg_input_signal_name);
input a;
input reg_input_signal_name;
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/indent_2.v 0000664 0000000 0000000 00000000511 13022141775 0021140 0 ustar 00root root 0000000 0000000 module foo(reg_input_signal_name,a,b,c,d,e);
// foo bar
output c;//this is a comment
reg foo;
//a
/* jj
KK */
reg foo;
output reg /* */ signed d;
output reg signed e; /* so is this */
reg [31:0] blather;
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/indent_3.v 0000664 0000000 0000000 00000000615 13022141775 0021146 0 ustar 00root root 0000000 0000000 module junk (/*AUTOARG*/
// Outputs
c_junk, d_junk,
// Inputs
a_junk, b_junk
) ;
input a_junk;
input wire signed [15:0] b_junk;
output c_junk;
output [15:0][31:0][1024:(`REALLY_BIG_NAME-1)] d_junk;
endmodule // junk
verilog-mode-20161124.fd230e6/tests_ok/indent_4.v 0000664 0000000 0000000 00000000435 13022141775 0021147 0 ustar 00root root 0000000 0000000 module foo;
initial
begin
s1;
end
always @(a)
begin
s1;
end // always @ (a)
always
begin
s1;
end // always begin
always_ff
begin
end // always_ff begin
task
t;
endtask // t
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/indent_always_decl.v 0000664 0000000 0000000 00000001752 13022141775 0023276 0 ustar 00root root 0000000 0000000 module foo ();
// Before the always block,
// indents to here: (which I like)
// V
wire [10:0] mux_output0 =
select0[0] ? mux_input0 :
select0[1] ? mux_input1 :
select0[2] ? mux_input2 :
select0[3] ? mux_input3 :
select0[4] ? mux_input4 :
select0[5] ? mux_input5 :
select0[6] ? mux_input6 :
mux_input7;
reg foobar;
always @(posedge clk)
if (reset_n) begin
foobar <= 1'b0;
end
// After the always block,
// indents to here:
// V
wire [10:0] mux_output1 =
select1[0] ? mux_input8 :
select1[1] ? mux_input9 :
select1[2] ? mux_input10 :
select1[3] ? mux_input11 :
select1[4] ? mux_input12 :
select1[5] ? mux_input13 :
select1[6] ? mux_input14 :
mux_input15;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_assert.v 0000664 0000000 0000000 00000000275 13022141775 0022307 0 ustar 00root root 0000000 0000000 module assert_test;
reg [31:0] whatever2;
initial begin
a = b;
assert(std::randomize(whatever2) with { whatever2 inside {[10:100]};});
end
endmodule // assert_test
verilog-mode-20161124.fd230e6/tests_ok/indent_assert_else.v 0000664 0000000 0000000 00000002455 13022141775 0023321 0 ustar 00root root 0000000 0000000 module myassert(input clk,
input reset,
input [15:0] data);
property myproperty;
@(posedge clk)
$rose(reset) |-> data == 16'h0;
endproperty
//Assert, cover, and assume property statements
//support begin/end keywords. The else begin/end
//clause below is getting indented improperly.
myassert0: assert property(myproperty) begin
$display("myassert0 was successful");
a;
b;
c;
d;
end // myassert0: assert property (myproperty)
else begin
$fatal("myassert0 was unsuccessful");
end // else: !assert property(myproperty)
if (a) begin
b;
c;
end // if (a)
else begin
o;
end // else: !if(a)
assert (a) begin
o;
end // assert (a)
else begin
o;
end // else: !assert (a)
assert (statement) begin
$display("assertion passed"); //this code is correctly indented
end // assert (statement)
else begin // this whole section should be moved to the left
$error("assertion failed");
end // else: !assert (statement)
//Also, any statements following the assert,
//cover, and assume property statements get
// indented too far to the right.
always @(posedge clk) begin
a;
end // always @ (posedge clk)
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_assert_property.v 0000664 0000000 0000000 00000001305 13022141775 0024246 0 ustar 00root root 0000000 0000000 module myassert(input clk,
input reset,
input [15:0] data);
property myproperty;
@(posedge clk)
$rose(reset) |-> data == 16'h0;
endproperty
//Assert, cover, and assume property statements
//support begin/end keywords. The else begin/end
//clause below is getting indented improperly.
myassert0: assert property(myproperty) begin
$display("myassert0 was successful");
end
else begin
$fatal("myassert0 was unsuccessful");
end
//Also, any statements following the assert,
//cover, and assume property statements get
// indented too far to the right.
always @(posedge clk) begin
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_assignment.v 0000664 0000000 0000000 00000000703 13022141775 0023152 0 ustar 00root root 0000000 0000000 // Issue 941 : The following operators should not be broken by auto-indents
module m;
initial begin
a = b;
a <= b;
a <<= b;
a <<<= b;
a >= b;
a >>= b;
a >>>= b;
a == b;
a != b;
a === b;
a !== b;
a ==? b;
a !=? b;
a <-> b;
a -> b;
a ->> b;
a |-> b;
a |=> b;
a #-# b;
a #=# b;
a := b;
a :/ b;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_attributes.v 0000664 0000000 0000000 00000000342 13022141775 0023167 0 ustar 00root root 0000000 0000000 module example(out1, out2, out3);
(* LOC = "D14" *)
output out1;
/* foobar */ (* LOC = "C15" *) /* jar */ output out2;
(* LOC = "C16" *)
output out3;
out1 = 1'b1;
out2 = 1'b1;
out3 = 1'b1;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_begin_clapp.v 0000664 0000000 0000000 00000000630 13022141775 0023244 0 ustar 00root root 0000000 0000000 // bug 825
module x;
always @*
begin
end
initial
begin
end
final
begin
end
initial forever
begin
end
foreach(1)
begin
end
do
begin
end while (i);
initial @a.b
begin
end
always @E
begin
end
forever @E
begin
end
endmodule
// Local Variables:
// verilog-indent-begin-after-if: nil
// End:
verilog-mode-20161124.fd230e6/tests_ok/indent_bracket.v 0000664 0000000 0000000 00000000473 13022141775 0022421 0 ustar 00root root 0000000 0000000 // bug437: Indentation of continued assignment incorrect if first line ends with ']'
module foo
(input [63:0] data_in,
input ctl_in,
output [63:0] data_out,
output ctl_out);
assign data_out = data_in[1] ? data_in[63:0]
: 64'h0;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_case.v 0000664 0000000 0000000 00000001434 13022141775 0021717 0 ustar 00root root 0000000 0000000 module testcaseindent();
case (a)
1: begin
asdf;
end // case: 1
2: begin
asdfasdf;
end // case: 2
3: begin
asdfasd;
end // case: 3
endcase // case (a)
unique case (a)
1: begin
asdf;
end // case: 1
2: begin
case (d)
2: a;
3: c;
4: begin
priority casex (f)
4: g;
5: h;
endcase // priority casex
end
endcase // case (d)
asdfasdf;
end // case: 2
3: begin
asdfasd;
end // case: 3
endcase // case (a)
unique case (a)
1: asdf;
2: asdfasdf;
3: asdfasd;
endcase // case (a)
endmodule // test_case_indent
verilog-mode-20161124.fd230e6/tests_ok/indent_class.v 0000664 0000000 0000000 00000002041 13022141775 0022104 0 ustar 00root root 0000000 0000000 class foo();
int my_field;
endclass // foo
class temp;
extern function test();
extern function test2();
function foo();
foo = 1;
endfunction // foo
extern function test3();
reg [31:0] b;
endclass // temp
class short extends temp;
logic a;
endclass
`define vmm_channel(A) A+A
module foo;
reg a;
reg [1:0] b;
initial begin
b = `vmm_channel(a);
end // initial begin
endmodule // foo
class A;
extern function int e1();
extern function int e2(int src,int dst);
extern static function int f1();
extern static function int f2(int src,int dst);
extern static function int f3(int src,int dst);
extern static function chandle f10(int src);
extern static function automatic int f11(int mcid);
extern function automatic int f13(int mcid);
static function int s1();
int i = 0;
endfunction
static function int s2();
int i = 0;
endfunction
function int f1();
int i = 0;
endfunction
function int f2();
int i = 0;
endfunction
endclass
verilog-mode-20161124.fd230e6/tests_ok/indent_clocking.v 0000664 0000000 0000000 00000000562 13022141775 0022576 0 ustar 00root root 0000000 0000000 module t;
default clocking @(posedge clk);
begin
a = 8;
end
property foo (a)
a = b;
endproperty
cover property (prop) $display("**COVERAGE**");
assert property (foo) a;
assume property (bar) b;
b1: assume property (bar) b;
B2: assert property (foo) a;
B2: cover property (foo) a;
assume property (bar) b;
a;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_clockingblock.v 0000664 0000000 0000000 00000001561 13022141775 0023611 0 ustar 00root root 0000000 0000000 class mipsbfm_trans extends vmm_data;
static vmm_log log = new ("mipsbfm_trans", "class") ;
logic [31:0] addr, data, mask, op;
function new();
super.new(this.log);
endfunction: new
endclass // mipsbfm_trans
interface mipsbfm_if(input clk);
logic [31:0] data;
logic [31:0] addr;
logic [31:0] mask;
logic [31:0] op;
logic valid;
clocking cb @(posedge clk);
output data;
output addr;
output mask;
output op;
output valid;
endclocking // cb
endinterface // mipsbfm_if
`vmm_channel(mipsbfm_trans);
//--------------------------------------------------------------
// MIPS BFM Master Xactor Class
//--------------------------------------------------------------
class mipsbfm_master extends vmm_xactor;
// Transaction channels
mipsbfm_trans_channel in_chan ;
endclass // mipsbfm_master
verilog-mode-20161124.fd230e6/tests_ok/indent_comments.v 0000664 0000000 0000000 00000000304 13022141775 0022624 0 ustar 00root root 0000000 0000000 module dummy (
input wire xx,
output wire yy, // comment with paren ) adsfasdf
ouput wire zz); // oops - matched paren in comment!!
endmodule // dummy
verilog-mode-20161124.fd230e6/tests_ok/indent_constraint.v 0000664 0000000 0000000 00000007200 13022141775 0023165 0 ustar 00root root 0000000 0000000 // my simple if else example, indented by verilog-mode
if (x == 1)
begin
test1 <= 1;
test2 <= 2;
end
else
begin
test1 <= 2;
test2 <= 1;
end
// code from IEEE spec, pg. 164
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 3
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 0
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
endclass // MyBus
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a {
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
b : coverpoint v_b {
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
//
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
// here is the same code with verilog-mode indenting
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a
{
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
// foo
b : coverpoint v_b
{
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
module fool;
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case (condition[1 :0])
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case (condition[1:0])
end
// But not this :
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case ({M_seqAddr,OPB_xferAck})
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case ({M_seqAddr,OPB_xferAck})
end // always @ (posedge clk)
endmodule // fool
module foo;
initial begin
k = 10;
std::randomize(delay) with { (delay>=1000 && delay<=3000); };
j = 9;
end
endmodule // foo
// Issue 324 - constraint indentation is not correct
// This checks for indentation around { and } inside constraint contents
class myclass;
constraint c {
foreach(items[i]) {
if(write) {
items[i].op_code == WRITE;
} else if(read) {
items[i].op_code == READ;
}
}
}
endclass // myclass
verilog-mode-20161124.fd230e6/tests_ok/indent_constraint2.v 0000664 0000000 0000000 00000002011 13022141775 0023242 0 ustar 00root root 0000000 0000000
constraint Cepon_gate_random::grant_relations_c {
foreach (grant_relation_m[index]) {
if ((index == 0) && (last_start_time_m < time_stamp_m+`MINIMUM_TIME_TO_GATE)) grant_relation_m[index] == EPON_GATE_IN_ORDER;
else {
grant_relation_m[index] dist {
EPON_GATE_IN_ORDER :/55,
EPON_GATE_1ST_CONTAINS_2ND :/5,
EPON_GATE_2ND_CONTAINS_1ST :/5,
EPON_GATE_1ST_START_2ND_START :/5,
EPON_GATE_2ND_START_1ST_START :/5,
EPON_GATE_NO_GAP_1ST :/5,
EPON_GATE_NO_GAP_2ND :/5,
EPON_GATE_1CC_GAP :/5,
EPON_GATE_1CC_INTERLEAVE :/5,
EQUAL :/5
};
}
}
}
verilog-mode-20161124.fd230e6/tests_ok/indent_constraint3.v 0000664 0000000 0000000 00000000772 13022141775 0023257 0 ustar 00root root 0000000 0000000 //bug433
class data;
rand integer data1;
rand integer data2,data3;
rand reg [31:0] foo;
constraint basic_c {
//empty constraint
}
constraint complex_c {
data1 <= 100;
foo inside {[40:999]};
if(foo < 87)
data2 == 10;
if(data2 == 76) {
data3 == 8;
}
}
constraint implication_c {
data1 == 10 -> data3 >= -1;
}
function new();
data1 = 0;
data2 = 78;
endfunction // new
endclass // data
verilog-mode-20161124.fd230e6/tests_ok/indent_covergroup.v 0000664 0000000 0000000 00000001336 13022141775 0023200 0 ustar 00root root 0000000 0000000 module coverage;
enum { red, green, blue } color;
covergroup foo @(posedge clk);
c : coverpoint color;
c : coverpoint color;
c : coverpoint color;
c : coverpoint color;
endgroup // foo
foo = bar;
sequence bar
b = c;
endsequence // bar
j = taskt;
function foo;
begin
foo = 1;
end
endfunction // foo
randsequence bar
b = c;
endsequence // bar
case (foo)
1: a;
2:b;
endcase // case (foo)
casex (foo)
1: a;
2:b;
endcase // case (foo)
casez (foo)
1: a;
2:b;
endcase // case (foo)
randcase (foo)
1: a;
2:b;
endcase // case (foo)
endmodule // coverage
verilog-mode-20161124.fd230e6/tests_ok/indent_coverpoint.v 0000664 0000000 0000000 00000001455 13022141775 0023177 0 ustar 00root root 0000000 0000000
// here is the same code with verilog-mode indenting
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk);
a: coverpoint v_a {
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
b: coverpoint v_b iff ( g )
{
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
c: coverpoint v_c iff ( !g ) {
bins c1 = {0};
bins c2 = { [1:84] };
bins c3 = { [85:169] };
bins c4 = { [170:255] };
}
d: cross a , b, c {
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
verilog-mode-20161124.fd230e6/tests_ok/indent_decl-1.v 0000664 0000000 0000000 00000001234 13022141775 0022047 0 ustar 00root root 0000000 0000000 module soft_rst
(
// System clock and reset
input clk,
input rst_n,
// Interface to software land
input req_soft_rst, // Soft reset request
output soft_rst_dne, // Soft reset done
// Interface to other modules
output dma_halt, // Reset pending, halt activity
input tx_quiet, // TX side is dormant
input rx_quiet, // RX side is dormant
input c,
output soft_rst, // Soft (sync) reset to VC3 side
output hs_async_rst_n // Async reset to host side
);
reg [1:0] state;
reg [1:0] IDLE = 2'h0,
HALT = 2'h1,
RST = 2'h2,
DONE = 2'h3;
endmodule // soft_rst
verilog-mode-20161124.fd230e6/tests_ok/indent_decl.v 0000664 0000000 0000000 00000000421 13022141775 0021706 0 ustar 00root root 0000000 0000000 module foo;
input a;
input b;
input [1:0] cfg_dev_i; // Config Device: 0b00 = Pangu, 0b01 = Switch
output switch_idsel_o; // Switch PCI IDSEL
output pangu_idsel_o; // Pangu PCI IDSEL
output wire g;
inout wire h;
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/indent_directives.v 0000664 0000000 0000000 00000002742 13022141775 0023150 0 ustar 00root root 0000000 0000000 module foo;
`ifdef LABEL_A
CHIP CPU (
.clkin(clkin),
`ifdef LABEL_B
.bclko(bclko),
`endif
.cmode(cmode),
);
input sysclk;
`ifdef LABEL_B
input bclko;
`endif
input cmode;
`endif
// instead of:
`ifdef LABEL_A
CHIP CPU (
.clkin(clkin),
`ifdef LABEL_B
.bclko(bclko),
`endif
.cmode(cmode),
);
input sysclk;
`ifdef LABEL_B
input bclko;
`endif
input cmode;
`endif // `ifdef LABEL_A
reg a,b;
`ifdef A
always @(a) begin
b = a; // asfSDfsdfsasa
b = a; // asfSDfsdfsasa
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
end
`elsif B
always @(b) begin
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
end
`else // !`elsif B
always @(a or b) begin
a <= b;
b <= a;
end
`endif // !`elsif B
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/indent_dpi.v 0000664 0000000 0000000 00000002071 13022141775 0021556 0 ustar 00root root 0000000 0000000 import "DPI-C" function string fna (input string str1);
export "DPI" c_identifier = task task_identifier;
import "DPI" context function string fnb (input string str1);
module testbench;
import "DPI" function string fn1 (input string str1);
import "DPI-C" function void dpiWriteArray (input bit[7:0] data[]);
import "DPI-C" pure function void dpiReadArray (output bit[7:0] data[]);
import "DPI-C" function void dpiAesSetKey ( int key_high_u int key_high_l,
int key_low_u, int key_low_l );
import "DPI-C" function void dpiAesSetIV (int iv_high_u, int iv_high_l,
int iv_low_u, int iv_low_l);
import "DPI-C" function void dpiAesSetSkip (int skip);
import "DPI-C" function void dpiAesCBCEncrypt ();
logic a;
endmodule // testbench
/*
package ref_model;
import "DPI-C" xx_write_bmp_file =
function void write_bmp_file(input string filename);
import "DPI-C" xx_demosaic =
function void demosaic(regs regs,
inout pix_buf imgR, imgG, imgB);
endpackage
*/
verilog-mode-20161124.fd230e6/tests_ok/indent_foreach.v 0000664 0000000 0000000 00000000420 13022141775 0022405 0 ustar 00root root 0000000 0000000 `ifndef FOO
`define FOO
module foo;
reg [31:0] payload [255:0];
reg [7:0] index;
always @ (b) begin
foreach (1) begin
@(router.cb);
end // foreach (1)
end // always @ (b)
endmodule // foo
`else // !`ifndef FOO
`endif // !`ifndef FOO
verilog-mode-20161124.fd230e6/tests_ok/indent_fork_join_any.v 0000664 0000000 0000000 00000000723 13022141775 0023633 0 ustar 00root root 0000000 0000000 module fork_join_any;
initial begin
fork
begin
fork
begin
end
join_any
a = b;
disable fork;
blah;
wait fork;
blah;
end
join_any
foo = bar;
end // initial fork
endmodule // fork_join_any
class x;
task y;
a = b;
wait fork;
$display("I'm indented too far");
endtask // y
endclass // x
verilog-mode-20161124.fd230e6/tests_ok/indent_formfeed.v 0000664 0000000 0000000 00000000072 13022141775 0022570 0 ustar 00root root 0000000 0000000
module x;
foo;
endmodule
bar;
module z;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_function.v 0000664 0000000 0000000 00000003004 13022141775 0022624 0 ustar 00root root 0000000 0000000 module t;
endmodule
class C;
function int f();
f = 17;
endfunction
extern function int g();
virtual function int f();
a;
endfunction // int
// pure virtual functions have no endfunction.
C a;
initial begin
$display("hello world");
$display("a of f is %d, g is %d", a.f(),a.g());
end
function int C::g();
g = 18;
endfunction // g
// pure virtual functions have no endfunction.
endclass // C
class pure_virt_func_class;
pure virtual function string pure_virt_func();
pure virtual function string pure_virt_func();
pure virtual function string pure_virt_func();
extern pure virtual task t();
pure virtual task t();
virtual task t();
/* body */
endtask // t
virtual function f();
/* body */
endfunction // f
endclass // pure_virt_func_class
class base_test extends uvm_test;
`uvm_component_utils(base_test)
typedef virtual my_if my_vif_t;
// A function definition starting with the virtual keyword should not be
// detected as a declaration. This issue is seen when an attempt to indent
// each declaration is done (when the verilog-auto-lineup variable is set
// to 'declarations).
// In other words, the "function" in "virtual function" below must not be
// aligned with "my_if" in the "typedef virtual my_if.." line above.
virtual function void start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
endfunction : start_of_simulation_phase
endclass : base_test
verilog-mode-20161124.fd230e6/tests_ok/indent_generate.v 0000664 0000000 0000000 00000000346 13022141775 0022577 0 ustar 00root root 0000000 0000000 module test();
reg [3:0] x;
genvar i;
generate
for(i=0; i<4; i=i+1) begin:a
always @(*) begin
x[i] = 1;
end
wire y = 0;
end
endgenerate
endmodule // test
verilog-mode-20161124.fd230e6/tests_ok/indent_if.v 0000664 0000000 0000000 00000000212 13022141775 0021373 0 ustar 00root root 0000000 0000000 module foo;
initial
if (cond1) begin
sig1 <= {4'h0, 4'hc};
sig2 <= 8'hff;
end // if (cond1)
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/indent_if2.v 0000664 0000000 0000000 00000000660 13022141775 0021464 0 ustar 00root root 0000000 0000000 module foo;
always@(*)
begin
if(state==LBT_STATE)
begin
if(something)
begin
end
else
begin
end
end
else if(state==HS_0_STATE)
begin
end
else if(state==STATE_4)
begin
end
else
begin
end
end // always@ (*)
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/indent_ifdef.v 0000664 0000000 0000000 00000002157 13022141775 0022064 0 ustar 00root root 0000000 0000000 module test(out);
output out;
`define wow
`define nest_one
`define second_nest
`define nest_two
`ifdef wow
initial $display("wow is defined");
`ifdef nest_one
initial $display("nest_one is defined");
`ifdef nest_two
initial $display("nest_two is defined");
`else
initial $display("nest_two is not defined");
`endif
`else
initial $display("nest_one is not defined");
`endif
`else
initial $display("wow is not defined");
`ifdef second_nest
initial $display("second_nest is defined");
`else
initial $display("second_nest is not defined");
`endif
`endif
endmodule
// Local Variables:
// verilog-auto-lineup: all
// verilog-auto-endcomments: t
// verilog-auto-indent-on-newline: t
// verilog-auto-lineup: all
// verilog-auto-newline: nil
// verilog-case-indent: 2
// verilog-highlight-p1800-keywords: nil
// verilog-indent-begin-after-if: t
// verilog-indent-level: 2
// verilog-indent-level-behavioral: 2
// verilog-indent-level-declaration: 2
// verilog-indent-level-directive: 2
// verilog-indent-level-module: 2
// verilog-minimum-comment-distance: 40
// verilog-tab-always-indent: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/indent_ifdef_generate.v 0000664 0000000 0000000 00000002546 13022141775 0023740 0 ustar 00root root 0000000 0000000 // Issue 559 - nested ifdef with generate indentation bug
module m;
`ifndef DDR_PT_GATE_SIM
generate
/***************** Assertions for DP HM signals ***************************************************************/
for (dp_id=0; dp_id = 0 ? 0 : 1)
// Incorrect indentation (v1) *strangely, not yet affected by the >= chars above*
`define DEF2 { "a" \
, "b" \
}
// Incorrect indentation (v2) *NOW aligns to the
// >= sign in `define TEMPB above (which it should not)
// Looks like the multi-line macro definition DEF2
// above caused this second version of incorrect
// indentation*
`define TEMPC ((`TEMPA + 1_000_000) >= 0 ? 0 : 1)
// BACK TO Incorrect indentation (v1)!
`define DEF3 { "a" \
, "b" \
}
// BACK TO Incorrect indentation (v2)! Surprisingly
// the >= sign in `define TEMPC macro did not affect
// the indentation this time; but the indentation
// returned to (v2) as set by that sign in `define TEMPB
`endif
verilog-mode-20161124.fd230e6/tests_ok/indent_mailbox.v 0000664 0000000 0000000 00000000443 13022141775 0022436 0 ustar 00root root 0000000 0000000 class Driver;
mailbox mbox; // <= not highlighted.
semaphore smtx;
int id;
virtual Rx_if Rx;
function new(mailbox mbox, int id, virtual Rx_if.TB Rx);
this.mbox = mbox;
this.id = i;
this.Rx = Rx;
endfunction // new
endclass // Driver
verilog-mode-20161124.fd230e6/tests_ok/indent_modansi.v 0000664 0000000 0000000 00000000735 13022141775 0022441 0 ustar 00root root 0000000 0000000 module testmodule(
input wire [1:0] pin1,
input wire pin2,
input wire [1:0] pin3,
input wire pin4,
output wire pin5,
output wire [10:0] pin6,
output reg pin7,
output reg [1:0] pin8
);
initial begin
$display("alls well that ends well");
end
endmodule // testmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_modport.v 0000664 0000000 0000000 00000000162 13022141775 0022465 0 ustar 00root root 0000000 0000000 module foo;
modport foo_mp;
modport foo_mp1(a);
modport foo_mp2(clocking bar_cb);
a;
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/indent_named_assert.v 0000664 0000000 0000000 00000000346 13022141775 0023452 0 ustar 00root root 0000000 0000000 module test;
property p_test;
a |-> b;
endproperty : p_test
assert property (p_test);
a_test : assert property (p_test);
a = b; // this and following lines are not properly indented
foo;
endmodule // test
verilog-mode-20161124.fd230e6/tests_ok/indent_ovm.v 0000664 0000000 0000000 00000004051 13022141775 0021603 0 ustar 00root root 0000000 0000000 module ovm;
class simple_item extends ovm_sequence_item;
rand int unsigned addr;
rand int unsigned data;
rand int unsigned delay;
constraint c1 { addr < 16'h2000; }
constraint c2 { data < 16'h1000; }
// OVM automation macros for general objects
`ovm_object_utils_begin(simple_item)
a = b;
c = d;
`ovm_field_int(addr, OVM_ALL_ON)
`ovm_field_int(data, OVM_ALL_ON)
`ovm_field_int(delay, OVM_ALL_ON)
`ovm_object_utils_end
// Constructor
function new (string name = "simple_item");
super.new(name);
endfunction : new
endclass : simple_item
class mydata extends ovm_object;
string str;
mydata subdata;
int field;
myenum e1;
int queue[$];
`ovm_object_utils(mydata)
`ovm_object_utils_begin(mydata) //requires ctor with default args
`ovm_field_string(str, OVM_DEFAULT)
`ovm_field_object(subdata, OVM_DEFAULT)
`ovm_field_int(field, OVM_DEC) //use decimal radix
`ovm_field_enum(myenum, e1, OVM_DEFAULT)
`ovm_field_queue_int(queue, OVM_DEFAULT)
`ovm_object_utils_end
`ovm_object_param_utils_begin(mydata) //requires ctor with default args
`ovm_field_string(str, OVM_DEFAULT)
`ovm_field_object(subdata, OVM_DEFAULT)
`ovm_field_int(field, OVM_DEC) //use decimal radix
`ovm_field_enum(myenum, e1, OVM_DEFAULT)
`ovm_field_queue_int(queue, OVM_DEFAULT)
`ovm_object_utils_end
endclass
class my_trans extends ovm_sequence_item;
rand bit [127:0] data [];
//---> Configuration
`ovm_object_utils_begin(my_trans)
`ovm_field_array_int ( data, OVM_ALL_ON)
`ovm_object_utils_end
function new (string name = "my_trans", ovm_sequencer_base sequencer = null, ovm_sequence parent_seq = null);
super.new(name, sequencer, parent_seq);
endfunction : new
endclass : my_trans
endmodule // ovm
module tt;
initial begin
while (1) begin
`ovm_do_with(aa, {bb == 0;})
`ovm_do(cc)
`ovm_do(cc)
end // while (1)
end // initial begin
endmodule // tt
verilog-mode-20161124.fd230e6/tests_ok/indent_param.v 0000664 0000000 0000000 00000000376 13022141775 0022110 0 ustar 00root root 0000000 0000000 module example_block
#(
parameter PARAM = 1,
FOO = 2,
BARFLUG = 4,
G = 5,
)
(// I/O
input reset_n,
input clk
input a, b,
output reg c
);
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_preproc.v 0000664 0000000 0000000 00000000436 13022141775 0022457 0 ustar 00root root 0000000 0000000
aa;
`__FILE__
`__LINE__
`celldefine
`end_keywords
`resetall
`unconnected_drive
`undefineall
`ifdef AA
`else
`endif
`ifndef AA
`elsif FOO
`endif
`begin_keywords "FOO"
`undef FOO
`line 2 "xx" 2
`include "YY"
`include
`pragma endofline
`timescale 10ns/10ps
`define foo bar
verilog-mode-20161124.fd230e6/tests_ok/indent_preproc_label.v 0000664 0000000 0000000 00000000575 13022141775 0023622 0 ustar 00root root 0000000 0000000 // bug861/862 - named coverpoint inside/near pre-processor macro confuses indentation
module m;
`ifdef ASSERT_ON
asrt_001: assert property(p_001);
asrt_002: assert property(p_002);
asrt_003: assert property(p_003);
`endif
`ifdef COVER_ON
chk_001: cover property(p_001);
chk_002: cover property(p_002);
chk_003: cover property(p_003);
`endif
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_property.v 0000664 0000000 0000000 00000002356 13022141775 0022674 0 ustar 00root root 0000000 0000000 module foo();
initial begin
a;
end
always @(a) begin
b;
end
task a (a);
begin
a = f;
a = f;
d <= 89;
sdf = sdf;
adada = > asda;
d ->> g;
aasd <<<= 3;
ccc %= 6;
d *= b;
g -= c;
end
endtask // a
property p_3;
a = > ##3 !a;
a |=> ##1 !a;
a |-> ##2 !a;
endproperty
property p_2;
@(posedge clk) b |-> ##1 c;
endproperty
property p_1;
@(posedge clk) a |-> b;
endproperty
initial d;
// ap_1 assert property (p_1); FIXME
// ap_2 assert property (p_2);
property p_lane_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(lane_inputs) |-> !$stable(lane_outputs);
endproperty
// Issue #940 - '=' in |=> , #=#, and [=n] operators should not mis-indent next line of continued expression
property p_nonSequential;
a |-> b[=n] ##0
c;
endproperty
property p_nonOverlapFollowedBy;
a #=#
c;
endproperty
property p_nonBlockingImplication;
a |=> b[*n] ##0
c;
endproperty
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_randcase.v 0000664 0000000 0000000 00000000404 13022141775 0022560 0 ustar 00root root 0000000 0000000 module aa;
int a,b,c;
initial begin
randcase
10 : begin
a = 1;
end
15 : begin
b = 0;
c = 5;
end
endcase // randcase
end // initial begin
endmodule // a
verilog-mode-20161124.fd230e6/tests_ok/indent_random.v 0000664 0000000 0000000 00000001410 13022141775 0022256 0 ustar 00root root 0000000 0000000 module top;
initial begin
// Test
$display("Hello world");
void'(std::randomize(foo) with {foo < 10;}; );
end
endmodule // top
/*
--------------------------
It also appears to have indentation problems with the following variation:
== The code: ==
*/
module top;
initial begin
// Test
$display("Hello world");
assert(std::randomize(foo) with {foo < 10;}; )
else $error("ERROR randomizing foo");
end
endmodule // top
/*
------------------------------
Also tried the following (removed semicolon after closing-curly-brace), and got same result:
*/
module top;
initial begin
// Test
$display("Hello world");
void'(std::randomize(foo) with {foo < 10;} );
end
endmodule // top
verilog-mode-20161124.fd230e6/tests_ok/indent_struct.v 0000664 0000000 0000000 00000001536 13022141775 0022333 0 ustar 00root root 0000000 0000000 module foo;
a = { g + c; };
a = c;
typedef struct {
reg r;
ahb_op_t op; // Read, write, etc.
ahb_cycle_type_t cti; // Cycle type for bursts
ahb_incr_type_t incr; // Increment type (for bursts)
bit b;
reg r;
ahb_thingy a;
bit [31:2] addr; // Starting address
bit [3:0] byte_sel; // Byte lane select
int len; // Length of transfer
bit [31:0] data[0:7]; // Write data
} ahb_req_t;
struct {
reg f;
xyzzy b;
};
struct packed {
int a; // ok
};
struct packed signed {
int a; // woops
};
struct packed unsigned {
int a; // woops
};
endmodule // foo
module foo (
input a;
input c;
output d;
);
always @(a) g;
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/indent_task.v 0000664 0000000 0000000 00000004424 13022141775 0021750 0 ustar 00root root 0000000 0000000 module foo;
// for each additional in-air txmacphy byte
task nextTxByte();
TxByteCnt++;
TxLastByteTime = $time;
endtask // nextTxByte
task automatic blah();
t;
endtask // blah
function static foo();
foo = 1;
endfunction // foo
// start counting when txmacphy sees first in-air byte
task firstTxByte();
TxByteCnt = 1;
TxFirstByteTime = $time;
TxLastByteTime = $time;
endtask // firstTxByte
// outputs the overall performance of the RX path in Mbps (MBits per second)
task printRxPerformance();
integer ibps;
real Mbps;
if( RxByteCnt && systemTop.intMonitor.frgRxedCnt >= 2 ) begin
ibps =
(RxByteCnt*8*1000000000)/(RxLastByteTime-RxFirstByteTime);
Mbps = ibps/1000000;
$display("%t: %s - RX average performance: %fMbps (Mbits/sec)",
$time, myName, Mbps );
end
else
$display("%t: %s - Requires >= 2 RX frames in order to measure performance", $time, myName);
endtask // printRxPerformance
endmodule // foo
class a;
virtual function void foo();
foo = 2;
endfunction // void
extern function void bar();
function fred();
aaa;
endfunction // fred
task foo;
endtask // endtask
virtual task foo;
endtask // endtask
generate g;
endgenerate
covergroup g;
endgroup // g
property p;
endproperty
sequence s;
endsequence // s
clocking c;
endclocking // c
function f;
endfunction //
virtual function f;
endfunction //
protected function f;
endfunction //
endclass // a
class base_test extends uvm_test;
`uvm_component_utils(base_test)
typedef virtual my_if my_vif_t;
// A task definition starting with the virtual keyword should not be
// detected as a declaration. This issue is seen when an attempt to indent
// each declaration is done (when the verilog-auto-lineup variable is set
// to 'declarations).
// In other words, the "task" in "virtual task" below must not be
// aligned with "my_if" in the "typedef virtual my_if.." line above.
virtual task run_phase(uvm_phase phase);
super.run_phase(phase);
endtask // run_phase
endclass // base_test
verilog-mode-20161124.fd230e6/tests_ok/indent_task_func_decl.sv 0000664 0000000 0000000 00000004437 13022141775 0024141 0 ustar 00root root 0000000 0000000 typedef class burst_drv;
class burst_drv extends vmm_xactor;
int EXECUTING;
int OBSERVED;
int SUB_OBSERVED;
protected burst_drv_cfg cfg;
local burst_drv_cfg reset_cfg;
protected burst_xn rx_factory;
local burst_xn reset_rx_factory;
burst_xn_channel in_chan;
burst_xn_channel obs_chan;
burst_xn tr_main; // Current transaction in main()
/* could have [extern] [virtual] [protected|local] task [static|automatic|] name (); */
/* If extern -> then it is complete; other wise it is not complete */
/* class could have:
class c
extern virtual static protected task t ();
endclass
task declaration could have
task static t();
endtask
*/
class c;
endclass // c
function f();
g;
endfunction // f
generate g;
/* a lot of stuff */
endgenerate
task t();
/**/
/**/
endtask // t
protected virtual task pv_t();
/**/
endtask // pv_t
protected task p_t();
/* ACK*/
endtask // p_t
virtual task v_t();
/**/
endtask // v_t
virtual protected task vp_t();
/**/
endtask // vp_t
protected virtual task pv_t();
/**/
endtask // pv_t
extern task e_t();
extern virtual task ev_t();
extern protected task ep_t();
extern protected virtual task epv_t();
extern protected virtual task main();
generate g;
/**/
endgenerate
extern virtual function void reconfigure(burst_drv_cfg cfg);
extern virtual function void reset_xactor(reset_e rst_type = SOFT_RST);
extern virtual function new (
string inst,
int stream_id,
burst_drv_cfg cfg = null,
burst_xn_channel in_chan = null,
burst_xn_channel obs_chan = null,
burst_xn rx_factory = null);
virtual task start();
super.start();
this.tx_dma.start();
this.rx_dma.start();
endtask // start
task start();
super.start();
this.tx_dma.start();
this.rx_dma.start();
endtask // start
task static start();
super.start();
this.tx_dma.start();
this.rx_dma.start();
endtask // static
endclass : burst_drv
verilog-mode-20161124.fd230e6/tests_ok/indent_typedef.sv 0000664 0000000 0000000 00000000206 13022141775 0022623 0 ustar 00root root 0000000 0000000 package p;
typedef enum {a, b} type_t;
typedef enum {TASK, TASK2} type2_t;
typedef enum {Package, Class} type3_t;
endpackage
verilog-mode-20161124.fd230e6/tests_ok/indent_unique_case-1.v 0000664 0000000 0000000 00000023476 13022141775 0023455 0 ustar 00root root 0000000 0000000 module xxx_xxxxxx (input wire clk, input wire reset);
typedef enum reg [4:0] {IDLE, IIII, HHHHH,
AA_OP, AA_CMRD, AA_CMRD_WAIT, AA_RMW, AA_RMW_WAIT, AA_CMLLL, AA_CMLLL_WAIT, AA_NEXT,
BB_OP, BB_CMLLL, BB_CMLLL_WAIT, BB_NEXT,
CC_OP, CC_NEXT_OOOO,
DD_OP, DD_CMRD, DD_CMRD_WAIT, DD_ACCUM, DD_CMLLL, DD_CMLLL_WAIT,
EE_OP, EE_NEXT_OOOO,
FF_OP,
zxcvzxcv, cvbncvbn} xxxxxx_state_e;
xxxxxx_state_e current_state;
always_ff @ (posedge clk) begin
if (reset) begin
current_state <= IDLE;
end
else begin
unique case (current_state)
IDLE : begin
qwerty <= '0;
if (~qqq_empty)
current_state <= HHHHH;
end
AA_CMLLL : begin
lll_start <= 1'b1;
if (jjjj_left < 4)
lll_wcnt <= jjjj_left[2:0];
else
lll_wcnt <= FOUR[2:0];
current_state <= AA_CMLLL_WAIT;
end
HHHHH : begin
qqq_opiuy <= 1'b1;
if (qqq_opiuy) begin
qqq_opiuy <= '0;
current_state <= IIII;
end
end
AA_OP : begin
if (aa_pgm_err) begin
current_state <= zxcvzxcv;
end
else begin
jjjj_left <= tgbyhn;
current_state <= AA_CMRD;
end
end
AA_CMRD : begin
uuuuu <= 1'b1;
current_state <= AA_CMRD_WAIT;
end
IIII : begin
qqq_opiuy <= '0;
if (err_iiii) begin
current_state <= zxcvzxcv;
end
else begin
unique0 case (opm_cur)
`XXXCP : current_state <= AA_OP;
`XXXZR : current_state <= BB_OP;
default : current_state <= zxcvzxcv;
endcase // unique0 case
end // else: !if(err_iiii)
end // case: IIII
AA_CMRD_WAIT : begin
uuuuu <= '0;
if (kjkjkjkjk) begin
if (err_cmrd_par) begin
current_state <= zxcvzxcv;
end
else begin
if (err_cmrd_csel) begin
current_state <= zxcvzxcv;
end
else begin : assign_writecvbn
lllcvbn <= asdf ? ghjk : rdcvbn;
lll_par <= asdf ? cvbn : rd_par;
current_state <= AA_CMLLL;
end
end // else: !if(err_cmrd_par)
end // if (kjkjkjkjk)
end // case: AA_CMRD_WAIT
AA_CMLLL_WAIT : begin
lll_start <= '0;
if (lll_done) begin
if (alalala) begin
current_state <= zxcvzxcv;
end
else begin
current_state <= AA_NEXT;
end
end
end // case: AA_CMLLL_WAIT
AA_NEXT : begin
if (qwerty) begin
qwerty <= '0;
unique case (opm_cur)
`XXXCP : current_state <= cvbncvbn;
`XXXSG : current_state <= CC_NEXT_OOOO;
default : current_state <= zxcvzxcv;
endcase // unique case
end // if (qwerty)
else begin
jjjj_left <= jjjj_left - 4;
current_state <= AA_CMRD;
end // else: !if(qwerty)
end // case: AA_NEXT
BB_OP : begin
if (bb_pgm_err) begin
current_state <= zxcvzxcv;
end
else begin
lllcvbn <= '0;
lll_par <= '0;
jjjj_left <= tgbyhn;
current_state <= BB_CMLLL;
end
end // case: BB_OP
BB_CMLLL : begin
lll_start <= 1'b1;
if (jjjj_left <= 4) begin
lll_wcnt <= jjjj_left[2:0];
qwerty <= 1'b1;
end
else begin
lll_wcnt <= FOUR[2:0];
end
current_state <= BB_CMLLL_WAIT;
end // case: BB_CMLLL
BB_CMLLL_WAIT : begin
lll_start <= '0;
if (lll_done) begin
if (alalala) begin
current_state <= zxcvzxcv;
end
else begin
current_state <= BB_NEXT;
end
end
end // case: BB_CMLLL_WAIT
BB_NEXT : begin
if (qwerty) begin
qwerty <= '0;
current_state <= cvbncvbn;
end
else begin
jjjj_left <= jjjj_left - 4;
current_state <= BB_CMLLL;
end
end
CC_OP : begin
jjjj_left_oooo <= tgbyhn;
if (tgbyhn <= oooo_cur) begin
last_oooo <= 1'b1;
jjjj_left <= tgbyhn;
end
else begin
jjjj_left <= oooo_cur;
end
current_state <= AA_CMRD;
end // case: CC_OP
CC_NEXT_OOOO : begin
if (last_oooo) begin
current_state <= cvbncvbn;
end
else begin
rd_rrrr <= rd_rrrr + ttttt_cur;
lll_rrrr <= lll_rrrr + oooo_cur;
if (jjjj_left_oooo <= oooo_cur) begin
last_oooo <= 1'b1;
jjjj_left <= jjjj_left_oooo;
end
else begin
jjjj_left <= oooo_cur;
end
current_state <= AA_CMRD;
end // else: !if(last_oooo)
end // case: CC_NEXT_OOOO
DD_OP : begin
accumulate_sum <= '0;
jjjj_left <= tgbyhn;
current_state <= DD_CMRD;
end
DD_CMRD : begin
uuuuu <= 1'b1;
if (jjjj_left <= 4) begin
qwerty <= 1'b1;
end
current_state <= DD_CMRD_WAIT;
end
DD_CMRD_WAIT : begin
uuuuu <= '0;
if (kjkjkjkjk) begin
if (zazaz) begin
current_state <= zxcvzxcv;
end
else begin
current_state <= DD_ACCUM;
end
end
end // case: DD_CMRD_WAIT
DD_ACCUM : begin
if (qwerty) begin
current_state <= DD_CMLLL;
end
else begin
current_state <= DD_CMRD;
end
end
DD_CMLLL : begin
lll_start <= 1'b1;
current_state <= DD_CMLLL_WAIT;
end
DD_CMLLL_WAIT : begin
lll_start <= '0;
end
EE_OP : begin
jjjj_left_oooo <= tgbyhn;
current_state <= AA_CMRD;
end
EE_NEXT_OOOO : begin
if (last_oooo) begin
current_state <= cvbncvbn;
end
else begin
end
end
FF_OP : begin
asdf <= 1'b1;
current_state <= CC_OP;
end
zxcvzxcv : begin
current_state <= cvbncvbn;
end
cvbncvbn : begin
if (dci_cur) begin
current_state <= IDLE;
cmd_proc_done <= 1'b1;
end
else if (crq_ready) begin
crq_start <= 1'b1;
crqcvbn <= complcvbn;
crq_proc_id <= proc_id_cur;
current_state <= IDLE;
cmd_proc_done <= 1'b1;
end
end // case: cvbncvbn
default : begin
current_state <= IDLE;
cmd_proc_done <= 1'b1;
end
endcase // unique case
end // else: !if(reset)
end // always _ff
endmodule // xxx_xxxxxx
verilog-mode-20161124.fd230e6/tests_ok/indent_unique_case-2.v 0000664 0000000 0000000 00000002344 13022141775 0023445 0 ustar 00root root 0000000 0000000 module testmod ();
always_comb begin
unique case (eeee)
ZERO[1:0] : begin
a = 1;
end // case: ZERO[1:0]
ONE[1:0] : begin
a = 1;
end // case: ONE[1:0]
TWO[1:0] : begin
a = 1;
end // case: TWO[1:0]
THREE[1:0] : begin
a = 1;
end // case: THREE[1:0]
endcase // unique case (eeee)
end // always_comb
always_ff @ (posedge clk) begin
if (reset) begin
current_state <= `TQ STATE0;
end // if (reset)
else begin
priority case (current_state)
STATE0 : begin
current_state <= `TQ STATE3;
end // case: STATE0
STATE1 : begin
current_state <= `TQ STATE3;
end // case: STATE1
STATE2 : begin
current_state <= `TQ STATE3;
end // case: STATE2
STATE3 : begin
current_state <= `TQ STATE0;
end // case: STATE3
default : current_state <= `TQ STATE0;
endcase // priority case (current_state)
end // else: !if(reset)
end // always_ff @
endmodule // testmod
verilog-mode-20161124.fd230e6/tests_ok/indent_unique_case.v 0000664 0000000 0000000 00000002451 13022141775 0023305 0 ustar 00root root 0000000 0000000 module foo;
// syntaxify the unique keyword correctly please...
always_comb (*) begin
case (f)
1 : 2;
endcase // case (f)
unique case(vlcnum)
0 : unique case(in.value1)
0 : out = 1; 1 : out = 3; 2 : out = 3; 3 : out = 4;
4 : out = 4; 5 : out = 5; 6 : out = 5; 7 : out = 6;
8 : out = 6; 9 : out = 7; 10: out = 7; 11: out = 8;
12 : out = 8; 13: out = 9; 14: out = 9; 15: out = 9;
endcase
1 :
unique
case(in.value1)
0 : out = 3;
1 : out = 3;
2 : out = 3;
3 : out = 3;
4 : out = 3;
5 : out = 4;
6 : out = 4;
7 : out = 4;
8 : out = 4;
9 : out = 5;
10 : out = 5;
11 : out = 6;
12 : out = 6;
13 : out = 6;
14 : out = 6;
endcase // case (in.value1)
endcase // case (in.value1)
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/indent_uvm.v 0000664 0000000 0000000 00000004052 13022141775 0021612 0 ustar 00root root 0000000 0000000 module uvm;
class simple_item extends uvm_sequence_item;
rand int unsigned addr;
rand int unsigned data;
rand int unsigned delay;
constraint c1 { addr < 16'h2000; }
constraint c2 { data < 16'h1000; }
// UVM automation macros for general objects
`uvm_object_utils_begin(simple_item)
a = b;
c = d;
`uvm_field_int(addr, UVM_ALL_ON)
`uvm_field_int(data, UVM_ALL_ON)
`uvm_field_int(delay, UVM_ALL_ON)
`uvm_object_utils_end
// Constructor
function new (string name = "simple_item");
super.new(name);
endfunction : new
endclass : simple_item
class mydata extends uvm_object;
string str;
mydata subdata;
int field;
myenum e1;
int queue[$];
`uvm_object_utils(mydata)
`uvm_object_utils_begin(mydata) //requires ctor with default args
`uvm_field_string(str, UVM_DEFAULT)
`uvm_field_object(subdata, UVM_DEFAULT)
`uvm_field_int(field, UVM_DEC) //use decimal radix
`uvm_field_enum(myenum, e1, UVM_DEFAULT)
`uvm_field_queue_int(queue, UVM_DEFAULT)
`uvm_object_utils_end
`uvm_object_param_utils_begin(mydata) //requires ctor with default args
`uvm_field_string(str, UVM_DEFAULT)
`uvm_field_object(subdata, UVM_DEFAULT)
`uvm_field_int(field, UVM_DEC) //use decimal radix
`uvm_field_enum(myenum, e1, UVM_DEFAULT)
`uvm_field_queue_int(queue, UVM_DEFAULT)
`uvm_object_utils_end
endclass
class my_trans extends uvm_sequence_item;
rand bit [127:0] data [];
//---> Configuration
`uvm_object_utils_begin(my_trans)
`uvm_field_array_int ( data, UVM_ALL_ON)
`uvm_object_utils_end
function new (string name = "my_trans", uvm_sequencer_base sequencer = null, uvm_sequence parent_seq = null);
super.new(name, sequencer, parent_seq);
endfunction : new
endclass : my_trans
endmodule // uvm
module tt;
initial begin
while (1) begin
`uvm_do_with(aa, {bb == 0;})
`uvm_do(cc)
`uvm_do(cc)
end // while (1)
end // initial begin
endmodule // tt
verilog-mode-20161124.fd230e6/tests_ok/indent_virtual_class.sv 0000664 0000000 0000000 00000000423 13022141775 0024037 0 ustar 00root root 0000000 0000000 // issue 928 - 'pure virtual' items in classes break indentation
package p:
virtual class c extends parent;
pure virtual protected task t(type_t a, type_t b);
function f(string s="");
blah;
endfunction:f
endclass
endpackage
verilog-mode-20161124.fd230e6/tests_ok/indent_warren.v 0000664 0000000 0000000 00000000075 13022141775 0022302 0 ustar 00root root 0000000 0000000 `include "x.h"
//
module x;
////
reg y;
endmodule // x
verilog-mode-20161124.fd230e6/tests_ok/inject_first.v 0000664 0000000 0000000 00000001255 13022141775 0022127 0 ustar 00root root 0000000 0000000 module ex_inject (i, o,/*AUTOARG*/
// Inputs
j
);
input i;
input j;
output o;
// Ok:
always @ (/*AS*/i or j)
o = i | j;
// No change:
always @ (j) o = i | j;
always @ (j or i or p) o = i | j;
// Instant
autoinst_lopaz_srpad pad
(.foo(bar),
.clk(newclk),
/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inouts
.pin (pin[w-1:0]),
// Inputs
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/inject_inst_empty_ports.v 0000664 0000000 0000000 00000001346 13022141775 0024423 0 ustar 00root root 0000000 0000000 module inject_inst_empty_ports;
logic [7:0] q;
logic [7:0] d;
logic clk, rst_n;
register r1 (.qb(), // unconnect output
/*AUTOINST*/
// Outputs
.q (q[7:0]),
// Inputs
.d (d[7:0]),
.clk (clk),
.rst_n (rst_n));
endmodule
module register (
output logic [7:0] q, qb,
input logic [7:0] d,
input logic clk, rst_n
/*AUTOARG*/);
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;
assign qb = ~q;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/inject_inst_endparen.v 0000664 0000000 0000000 00000001575 13022141775 0023636 0 ustar 00root root 0000000 0000000 module inject_inst_endparen;
logic [7:0] q;
logic [7:0] d;
logic clk, nreset;
register r1 (.rst_n(nreset),
/*AUTOINST*/
// Outputs
.q (q[7:0]),
// Inputs
.d (d[7:0]),
.clk (clk));
`if NEVER
register r1 (.q(qKEEP),
.d(dKEEP),
.clk(clkKEEP),
// This is the
// asynchronous reset
.rst_n(nreset)
/*AUTOINST*/);
`endif
endmodule
module register (
output logic [7:0] q,
input logic [7:0] d,
input logic clk, rst_n
/*AUTOARG*/);
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/inject_inst_net_case.v 0000664 0000000 0000000 00000002363 13022141775 0023617 0 ustar 00root root 0000000 0000000 module inject_inst_net_case (
output logic [7:0] q2,
input logic [7:0] d,
input logic clk, rst_n
/*AUTOARG*/);
logic [7:0] Q1;
register2 r2 (.q1(Q1), .ck(clk),
/*AUTOINST*/
// Outputs
.q2 (q2[7:0]),
// Inputs
.rst_n (rst_n));
register1 r1 (.q1(Q1), .ck(clk),
/*AUTOINST*/
// Inputs
.d (d[7:0]),
.rst_n (rst_n));
endmodule
module register2 (
output logic [7:0] q2,
input logic [7:0] q1,
input logic ck, rst_n
/*AUTOARG*/);
always_ff @(posedge ck or negedge rst_n)
if (!rst_n) q2 <= '0;
else q2 <= q1;
endmodule
module register1 (
output logic [7:0] q1,
input logic [7:0] d,
input logic ck, rst_n
/*AUTOARG*/);
always_ff @(posedge ck or negedge rst_n)
if (!rst_n) q1 <= '0;
else q1 <= d;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/inject_inst_param.v 0000664 0000000 0000000 00000001700 13022141775 0023130 0 ustar 00root root 0000000 0000000 module inject_inst_param;
parameter WIDTH = 8;
logic [WIDTH-1:0] q;
logic [WIDTH-1:0] d;
logic clk, rst_n;
register #(.WIDTH(WIDTH)) r1 (
/*AUTOINST*/
// Outputs
.q (q[WIDTH-1:0]),
// Inputs
.d (d[WIDTH-1:0]),
.clk (clk),
.rst_n (rst_n));
endmodule
module register #(parameter WIDTH=4) (
output logic [WIDTH-1:0] q,
input logic [WIDTH-1:0] d,
input logic clk, rst_n
/*AUTOARG*/);
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/inject_path.v 0000664 0000000 0000000 00000000745 13022141775 0021737 0 ustar 00root root 0000000 0000000 module inject_path;
logic [7:0] q;
logic [7:0] d;
logic clk, rst_n;
register r1 (
/*AUTOINST*/
// Outputs
.q (q[7:0]),
// Inputs
.d (d[7:0]),
.clk (clk),
.rst_n (rst_n));
endmodule
// Local Variables:
// mode: Verilog
// verilog-library-flags:("-f inject_path.f")
// End:
verilog-mode-20161124.fd230e6/tests_ok/inject_path_cmt.v 0000664 0000000 0000000 00000000746 13022141775 0022603 0 ustar 00root root 0000000 0000000 module comments_test;
logic [7:0] q1;
logic [7:0] d;
logic clk, rst_n;
register r1 (.q(q1),
.clk100(clk),
// Asynchronous reset
/*AUTOINST*/
// Inputs
.d (d[7:0]),
.clk (clk),
.rst_n (rst_n));
endmodule
// Local Variables:
// mode: Verilog
// verilog-library-flags:("-f inject_path.f")
// End:
verilog-mode-20161124.fd230e6/tests_ok/inject_path_sub.v 0000664 0000000 0000000 00000001513 13022141775 0022602 0 ustar 00root root 0000000 0000000 // Note module names don't match, this is intentional to check the .f file
module reg_core (
output logic [7:0] q,
input logic [7:0] d,
input logic clk, rst_n
/*AUTOARG*/);
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;
endmodule
module register (
output logic [7:0] q,
input logic [7:0] d,
input logic clk, rst_n
/*AUTOARG*/);
reg_core c1 (
/*AUTOINST*/
// Outputs
.q (q[7:0]),
// Inputs
.d (d[7:0]),
.clk (clk),
.rst_n (rst_n));
endmodule
verilog-mode-20161124.fd230e6/tests_ok/inst.v 0000664 0000000 0000000 00000000503 13022141775 0020414 0 ustar 00root root 0000000 0000000 module inst (/*AUTOARG*/
// Outputs
lower_out,
// Inputs
lower_inb, lower_ina
);
parameter param1;
parameter param2;
input lower_inb;
input lower_ina;
output lower_out;
wire lower_out = lower_ina | lower_inb;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/label_always.v 0000664 0000000 0000000 00000001400 13022141775 0022073 0 ustar 00root root 0000000 0000000 // bug 895 - labeling of always constructs
module example;
always
begin
end // always
always @(posedge clk)
begin
end // always @ (posedge clk)
always @*
begin
end // always @ *
always @(*)
begin
end // always @ (*)
always_comb
begin
end // always_comb
always_latch
begin
end // always_latch
always @( *)
begin
end // always @ ( *)
always @(* )
begin
end // always @ (* )
always_ff @(posedge clk)
begin
end // always_ff @ (posedge clk)
always @(*)
begin
end // always @ (*)
endmodule // example
// Local Variables:
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/label_class.sv 0000664 0000000 0000000 00000000163 13022141775 0022070 0 ustar 00root root 0000000 0000000 // Bug 888 -- verilog-label-be should remove existing comment labels before adding new ones
class c;
endclass // c
verilog-mode-20161124.fd230e6/tests_ok/label_do.v 0000664 0000000 0000000 00000000267 13022141775 0021207 0 ustar 00root root 0000000 0000000 // bug 842
module x;
do begin
end while(); // do begin
endmodule // x
// Local Variables:
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/label_function.v 0000664 0000000 0000000 00000003023 13022141775 0022423 0 ustar 00root root 0000000 0000000 module test();
// function with no lifetime, return-type, or port-list
function f0;
blah0;
endfunction // f0
// empty port-list
function f1();
blah1;
endfunction // f1
// non-empty portlist
function f2(stuff2);
blah2;
endfunction // f2
// test that ": function_identifier" remains unscathed
function f3;
endfunction : f3
// return type
function void f4;
blah4;
endfunction // f4
// return type with empty port-list.
function void f5();
int i;
begin
blah4;
end
endfunction // f5
// return type, non-empty portlist
// also check that a stale auto-comment gets removed
function void f6(stuff,
that,
spans,
lines);
blah5;
endfunction // f6
// test lifetime keywords 'automatic' and 'static'
function automatic f7();
endfunction // f7
// test a crazy-long function declaration
function static union packed signed {bit[1:0] a, bit[2:0] b} [5:0] f8(input ports, input ports, output ports);
endfunction // f8
// port-list that doesn't start on the same line as the function declaration
function automatic void f9
(int a,
int b);
endfunction // f9
// mismatched keyword
function f10;
endtask // unmatched end(function|task|module|primitive|interface|package|class|clocking)
// make sure previous screw-up doesn't affect future functions
function f11;
endfunction // f11
endmodule // test
verilog-mode-20161124.fd230e6/tests_ok/label_macro.v 0000664 0000000 0000000 00000000745 13022141775 0021707 0 ustar 00root root 0000000 0000000 // Bug 859 -- 'end' should label after a user/library-defined macro
// that isn't terminated with a semi-colon
class c;
`uvm_info(get_type_name(), "Digital power up.", UVM_MEDIUM)
fork
begin
end // fork begin
join
`made_up_macro (a, \
b, \
c)
begin: named_block
end // block: named_block
endclass // c
// Local Variables:
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/label_no_indent.v 0000664 0000000 0000000 00000000363 13022141775 0022557 0 ustar 00root root 0000000 0000000 // bug 841
module x;
always @*
begin
end // always @ *
endmodule // x
// Local Variables:
// verilog-indent-level-module: 0
// verilog-indent-begin-after-if: nil
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// End:
verilog-mode-20161124.fd230e6/tests_ok/label_task.v 0000664 0000000 0000000 00000002151 13022141775 0021541 0 ustar 00root root 0000000 0000000 module test();
// task with no lifetime, return-type, or port-list
task t0;
blah0;
endtask // t0
// empty port-list
task t1();
blah1;
endtask // t1
// non-empty portlist
task t2(stuff2);
blah2;
endtask // t2
// test that ": task_identifier" remains unscathed
task t3;
endtask : t3
// check that stale auto-label is overwritten
task t4(input port1, output port2, inout port3);
begin
blah blah blah;
end
endtask // t4
// test lifetime keywords 'automatic' and 'static'
task static t7();
endtask // t7
// test a more complete example
task automatic t8(input ports, input ports, output ports);
endtask // t8
// port-list that doesn't start on the same line as the task declaration
task automatic t9
(int a,
int b);
endtask // t9
// mismatched keyword
task t10;
endfunction // unmatched end(function|task|module|primitive|interface|package|class|clocking)
// make sure even the simplest test works after all the insanity
task t11;
endtask // t11
endmodule // test
verilog-mode-20161124.fd230e6/tests_ok/lavigne_instpath.v 0000664 0000000 0000000 00000001176 13022141775 0023005 0 ustar 00root root 0000000 0000000 module lavigne_instpath ();
/* lavigne_t1 AUTO_TEMPLATE (
.a(a1),
);
*/
lavigne_t1 m1 (/*AUTOINST*/
// Inputs
.a (a1)); // Templated
/* lavigne_t2 AUTO_TEMPLATE (
.b(b2),
);
*/
lavigne_t2 m2 (/*AUTOINST*/
// Inputs
.b (b2)); // Templated
endmodule
// verilkkkkkkkog-library-directories:("*/")
//(load-file "/usr/local/common/site-lisp/local/verilog-mode.el")
// Local Variables:
// verilog-library-flags:("-y lavigne_instpath/")
// End:
verilog-mode-20161124.fd230e6/tests_ok/lavigne_instpath/ 0000775 0000000 0000000 00000000000 13022141775 0022611 5 ustar 00root root 0000000 0000000 verilog-mode-20161124.fd230e6/tests_ok/lavigne_instpath/lavigne_t1.v 0000664 0000000 0000000 00000000052 13022141775 0025026 0 ustar 00root root 0000000 0000000 module lavigne_t1 (a);
input a;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/lavigne_instpath/lavigne_t2.v 0000664 0000000 0000000 00000000052 13022141775 0025027 0 ustar 00root root 0000000 0000000 module lavigne_t2 (b);
input b;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/lineup.v 0000664 0000000 0000000 00000000142 13022141775 0020732 0 ustar 00root root 0000000 0000000 module ocnSwitchClockGen(output reg ocnSwitchClock);
parameter ocnSwitchClockPeriod = 2000;
verilog-mode-20161124.fd230e6/tests_ok/local_vmode.x 0000664 0000000 0000000 00000000365 13022141775 0021733 0 ustar 00root root 0000000 0000000 module local_vmode ();
local_vmode_sub sub (/*AUTOINST*/
// Inputs
.in (in));
endmodule
// Local Variables:
// mode: Verilog
// verilog-library-flags:("+libext+.x")
// End:
verilog-mode-20161124.fd230e6/tests_ok/local_vmode_sub.x 0000664 0000000 0000000 00000000133 13022141775 0022575 0 ustar 00root root 0000000 0000000 module local_vmode_sub (input in);
endmodule
// Local Variables:
// mode: Verilog
// End:
verilog-mode-20161124.fd230e6/tests_ok/mac_autosense_dot.v 0000664 0000000 0000000 00000000432 13022141775 0023134 0 ustar 00root root 0000000 0000000 //From: Michael McNamara
//Date: Tue, 27 Jun 2000 04:38:32 -0700 (PDT)
module x;
always @ (/*AS*/top.agc_tool.adc_dta_i or top.agc_tool.adc_preagc_dta_i) begin
agctoolerr = top.agc_tool.adc_dta_i / top.agc_tool.adc_preagc_dta_i;
end
endmodule
verilog-mode-20161124.fd230e6/tests_ok/mac_test2.sv 0000664 0000000 0000000 00000000425 13022141775 0021506 0 ustar 00root root 0000000 0000000 module foobar;
sequence s_1;
{txd, txdk} && (ppd == 3'b000) && !txe;
endsequence // s_1
sequence s_phy_transmitting;
{rxd, rxdk} &&
((ppd == 3'b000) || (ppd == 3'b001))
&& rxv;
endsequence // s_phy_transmitting
endmodule
verilog-mode-20161124.fd230e6/tests_ok/mac_test2.v 0000664 0000000 0000000 00000000425 13022141775 0021323 0 ustar 00root root 0000000 0000000 module foobar;
sequence s_1;
{txd, txdk} && (ppd == 3'b000) && !txe;
endsequence // s_1
sequence s_phy_transmitting;
{rxd, rxdk} &&
((ppd == 3'b000) || (ppd == 3'b001))
&& rxv;
endsequence // s_phy_transmitting
endmodule
verilog-mode-20161124.fd230e6/tests_ok/more_params.v 0000664 0000000 0000000 00000003151 13022141775 0021746 0 ustar 00root root 0000000 0000000 module InstName (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [7:0] in;
output [7:0] out;
wire [7:0] out = ~in;
endmodule // bottm
module top (/*AUTOARG*/
// Outputs
outgo,
// Inputs
incom
);
input [31:0] incom;
output [31:0] outgo;
/* AUTO_LISP(defun getparam2 (strg)
(string-match "[^0-9]*[0-9]+[^0-9]*\\([0-9]+\\)" strg)
(match-string 1 strg))*/
/* InstName AUTO_TEMPLATE (
.out (@),
.in (@"(getparam2 vl-cell-name)"),
);
*/
InstName BT0_2 (/*AUTOINST*/
// Outputs
.out (0), // Templated
// Inputs
.in (2)); // Templated
InstName BT1_3 (/*AUTOINST*/
// Outputs
.out (1), // Templated
// Inputs
.in (3)); // Templated
InstName BT2_5 (/*AUTOINST*/
// Outputs
.out (2), // Templated
// Inputs
.in (5)); // Templated
InstName BT3_9 (/*AUTOINST*/
// Outputs
.out (3), // Templated
// Inputs
.in (9)); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests_ok/morrison.v 0000664 0000000 0000000 00000000370 13022141775 0021311 0 ustar 00root root 0000000 0000000 `define XYZ 4'ha
module test ();
always @(/*AUTOSENSE*/r or x)
begin
casex(x)
5: d = {r, `XYZ };
endcase
end
endmodule // test
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/params_multiline_msg618.v 0000664 0000000 0000000 00000000632 13022141775 0024114 0 ustar 00root root 0000000 0000000 module testMultiLineParams (/*AUTOARG*/) ;
`include "params_multiline_msg618_inc.vh"
reg comboIn, comboOut;
// expect AUTOSENSE to be comboIn only, no params
always @ ( /*AUTOSENSE*/comboIn) begin
comboOout = param1 & param2 & param3 & comboIn;
end
endmodule // foo
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/params_multiline_msg618_inc.vh 0000664 0000000 0000000 00000000242 13022141775 0025112 0 ustar 00root root 0000000 0000000 parameter
// full line comment
param1 = 1'b1, // trailing comment
param2 = 1'b0, /* trailing comment */
// full line comment
param3 = 1'b1;
verilog-mode-20161124.fd230e6/tests_ok/property_test.v 0000664 0000000 0000000 00000003621 13022141775 0022366 0 ustar 00root root 0000000 0000000
//////////////////////////////////////////////////////////////////////////////
//
// Main
//
//////////////////////////////////////////////////////////////////////////////
module test();
integer count;
bit test_clk;
// Create a test clock
always #01.8 test_clk = ~test_clk;
//**********************************************************************
// Testing.
// Shift a moving set of ones up the input vector. At each shift
// the outputs should change, which is checked by the assertions
// below. This test doesnt care which output changes, as that was
// checked to be accurate by formal means.
//**********************************************************************
initial begin
count=0;
end
always @(posedge test_clk) begin
count++;
end
//**********************************************************************
// SV assertions
//**********************************************************************
property p_lane_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(lane_inputs) |-> !$stable(lane_outputs);
endproperty
a_lane_output_change_on_input_change: assert property (p_lane_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (lane)",
lane_inputs);
end // UNMATCHED !!
endproperty //FIXME
property p_sup_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(sup_inputs) |-> !$stable(sup_outputs);
endproperty
a_sup_output_change_on_input_change: assert property (p_sup_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (sup)",
sup_inputs);
end
endproperty
endmodule // test
verilog-mode-20161124.fd230e6/tests_ok/reversed_bits.v 0000664 0000000 0000000 00000001234 13022141775 0022301 0 ustar 00root root 0000000 0000000 module lbnsub
(/*AUTOARG*/
// Outputs
outgo,
// Inputs
income
);
input [7:4] income;
output [7:4] outgo;
wire [7:4] outgo = income;
endmodule
module lbm
(/*AUTOARG*/
// Outputs
outgo,
// Inputs
income
);
input [7:4] income;
output [7:4] outgo;
/*
lbnsub AUTO_TEMPLATE (
// Inputs
.income (income[4:7]));
*/
lbnsub lbnsub (/*AUTOINST*/
// Outputs
.outgo (outgo[7:4]),
// Inputs
.income (income[4:7])); // Templated
endmodule
verilog-mode-20161124.fd230e6/tests_ok/set_membership.sv 0000664 0000000 0000000 00000002041 13022141775 0022627 0 ustar 00root root 0000000 0000000 import avm_pkg::*;
import tinyalu_pkg::*;
module top;
alu_operation req;
string msg;
integer i;
initial begin
$display ("---- A or B inside {0,8'hFF} ----");
for (i = 1; i<=5; i++) begin
req = new();
assert( a() with {A} );
req.randomize()
with
{
A inside {0,8'hFF};
B inside {0,8'hFF};
};
$sformat (msg,"ALU Request: %s", req.convert2string());
avm_report_message("TOP",msg);
$display;
$display ("---- op inside [add_op : mul_op] ----");
for (i = 1; i<=10; i++) begin
req = new();
assert(
req.randomize() with
{
op inside {[add_op : mul_op]};
}
);
$sformat (msg,"ALU Request: %s", req.convert2string());
avm_report_message("TOP",msg);
end // for (i = 1; i<=10; i++)
end // initial begin
endmodule // req_reader
verilog-mode-20161124.fd230e6/tests_ok/singh.v 0000664 0000000 0000000 00000002744 13022141775 0020560 0 ustar 00root root 0000000 0000000 // HERE IS THE TEST CASE
module bt (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [7:0] in;
output [7:0] out;
wire [7:0] out = ~in;
endmodule // bottm
module top (/*AUTOARG*/
// Outputs
outgo,
// Inputs
incom
);
input [31:0] incom;
output [31:0] outgo;
/* bt AUTO_TEMPLATE (
.in (incom[@"(+ (* 8 @) 7)":@"(* 8 @)"]),
.out (outgo[@"(concat (int-to-string (+ (* 8 @) 7)) \":\" (int-to-string ( * 8 @)))"]));
*/
bt BT0 (/*AUTOINST*/
// Outputs
.out (outgo[7:0]), // Templated
// Inputs
.in (incom[7:0])); // Templated
bt BT1 (/*AUTOINST*/
// Outputs
.out (outgo[15:8]), // Templated
// Inputs
.in (incom[15:8])); // Templated
bt BT2 (/*AUTOINST*/
// Outputs
.out (outgo[23:16]), // Templated
// Inputs
.in (incom[23:16])); // Templated
bt BT3 (/*AUTOINST*/
// Outputs
.out (outgo[31:24]), // Templated
// Inputs
.in (incom[31:24])); // Templated
endmodule // top
verilog-mode-20161124.fd230e6/tests_ok/sol_asense.v 0000664 0000000 0000000 00000005200 13022141775 0021571 0 ustar 00root root 0000000 0000000 module x (/*AUTOARG*/
// Inputs
MIERHW, MBOOTH_P, CEIopMADH_E_D2_R, CEIopMAZH_E_D2_R, DDATAH, DIV2HI, HI_R, MCLA, MCLASH,
MULTSHCYC, MULTUSCYC, HI_P
);
input [18:0] MIERHW;
integer i;
integer MTEMP1;
integer MTEMP2;
input MBOOTH_P;
input CEIopMADH_E_D2_R;
input CEIopMAZH_E_D2_R;
input DDATAH;
input DIV2HI;
input HI_R;
input MCLA;
input MCLASH;
input MULTSHCYC;
input MULTUSCYC;
input HI_P;
/*AUTOREG*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
always @(/*AUTOSENSE*/MIERHW) begin
for (i=0; i<=5; i=i+1) begin
MTEMP1[3:0] = {MIERHW[i*3+3],
MIERHW[i*3+2],
MIERHW[i*3+1],
MIERHW[i*3+0]};
casex (MTEMP1)
4'b0000: MTEMP2 = 4'b0101; // +0
4'b0001: MTEMP2 = 4'b0001; // +1
4'b0010: MTEMP2 = 4'b0001; // +1
4'b0011: MTEMP2 = 4'b0010; // +2
4'b0100: MTEMP2 = 4'b0010; // +2
4'b0101: MTEMP2 = 4'b0100; // +3
4'b0110: MTEMP2 = 4'b0100; // +3
4'b0111: MTEMP2 = 4'b1000; // +4
4'b1000: MTEMP2 = 4'b0111; // -4
4'b1001: MTEMP2 = 4'b1011; // -3
4'b1010: MTEMP2 = 4'b1011; // -3
4'b1011: MTEMP2 = 4'b1101; // -2
4'b1100: MTEMP2 = 4'b1101; // -2
4'b1101: MTEMP2 = 4'b1110; // -1
4'b1110: MTEMP2 = 4'b1110; // -1
4'b1111: MTEMP2 = 4'b1010; // -0
endcase
end
{MBOOTH_P[i*4+3],
MBOOTH_P[i*4+2],
MBOOTH_P[i*4+1],
MBOOTH_P[i*4+0]} = MTEMP2[3:0];
end
// always @(/*AUTOnotSENSE*/
// __CEIopMADH_E_D2_R or __CEIopMAZH_E_D2_R or __DIV2HI or
// __MULTUSCYC or __MULTSHCYC or
// __DDATAH or __HI_R or __MCLA or __MCLASH) begin
// always @(/*AUTOSENSE*/DDATAH or HI_R or MCLA or MCLASH) begin
`define DMCLASH MCLASH
`define DCONST 1'b1
always @(/*AUTOSENSE*/CEIopMADH_E_D2_R or CEIopMAZH_E_D2_R or DDATAH or DIV2HI or MCLA or MCLASH
or MULTSHCYC or MULTUSCYC) begin
case (1'b1)
CEIopMADH_E_D2_R: HI_P = MCLA;
CEIopMAZH_E_D2_R: HI_P = MCLA;
DIV2HI: HI_P = DDATAH;
MULTUSCYC: HI_P = MCLA;
MULTSHCYC: HI_P = `DMCLASH;
default: HI_P = `DCONST;
endcase
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
verilog-mode-20161124.fd230e6/tests_ok/src_frag.vs 0000664 0000000 0000000 00000004450 13022141775 0021415 0 ustar 00root root 0000000 0000000 module src_frag (
input logic inp_signal_0, // Input Signal 0
input logic inp_signal_1, // Input Signal 1
input logic inp_signal_2, // Input Signal 2
input logic [10:0] inp_signal_3; // Input Signal 3
input logic inp_signal_4, // Input Signal 4
output logic outp_signal_0, // Output Signal 0
inout logic test,
output logic outp_signal_1 // Output Signal 1
);
logic [7:0] local_0; // Local Signal 0
logic local_1; // Local Signal 1
logic local_3; // Local Signal 3
var logic local_4; // Local Signal 4
var logic local_5; // Local Signal 5
logic signed [1:0] local_6;
logic local_1; // Local Signal 1
input logic in_lg;
inout logic io_lg;
output logic o_lg;
ref logic r_lg;
const logic c_rg;
static logic s_rg;
protected logic p_lg;
local logic l_lg;
localparam logic lp_lg = 23;
parameter logic p_lg = 32;
typedef logic td_lg;
input wire foo;
logic local_3; // Local Signal 3
var logic local_5; // Local Signal 5
byte B;
shortint si;
int f;
longint li;
integer I;
int unsigned uI;
time t;
bit b;
logic l;
reg r;
shortreal sR;
real R;
realtime Rt;
supply0 s0;
supply1 s1;
tri tr;
triand tra;
trior tro;
trireg trr;
tri0 tr0;
tri1 tr1;
uwire uw;
wire w;
wand wa;
wor wo;
string s;
event e;
chandle ch;
virtual v;
enum en;
genvar g;
struct st;
union u;
mailbox mb;
semaphore sm;
defparam v_lg = 56;
endmodule // src_frag
// Local Variables:
// mode: Verilog
// End:
verilog-mode-20161124.fd230e6/tests_ok/sv_import.v 0000664 0000000 0000000 00000000312 13022141775 0021457 0 ustar 00root root 0000000 0000000 module dpi_test ();
/* FIXME
import "DPI-C" context task c_task (input int i,
output int o);
logic [7:0] byte_array[1:20];
*/
endmodule // dpi_test
verilog-mode-20161124.fd230e6/tests_ok/t_autoinst_def_clk.v 0000664 0000000 0000000 00000001531 13022141775 0023301 0 ustar 00root root 0000000 0000000 module t_autoinst_def_clk
(/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input a, // To sub of sub.v
input b, // To sub of sub.v
input clk, // To sub of sub.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output c // From sub of sub.v
// End of automatics
);
sub sub
(/*AUTOINST*/
// Outputs
.c (c),
// Inputs
.clk (clk),
.a (a),
.b (b));
endmodule // sdc_wombat
module sub
(input clk,
input a,
input b,
output c
);
clocking cb
@(posedge clk);
endclocking
default clocking cb;
endmodule
verilog-mode-20161124.fd230e6/tests_ok/task.v 0000664 0000000 0000000 00000000511 13022141775 0020400 0 ustar 00root root 0000000 0000000 module foo(input bit [3:0] def,
input bit ghi,
input bit [1:0] jkl);
task cba(input bit [3:0] a,
input b,
c);
endtask // cba
task abc(input bit [3:0] def,
input bit ghi,
input bit [1:0] jkl);
endtask // abc
endmodule // foo
verilog-mode-20161124.fd230e6/tests_ok/testcase.sv 0000664 0000000 0000000 00000000401 13022141775 0021432 0 ustar 00root root 0000000 0000000 `define moo 1
class foo;
extern function void bar();
endclass: foo
function void foo::bar();
int variable;
endfunction: bar
`define moo 1
class fu;
extern function void br();
endclass: fu
function void fu::br();
int variable;
endfunction: br
verilog-mode-20161124.fd230e6/tests_ok/testcases.v 0000664 0000000 0000000 00000013252 13022141775 0021442 0 ustar 00root root 0000000 0000000 //Verilint 182 off // WARNING: Illegal statement for synthesis: $realtobits (in1)
//Verilint 311 off // WARNING: Converting real to unsigned: $realtobits (in1)
//Verilint 20 off // WARNING: Assign statement may not be synthesizable: assign out7[i] = ...;
//Verilint 599 off // WARNING: This construct is not supported by Synopsys
//Verilint 433 off // WARNING: More than one top level module
//Verilint 71 off // WARNING: Case statement without default clause
module testmodule (/*AUTOARG*/
// Outputs
out1, out2, out3, out4, out5, out7, out8, outb2, outb3, outb4, outb6, outb7, outb8, outb9,
outb10, outw1, outw2, outw3,
// Inputs
in1, in2, in3, in4, in5
);
function [2:0] ffs;
input [2:0] in;
ffs = in & 3'b010;
endfunction
task show;
input [2:0] in;
begin
$display ("Hi %x", in);
end
endtask
input [2:0] in1,in2,in3,in4,in5;
output [2:0] out1, out2,out3,out4,out5,out7,out8;
output outb2,outb3,outb4,outb6,outb7,outb8,outb9,outb10;
output [7:0] outw1,outw2,outw3;
reg [2:0] memarry [0:2];
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0] out1;
reg [2:0] out2;
reg [2:0] out3;
reg [2:0] out4;
reg [2:0] out5;
reg [2:0] out8;
reg outb2;
reg outb3;
reg outb4;
reg outb6;
reg outb7;
reg [7:0] outw1;
reg [7:0] outw2;
reg [7:0] outw3;
// End of automatics
wire outb8=1'b1, outb9=|{in1[0],in2[0]}, outb10=1'b0;
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
:ignore_label
out1 = $realtobits(in1);
out2 = ffs(in1 | (in2) );
out3 = ffs /*check*/ (in2);
$display ("chk ", in1);
show (in4);
if (|in3) out4=1; else out4=0;
end
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in5) begin
casex ({in5[1:0], (3'b010==in2)})
3'bx_1_0: out5=3'b000;
3'bx_1_1: out5=3'b010;
3'bx_0_x: out5=3'b100;
endcase
casex ({in3[in1]})
1'bx: out5=3'b000;
endcase
end
/*AUTO_CONSTANT (`temp) */
`define temp 3'b010
always @(/*AUTOSENSE*/in3) begin
outb6 = (in3 == `temp);
end
integer i;
reg [2:0] out7;
always @ (/*AUTOSENSE*/in1) begin
for (i=0; i<3; i=i+1) begin
assign out7[i] = ~in1[i];
end
end
always @ (/*AUTOSENSE*/in1 or in2 or in3) begin
{outw1 [ffs(in1)], outw2 [ffs(in2)]} = 2'b10;
{outw3[(|in1)?in2:in3], outb2} = 2'b10;
end
initial memarry[0] = in2;
always @ (/*AUTOSENSE*/ /*memory or*/ in1) begin
$display (memarry[in1]);
end
always @(/*AUTOSENSE*/in1 or in2)
casex(in1[1:0]) // synopsys full_case parallel_case
2'b01 : out8 = 3'b001;
2'b10 : out8 = 3'b010;
default
out8 = in2;
endcase
parameter READ = 3'b111,
//WRITE = 3'b111,
CFG = 3'b010;
//supply1 one;
always @(/*AUTOSENSE*/in1 or in2) begin
outb7 = (in1==READ) || (in2==CFG);
end
always @(/*AUTOSENSE*/in1) begin
if (|in1) $display("We're at %t\n",$time);
end // case: default
`define shift_instr 5'b01011
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4 or in5 or outw1)
/*AUTO_CONSTANT(`shift_instr)*/
begin: label_no_sense
casex (outw1) // synopsys full_case parallel_case
{`shift_instr,3'bxxx}:
outb3 = in3[0];
8'b00001x10: outb3 = in4[0];
8'b00110011:
if (in5[0])
outb3 = in1[0];
else
outb3 = in2[1];
default
outb3 = in4[0];
endcase
end
parameter WIDLE = 0; // No Manual Write Burst
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
case(1'b1)
in2[WIDLE]:
outb4 = in1[0];
in3[in4]:
outb4 = in1[0];
default:
outb4 = 1'bx;
endcase
end
endmodule
module darren_jones_2 (/*AUTOARG*/
// Outputs
next_WSTATE,
// Inputs
WSTATE
);
input [1:0] WSTATE;
output [1:0] next_WSTATE;
reg [1:0] next_WSTATE;
parameter
WIDLE = 0, // No Manual Write Burst
WCB0 = 1; // 1st of the 4 Manual Write Burst
always @ (/*AUTOSENSE*/WSTATE) begin
next_WSTATE = 2'b0;
case (1'b1)
WSTATE[WIDLE]:
next_WSTATE[1'b0] = 1'b1;
WSTATE[WCB0]:
next_WSTATE[WCB0] = 1'b1;
endcase
end
endmodule
module darren_jones_3 (/*AUTOARG*/
// Outputs
var1,
// Inputs
state
);
input [2:1] state;
output var1;
reg var1;
parameter
IDLE = 1,
CAS1 = 2;
always @(/*AUTOSENSE*/state) begin
case (1'b1)
state[IDLE] : begin
var1 = 1'b1;
end
state[CAS1] : begin
var1 = 1'b1;
end
default : begin
var1 = 1'b1;
end
endcase
end
always @(/*AUTOSENSE*/add or lo or mc_32pff or mc_losel or slo or var1) begin
case(mc_losel)
6'b000001: lo_mux = mc_32pff ? {add[39:0],lo[31:8]} :
{add[7:0],lo[63:8]};
6'b010000: lo_mux = lo;
6'b100000: lo_mux = var1 ? IDLE : slo;
endcase
end // always @ (...
endmodule
verilog-mode-20161124.fd230e6/tests_ok/tss_max32.v 0000664 0000000 0000000 00000002725 13022141775 0021272 0 ustar 00root root 0000000 0000000 // $Id: tss_max32.v,v 1.6 1999/01/20 17:34:54 wsnyder Exp $
//============================================================================
`time_scale
module tss_max32 (/*AUTOARG*/
// Outputs
max,
// Inputs
a, b
);
//======================================================================
// Inputs/Outputs
//======================================================================
input [31:0] a; // Time a
input [31:0] b; // Time b
output [31:0] max; // MAX (a,b)
//======================================================================
// Automatic Wire/Register Declarations
//======================================================================
/*AUTOREG*/
//======================================================================
// Comparison
//======================================================================
wire alessb; // a
;; Wilson Snyder
;; http://www.verilog.com
;; http://www.veripool.org
;; Created: 3 Jan 1996
;; Keywords: languages
;; Yoni Rabkin contacted the maintainer of this
;; file on 19/3/2008, and the maintainer agreed that when a bug is
;; filed in the Emacs bug reporting system against this file, a copy
;; of the bug report be sent to the maintainer's email address.
;; This code supports Emacs 21.1 and later
;; And XEmacs 21.1 and later
;; Please do not make changes that break Emacs 21. Thanks!
;;
;;
;; This file is part of GNU Emacs.
;; GNU Emacs is free software: you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation, either version 3 of the License, or
;; (at your option) any later version.
;; GNU Emacs is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GNU Emacs. If not, see .
;;; Commentary:
;; USAGE
;; =====
;; A major mode for editing Verilog and SystemVerilog HDL source code (IEEE
;; 1364-2005 and IEEE 1800-2012 standards). When you have entered Verilog
;; mode, you may get more info by pressing C-h m. You may also get online
;; help describing various functions by: C-h f
;; KNOWN BUGS / BUG REPORTS
;; =======================
;; SystemVerilog is a rapidly evolving language, and hence this mode is
;; under continuous development. Please report any issues to the issue
;; tracker at
;;
;; http://www.veripool.org/verilog-mode
;;
;; Please use verilog-submit-bug-report to submit a report; type C-c
;; C-b to invoke this and as a result we will have a much easier time
;; of reproducing the bug you find, and hence fixing it.
;; INSTALLING THE MODE
;; ===================
;; An older version of this mode may be already installed as a part of
;; your environment, and one method of updating would be to update
;; your Emacs environment. Sometimes this is difficult for local
;; political/control reasons, and hence you can always install a
;; private copy (or even a shared copy) which overrides the system
;; default.
;; You can get step by step help in installing this file by going to
;;
;; The short list of installation instructions are: To set up
;; automatic Verilog mode, put this file in your load path, and put
;; the following in code (please un comment it first!) in your
;; .emacs, or in your site's site-load.el
;; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
;; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
;; Be sure to examine at the help for verilog-auto, and the other
;; verilog-auto-* functions for some major coding time savers.
;;
;; If you want to customize Verilog mode to fit your needs better,
;; you may add the below lines (the values of the variables presented
;; here are the defaults). Note also that if you use an Emacs that
;; supports custom, it's probably better to use the custom menu to
;; edit these. If working as a member of a large team these settings
;; should be common across all users (in a site-start file), or set
;; in Local Variables in every file. Otherwise, different people's
;; AUTO expansion may result different whitespace changes.
;;
;; ;; Enable syntax highlighting of **all** languages
;; (global-font-lock-mode t)
;;
;; ;; User customization for Verilog mode
;; (setq verilog-indent-level 3
;; verilog-indent-level-module 3
;; verilog-indent-level-declaration 3
;; verilog-indent-level-behavioral 3
;; verilog-indent-level-directive 1
;; verilog-case-indent 2
;; verilog-auto-newline t
;; verilog-auto-indent-on-newline t
;; verilog-tab-always-indent t
;; verilog-auto-endcomments t
;; verilog-minimum-comment-distance 40
;; verilog-indent-begin-after-if t
;; verilog-auto-lineup 'declarations
;; verilog-highlight-p1800-keywords nil
;; verilog-linter "my_lint_shell_command"
;; )
;;; History:
;;
;; See commit history at http://www.veripool.org/verilog-mode.html
;; (This section is required to appease checkdoc.)
;;; Code:
;;
;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "__VMVERSION__-__VMREVISION__-__VMPACKAGER__"
"Version of this Verilog mode.")
(defconst verilog-mode-release-emacs nil
"If non-nil, this version of Verilog mode was released with Emacs itself.")
(defun verilog-version ()
"Inform caller of the version of this file."
(interactive)
(message "Using verilog-mode version %s" verilog-mode-version))
;; Insure we have certain packages, and deal with it if we don't
;; Be sure to note which Emacs flavor and version added each feature.
(eval-when-compile
;; Provide stuff if we are XEmacs
(when (featurep 'xemacs)
(condition-case nil
(require 'easymenu)
(error nil))
(condition-case nil
(require 'regexp-opt)
(error nil))
;; Bug in 19.28 through 19.30 skeleton.el, not provided.
(condition-case nil
(load "skeleton")
(error nil))
(condition-case nil
(if (fboundp 'when)
nil ; fab
(defmacro when (cond &rest body)
(list 'if cond (cons 'progn body))))
(error nil))
(condition-case nil
(if (fboundp 'unless)
nil ; fab
(defmacro unless (cond &rest body)
(cons 'if (cons cond (cons nil body)))))
(error nil))
(condition-case nil
(if (fboundp 'store-match-data)
nil ; fab
(defmacro store-match-data (&rest _args) nil))
(error nil))
(condition-case nil
(if (fboundp 'char-before)
nil ; great
(defmacro char-before (&rest _body)
(char-after (1- (point)))))
(error nil))
(condition-case nil
(if (fboundp 'when)
nil ; fab
(defsubst point-at-bol (&optional N)
(save-excursion (beginning-of-line N) (point))))
(error nil))
(condition-case nil
(if (fboundp 'when)
nil ; fab
(defsubst point-at-eol (&optional N)
(save-excursion (end-of-line N) (point))))
(error nil))
(condition-case nil
(require 'custom)
(error nil))
(condition-case nil
(if (fboundp 'match-string-no-properties)
nil ; great
(defsubst match-string-no-properties (num &optional string)
"Return string of text matched by last search, without text properties.
NUM specifies which parenthesized expression in the last regexp.
Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
Zero means the entire text matched by the whole regexp or whole string.
STRING should be given if the last search was by `string-match' on STRING."
(if (match-beginning num)
(if string
(let ((result
(substring string
(match-beginning num) (match-end num))))
(set-text-properties 0 (length result) nil result)
result)
(buffer-substring-no-properties (match-beginning num)
(match-end num)
(current-buffer)))))
)
(error nil))
(if (and (featurep 'custom) (fboundp 'custom-declare-variable))
nil ; We've got what we needed
;; We have the old custom-library, hack around it!
(defmacro defgroup (&rest _args) nil)
(defmacro customize (&rest _args)
(message
"Sorry, Customize is not available with this version of Emacs"))
(defmacro defcustom (var value doc &rest _args)
`(defvar ,var ,value ,doc))
)
(if (fboundp 'defface)
nil ; great!
(defmacro defface (var values doc &rest _args)
`(make-face ,var))
)
(if (and (featurep 'custom) (fboundp 'customize-group))
nil ; We've got what we needed
;; We have an intermediate custom-library, hack around it!
(defmacro customize-group (var &rest _args)
`(customize ,var))
)
(defvar inhibit-modification-hooks)
(defvar inhibit-point-motion-hooks)
(defvar deactivate-mark)
)
;;
;; OK, do this stuff if we are NOT XEmacs:
(unless (featurep 'xemacs)
(unless (fboundp 'region-active-p)
(defmacro region-active-p ()
`(and transient-mark-mode mark-active))))
)
;; Provide a regular expression optimization routine, using regexp-opt
;; if provided by the user's elisp libraries
(eval-and-compile
;; The below were disabled when GNU Emacs 22 was released;
;; perhaps some still need to be there to support Emacs 21.
(if (featurep 'xemacs)
(if (fboundp 'regexp-opt)
;; regexp-opt is defined, does it take 3 or 2 arguments?
(if (fboundp 'function-max-args)
(let ((args (function-max-args `regexp-opt)))
(cond
((eq args 3) ; It takes 3
(condition-case nil ; Hide this defun from emacses
; with just a two input regexp
(defun verilog-regexp-opt (a b)
"Deal with differing number of required arguments for `regexp-opt'.
Call `regexp-opt' on A and B."
(regexp-opt a b t))
(error nil))
)
((eq args 2) ; It takes 2
(defun verilog-regexp-opt (a b)
"Call `regexp-opt' on A and B."
(regexp-opt a b))
)
(t nil)))
;; We can't tell; assume it takes 2
(defun verilog-regexp-opt (a b)
"Call `regexp-opt' on A and B."
(regexp-opt a b))
)
;; There is no regexp-opt, provide our own
(defun verilog-regexp-opt (strings &optional paren _shy)
(let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
(concat open (mapconcat 'regexp-quote strings "\\|") close)))
)
;; Emacs.
(defalias 'verilog-regexp-opt 'regexp-opt)))
;; emacs >=22 has looking-back, but older emacs and xemacs don't.
;; This function is lifted directly from emacs's subr.el
;; so that it can be used by xemacs.
;; The idea for this was borrowed from org-mode via this link:
;; https://lists.gnu.org/archive/html/emacs-orgmode/2009-12/msg00032.html
(eval-and-compile
(cond
((fboundp 'looking-back)
(defalias 'verilog-looking-back 'looking-back))
(t
(defun verilog-looking-back (regexp limit &optional greedy)
"Return non-nil if text before point matches regular expression REGEXP.
Like `looking-at' except matches before point, and is slower.
LIMIT if non-nil speeds up the search by specifying a minimum
starting position, to avoid checking matches that would start
before LIMIT.
If GREEDY is non-nil, extend the match backwards as far as
possible, stopping when a single additional previous character
cannot be part of a match for REGEXP. When the match is
extended, its starting position is allowed to occur before
LIMIT.
As a general recommendation, try to avoid using `looking-back'
wherever possible, since it is slow."
(let ((start (point))
(pos
(save-excursion
(and (re-search-backward (concat "\\(?:" regexp "\\)\\=") limit t)
(point)))))
(if (and greedy pos)
(save-restriction
(narrow-to-region (point-min) start)
(while (and (> pos (point-min))
(save-excursion
(goto-char pos)
(backward-char 1)
(looking-at (concat "\\(?:" regexp "\\)\\'"))))
(setq pos (1- pos)))
(save-excursion
(goto-char pos)
(looking-at (concat "\\(?:" regexp "\\)\\'")))))
(not (null pos)))))))
(eval-and-compile
(cond
((fboundp 'restore-buffer-modified-p)
;; Faster, as does not update mode line when nothing changes
(defalias 'verilog-restore-buffer-modified-p 'restore-buffer-modified-p))
(t
(defalias 'verilog-restore-buffer-modified-p 'set-buffer-modified-p))))
(eval-and-compile
;; Both xemacs and emacs
(condition-case nil
(require 'diff) ; diff-command and diff-switches
(error nil))
(condition-case nil
(require 'compile) ; compilation-error-regexp-alist-alist
(error nil))
(condition-case nil
(unless (fboundp 'buffer-chars-modified-tick) ; Emacs 22 added
(defmacro buffer-chars-modified-tick () (buffer-modified-tick)))
(error nil))
;; Added in Emacs 24.1
(condition-case nil
(unless (fboundp 'prog-mode)
(define-derived-mode prog-mode fundamental-mode "Prog"))
(error nil))
;; Added in Emacs 25.1
(condition-case nil
(unless (fboundp 'forward-word-strictly)
(defalias 'forward-word-strictly 'forward-word))
(error nil)))
(eval-when-compile
(defun verilog-regexp-words (a)
"Call `regexp-opt' with word delimiters for the words A."
(concat "\\<" (verilog-regexp-opt a t) "\\>")))
(defun verilog-regexp-words (a)
"Call `regexp-opt' with word delimiters for the words A."
;; The FAQ references this function, so user LISP sometimes calls it
(concat "\\<" (verilog-regexp-opt a t) "\\>"))
(defun verilog-easy-menu-filter (menu)
"Filter `easy-menu-define' MENU to support new features."
(cond ((not (featurep 'xemacs))
menu) ; GNU Emacs - passthru
;; XEmacs doesn't support :help. Strip it.
;; Recursively filter the a submenu
((listp menu)
(mapcar 'verilog-easy-menu-filter menu))
;; Look for [:help "blah"] and remove
((vectorp menu)
(let ((i 0) (out []))
(while (< i (length menu))
(if (equal `:help (aref menu i))
(setq i (+ 2 i))
(setq out (vconcat out (vector (aref menu i)))
i (1+ i))))
out))
(t menu))) ; Default - ok
;;(verilog-easy-menu-filter
;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
;; "----" ["MB" nil :help "Help MB"]))
(defun verilog-define-abbrev (table name expansion &optional hook)
"Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
Provides SYSTEM-FLAG in newer Emacs."
(condition-case nil
(define-abbrev table name expansion hook 0 t)
(error
(define-abbrev table name expansion hook))))
(defun verilog-customize ()
"Customize variables and other settings used by Verilog-Mode."
(interactive)
(customize-group 'verilog-mode))
(defun verilog-font-customize ()
"Customize fonts used by Verilog-Mode."
(interactive)
(if (fboundp 'customize-apropos)
(customize-apropos "font-lock-*" 'faces)))
(defun verilog-booleanp (value)
"Return t if VALUE is boolean.
This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
This function may be removed when Emacs 21 is no longer supported."
(or (equal value t) (equal value nil)))
(defun verilog-insert-last-command-event ()
"Insert the `last-command-event'."
(insert (if (featurep 'xemacs)
;; XEmacs 21.5 doesn't like last-command-event
last-command-char
;; And GNU Emacs 22 has obsoleted last-command-char
last-command-event)))
(defvar verilog-no-change-functions nil
"True if `after-change-functions' is disabled.
Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
(defvar verilog-in-hooks nil
"True when within a `verilog-run-hooks' block.")
(defmacro verilog-run-hooks (&rest hooks)
"Run each hook in HOOKS using `run-hooks'.
Set `verilog-in-hooks' during this time, to assist AUTO caches."
`(let ((verilog-in-hooks t))
(run-hooks ,@hooks)))
(defun verilog-syntax-ppss (&optional pos)
(when verilog-no-change-functions
(if verilog-in-hooks
(verilog-scan-cache-flush)
;; else don't let the AUTO code itself get away with flushing the cache,
;; as that'll make things very slow
(backtrace)
(error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
(verilog-point-text))))
(if (fboundp 'syntax-ppss)
(syntax-ppss pos)
(parse-partial-sexp (point-min) (or pos (point)))))
(defgroup verilog-mode nil
"Major mode for Verilog source code."
:version "22.2"
:group 'languages)
;; (defgroup verilog-mode-fonts nil
;; "Facilitates easy customization fonts used in Verilog source text"
;; :link '(customize-apropos "font-lock-*" 'faces)
;; :group 'verilog-mode)
(defgroup verilog-mode-indent nil
"Customize indentation and highlighting of Verilog source text."
:group 'verilog-mode)
(defgroup verilog-mode-actions nil
"Customize actions on Verilog source text."
:group 'verilog-mode)
(defgroup verilog-mode-auto nil
"Customize AUTO actions when expanding Verilog source text."
:group 'verilog-mode)
(defvar verilog-debug nil
"Non-nil means enable debug messages for `verilog-mode' internals.")
(defvar verilog-warn-fatal nil
"Non-nil means `verilog-warn-error' warnings are fatal `error's.")
(defcustom verilog-linter
"echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
"Unix program and arguments to call to run a lint checker on Verilog source.
Depending on the `verilog-set-compile-command', this may be invoked when
you type \\[compile]. When the compile completes, \\[next-error] will take
you to the next lint error."
:type 'string
:group 'verilog-mode-actions)
;; We don't mark it safe, as it's used as a shell command
(defcustom verilog-coverage
"echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
"Program and arguments to use to annotate for coverage Verilog source.
Depending on the `verilog-set-compile-command', this may be invoked when
you type \\[compile]. When the compile completes, \\[next-error] will take
you to the next lint error."
:type 'string
:group 'verilog-mode-actions)
;; We don't mark it safe, as it's used as a shell command
(defcustom verilog-simulator
"echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
"Program and arguments to use to interpret Verilog source.
Depending on the `verilog-set-compile-command', this may be invoked when
you type \\[compile]. When the compile completes, \\[next-error] will take
you to the next lint error."
:type 'string
:group 'verilog-mode-actions)
;; We don't mark it safe, as it's used as a shell command
(defcustom verilog-compiler
"echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
"Program and arguments to use to compile Verilog source.
Depending on the `verilog-set-compile-command', this may be invoked when
you type \\[compile]. When the compile completes, \\[next-error] will take
you to the next lint error."
:type 'string
:group 'verilog-mode-actions)
;; We don't mark it safe, as it's used as a shell command
(defcustom verilog-preprocessor
;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
"vppreproc __FLAGS__ __FILE__"
"Program and arguments to use to preprocess Verilog source.
This is invoked with `verilog-preprocess', and depending on the
`verilog-set-compile-command', may also be invoked when you type
\\[compile]. When the compile completes, \\[next-error] will
take you to the next lint error."
:type 'string
:group 'verilog-mode-actions)
;; We don't mark it safe, as it's used as a shell command
(defvar verilog-preprocess-history nil
"History for `verilog-preprocess'.")
(defvar verilog-tool 'verilog-linter
"Which tool to use for building compiler-command.
Either nil, `verilog-linter', `verilog-compiler',
`verilog-coverage', `verilog-preprocessor', or `verilog-simulator'.
Alternatively use the \"Choose Compilation Action\" menu. See
`verilog-set-compile-command' for more information.")
(defcustom verilog-highlight-translate-off nil
"Non-nil means background-highlight code excluded from translation.
That is, all code between \"// synopsys translate_off\" and
\"// synopsys translate_on\" is highlighted using a different background color
\(face `verilog-font-lock-translate-off-face').
Note: This will slow down on-the-fly fontification (and thus editing).
Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
:type 'boolean
:group 'verilog-mode-indent)
;; Note we don't use :safe, as that would break on Emacsen before 22.0.
(put 'verilog-highlight-translate-off 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-lineup 'declarations
"Type of statements to lineup across multiple lines.
If `all' is selected, then all line ups described below are done.
If `declarations', then just declarations are lined up with any
preceding declarations, taking into account widths and the like,
so or example the code:
reg [31:0] a;
reg b;
would become
reg [31:0] a;
reg b;
If `assignment', then assignments are lined up with any preceding
assignments, so for example the code
a_long_variable <= b + c;
d = e + f;
would become
a_long_variable <= b + c;
d = e + f;
In order to speed up editing, large blocks of statements are lined up
only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
are lineup only when \\[verilog-pretty-declarations] is typed."
:type '(radio (const :tag "Line up Assignments and Declarations" all)
(const :tag "Line up Assignment statements" assignments )
(const :tag "Line up Declarations" declarations)
(function :tag "Other"))
:group 'verilog-mode-indent )
(put 'verilog-auto-lineup 'safe-local-variable
'(lambda (x) (memq x '(nil all assignments declarations))))
(defcustom verilog-indent-level 3
"Indentation of Verilog statements with respect to containing block."
:group 'verilog-mode-indent
:type 'integer)
(put 'verilog-indent-level 'safe-local-variable 'integerp)
(defcustom verilog-indent-level-module 3
"Indentation of Module level Verilog statements (eg always, initial).
Set to 0 to get initial and always statements lined up on the left side of
your screen."
:group 'verilog-mode-indent
:type 'integer)
(put 'verilog-indent-level-module 'safe-local-variable 'integerp)
(defcustom verilog-indent-level-declaration 3
"Indentation of declarations with respect to containing block.
Set to 0 to get them list right under containing block."
:group 'verilog-mode-indent
:type 'integer)
(put 'verilog-indent-level-declaration 'safe-local-variable 'integerp)
(defcustom verilog-indent-declaration-macros nil
"How to treat macro expansions in a declaration.
If nil, indent as:
input [31:0] a;
input \\=`CP;
output c;
If non nil, treat as:
input [31:0] a;
input \\=`CP ;
output c;"
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-indent-declaration-macros 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-indent-lists t
"How to treat indenting items in a list.
If t (the default), indent as:
always @( posedge a or
reset ) begin
If nil, treat as:
always @( posedge a or
reset ) begin"
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-indent-lists 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-indent-level-behavioral 3
"Absolute indentation of first begin in a task or function block.
Set to 0 to get such code to start at the left side of the screen."
:group 'verilog-mode-indent
:type 'integer)
(put 'verilog-indent-level-behavioral 'safe-local-variable 'integerp)
(defcustom verilog-indent-level-directive 1
"Indentation to add to each level of \\=`ifdef declarations.
Set to 0 to have all directives start at the left side of the screen."
:group 'verilog-mode-indent
:type 'integer)
(put 'verilog-indent-level-directive 'safe-local-variable 'integerp)
(defcustom verilog-cexp-indent 2
"Indentation of Verilog statements split across lines."
:group 'verilog-mode-indent
:type 'integer)
(put 'verilog-cexp-indent 'safe-local-variable 'integerp)
(defcustom verilog-case-indent 2
"Indentation for case statements."
:group 'verilog-mode-indent
:type 'integer)
(put 'verilog-case-indent 'safe-local-variable 'integerp)
(defcustom verilog-auto-newline t
"Non-nil means automatically newline after semicolons."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-indent-on-newline t
"Non-nil means automatically indent line after newline."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-tab-always-indent t
"Non-nil means TAB should always re-indent the current line.
A nil value means TAB will only reindent when at the beginning of the line."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-tab-to-comment nil
"Non-nil means TAB moves to the right hand column in preparation for a comment."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-indent-begin-after-if t
"Non-nil means indent begin statements following if, else, while, etc.
Otherwise, line them up."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-align-ifelse nil
"Non-nil means align `else' under matching `if'.
Otherwise else is lined up with first character on line holding matching if."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-align-ifelse 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-minimum-comment-distance 10
"Minimum distance (in lines) between begin and end required before a comment.
Setting this variable to zero results in every end acquiring a comment; the
default avoids too many redundant comments in tight quarters."
:group 'verilog-mode-indent
:type 'integer)
(put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp)
(defcustom verilog-highlight-p1800-keywords nil
"Non-nil means highlight words newly reserved by IEEE-1800.
These will appear in `verilog-font-lock-p1800-face' in order to gently
suggest changing where these words are used as variables to something else.
A nil value means highlight these words as appropriate for the SystemVerilog
IEEE-1800 standard. Note that changing this will require restarting Emacs
to see the effect as font color choices are cached by Emacs."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-highlight-grouping-keywords nil
"Non-nil means highlight grouping keywords more dramatically.
If false, these words are in the `font-lock-type-face'; if True
then they are in `verilog-font-lock-grouping-keywords-face'.
Some find that special highlighting on these grouping constructs
allow the structure of the code to be understood at a glance."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-highlight-grouping-keywords 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-highlight-modules nil
"Non-nil means highlight module statements for `verilog-load-file-at-point'.
When true, mousing over module names will allow jumping to the
module definition. If false, this is not supported. Setting
this is experimental, and may lead to bad performance."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-highlight-modules 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-highlight-includes t
"Non-nil means highlight module statements for `verilog-load-file-at-point'.
When true, mousing over include file names will allow jumping to the
file referenced. If false, this is not supported."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-highlight-includes 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-declare-nettype nil
"Non-nil specifies the data type to use with `verilog-auto-input' etc.
Set this to \"wire\" if the Verilog code uses \"\\=`default_nettype
none\". Note using \\=`default_nettype none isn't recommended practice; this
mode is experimental."
:version "24.1" ; rev670
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
(defcustom verilog-auto-wire-comment t
"Non-nil indicates to insert to/from comments with `verilog-auto-wire' etc."
:version "25.1"
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-wire-comment 'safe-local-variable `verilog-booleanp)
(defcustom verilog-auto-wire-type nil
"Non-nil specifies the data type to use with `verilog-auto-wire' etc.
Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
:version "24.1" ; rev673
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-wire-type 'safe-local-variable `stringp)
(defcustom verilog-auto-endcomments t
"Non-nil means insert a comment /* ... */ after `end's.
The name of the function or case will be set between the braces."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-delete-trailing-whitespace nil
"Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
:version "24.1" ; rev703
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-ignore-concat nil
"Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
This will exclude signals referenced as pin connections in {...}
from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
for backward compatibility only and not set in new designs; it
may be removed in future versions."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-read-includes nil
"Non-nil means to automatically read includes before AUTOs.
This will do a `verilog-read-defines' and `verilog-read-includes' before
each AUTO expansion. This makes it easier to embed defines and includes,
but can result in very slow reading times if there are many or large
include files."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-read-includes 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-save-policy nil
"Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
A value of `force' will always do a \\[verilog-auto] automatically if
needed on every save. A value of `detect' will do \\[verilog-auto]
automatically when it thinks necessary. A value of `ask' will query the
user when it thinks updating is needed.
You should not rely on the `ask' or `detect' policies, they are safeguards
only. They do not detect when AUTOINSTs need to be updated because a
sub-module's port list has changed."
:group 'verilog-mode-actions
:type '(choice (const nil) (const ask) (const detect) (const force)))
(defcustom verilog-auto-star-expand t
"Non-nil means to expand SystemVerilog .* instance ports.
They will be expanded in the same way as if there was an AUTOINST in the
instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-star-save nil
"Non-nil means save to disk SystemVerilog .* instance expansions.
A nil value indicates direct connections will be removed before saving.
Only meaningful to those created due to `verilog-auto-star-expand' being set.
Instead of setting this, you may want to use /*AUTOINST*/, which will
always be saved."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-star-save 'safe-local-variable 'verilog-booleanp)
(defvar verilog-auto-update-tick nil
"Modification tick at which autos were last performed.")
(defvar verilog-auto-last-file-locals nil
"Text from file-local-variables during last evaluation.")
(defvar verilog-diff-function 'verilog-diff-report
"Function to run when `verilog-diff-auto' detects differences.
Function takes three arguments, the original buffer, the
difference buffer, and the point in original buffer with the
first difference.")
(defvar verilog-diff-ignore-regexp nil
"Non-nil specifies regexp which `verilog-diff-auto' will ignore.
This is typically nil.")
;;; Compile support:
;;
(require 'compile)
(defvar verilog-error-regexp-added nil)
(defvar verilog-error-regexp-emacs-alist
'(
(verilog-xl-1
"\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
(verilog-xl-2
"([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
(verilog-IES
".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
(verilog-surefire-1
"[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
(verilog-surefire-2
"\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
(verilog-verbose
"\
\\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
:\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
(verilog-xsim
"\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
(verilog-vcs-1
"\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
(verilog-vcs-2
"Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
(verilog-vcs-3
"\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
(verilog-vcs-4
"syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
(verilog-verilator
"%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
(verilog-leda
"^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
)
"List of regexps for Verilog compilers.
See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
(defvar verilog-error-regexp-xemacs-alist
;; Emacs form is '((v-tool "re" 1 2) ...)
;; XEmacs form is '(verilog ("re" 1 2) ...)
;; So we can just map from Emacs to XEmacs
(cons 'verilog (mapcar 'cdr verilog-error-regexp-emacs-alist))
"List of regexps for Verilog compilers.
See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
(defvar verilog-error-font-lock-keywords
'(
;; verilog-xl-1
("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
;; verilog-xl-2
("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t)
("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t)
;; verilog-IES (nc-verilog)
(".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
(".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t)
;; verilog-surefire-1
("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
;; verilog-surefire-2
("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
;; verilog-verbose
("\
\\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
:\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
("\
\\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
:\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
;; verilog-vcs-1
("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t)
("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t)
;; verilog-vcs-2
("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
;; verilog-vcs-3
("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t)
;; verilog-vcs-4
("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t)
("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
;; verilog-verilator
(".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t)
(".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t)
;; verilog-leda
("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t)
("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t)
)
"Keywords to also highlight in Verilog *compilation* buffers.
Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
(defcustom verilog-library-flags '("")
"List of standard Verilog arguments to use for /*AUTOINST*/.
These arguments are used to find files for `verilog-auto', and match
the flags accepted by a standard Verilog-XL simulator.
-f filename Reads more `verilog-library-flags' from the filename.
+incdir+dir Adds the directory to `verilog-library-directories'.
-Idir Adds the directory to `verilog-library-directories'.
-y dir Adds the directory to `verilog-library-directories'.
+libext+.v Adds the extensions to `verilog-library-extensions'.
-v filename Adds the filename to `verilog-library-files'.
filename Adds the filename to `verilog-library-files'.
This is not recommended, -v is a better choice.
You might want these defined in each file; put at the *END* of your file
something like:
// Local Variables:
// verilog-library-flags:(\"-y dir -y otherdir\")
// End:
Verilog-mode attempts to detect changes to this local variable, but they
are only insured to be correct when the file is first visited. Thus if you
have problems, use \\[find-alternate-file] RET to have these take effect.
See also the variables mentioned above."
:group 'verilog-mode-auto
:type '(repeat string))
(put 'verilog-library-flags 'safe-local-variable 'listp)
(defcustom verilog-library-directories '(".")
"List of directories when looking for files for /*AUTOINST*/.
The directory may be relative to the current file, or absolute.
Environment variables are also expanded in the directory names.
Having at least the current directory is a good idea.
You might want these defined in each file; put at the *END* of your file
something like:
// Local Variables:
// verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
// End:
Verilog-mode attempts to detect changes to this local variable, but they
are only insured to be correct when the file is first visited. Thus if you
have problems, use \\[find-alternate-file] RET to have these take effect.
See also `verilog-library-flags', `verilog-library-files'
and `verilog-library-extensions'."
:group 'verilog-mode-auto
:type '(repeat file))
(put 'verilog-library-directories 'safe-local-variable 'listp)
(defcustom verilog-library-files '()
"List of files to search for modules.
AUTOINST will use this when it needs to resolve a module name.
This is a complete path, usually to a technology file with many standard
cells defined in it.
You might want these defined in each file; put at the *END* of your file
something like:
// Local Variables:
// verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
// End:
Verilog-mode attempts to detect changes to this local variable, but they
are only insured to be correct when the file is first visited. Thus if you
have problems, use \\[find-alternate-file] RET to have these take effect.
See also `verilog-library-flags', `verilog-library-directories'."
:group 'verilog-mode-auto
:type '(repeat directory))
(put 'verilog-library-files 'safe-local-variable 'listp)
(defcustom verilog-library-extensions '(".v" ".sv")
"List of extensions to use when looking for files for /*AUTOINST*/.
See also `verilog-library-flags', `verilog-library-directories'."
:type '(repeat string)
:group 'verilog-mode-auto)
(put 'verilog-library-extensions 'safe-local-variable 'listp)
(defcustom verilog-active-low-regexp nil
"If true, treat signals matching this regexp as active low.
This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
you will probably also need `verilog-auto-reset-widths' set."
:group 'verilog-mode-auto
:type '(choice (const nil) regexp))
(put 'verilog-active-low-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-sense-include-inputs nil
"Non-nil means AUTOSENSE should include all inputs.
If nil, only inputs that are NOT output signals in the same block are
included."
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-sense-defines-constant nil
"Non-nil means AUTOSENSE should assume all defines represent constants.
When true, the defines will not be included in sensitivity lists. To
maintain compatibility with other sites, this should be set at the bottom
of each Verilog file that requires it, rather than being set globally."
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-reset-blocking-in-non t
"Non-nil means AUTORESET will reset blocking statements.
When true, AUTORESET will reset in blocking statements those
signals which were assigned with blocking assignments (=) even in
a block with non-blocking assignments (<=).
If nil, all blocking assigned signals are ignored when any
non-blocking assignment is in the AUTORESET block. This allows
blocking assignments to be used for temporary values and not have
those temporaries reset. See example in `verilog-auto-reset'."
:version "24.1" ; rev718
:type 'boolean
:group 'verilog-mode-auto)
(put 'verilog-auto-reset-blocking-in-non 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-reset-widths t
"True means AUTORESET should determine the width of signals.
This is then used to set the width of the zero (32'h0 for example). This
is required by some lint tools that aren't smart enough to ignore widths of
the constant zero. This may result in ugly code when parameters determine
the MSB or LSB of a signal inside an AUTORESET.
If nil, AUTORESET uses \"0\" as the constant.
If `unbased', AUTORESET used the unbased unsized literal \"\\='0\"
as the constant. This setting is strongly recommended for
SystemVerilog designs."
:type 'boolean
:group 'verilog-mode-auto)
(put 'verilog-auto-reset-widths 'safe-local-variable
'(lambda (x) (memq x '(nil t unbased))))
(defcustom verilog-assignment-delay ""
"Text used for delays in delayed assignments. Add a trailing space if set."
:group 'verilog-mode-auto
:type 'string)
(put 'verilog-assignment-delay 'safe-local-variable 'stringp)
(defcustom verilog-auto-arg-format 'packed
"Formatting to use for AUTOARG signal names.
If `packed', then as many inputs and outputs that fit within
`fill-column' will be put onto one line.
If `single', then a single input or output will be put onto each
line."
:version "25.1"
:type '(radio (const :tag "Line up Assignments and Declarations" packed)
(const :tag "Line up Assignment statements" single))
:group 'verilog-mode-auto)
(put 'verilog-auto-arg-format 'safe-local-variable
'(lambda (x) (memq x '(packed single))))
(defcustom verilog-auto-arg-sort nil
"Non-nil means AUTOARG signal names will be sorted, not in declaration order.
Declaration order is advantageous with order based instantiations
and is the default for backward compatibility. Sorted order
reduces changes when declarations are moved around in a file, and
it's bad practice to rely on order based instantiations anyhow.
See also `verilog-auto-inst-sort'."
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-dot-name nil
"Non-nil means when creating ports with AUTOINST, use .name syntax.
This will use \".port\" instead of \".port(port)\" when possible.
This is only legal in SystemVerilog files, and will confuse older
simulators. Setting `verilog-auto-inst-vector' to nil may also
be desirable to increase how often .name will be used."
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-dot-name 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-param-value nil
"Non-nil means AUTOINST will replace parameters with the parameter value.
If nil, leave parameters as symbolic names.
Parameters must be in Verilog 2001 format #(...), and if a parameter is not
listed as such there (as when the default value is acceptable), it will not
be replaced, and will remain symbolic.
For example, imagine a submodule uses parameters to declare the size of its
inputs. This is then used by an upper module:
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule
module ExampInst;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output OUT_t o;
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.i (i[WIDTH-1:0]),
.o (o));
Note even though WIDTH=10, the AUTOINST has left the parameter as
a symbolic name. Likewise the OUT_t is preserved as the name
from the instantiated module.
If `verilog-auto-inst-param-value' is set, this will
instead expand to:
module ExampInst;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output upper_t o;
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.i (i[9:0]),
.o (o));
Note that the instantiation now has \"i[9:0]\" as the WIDTH
was expanded. Likewise the data type of \"o\" in the AUTOOUTPUT
is now upper_t, from the OUT_t parameter override.
This second expansion of parameter types can be overridden with
`verilog-auto-inst-param-value-type'."
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-param-value-type t
"Non-nil means expand parameter type in instantiations.
If nil, leave parameter types as symbolic names.
See `verilog-auto-inst-param-value'."
:version "25.1"
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-param-value-type 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-sort nil
"Non-nil means AUTOINST signals will be sorted, not in declaration order.
Also affects AUTOINSTPARAM. Declaration order is the default for
backward compatibility, and as some teams prefer signals that are
declared together to remain together. Sorted order reduces
changes when declarations are moved around in a file.
See also `verilog-auto-arg-sort'."
:version "24.1" ; rev688
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-vector t
"Non-nil means when creating default ports with AUTOINST, use bus subscripts.
If nil, skip the subscript when it matches the entire bus as declared in
the module (AUTOWIRE signals always are subscripted, you must manually
declare the wire to have the subscripts removed.) Setting this to nil may
speed up some simulators, but is less general and harder to read, so avoid."
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-template-numbers nil
"If true, when creating templated ports with AUTOINST, add a comment.
If t, the comment will add the line number of the template that
was used for that port declaration. This setting is suggested
only for debugging use, as regular use may cause a large numbers
of merge conflicts.
If `lhs', the comment will show the left hand side of the
AUTO_TEMPLATE rule that is matched. This is less precise than
numbering (t) when multiple rules have the same pin name, but
won't merge conflict."
:group 'verilog-mode-auto
:type '(choice (const nil) (const t) (const lhs)))
(put 'verilog-auto-inst-template-numbers 'safe-local-variable
'(lambda (x) (memq x '(nil t lhs))))
(defcustom verilog-auto-inst-column 40
"Indent-to column number for net name part of AUTOINST created pin."
:group 'verilog-mode-indent
:type 'integer)
(put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
(defcustom verilog-auto-inst-interfaced-ports nil
"Non-nil means include interfaced ports in AUTOINST expansions."
:version "24.3" ; rev773, default change rev815
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-interfaced-ports 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-input-ignore-regexp nil
"If non-nil, when creating AUTOINPUT, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
:type '(choice (const nil) regexp))
(put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-inout-ignore-regexp nil
"If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
:type '(choice (const nil) regexp))
(put 'verilog-auto-inout-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-output-ignore-regexp nil
"If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
:type '(choice (const nil) regexp))
(put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-template-warn-unused nil
"Non-nil means report warning if an AUTO_TEMPLATE line is not used.
This feature is not supported before Emacs 21.1 or XEmacs 21.4."
:version "24.3" ; rev787
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-tieoff-declaration "wire"
"Data type used for the declaration for AUTOTIEOFF.
If \"wire\" then create a wire, if \"assign\" create an
assignment, else the data type for variable creation."
:version "24.1" ; rev713
:group 'verilog-mode-auto
:type 'string)
(put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
(defcustom verilog-auto-tieoff-ignore-regexp nil
"If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
:type '(choice (const nil) regexp))
(put 'verilog-auto-tieoff-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-unused-ignore-regexp nil
"If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
:type '(choice (const nil) regexp))
(put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-case-fold t
"Non-nil means `verilog-mode' regexps should ignore case.
This variable is t for backward compatibility; nil is suggested."
:version "24.4"
:group 'verilog-mode
:type 'boolean)
(put 'verilog-case-fold 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-typedef-regexp nil
"If non-nil, regular expression that matches Verilog-2001 typedef names.
For example, \"_t$\" matches typedefs named with _t, as in the C language.
See also `verilog-case-fold'."
:group 'verilog-mode-auto
:type '(choice (const nil) regexp))
(put 'verilog-typedef-regexp 'safe-local-variable 'stringp)
(defcustom verilog-mode-hook 'verilog-set-compile-command
"Hook run after Verilog mode is loaded."
:type 'hook
:group 'verilog-mode)
(defcustom verilog-auto-hook nil
"Hook run after `verilog-mode' updates AUTOs."
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-before-auto-hook nil
"Hook run before `verilog-mode' updates AUTOs."
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-delete-auto-hook nil
"Hook run after `verilog-mode' deletes AUTOs."
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-before-delete-auto-hook nil
"Hook run before `verilog-mode' deletes AUTOs."
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-getopt-flags-hook nil
"Hook run after `verilog-getopt-flags' determines the Verilog option lists."
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-before-getopt-flags-hook nil
"Hook run before `verilog-getopt-flags' determines the Verilog option lists."
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-before-save-font-hook nil
"Hook run before `verilog-save-font-mods' removes highlighting."
:version "24.3" ; rev735
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-after-save-font-hook nil
"Hook run after `verilog-save-font-mods' restores highlighting."
:version "24.3" ; rev735
:group 'verilog-mode-auto
:type 'hook)
(defvar verilog-imenu-generic-expression
'((nil "^\\s-*\\(?:m\\(?:odule\\|acromodule\\)\\|p\\(?:rimitive\\|rogram\\|ackage\\)\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 1)
("*Variables*" "^\\s-*\\(reg\\|wire\\|logic\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3)
("*Classes*" "^\\s-*\\(?:\\(?:virtual\\|interface\\)\\s-+\\)?class\\s-+\\([A-Za-z_][A-Za-z0-9_]+\\)" 1)
("*Tasks*" "^\\s-*\\(?:\\(?:static\\|pure\\|virtual\\|local\\|protected\\)\\s-+\\)*task\\s-+\\(?:\\(?:static\\|automatic\\)\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_:]+\\)" 1)
("*Functions*" "^\\s-*\\(?:\\(?:static\\|pure\\|virtual\\|local\\|protected\\)\\s-+\\)*function\\s-+\\(?:\\(?:static\\|automatic\\)\\s-+\\)?\\(?:\\w+\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_:]+\\)" 1)
("*Interfaces*" "^\\s-*interface\\s-+\\([a-zA-Z_0-9]+\\)" 1)
("*Types*" "^\\s-*typedef\\s-+.*\\s-+\\([a-zA-Z_0-9]+\\)\\s-*;" 1))
"Imenu expression for Verilog mode. See `imenu-generic-expression'.")
;;
;; provide a verilog-header function.
;; Customization variables:
;;
(defvar verilog-date-scientific-format nil
"If non-nil, dates are written in scientific format (e.g. 1997/09/17).
If nil, in European format (e.g. 17.09.1997). The brain-dead American
format (e.g. 09/17/1997) is not supported.")
(defvar verilog-company nil
"Default name of Company for Verilog header.
If set will become buffer local.")
(make-variable-buffer-local 'verilog-company)
(defvar verilog-project nil
"Default name of Project for Verilog header.
If set will become buffer local.")
(make-variable-buffer-local 'verilog-project)
;;; Keymap and Menu:
;;
(defvar verilog-mode-map
(let ((map (make-sparse-keymap)))
(define-key map ";" 'electric-verilog-semi)
(define-key map [(control 59)] 'electric-verilog-semi-with-comment)
(define-key map ":" 'electric-verilog-colon)
;;(define-key map "=" 'electric-verilog-equal)
(define-key map "`" 'electric-verilog-tick)
(define-key map "\t" 'electric-verilog-tab)
(define-key map "\r" 'electric-verilog-terminate-line)
;; backspace/delete key bindings
(define-key map [backspace] 'backward-delete-char-untabify)
(unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
(define-key map [delete] 'delete-char)
(define-key map [(meta delete)] 'kill-word))
(define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
(define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
(define-key map "\M-\r" `electric-verilog-terminate-and-indent)
(define-key map "\M-\t" 'verilog-complete-word)
(define-key map "\M-?" 'verilog-show-completions)
;; Note \C-c and letter are reserved for users
(define-key map "\C-c`" 'verilog-lint-off)
(define-key map "\C-c*" 'verilog-delete-auto-star-implicit)
(define-key map "\C-c?" 'verilog-diff-auto)
(define-key map "\C-c\C-r" 'verilog-label-be)
(define-key map "\C-c\C-i" 'verilog-pretty-declarations)
(define-key map "\C-c=" 'verilog-pretty-expr)
(define-key map "\C-c\C-b" 'verilog-submit-bug-report)
(define-key map "\C-c/" 'verilog-star-comment)
(define-key map "\C-c\C-c" 'verilog-comment-region)
(define-key map "\C-c\C-u" 'verilog-uncomment-region)
(when (featurep 'xemacs)
(define-key map [(meta control h)] 'verilog-mark-defun)
(define-key map "\M-\C-a" 'verilog-beg-of-defun)
(define-key map "\M-\C-e" 'verilog-end-of-defun))
(define-key map "\C-c\C-d" 'verilog-goto-defun)
(define-key map "\C-c\C-k" 'verilog-delete-auto)
(define-key map "\C-c\C-a" 'verilog-auto)
(define-key map "\C-c\C-s" 'verilog-auto-save-compile)
(define-key map "\C-c\C-p" 'verilog-preprocess)
(define-key map "\C-c\C-z" 'verilog-inject-auto)
(define-key map "\C-c\C-e" 'verilog-expand-vector)
(define-key map "\C-c\C-h" 'verilog-header)
map)
"Keymap used in Verilog mode.")
;; menus
(easy-menu-define
verilog-menu verilog-mode-map "Menu for Verilog mode"
(verilog-easy-menu-filter
'("Verilog"
("Choose Compilation Action"
["None"
(progn
(setq verilog-tool nil)
(verilog-set-compile-command))
:style radio
:selected (equal verilog-tool nil)
:help "When invoking compilation, use compile-command"]
["Lint"
(progn
(setq verilog-tool 'verilog-linter)
(verilog-set-compile-command))
:style radio
:selected (equal verilog-tool `verilog-linter)
:help "When invoking compilation, use lint checker"]
["Coverage"
(progn
(setq verilog-tool 'verilog-coverage)
(verilog-set-compile-command))
:style radio
:selected (equal verilog-tool `verilog-coverage)
:help "When invoking compilation, annotate for coverage"]
["Simulator"
(progn
(setq verilog-tool 'verilog-simulator)
(verilog-set-compile-command))
:style radio
:selected (equal verilog-tool `verilog-simulator)
:help "When invoking compilation, interpret Verilog source"]
["Compiler"
(progn
(setq verilog-tool 'verilog-compiler)
(verilog-set-compile-command))
:style radio
:selected (equal verilog-tool `verilog-compiler)
:help "When invoking compilation, compile Verilog source"]
["Preprocessor"
(progn
(setq verilog-tool 'verilog-preprocessor)
(verilog-set-compile-command))
:style radio
:selected (equal verilog-tool `verilog-preprocessor)
:help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
)
("Move"
["Beginning of function" verilog-beg-of-defun
:keys "C-M-a"
:help "Move backward to the beginning of the current function or procedure"]
["End of function" verilog-end-of-defun
:keys "C-M-e"
:help "Move forward to the end of the current function or procedure"]
["Mark function" verilog-mark-defun
:keys "C-M-h"
:help "Mark the current Verilog function or procedure"]
["Goto function/module" verilog-goto-defun
:help "Move to specified Verilog module/task/function"]
["Move to beginning of block" electric-verilog-backward-sexp
:help "Move backward over one balanced expression"]
["Move to end of block" electric-verilog-forward-sexp
:help "Move forward over one balanced expression"]
)
("Comments"
["Comment Region" verilog-comment-region
:help "Put marked area into a comment"]
["UnComment Region" verilog-uncomment-region
:help "Uncomment an area commented with Comment Region"]
["Multi-line comment insert" verilog-star-comment
:help "Insert Verilog /* */ comment at point"]
["Lint error to comment" verilog-lint-off
:help "Convert a Verilog linter warning line into a disable statement"]
)
"----"
["Compile" compile
:help "Perform compilation-action (above) on the current buffer"]
["AUTO, Save, Compile" verilog-auto-save-compile
:help "Recompute AUTOs, save buffer, and compile"]
["Next Compile Error" next-error
:help "Visit next compilation error message and corresponding source code"]
["Ignore Lint Warning at point" verilog-lint-off
:help "Convert a Verilog linter warning line into a disable statement"]
"----"
["Line up declarations around point" verilog-pretty-declarations
:help "Line up declarations around point"]
["Line up equations around point" verilog-pretty-expr
:help "Line up expressions around point"]
["Redo/insert comments on every end" verilog-label-be
:help "Label matching begin ... end statements"]
["Expand [x:y] vector line" verilog-expand-vector
:help "Take a signal vector on the current line and expand it to multiple lines"]
["Insert begin-end block" verilog-insert-block
:help "Insert begin ... end"]
["Complete word" verilog-complete-word
:help "Complete word at point"]
"----"
["Recompute AUTOs" verilog-auto
:help "Expand AUTO meta-comment statements"]
["Kill AUTOs" verilog-delete-auto
:help "Remove AUTO expansions"]
["Diff AUTOs" verilog-diff-auto
:help "Show differences in AUTO expansions"]
["Inject AUTOs" verilog-inject-auto
:help "Inject AUTOs into legacy non-AUTO buffer"]
("AUTO Help..."
["AUTO General" (describe-function 'verilog-auto)
:help "Help introduction on AUTOs"]
["AUTO Library Flags" (describe-variable 'verilog-library-flags)
:help "Help on verilog-library-flags"]
["AUTO Library Path" (describe-variable 'verilog-library-directories)
:help "Help on verilog-library-directories"]
["AUTO Library Files" (describe-variable 'verilog-library-files)
:help "Help on verilog-library-files"]
["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
:help "Help on verilog-library-extensions"]
["AUTO `define Reading" (describe-function 'verilog-read-defines)
:help "Help on reading `defines"]
["AUTO `include Reading" (describe-function 'verilog-read-includes)
:help "Help on parsing `includes"]
["AUTOARG" (describe-function 'verilog-auto-arg)
:help "Help on AUTOARG - declaring module port list"]
["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
:help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
:help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
["AUTOINOUT" (describe-function 'verilog-auto-inout)
:help "Help on AUTOINOUT - adding inouts from cells"]
["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
:help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
:help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
:help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
:help "Help on AUTOINOUTMODULE - copying i/o from another file"]
["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
:help "Help on AUTOINOUTPARAM - copying parameters from another file"]
["AUTOINPUT" (describe-function 'verilog-auto-input)
:help "Help on AUTOINPUT - adding inputs from cells"]
["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
:help "Help on AUTOINSERTLISP - insert text from a lisp function"]
["AUTOINSERTLAST" (describe-function 'verilog-auto-insert-last)
:help "Help on AUTOINSERTLISPLAST - insert text from a lisp function"]
["AUTOINST" (describe-function 'verilog-auto-inst)
:help "Help on AUTOINST - adding pins for cells"]
["AUTOINST (.*)" (describe-function 'verilog-auto-star)
:help "Help on expanding Verilog-2001 .* pins"]
["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
:help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
["AUTOLOGIC" (describe-function 'verilog-auto-logic)
:help "Help on AUTOLOGIC - declaring logic signals"]
["AUTOOUTPUT" (describe-function 'verilog-auto-output)
:help "Help on AUTOOUTPUT - adding outputs from cells"]
["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
:help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
["AUTOREG" (describe-function 'verilog-auto-reg)
:help "Help on AUTOREG - declaring registers for non-wires"]
["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
:help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
["AUTORESET" (describe-function 'verilog-auto-reset)
:help "Help on AUTORESET - resetting always blocks"]
["AUTOSENSE or AS" (describe-function 'verilog-auto-sense)
:help "Help on AUTOSENSE - sensitivity lists for always blocks"]
["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
:help "Help on AUTOTIEOFF - tying off unused outputs"]
["AUTOUNDEF" (describe-function 'verilog-auto-undef)
:help "Help on AUTOUNDEF - undefine all local defines"]
["AUTOUNUSED" (describe-function 'verilog-auto-unused)
:help "Help on AUTOUNUSED - terminating unused inputs"]
["AUTOWIRE" (describe-function 'verilog-auto-wire)
:help "Help on AUTOWIRE - declaring wires for cells"]
)
"----"
["Submit bug report" verilog-submit-bug-report
:help "Submit via mail a bug report on verilog-mode.el"]
["Version and FAQ" verilog-faq
:help "Show the current version, and where to get the FAQ etc"]
["Customize Verilog Mode..." verilog-customize
:help "Customize variables and other settings used by Verilog-Mode"]
["Customize Verilog Fonts & Colors" verilog-font-customize
:help "Customize fonts used by Verilog-Mode."])))
(easy-menu-define
verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
(verilog-easy-menu-filter
'("Statements"
["Header" verilog-sk-header
:help "Insert a header block at the top of file"]
["Comment" verilog-sk-comment
:help "Insert a comment block"]
"----"
["Module" verilog-sk-module
:help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
["OVM Class" verilog-sk-ovm-class
:help "Insert an OVM class block"]
["UVM Object" verilog-sk-uvm-object
:help "Insert an UVM object block"]
["UVM Component" verilog-sk-uvm-component
:help "Insert an UVM component block"]
["Primitive" verilog-sk-primitive
:help "Insert a primitive .. (.. );.. endprimitive block"]
"----"
["Input" verilog-sk-input
:help "Insert an input declaration"]
["Output" verilog-sk-output
:help "Insert an output declaration"]
["Inout" verilog-sk-inout
:help "Insert an inout declaration"]
["Wire" verilog-sk-wire
:help "Insert a wire declaration"]
["Reg" verilog-sk-reg
:help "Insert a register declaration"]
["Define thing under point as a register" verilog-sk-define-signal
:help "Define signal under point as a register at the top of the module"]
"----"
["Initial" verilog-sk-initial
:help "Insert an initial begin .. end block"]
["Always" verilog-sk-always
:help "Insert an always @(AS) begin .. end block"]
["Function" verilog-sk-function
:help "Insert a function .. begin .. end endfunction block"]
["Task" verilog-sk-task
:help "Insert a task .. begin .. end endtask block"]
["Specify" verilog-sk-specify
:help "Insert a specify .. endspecify block"]
["Generate" verilog-sk-generate
:help "Insert a generate .. endgenerate block"]
"----"
["Begin" verilog-sk-begin
:help "Insert a begin .. end block"]
["If" verilog-sk-if
:help "Insert an if (..) begin .. end block"]
["(if) else" verilog-sk-else-if
:help "Insert an else if (..) begin .. end block"]
["For" verilog-sk-for
:help "Insert a for (...) begin .. end block"]
["While" verilog-sk-while
:help "Insert a while (...) begin .. end block"]
["Fork" verilog-sk-fork
:help "Insert a fork begin .. end .. join block"]
["Repeat" verilog-sk-repeat
:help "Insert a repeat (..) begin .. end block"]
["Case" verilog-sk-case
:help "Insert a case block, prompting for details"]
["Casex" verilog-sk-casex
:help "Insert a casex (...) item: begin.. end endcase block"]
["Casez" verilog-sk-casez
:help "Insert a casez (...) item: begin.. end endcase block"])))
(defvar verilog-mode-abbrev-table nil
"Abbrev table in use in Verilog-mode buffers.")
(define-abbrev-table 'verilog-mode-abbrev-table ())
(verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
(verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
(verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
(verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
(verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
(verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
(verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
(verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
(verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
(verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
(verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
(verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
(verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
(verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
(verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
(verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
(verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
(verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
(verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
(verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
(verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
(verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
(verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
(verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
(verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
;;
;; Macros
;;
(defsubst verilog-within-string ()
(nth 3 (parse-partial-sexp (point-at-bol) (point))))
(defsubst verilog-string-match-fold (regexp string &optional start)
"Like `string-match', but use `verilog-case-fold'.
Return index of start of first match for REGEXP in STRING, or nil.
Matching ignores case if `verilog-case-fold' is non-nil.
If third arg START is non-nil, start search at that index in STRING."
(let ((case-fold-search verilog-case-fold))
(string-match regexp string start)))
(defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
"Replace occurrences of FROM-STRING with TO-STRING.
FIXEDCASE and LITERAL as in `replace-match'. STRING is what to replace.
The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
will break, as the o's continuously replace. xa -> x works ok though."
;; Hopefully soon to an Emacs built-in
;; Also note \ in the replacement prevent multiple replacements; IE
;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
(let ((start 0))
(while (string-match from-string string start)
(setq string (replace-match to-string fixedcase literal string)
start (min (length string) (+ (match-beginning 0) (length to-string)))))
string))
(defsubst verilog-string-remove-spaces (string)
"Remove spaces surrounding STRING."
(save-match-data
(setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
(setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
string))
(defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
;; checkdoc-params: (REGEXP BOUND NOERROR)
"Like `re-search-forward', but skips over match in comments or strings."
(let ((mdata '(nil nil))) ; So match-end will return nil if no matches found
(while (and
(re-search-forward REGEXP BOUND NOERROR)
(setq mdata (match-data))
(and (verilog-skip-forward-comment-or-string)
(progn
(setq mdata '(nil nil))
(if BOUND
(< (point) BOUND)
t)))))
(store-match-data mdata)
(match-end 0)))
(defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
;; checkdoc-params: (REGEXP BOUND NOERROR)
"Like `re-search-backward', but skips over match in comments or strings."
(let ((mdata '(nil nil))) ; So match-end will return nil if no matches found
(while (and
(re-search-backward REGEXP BOUND NOERROR)
(setq mdata (match-data))
(and (verilog-skip-backward-comment-or-string)
(progn
(setq mdata '(nil nil))
(if BOUND
(> (point) BOUND)
t)))))
(store-match-data mdata)
(match-end 0)))
(defsubst verilog-re-search-forward-quick (regexp bound noerror)
"Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
but trashes match data and is faster for REGEXP that doesn't match often.
This uses `verilog-scan' and text properties to ignore comments,
so there may be a large up front penalty for the first search."
(let (pt)
(while (and (not pt)
(re-search-forward regexp bound noerror))
(if (verilog-inside-comment-or-string-p (match-beginning 0))
(re-search-forward "[/\"\n]" nil t) ; Only way a comment or quote can end
(setq pt (match-end 0))))
pt))
(defsubst verilog-re-search-backward-quick (regexp bound noerror)
;; checkdoc-params: (REGEXP BOUND NOERROR)
"Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
but trashes match data and is faster for REGEXP that doesn't match often.
This uses `verilog-scan' and text properties to ignore comments,
so there may be a large up front penalty for the first search."
(let (pt)
(while (and (not pt)
(re-search-backward regexp bound noerror))
(if (verilog-inside-comment-or-string-p (match-beginning 0))
(re-search-backward "[/\"]" nil t) ; Only way a comment or quote can begin
(setq pt (match-beginning 0))))
pt))
(defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
"Like `re-search-forward', but first search for SUBSTR constant.
Then searched for the normal REGEXP (which contains SUBSTR), with given
BOUND and NOERROR. The REGEXP must fit within a single line.
This speeds up complicated regexp matches."
;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
;; thus require matches to be on one line, and use beginning-of-line.
(let (done)
(while (and (not done)
(search-forward substr bound noerror))
(save-excursion
(beginning-of-line)
(setq done (re-search-forward regexp (point-at-eol) noerror)))
(unless (and (<= (match-beginning 0) (point))
(>= (match-end 0) (point)))
(setq done nil)))
(when done (goto-char done))
done))
;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ; -end (test bait)
(defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
"Like `re-search-backward', but first search for SUBSTR constant.
Then searched for the normal REGEXP (which contains SUBSTR), with given
BOUND and NOERROR. The REGEXP must fit within a single line.
This speeds up complicated regexp matches."
;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
;; thus require matches to be on one line, and use beginning-of-line.
(let (done)
(while (and (not done)
(search-backward substr bound noerror))
(save-excursion
(end-of-line)
(setq done (re-search-backward regexp (point-at-bol) noerror)))
(unless (and (<= (match-beginning 0) (point))
(>= (match-end 0) (point)))
(setq done nil)))
(when done (goto-char done))
done))
;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ; -end (test bait)
(defun verilog-delete-trailing-whitespace ()
"Delete trailing spaces or tabs, but not newlines nor linefeeds.
Also add missing final newline.
To call this from the command line, see \\[verilog-batch-diff-auto].
To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
(save-excursion
(goto-char (point-min))
(while (re-search-forward "[ \t]+$" nil t) ; Not syntactic WS as no formfeed
(replace-match "" nil nil))
(goto-char (point-max))
(unless (bolp) (insert "\n"))))
(defvar compile-command)
(defvar create-lockfiles) ; Emacs 24
;; compilation program
(defun verilog-set-compile-command ()
"Function to compute shell command to compile Verilog.
This reads `verilog-tool' and sets `compile-command'. This specifies the
program that executes when you type \\[compile] or
\\[verilog-auto-save-compile].
By default `verilog-tool' uses a Makefile if one exists in the
current directory. If not, it is set to the `verilog-linter',
`verilog-compiler', `verilog-coverage', `verilog-preprocessor',
or `verilog-simulator' variables, as selected with the Verilog ->
\"Choose Compilation Action\" menu.
You should set `verilog-tool' or the other variables to the path and
arguments for your Verilog simulator. For example:
\"vcs -p123 -O\"
or a string like:
\"(cd /tmp; surecov %s)\".
In the former case, the path to the current buffer is concat'ed to the
value of `verilog-tool'; in the later, the path to the current buffer is
substituted for the %s.
Where __FLAGS__ appears in the string `verilog-current-flags'
will be substituted.
Where __FILE__ appears in the string, the variable
`buffer-file-name' of the current buffer, without the directory
portion, will be substituted."
(interactive)
(cond
((or (file-exists-p "makefile") ;If there is a makefile, use it
(file-exists-p "Makefile"))
(set (make-local-variable 'compile-command) "make "))
(t
(set (make-local-variable 'compile-command)
(if verilog-tool
(if (string-match "%s" (eval verilog-tool))
(format (eval verilog-tool) (or buffer-file-name ""))
(concat (eval verilog-tool) " " (or buffer-file-name "")))
""))))
(verilog-modify-compile-command))
(defun verilog-expand-command (command)
"Replace meta-information in COMMAND and return it.
Where __FLAGS__ appears in the string `verilog-current-flags'
will be substituted. Where __FILE__ appears in the string, the
current buffer's file-name, without the directory portion, will
be substituted."
(setq command (verilog-string-replace-matches
;; Note \\b only works if under verilog syntax table
"\\b__FLAGS__\\b" (verilog-current-flags)
t t command))
(setq command (verilog-string-replace-matches
"\\b__FILE__\\b" (file-name-nondirectory
(or (buffer-file-name) ""))
t t command))
command)
(defun verilog-modify-compile-command ()
"Update `compile-command' using `verilog-expand-command'."
(when (and
(stringp compile-command)
(string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
(set (make-local-variable 'compile-command)
(verilog-expand-command compile-command))))
(if (featurep 'xemacs)
;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
(defun verilog-error-regexp-add-xemacs ()
"Teach XEmacs about verilog errors.
Called by `compilation-mode-hook'. This allows \\[next-error] to
find the errors."
(interactive)
(if (boundp 'compilation-error-regexp-systems-alist)
(if (and
(not (equal compilation-error-regexp-systems-list 'all))
(not (member compilation-error-regexp-systems-list 'verilog)))
(push 'verilog compilation-error-regexp-systems-list)))
(if (boundp 'compilation-error-regexp-alist-alist)
(if (not (assoc 'verilog compilation-error-regexp-alist-alist))
(setcdr compilation-error-regexp-alist-alist
(cons verilog-error-regexp-xemacs-alist
(cdr compilation-error-regexp-alist-alist)))))
(if (boundp 'compilation-font-lock-keywords)
(progn
(set (make-local-variable 'compilation-font-lock-keywords)
verilog-error-font-lock-keywords)
(font-lock-set-defaults)))
;; Need to re-run compilation-error-regexp builder
(if (fboundp 'compilation-build-compilation-error-regexp-alist)
(compilation-build-compilation-error-regexp-alist))
))
;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
(defun verilog-error-regexp-add-emacs ()
"Tell Emacs compile that we are Verilog.
Called by `compilation-mode-hook'. This allows \\[next-error] to
find the errors."
(interactive)
(when (boundp 'compilation-error-regexp-alist-alist)
(when (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
(mapcar
(lambda (item)
(push (car item) compilation-error-regexp-alist)
(push item compilation-error-regexp-alist-alist))
verilog-error-regexp-emacs-alist))))
(if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
(if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
(defconst verilog-compiler-directives
(eval-when-compile
'(
;; compiler directives, from IEEE 1800-2012 section 22.1
"`__FILE__" "`__LINE" "`begin_keywords" "`celldefine" "`default_nettype"
"`define" "`else" "`elsif" "`end_keywords" "`endcelldefine" "`endif"
"`ifdef" "`ifndef" "`include" "`line" "`nounconnected_drive" "`pragma"
"`resetall" "`timescale" "`unconnected_drive" "`undef" "`undefineall"
;; compiler directives not covered by IEEE 1800
"`case" "`default" "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for"
"`format" "`if" "`let" "`protect" "`switch" "`timescale" "`time_scale"
"`while"
))
"List of Verilog compiler directives.")
(defconst verilog-directive-re
(verilog-regexp-words verilog-compiler-directives))
(defconst verilog-directive-re-1
(concat "[ \t]*" verilog-directive-re))
(defconst verilog-directive-begin
"\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
(defconst verilog-directive-middle
"\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
(defconst verilog-directive-end
"`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
(defconst verilog-ovm-begin-re
(eval-when-compile
(verilog-regexp-opt
'(
"`ovm_component_utils_begin"
"`ovm_component_param_utils_begin"
"`ovm_field_utils_begin"
"`ovm_object_utils_begin"
"`ovm_object_param_utils_begin"
"`ovm_sequence_utils_begin"
"`ovm_sequencer_utils_begin"
) nil )))
(defconst verilog-ovm-end-re
(eval-when-compile
(verilog-regexp-opt
'(
"`ovm_component_utils_end"
"`ovm_field_utils_end"
"`ovm_object_utils_end"
"`ovm_sequence_utils_end"
"`ovm_sequencer_utils_end"
) nil )))
(defconst verilog-uvm-begin-re
(eval-when-compile
(verilog-regexp-opt
'(
"`uvm_component_utils_begin"
"`uvm_component_param_utils_begin"
"`uvm_field_utils_begin"
"`uvm_object_utils_begin"
"`uvm_object_param_utils_begin"
"`uvm_sequence_utils_begin"
"`uvm_sequencer_utils_begin"
) nil )))
(defconst verilog-uvm-end-re
(eval-when-compile
(verilog-regexp-opt
'(
"`uvm_component_utils_end"
"`uvm_field_utils_end"
"`uvm_object_utils_end"
"`uvm_sequence_utils_end"
"`uvm_sequencer_utils_end"
) nil )))
(defconst verilog-vmm-begin-re
(eval-when-compile
(verilog-regexp-opt
'(
"`vmm_data_member_begin"
"`vmm_env_member_begin"
"`vmm_scenario_member_begin"
"`vmm_subenv_member_begin"
"`vmm_xactor_member_begin"
) nil ) ) )
(defconst verilog-vmm-end-re
(eval-when-compile
(verilog-regexp-opt
'(
"`vmm_data_member_end"
"`vmm_env_member_end"
"`vmm_scenario_member_end"
"`vmm_subenv_member_end"
"`vmm_xactor_member_end"
) nil ) ) )
(defconst verilog-vmm-statement-re
(eval-when-compile
(verilog-regexp-opt
'(
"`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
;; "`vmm_xactor_member_enum_array"
;; "`vmm_xactor_member_scalar_array"
;; "`vmm_xactor_member_scalar"
) nil )))
(defconst verilog-ovm-statement-re
(eval-when-compile
(verilog-regexp-opt
'(
;; Statements
"`DUT_ERROR"
"`MESSAGE"
"`dut_error"
"`message"
"`ovm_analysis_imp_decl"
"`ovm_blocking_get_imp_decl"
"`ovm_blocking_get_peek_imp_decl"
"`ovm_blocking_master_imp_decl"
"`ovm_blocking_peek_imp_decl"
"`ovm_blocking_put_imp_decl"
"`ovm_blocking_slave_imp_decl"
"`ovm_blocking_transport_imp_decl"
"`ovm_component_registry"
"`ovm_component_registry_param"
"`ovm_component_utils"
"`ovm_create"
"`ovm_create_seq"
"`ovm_declare_sequence_lib"
"`ovm_do"
"`ovm_do_seq"
"`ovm_do_seq_with"
"`ovm_do_with"
"`ovm_error"
"`ovm_fatal"
"`ovm_field_aa_int_byte"
"`ovm_field_aa_int_byte_unsigned"
"`ovm_field_aa_int_int"
"`ovm_field_aa_int_int_unsigned"
"`ovm_field_aa_int_integer"
"`ovm_field_aa_int_integer_unsigned"
"`ovm_field_aa_int_key"
"`ovm_field_aa_int_longint"
"`ovm_field_aa_int_longint_unsigned"
"`ovm_field_aa_int_shortint"
"`ovm_field_aa_int_shortint_unsigned"
"`ovm_field_aa_int_string"
"`ovm_field_aa_object_int"
"`ovm_field_aa_object_string"
"`ovm_field_aa_string_int"
"`ovm_field_aa_string_string"
"`ovm_field_array_int"
"`ovm_field_array_object"
"`ovm_field_array_string"
"`ovm_field_enum"
"`ovm_field_event"
"`ovm_field_int"
"`ovm_field_object"
"`ovm_field_queue_int"
"`ovm_field_queue_object"
"`ovm_field_queue_string"
"`ovm_field_sarray_int"
"`ovm_field_string"
"`ovm_field_utils"
"`ovm_file"
"`ovm_get_imp_decl"
"`ovm_get_peek_imp_decl"
"`ovm_info"
"`ovm_info1"
"`ovm_info2"
"`ovm_info3"
"`ovm_info4"
"`ovm_line"
"`ovm_master_imp_decl"
"`ovm_msg_detail"
"`ovm_non_blocking_transport_imp_decl"
"`ovm_nonblocking_get_imp_decl"
"`ovm_nonblocking_get_peek_imp_decl"
"`ovm_nonblocking_master_imp_decl"
"`ovm_nonblocking_peek_imp_decl"
"`ovm_nonblocking_put_imp_decl"
"`ovm_nonblocking_slave_imp_decl"
"`ovm_object_registry"
"`ovm_object_registry_param"
"`ovm_object_utils"
"`ovm_peek_imp_decl"
"`ovm_phase_func_decl"
"`ovm_phase_task_decl"
"`ovm_print_aa_int_object"
"`ovm_print_aa_string_int"
"`ovm_print_aa_string_object"
"`ovm_print_aa_string_string"
"`ovm_print_array_int"
"`ovm_print_array_object"
"`ovm_print_array_string"
"`ovm_print_object_queue"
"`ovm_print_queue_int"
"`ovm_print_string_queue"
"`ovm_put_imp_decl"
"`ovm_rand_send"
"`ovm_rand_send_with"
"`ovm_send"
"`ovm_sequence_utils"
"`ovm_slave_imp_decl"
"`ovm_transport_imp_decl"
"`ovm_update_sequence_lib"
"`ovm_update_sequence_lib_and_item"
"`ovm_warning"
"`static_dut_error"
"`static_message") nil )))
(defconst verilog-uvm-statement-re
(eval-when-compile
(verilog-regexp-opt
'(
;; Statements
"`uvm_analysis_imp_decl"
"`uvm_blocking_get_imp_decl"
"`uvm_blocking_get_peek_imp_decl"
"`uvm_blocking_master_imp_decl"
"`uvm_blocking_peek_imp_decl"
"`uvm_blocking_put_imp_decl"
"`uvm_blocking_slave_imp_decl"
"`uvm_blocking_transport_imp_decl"
"`uvm_component_param_utils"
"`uvm_component_registry"
"`uvm_component_registry_param"
"`uvm_component_utils"
"`uvm_create"
"`uvm_create_on"
"`uvm_create_seq" ; Undocumented in 1.1
"`uvm_declare_p_sequencer"
"`uvm_declare_sequence_lib" ; Deprecated in 1.1
"`uvm_do"
"`uvm_do_callbacks"
"`uvm_do_callbacks_exit_on"
"`uvm_do_obj_callbacks"
"`uvm_do_obj_callbacks_exit_on"
"`uvm_do_on"
"`uvm_do_on_pri"
"`uvm_do_on_pri_with"
"`uvm_do_on_with"
"`uvm_do_pri"
"`uvm_do_pri_with"
"`uvm_do_seq" ; Undocumented in 1.1
"`uvm_do_seq_with" ; Undocumented in 1.1
"`uvm_do_with"
"`uvm_error"
"`uvm_error_context"
"`uvm_fatal"
"`uvm_fatal_context"
"`uvm_field_aa_int_byte"
"`uvm_field_aa_int_byte_unsigned"
"`uvm_field_aa_int_enum"
"`uvm_field_aa_int_int"
"`uvm_field_aa_int_int_unsigned"
"`uvm_field_aa_int_integer"
"`uvm_field_aa_int_integer_unsigned"
"`uvm_field_aa_int_key"
"`uvm_field_aa_int_longint"
"`uvm_field_aa_int_longint_unsigned"
"`uvm_field_aa_int_shortint"
"`uvm_field_aa_int_shortint_unsigned"
"`uvm_field_aa_int_string"
"`uvm_field_aa_object_int"
"`uvm_field_aa_object_string"
"`uvm_field_aa_string_int"
"`uvm_field_aa_string_string"
"`uvm_field_array_enum"
"`uvm_field_array_int"
"`uvm_field_array_object"
"`uvm_field_array_string"
"`uvm_field_enum"
"`uvm_field_event"
"`uvm_field_int"
"`uvm_field_object"
"`uvm_field_queue_enum"
"`uvm_field_queue_int"
"`uvm_field_queue_object"
"`uvm_field_queue_string"
"`uvm_field_real"
"`uvm_field_sarray_enum"
"`uvm_field_sarray_int"
"`uvm_field_sarray_object"
"`uvm_field_sarray_string"
"`uvm_field_string"
"`uvm_field_utils"
"`uvm_file" ; Undocumented in 1.1, use `__FILE__
"`uvm_get_imp_decl"
"`uvm_get_peek_imp_decl"
"`uvm_info"
"`uvm_info_context"
"`uvm_line" ; Undocumented in 1.1, use `__LINE__
"`uvm_master_imp_decl"
"`uvm_non_blocking_transport_imp_decl" ; Deprecated in 1.1
"`uvm_nonblocking_get_imp_decl"
"`uvm_nonblocking_get_peek_imp_decl"
"`uvm_nonblocking_master_imp_decl"
"`uvm_nonblocking_peek_imp_decl"
"`uvm_nonblocking_put_imp_decl"
"`uvm_nonblocking_slave_imp_decl"
"`uvm_nonblocking_transport_imp_decl"
"`uvm_object_param_utils"
"`uvm_object_registry"
"`uvm_object_registry_param" ; Undocumented in 1.1
"`uvm_object_utils"
"`uvm_pack_array"
"`uvm_pack_arrayN"
"`uvm_pack_enum"
"`uvm_pack_enumN"
"`uvm_pack_int"
"`uvm_pack_intN"
"`uvm_pack_queue"
"`uvm_pack_queueN"
"`uvm_pack_real"
"`uvm_pack_sarray"
"`uvm_pack_sarrayN"
"`uvm_pack_string"
"`uvm_peek_imp_decl"
"`uvm_put_imp_decl"
"`uvm_rand_send"
"`uvm_rand_send_pri"
"`uvm_rand_send_pri_with"
"`uvm_rand_send_with"
"`uvm_record_attribute"
"`uvm_record_field"
"`uvm_register_cb"
"`uvm_send"
"`uvm_send_pri"
"`uvm_sequence_utils" ; Deprecated in 1.1
"`uvm_set_super_type"
"`uvm_slave_imp_decl"
"`uvm_transport_imp_decl"
"`uvm_unpack_array"
"`uvm_unpack_arrayN"
"`uvm_unpack_enum"
"`uvm_unpack_enumN"
"`uvm_unpack_int"
"`uvm_unpack_intN"
"`uvm_unpack_queue"
"`uvm_unpack_queueN"
"`uvm_unpack_real"
"`uvm_unpack_sarray"
"`uvm_unpack_sarrayN"
"`uvm_unpack_string"
"`uvm_update_sequence_lib" ; Deprecated in 1.1
"`uvm_update_sequence_lib_and_item" ; Deprecated in 1.1
"`uvm_warning"
"`uvm_warning_context") nil )))
;;
;; Regular expressions used to calculate indent, etc.
;;
(defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
;; Want to match
;; aa :
;; aa,bb :
;; a[34:32] :
;; a,
;; b :
(defconst verilog-assignment-operator-re
(eval-when-compile
(verilog-regexp-opt
`(
;; blocking assignment_operator
"=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
;; non blocking assignment operator
"<="
;; comparison
"==" "!=" "===" "!==" "<=" ">=" "==?" "!=?" "<->"
;; event_trigger
"->" "->>"
;; property_expr
"|->" "|=>" "#-#" "#=#"
;; distribution weighting
":=" ":/"
) 't
)))
(defconst verilog-assignment-operation-re
(concat
;; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
;; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
"\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
(defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
(defconst verilog-property-re
(concat "\\(" verilog-label-re "\\)?"
;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
"\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\\\)\\|\\(assert\\)"))
(defconst verilog-no-indent-begin-re
(eval-when-compile
(verilog-regexp-words
'("always" "always_comb" "always_ff" "always_latch" "initial" "final" ; procedural blocks
"if" "else" ; conditional statements
"while" "for" "foreach" "repeat" "do" "forever" )))) ; loop statements
(defconst verilog-ends-re
;; Parenthesis indicate type of keyword found
(concat
"\\(\\\\)\\|" ; 1
"\\(\\\\)\\|" ; 2
"\\(\\\\)\\|" ; 3
"\\(\\\\)\\|" ; 3.1
"\\(\\\\)\\|" ; 4
"\\(\\\\)\\|" ; 5
"\\(\\\\)\\|" ; 6
"\\(\\\\)\\|" ; 7
"\\(\\\\)\\|" ; 8
"\\(\\\\)\\|" ; 9
"\\(\\\\)\\|" ; 10
"\\(\\\\)\\|" ; 11
"\\(\\\\)\\|" ; 12
;; VMM
"\\(\\<`vmm_data_member_end\\>\\)\\|"
"\\(\\<`vmm_env_member_end\\>\\)\\|"
"\\(\\<`vmm_scenario_member_end\\>\\)\\|"
"\\(\\<`vmm_subenv_member_end\\>\\)\\|"
"\\(\\<`vmm_xactor_member_end\\>\\)\\|"
;; OVM
"\\(\\<`ovm_component_utils_end\\>\\)\\|"
"\\(\\<`ovm_field_utils_end\\>\\)\\|"
"\\(\\<`ovm_object_utils_end\\>\\)\\|"
"\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
"\\(\\<`ovm_sequencer_utils_end\\>\\)"
;; UVM
"\\(\\<`uvm_component_utils_end\\>\\)\\|"
"\\(\\<`uvm_field_utils_end\\>\\)\\|"
"\\(\\<`uvm_object_utils_end\\>\\)\\|"
"\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
"\\(\\<`uvm_sequencer_utils_end\\>\\)"
))
(defconst verilog-auto-end-comment-lines-re
;; Matches to names in this list cause auto-end-commenting
(concat "\\("
verilog-directive-re "\\)\\|\\("
(eval-when-compile
(verilog-regexp-words
`( "begin"
"else"
"end"
"endcase"
"endclass"
"endclocking"
"endgroup"
"endfunction"
"endmodule"
"endprogram"
"endprimitive"
"endinterface"
"endpackage"
"endsequence"
"endproperty"
"endspecify"
"endtable"
"endtask"
"join"
"join_any"
"join_none"
"module"
"macromodule"
"primitive"
"interface"
"package")))
"\\)"))
;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
;; verilog-end-block-ordered-re matches exactly the same strings.
(defconst verilog-end-block-ordered-re
;; Parenthesis indicate type of keyword found
(concat "\\(\\\\)\\|" ; 1
"\\(\\\\)\\|" ; 2
"\\(\\\\)"))
(defconst verilog-end-block-re
(eval-when-compile
(verilog-regexp-words
`("end" ; closes begin
"endcase" ; closes any of case, casex casez or randcase
"join" "join_any" "join_none" ; closes fork
"endclass"
"endtable"
"endspecify"
"endfunction"
"endgenerate"
"endtask"
"endgroup"
"endproperty"
"endinterface"
"endpackage"
"endprogram"
"endsequence"
"endclocking"
;; OVM
"`ovm_component_utils_end"
"`ovm_field_utils_end"
"`ovm_object_utils_end"
"`ovm_sequence_utils_end"
"`ovm_sequencer_utils_end"
;; UVM
"`uvm_component_utils_end"
"`uvm_field_utils_end"
"`uvm_object_utils_end"
"`uvm_sequence_utils_end"
"`uvm_sequencer_utils_end"
;; VMM
"`vmm_data_member_end"
"`vmm_env_member_end"
"`vmm_scenario_member_end"
"`vmm_subenv_member_end"
"`vmm_xactor_member_end"
))))
(defconst verilog-endcomment-reason-re
;; Parenthesis indicate type of keyword found
(concat
"\\(\\\\)\\|" ; 1
"\\(\\\\)\\|" ; 2
"\\(\\\\s-+\\\\)\\|" ; 3
"\\(\\\\(?:[ \t]*@\\)\\)\\|" ; 4 (matches always or always_ff w/ @...)
"\\(\\\\)\\|" ; 5 (matches always, always_comb, always_latch w/o @...)
"\\(\\\\)\\|" ; 7
"\\(\\\\)\\|"
verilog-property-re "\\|"
"\\(\\(" verilog-label-re "\\)?\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(@\\)\\|"
"\\(\\\\)\\|\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|\\(\\\\)\\|"
"#"))
(defconst verilog-named-block-re "begin[ \t]*:")
;; These words begin a block which can occur inside a module which should be indented,
;; and closed with the respective word from the end-block list
(defconst verilog-beg-block-re
(eval-when-compile
(verilog-regexp-words
`("begin"
"case" "casex" "casez" "randcase"
"clocking"
"generate"
"fork"
"function"
"property"
"specify"
"table"
"task"
;; OVM
"`ovm_component_utils_begin"
"`ovm_component_param_utils_begin"
"`ovm_field_utils_begin"
"`ovm_object_utils_begin"
"`ovm_object_param_utils_begin"
"`ovm_sequence_utils_begin"
"`ovm_sequencer_utils_begin"
;; UVM
"`uvm_component_utils_begin"
"`uvm_component_param_utils_begin"
"`uvm_field_utils_begin"
"`uvm_object_utils_begin"
"`uvm_object_param_utils_begin"
"`uvm_sequence_utils_begin"
"`uvm_sequencer_utils_begin"
;; VMM
"`vmm_data_member_begin"
"`vmm_env_member_begin"
"`vmm_scenario_member_begin"
"`vmm_subenv_member_begin"
"`vmm_xactor_member_begin"
))))
;; These are the same words, in a specific order in the regular
;; expression so that matching will work nicely for
;; verilog-forward-sexp and verilog-calc-indent
(defconst verilog-beg-block-re-ordered
( concat "\\(\\\\)" ;1
"\\|\\(\\\\|\\(\\\\)" ; 2,3
"\\|\\(\\(\\\\s-+\\|\\\\s-+\\)?fork\\>\\)" ;4,5
"\\|\\(\\\\)" ;6
"\\|\\(\\\\)" ;7
"\\|\\(\\\\)" ;8
"\\|\\(\\\\)" ;9
"\\|\\(\\(?:\\<\\(?:virtual\\|protected\\|static\\)\\>\\s-+\\)*\\\\)" ;10
"\\|\\(\\\\)" ;11
"\\|\\(\\(?:\\<\\(?:virtual\\|protected\\|static\\)\\>\\s-+\\)*\\\\)" ;12
"\\|\\(\\\\)" ;13
"\\|\\(\\\\)" ;14
"\\|\\(\\(?:\\(?:\\\\s-+\\)\\|\\(?:\\\\s-+\\)\\)*\\\\)" ;15
"\\|\\(\\<\\(?:rand\\)?sequence\\>\\)" ;16
"\\|\\(\\\\)" ;17
"\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;18
"\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
;;
))
(defconst verilog-end-block-ordered-rry
[ "\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)"
"\\(\\\\|\\\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
"\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\\\)"
"\\(\\\\)\\|\\(\\\\)"
] )
(defconst verilog-nameable-item-re
(eval-when-compile
(verilog-regexp-words
`("begin"
"fork"
"join" "join_any" "join_none"
"end"
"endcase"
"endchecker"
"endclass"
"endclocking"
"endconfig"
"endfunction"
"endgenerate"
"endgroup"
"endmodule"
"endprimitive"
"endinterface"
"endpackage"
"endprogram"
"endproperty"
"endsequence"
"endspecify"
"endtable"
"endtask" )
)))
(defconst verilog-declaration-opener
(eval-when-compile
(verilog-regexp-words
`("module" "begin" "task" "function"))))
(defconst verilog-declaration-prefix-re
(eval-when-compile
(verilog-regexp-words
`(
;; port direction
"inout" "input" "output" "ref"
;; changeableness
"const" "static" "protected" "local"
;; parameters
"localparam" "parameter" "var"
;; type creation
"typedef"
))))
(defconst verilog-declaration-core-re
(eval-when-compile
(verilog-regexp-words
`(
;; port direction (by themselves)
"inout" "input" "output"
;; integer_atom_type
"byte" "shortint" "int" "longint" "integer" "time"
;; integer_vector_type
"bit" "logic" "reg"
;; non_integer_type
"shortreal" "real" "realtime"
;; net_type
"supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
;; misc
"string" "event" "chandle" "virtual" "enum" "genvar"
"struct" "union"
;; builtin classes
"mailbox" "semaphore"
))))
(defconst verilog-declaration-re
(concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
(defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
(defconst verilog-optional-signed-re "\\s-*\\(\\(un\\)?signed\\)?")
(defconst verilog-optional-signed-range-re
(concat
"\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<\\(un\\)?signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
(defconst verilog-macroexp-re "`\\sw+")
(defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
(defconst verilog-declaration-re-2-no-macro
(concat "\\s-*" verilog-declaration-re
"\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
"\\)?"))
(defconst verilog-declaration-re-2-macro
(concat "\\s-*" verilog-declaration-re
"\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
"\\|\\(" verilog-macroexp-re "\\)"
"\\)?"))
(defconst verilog-declaration-re-1-macro
(concat "^" verilog-declaration-re-2-macro))
(defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
(defconst verilog-defun-re
(eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
(defconst verilog-end-defun-re
(eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
(defconst verilog-zero-indent-re
(concat verilog-defun-re "\\|" verilog-end-defun-re))
(defconst verilog-inst-comment-re
(eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
(defconst verilog-behavioral-block-beg-re
(eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
"function" "task"))))
(defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
(defconst verilog-in-constraint-re ; keywords legal in constraint blocks starting a statement/block
(eval-when-compile (verilog-regexp-words `("if" "else" "solve" "foreach"))))
(defconst verilog-indent-re
(eval-when-compile
(verilog-regexp-words
`(
"{"
"always" "always_latch" "always_ff" "always_comb"
"begin" "end"
;; "unique" "priority"
"case" "casex" "casez" "randcase" "endcase"
"class" "endclass"
"clocking" "endclocking"
"config" "endconfig"
"covergroup" "endgroup"
"fork" "join" "join_any" "join_none"
"function" "endfunction"
"final"
"generate" "endgenerate"
"initial"
"interface" "endinterface"
"module" "macromodule" "endmodule"
"package" "endpackage"
"primitive" "endprimitive"
"program" "endprogram"
"property" "endproperty"
"sequence" "randsequence" "endsequence"
"specify" "endspecify"
"table" "endtable"
"task" "endtask"
"virtual"
"`case"
"`default"
"`define" "`undef"
"`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
"`while" "`endwhile"
"`for" "`endfor"
"`format"
"`include"
"`let"
"`protect" "`endprotect"
"`switch" "`endswitch"
"`timescale"
"`time_scale"
;; OVM Begin tokens
"`ovm_component_utils_begin"
"`ovm_component_param_utils_begin"
"`ovm_field_utils_begin"
"`ovm_object_utils_begin"
"`ovm_object_param_utils_begin"
"`ovm_sequence_utils_begin"
"`ovm_sequencer_utils_begin"
;; OVM End tokens
"`ovm_component_utils_end"
"`ovm_field_utils_end"
"`ovm_object_utils_end"
"`ovm_sequence_utils_end"
"`ovm_sequencer_utils_end"
;; UVM Begin tokens
"`uvm_component_utils_begin"
"`uvm_component_param_utils_begin"
"`uvm_field_utils_begin"
"`uvm_object_utils_begin"
"`uvm_object_param_utils_begin"
"`uvm_sequence_utils_begin"
"`uvm_sequencer_utils_begin"
;; UVM End tokens
"`uvm_component_utils_end" ; Typo in spec, it's not uvm_component_end
"`uvm_field_utils_end"
"`uvm_object_utils_end"
"`uvm_sequence_utils_end"
"`uvm_sequencer_utils_end"
;; VMM Begin tokens
"`vmm_data_member_begin"
"`vmm_env_member_begin"
"`vmm_scenario_member_begin"
"`vmm_subenv_member_begin"
"`vmm_xactor_member_begin"
;; VMM End tokens
"`vmm_data_member_end"
"`vmm_env_member_end"
"`vmm_scenario_member_end"
"`vmm_subenv_member_end"
"`vmm_xactor_member_end"
))))
(defconst verilog-defun-level-not-generate-re
(eval-when-compile
(verilog-regexp-words
`( "module" "macromodule" "primitive" "class" "program"
"interface" "package" "config"))))
(defconst verilog-defun-level-re
(eval-when-compile
(verilog-regexp-words
(append
`( "module" "macromodule" "primitive" "class" "program"
"interface" "package" "config")
`( "initial" "final" "always" "always_comb" "always_ff"
"always_latch" "endtask" "endfunction" )))))
(defconst verilog-defun-level-generate-only-re
(eval-when-compile
(verilog-regexp-words
`( "initial" "final" "always" "always_comb" "always_ff"
"always_latch" "endtask" "endfunction" ))))
(defconst verilog-cpp-level-re
(eval-when-compile
(verilog-regexp-words
`(
"endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
))))
(defconst verilog-dpi-import-export-re
(eval-when-compile
"\\(\\<\\(import\\|export\\)\\>\\s-+\"DPI\\(-C\\)?\"\\s-+\\(\\<\\(context\\|pure\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\<\\(function\\|task\\)\\>\\)"
))
(defconst verilog-default-clocking-re "\\")
(defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
(defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\|randcase\\)")
(defconst verilog-extended-complete-re
;; verilog-beg-of-statement also looks backward one token to extend this match
(concat "\\(\\(\\\\s-+\\)?virtual\\s-+\\|\\\\|\\\\)\\)"
"\\|\\(\\(\\\\s-+\\)*\\(\\\\|\\\\|\\\\)\\)"
"\\|\\(\\(\\<\\(import\\|export\\)\\>\\s-+\\)?\\(\"DPI\\(-C\\)?\"\\s-+\\)?\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\(function\\>\\|task\\>\\)\\)"
"\\|" verilog-extended-case-re ))
(defconst verilog-basic-complete-re
(eval-when-compile
(verilog-regexp-words
`(
"always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
"import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
"if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
))))
(defconst verilog-complete-reg
(concat
verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
(defconst verilog-end-statement-re
(concat "\\(" verilog-beg-block-re "\\)\\|\\("
verilog-end-block-re "\\)"))
(defconst verilog-endcase-re
(concat verilog-extended-case-re "\\|"
"\\(endcase\\)\\|"
verilog-defun-re
))
(defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
"String used to mark beginning of excluded text.")
(defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
"String used to mark end of excluded text.")
(defconst verilog-preprocessor-re
(eval-when-compile
(concat
;; single words
"\\(?:"
(verilog-regexp-words
`("`__FILE__"
"`__LINE__"
"`celldefine"
"`else"
"`end_keywords"
"`endcelldefine"
"`endif"
"`nounconnected_drive"
"`resetall"
"`unconnected_drive"
"`undefineall"))
"\\)\\|\\(?:"
;; two words: i.e. `ifdef DEFINE
"\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\\)\\>\\s-"
"\\)\\|\\(?:"
;; `line number "filename" level
"\\<\\(`line\\)\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]"
"\\)\\|\\(?:"
;;`include "file" or `include
"\\<\\(`include\\)\\>\\s-+\\(?:\"[^\"]+\"\\|<[^>]+>\\)"
"\\)\\|\\(?:"
;; `pragma (no mention in IEEE 1800-2012 that pragma can span multiple lines
"\\<\\(`pragma\\)\\>\\s-+.+$"
"\\)\\|\\(?:"
;; `timescale time_unit / time_precision
"\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*\\/\\s-*10\\{0,2\\}\\s-*[munpf]?s"
"\\)\\|\\(?:"
;; `define and `if can span multiple lines if line ends in '\'. NOTE: `if is not IEEE 1800-2012
;; from http://www.emacswiki.org/emacs/MultilineRegexp
(concat "\\<\\(`define\\|`if\\)\\>" ; directive
"\\s-+" ; separator
"\\(?:.*?\\(?:\n.*\\)*?\\)" ; definition: to end of line, then maybe more lines (excludes any trailing \n)
"\\(?:\n\\s-*\n\\|\\'\\)") ; blank line or EOF
"\\)\\|\\(?:"
;; `() : i.e. `uvm_info(a,b,c) or any other pre-defined macro
;; Since parameters inside the macro can have parentheses, and
;; the macro can span multiple lines, just look for the opening
;; parentheses and then continue to the end of the first
;; non-escaped EOL
(concat "\\<`\\w+\\>\\s-*("
"\\(?:.*?\\(?:\n.*\\)*?\\)" ; definition: to end of line, then maybe more lines (excludes any trailing \n)
"\\(?:\n\\s-*\n\\|\\'\\)") ; blank line or EOF
"\\)"
)))
(defconst verilog-keywords
(append verilog-compiler-directives
'(
"after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
"assert" "assign" "assume" "automatic" "before" "begin" "bind"
"bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
"case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
"config" "const" "constraint" "context" "continue" "cover"
"covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
"design" "disable" "dist" "do" "edge" "else" "end" "endcase"
"endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
"endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
"endprogram" "endproperty" "endspecify" "endsequence" "endtable"
"endtask" "enum" "event" "expect" "export" "extends" "extern"
"final" "first_match" "for" "force" "foreach" "forever" "fork"
"forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
"iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
"include" "initial" "inout" "input" "inside" "instance" "int"
"integer" "interface" "intersect" "join" "join_any" "join_none"
"large" "liblist" "library" "local" "localparam" "logic"
"longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
"nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
"notif0" "notif1" "null" "or" "output" "package" "packed"
"parameter" "pmos" "posedge" "primitive" "priority" "program"
"property" "protected" "pull0" "pull1" "pulldown" "pullup"
"pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
"randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
"release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
"rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
"showcancelled" "signed" "small" "solve" "specify" "specparam"
"static" "string" "strong0" "strong1" "struct" "super" "supply0"
"supply1" "table" "tagged" "task" "this" "throughout" "time"
"timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
"tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
"unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
"wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
"wire" "with" "within" "wor" "xnor" "xor"
;; 1800-2009
"accept_on" "checker" "endchecker" "eventually" "global" "implies"
"let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
"s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
"sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
;; 1800-2012
"implements" "interconnect" "nettype" "soft"
))
"List of Verilog keywords.")
(defconst verilog-comment-start-regexp "//\\|/\\*"
"Dual comment value for `comment-start-regexp'.")
(defvar verilog-mode-syntax-table
(let ((table (make-syntax-table)))
;; Populate the syntax TABLE.
(modify-syntax-entry ?\\ "\\" table)
(modify-syntax-entry ?+ "." table)
(modify-syntax-entry ?- "." table)
(modify-syntax-entry ?= "." table)
(modify-syntax-entry ?% "." table)
(modify-syntax-entry ?< "." table)
(modify-syntax-entry ?> "." table)
(modify-syntax-entry ?& "." table)
(modify-syntax-entry ?| "." table)
(modify-syntax-entry ?` "w" table) ; ` is part of definition symbols in Verilog
(modify-syntax-entry ?_ "w" table)
(modify-syntax-entry ?\' "." table)
;; Set up TABLE to handle block and line style comments.
(if (featurep 'xemacs)
(progn
;; XEmacs (formerly Lucid) has the best implementation
(modify-syntax-entry ?/ ". 1456" table)
(modify-syntax-entry ?* ". 23" table)
(modify-syntax-entry ?\n "> b" table))
;; Emacs does things differently, but we can work with it
(modify-syntax-entry ?/ ". 124b" table)
(modify-syntax-entry ?* ". 23" table)
(modify-syntax-entry ?\n "> b" table))
table)
"Syntax table used in Verilog mode buffers.")
(defvar verilog-font-lock-keywords nil
"Default highlighting for Verilog mode.")
(defvar verilog-font-lock-keywords-1 nil
"Subdued level highlighting for Verilog mode.")
(defvar verilog-font-lock-keywords-2 nil
"Medium level highlighting for Verilog mode.
See also `verilog-font-lock-extra-types'.")
(defvar verilog-font-lock-keywords-3 nil
"Gaudy level highlighting for Verilog mode.
See also `verilog-font-lock-extra-types'.")
(defvar verilog-font-lock-translate-off-face
'verilog-font-lock-translate-off-face
"Font to use for translated off regions.")
(defface verilog-font-lock-translate-off-face
'((((class color)
(background light))
(:background "gray90" :italic t ))
(((class color)
(background dark))
(:background "gray10" :italic t ))
(((class grayscale) (background light))
(:foreground "DimGray" :italic t))
(((class grayscale) (background dark))
(:foreground "LightGray" :italic t))
(t (:italis t)))
"Font lock mode face used to background highlight translate-off regions."
:group 'font-lock-highlighting-faces)
(defvar verilog-font-lock-p1800-face
'verilog-font-lock-p1800-face
"Font to use for p1800 keywords.")
(defface verilog-font-lock-p1800-face
'((((class color)
(background light))
(:foreground "DarkOrange3" :bold t ))
(((class color)
(background dark))
(:foreground "orange1" :bold t ))
(t (:italic t)))
"Font lock mode face used to highlight P1800 keywords."
:group 'font-lock-highlighting-faces)
(defvar verilog-font-lock-ams-face
'verilog-font-lock-ams-face
"Font to use for Analog/Mixed Signal keywords.")
(defface verilog-font-lock-ams-face
'((((class color)
(background light))
(:foreground "Purple" :bold t ))
(((class color)
(background dark))
(:foreground "orange1" :bold t ))
(t (:italic t)))
"Font lock mode face used to highlight AMS keywords."
:group 'font-lock-highlighting-faces)
(defvar verilog-font-lock-grouping-keywords-face
'verilog-font-lock-grouping-keywords-face
"Font to use for Verilog Grouping Keywords (such as begin..end).")
(defface verilog-font-lock-grouping-keywords-face
'((((class color)
(background light))
(:foreground "Purple" :bold t ))
(((class color)
(background dark))
(:foreground "orange1" :bold t ))
(t (:italic t)))
"Font lock mode face used to highlight verilog grouping keywords."
:group 'font-lock-highlighting-faces)
(let* ((verilog-type-font-keywords
(eval-when-compile
(verilog-regexp-opt
'(
"and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
"event" "genvar" "inout" "input" "integer" "localparam"
"logic" "mailbox" "nand" "nmos" "nor" "not" "notif0" "notif1" "or"
"output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
"rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
"rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
"supply0" "supply1" "time" "tran" "tranif0" "tranif1"
"tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
"uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
) nil )))
(verilog-pragma-keywords
(eval-when-compile
(verilog-regexp-opt
'("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
) nil )))
(verilog-1800-2005-keywords
(eval-when-compile
(verilog-regexp-opt
'("alias" "assert" "assume" "automatic" "before" "bind"
"bins" "binsof" "break" "byte" "cell" "chandle" "class"
"clocking" "config" "const" "constraint" "context" "continue"
"cover" "covergroup" "coverpoint" "cross" "deassign" "design"
"dist" "do" "edge" "endclass" "endclocking" "endconfig"
"endgroup" "endprogram" "endproperty" "endsequence" "enum"
"expect" "export" "extends" "extern" "first_match" "foreach"
"forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
"illegal_bins" "import" "incdir" "include" "inside" "instance"
"int" "intersect" "large" "liblist" "library" "local" "longint"
"matches" "medium" "modport" "new" "noshowcancelled" "null"
"packed" "program" "property" "protected" "pull0" "pull1"
"pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
"randcase" "randsequence" "ref" "release" "return" "scalared"
"sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
"specparam" "static" "string" "strong0" "strong1" "struct"
"super" "tagged" "this" "throughout" "timeprecision" "timeunit"
"type" "union" "unsigned" "use" "var" "virtual" "void"
"wait_order" "weak0" "weak1" "wildcard" "with" "within"
) nil )))
(verilog-1800-2009-keywords
(eval-when-compile
(verilog-regexp-opt
'("accept_on" "checker" "endchecker" "eventually" "global"
"implies" "let" "nexttime" "reject_on" "restrict" "s_always"
"s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
"sync_accept_on" "sync_reject_on" "unique0" "until"
"until_with" "untyped" "weak" ) nil )))
(verilog-1800-2012-keywords
(eval-when-compile
(verilog-regexp-opt
'("implements" "interconnect" "nettype" "soft" ) nil )))
(verilog-ams-keywords
(eval-when-compile
(verilog-regexp-opt
'("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
"aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
"branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
"ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
"endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
"floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
"initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
"last_crossing" "limexp" "ln" "log" "max" "min" "nature"
"net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
"sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
"wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
(verilog-font-keywords
(eval-when-compile
(verilog-regexp-opt
'(
"assign" "case" "casex" "casez" "randcase" "deassign"
"default" "disable" "else" "endcase" "endfunction"
"endgenerate" "endinterface" "endmodule" "endprimitive"
"endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
"continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
"interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
"package" "endpackage" "always" "always_comb" "always_ff"
"always_latch" "posedge" "primitive" "priority" "release"
"repeat" "specify" "table" "task" "unique" "wait" "while"
"class" "program" "endclass" "endprogram"
) nil )))
(verilog-font-grouping-keywords
(eval-when-compile
(verilog-regexp-opt
'( "begin" "end" ) nil ))))
(setq verilog-font-lock-keywords
(list
;; Fontify all builtin keywords
(concat "\\<\\(" verilog-font-keywords "\\|"
;; And user/system tasks and functions
"\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
"\\)\\>")
;; Fontify all types
(if verilog-highlight-grouping-keywords
(cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
'verilog-font-lock-grouping-keywords-face)
(cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
'font-lock-type-face))
(cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
'font-lock-type-face)
;; Fontify IEEE-1800-2005 keywords appropriately
(if verilog-highlight-p1800-keywords
(cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
'verilog-font-lock-p1800-face)
(cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
'font-lock-type-face))
;; Fontify IEEE-1800-2009 keywords appropriately
(if verilog-highlight-p1800-keywords
(cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
'verilog-font-lock-p1800-face)
(cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
'font-lock-type-face))
;; Fontify IEEE-1800-2012 keywords appropriately
(if verilog-highlight-p1800-keywords
(cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
'verilog-font-lock-p1800-face)
(cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
'font-lock-type-face))
;; Fontify Verilog-AMS keywords
(cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
'verilog-font-lock-ams-face)))
(setq verilog-font-lock-keywords-1
(append verilog-font-lock-keywords
(list
;; Fontify module definitions
(list
"\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
'(1 font-lock-keyword-face)
'(3 font-lock-function-name-face 'prepend))
;; Fontify function definitions
(list
(concat "\\\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
'(1 font-lock-keyword-face)
'(3 font-lock-constant-face prepend))
'("\\\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
(1 font-lock-keyword-face)
(2 font-lock-constant-face append))
'("\\\\s-+\\(\\sw+\\)"
1 'font-lock-constant-face append))))
(setq verilog-font-lock-keywords-2
(append verilog-font-lock-keywords-1
(list
;; Fontify pragmas
(concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
;; Fontify escaped names
'("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
;; Fontify macro definitions/ uses
'("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
'font-lock-preprocessor-face
'font-lock-type-face))
;; Fontify delays/numbers
'("\\(@\\)\\|\\([ \t\n\f\r]#\\s-*\\(\\([0-9_.]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
0 font-lock-type-face append)
;; Fontify property/sequence cycle delays - these start with '##'
'("\\(##\\(\\sw+\\|\\[[^]]+\\]\\)\\)"
0 font-lock-type-face append)
;; Fontify instantiation names
'("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
)))
(setq verilog-font-lock-keywords-3
(append verilog-font-lock-keywords-2
(when verilog-highlight-translate-off
(list
;; Fontify things in translate off regions
'(verilog-match-translate-off
(0 'verilog-font-lock-translate-off-face prepend))
)))))
;;
;; Buffer state preservation
(defmacro verilog-save-buffer-state (&rest body)
"Execute BODY forms, saving state around insignificant change.
Changes in text properties like `face' or `syntax-table' are
considered insignificant. This macro allows text properties to
be changed, even in a read-only buffer.
A change is considered significant if it affects the buffer text
in any way that isn't completely restored again. Any
user-visible changes to the buffer must not be within a
`verilog-save-buffer-state'."
`(let ((inhibit-point-motion-hooks t)
(verilog-no-change-functions t))
,(if (fboundp 'with-silent-modifications)
`(with-silent-modifications ,@body)
;; Backward compatible version of with-silent-modifications
`(let* ((modified (buffer-modified-p))
(buffer-undo-list t)
(inhibit-read-only t)
(inhibit-modification-hooks t)
;; XEmacs ignores inhibit-modification-hooks.
before-change-functions after-change-functions
deactivate-mark
buffer-file-name ; Prevent primitives checking
buffer-file-truename) ; for file modification
(unwind-protect
(progn ,@body)
(and (not modified)
(buffer-modified-p)
(verilog-restore-buffer-modified-p nil)))))))
(defvar verilog-save-font-mod-hooked nil
"Local variable when inside a `verilog-save-font-no-change-functions' block.")
(make-variable-buffer-local 'verilog-save-font-mod-hooked)
(defmacro verilog-save-font-no-change-functions (&rest body)
"Execute BODY forms, disabling all change hooks in BODY.
Includes temporary disabling of `font-lock' to restore the buffer
to full text form for parsing. Additional actions may be specified with
`verilog-before-save-font-hook' and `verilog-after-save-font-hook'.
For insignificant changes, see instead `verilog-save-buffer-state'."
`(if verilog-save-font-mod-hooked ; Short-circuit a recursive call
(progn ,@body)
;; Before version 20, match-string with font-lock returns a
;; vector that is not equal to the string. IE if on "input"
;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
;; Therefore we must remove and restore font-lock mode
(verilog-run-hooks 'verilog-before-save-font-hook)
(let* ((verilog-save-font-mod-hooked (- (point-max) (point-min)))
;; Significant speed savings with no font-lock properties
(fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
(font-lock-mode 0)
t)))
(run-hook-with-args 'before-change-functions (point-min) (point-max))
(unwind-protect
;; Must inhibit and restore hooks before restoring font-lock
(let* ((inhibit-point-motion-hooks t)
(inhibit-modification-hooks t)
(verilog-no-change-functions t)
;; XEmacs and pre-Emacs 21 ignore inhibit-modification-hooks.
before-change-functions after-change-functions)
(progn ,@body))
;; Unwind forms
(run-hook-with-args 'after-change-functions (point-min) (point-max)
verilog-save-font-mod-hooked) ; old length
(when fontlocked (font-lock-mode t))
(verilog-run-hooks 'verilog-after-save-font-hook)))))
;;
;; Comment detection and caching
(defvar verilog-scan-cache-preserving nil
"If true, the specified buffer's comment properties are static.
Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
and `verilog-scan'.")
(defvar verilog-scan-cache-tick nil
"Modification tick at which `verilog-scan' was last completed.")
(make-variable-buffer-local 'verilog-scan-cache-tick)
(defun verilog-scan-cache-flush ()
"Flush the `verilog-scan' cache."
(setq verilog-scan-cache-tick nil))
(defun verilog-scan-cache-ok-p ()
"Return t if the scan cache is up to date."
(or (and verilog-scan-cache-preserving
(eq verilog-scan-cache-preserving (current-buffer))
verilog-scan-cache-tick)
(equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
(defmacro verilog-save-scan-cache (&rest body)
"Execute the BODY forms, allowing scan cache preservation within BODY.
This requires that insertions must use `verilog-insert'."
;; If the buffer is out of date, trash it, as we'll not check later the tick
;; Note this must work properly if there's multiple layers of calls
;; to verilog-save-scan-cache even with differing ticks.
`(progn
(unless (verilog-scan-cache-ok-p) ; Must be before let
(setq verilog-scan-cache-tick nil))
(let* ((verilog-scan-cache-preserving (current-buffer)))
(progn ,@body))))
(defun verilog-scan-region (beg end)
"Parse between BEG and END for `verilog-inside-comment-or-string-p'.
This creates v-cmts properties where comments are in force."
;; Why properties and not overlays? Overlays have much slower non O(1)
;; lookup times.
;; This function is warm - called on every verilog-insert
(save-excursion
(save-match-data
(verilog-save-buffer-state
(let (pt)
(goto-char beg)
(while (< (point) end)
(cond ((looking-at "//")
(setq pt (point))
(or (search-forward "\n" end t)
(goto-char end))
;; "1+": The leading // or /* itself isn't considered as
;; being "inside" the comment, so that a (search-backward)
;; that lands at the start of the // won't mis-indicate
;; it's inside a comment. Also otherwise it would be
;; hard to find a commented out /*AS*/ vs one that isn't
(put-text-property (1+ pt) (point) 'v-cmts t))
((looking-at "/\\*")
(setq pt (point))
(or (search-forward "*/" end t)
;; No error - let later code indicate it so we can
;; use inside functions on-the-fly
;;(error "%s: Unmatched /* */, at char %d"
;; (verilog-point-text) (point))
(goto-char end))
(put-text-property (1+ pt) (point) 'v-cmts t))
((looking-at "\"")
(setq pt (point))
(or (re-search-forward "[^\\]\"" end t) ; don't forward-char first, since we look for a non backslash first
;; No error - let later code indicate it so we can
(goto-char end))
(put-text-property (1+ pt) (point) 'v-cmts t))
(t
(forward-char 1)
(if (re-search-forward "[/\"]" end t)
(backward-char 1)
(goto-char end))))))))))
(defun verilog-scan ()
"Parse the buffer, marking all comments with properties.
Also assumes any text inserted since `verilog-scan-cache-tick'
either is ok to parse as a non-comment, or `verilog-insert' was used."
;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
(unless (verilog-scan-cache-ok-p)
(save-excursion
(verilog-save-buffer-state
(when verilog-debug
(message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
verilog-scan-cache-preserving verilog-scan-cache-tick
(buffer-chars-modified-tick)))
(remove-text-properties (point-min) (point-max) '(v-cmts nil))
(verilog-scan-region (point-min) (point-max))
(setq verilog-scan-cache-tick (buffer-chars-modified-tick))
(when verilog-debug (message "Scanning... done"))))))
(defun verilog-scan-debug ()
"For debugging, show with display face results of `verilog-scan'."
(font-lock-mode 0)
;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
(save-excursion
(goto-char (point-min))
(remove-text-properties (point-min) (point-max) '(face nil))
(while (not (eobp))
(cond ((get-text-property (point) 'v-cmts)
(put-text-property (point) (1+ (point)) `face 'underline)
;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
(forward-char 1))
(t
(goto-char (or (next-property-change (point)) (point-max))))))))
(defun verilog-scan-and-debug ()
"For debugging, run `verilog-scan' and `verilog-scan-debug'."
(let (verilog-scan-cache-preserving
verilog-scan-cache-tick)
(goto-char (point-min))
(verilog-scan)
(verilog-scan-debug)))
(defun verilog-inside-comment-or-string-p (&optional pos)
"Check if optional point POS is inside a comment.
This may require a slow pre-parse of the buffer with `verilog-scan'
to establish comment properties on all text."
;; This function is very hot
(verilog-scan)
(if pos
(and (>= pos (point-min))
(get-text-property pos 'v-cmts))
(get-text-property (point) 'v-cmts)))
(defun verilog-insert (&rest stuff)
"Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
Any insert that includes a comment must have the entire comment
inserted using a single call to `verilog-insert'."
(let ((pt (point)))
(while stuff
(insert (car stuff))
(setq stuff (cdr stuff)))
(verilog-scan-region pt (point))))
;; More searching
(defun verilog-declaration-end ()
(search-forward ";"))
(defun verilog-point-text (&optional pointnum)
"Return text describing where POINTNUM or current point is (for errors).
Use filename, if current buffer being edited shorten to just buffer name."
(concat (or (and (equal (window-buffer) (current-buffer))
(buffer-name))
buffer-file-name
(buffer-name))
":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
(defun electric-verilog-backward-sexp ()
"Move backward over one balanced expression."
(interactive)
;; before that see if we are in a comment
(verilog-backward-sexp))
(defun electric-verilog-forward-sexp ()
"Move forward over one balanced expression."
(interactive)
;; before that see if we are in a comment
(verilog-forward-sexp))
(defun verilog-forward-sexp-function (arg)
"Move forward ARG sexps."
;; Used by hs-minor-mode
(if (< arg 0)
(verilog-backward-sexp)
(verilog-forward-sexp)))
(defun verilog-backward-sexp ()
(let ((reg)
(elsec 1)
(found nil)
(st (point)))
(if (not (looking-at "\\<"))
(forward-word-strictly -1))
(cond
((verilog-skip-backward-comment-or-string))
((looking-at "\\")
(setq reg (concat
verilog-end-block-re
"\\|\\(\\\\)"
"\\|\\(\\\\)"))
(while (and (not found)
(verilog-re-search-backward reg nil 'move))
(cond
((match-end 1) ; matched verilog-end-block-re
;; try to leap back to matching outward block by striding across
;; indent level changing tokens then immediately
;; previous line governs indentation.
(verilog-leap-to-head))
((match-end 2) ; else, we're in deep
(setq elsec (1+ elsec)))
((match-end 3) ; found it
(setq elsec (1- elsec))
(if (= 0 elsec)
;; Now previous line describes syntax
(setq found 't))))))
((looking-at verilog-end-block-re)
(verilog-leap-to-head))
((looking-at "\\(endmodule\\>\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)")
(cond
((match-end 1)
(verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
((match-end 2)
(verilog-re-search-backward "\\" nil 'move))
((match-end 3)
(verilog-re-search-backward "\\" nil 'move))
((match-end 4)
(verilog-re-search-backward "\\" nil 'move))
((match-end 5)
(verilog-re-search-backward "\\" nil 'move))
((match-end 6)
(verilog-re-search-backward "\\" nil 'move))
(t
(goto-char st)
(backward-sexp 1))))
(t
(goto-char st)
(backward-sexp)))))
(defun verilog-forward-sexp ()
(let ((reg)
(md 2)
(st (point))
(nest 'yes))
(if (not (looking-at "\\<"))
(forward-word-strictly -1))
(cond
((verilog-skip-forward-comment-or-string)
(verilog-forward-syntactic-ws))
((looking-at verilog-beg-block-re-ordered)
(cond
((match-end 1);
;; Search forward for matching end
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 2)
;; Search forward for matching endcase
(setq reg "\\(\\\\|\\(\\\\s-+\\|\\\\s-+\\)?\\[^:]\\)\\|\\(\\\\)" )
(setq md 3) ; ender is third item in regexp
)
((match-end 4)
;; might be "disable fork" or "wait fork"
(let
(here)
(if (or
(looking-at verilog-disable-fork-re)
(and (looking-at "fork")
(progn
(setq here (point)) ; sometimes a fork is just a fork
(forward-word-strictly -1)
(looking-at verilog-disable-fork-re))))
(progn ; it is a disable fork; ignore it
(goto-char (match-end 0))
(forward-word-strictly 1)
(setq reg nil))
(progn ; it is a nice simple fork
(goto-char here) ; return from looking for "disable fork"
;; Search forward for matching join
(setq reg "\\(\\\\)\\|\\(\\\\)" )))))
((match-end 6)
;; Search forward for matching endclass
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 7)
;; Search forward for matching endtable
(setq reg "\\" )
(setq nest 'no))
((match-end 8)
;; Search forward for matching endspecify
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 9)
;; Search forward for matching endfunction
(setq reg "\\" )
(setq nest 'no))
((match-end 10)
;; Search forward for matching endfunction
(setq reg "\\" )
(setq nest 'no))
((match-end 11)
;; Search forward for matching endtask
(setq reg "\\" )
(setq nest 'no))
((match-end 12)
;; Search forward for matching endtask
(setq reg "\\" )
(setq nest 'no))
((match-end 12)
;; Search forward for matching endgenerate
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 13)
;; Search forward for matching endgroup
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 14)
;; Search forward for matching endproperty
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 15)
;; Search forward for matching endsequence
(setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\\\)" )
(setq md 3)) ; 3 to get to endsequence in the reg above
((match-end 17)
;; Search forward for matching endclocking
(setq reg "\\(\\\\)\\|\\(\\\\)" )))
(if (and reg
(forward-word-strictly 1))
(catch 'skip
(if (eq nest 'yes)
(let ((depth 1)
here)
(while (verilog-re-search-forward reg nil 'move)
(cond
((match-end md) ; a closer in regular expression, so we are climbing out
(setq depth (1- depth))
(if (= 0 depth) ; we are out!
(throw 'skip 1)))
((match-end 1) ; an opener in the r-e, so we are in deeper now
(setq here (point)) ; remember where we started
(goto-char (match-beginning 1))
(cond
((if (or
(looking-at verilog-disable-fork-re)
(and (looking-at "fork")
(progn
(forward-word-strictly -1)
(looking-at verilog-disable-fork-re))))
(progn ; it is a disable fork; another false alarm
(goto-char (match-end 0)))
(progn ; it is a simple fork (or has nothing to do with fork)
(goto-char here)
(setq depth (1+ depth))))))))))
(if (verilog-re-search-forward reg nil 'move)
(throw 'skip 1))))))
((looking-at (concat
"\\(\\<\\(macro\\)?module\\>\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)\\|"
"\\(\\\\)"))
(cond
((match-end 1)
(verilog-re-search-forward "\\" nil 'move))
((match-end 2)
(verilog-re-search-forward "\\" nil 'move))
((match-end 3)
(verilog-re-search-forward "\\" nil 'move))
((match-end 4)
(verilog-re-search-forward "\\" nil 'move))
((match-end 5)
(verilog-re-search-forward "\\" nil 'move))
((match-end 6)
(verilog-re-search-forward "\\" nil 'move))
(t
(goto-char st)
(if (= (following-char) ?\) )
(forward-char 1)
(forward-sexp 1)))))
(t
(goto-char st)
(if (= (following-char) ?\) )
(forward-char 1)
(forward-sexp 1))))))
(defun verilog-declaration-beg ()
(verilog-re-search-backward verilog-declaration-re (bobp) t))
;;
;;
;; Mode
;;
(defvar verilog-which-tool 1)
;;;###autoload
(define-derived-mode verilog-mode prog-mode "Verilog"
"Major mode for editing Verilog code.
\\
See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
AUTOs can improve coding efficiency.
Use \\[verilog-faq] for a pointer to frequently asked questions.
NEWLINE, TAB indents for Verilog code.
Delete converts tabs to spaces as it moves back.
Supports highlighting.
Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
with no args, if that value is non-nil.
Variables controlling indentation/edit style:
variable `verilog-indent-level' (default 3)
Indentation of Verilog statements with respect to containing block.
`verilog-indent-level-module' (default 3)
Absolute indentation of Module level Verilog statements.
Set to 0 to get initial and always statements lined up
on the left side of your screen.
`verilog-indent-level-declaration' (default 3)
Indentation of declarations with respect to containing block.
Set to 0 to get them list right under containing block.
`verilog-indent-level-behavioral' (default 3)
Indentation of first begin in a task or function block
Set to 0 to get such code to lined up underneath the task or
function keyword.
`verilog-indent-level-directive' (default 1)
Indentation of \\=`ifdef/\\=`endif blocks.
`verilog-cexp-indent' (default 1)
Indentation of Verilog statements broken across lines i.e.:
if (a)
begin
`verilog-case-indent' (default 2)
Indentation for case statements.
`verilog-auto-newline' (default nil)
Non-nil means automatically newline after semicolons and the punctuation
mark after an end.
`verilog-auto-indent-on-newline' (default t)
Non-nil means automatically indent line after newline.
`verilog-tab-always-indent' (default t)
Non-nil means TAB in Verilog mode should always reindent the current line,
regardless of where in the line point is when the TAB command is used.
`verilog-indent-begin-after-if' (default t)
Non-nil means to indent begin statements following a preceding
if, else, while, for and repeat statements, if any. Otherwise,
the begin is lined up with the preceding token. If t, you get:
if (a)
begin // amount of indent based on `verilog-cexp-indent'
otherwise you get:
if (a)
begin
`verilog-auto-endcomments' (default t)
Non-nil means a comment /* ... */ is set after the ends which ends
cases, tasks, functions and modules.
The type and name of the object will be set between the braces.
`verilog-minimum-comment-distance' (default 10)
Minimum distance (in lines) between begin and end required before a comment
will be inserted. Setting this variable to zero results in every
end acquiring a comment; the default avoids too many redundant
comments in tight quarters.
`verilog-auto-lineup' (default `declarations')
List of contexts where auto lineup of code should be done.
Variables controlling other actions:
`verilog-linter' (default `surelint')
Unix program to call to run the lint checker. This is the default
command for \\[compile-command] and \\[verilog-auto-save-compile].
See \\[customize] for the complete list of variables.
AUTO expansion functions are, in part:
\\[verilog-auto] Expand AUTO statements.
\\[verilog-delete-auto] Remove the AUTOs.
\\[verilog-inject-auto] Insert AUTOs for the first time.
Some other functions are:
\\[verilog-complete-word] Complete word with appropriate possibilities.
\\[verilog-mark-defun] Mark function.
\\[verilog-beg-of-defun] Move to beginning of current function.
\\[verilog-end-of-defun] Move to end of current function.
\\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
\\[verilog-comment-region] Put marked area in a comment.
\\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
\\[verilog-insert-block] Insert begin ... end.
\\[verilog-star-comment] Insert /* ... */.
\\[verilog-sk-always] Insert an always @(AS) begin .. end block.
\\[verilog-sk-begin] Insert a begin .. end block.
\\[verilog-sk-case] Insert a case block, prompting for details.
\\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
\\[verilog-sk-generate] Insert a generate .. endgenerate block.
\\[verilog-sk-header] Insert a header block at the top of file.
\\[verilog-sk-initial] Insert an initial begin .. end block.
\\[verilog-sk-fork] Insert a fork begin .. end .. join block.
\\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
\\[verilog-sk-ovm-class] Insert an OVM Class block.
\\[verilog-sk-uvm-object] Insert an UVM Object block.
\\[verilog-sk-uvm-component] Insert an UVM Component block.
\\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
\\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
\\[verilog-sk-specify] Insert a specify .. endspecify block.
\\[verilog-sk-task] Insert a task .. begin .. end endtask block.
\\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
\\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
\\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
\\[verilog-sk-if] Insert an if (..) begin .. end block.
\\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
\\[verilog-sk-comment] Insert a comment block.
\\[verilog-sk-assign] Insert an assign .. = ..; statement.
\\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
\\[verilog-sk-input] Insert an input declaration, prompting for details.
\\[verilog-sk-output] Insert an output declaration, prompting for details.
\\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
\\[verilog-sk-inout] Insert an inout declaration, prompting for details.
\\[verilog-sk-wire] Insert a wire declaration, prompting for details.
\\[verilog-sk-reg] Insert a register declaration, prompting for details.
\\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
Key bindings specific to `verilog-mode-map' are:
\\{verilog-mode-map}"
:abbrev-table verilog-mode-abbrev-table
(set (make-local-variable 'beginning-of-defun-function)
'verilog-beg-of-defun)
(set (make-local-variable 'end-of-defun-function)
'verilog-end-of-defun)
(set-syntax-table verilog-mode-syntax-table)
(set (make-local-variable 'indent-line-function)
#'verilog-indent-line-relative)
(set (make-local-variable 'comment-indent-function) 'verilog-comment-indent)
(set (make-local-variable 'parse-sexp-ignore-comments) nil)
(set (make-local-variable 'comment-start) "// ")
(set (make-local-variable 'comment-end) "")
(set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
(set (make-local-variable 'comment-multi-line) nil)
;; Set up for compilation
(setq verilog-which-tool 1)
(setq verilog-tool 'verilog-linter)
(verilog-set-compile-command)
(when (boundp 'hack-local-variables-hook) ; Also modify any file-local-variables
(add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
;; Setting up menus
(when (featurep 'xemacs)
(easy-menu-add verilog-stmt-menu)
(easy-menu-add verilog-menu)
(setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
;; Stuff for GNU Emacs
(set (make-local-variable 'font-lock-defaults)
`((verilog-font-lock-keywords
verilog-font-lock-keywords-1
verilog-font-lock-keywords-2
verilog-font-lock-keywords-3)
nil nil nil
,(if (functionp 'syntax-ppss)
;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
;; font-lock-beginning-of-syntax-function, so
;; font-lock-beginning-of-syntax-function, can't use
;; verilog-beg-of-defun.
nil
'verilog-beg-of-defun)))
;;------------------------------------------------------------
;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
;; all buffer local:
(unless noninteractive ; Else can't see the result, and change hooks are slow
(when (featurep 'xemacs)
(make-local-hook 'font-lock-mode-hook)
(make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
(make-local-hook 'after-change-functions))
(add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
(add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
(add-hook 'after-change-functions 'verilog-highlight-region t t))
;; Tell imenu how to handle Verilog.
(set (make-local-variable 'imenu-generic-expression)
verilog-imenu-generic-expression)
;; Tell which-func-modes that imenu knows about verilog
(when (and (boundp 'which-func-modes) (listp which-func-modes))
(add-to-list 'which-func-modes 'verilog-mode))
;; hideshow support
(when (boundp 'hs-special-modes-alist)
(unless (assq 'verilog-mode hs-special-modes-alist)
(setq hs-special-modes-alist
(cons '(verilog-mode-mode "\\" "\\" nil
verilog-forward-sexp-function)
hs-special-modes-alist))))
;; Stuff for autos
(add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
;; verilog-mode-hook call added by define-derived-mode
)
;;; Integration with the speedbar
;;
;; Avoid problems with XEmacs byte-compiles.
;; For GNU Emacs, the eval-after-load will handle if it isn't loaded yet.
(when (eval-when-compile (fboundp 'declare-function))
(declare-function speedbar-add-supported-extension "speedbar" (extension)))
(defun verilog-speedbar-initialize ()
"Initialize speedbar to understand `verilog-mode'."
;; Set Verilog file extensions (extracted from `auto-mode-alist')
(let ((mode-alist auto-mode-alist))
(while mode-alist
(when (eq (cdar mode-alist) 'verilog-mode)
(speedbar-add-supported-extension (caar mode-alist)))
(setq mode-alist (cdr mode-alist)))))
;; If the speedbar is loaded, execute initialization instructions right away,
;; otherwise add the initialization instructions to the speedbar loader.
(eval-after-load "speedbar" '(verilog-speedbar-initialize))
;;; Electric functions:
;;
(defun electric-verilog-terminate-line (&optional arg)
"Terminate line and indent next line.
With optional ARG, remove existing end of line comments."
(interactive)
;; before that see if we are in a comment
(let ((state (save-excursion (verilog-syntax-ppss))))
(cond
((nth 7 state) ; Inside // comment
(if (eolp)
(progn
(delete-horizontal-space)
(newline))
(progn
(newline)
(insert "// ")
(beginning-of-line)))
(verilog-indent-line))
((nth 4 state) ; Inside any comment (hence /**/)
(newline)
(verilog-more-comment))
((eolp)
;; First, check if current line should be indented
(if (save-excursion
(delete-horizontal-space)
(beginning-of-line)
(skip-chars-forward " \t")
(if (looking-at verilog-auto-end-comment-lines-re)
(let ((indent-str (verilog-indent-line)))
;; Maybe we should set some endcomments
(if verilog-auto-endcomments
(verilog-set-auto-endcomments indent-str arg))
(end-of-line)
(delete-horizontal-space)
(if arg
()
(newline))
nil)
(progn
(end-of-line)
(delete-horizontal-space)
't)))
;; see if we should line up assignments
(progn
(if (or (eq 'all verilog-auto-lineup)
(eq 'assignments verilog-auto-lineup))
(verilog-pretty-expr t "\\(<\\|:\\)?=" ))
(newline))
(forward-line 1))
;; Indent next line
(if verilog-auto-indent-on-newline
(verilog-indent-line)))
(t
(newline)))))
(defun electric-verilog-terminate-and-indent ()
"Insert a newline and indent for the next statement."
(interactive)
(electric-verilog-terminate-line 1))
(defun electric-verilog-semi ()
"Insert `;' character and reindent the line."
(interactive)
(verilog-insert-last-command-event)
(if (or (verilog-in-comment-or-string-p)
(verilog-in-escaped-name-p))
()
(save-excursion
(beginning-of-line)
(verilog-forward-ws&directives)
(verilog-indent-line))
(if (and verilog-auto-newline
(not (verilog-parenthesis-depth)))
(electric-verilog-terminate-line))))
(defun electric-verilog-semi-with-comment ()
"Insert `;' character, reindent the line and indent for comment."
(interactive)
(insert ";")
(save-excursion
(beginning-of-line)
(verilog-indent-line))
(indent-for-comment))
(defun electric-verilog-colon ()
"Insert `:' and do all indentations except line indent on this line."
(interactive)
(verilog-insert-last-command-event)
;; Do nothing if within string.
(if (or
(verilog-within-string)
(not (verilog-in-case-region-p)))
()
(save-excursion
(let ((p (point))
(lim (progn (verilog-beg-of-statement) (point))))
(goto-char p)
(verilog-backward-case-item lim)
(verilog-indent-line)))
;; (let ((verilog-tab-always-indent nil))
;; (verilog-indent-line))
))
;;(defun electric-verilog-equal ()
;; "Insert `=', and do indentation if within block."
;; (interactive)
;; (verilog-insert-last-command-event)
;; Could auto line up expressions, but not yet
;; (if (eq (car (verilog-calculate-indent)) 'block)
;; (let ((verilog-tab-always-indent nil))
;; (verilog-indent-command)))
;; )
(defun electric-verilog-tick ()
"Insert back-tick, and indent to column 0 if this is a CPP directive."
(interactive)
(verilog-insert-last-command-event)
(save-excursion
(if (verilog-in-directive-p)
(verilog-indent-line))))
(defun electric-verilog-tab ()
"Function called when TAB is pressed in Verilog mode."
(interactive)
;; If verilog-tab-always-indent, indent the beginning of the line.
(cond
;; The region is active, indent it.
((and (region-active-p)
(not (eq (region-beginning) (region-end))))
(indent-region (region-beginning) (region-end) nil))
((or verilog-tab-always-indent
(save-excursion
(skip-chars-backward " \t")
(bolp)))
(let* ((oldpnt (point))
(boi-point
(save-excursion
(beginning-of-line)
(skip-chars-forward " \t")
(verilog-indent-line)
(back-to-indentation)
(point))))
(if (< (point) boi-point)
(back-to-indentation)
(cond ((not verilog-tab-to-comment))
((not (eolp))
(end-of-line))
(t
(indent-for-comment)
(when (and (eolp) (= oldpnt (point)))
;; kill existing comment
(beginning-of-line)
(re-search-forward comment-start-skip oldpnt 'move)
(goto-char (match-beginning 0))
(skip-chars-backward " \t")
(kill-region (point) oldpnt)))))))
(t (progn (insert "\t")))))
;;; Interactive functions:
;;
(defun verilog-indent-buffer ()
"Indent-region the entire buffer as Verilog code.
To call this from the command line, see \\[verilog-batch-indent]."
(interactive)
(verilog-mode)
(indent-region (point-min) (point-max) nil))
(defun verilog-insert-block ()
"Insert Verilog begin ... end; block in the code with right indentation."
(interactive)
(verilog-indent-line)
(insert "begin")
(electric-verilog-terminate-line)
(save-excursion
(electric-verilog-terminate-line)
(insert "end")
(beginning-of-line)
(verilog-indent-line)))
(defun verilog-star-comment ()
"Insert Verilog star comment at point."
(interactive)
(verilog-indent-line)
(insert "/*")
(save-excursion
(newline)
(insert " */"))
(newline)
(insert " * "))
(defun verilog-insert-1 (fmt max)
"Use format string FMT to insert integers 0 to MAX - 1.
Inserts one integer per line, at the current column. Stops early
if it reaches the end of the buffer."
(let ((col (current-column))
(n 0))
(save-excursion
(while (< n max)
(insert (format fmt n))
(forward-line 1)
;; Note that this function does not bother to check for lines
;; shorter than col.
(if (eobp)
(setq n max)
(setq n (1+ n))
(move-to-column col))))))
(defun verilog-insert-indices (max)
"Insert a set of indices into a rectangle.
The upper left corner is defined by point. Indices begin with 0
and extend to the MAX - 1. If no prefix arg is given, the user
is prompted for a value. The indices are surrounded by square
brackets []. For example, the following code with the point
located after the first `a' gives:
a = b a[ 0] = b
a = b a[ 1] = b
a = b a[ 2] = b
a = b a[ 3] = b
a = b ==> insert-indices ==> a[ 4] = b
a = b a[ 5] = b
a = b a[ 6] = b
a = b a[ 7] = b
a = b a[ 8] = b"
(interactive "NMAX: ")
(verilog-insert-1 "[%3d]" max))
(defun verilog-generate-numbers (max)
"Insert a set of generated numbers into a rectangle.
The upper left corner is defined by point. The numbers are padded to three
digits, starting with 000 and extending to (MAX - 1). If no prefix argument
is supplied, then the user is prompted for the MAX number. Consider the
following code fragment:
buf buf buf buf000
buf buf buf buf001
buf buf buf buf002
buf buf buf buf003
buf buf ==> generate-numbers ==> buf buf004
buf buf buf buf005
buf buf buf buf006
buf buf buf buf007
buf buf buf buf008"
(interactive "NMAX: ")
(verilog-insert-1 "%3.3d" max))
(defun verilog-mark-defun ()
"Mark the current Verilog function (or procedure).
This puts the mark at the end, and point at the beginning."
(interactive)
(if (featurep 'xemacs)
(progn
(push-mark (point))
(verilog-end-of-defun)
(push-mark (point))
(verilog-beg-of-defun)
(if (fboundp 'zmacs-activate-region)
(zmacs-activate-region)))
(mark-defun)))
(defun verilog-comment-region (start end)
;; checkdoc-params: (start end)
"Put the region into a Verilog comment.
The comments that are in this area are \"deformed\":
`*)' becomes `!(*' and `}' becomes `!{'.
These deformed comments are returned to normal if you use
\\[verilog-uncomment-region] to undo the commenting.
The commented area starts with `verilog-exclude-str-start', and ends with
`verilog-exclude-str-end'. But if you change these variables,
\\[verilog-uncomment-region] won't recognize the comments."
(interactive "r")
(save-excursion
;; Insert start and endcomments
(goto-char end)
(if (and (save-excursion (skip-chars-forward " \t") (eolp))
(not (save-excursion (skip-chars-backward " \t") (bolp))))
(forward-line 1)
(beginning-of-line))
(insert verilog-exclude-str-end)
(setq end (point))
(newline)
(goto-char start)
(beginning-of-line)
(insert verilog-exclude-str-start)
(newline)
;; Replace end-comments within commented area
(goto-char end)
(save-excursion
(while (re-search-backward "\\*/" start t)
(replace-match "*-/" t t)))
(save-excursion
(let ((s+1 (1+ start)))
(while (re-search-backward "/\\*" s+1 t)
(replace-match "/-*" t t))))))
(defun verilog-uncomment-region ()
"Uncomment a commented area; change deformed comments back to normal.
This command does nothing if the pointer is not in a commented
area. See also `verilog-comment-region'."
(interactive)
(save-excursion
(let ((start (point))
(end (point)))
;; Find the boundaries of the comment
(save-excursion
(setq start (progn (search-backward verilog-exclude-str-start nil t)
(point)))
(setq end (progn (search-forward verilog-exclude-str-end nil t)
(point))))
;; Check if we're really inside a comment
(if (or (equal start (point)) (<= end (point)))
(message "Not standing within commented area.")
(progn
;; Remove endcomment
(goto-char end)
(beginning-of-line)
(let ((pos (point)))
(end-of-line)
(delete-region pos (1+ (point))))
;; Change comments back to normal
(save-excursion
(while (re-search-backward "\\*-/" start t)
(replace-match "*/" t t)))
(save-excursion
(while (re-search-backward "/-\\*" start t)
(replace-match "/*" t t)))
;; Remove start comment
(goto-char start)
(beginning-of-line)
(let ((pos (point)))
(end-of-line)
(delete-region pos (1+ (point)))))))))
(defun verilog-beg-of-defun ()
"Move backward to the beginning of the current function or procedure."
(interactive)
(verilog-re-search-backward verilog-defun-re nil 'move))
(defun verilog-beg-of-defun-quick ()
"Move backward to the beginning of the current function or procedure.
Uses `verilog-scan' cache."
(interactive)
(verilog-re-search-backward-quick verilog-defun-re nil 'move))
(defun verilog-end-of-defun ()
"Move forward to the end of the current function or procedure."
(interactive)
(verilog-re-search-forward verilog-end-defun-re nil 'move))
(defun verilog-get-end-of-defun ()
(save-excursion
(cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
(point))
(t
(error "%s: Can't find endmodule" (verilog-point-text))
(point-max)))))
(defun verilog-label-be ()
"Label matching begin ... end, fork ... join and case ... endcase statements."
(interactive)
(let ((cnt 0)
(case-fold-search nil)
(oldpos (point))
(b (progn
(verilog-beg-of-defun)
(point-marker)))
(e (progn
(verilog-end-of-defun)
(point-marker))))
(goto-char (marker-position b))
(if (> (- e b) 200)
(message "Relabeling module..."))
(while (and
(> (marker-position e) (point))
(verilog-re-search-forward
verilog-auto-end-comment-lines-re
nil 'move))
(goto-char (match-beginning 0))
(let ((indent-str (verilog-indent-line)))
(verilog-set-auto-endcomments indent-str 't)
(end-of-line)
(delete-horizontal-space))
(setq cnt (1+ cnt))
(if (= 9 (% cnt 10))
(message "%d..." cnt)))
(goto-char oldpos)
(if (or
(> (- e b) 200)
(> cnt 20))
(message "%d lines auto commented" cnt))))
(defun verilog-beg-of-statement ()
"Move backward to beginning of statement."
(interactive)
;; Move back token by token until we see the end
;; of some earlier line.
(let (h)
(while
;; If the current point does not begin a new
;; statement, as in the character ahead of us is a ';', or SOF
;; or the string after us unambiguously starts a statement,
;; or the token before us unambiguously ends a statement,
;; then move back a token and test again.
(not (or
;; stop if beginning of buffer
(bobp)
;; stop if looking at a pre-processor directive
(looking-at "`\\w+")
;; stop if we find a ;
(= (preceding-char) ?\;)
;; stop if we see a named coverpoint
(looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
;; keep going if we are in the middle of a word
(not (or (looking-at "\\<") (forward-word-strictly -1)))
;; stop if we see an assertion (perhaps labeled)
(and
(looking-at "\\(\\w+\\W*:\\W*\\)?\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\\\)\\|\\(\\\\)")
(progn
(setq h (point))
(save-excursion
(verilog-backward-token)
(if (and (looking-at verilog-label-re)
(not (looking-at verilog-end-block-re)))
(setq h (point))))
(goto-char h)))
;; stop if we see an extended complete reg, perhaps a complete one
(and
(looking-at verilog-complete-reg)
(let* ((p (point)))
(while (and (looking-at verilog-extended-complete-re)
(progn (setq p (point))
(verilog-backward-token)
(/= p (point)))))
(goto-char p)))
;; stop if we see a complete reg (previous found extended ones)
(looking-at verilog-basic-complete-re)
;; stop if previous token is an ender
(save-excursion
(verilog-backward-token)
(looking-at verilog-end-block-re))))
(verilog-backward-syntactic-ws)
(verilog-backward-token))
;; Now point is where the previous line ended.
(verilog-forward-syntactic-ws)
;; Skip forward over any preprocessor directives, as they have wacky indentation
(if (looking-at verilog-preprocessor-re)
(progn (goto-char (match-end 0))
(verilog-forward-syntactic-ws)))))
(defun verilog-beg-of-statement-1 ()
"Move backward to beginning of statement."
(interactive)
(if (verilog-in-comment-p)
(verilog-backward-syntactic-ws))
(let ((pt (point)))
(catch 'done
(while (not (looking-at verilog-complete-reg))
(setq pt (point))
(verilog-backward-syntactic-ws)
(if (or (bolp)
(= (preceding-char) ?\;)
(progn
(verilog-backward-token)
(looking-at verilog-ends-re)))
(progn
(goto-char pt)
(throw 'done t)))))
(verilog-forward-syntactic-ws)))
;;
;; (while (and
;; (not (looking-at verilog-complete-reg))
;; (not (bolp))
;; (not (= (preceding-char) ?\;)))
;; (verilog-backward-token)
;; (verilog-backward-syntactic-ws)
;; (setq pt (point)))
;; (goto-char pt)
;; ;(verilog-forward-syntactic-ws)
(defun verilog-end-of-statement ()
"Move forward to end of current statement."
(interactive)
(let ((nest 0) pos)
(cond
((verilog-in-directive-p)
(forward-line 1)
(backward-char 1))
((looking-at verilog-beg-block-re)
(verilog-forward-sexp))
((equal (char-after) ?\})
(forward-char))
;; Skip to end of statement
((condition-case nil
(setq pos
(catch 'found
(while t
(forward-sexp 1)
(verilog-skip-forward-comment-or-string)
(if (eolp)
(forward-line 1))
(cond ((looking-at "[ \t]*;")
(skip-chars-forward "^;")
(forward-char 1)
(throw 'found (point)))
((save-excursion
(forward-sexp -1)
(looking-at verilog-beg-block-re))
(goto-char (match-beginning 0))
(throw 'found nil))
((looking-at "[ \t]*)")
(throw 'found (point)))
((eobp)
(throw 'found (point)))
)))
)
(error nil))
(if (not pos)
;; Skip a whole block
(catch 'found
(while t
(verilog-re-search-forward verilog-end-statement-re nil 'move)
(setq nest (if (match-end 1)
(1+ nest)
(1- nest)))
(cond ((eobp)
(throw 'found (point)))
((= 0 nest)
(throw 'found (verilog-end-of-statement))))))
pos)))))
(defun verilog-in-case-region-p ()
"Return true if in a case region.
More specifically, point @ in the line foo : @ begin"
(interactive)
(save-excursion
(if (and
(progn (verilog-forward-syntactic-ws)
(looking-at "\\"))
(progn (verilog-backward-syntactic-ws)
(= (preceding-char) ?\:)))
(catch 'found
(let ((nest 1))
(while t
(verilog-re-search-backward
(concat "\\(\\\\)\\|\\(\\\\|\\[^:]\\)\\|"
"\\(\\\\)\\>")
nil 'move)
(cond
((match-end 3)
(setq nest (1+ nest)))
((match-end 2)
(if (= nest 1)
(throw 'found 1))
(setq nest (1- nest)))
(t
(throw 'found (= nest 0)))))))
nil)))
(defun verilog-backward-up-list (arg)
"Call `backward-up-list' ARG, ignoring comments."
(let ((parse-sexp-ignore-comments t))
(backward-up-list arg)))
(defun verilog-forward-sexp-cmt (arg)
"Call `forward-sexp' ARG, inside comments."
(let ((parse-sexp-ignore-comments nil))
(forward-sexp arg)))
(defun verilog-forward-sexp-ign-cmt (arg)
"Call `forward-sexp' ARG, ignoring comments."
(let ((parse-sexp-ignore-comments t))
(forward-sexp arg)))
(defun verilog-in-generate-region-p ()
"Return true if in a generate region.
More specifically, after a generate and before an endgenerate."
(interactive)
(let ((nest 1))
(save-excursion
(catch 'done
(while (and
(/= nest 0)
(verilog-re-search-backward
"\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
(cond
((match-end 1) ; module - we have crawled out
(throw 'done 1))
((match-end 2) ; generate
(setq nest (1- nest)))
((match-end 3) ; endgenerate
(setq nest (1+ nest))))))))
(= nest 0) )) ; return nest
(defun verilog-in-fork-region-p ()
"Return true if between a fork and join."
(interactive)
(let ((lim (save-excursion (verilog-beg-of-defun) (point)))
(nest 1))
(save-excursion
(while (and
(/= nest 0)
(verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
(cond
((match-end 1) ; fork
(setq nest (1- nest)))
((match-end 2) ; join
(setq nest (1+ nest)))))))
(= nest 0) )) ; return nest
(defun verilog-in-deferred-immediate-final-p ()
"Return true if inside an `assert/assume/cover final' statement."
(interactive)
(and (looking-at "final")
(verilog-looking-back "\\<\\(?:assert\\|assume\\|cover\\)\\>\\s-+" nil))
)
(defun verilog-backward-case-item (lim)
"Skip backward to nearest enclosing case item.
Limit search to point LIM."
(interactive)
(let ((str 'nil)
(lim1
(progn
(save-excursion
(verilog-re-search-backward verilog-endcomment-reason-re
lim 'move)
(point)))))
;; Try to find the real :
(if (save-excursion (search-backward ":" lim1 t))
(let ((colon 0)
b e )
(while
(and
(< colon 1)
(verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
lim1 'move))
(cond
((match-end 1) ; [
(setq colon (1+ colon))
(if (>= colon 0)
(error "%s: unbalanced [" (verilog-point-text))))
((match-end 2) ; ]
(setq colon (1- colon)))
((match-end 3) ; :
(setq colon (1+ colon)))))
;; Skip back to beginning of case item
(skip-chars-backward "\t ")
(verilog-skip-backward-comment-or-string)
(setq e (point))
(setq b
(progn
(if
(verilog-re-search-backward
"\\<\\(randcase\\|case[zx]?\\)\\>\\|;\\|\\" nil 'move)
(progn
(cond
((match-end 1)
(goto-char (match-end 1))
(verilog-forward-ws&directives)
(if (looking-at "(")
(progn
(forward-sexp)
(verilog-forward-ws&directives)))
(point))
(t
(goto-char (match-end 0))
(verilog-forward-ws&directives)
(point))))
(error "Malformed case item"))))
(setq str (buffer-substring b e))
(if
(setq e
(string-match
"[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
(setq str (concat (substring str 0 e) "...")))
str)
'nil)))
;;; Other functions:
;;
(defun verilog-kill-existing-comment ()
"Kill auto comment on this line."
(save-excursion
(let* (
(e (progn
(end-of-line)
(point)))
(b (progn
(beginning-of-line)
(search-forward "//" e t))))
(if b
(delete-region (- b 2) e)))))
(defconst verilog-directive-nest-re
(concat "\\(`else\\>\\)\\|"
"\\(`endif\\>\\)\\|"
"\\(`if\\>\\)\\|"
"\\(`ifdef\\>\\)\\|"
"\\(`ifndef\\>\\)\\|"
"\\(`elsif\\>\\)"))
(defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
"Add ending comment with given INDENT-STR.
With KILL-EXISTING-COMMENT, remove what was there before.
Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
Insert `// case expr ' if this line ends a case block.
Insert `// ifdef FOO ' if this line ends code conditional on FOO.
Insert `// NAME ' if this line ends a function, task, module,
primitive or interface named NAME."
(save-excursion
(cond
(; Comment close preprocessor directives
(and
(looking-at "\\(`endif\\)\\|\\(`else\\)")
(or kill-existing-comment
(not (save-excursion
(end-of-line)
(search-backward "//" (point-at-bol) t)))))
(let ((nest 1) b e
m
(else (if (match-end 2) "!" " ")))
(end-of-line)
(if kill-existing-comment
(verilog-kill-existing-comment))
(delete-horizontal-space)
(save-excursion
(backward-sexp 1)
(while (and (/= nest 0)
(verilog-re-search-backward verilog-directive-nest-re nil 'move))
(cond
((match-end 1) ; `else
(if (= nest 1)
(setq else "!")))
((match-end 2) ; `endif
(setq nest (1+ nest)))
((match-end 3) ; `if
(setq nest (1- nest)))
((match-end 4) ; `ifdef
(setq nest (1- nest)))
((match-end 5) ; `ifndef
(setq nest (1- nest)))
((match-end 6) ; `elsif
(if (= nest 1)
(progn
(setq else "!")
(setq nest 0))))))
(if (match-end 0)
(setq
m (buffer-substring
(match-beginning 0)
(match-end 0))
b (progn
(skip-chars-forward "^ \t")
(verilog-forward-syntactic-ws)
(point))
e (progn
(skip-chars-forward "a-zA-Z0-9_")
(point)))))
(if b
(if (> (count-lines (point) b) verilog-minimum-comment-distance)
(insert (concat " // " else m " " (buffer-substring b e))))
(progn
(insert " // unmatched `else, `elsif or `endif")
(ding 't)))))
(; Comment close case/class/function/task/module and named block
(and (looking-at "\\")
(setq str "randcase")
(setq err nil))
((looking-at "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
(goto-char (match-end 0))
(setq str (concat (match-string 0) " " (verilog-get-expr)))
(setq err nil))
))
(end-of-line)
(if kill-existing-comment
(verilog-kill-existing-comment))
(delete-horizontal-space)
(insert (concat " // " str ))
(if err (ding 't))))
(;- This is a begin..end block
(match-end 2) ; of verilog-end-block-ordered-re
(let ((str " // UNMATCHED !!")
(err 't)
(here (point))
there
cntx)
(save-excursion
(verilog-leap-to-head)
(setq there (point))
(if (not (match-end 0))
(progn
(goto-char here)
(end-of-line)
(if kill-existing-comment
(verilog-kill-existing-comment))
(delete-horizontal-space)
(insert str)
(ding 't))
(let ((lim
(save-excursion (verilog-beg-of-defun) (point)))
(here (point)))
(cond
(;-- handle named block differently
(looking-at verilog-named-block-re)
(search-forward ":")
(setq there (point))
(setq str (verilog-get-expr))
(setq err nil)
(setq str (concat " // block: " str )))
((verilog-in-case-region-p) ;-- handle case item differently
(goto-char here)
(setq str (verilog-backward-case-item lim))
(setq there (point))
(setq err nil)
(setq str (concat " // case: " str )))
(;- try to find "reason" for this begin
(cond
(;
(eq here (progn
;; (verilog-backward-token)
(verilog-beg-of-statement)
(point)))
(setq err nil)
(setq str ""))
((looking-at verilog-endcomment-reason-re)
(setq there (match-end 0))
(setq cntx (concat (match-string 0) " "))
(cond
(;- begin
(match-end 1)
(setq err nil)
(save-excursion
(if (and (verilog-continued-line)
(looking-at "\\\\|\\\\|\\"))
(progn
(goto-char (match-end 0))
(setq there (point))
(setq str
(concat " // " (match-string 0) " " (verilog-get-expr))))
(setq str ""))))
(;- else
(match-end 2)
(let ((nest 0)
( reg "\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(assert\\)"))
(catch 'skip
(while (verilog-re-search-backward reg nil 'move)
(cond
((match-end 1) ; begin
(setq nest (1- nest)))
((match-end 2) ; end
(setq nest (1+ nest)))
((match-end 3)
(if (= 0 nest)
(progn
(goto-char (match-end 0))
(setq there (point))
(setq err nil)
(setq str (verilog-get-expr))
(setq str (concat " // else: !if" str ))
(throw 'skip 1))))
((match-end 4)
(if (= 0 nest)
(progn
(goto-char (match-end 0))
(setq there (point))
(setq err nil)
(setq str (verilog-get-expr))
(setq str (concat " // else: !assert " str ))
(throw 'skip 1)))))))))
(;- end else
(match-end 3)
(goto-char there)
(let ((nest 0)
(reg "\\(\\\\)\\|\\(\\\\)\\|\\(\\\\)\\|\\(assert\\)"))
(catch 'skip
(while (verilog-re-search-backward reg nil 'move)
(cond
((match-end 1) ; begin
(setq nest (1- nest)))
((match-end 2) ; end
(setq nest (1+ nest)))
((match-end 3)
(if (= 0 nest)
(progn
(goto-char (match-end 0))
(setq there (point))
(setq err nil)
(setq str (verilog-get-expr))
(setq str (concat " // else: !if" str ))
(throw 'skip 1))))
((match-end 4)
(if (= 0 nest)
(progn
(goto-char (match-end 0))
(setq there (point))
(setq err nil)
(setq str (verilog-get-expr))
(setq str (concat " // else: !assert " str ))
(throw 'skip 1)))))))))
(; always, always_comb, always_latch w/o @...
(match-end 5)
(goto-char (match-end 0))
(setq there (point))
(setq err nil)
(setq str (concat " // " cntx )))
(;- task/function/initial et cetera
t
(match-end 0)
(goto-char (match-end 0))
(setq there (point))
(setq err nil)
(setq str (concat " // " cntx (verilog-get-expr))))
(;-- otherwise...
(setq str " // auto-endcomment confused "))))
((and
(verilog-in-case-region-p) ;-- handle case item differently
(progn
(setq there (point))
(goto-char here)
(setq str (verilog-backward-case-item lim))))
(setq err nil)
(setq str (concat " // case: " str )))
((verilog-in-fork-region-p)
(setq err nil)
(setq str " // fork branch" ))
((looking-at "\\")
;; HERE
(forward-word-strictly 1)
(verilog-forward-syntactic-ws)
(setq err nil)
(setq str (verilog-get-expr))
(setq str (concat " // " cntx str )))
))))
(goto-char here)
(end-of-line)
(if kill-existing-comment
(verilog-kill-existing-comment))
(delete-horizontal-space)
(if (or err
(> (count-lines here there) verilog-minimum-comment-distance))
(insert str))
(if err (ding 't))
))))
(;- this is endclass, which can be nested
(match-end 11) ; of verilog-end-block-ordered-re
;;(goto-char there)
(let ((nest 0)
(reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
string)
(save-excursion
(catch 'skip
(while (verilog-re-search-backward reg nil 'move)
(cond
((match-end 3) ; endclass
(ding 't)
(setq string "unmatched endclass")
(throw 'skip 1))
((match-end 2) ; endclass
(setq nest (1+ nest)))
((match-end 1) ; class
(setq nest (1- nest))
(if (< nest 0)
(progn
(goto-char (match-end 0))
(let (b e)
(setq b (progn
(skip-chars-forward "^ \t")
(verilog-forward-ws&directives)
(point))
e (progn
(skip-chars-forward "a-zA-Z0-9_")
(point)))
(setq string (buffer-substring b e)))
(throw 'skip 1))))
))))
(end-of-line)
(if kill-existing-comment
(verilog-kill-existing-comment))
(delete-horizontal-space)
(insert (concat " // " string ))))
(; - this is end{function,generate,task,module,primitive,table,generate}
;; - which can not be nested.
t
(let (string reg (name-re nil))
(end-of-line)
(if kill-existing-comment
(save-match-data
(verilog-kill-existing-comment)))
(delete-horizontal-space)
(backward-sexp)
(cond
((match-end 5) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
(setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
((match-end 6) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
(setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
((match-end 7) ; of verilog-end-block-ordered-re
(setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\"))
((match-end 8) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
((match-end 9) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
((match-end 10) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
((match-end 11) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
((match-end 12) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
((match-end 13) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
((match-end 14) ; of verilog-end-block-ordered-re
(setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
((match-end 15) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\"))
((match-end 16) ; of verilog-end-block-ordered-re
(setq reg "\\(\\\\)\\|\\"))
(t (error "Problem in verilog-set-auto-endcomments")))
(let (b e)
(save-excursion
(verilog-re-search-backward reg nil 'move)
(cond
((match-end 1)
(setq b (progn
(skip-chars-forward "^ \t")
(verilog-forward-ws&directives)
(if (looking-at "static\\|automatic")
(progn
(goto-char (match-end 0))
(verilog-forward-ws&directives)))
(if (and name-re (verilog-re-search-forward name-re nil 'move))
(progn
(goto-char (match-beginning 0))
(verilog-forward-ws&directives)))
(point))
e (progn
(skip-chars-forward "a-zA-Z0-9_")
(point)))
(setq string (buffer-substring b e)))
(t
(ding 't)
(setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
(end-of-line)
(insert (concat " // " string )))
))))))))))
(defun verilog-get-expr()
"Grab expression at point, e.g., case ( a | b & (c ^d))."
(let* ((b (progn
(verilog-forward-syntactic-ws)
(skip-chars-forward " \t")
(point)))
(e (let ((par 1))
(cond
((looking-at "@")
(forward-char 1)
(verilog-forward-syntactic-ws)
(if (looking-at "(")
(progn
(forward-char 1)
(while (and (/= par 0)
(verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
(cond
((match-end 1)
(setq par (1+ par)))
((match-end 2)
(setq par (1- par)))))))
(point))
((looking-at "(")
(forward-char 1)
(while (and (/= par 0)
(verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
(cond
((match-end 1)
(setq par (1+ par)))
((match-end 2)
(setq par (1- par)))))
(point))
((looking-at "\\[")
(forward-char 1)
(while (and (/= par 0)
(verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
(cond
((match-end 1)
(setq par (1+ par)))
((match-end 2)
(setq par (1- par)))))
(verilog-forward-syntactic-ws)
(skip-chars-forward "^ \t\n\f")
(point))
((looking-at "/[/\\*]")
b)
('t
(skip-chars-forward "^: \t\n\f")
(point)))))
(str (buffer-substring b e)))
(if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
(setq str (concat (substring str 0 e) "...")))
str))
(defun verilog-expand-vector ()
"Take a signal vector on the current line and expand it to multiple lines.
Useful for creating tri's and other expanded fields."
(interactive)
(verilog-expand-vector-internal "[" "]"))
(defun verilog-expand-vector-internal (bra ket)
"Given BRA, the start brace and KET, the end brace, expand one line into many lines."
(save-excursion
(forward-line 0)
(let ((signal-string (buffer-substring (point)
(progn
(end-of-line) (point)))))
(if (string-match
(concat "\\(.*\\)"
(regexp-quote bra)
"\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
(regexp-quote ket)
"\\(.*\\)$") signal-string)
(let* ((sig-head (match-string 1 signal-string))
(vec-start (string-to-number (match-string 2 signal-string)))
(vec-end (if (= (match-beginning 3) (match-end 3))
vec-start
(string-to-number
(substring signal-string (1+ (match-beginning 3))
(match-end 3)))))
(vec-range
(if (= (match-beginning 4) (match-end 4))
1
(string-to-number
(substring signal-string (+ 2 (match-beginning 4))
(match-end 4)))))
(sig-tail (match-string 5 signal-string))
vec)
;; Decode vectors
(setq vec nil)
(if (< vec-range 0)
(let ((tmp vec-start))
(setq vec-start vec-end
vec-end tmp
vec-range (- vec-range))))
(if (< vec-end vec-start)
(while (<= vec-end vec-start)
(setq vec (append vec (list vec-start)))
(setq vec-start (- vec-start vec-range)))
(while (<= vec-start vec-end)
(setq vec (append vec (list vec-start)))
(setq vec-start (+ vec-start vec-range))))
;;
;; Delete current line
(delete-region (point) (progn (forward-line 0) (point)))
;;
;; Expand vector
(while vec
(insert (concat sig-head bra
(int-to-string (car vec)) ket sig-tail "\n"))
(setq vec (cdr vec)))
(delete-char -1)
;;
)))))
(defun verilog-strip-comments ()
"Strip all comments from the Verilog code."
(interactive)
(goto-char (point-min))
(while (re-search-forward "//" nil t)
(if (verilog-within-string)
(re-search-forward "\"" nil t)
(if (verilog-in-star-comment-p)
(re-search-forward "\\*/" nil t)
(let ((bpt (- (point) 2)))
(end-of-line)
(delete-region bpt (point))))))
;;
(goto-char (point-min))
(while (re-search-forward "/\\*" nil t)
(if (verilog-within-string)
(re-search-forward "\"" nil t)
(let ((bpt (- (point) 2)))
(re-search-forward "\\*/")
(delete-region bpt (point))))))
(defun verilog-one-line ()
"Convert structural Verilog instances to occupy one line."
(interactive)
(goto-char (point-min))
(while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
(replace-match "\\1 " nil nil)))
(defun verilog-linter-name ()
"Return name of linter, either surelint or verilint."
(let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
compile-command))
(lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
verilog-linter)))
(cond ((equal compile-word1 "surelint") `surelint)
((equal compile-word1 "verilint") `verilint)
((equal lint-word1 "surelint") `surelint)
((equal lint-word1 "verilint") `verilint)
(t `surelint)))) ; back compatibility
(defun verilog-lint-off ()
"Convert a Verilog linter warning line into a disable statement.
For example:
pci_bfm_null.v, line 46: Unused input: pci_rst_
becomes a comment for the appropriate tool.
The first word of the `compile-command' or `verilog-linter'
variables is used to determine which product is being used.
See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
(interactive)
(let ((linter (verilog-linter-name)))
(cond ((equal linter `surelint)
(verilog-surelint-off))
((equal linter `verilint)
(verilog-verilint-off))
(t (error "Linter name not set")))))
(defvar compilation-last-buffer)
(defvar next-error-last-buffer)
(defun verilog-surelint-off ()
"Convert a SureLint warning line into a disable statement.
Run from Verilog source window; assumes there is a *compile* buffer
with point set appropriately.
For example:
WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
becomes:
// surefire lint_line_off UDDONX"
(interactive)
(let ((buff (if (boundp 'next-error-last-buffer)
next-error-last-buffer
compilation-last-buffer)))
(when (buffer-live-p buff)
(save-excursion
(switch-to-buffer buff)
(beginning-of-line)
(when
(looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
(let* ((code (match-string 2))
(file (match-string 3))
(line (match-string 4))
(buffer (get-file-buffer file))
dir filename)
(unless buffer
(progn
(setq buffer
(and (file-exists-p file)
(find-file-noselect file)))
(or buffer
(let* ((pop-up-windows t))
(let ((name (expand-file-name
(read-file-name
(format "Find this error in: (default %s) "
file)
dir file t))))
(if (file-directory-p name)
(setq name (expand-file-name filename name)))
(setq buffer
(and (file-exists-p name)
(find-file-noselect name))))))))
(switch-to-buffer buffer)
(goto-char (point-min))
(forward-line (- (string-to-number line)))
(end-of-line)
(catch 'already
(cond
((verilog-in-slash-comment-p)
(re-search-backward "//")
(cond
((looking-at "// surefire lint_off_line ")
(goto-char (match-end 0))
(let ((lim (point-at-eol)))
(if (re-search-forward code lim 'move)
(throw 'already t)
(insert (concat " " code)))))
(t
)))
((verilog-in-star-comment-p)
(re-search-backward "/\\*")
(insert (format " // surefire lint_off_line %6s" code )))
(t
(insert (format " // surefire lint_off_line %6s" code ))
)))))))))
(defun verilog-verilint-off ()
"Convert a Verilint warning line into a disable statement.
For example:
(W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
becomes:
//Verilint 240 off // WARNING: Unused input"
(interactive)
(save-excursion
(beginning-of-line)
(when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
(replace-match (format
;; %3s makes numbers 1-999 line up nicely
"\\1//Verilint %3s off // WARNING: \\3"
(match-string 2)))
(beginning-of-line)
(verilog-indent-line))))
(defun verilog-auto-save-compile ()
"Update automatics with \\[verilog-auto], save the buffer, and compile."
(interactive)
(verilog-auto) ; Always do it for safety
(save-buffer)
(compile compile-command))
(defun verilog-preprocess (&optional command filename)
"Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
Takes optional COMMAND or defaults to `verilog-preprocessor', and
FILENAME to find directory to run in, or defaults to `buffer-file-name'."
(interactive
(list
(let ((default (verilog-expand-command verilog-preprocessor)))
(set (make-local-variable `verilog-preprocessor)
(read-from-minibuffer "Run Preprocessor (like this): "
default nil nil
'verilog-preprocess-history default)))))
(unless command (setq command (verilog-expand-command verilog-preprocessor)))
(let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
(dir (file-name-directory (or filename buffer-file-name)))
(cmd (concat "cd " dir "; " command)))
(with-output-to-temp-buffer "*Verilog-Preprocessed*"
(with-current-buffer (get-buffer "*Verilog-Preprocessed*")
(insert (concat "// " cmd "\n"))
(call-process shell-file-name nil t nil shell-command-switch cmd)
(verilog-mode)
;; Without this force, it takes a few idle seconds
;; to get the color, which is very jarring
(unless (fboundp 'font-lock-ensure)
;; We should use font-lock-ensure in preference to
;; font-lock-fontify-buffer, but IIUC the problem this is supposed to
;; solve only appears in Emacsen older than font-lock-ensure anyway.
;; So avoid bytecomp's interactive-only by going through intern.
(when fontlocked (funcall (intern "font-lock-fontify-buffer"))))))))
;;; Batch:
;;
(defun verilog-warn (string &rest args)
"Print a warning with `format' using STRING and optional ARGS."
(apply 'message (concat "%%Warning: " string) args))
(defun verilog-warn-error (string &rest args)
"Call `error' using STRING and optional ARGS.
If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
(if verilog-warn-fatal
(apply 'error string args)
(apply 'verilog-warn string args)))
(defmacro verilog-batch-error-wrapper (&rest body)
"Execute BODY and add error prefix to any errors found.
This lets programs calling batch mode to easily extract error messages."
`(let ((verilog-warn-fatal nil))
(condition-case err
(progn ,@body)
(error
(error "%%Error: %s%s" (error-message-string err)
(if (featurep 'xemacs) "\n" "")))))) ; XEmacs forgets to add a newline
(defun verilog-batch-execute-func (funref &optional no-save)
"Internal processing of a batch command.
Runs FUNREF on all command arguments.
Save the result unless optional NO-SAVE is t."
(verilog-batch-error-wrapper
;; Setting global variables like that is *VERY NASTY* !!! --Stef
;; However, this function is called only when Emacs is being used as
;; a standalone language instead of as an editor, so we'll live.
;;
;; General globals needed
(setq make-backup-files nil)
(setq-default make-backup-files nil)
(setq enable-local-variables t)
(setq enable-local-eval t)
(setq create-lockfiles nil)
;; Make sure any sub-files we read get proper mode
(setq-default major-mode 'verilog-mode)
;; Ditto files already read in
;; Remember buffer list, so don't later pickup any verilog-getopt files
(let ((orig-buffer-list (buffer-list)))
(mapc (lambda (buf)
(when (buffer-file-name buf)
(with-current-buffer buf
(verilog-mode)
(verilog-auto-reeval-locals)
(verilog-getopt-flags))))
orig-buffer-list)
;; Process the files
(mapcar (lambda (buf)
(when (buffer-file-name buf)
(save-excursion
(if (not (file-exists-p (buffer-file-name buf)))
(error
"File not found: %s" (buffer-file-name buf)))
(message "Processing %s" (buffer-file-name buf))
(set-buffer buf)
(funcall funref)
(when (and (not no-save)
(buffer-modified-p)) ; Avoid "no changes to be saved"
(save-buffer)))))
orig-buffer-list))))
(defun verilog-batch-auto ()
"For use with --batch, perform automatic expansions as a stand-alone tool.
This sets up the appropriate Verilog mode environment, updates automatics
with \\[verilog-auto] on all command-line files, and saves the buffers.
For proper results, multiple filenames need to be passed on the command
line in bottom-up order."
(unless noninteractive
(error "Use verilog-batch-auto only with --batch")) ; Otherwise we'd mess up buffer modes
(verilog-batch-execute-func `verilog-auto))
(defun verilog-batch-delete-auto ()
"For use with --batch, perform automatic deletion as a stand-alone tool.
This sets up the appropriate Verilog mode environment, deletes automatics
with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
(unless noninteractive
(error "Use verilog-batch-delete-auto only with --batch")) ; Otherwise we'd mess up buffer modes
(verilog-batch-execute-func `verilog-delete-auto))
(defun verilog-batch-delete-trailing-whitespace ()
"For use with --batch, perform whitespace deletion as a stand-alone tool.
This sets up the appropriate Verilog mode environment, removes
whitespace with \\[verilog-delete-trailing-whitespace] on all
command-line files, and saves the buffers."
(unless noninteractive
(error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ; Otherwise we'd mess up buffer modes
(verilog-batch-execute-func `verilog-delete-trailing-whitespace))
(defun verilog-batch-diff-auto ()
"For use with --batch, perform automatic differences as a stand-alone tool.
This sets up the appropriate Verilog mode environment, expand automatics
with \\[verilog-diff-auto] on all command-line files, and reports an error
if any differences are observed. This is appropriate for adding to regressions
to insure automatics are always properly maintained."
(unless noninteractive
(error "Use verilog-batch-diff-auto only with --batch")) ; Otherwise we'd mess up buffer modes
(verilog-batch-execute-func `verilog-diff-auto t))
(defun verilog-batch-inject-auto ()
"For use with --batch, perform automatic injection as a stand-alone tool.
This sets up the appropriate Verilog mode environment, injects new automatics
with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
For proper results, multiple filenames need to be passed on the command
line in bottom-up order."
(unless noninteractive
(error "Use verilog-batch-inject-auto only with --batch")) ; Otherwise we'd mess up buffer modes
(verilog-batch-execute-func `verilog-inject-auto))
(defun verilog-batch-indent ()
"For use with --batch, reindent an entire file as a stand-alone tool.
This sets up the appropriate Verilog mode environment, calls
\\[verilog-indent-buffer] on all command-line files, and saves the buffers."
(unless noninteractive
(error "Use verilog-batch-indent only with --batch")) ; Otherwise we'd mess up buffer modes
(verilog-batch-execute-func `verilog-indent-buffer))
;;; Indentation:
;;
(defconst verilog-indent-alist
'((block . (+ ind verilog-indent-level))
(case . (+ ind verilog-case-indent))
(cparenexp . (+ ind verilog-indent-level))
(cexp . (+ ind verilog-cexp-indent))
(defun . verilog-indent-level-module)
(declaration . verilog-indent-level-declaration)
(directive . (verilog-calculate-indent-directive))
(tf . verilog-indent-level)
(behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
(statement . ind)
(cpp . 0)
(comment . (verilog-comment-indent))
(unknown . 3)
(string . 0)))
(defun verilog-continued-line-1 (lim)
"Return true if this is a continued line.
Set point to where line starts. Limit search to point LIM."
(let ((continued 't))
(if (eq 0 (forward-line -1))
(progn
(end-of-line)
(verilog-backward-ws&directives lim)
(if (bobp)
(setq continued nil)
(setq continued (verilog-backward-token))))
(setq continued nil))
continued))
(defun verilog-calculate-indent ()
"Calculate the indent of the current Verilog line.
Examine previous lines. Once a line is found that is definitive as to the
type of the current line, return that lines' indent level and its type.
Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
(save-excursion
(let* ((starting_position (point))
(case-fold-search nil)
(par 0)
(begin (looking-at "[ \t]*begin\\>"))
(lim (save-excursion (verilog-re-search-backward "\\(\\\\)\\|\\(\\\\)" nil t)))
(structres nil)
(type (catch 'nesting
;; Keep working backwards until we can figure out
;; what type of statement this is.
;; Basically we need to figure out
;; 1) if this is a continuation of the previous line;
;; 2) are we in a block scope (begin..end)
;; if we are in a comment, done.
(if (verilog-in-star-comment-p)
(throw 'nesting 'comment))
;; if we have a directive, done.
(if (save-excursion (beginning-of-line)
(and (looking-at verilog-directive-re-1)
(not (or (looking-at "[ \t]*`[ou]vm_")
(looking-at "[ \t]*`vmm_")))))
(throw 'nesting 'directive))
;; indent structs as if there were module level
(setq structres (verilog-in-struct-nested-p))
(cond ((not structres) nil)
;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
((> structres 0) (throw 'nesting 'nested-struct))
((= structres 0) (throw 'nesting 'block))
(t nil))
;; if we are in a parenthesized list, and the user likes to indent these, return.
;; unless we are in the newfangled coverpoint or constraint blocks
(if (and
verilog-indent-lists
(verilog-in-paren)
(not (verilog-in-coverage-p))
)
(progn (setq par 1)
(throw 'nesting 'block)))
;; See if we are continuing a previous line
(while t
;; trap out if we crawl off the top of the buffer
(if (bobp) (throw 'nesting 'cpp))
(if (and (verilog-continued-line-1 lim)
(or (not (verilog-in-coverage-p))
(looking-at verilog-in-constraint-re) )) ; may still get hosed if concat in constraint
(let ((sp (point)))
(if (and
(not (looking-at verilog-complete-reg))
(verilog-continued-line-1 lim))
(progn (goto-char sp)
(throw 'nesting 'cexp))
(goto-char sp))
(if (and (verilog-in-coverage-p)
(looking-at verilog-in-constraint-re))
(progn
(beginning-of-line)
(skip-chars-forward " \t")
(throw 'nesting 'constraint)))
(if (and begin
(not verilog-indent-begin-after-if)
(looking-at verilog-no-indent-begin-re))
(progn
(beginning-of-line)
(skip-chars-forward " \t")
(throw 'nesting 'statement))
(progn
(throw 'nesting 'cexp))))
;; not a continued line
(goto-char starting_position))
(if (looking-at "\\")
;; search back for governing if, striding across begin..end pairs
;; appropriately
(let ((elsec 1))
(while (verilog-re-search-backward verilog-ends-re nil 'move)
(cond
((match-end 1) ; else, we're in deep
(setq elsec (1+ elsec)))
((match-end 2) ; if
(setq elsec (1- elsec))
(if (= 0 elsec)
(if verilog-align-ifelse
(throw 'nesting 'statement)
(progn ; back up to first word on this line
(beginning-of-line)
(verilog-forward-syntactic-ws)
(throw 'nesting 'statement)))))
((match-end 3) ; assert block
(setq elsec (1- elsec))
(verilog-beg-of-statement) ; doesn't get to beginning
(if (looking-at verilog-property-re)
(throw 'nesting 'statement) ; We don't need an endproperty for these
(throw 'nesting 'block) ; We still need an endproperty
))
(t ; endblock
;; try to leap back to matching outward block by striding across
;; indent level changing tokens then immediately
;; previous line governs indentation.
(let (( reg) (nest 1))
;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
(cond
((match-end 4) ; end
;; Search back for matching begin
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 5) ; endcase
;; Search back for matching case
(setq reg "\\(\\\\|\\[^:]\\)\\|\\(\\\\)" ))
((match-end 6) ; endfunction
;; Search back for matching function
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 7) ; endtask
;; Search back for matching task
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 8) ; endspecify
;; Search back for matching specify
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 9) ; endtable
;; Search back for matching table
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 10) ; endgenerate
;; Search back for matching generate
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 11) ; joins
;; Search back for matching fork
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 12) ; class
;; Search back for matching class
(setq reg "\\(\\\\)\\|\\(\\\\)" ))
((match-end 13) ; covergroup
;; Search back for matching covergroup
(setq reg "\\(\\\\)\\|\\(\\