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T 595 95 8 10 0 0 0 0 1 footprint=TO92 T 595 95 8 10 0 0 0 0 1 description=N-Channel JFET VeroRoute/tutorials/tutorial_11.vrt000644 001750 001750 00000073551 14066376766 017723 0ustar00alexalex000000 000000 2-”TUTORIAL 11 - MAKING CONNECTIONS As seen in the previous tutorials, connections are automatically made between adjacent grid points that have the same NodeID. So to manually build a track, NodeIDs need to be "painted" to grid points and component pins. We will run through an example, but first of all here is an overview. To paint things (i.e. assign NodeIDs) you must hold down a particular keyboard key while clicking the mouse. The key used depends on whether you want to paint a component pin or a regular grid point. PAINTING COMPONENT PINS Component pins are special and must be protected from being edited by accident. Therefore in order to paint or erase a pin you must hold down the "P" key for "pin" while you click the mouse on the pin to modify it. You can actually paint regular (i.e. non-pin) grid points while holding down "P" too, but have to repeatedly click to paint. Note that it is not possible to paint a component pin if the component is floating. It must be placed on the grid first. PAINTING THE GRID Regular grid points can be painted by holding down the SPACE bar and clicking with the mouse. Using the SPACE bar avoids the need for repeated mouse-clicks and you can paint (or erase) multiple points by moving the mouse while holding down a mouse button. Component pins are protected and left unmodified when painting with the SPACE bar. ERASING When either the "P" key or the SPACE bar is being held down, use the left mouse button to paint, and use the right mouse button to erase. SELECTING THE NODEID FOR PAINTING To paint using an existing NodeID, you must first make it the "selected NodeID" by left-clicking on it in the view (or in the "Broken" list) just as you would when viewing connectivity. It will be highlighted in dark grey in the view. To paint with a brand new NodeID, you must first right-click the mouse (without holding down any keys) to clear the "selected NodeID" so that nothing in the view is shown in dark grey. This will cause a brand new NodeID to be used for painting. EXAMPLE Now let's paint the circuit in the top part of the view... Start by right clicking in the view so that nothing is shown in dark grey. This means the first thing we paint will have a brand new NodeID. Hold down "P" and left-click on the top pin of R1. It will be painted in dark grey with the new NodeID. We want to connect the tops of R1, R2 and R3. So making sure that the top pin of R1 is still shown in dark grey, hold down "P" and click on the top pins of R2 and R3. You will see that the NodeID is "Broken" because the three painted pins are not electrically connected. You can fix that my moving the parts so that the pins are adjacent, but let's paint a track instead. Hold down the SPACE bar and paint in the grid points between the 3 pins to join them electrically and fix the "Broken" NodeID. Now drag R1 a few steps to the left with the mouse. Upon releasing the mouse, connectivity is re-evaluated and you will see that the NodeID is "Broken" again. This is because parts (except for wires) take their NodeIDs with them as they are moved. So the act of painting a pin does not paint the underlying grid. Now move R1 back. Next we will connect the bottom of R2 to the top of Q1. We want to use a brand new NodeID, so right-click the mouse anywhere in the view (without holding down any keys) so that nothing in the view is shown in dark grey. Then hold down "P" and left-click on the bottom of R2, and on the top of Q1, and then paint a track between them. That's all there is to it. The only difference between painting and erasing is using the right mouse button instead of the left. So holding down the SPACE bar, right-click and move the mouse to wipe all the tracks that you have painted. Notice that the pins are not wiped when using the SPACE bar. If you want to wipe them, you must use the "P" key instead and right-click on each one. PAINTING WIRES When painting a wire-end, you are actually painting the grid point under the wire-end rather than the wire itself. Try the following. Hold down the SPACE bar and left-click to paint one end of the wire on the left of the grid. Notice that the other wire-end is automatically painted. Now move the wire up. You will see the point that you painted is still colored, but the other point loses its color once the wire is moved. That is because it was only electrically connected to the painted point while the wire was in place. PAINTING TRACKS & PINS WITH FLOOD FILL It is possible to repaint entire tracks and all the pins on them using a "flood-fill". To do this, hold down the "F" key instead of the "P" key or SPACE bar. Try this now by first left-clicking on one of the track portions in the bottom-right portion of the view to select a NodeID for painting. Then hold down the F key and left click on the unbroken vertical track connecting C1 and C2. Both the track and the pins on it will be assigned the selected NodeID. Now try painting the broken track portion on the right of C1. Notice that the the broken track portion on C2 remains unaffected because it was not connected to the point that was clicked. TOGGLING BETWEEN COMPETING DIAGONALS Finally, look at the painted track sections in the bottom right of the grid. (You may need to Reload this tutorial if you modified what was originally there). There is a short diagonal track section going from top-left to bottom-right between two other track sections. VeroRoute does not allow diagonal connections to cross each other, so the current diagonal connection blocks a potential diagonal connection going the other way (from top-right to bottom-left). Double-clicking on the diagonal connection (without holding down any keys) will cause the competing diagonal to be used instead. Give that a try. џџџџџџџџџџџZ. 2: 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T 600 400 8 10 0 0 0 0 1 footprint=TO92 T 600 400 8 10 0 0 0 0 1 description=PNP Transistor VeroRoute/Src/StringHelper.h000644 001750 001750 00000004665 14026026345 016257 0ustar00alexalex000000 000000 /* VeroRoute - Qt based Veroboard/Perfboard/PCB layout & routing application. Copyright (C) 2017 Alex Lawrow ( dralx@users.sourceforge.net ) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #pragma once #include "Common.h" struct StringHelper { static bool IsEmptyStr(const std::string& in) { std::string s = in; s.erase(std::remove_if(s.begin(), s.end(), ::isspace), s.end()); return s.empty(); } static bool HasSpaces(const std::string& in) { std::string s = in; s.erase(std::remove_if(s.begin(), s.end(), ::isspace), s.end()); return s.size() < in.size(); } // Helper function for reading a line from a file during the netlist import. // Handles differing line-ending conventions between the file and the operating system. static std::istream& getline_safe(std::istream& inStream, std::string& str) { std::istream::sentry se(inStream, true); // Sentry object to protect and manage the stream buffer std::streambuf* sb = inStream.rdbuf(); str.clear(); while(true) { const int c = sb->sbumpc(); switch( c ) { case '\n': return inStream; case '\r': if ( sb->sgetc() == '\n' ) sb->sbumpc(); return inStream; case EOF: if ( str.empty() ) // In case last line has no ending inStream.setstate(std::ios::eofbit); return inStream; default: str += static_cast( c ); } } } std::vector strList; static void GetSubStrings(const std::string& in, std::vector& strList) { strList.clear(); std::istringstream iss(in); for (std::string s; iss >> s; ) strList.push_back(s); } StringHelper() { assert( true || PreventBuildWarnings() ); } private: bool PreventBuildWarnings() const { std::ifstream inStream; std::string str; StringHelper::IsEmptyStr(""); StringHelper::HasSpaces(""); StringHelper::getline_safe(inStream, str); return true; } }; VeroRoute/libraries/TinyCAD/VeroRoute_Diode.TCLib000644 001750 001750 00000260000 13515171160 022056 0ustar00alexalex000000 000000 SQLite format 3@ TH6ћћ.!%%‚tableSymbolSymbolCREATE TABLE [Symbol] ([SymbolID] INTEGER PRIMARY KEY,[Data] TEXT)ƒ8!†9tableNameNameCREATE TABLE [Name] ([NameID] INTEGER PRIMARY KEY,[Name] TEXT,[SymbolID] INTEGER,[Type] INTEGER,[Reference] TEXT,[ppp] INTEGER,[Description] TEXT,[ShowName] INTEGER,[ShowRef] INTEGER,[DefRotate] INTEGE ўб˜б YллУУУУYG =AOPAMP-SINGLEU?Single Op Amp5 --RES )ESW-SPSTSW?Off Board SPSTЩ)ESW-SPDTSW?Off Board SPDT†)ESW-DPDTSW?Off Board DPDTgC)ESW-3PDTSW?Off Board 3PDT?]LEDD?Light Emitting Diodeњ99DIODE-ZENERD?Zener DiodeњEEDIODE-SCHOTTKY D?Schottky Di+ %!1N4148D?Diodeе]LK )]Red-LEDD?Light Emitting Diode= 19ZENER-12VD?Zener Diode; !EBAT41D?Schottky Diode+!!DIODE D?Diodeт!ћіёьчтггггггггггЮ’’’’’7šr -10 0 400 0 0 0 0 Arial 000000 1 -1 000000 +ооЦЦ>>>8i$$SPICE_PROLOG_PRIORITY5 )!PackagePADS98i$$SPICE_EPILOG_PRIORITY58ir:i$$SPICE_PROLOG_PRIORITY58i$$SPICE_EPILOG_PRIORITY5:i$$SPICE_EPILOG_PRIORITY5")!PackagePADS23)PackageLED82i$$SPICE_EPILOG_PRIORITY581i$$SPICE_PROLOG_PRIORITY5 6)!PackageDIODE85i$$SPICE_EPILOG_PRIORITY584i$$SPICE_PROLOG_PRIORITY5 *)!PackageDIODE8)i$$SPICE_EPILOG_PRIORITY58(i$$SPICE_PROLOG_PRIORITY5 -)!PackageDIODE8,i$$SPICE_EPILOG_PRIORITY58+i$$SPICE_PROLOG_PRIORITY5 ””OЫƒ8!†9tableNameNameCREATE TABLE [Name] ([NameID] INTEGER PRIMARY KEY,[Name] TEXT,[SymbolID] INTEGER,[Type] INTEGER,[Reference] TEXT,[ppp] INTEGER,[Descriptƒ8!†9tableNameNameCREATE TABLE [Name] ([NameID] INTEGER PRIMARY KEY,[Name] TEXT,[SymbolID] INTEGER,[Type] INTEGER,[Reference] TEXT,[ppp] INTEGER,[Description] TEXT,[ShowName] INTEGER,[ShowRef] INTEGER,[DefRotate] INTEGER).!%%‚tableSymbolSymbolCREATE TABLE [Symbol] ([SymbolID] INTEGER PRIMARY KEY,[Data] TEXT) ИштмњєюФОИжаЪLLLLLLРРРŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠŠxxxTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTв$&rв&qв&pв%oв %nв%mв$lв $kв$jв6#iв0#hв*#gв$"fв"eв"dв!cв !bв!a”Œ `”† _”€ ^”z] \[ъZP0YP*XP$WPVPUPTP SPR Qю,Pю&Oю NP MPLDKJIќH GFhE DCzB A@Œ? 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Try out the following track styles on the current circuit. FAT: The horizontal and vertical tracks are wide and enlarged to have the same width as the pads. THIN: The tracks are narrower than the pads. This mode is the easiest way to work with things visually. CURVED: This is similar to the thin track style, except the tracks are smoothed to avoid sharp corners. Note that the fat, thin and curved modes have the same electrical connectivity, so the difference between them is cosmetic. VERO: There is no topological difference between using a Vero track style, and using another style with diagonal connections disabled. For stripboard builds, it is advised to use the "Thin" or "Curved" style with diagonal connections disabled during the bulk of the design process, as it is hard to work with the Vero style due to "visual overload". It is best to switch to a "Vero" style once the circuit layout and connectivity is complete. Note that the strips are not created before the circuit is built. Instead they are determined by the layout, and the program can create the strips for you. Try the following for the current circuit... Select the vertical "Vero" style, and you will see that there are many short strip fragments. Now check the "On" box in the Control Dialog to enable Auto-Routing, and then hit the "Paste" button. This will automatically fill out the circuit with strips. The "Vero" styles automatically draw elliptical solder bridges to join adjacent strips together where needed. This is especially useful when the circuit is viewed in a flipped ("mirror") mode with the lower slider moved to the far left to turn off component outlines. This then shows a view of the strip side of the board with all the strip breaks and required bridges easily visible.џџџџџџџџZ. 2: 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300 250 300 150 3 0 0 0 -1 -1 L 250 200 350 200 3 0 0 0 -1 -1 L 250 600 350 600 3 0 0 0 -1 -1 T 600 900 5 10 1 1 0 0 1 device=NJM4558L T 200 900 8 10 1 1 0 0 1 refdes=U? T 200 1100 8 10 0 0 0 0 1 footprint=SIP8 T 200 1100 8 10 0 0 0 0 1 description=Dual Op Amp (SIL package) VeroRoute/Src/HistoryManager.h000644 001750 001750 00000013364 14026034242 016574 0ustar00alexalex000000 000000 /* VeroRoute - Qt based Veroboard/Perfboard/PCB layout & routing application. Copyright (C) 2017 Alex Lawrow ( dralx@users.sourceforge.net ) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #pragma once // Class to manage history files for undo/redo functionality // An upper limit of 1000 files has been set, so the max undo level is 999. // This is to prevent the files using too much disk space. #include "Board.h" static const size_t MAX_HISTORY_FILES = 1000; typedef std::tuple HistoryItem; // typedef std::list::const_iterator HistoryItemIter; class HistoryManager { public: HistoryManager() : m_ID(0), m_bLocked(false) {} ~HistoryManager() { Clear(); } void SetPathStr(const std::string& str) { m_pathStr = str; } bool GetCanUndo() const { return !m_list.empty() && m_currentIter != m_list.begin(); } bool GetCanRedo() const { return !m_list.empty() && GetNextIter() != m_list.end(); } const std::string& GetUndoText() const { return std::get<2>(*m_currentIter); } const std::string& GetRedoText() const { return std::get<2>(*GetNextIter()); } bool Reset(const std::string& str, Board& board) { if ( m_bLocked ) return false; if ( m_ID != 0 ) Clear(); // If m_ID is valid then wipe all files that used it // Set a new (unique) m_ID for (m_ID = 1; m_ID < INT_MAX; m_ID++ ) // Keep increasing this until we get a unique ID { std::ifstream fTest( GetFilename(0) ); // See if (zeroth) filename with this ID exists if ( !fTest.good() ) break; // ID is not already in use so break } AddEntry(0, BAD_COMPID, str); return Save(board); } bool Update(const std::string& str, const int compId, Board& board) { if ( m_bLocked ) return false; if ( compId != BAD_COMPID ) // compId is only used when updating the Name and Value fields for a part { // or the 4 text fields in the component editor (which always uses compId == 0) assert( str == "Part name change" || str == "Part value change" || str == "Edit Value string" || str == "Edit Prefix string"|| str == "Edit Type string" || str == "Edit Import string" ); if ( (std::get<1>(*m_currentIter) == compId ) && // If we're working on the same part ... (std::get<2>(*m_currentIter) == str ) ) // ... and the same text field ... return Save(board); // ... then overwrite the current entry instead of adding a new one } auto iterNext = GetNextIter(); if ( iterNext != m_list.end() ) // We're modifying within the list ... { // Delete later history files for (auto iter = iterNext; iter != m_list.end(); ++iter) remove( GetFilename(std::get<0>(*iter)) ); m_list.erase(iterNext, m_list.end()); // Erase later history list items } else if ( m_list.size() == MAX_HISTORY_FILES ) // We're at the end of the list and the list is full ... { // We'll overwrite the first history file, so no need to delete it m_list.erase(m_list.begin()); // Erase first history list item } AddEntry(std::get<0>(*m_currentIter) + 1, compId, str); return Save(board); } void Lock() { m_bLocked = true; } void UnLock() { m_bLocked = false; } bool Undo(Board& board) { assert( m_bLocked ); // Should only Undo while the list is locked if ( !GetCanUndo() ) return false; --m_currentIter; return Load(board); } bool Redo(Board& board) { assert( m_bLocked ); // Should only Redo while the list is locked if ( !GetCanRedo() ) return false; ++m_currentIter; return Load(board); } const char* GetCurrentFilename() const { return ( m_list.empty() ) ? "\0" : GetFilename(std::get<0>(*m_currentIter)); } private: void AddEntry(const size_t& index, const int compId, const std::string& str) { m_list.push_back( HistoryItem(index % MAX_HISTORY_FILES, compId, str) ); m_currentIter = m_list.end(); m_currentIter--; } void Clear() { for (size_t i = 0; i < MAX_HISTORY_FILES; i++) remove( GetFilename(i) );// Delete all possible history files m_bLocked = false; m_list.clear(); } bool Load(Board& board) { DataStream inStream(DataStream::READ); if ( !inStream.Open( GetCurrentFilename() ) ) return false; board.Load(inStream); inStream.Close(); return inStream.GetOK(); } bool Save(Board& board) { DataStream outStream(DataStream::WRITE); if ( !outStream.Open( GetCurrentFilename() ) ) return false; board.Save(outStream); outStream.Close(); return true; } HistoryItemIter GetNextIter() const { auto iter = m_currentIter; ++iter; return iter; } const char* GetFilename(const size_t& index) const { assert( index < MAX_HISTORY_FILES ); // Sanity check memset(m_buffer, 0, 256 * sizeof(char)); sprintf(m_buffer, "%s/history/history_%d_%d.vrt", m_pathStr.c_str(), m_ID, static_cast(index)); return m_buffer; } private: std::string m_pathStr; // Path to the "history" folder int m_ID; // Allows multiple VeroRoute instances to share the same "history" folder. bool m_bLocked; // Should lock the list while doing Undo() or Redo() std::list m_list; // Each history item is an pair HistoryItemIter m_currentIter; // Points to the last written history item mutable char m_buffer[256]; // For constructing history filenames }; VeroRoute/Src/Persist.h000644 001750 001750 00000007160 14026372123 015271 0ustar00alexalex000000 000000 /* VeroRoute - Qt based Veroboard/Perfboard/PCB layout & routing application. Copyright (C) 2017 Alex Lawrow ( dralx@users.sourceforge.net ) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #pragma once // A helper for reading/writing data to a file in binary form #include #include #include "VrtVersion.h" #include "StringHelper.h" struct DataStream { enum TYPE { READ = 0, WRITE = 1 }; DataStream(TYPE type) : m_type(type), m_version(0), m_bOK(true) {} ~DataStream() {} bool Open(const char* fileName) { m_file.setFileName( QString(fileName) ); m_bOK = m_file.open(m_type == READ ? QIODevice::ReadOnly : QIODevice::WriteOnly); if ( m_bOK ) { m_ios.setDevice(&m_file); m_ios.setVersion(QDataStream::Qt_4_5); } return m_bOK; } void Close() { m_file.close(); } void Load(bool& o) { m_ios >> o; } void Load(char& o) { qint8 t; m_ios >> t; o = static_cast (t); } void Load(unsigned char& o) { quint8 t; m_ios >> t; o = static_cast (t); } void Load(short& o) { qint16 t; m_ios >> t; o = static_cast (t); } void Load(unsigned short& o) { quint16 t; m_ios >> t; o = static_cast (t); } void Load(int& o) { qint32 t; m_ios >> t; o = static_cast (t); } void Load(unsigned int& o) { quint32 t; m_ios >> t; o = static_cast (t); } void Load(float& o) { m_ios >> o; } void Load(double& o) { m_ios >> o; } void Load(std::string& o) { QString t; m_ios >> t; o = t.toStdString();} void Save(const bool& o) { m_ios << o; } void Save(const char& o) { m_ios << static_cast (o); } void Save(const unsigned char& o) { m_ios << static_cast (o); } void Save(const short& o) { m_ios << static_cast (o); } void Save(const unsigned short& o) { m_ios << static_cast (o); } void Save(const int& o) { m_ios << static_cast (o); } void Save(const unsigned int& o) { m_ios << static_cast (o); } void Save(const float& o) { m_ios << o; } void Save(const double& o) { m_ios << o; } void Save(const std::string& o) { m_ios << QString::fromStdString(o); } const int& GetVersion() const { return m_version; } void SetVersion(int i) { m_version = i; } const bool& GetOK() const { return m_bOK; } void SetOK(bool b) { m_bOK = b; } private: TYPE m_type; QFile m_file; QDataStream m_ios; int m_version; // Used to represent VRT version being loaded so the format can evolve bool m_bOK; // To flag problems }; // The interface definition for load and saving data to file struct Persist { virtual void Load(DataStream&) = 0; virtual void Save(DataStream&) = 0; }; // A helper struct to allow 2 Board objects to be merged without conflicts. struct MergeOffsets { int deltaNodeId = 0; int deltaCompId = 0; int deltaGroupId = 0; int deltaLyr = 0; int deltaRow = 0; int deltaCol = 0; }; // The interface definition for handling merge offsets struct Merge { virtual void UpdateMergeOffsets(MergeOffsets&) = 0; virtual void ApplyMergeOffsets(const MergeOffsets&) = 0; }; VeroRoute/libraries/gEDA/veroroute_linear/OTA_LM13600.sym000644 001750 001750 00000006561 13515171161 023204 0ustar00alexalex000000 000000 v 20130925 2 T 200 1100 5 10 0 0 0 0 1 slot=1 T 200 1300 5 10 0 0 0 0 1 numslots=2 T 200 1500 5 10 0 0 0 0 1 slotdef=1:1,2,3,4,5,6,7,8,11 T 200 1700 5 10 0 0 0 0 1 slotdef=2:16,15,14,13,12,6,10,9,11 P 1400 1800 1400 2000 1 0 1 { T 1450 1850 5 8 1 1 0 0 1 pinnumber=1 T 1450 1100 5 8 0 1 0 0 1 pinseq=1 T 1800 1050 9 8 0 1 0 5 1 pinlabel=AMP BIAS T 1450 1100 5 8 0 1 0 0 1 pintype=in } P 0 1000 200 1000 1 0 0 { T 150 1050 5 8 1 1 0 6 1 pinnumber=2 T 350 1050 5 8 0 1 0 0 1 pinseq=2 T 425 950 9 8 0 1 0 0 1 pinlabel=DIODE BIAS T 350 1050 5 8 0 1 0 0 1 pintype=in } P 0 1400 200 1400 1 0 0 { T 150 1450 5 8 1 1 0 6 1 pinnumber=3 T 350 1450 5 8 0 1 0 0 1 pinseq=3 T 450 1400 9 8 0 1 0 0 1 pinlabel=IN+ T 350 1450 5 8 0 1 0 0 1 pintype=in } P 0 600 200 600 1 0 0 { T 150 650 5 8 1 1 0 6 1 pinnumber=4 T 350 650 5 8 0 1 0 0 1 pinseq=4 T 450 600 9 8 0 1 0 0 1 pinlabel=IN- T 350 650 5 8 0 1 0 0 1 pintype=in } P 1600 200 1600 0 1 0 1 { T 1650 50 5 8 1 1 0 0 1 pinnumber=5 T 1650 500 5 8 0 1 0 0 1 pinseq=5 T 1550 600 9 8 0 1 0 3 1 pinlabel=5 T 1650 500 5 8 0 1 0 0 1 pintype=out } P 2000 200 2000 0 1 0 1 { T 2050 50 5 8 1 1 0 0 1 pinnumber=6 T 2050 400 5 8 0 1 0 0 1 pinseq=6 T 2000 250 9 8 1 1 0 3 1 pinlabel=V- T 2050 400 5 8 0 1 0 0 1 pintype=pwr } P 2400 200 2400 0 1 0 1 { T 2450 50 5 8 1 1 0 0 1 pinnumber=7 T 2450 500 5 8 0 1 0 0 1 pinseq=7 T 2350 600 9 8 0 1 0 3 1 pinlabel=7 T 2450 500 5 8 0 0 0 0 1 pintype=in } P 3000 200 3000 0 1 0 1 { T 3050 50 5 8 1 1 0 0 1 pinnumber=8 T 3050 500 5 8 0 1 0 0 1 pinseq=8 T 2950 600 9 8 0 1 0 3 1 pinlabel=8 T 3050 500 5 8 0 1 0 0 1 pintype=out } P 2000 1800 2000 2000 1 0 1 { T 2050 1850 5 8 1 1 0 0 1 pinnumber=11 T 2150 1400 5 8 0 1 0 0 1 pinseq=9 T 1875 1675 9 8 1 1 0 5 1 pinlabel=V+ T 2150 1400 5 8 0 1 0 0 1 pintype=pwr } B 200 200 3000 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 V 1350 1000 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 V 1450 1000 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 L 3000 1300 3000 200 3 0 0 0 -1 -1 L 2000 1800 2000 800 3 0 0 0 -1 -1 L 2200 800 2000 800 3 0 0 0 -1 -1 L 2300 600 2200 800 3 0 0 0 -1 -1 L 2400 600 2400 200 3 0 0 0 -1 -1 L 2200 600 2600 600 3 0 0 0 -1 -1 L 2500 600 2600 800 3 0 0 0 -1 -1 H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5 M 2591,703 L 2600,801 L 2527,731 L 2560,725 z L 2400 1100 2800 1100 3 0 0 0 -1 -1 L 2600 800 2600 1100 3 0 0 0 -1 -1 L 2700 1100 2800 1300 3 0 0 0 -1 -1 H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5 M 2791,1203 L 2800,1301 L 2727,1231 L 2760,1225 z L 2500 1100 2400 1300 3 0 0 0 -1 -1 L 2400 1300 2000 1300 3 0 0 0 -1 -1 L 2800 1300 3000 1300 3 0 0 0 -1 -1 L 1600 1000 1550 1000 3 0 0 0 -1 -1 L 1600 200 1600 1000 3 0 0 0 -1 -1 L 350 1150 400 1250 3 0 0 0 -1 -1 L 450 1150 400 1250 3 0 0 0 -1 -1 L 350 1250 450 1250 3 0 0 0 -1 -1 L 350 1150 450 1150 3 0 0 0 -1 -1 L 350 850 450 850 3 0 0 0 -1 -1 L 350 750 450 750 3 0 0 0 -1 -1 L 400 750 450 850 3 0 0 0 -1 -1 L 400 750 350 850 3 0 0 0 -1 -1 L 400 1600 400 1250 3 0 0 0 -1 -1 L 400 1150 400 850 3 0 0 0 -1 -1 L 1400 1800 1400 1100 3 0 0 0 -1 -1 L 400 1400 200 1400 3 0 0 0 -1 -1 L 400 600 200 600 3 0 0 0 -1 -1 L 400 1000 200 1000 3 0 0 0 -1 -1 L 400 750 400 400 3 0 0 0 -1 -1 L 400 1600 1250 1000 3 0 0 0 -1 -1 L 1250 1000 400 400 3 0 0 0 -1 -1 L 500 1450 500 1350 3 0 0 0 -1 -1 L 450 1400 550 1400 3 0 0 0 -1 -1 L 450 600 550 600 3 0 0 0 -1 -1 T 200 2000 5 10 1 1 0 0 1 device=LM13600 T 200 2200 8 10 1 1 0 0 1 refdes=U? T 200 1100 8 10 0 0 0 0 1 footprint=DIP16 T 200 1100 8 10 0 0 0 0 1 description=Dual OTA VeroRoute/libraries/gEDA/veroroute_linear/Comparator_LM311.sym000644 001750 001750 00000003351 13515171161 024515 0ustar00alexalex000000 000000 v 20130925 2 T 400 900 8 10 0 0 0 0 1 numslots=0 P 400 900 200 900 1 0 1 { T 250 925 5 8 1 1 0 0 1 pinnumber=2 T 250 925 5 8 0 0 0 0 1 pinseq=2 T 250 925 5 8 0 0 0 0 1 pinlabel=2 T 250 925 5 8 0 0 0 0 1 pintype=pas } P 400 500 200 500 1 0 1 { T 250 525 5 8 1 1 0 0 1 pinnumber=3 T 250 525 5 8 0 0 0 0 1 pinseq=3 T 250 525 5 8 0 0 0 0 1 pinlabel=3 T 250 525 5 8 0 0 0 0 1 pintype=pas } P 1000 700 1200 700 1 0 1 { T 1075 725 5 8 1 1 0 0 1 pinnumber=7 T 1075 725 5 8 0 0 0 0 1 pinseq=7 T 1075 725 5 8 0 0 0 0 1 pinlabel=7 T 1075 725 5 8 0 0 0 0 1 pintype=pas } P 500 1025 500 1200 1 0 1 { T 525 1050 5 8 1 1 0 0 1 pinnumber=8 T 500 1200 5 8 0 0 0 0 1 pinseq=8 T 500 1200 5 8 0 0 0 0 1 pinlabel=8 T 500 1200 5 8 0 0 0 0 1 pintype=pas } P 500 375 500 100 1 0 1 { T 375 50 5 8 1 1 0 0 1 pinnumber=4 T 375 50 5 8 0 0 0 0 1 pinseq=4 T 375 50 5 8 0 0 0 0 1 pinlabel=4 T 375 50 5 8 0 0 0 0 1 pintype=pas } P 700 500 700 100 1 0 1 { T 750 125 5 8 1 1 0 0 1 pinnumber=1 T 750 125 5 8 0 0 0 0 1 pinseq=1 T 750 125 5 8 0 0 0 0 1 pinlabel=1 T 750 125 5 8 0 0 0 0 1 pintype=pas } P 700 900 700 1200 1 0 1 { T 750 1050 5 8 1 1 0 0 1 pinnumber=5 T 725 1175 5 8 0 0 0 0 1 pinseq=5 T 725 1175 5 8 0 0 0 0 1 pinlabel=5 T 725 1175 5 8 0 0 0 0 1 pintype=pas } P 900 775 900 1200 1 0 1 { T 950 1050 5 8 1 1 0 0 1 pinnumber=6 T 925 1150 5 8 0 0 0 0 1 pinseq=6 T 925 1150 5 8 0 0 0 0 1 pinlabel=6 T 925 1150 5 8 0 0 0 0 1 pintype=pas } L 400 1100 400 300 3 0 0 0 -1 -1 L 400 300 1000 700 3 0 0 0 -1 -1 L 1000 700 400 1100 3 0 0 0 -1 -1 L 500 950 500 850 3 0 0 0 -1 -1 L 450 900 550 900 3 0 0 0 -1 -1 L 450 500 550 500 3 0 0 0 -1 -1 T 950 150 5 10 1 1 0 0 1 device=LM311 T 1000 400 8 10 1 1 0 0 1 refdes=U? T 700 600 8 10 0 0 0 0 1 footprint=DIP8 T 700 600 8 10 0 0 0 0 1 description=Comparator VeroRoute/Src/ConnectionMatrix.h000644 001750 001750 00000005571 14026034476 017136 0ustar00alexalex000000 000000 /* VeroRoute - Qt based Veroboard/Perfboard/PCB layout & routing application. Copyright (C) 2017 Alex Lawrow ( dralx@users.sourceforge.net ) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #pragma once #include "Common.h" // Keeps track of connectivity between a set of points (e.g. target pins in the routing algorithm) class ConnectionMatrix { public: ConnectionMatrix() {} ~ConnectionMatrix() { DeAllocate(); } void Allocate(const size_t& N) { m_N = N; const size_t N2 = m_N * m_N; m_p = new bool[N2]; m_pp = new bool*[m_N]; memset(m_p, 0, N2 * sizeof(bool)); for (size_t i = 0; i < m_N; i++) m_pp[i] = m_p + i * m_N; for (size_t i = 0; i < m_N; i++) m_pp[i][i] = true; // Each point is connected to itself m_cost = static_cast(N2 - m_N); // Cost = number of false values in the connection matrix } void DeAllocate() { if ( m_pp ) delete[] m_pp; if ( m_p ) delete[] m_p; m_pp = nullptr; m_p = nullptr; } void Connect(const size_t& j, const size_t& k) { // Make j-k connection and enforce transitivity typedef std::pair CONNECTION; std::list list; // Helper for updating the connection matrix list.push_back( CONNECTION(j,k) ); while ( !list.empty() ) { auto iter = list.begin(); // Read info from first list entry ... const auto a = iter->first; const auto b = iter->second; list.erase( iter ); // ... then remove the list entry if ( !m_pp[a][b] ) // If no a-b connection ... { m_pp[a][b] = m_pp[b][a] = true; // Make a-b connection ... m_cost -= 2; // Update cost for (size_t c = 0; c < m_N; c++) // Update 1st-order transitive relations { if ( m_pp[a][c] ) { if ( !m_pp[b][c] ) list.push_back( CONNECTION(b,c) ); // a-c connection ==> b-c connection } else { if ( m_pp[b][c] ) list.push_back( CONNECTION(a,c) ); // b-c connection ==> a-c connection } } } } } const bool& GetAreConnected(const size_t& j, const size_t& k) const { return m_pp[j][k]; } const unsigned int& GetCost() const { return m_cost; } private: size_t m_N = 0; // Number of points in the set bool* m_p = nullptr; // bool** m_pp = nullptr; // m_pp[j][k] is true if points j and k are connected unsigned int m_cost = UINT_MAX; // Zero ==> all points are connected }; VeroRoute/libraries/gEDA/veroroute_transistor/NPN_2N3903.sym000644 001750 001750 00000001563 13515171161 024043 0ustar00alexalex000000 000000 v 20130925 2 T 0 500 5 10 0 0 0 0 1 numslots=0 P 0 500 200 500 1 0 0 { T 100 550 5 6 1 1 0 0 1 pinnumber=2 T 100 550 5 6 0 0 0 0 1 pinseq=2 T 100 550 5 6 0 0 0 0 1 pinlabel=2 T 100 550 5 6 0 0 0 0 1 pintype=pas } P 500 1000 500 800 1 0 0 { T 400 850 5 6 1 1 0 0 1 pinnumber=3 T 400 850 5 6 0 0 0 0 1 pinseq=3 T 400 850 5 6 0 0 0 0 1 pinlabel=3 T 400 850 5 6 0 0 0 0 1 pintype=pas } P 500 200 500 0 1 0 1 { T 400 50 5 6 1 1 0 0 1 pinnumber=1 T 400 50 5 6 0 0 0 0 1 pinseq=1 T 400 50 5 6 0 0 0 0 1 pinlabel=1 T 400 50 5 6 0 0 0 0 1 pintype=pas } L 200 650 500 800 3 0 0 0 -1 -1 L 200 350 500 200 3 0 0 0 -1 -1 L 200 800 200 200 3 0 0 0 -1 -1 H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5 M 403,209 L 501,200 L 431,273 L 425,240 z T 600 700 5 10 1 1 0 0 1 device=2N3903 T 600 400 8 10 1 1 0 0 1 refdes=Q? T 600 400 8 10 0 0 0 0 1 footprint=TO92 T 600 400 8 10 0 0 0 0 1 description=NPN Transistor VeroRoute/Src/Shape.h000644 001750 001750 00000021605 14026366533 014710 0ustar00alexalex000000 000000 /* VeroRoute - Qt based Veroboard/Perfboard/PCB layout & routing application. Copyright (C) 2017 Alex Lawrow ( dralx@users.sourceforge.net ) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #pragma once #include "MyRGB.h" // Class to describe a simple shape (e.g. for drawing component outlines) enum class SHAPE { LINE = 0, RECT, ROUNDED_RECT, ELLIPSE, ARC, CHORD }; class Shape : public Persist { public: Shape(SHAPE type = SHAPE::RECT, bool bLine = true, bool bFill = false, double x1 = 0, double x2 = 0, double y1 = 0, double y2 = 0, double a3 = 0) : m_type(type) , m_x1(x1), m_x2(x2) , m_y1(y1), m_y2(y2) , m_a1(0), m_a2(90), m_a3(a3) , m_bDrawLine(bLine) , m_bDrawFill(bFill) , m_lineColor(0x000000) , m_fillColor(0x00FF00) // Green { } Shape(SHAPE type, bool bLine, bool bFill, double x1, double x2, double y1, double y2, double a1, double a2, double a3 = 0) : m_type(type) , m_x1(x1), m_x2(x2) , m_y1(y1), m_y2(y2) , m_a1(a1), m_a2(a2), m_a3(a3) , m_bDrawLine(bLine) , m_bDrawFill(bFill) , m_lineColor(0x000000) , m_fillColor(0x00FF00) // Green { } Shape(const Shape& o) { *this = o; } virtual ~Shape() {} Shape& operator=(const Shape& o) { m_type = o.m_type; m_x1 = o.m_x1; m_x2 = o.m_x2; m_y1 = o.m_y1; m_y2 = o.m_y2; m_a1 = o.m_a1; m_a2 = o.m_a2; m_a3 = o.m_a3; m_bDrawLine = o.m_bDrawLine; m_bDrawFill = o.m_bDrawFill; m_lineColor = o.m_lineColor; m_fillColor = o.m_fillColor; return *this; } bool operator==(const Shape& o) const // Compare persisted info { return m_type == o.m_type && m_x1 - o.m_x1 == 0.0 && m_x2 - o.m_x2 == 0.0 && m_y1 - o.m_y1 == 0.0 && m_y2 - o.m_y2 == 0.0 && m_a1 - o.m_a1 == 0.0 && m_a2 - o.m_a2 == 0.0 && m_a3 - o.m_a3 == 0.0 && m_bDrawLine == o.m_bDrawLine && m_bDrawFill == o.m_bDrawFill && m_lineColor == o.m_lineColor && m_fillColor == o.m_fillColor; } bool operator!=(const Shape& o) const { return !(*this == o); } bool operator<(const Shape& o) const // For determining render order { if ( m_bDrawLine != o.m_bDrawLine ) return !m_bDrawLine; // Prefer no line if ( m_bDrawFill != o.m_bDrawFill ) return m_bDrawFill; // Prefer fill if ( m_lineColor != o.m_lineColor ) return m_lineColor < o.m_lineColor; if ( m_fillColor != o.m_fillColor ) return m_fillColor < o.m_fillColor; if ( m_type != o.m_type ) return static_cast(m_type) < static_cast(o.m_type); if ( m_x1 - o.m_x1 != 0.0 ) return m_x1 < o.m_x1; if ( m_x2 - o.m_x2 != 0.0 ) return m_x2 < o.m_x2; if ( m_y1 - o.m_y1 != 0.0 ) return m_y1 < o.m_y1; if ( m_y2 - o.m_y2 != 0.0 ) return m_y2 < o.m_y2; if ( m_a1 - o.m_a1 != 0.0 ) return m_a1 < o.m_a1; if ( m_a2 - o.m_a2 != 0.0 ) return m_a2 < o.m_a2; return m_a3 < o.m_a3; } void SetType(const SHAPE& c) { m_type = c; } void SetX1(const double& d) { m_x1 = d; } void SetX2(const double& d) { m_x2 = d; } void SetY1(const double& d) { m_y1 = d; } void SetY2(const double& d) { m_y2 = d; } void SetA1(const double& d) { m_a1 = d; } void SetA2(const double& d) { m_a2 = d; } void SetA3(const double& d) { m_a3 = d; } void SetDrawLine(const bool& b) { m_bDrawLine = b; } void SetDrawFill(const bool& b) { m_bDrawFill = b; } void SetLineColor(const MyRGB& r) { m_lineColor = r; } void SetFillColor(const MyRGB& r) { m_fillColor = r; } void Set(const double& x1, const double& x2, const double& y1, const double& y2, const double& a1, const double& a2, const double& a3) { m_x1 = x1; m_x2 = x2; m_y1 = y1; m_y2 = y2; m_a1 = a1; m_a2 = a2; m_a3 = a3; } void SetCX(const double& d) { Move(0, d - GetCX()); } void SetCY(const double& d) { Move(d - GetCY(), 0); } void SetDX(const double& d) { Expand( d - GetDX(), 0 ); } void SetDY(const double& d) { Expand( 0, d - GetDY() ); } void Move(const double& dDown, const double& dRight) { m_x1 += dRight; m_x2 += dRight; m_y1 += dDown; m_y2 += dDown; } void Expand(const double& dx, const double& dy) { m_x1 -= 0.5 * dx; m_x2 += 0.5 * dx; m_y1 -= 0.5 * dy; m_y2 += 0.5 * dy; } const SHAPE& GetType() const { return m_type; } const double& GetX1() const { return m_x1; } const double& GetX2() const { return m_x2; } const double& GetY1() const { return m_y1; } const double& GetY2() const { return m_y2; } const double& GetA1() const { return m_a1; } const double& GetA2() const { return m_a2; } const double& GetA3() const { return m_a3; } const bool& GetDrawLine() const { return m_bDrawLine; } const bool& GetDrawFill() const { return m_bDrawFill; } const MyRGB& GetLineColor() const { return m_lineColor; } const MyRGB& GetFillColor() const { return m_fillColor; } const double& GetXmin() const { return std::min(m_x1, m_x2); } const double& GetXmax() const { return std::max(m_x1, m_x2); } const double& GetYmin() const { return std::min(m_y1, m_y2); } const double& GetYmax() const { return std::max(m_y1, m_y2); } double GetCX() const { return 0.5 * ( m_x1 + m_x2 ); } double GetCY() const { return 0.5 * ( m_y1 + m_y2 ); } double GetDX() const { return m_x2 - m_x1; } double GetDY() const { return m_y2 - m_y1; } double GetXlen() const { return fabs(GetDX()); } double GetYlen() const { return fabs(GetDY()); } double GetAlen() const { double d = m_a2 - m_a1; while ( d < 0 ) d += 360.0; return d; } void GetSafeBounds(double& L, double& R, double& T, double& B) const // Allows for worst case rotation "A3" { if ( GetA3() == 0.0 ) { L = GetXmin(); R = GetXmax(); T = GetYmin(); B = GetYmax(); } else { // The following could be improved (to a tighter bound) by considering the shape and rotation angle const double DX( GetDX() ), DY( GetDY() ); const double d = sqrt(DX*DX + DY*DY) * 0.5; L = GetCX() - d; R = GetCX() + d; T = GetCY() - d; B = GetCY() + d; } } // Persist interface functions virtual void Load(DataStream& inStream) override { int type(0); inStream.Load(type); m_type = static_cast(type); inStream.Load(m_x1); inStream.Load(m_x2); inStream.Load(m_y1); inStream.Load(m_y2); inStream.Load(m_a1); inStream.Load(m_a2); if ( inStream.GetVersion() >= VRT_VERSION_29 ) { inStream.Load(m_a3); // Added in VRT_VERSION_29 inStream.Load(m_bDrawLine); // Added in VRT_VERSION_29 inStream.Load(m_bDrawFill); // Added in VRT_VERSION_29 m_lineColor.Load(inStream); // Added in VRT_VERSION_29 m_fillColor.Load(inStream); // Added in VRT_VERSION_29 } else { m_a3 = 0; m_bDrawLine = true; m_bDrawFill = false; m_lineColor.SetRGB(0,0,0); m_fillColor.SetRGB(0,255,0); // Green } } virtual void Save(DataStream& outStream) override { outStream.Save(static_cast(m_type)); outStream.Save(m_x1); outStream.Save(m_x2); outStream.Save(m_y1); outStream.Save(m_y2); outStream.Save(m_a1); outStream.Save(m_a2); outStream.Save(m_a3); // Added in VRT_VERSION_29 outStream.Save(m_bDrawLine); // Added in VRT_VERSION_29 outStream.Save(m_bDrawFill); // Added in VRT_VERSION_29 m_lineColor.Save(outStream); // Added in VRT_VERSION_29 m_fillColor.Save(outStream); // Added in VRT_VERSION_29 } static const std::map& GetMapShapeStrings() { static std::map mapShapeToStr; // Mapping of SHAPE enum to strings if ( mapShapeToStr.empty() ) { mapShapeToStr[SHAPE::LINE] = "Line"; mapShapeToStr[SHAPE::RECT] = "Rectangle"; mapShapeToStr[SHAPE::ROUNDED_RECT] = "Rounded Rectangle"; mapShapeToStr[SHAPE::ELLIPSE] = "Ellipse"; mapShapeToStr[SHAPE::ARC] = "Arc"; mapShapeToStr[SHAPE::CHORD] = "Chord"; } return mapShapeToStr; } private: // Data (x1,y1) and (x2,y2) are either // the start and end points of a line, or the TL and BR corners of a rectangle. // Ellipses fit to the rectangle. // An arc is a CCW part of the ellipse, starting at "a1" and ending at "a2". // Note the angle is w.r.t. a circle rather than an ellipse. // The angle "a3" can be used to provide a final CCW rotation of the shape about its centre. SHAPE m_type; double m_x1, m_x2; // Units of 100 mil w.r.t. footprint centre double m_y1, m_y2; // Units of 100 mil w.r.t. footprint centre double m_a1, m_a2, m_a3; // Angles measured CCW degrees. Zero at 3 o'clock. bool m_bDrawLine; // Draw line (can only be false if m_bFill is true) bool m_bDrawFill; // Fill with color MyRGB m_lineColor; // Line color. Always black MyRGB m_fillColor; // Fill color. }; VeroRoute/Src/Grid.h000644 001750 001750 00000032227 14026402510 014521 0ustar00alexalex000000 000000 /* VeroRoute - Qt based Veroboard/Perfboard/PCB layout & routing application. Copyright (C) 2017 Alex Lawrow ( dralx@users.sourceforge.net ) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #pragma once #include "CompElement.h" #include "Element.h" #include "CompTypes.h" // For component length limits // Grid is a templatized 3-dimensional array, with data that can be indexed by layer, row and column template class Grid : public Persist, public Merge { public: Grid() { Allocate(0, 0, 0); } Grid(const Grid& o) { *this = o; } virtual ~Grid() { DeAllocate(); } Grid& operator=(const Grid& o) { Allocate(o.m_lyrs, o.m_rows, o.m_cols); for (int i = 0, iSize = GetSize(); i < iSize; i++) m_pData[i] = o.m_pData[i]; return *this; } bool operator==(const Grid& o) const // Compare persisted info { bool bOK = m_lyrs == o.m_lyrs && m_rows == o.m_rows && m_cols == o.m_cols; for (int i = 0, iSize = GetSize(); i < iSize && bOK; i++) bOK = ( m_pData[i] == o.m_pData[i] ); return bOK; } bool operator!=(const Grid& o) const { return !(*this == o); } void Clear(const T& val) { for (int i = 0, iSize = GetSize(); i < iSize; i++) m_pData[i] = val; } void Allocate(int lyrs, int rows, int cols) { DeAllocate(); m_lyrs = lyrs; m_rows = rows; m_cols = cols; m_pData = new T[m_lyrs * m_rows * m_cols]; m_ppData = new T*[m_lyrs * m_rows]; m_pppData = new T**[m_lyrs]; for (int i = 0, iSize = m_lyrs * m_rows; i < iSize; i++) m_ppData[i] = m_pData + i * m_cols; for (int i = 0, iSize = m_lyrs; i < iSize; i++) m_pppData[i] = m_ppData + i * m_rows; } void DeAllocate() { if ( m_pppData ) delete[] m_pppData; if ( m_ppData ) delete[] m_ppData; if ( m_pData ) delete[] m_pData; m_pppData = nullptr; m_ppData = nullptr; m_pData = nullptr; m_lyrs = m_rows = m_cols = 0; } const int& GetLyrs() const { return m_lyrs; } const int& GetRows() const { return m_rows; } const int& GetCols() const { return m_cols; } int GetSize() const { return m_lyrs * m_rows * m_cols; } void GetRowCol(const T* p, int& row, int& col) const { int lyr; // dummy GetLyrRowCol(p, lyr, row, col); } void GetLyrRowCol(const T* p, int& lyr, int& row, int& col) const { const size_t ii = ( p - m_pData ); assert( ii < static_cast ( GetSize() ) ); const int i = static_cast (ii); const int rowLyr = i / m_cols; col = i % m_cols; lyr = rowLyr / m_rows; row = rowLyr % m_rows; } T* GetAt(int i) { return m_pData + i; } T* GetAtConst(int i) const { return m_pData + i; } T* Get(int lyr, int row, int col) const { return m_pppData[lyr][row] + col;} void SetAt(int i, const T& val) { m_pData[i] = val; } void Set(int lyr, int row, int col, const T& o) { m_pppData[lyr][row][col] = o; } void Grow(int incLyrs, int incRows, int incCols) // Grow/shrink the current array { if ( incLyrs == 0 && incRows == 0 && incCols == 0 ) return; Grid tmp(*this); // Make a temporary copy of this grid Allocate(m_lyrs + incLyrs, m_rows + incRows, m_cols + incCols); // Re-allocate this grid to make it larger/smaller // Now copy the tmp data into the new grid for (int lyr = 0, lyrs = std::min(GetLyrs(), tmp.GetLyrs()); lyr < lyrs; lyr++) for (int row = 0, rows = std::min(GetRows(), tmp.GetRows()); row < rows; row++) for (int col = 0, cols = std::min(GetCols(), tmp.GetCols()); col < cols; col++) m_pppData[lyr][row][col] = tmp.m_pppData[lyr][row][col]; } // Merge interface functions virtual void UpdateMergeOffsets(MergeOffsets& o) override { // o.deltaLyr = std::max(o.deltaLyr, GetLyrs() + 1); o.deltaRow = std::max(o.deltaRow, GetRows() + 1); // o.deltaCol = std::max(o.deltaCol, GetCols() + 1); for (int i = 0, iSize = GetSize(); i < iSize; i++) m_pData[i].UpdateMergeOffsets(o); } virtual void ApplyMergeOffsets(const MergeOffsets& o) override { for (int i = 0, iSize = GetSize(); i < iSize; i++) m_pData[i].ApplyMergeOffsets(o); } void Merge(const Grid& src, const MergeOffsets& o) { for (int lyr = 0, lyrs = src.GetLyrs(); lyr < lyrs; lyr++) for (int row = 0, rows = src.GetRows(); row < rows; row++) for (int col = 0, cols = src.GetCols(); col < cols; col++) Get(lyr + o.deltaLyr, row + o.deltaRow, col + o.deltaCol)->Merge(*src.Get(lyr, row, col)); } // Persist interface functions virtual void Load(DataStream& inStream) override { int lyrs(1), rows(1), cols(1); inStream.Load(rows); inStream.Load(cols); if ( inStream.GetVersion() >= VRT_VERSION_34 ) inStream.Load(lyrs); // Added in VRT_VERSION_34 Allocate(lyrs, rows, cols); for (int i = 0, iSize = GetSize(); i < iSize; i++) m_pData[i].Load(inStream); } virtual void Save(DataStream& outStream) override { outStream.Save(m_rows); outStream.Save(m_cols); outStream.Save(m_lyrs); // Added in VRT_VERSION_34 for (int i = 0, iSize = GetSize(); i < iSize; i++) m_pData[i].Save(outStream); } private: int m_lyrs = 0; int m_rows = 0; int m_cols = 0; T* m_pData = nullptr; T** m_ppData = nullptr; T*** m_pppData = nullptr; // So we can access data using [][][] }; // The PinGrid class is used by the component editor class (CompDefiner) typedef Grid PinGrid; typedef Grid TrackElementGrid; // The CompElementGrid class is used for component footprints and "track footprints". // It can handle simple transformations like stretching and rotating. // The internal "direction" of a CompElementGrid is always West ('W') // meaning that Pin 1 is to the West (left) of the centre. // For example, a resistor footprint is always stored as a CompElementGrid with a // single horizontal row, with the first pin on the far left and the second pin on the far right. // If we rotate a component so it points in another direction on screen, then any // methods that access the CompElementGrid information in a spatial way should specify // the component direction so the internal data can be read correctly. class CompElementGrid : public Grid { public: CompElementGrid() : Grid() {} CompElementGrid(const CompElementGrid& o) : Grid(o) { *this = o; } virtual ~CompElementGrid() override {} CompElementGrid& operator=(const CompElementGrid& o) { Grid::operator=(o); return *this; } bool operator==(const CompElementGrid& o) const { return Grid::operator==(o); } bool operator!=(const CompElementGrid& o) const { return Grid::operator!=(o); } const int& GetCols(char direction = 'W') const { switch( direction ) // Component direction: 'W','E','N','S' { case 'N': case 'S': return Grid::GetRows(); default: return Grid::GetCols(); } } const int& GetRows(char direction = 'W') const { switch( direction ) // Component direction: 'W','E','N','S' { case 'N': case 'S': return Grid::GetCols(); default: return Grid::GetRows(); } } CompElement* Get(int row, int col) const { assert( GetLyrs() == 1 ); return Grid::Get(0, row, col); } CompElement* Get(int lyr, int row, int col, char direction = 'W') const { assert( lyr == 0 && GetLyrs() == 1 ); Transform(row, col, direction); // Handle direction transformation return Grid::Get(lyr, row, col); } void StretchSimple(bool bGrow, const CompElement& initVal) // For simple 2-pin components like resistors, wires, diodes, caps { assert( GetLyrs() == 1 ); // Pins are assumed to be first and last element on the row if ( GetRows() == 1 && ( bGrow || GetCols() > 2 ) ) { CompElement a(*GetAt(0)), b(*GetAt(GetCols()-1)); // Read ends Allocate(GetLyrs(), GetRows(), bGrow ? GetCols() + 1 : GetCols() - 1); // Resize Clear(initVal); *GetAt(0) = a; *GetAt(GetCols()-1) = b; // Set ends } } void StretchComplex(const COMP& eType, bool bGrow) // For ICs and switches { assert( GetLyrs() == 1 ); if ( !bGrow && GetCols() == CompTypes::GetMinLength(eType) ) return; // Don't shrink to less than min allowed length if ( bGrow && GetCols() == CompTypes::GetMaxLength(eType) ) return; // Don't expand to more than max allowed length const int iDelta = CompTypes::GetStretchIncrement(eType); return Allocate(GetLyrs(), GetRows(), bGrow ? GetCols() + iDelta : GetCols() - iDelta); // Resize } void StretchWidthIC(bool bGrow) // For DIPs only { assert( GetLyrs() == 1 ); if ( !bGrow && GetRows() == 2 ) return; // Don't shrink DIP width to less than 2 rows return Allocate(GetLyrs(), bGrow ? GetRows() + 1 : GetRows() - 1, GetCols()); // Resize } virtual void Load(DataStream& inStream) override { if ( inStream.GetVersion() >= VRT_VERSION_11 ) return Grid::Load(inStream); // Handle legacy VRTs where components used a simple PinGrid instead of an CompElementGrid int rows(0), cols(0); inStream.Load(rows); inStream.Load(cols); const int lyrs = ( rows > 0 && cols > 0 ) ? 1 : 0; Allocate(lyrs, rows, cols); CompElement tmp; const int iSize = GetSize(); for (int i = 0; i < iSize; i++) { tmp.Pin::Load(inStream); // Just load the Pin info SetAt(i, tmp); } } private: void Transform(int& row, int& col, char direction) const { assert( GetLyrs() == 1 ); // On input: (row,col) are the "footprint" co-ordinates (as seen on screen). // On output: (row,col) have been set to the corresponding internal values. const int rTmp(row), cTmp(col); switch( direction ) // Component direction: 'W','E','N','S' { case 'W': return; case 'E': row = Grid::GetRows()-1 - rTmp; col = Grid::GetCols()-1 - cTmp; return; case 'N': row = Grid::GetRows()-1 - cTmp; col = rTmp; return; case 'S': row = cTmp; col = Grid::GetCols()-1 - rTmp; return; } } }; // The ElementGrid is used for the board and has a hidden toroidal behaviour. // So things that move too far right can appear on the left. // Similarly for top and bottom. // It's a lazy way of avoiding bounds checking during development. // More importantly, it makes the neighbouring element concept simpler // since every element will always have non-null neighbour pointers. class ElementGrid : public Grid { public: ElementGrid() : Grid() {} ElementGrid(const ElementGrid& o) : Grid(o) { *this = o; } virtual ~ElementGrid() override {} ElementGrid& operator=(const ElementGrid& o) { Grid::operator=(o); return *this; } bool operator==(const ElementGrid& o) const { return Grid::operator==(o); } bool operator!=(const ElementGrid& o) const { return Grid::operator!=(o); } void MakeToroid(int& row, int& col) const // Make co-ordinates wrap around at grid edges { assert( GetRows() > 0 ); if ( GetRows() > 0 ) { while ( row < 0 ) { row += GetRows(); } while ( row >= GetRows() ) { row -= GetRows(); } } assert( GetCols() > 0 ); if ( GetCols() > 0 ) { while ( col < 0 ) { col += GetCols(); } while ( col >= GetCols() ) { col -= GetCols(); } } } void MakeToroid(int& lyr, int& row, int& col) const // Make co-ordinates wrap around at grid edges { assert( GetLyrs() > 0 ); if ( GetLyrs() > 0 ) { while ( lyr < 0 ) { lyr += GetLyrs(); } while ( lyr >= GetLyrs() ) { lyr -= GetLyrs(); } } MakeToroid(row, col); } Element* Get(int lyr, int row, int col) const { MakeToroid(lyr, row, col); // Make co-ordinates wrap around at grid edges return Grid::Get(lyr, row, col); } void Pan(int iDown, int iRight) // Input arguments can be +ve or -ve. { if ( iDown == 0 && iRight == 0 ) return; ElementGrid tmp(*this); // Make a temporary copy of this grid for (int iLyr = 0, lyrs = GetLyrs(); iLyr < lyrs; iLyr++) for (int iRow = 0, rows = GetRows(); iRow < rows; iRow++) for (int iCol = 0, cols = GetCols(); iCol < cols; iCol++) Set(iLyr, iRow, iCol, *(tmp.Get(iLyr, iRow - iDown, iCol - iRight))); // ElementGrid::Get() accounts for toroidal behaviour } bool CopyFrom(const TrackElementGrid& o) { if ( o.GetLyrs() != GetLyrs() || o.GetRows() != GetRows() || o.GetCols() != GetCols() ) return false; for (int i = 0, iSize = GetSize(); i < iSize; i++) GetAt(i)->TrackElement::operator=(*o.GetAtConst(i)); return true; } void CopyTo(TrackElementGrid& o) const { if ( o.GetLyrs() != GetLyrs() || o.GetRows() != GetRows() || o.GetCols() != GetCols() ) o.Allocate(GetLyrs(), GetRows(), GetCols()); for (int i = 0, iSize = GetSize(); i < iSize; i++) o.GetAt(i)->operator=(*GetAtConst(i)); } size_t GetNumNodeIds() const { std::set nodeIds; for (int i = 0, iSize = GetSize(); i < iSize; i++) { const int& iNodeId = GetAtConst(i)->GetNodeId(); if ( iNodeId != BAD_NODEID ) nodeIds.insert(iNodeId); } return nodeIds.size(); } }; VeroRoute/libraries/gEDA/veroroute_linear/Generic_SIP10.sym000644 001750 001750 00000003756 13515171161 024032 0ustar00alexalex000000 000000 v 20130925 2 T 300 0 8 10 0 0 0 0 1 numslots=0 B 300 0 1400 4000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 0 3800 300 3800 1 0 0 { T 205 3845 5 10 1 1 0 6 1 pinnumber=1 T 200 3800 5 10 0 1 0 0 1 pinseq=1 T 355 3795 5 10 0 1 0 0 1 pinlabel=1 T 200 3800 5 10 0 1 0 0 1 pintype=pas } P 0 3400 300 3400 1 0 0 { T 205 3445 5 10 1 1 0 6 1 pinnumber=2 T 200 3400 5 10 0 1 0 0 1 pinseq=2 T 355 3345 5 10 0 1 0 0 1 pinlabel=2 T 200 3400 5 10 0 1 0 0 1 pintype=pas } P 0 3000 300 3000 1 0 0 { T 205 3045 5 10 1 1 0 6 1 pinnumber=3 T 200 3000 5 10 0 1 0 0 1 pinseq=3 T 355 2945 5 10 0 1 0 0 1 pinlabel=3 T 200 3000 5 10 0 1 0 0 1 pintype=pas } P 0 2600 300 2600 1 0 0 { T 205 2645 5 10 1 1 0 6 1 pinnumber=4 T 200 2600 5 10 0 1 0 0 1 pinseq=4 T 355 2545 5 10 0 1 0 0 1 pinlabel=4 T 200 2600 5 10 0 1 0 0 1 pintype=pas } P 0 2200 300 2200 1 0 0 { T 205 2245 5 10 1 1 0 6 1 pinnumber=5 T 200 2200 5 10 0 1 0 0 1 pinseq=5 T 355 2145 5 10 0 1 0 0 1 pinlabel=5 T 200 2200 5 10 0 1 0 0 1 pintype=pas } P 0 1800 300 1800 1 0 0 { T 205 1845 5 10 1 1 0 6 1 pinnumber=6 T 200 1800 5 10 0 1 0 0 1 pinseq=6 T 355 1745 5 10 0 1 0 0 1 pinlabel=6 T 200 1800 5 10 0 1 0 0 1 pintype=pas } P 0 1400 300 1400 1 0 0 { T 205 1445 5 10 1 1 0 6 1 pinnumber=7 T 200 1400 5 10 0 1 0 0 1 pinseq=7 T 355 1345 5 10 0 1 0 0 1 pinlabel=7 T 200 1400 5 10 0 1 0 0 1 pintype=pas } P 0 1000 300 1000 1 0 0 { T 205 1045 5 10 1 1 0 6 1 pinnumber=8 T 200 1000 5 10 0 1 0 0 1 pinseq=8 T 355 945 5 10 0 1 0 0 1 pinlabel=8 T 200 1000 5 10 0 1 0 0 1 pintype=pas } P 0 200 300 200 1 0 0 { T 205 245 5 10 1 1 0 6 1 pinnumber=10 T 200 200 5 10 0 1 180 6 1 pinseq=10 T 355 195 5 10 0 1 0 0 1 pinlabel=10 T 200 200 5 10 0 1 180 6 1 pintype=pas } P 0 600 300 600 1 0 0 { T 205 645 5 10 1 1 0 6 1 pinnumber=9 T 200 600 5 10 0 1 180 6 1 pinseq=9 T 355 595 5 10 0 1 0 0 1 pinlabel=9 T 200 600 5 10 0 1 180 6 1 pintype=pas } T 1200 4155 5 10 1 1 0 0 1 device=Name T 300 4155 8 10 1 1 0 0 1 refdes=U? T 1600 2055 8 10 0 1 0 0 1 footprint=SIP10 T 1900 1845 8 10 0 1 0 0 1 description=Generic 10 Pin SIP VeroRoute/libraries/gEDA/veroroute_passive/Capacitor_Electrolytic_NP_200mil.sym000644 001750 001750 00000001340 13515171161 030074 0ustar00alexalex000000 000000 v 20130925 2 T 200 700 5 10 0 0 0 0 1 numslots=0 P 200 700 400 700 1 0 0 { T 350 750 5 8 1 1 0 6 1 pinnumber=1 T 350 750 5 8 0 0 0 6 1 pinseq=1 T 350 750 5 8 0 0 0 6 1 pinlabel=1 T 350 750 5 8 0 0 0 6 1 pintype=pas } P 1100 700 900 700 1 0 0 { T 950 750 5 8 1 1 0 0 1 pinnumber=2 T 950 750 5 8 0 0 0 0 1 pinseq=2 T 950 750 5 8 0 0 0 0 1 pinlabel=2 T 950 750 5 8 0 0 0 0 1 pintype=pas } L 600 900 600 500 3 0 0 0 -1 -1 L 900 700 700 700 3 0 0 0 -1 -1 L 600 700 400 700 3 0 0 0 -1 -1 A 1400 700 700 165 30 3 0 0 0 -1 -1 T 500 300 5 10 1 1 0 0 1 device=1u T 500 1000 8 10 1 1 0 0 1 refdes=C? T 500 700 8 10 0 0 0 0 1 footprint=CAP_ELECTRO_200_NP T 500 700 8 10 0 0 0 0 1 description=Non-Polarised Electrolytic Capacitor (200 mil diameter) VeroRoute/libraries/gEDA/veroroute_passive/Resistor_200mil.sym000644 001750 001750 00000001141 13515171161 024661 0ustar00alexalex000000 000000 v 20130925 2 T 0 400 5 10 0 0 0 0 1 numslots=0 P 0 400 150 400 1 0 0 { T 100 450 5 8 0 1 0 0 1 pinnumber=1 T 100 450 5 8 0 0 0 0 1 pinseq=1 T 100 450 5 8 0 0 0 0 1 pinlabel=1 T 100 450 5 8 0 0 0 0 1 pintype=pas } P 900 400 750 400 1 0 0 { T 800 450 5 8 0 1 0 0 1 pinnumber=2 T 800 450 5 8 0 0 0 0 1 pinseq=2 T 800 450 5 8 0 0 0 0 1 pinlabel=2 T 800 450 5 8 0 0 0 0 1 pintype=pas } B 150 300 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 T 200 50 5 10 1 1 0 0 1 device=100k T 300 600 8 10 1 1 0 0 1 refdes=R? T 100 400 8 10 0 0 0 0 1 footprint=RESISTOR2 T 100 400 8 10 0 0 0 0 1 description=Resistor (200 mil length) VeroRoute/libraries/gEDA/veroroute_transistor/NPN_BC639.sym000644 001750 001750 00000001562 13515171161 023772 0ustar00alexalex000000 000000 v 20130925 2 T 0 500 5 10 0 0 0 0 1 numslots=0 P 0 500 200 500 1 0 0 { T 100 550 5 6 1 1 0 0 1 pinnumber=3 T 100 550 5 6 0 0 0 0 1 pinseq=3 T 100 550 5 6 0 0 0 0 1 pinlabel=3 T 100 550 5 6 0 0 0 0 1 pintype=pas } P 500 1000 500 800 1 0 0 { T 400 850 5 6 1 1 0 0 1 pinnumber=2 T 400 850 5 6 0 0 0 0 1 pinseq=2 T 400 850 5 6 0 0 0 0 1 pinlabel=2 T 400 850 5 6 0 0 0 0 1 pintype=pas } P 500 200 500 0 1 0 1 { T 400 50 5 6 1 1 0 0 1 pinnumber=1 T 400 50 5 6 0 0 0 0 1 pinseq=1 T 400 50 5 6 0 0 0 0 1 pinlabel=1 T 400 50 5 6 0 0 0 0 1 pintype=pas } L 200 650 500 800 3 0 0 0 -1 -1 L 200 350 500 200 3 0 0 0 -1 -1 L 200 800 200 200 3 0 0 0 -1 -1 H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5 M 403,209 L 501,200 L 431,273 L 425,240 z T 600 700 5 10 1 1 0 0 1 device=BC639 T 600 400 8 10 1 1 0 0 1 refdes=Q? T 600 400 8 10 0 0 0 0 1 footprint=TO92 T 600 400 8 10 0 0 0 0 1 description=NPN Transistor VeroRoute/libraries/gEDA/veroroute_bbd/MN3009.sym000644 001750 001750 00000003277 13515171160 021702 0ustar00alexalex000000 000000 v 20130925 2 T 300 400 8 10 0 0 0 0 1 numslots=0 B 300 400 1800 1800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 0 1000 300 1000 1 0 0 { T 205 1045 5 10 1 1 0 6 1 pinnumber=1 T 200 1000 5 10 0 0 0 0 1 pinseq=1 T 355 945 5 10 1 1 0 0 1 pinlabel=GND T 200 1000 5 10 0 0 0 0 1 pintype=pwr } P 0 1600 300 1600 1 0 0 { T 205 1645 5 10 1 1 0 6 1 pinnumber=3 T 200 1600 5 10 0 0 0 0 1 pinseq=3 T 355 1545 5 10 1 1 0 0 1 pinlabel=IN T 200 1600 5 10 0 0 0 0 1 pintype=in } P 900 2500 900 2200 1 0 0 { T 850 2295 5 10 1 1 90 0 1 pinnumber=5 T 900 2400 5 10 0 0 0 0 1 pinseq=5 T 950 2145 5 10 1 1 90 6 1 pinlabel=VDD T 900 2400 5 10 0 0 0 0 1 pintype=pwr } P 1500 2500 1500 2200 1 0 0 { T 1450 2295 5 10 1 1 90 0 1 pinnumber=4 T 1500 2400 5 10 0 0 0 0 1 pinseq=4 T 1550 2145 5 10 1 1 90 6 1 pinlabel=VGG T 1500 2400 5 10 0 0 0 0 1 pintype=pas } P 2400 1600 2100 1600 1 0 0 { T 2195 1645 5 10 1 1 0 0 1 pinnumber=8 T 2500 1600 5 10 0 0 0 0 1 pinseq=8 T 2045 1545 5 10 1 1 0 6 1 pinlabel=OUT2 T 2500 1600 5 10 0 0 0 0 1 pintype=out } P 2400 1000 2100 1000 1 0 0 { T 2195 1045 5 10 1 1 0 0 1 pinnumber=7 T 2500 1000 5 10 0 0 0 0 1 pinseq=7 T 2045 945 5 10 1 1 0 6 1 pinlabel=OUT1 T 2500 1000 5 10 0 0 0 0 1 pintype=out } P 900 100 900 400 1 0 0 { T 850 305 5 10 1 1 90 6 1 pinnumber=2 T 900 100 5 10 0 0 0 0 1 pinseq=2 T 950 455 5 10 1 1 90 0 1 pinlabel=CP1 T 900 100 5 10 0 0 0 0 1 pintype=clk } P 1500 100 1500 400 1 0 0 { T 1450 305 5 10 1 1 90 6 1 pinnumber=6 T 1500 100 5 10 0 0 0 0 1 pinseq=6 T 1550 455 5 10 1 1 90 0 1 pinlabel=CP2 T 1500 100 5 10 0 0 0 0 1 pintype=clk } T 1900 2455 5 10 1 1 0 0 1 device=MN3009 T 1900 2655 8 10 1 1 0 0 1 refdes=U? T 1600 2055 8 10 0 1 0 0 1 footprint=DIP8 T 1900 1845 8 10 0 1 0 0 1 description=256-Stage BBD VeroRoute/tutorials/tutorial_20.vrt000644 001750 001750 00000221763 14015257214 017677 0ustar00alexalex000000 000000 0 іTUTORIAL 20 - FLYING WIRES Regular wires in VeroRoute behave in a certain way. In particular... 1) They do not have a netlist value of their own, but rather inherit the netlist value of the grid square where they are placed. 2) They can only be placed horizontally or vertically. 3) They cannot cross other parts but can be placed in the gap between pins of an IC socket. 4) There are options to allow 2 wires to share a hole, and for 2 wires to cross or overlay one another. "Flying wires" in VeroRoute are not actual objects, but rather automatically generated connections between a set of "flying wire pads". So to create "flying wires" you must place a set of "flying wire pads" down on the grid and paint them with the same netlist value. VeroRoute treats all "flying wire pads" with the same netlist value as being electrically connected, and it automatically generates a daisy chain of flying wires between them to indicate that. Look at the example circuit. Flying wires are drawn in the same style as regular wires except they have white stripes instead of a solid color. Note that the "Broken Nodes" list for the circuit is empty meaning there are no open circuits. Now go the View menu and choose "Hide Flying Wires". The "Broken Nodes" list remains empty because the flying wire pads have an implicit electrical connection regardless of whether you choose to draw the flying wires to screen. Flying wires are always hidden in Mono and PCB modes. Now go the the View menu and choose "Show Flying Wires". Click on one of the "flying wire pad" objects (e.g. the green pad to the right of D5 near the top of the circuit) and drag it to different places in the view. You will see the daisy chain of flying wires being rebuilt according to where the pad is placed. џџџџџџџџZ. 2? џџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ@Wџџџџџџџџџџџџџџџџџџџџџџџџџ*@Wџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ Dџџџџџџџџџџ џџџџџџџџџџ џџџџџџџџџ*Zџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ D]џџџџџџ џџџџџџџџџ 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WF(12ПьЬЬЬЬЬЭ?ьЬЬЬЬЬЭПй™™™™™š?й™™™™™š@V€џ PПьЬЬЬЬЬЭ?ьЬЬЬЬЬЭПй™™™™™š?й™™™™™š@V€џ Pџє1C1010nCCeramicCAP_CERAMICEF(12Піffffff?іffffffПй™™™™™š?й™™™™™š@V€џ PПіffffff?іffffffПй™™™™™š?й™™™™™š@V€џ Pd;5OutPadPadPADWF(1ПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпnSPad"Pad (Flying Wire)PAD_FLYINGWIRE WF(1ПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпџџ,TR383k6RResistorRESISTORWF("1)2ПђсGЎzс?ђсGЎzсПдzсGЎ{?дzсGЎ{@V€‚Я§П§ИQы…П№Qы…ИRПй™™™™™š?й™™™™™™@V€‚Я§?№Qы…ИR?§ИQы…Пй™™™™™š?й™™™™™™@V€‚Я§ПђсGЎzс?ђсGЎzсПдzсGЎ{ПдzсGЎ{@V€‚Я§ПђсGЎzс?ђсGЎzс?дzсGЎ{?дzсGЎ{@V€‚Я§П§ИQы…П№Qы…ИRПй™™™™™š?й™™™™™™@J€РJ€‚Я§?№Qы…ИR?§ИQы…Пй™™™™™š?й™™™™™™@m @_Р‚Я§џШ= Wire3 Wire3WireWire WF(12П№?№ПЙ™™™™™š?Й™™™™™š@V€пџџП№?№ПЙ™™™™™š?Й™™™™™š@V€пџџnlPad"Pad (Flying Wire)PAD_FLYINGWIRE WF(1ПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпџџ, R810kRResistorRESISTOR EF( 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Copyright (C) 2017 Alex Lawrow ( dralx@users.sourceforge.net ) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #pragma once #include "Common.h" #include // Class to transform a QPointF (i.e. translate/rotate it w.r.t. the origin) enum class TRANSFORM { NONE = 0, SCALE, TRANSLATE, ROTATE }; struct Transform { Transform(TRANSFORM eType, qreal a = 0, qreal b = 0) : m_eType(eType), m_A(a), m_B(b) {} ~Transform() {} Transform(const Transform& o) { *this = o; } Transform& operator=(const Transform& o) { m_eType = o.m_eType; m_A = o.m_A; m_B = o.m_B; return *this; } void Do(QPointF& o) const // Transform the passed in point { qreal dRadians(0), C(0), S(0); const qreal x = o.x(); // Take a copy (not a reference) const qreal y = o.y(); // Take a copy (not a reference) switch( m_eType ) { case TRANSFORM::SCALE: o.setX(x * m_A); o.setY(y * m_B); return; case TRANSFORM::TRANSLATE: o.setX(x + m_A); o.setY(y + m_B); return; case TRANSFORM::ROTATE: dRadians = m_A * M_PI / 180; C = cos(dRadians); S = sin(dRadians); o.setX(x*C - y*S); o.setY(x*S + y*C); return; default: assert(m_eType == TRANSFORM::NONE); return; } } const TRANSFORM& GetType() const { return m_eType; } private: TRANSFORM m_eType = TRANSFORM::TRANSLATE; // Transform type qreal m_A = 0; // Parameter 1 qreal m_B = 0; // Parameter 2 }; VeroRoute/examples/README.txt000644 001750 001750 00000000221 13515171160 016243 0ustar00alexalex000000 000000 This folder contains a circuit schematic and its corresponding netlist. The vrt files are veroboard and PCB layouts using the imported netlist. VeroRoute/Src/images/mid.png000644 001750 001750 00000000350 14064443172 016212 0ustar00alexalex000000 000000 ‰PNG  IHDR йsВbKGDџ‡ЬП pHYs з зB(›xtIMEх„aAyIDATHЧн•С Р0Cc)tз§џіvqзQД‚–Ѓ„цЕRXRx’Еа@JœКFнiƒщM$Xg*ѓѾu*ўРйB|^ў…ЮНbDL[б]пFхxПТФф"{Щь.H(_ЪПёзЉz*WoІ/Зѓ ЪZ M]YIENDЎB`‚VeroRoute/libraries/gEDA/veroroute_transistor/NPN_BC213.sym000644 001750 001750 00000001562 13515171161 023756 0ustar00alexalex000000 000000 v 20130925 2 T 0 500 5 10 0 0 0 0 1 numslots=0 P 0 500 200 500 1 0 0 { T 100 550 5 6 1 1 0 0 1 pinnumber=2 T 100 550 5 6 0 0 0 0 1 pinseq=2 T 100 550 5 6 0 0 0 0 1 pinlabel=2 T 100 550 5 6 0 0 0 0 1 pintype=pas } P 500 1000 500 800 1 0 0 { T 400 850 5 6 1 1 0 0 1 pinnumber=3 T 400 850 5 6 0 0 0 0 1 pinseq=3 T 400 850 5 6 0 0 0 0 1 pinlabel=3 T 400 850 5 6 0 0 0 0 1 pintype=pas } P 500 200 500 0 1 0 1 { T 400 50 5 6 1 1 0 0 1 pinnumber=1 T 400 50 5 6 0 0 0 0 1 pinseq=1 T 400 50 5 6 0 0 0 0 1 pinlabel=1 T 400 50 5 6 0 0 0 0 1 pintype=pas } L 200 650 500 800 3 0 0 0 -1 -1 L 200 350 500 200 3 0 0 0 -1 -1 L 200 800 200 200 3 0 0 0 -1 -1 H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5 M 403,209 L 501,200 L 431,273 L 425,240 z T 600 700 5 10 1 1 0 0 1 device=BC213 T 600 400 8 10 1 1 0 0 1 refdes=Q? T 600 400 8 10 0 0 0 0 1 footprint=TO92 T 600 400 8 10 0 0 0 0 1 description=NPN Transistor VeroRoute/tutorials/tutorial_12.vrt000644 001750 001750 00000115702 13646427476 017715 0ustar00alexalex000000 000000 (”TUTORIAL 12 - AUTO-ROUTING WIRING UP PARTS QUICKLY The quick way of wiring parts is to just paint the pins and let the auto-routing draw the tracks for you. The auto-routing is interactive. It is still being developed and will not always manage to route the whole circuit. When it fails to do so, the NodeIDs with open-circuits will be listed in the "Broken" list of the Control dialog. While auto-routing is enabled, the auto-routed tracks are shown in color but with thin, white, diamond-hatched lines. This is to differentiate them from any points that have been manually painted by you (the user). User-painted points are shown without the diamond-hatched lines. The routing algorithm will not overwrite or modify any of the user-painted points while it is running. The auto-routing is dynamic and runs every time the circuit is modified (e.g. every time you paint or erase grid points or manipulate parts). This makes it possible to work interactively with the routing algorithm. For example, if the routing algorithm does something like lay a track that blocks an obvious connection between nearby points, then you can simply paint in the desired connection manually and the algorithm will be forced to re-route around it. If a pair of pins are connected by a track that has been painted manually (from one pin to the other) then the auto-router will not autoroute a new track between those pins. Try the following exercise... The top circuit has already been wired up. Now try and copy that wiring on the bottom set of parts. Auto-routing has been switched on. All you need to do is paint the component pins on the bottom. The tracks may not go where you want them, but don't worry about that. You can move parts if you want, and the auto-routing will re-route the tracks. See what happens as you check and uncheck the "On" box during auto-routing. Note that it is recommended to use "Fast" auto-routing by default. Disabling the fast mode makes the algorithm try harder to route any broken nodes, but it may not always make an improvement and can be 10 times slower to run. In order to commit the auto-routed tracks to the board, you need to hit the "Paste" button. The "Tidy" button is only enabled when auto-routing is turned off and there are no Broken nodes. Hitting "Tidy" will then try to re-route the circuit and remove any points that are not considered to provide a useful connection. Since this can erase user-painted tracks and replace them with auto-routed tracks, it is not functionality that will be used often. The "Wipe All Tracks" button can be hit at any time. This will disable auto-routing and wipe all colored points on the board except for component pins. If you have any highlighted rectangular areas on the screen (created by holding down "R" and drawing with the mouse) then the wipe is restricted to those areas. Also, when using "Vero" style, hitting the "Paste" button will automatically fill-out the board with strips with breaks in the required places.џџџџџџџџZ. 29 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1ПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпџџ,R4390RResistorRESISTORNF(12ПђсGЎzс?ђсGЎzсПдzсGЎ{?дzсGЎ{@V€‚Я§П§ИQы…П№Qы…ИRПй™™™™™š?й™™™™™™@V€‚Я§?№Qы…ИR?§ИQы…Пй™™™™™š?й™™™™™™@V€‚Я§ПђсGЎzс?ђсGЎzсПдzсGЎ{ПдzсGЎ{@V€‚Я§ПђсGЎzс?ђсGЎzс?дzсGЎ{?дzсGЎ{@V€‚Я§П§ИQы…П№Qы…ИRПй™™™™™š?й™™™™™™@J€РJ€‚Я§?№Qы…ИR?§ИQы…Пй™™™™™š?й™™™™™™@m @_Р‚Я§џє C2150nCCeramicCAP_CERAMICWF(1 2Піffffff?іffffffПй™™™™™š?й™™™™™š@V€џ PПіffffff?іffffffПй™™™™™š?й™™™™™š@V€џ Pџє C1150nCCeramicCAP_CERAMICWF( 12Піffffff?іffffffПй™™™™™š?й™™™™™š@V€џ PПіffffff?іffffffПй™™™™™š?й™™™™™š@V€џ PdPad49VPadPadPADWF(1ПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпПмЬЬЬЬЬЭ?мЬЬЬЬЬЭПмЬЬЬЬЬЭ?мЬЬЬЬЬЭ@V€џџпџџ,R2100kRResistorRESISTORNF(12ПђсGЎzс?ђсGЎzсПдzсGЎ{?дzсGЎ{@V€‚Я§П§ИQы…П№Qы…ИRПй™™™™™š?й™™™™™™@V€‚Я§?№Qы…ИR?§ИQы…Пй™™™™™š?й™™™™™™@V€‚Я§ПђсGЎzс?ђсGЎzсПдzсGЎ{ПдzсGЎ{@V€‚Я§ПђсGЎzс?ђсGЎzс?дzсGЎ{?дzсGЎ{@V€‚Я§П§ИQы…П№Qы…ИRПй™™™™™š?й™™™™™™@J€РJ€‚Я§?№Qы…ИR?§ИQы…Пй™™™™™š?й™™™™™™@m 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TracksWF(џџџ€џџџ€џџџ€џџџ€џџџџџџџџF#џ џ џ џ џ џ џ џ џ џ џ џ џ џ џ џ Р@Р@@V€џVeroRoute/libraries/gEDA/veroroute_linear/Generic_DIP12.sym000644 001750 001750 00000004560 13515171161 024007 0ustar00alexalex000000 000000 v 20130925 2 T 300 0 8 10 0 0 0 0 1 numslots=0 B 300 0 1400 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 0 2200 300 2200 1 0 0 { T 205 2245 5 10 1 1 0 6 1 pinnumber=1 T 200 2200 5 10 0 1 0 0 1 pinseq=1 T 355 2195 5 10 0 1 0 0 1 pinlabel=1 T 200 2200 5 10 0 1 0 0 1 pintype=pas } P 0 1800 300 1800 1 0 0 { T 205 1845 5 10 1 1 0 6 1 pinnumber=2 T 200 1800 5 10 0 1 0 0 1 pinseq=2 T 355 1745 5 10 0 1 0 0 1 pinlabel=2 T 200 1800 5 10 0 1 0 0 1 pintype=pas } P 0 1400 300 1400 1 0 0 { T 205 1445 5 10 1 1 0 6 1 pinnumber=3 T 200 1400 5 10 0 1 0 0 1 pinseq=3 T 355 1345 5 10 0 1 0 0 1 pinlabel=3 T 200 1400 5 10 0 1 0 0 1 pintype=pas } P 0 1000 300 1000 1 0 0 { T 205 1045 5 10 1 1 0 6 1 pinnumber=4 T 200 1000 5 10 0 1 0 0 1 pinseq=4 T 355 945 5 10 0 1 0 0 1 pinlabel=4 T 200 1000 5 10 0 1 0 0 1 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T 1600 2055 8 10 0 1 0 0 1 footprint=DIP12 T 1900 1845 8 10 0 1 0 0 1 description=Generic 12 Pin DIP8 VeroRoute/libraries/gEDA/veroroute_transistor/PNP_BC309.sym000644 001750 001750 00000001562 13515171161 023766 0ustar00alexalex000000 000000 v 20130925 2 T 0 500 5 10 0 0 0 0 1 numslots=0 P 0 500 200 500 1 0 0 { T 100 550 5 6 1 1 0 0 1 pinnumber=2 T 100 550 5 6 0 0 0 0 1 pinseq=2 T 100 550 5 6 0 0 0 0 1 pinlabel=2 T 100 550 5 6 0 0 0 0 1 pintype=pas } P 500 1000 500 800 1 0 0 { T 400 850 5 6 1 1 0 0 1 pinnumber=1 T 400 850 5 6 0 0 0 0 1 pinseq=1 T 400 850 5 6 0 0 0 0 1 pinlabel=1 T 400 850 5 6 0 0 0 0 1 pintype=pas } P 500 200 500 0 1 0 1 { T 400 50 5 6 1 1 0 0 1 pinnumber=3 T 400 50 5 6 0 0 0 0 1 pinseq=3 T 400 50 5 6 0 0 0 0 1 pinlabel=3 T 400 50 5 6 0 0 0 0 1 pintype=pas } L 200 650 500 800 3 0 0 0 -1 -1 L 200 350 500 200 3 0 0 0 -1 -1 L 200 800 200 200 3 0 0 0 -1 -1 H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5 M 297,341 L 199,350 L 269,277 L 275,310 z T 600 700 5 10 1 1 0 0 1 device=BC309 T 600 400 8 10 1 1 0 0 1 refdes=Q? T 600 400 8 10 0 0 0 0 1 footprint=TO92 T 600 400 8 10 0 0 0 0 1 description=PNP Transistor VeroRoute/libraries/TinyCAD/000775 001750 001750 00000000000 13515171160 016145 5ustar00alexalex000000 000000 VeroRoute/Src/images/grid.png000644 001750 001750 00000000261 13734457550 016377 0ustar00alexalex000000 000000 ‰PNG  IHDR йsВbKGDЊ#2 pHYsФФ•+tIMEф  0’C~†BIDATHЧэ’1 ФŠсџ_ЦХнT&ЭнжЅЄPœAD‚С)ћА1[ЗЙU_( |=nјёЉu д:јЊƒИћ@%ї;„wIENDЎB`‚VeroRoute/CHANGELOG.txt000644 001750 001750 00000061147 14066654505 015010 0ustar00alexalex000000 000000 V2.15 Improvement: Added background brightness to Rendering Options. V2.14 Improvement: Added vertical alignment options to text boxes. V2.13 Bug fix: Code to fix corruption can mess up competing diagonals on boards that are OK. V2.12 Bug fix: Corrected tab order in Rendering Options and Component Editor dialogs. Updated Tutorial 18 with info on applying pad offsets. V2.11 Bug fix: The routing changes in V2.09 introduced a bug in the connectivity checking of layouts with wires, so fully connected nets that use wires could sometimes be wrongly listed as "Bad Nodes". V2.10 Bug fix: Show closest tracks did not draw all locations due to rounding errors. Bug fix: Flying wires not drawn properly to offset pads. Improvement: If all pads on a component are shifted by the same amount, then give the component outline and text the same shift. Improvement: Show rectangular area sizes and pad offsets in both mil and mm. Improvement: Allow pad offsets to change in 1 mil steps instead of 5 mil. New feature: Added distance tool for measuring distance between holes/grid points (to help set pad offsets) V2.09 Improvement: Routing algorithm speed increased. V2.08 Bug fix: Autorouting in non-fast mode corrupts how adjacent nodeIDs on the grid are tracked, leading to many adjacent nets being given the same color. Improvement: Speed up how flying wires are handled during connectivity checking. Improvement: Speed up code for tracking adjacent nodeIDs on the grid. Improvement: Speed up routing in non-fast mode by 5% to 10%. Improvement: Allow "Paste" when auto-routing to be restricted to grey areas. Improvement: Moving/rotating grey areas while auto-routing will ignore auto-routed tracks in the grey areas instead of pasting them. V2.07 Improvement: Faster algorithm for building the list of broken nodes. Improvement: Copying a part with no name and no value should produce a part with no name and no value. New feature: Flying wires. Automatically generated between "Pad (Flying Wire)" objects. V2.06 Bug fix: In Rendering Options, the "Show closest tracks" box was not being hidden when minimum separation was same as Gap size. Bug fix. In Fat Tracks mode with diagonals, tracks in the view were not all of correct width, but the ones in Gerber export were. Bug fix: In Fat Tracks mode with diagonals, the track separation algorithm was not handling all cases properly. Bug fix: In Fat Tracks mode, Gerber export should create an aperture for pads even if there are no parts in the circuit. Improvement: Allow reset pin layer preference ("T" + right button) while moving mouse instead of having to do single clicks. V2.05 Bug fix: Code for filling parts with color not correctly handling shape transformations. Bug fix: Track separation info in the Rendering dialog not updating when auto-routing toggled. Bug fix: Components with lines outside the footprint area could be rendered off screen leading to an invalid set of Gerber files (e.g. GTO file having points outside the boundary in the GKO file). Improvement: Total rewrite of minimum track separation for improved accuracy. Improvement: Show points for all layers when displaying locations of minimum track separation. New feature: In PCB mode, individual pad locations can be shifted by up to 50 mil using Ctrl + Arrow keys. V2.04 Bug fix: Since 2.02, VeroRoute freezes if the grid is made 1 column wide. Omit deprecated G codes from Gerber export, and allow Gerber export in mm or inches. Allow circuit panning/grid resize by grabbing the grid with the right mouse button (ctrl key optional). Improve GUI behaviour in Tutorials by passing key presses from the Info dialog to the main window. V2.03 Bug fix: Wire rendering broken in 2.02. New feature. Can specify layer preference on component pins of 2-layer PCBs. Updated tutorials. V2.02 Bug fix: Fill slider should be enabled when track slider is set to Off. Bug fix: Calculation of minimum track separation was not correct when using fat tracks style. Bug fix: Changed render order in Color/Mono mode to fix issues with how custom sizes pads are drawn. Track width changes: Minimum allowed track widths lowered to 4 mil. Minimum allowed via hole lowered to 8 mil. Minimum allowed via pad lowered to 16 mil. Maximum custom pad size increased to 130 mil. Maximum custom hole size increased to 100 mil. New feature: Add ability to show locations of minimum track separation. Updated tutorials. V2.01 Bug fix: Chains of wires sharing holes sometimes not colored completely. Added ability to define custom pad/hole size in component editor. Added ability to add veroboard labels (numbers or letters). Improved algorithm for solder bridges. Don't show a solder bridge if a wire is already doing that job. V2.00 Bug fix: Poor-man's 2-layer Gerber export was not handling crossing wires. Bug fix: Isolated nodes were rendered to Gerber with pad-width instead of track-width. Bug fix: Isolated nodes were rendered to top layer for poor-man's 2-layer Gerber export. Improvement: Allow TAB to change focus of dialog controls. Improvement: Reworked some icons that did not work well with dark themes. Removed menu item to fix corruption. Old corrupted VRTS are now auto-fixed on load. V1.99 Code changes to help prevent layout from becoming corrupted. V1.98 Put in extra checks to stop potential crashes arising from a corrupted layout. Added file menu option to fix a corrupted layout. V1.97 Bug fix: In Color mode, diagonal track portions were drawn too long if using custom track color. Disabled code for drawing extra thermal relief tags (so a filled PCB will be easier to solder). V1.96 New feature: In Color mode, color each wire according to its NodeId. V1.95 Bug fix: Thermal relief tags not calculated properly for pads with custom size. New feature: Allow user to specify a color for any NodeID. Improvement: Show info on Bad/Floating nodes in a single list. For consistency between view types, draw hashed lines for broken connections in red instead of yellow. V1.94 Bug fix: When ground-filling with no specified nodeId, do not draw thermal relief tags to unassigned pins. New feature: Find parts in layout by Name or Value. Improvement: Made Rendering Options dialog better handle 11pt font. V1.93 Make control dialog better handle large font. Draw pads for unassigned pins in Mono/PCB mode. V1.92 Bug fix: Delete selected template would sometimes remove wrong template. V1.91 Bug fix: Allow 2-pin DIPs. Bug fix: Mouse click not always selecting most relevant shape in component editor mode. Improvement: Draw some parts (e.g. resistors/diodes/DIPs) differently in PCB mode when appropriate. V1.90 Bug fix: While auto-routing, unpainting the board under a part would not always let it fall into place. Bug fix: Hole-usage was not handled properly for non-wires. Improvement: Increase max allowed hole size for parts from 40 mil to 50 mil. V1.89 Bug fix: Gerber export in V1.88 was writing unusable drill file, and not handling variable pad/hole widths correctly. V1.88 Roll back of change made in V1.85: Top solder mask now works in same way as bottom solder mask. Bug fix: Fix problem with docked dialogs passing mouse clicks to the main window. Improvement: Various minor fixes, improvements and simplificatons to Gerber Export code. Improvement: Changed diode cathode marking so it is less likely to be erased on a PCB. Improvement: Show actual minimum track separation (instead of the guaranteed minimum). New feature: Show minimum ground fill width to help avoid isolated ground "islands". New feature: Allow custom pad and hole sizes to be set on each part. V1.87 Bug fix: 300 mil electrolytic cap was missing line marking negative side. Improvement: When modifying shapes in component editor, allow unit steps with the mouse wheel. Improvement: Allow flipped views in PCB mode but don't allow export/editing when flipped. Lots of minor GUI tweaks such as disabling certain buttons according to display mode. Added the Bourns 3362 series to the set of trimmers in the Templates dialog. V1.86 Bug fix: V1.85 was sometimes hiding pin outlines (e.g. when track slider was set to Off). Bug fix: Switching to Component Editor mode from PCB mode gave black background. Bug fix: Placing a wire in 2-layer mode did not handle both wire ends properly. Improvement: Added button to Templates dialog to save all templates to a VRT file. Improvement: For ground-fills, auto-generate additional tags for thermal reliefs. Functionality change: To avoid track breaks, markers in Mono mode only make holes in ground-fills. Functionality change: Disabled show/hide of docked widgets by right mouse-click on menu bar. Added command line options (-h, --help, -v, --version). Added manpage as part of unix installation. V1.85 Bug fix: Refresh problem. Broken and Floating lists could show zombie entries when the control dialog is docked. Bug fix: Rendering problem. In Mono and Color modes, some zoom levels would leave gaps between pixmaps and draw offset diagonals. Bug fix: In Mono and Color modes, it was not possible to set via-pad and via-hole sizes. Improvement: Allow larger zoom level. Improvement: To avoid problems with some PCB companies, made the top solder mask cover most (but not all) of each pad/via. Improvement: When rendering the top layer in PCB mode, make it better represent the fact that a portion of each pad/via is visible. Improvement: When writing the drill file, use XNC/Excellon Format 2. V1.84 Bug fix: Repainting pins on layer 2 did not update grid connections properly, and could crash when the part is moved. V1.83 Bug fix: Pin dialog should be hidden in component editor mode. Bug fix: Vias were only drawn with correct size in PCB mode. Improvement: Zoom with respect to mouse position rather than centre of view. Improvement: When adding to part templates from current circuit, only consider currently selected parts. Improvement: Reduce minimum allowed track width from 30 mil to 12 mil. New feature: Allow use vias to be enabled/disabled under Layers menu. New feature: Added new "Thin" track style for more traditional look and smaller Gerber files. V1.82 Bug fix: Merge should not update the filename used for saving. V1.81 Bug fix: Hiding the top toolbar made mouse clicks map to the wrong grid locations. Bug fix: Right clicking on the top toolbar allowed control and component editor dialogs to be displayed together. Added shell script to uninstall on Linux and updated README.txt with info on uninstall procedure. V1.80 Added second board layer. Made the Control and Component Editor dialogs dockable and docked by default. Updated the tutorials to describe 2-layer functionality. V1.79 New feature: File menu allows Gerber export as either 1-layer or 2-layer. Removed NPTH/PTH selection since it is implied by the export type (1-layer/2-layer). Changed hatched lines in Mono mode from yellow to red. Hide vias in PCB mode (as they are ignored at the moment). Help->Support now opens forum in browser. Added "Clear recent files list" to File menu. V1.78 Bug fix: Unpainted wire ends were being drawn as painted. Improvement: Added default label offsets to small Electrolytic Caps so they don't lie over pin holes. Stop offsetting pad labels by default (it was too confusing manipulating them like that). V1.77 Bug fix: Text rendering to PDF was broken by changes for PCB text. Improvement: Text size setting in Renderer Dialog affects PCB text size also. Improvement: Added more PCB parameters (for Gerber) to Rendering Dialog. Moved all Gerber related viewing from Mono mode to new PCB mode on the Track slider. V1.76 Improvement: In Mono mode, all text boxes are now automatically mirrored for toner-transfer. Improvement: In Mono mode, all component outlines and component text are rendered to match Gerber output. V1.75 Partial bug fix: Rendering components to PDF would always show them filled (even if "Fill" slider was off). Fixed to show only outline if "Fill" slider is off. New feature: Added info to rendering dialog showing the minimum guaranteed track separation based on the current (pad, track, gap, diagonal mode, ground fill) settings. New feature: Allow Gerber export when in Mono mode (Beta). V1.74 Better treatment of part labels under part rotation. Offset labels for Pads/Connectors by default. V1.73 New feature: Make pin label alignment (Left,Centre,Right) editable in pin labels dialog. V1.72 Bug fix: Flood fill not preserving status of grid under wires. V1.71 Bug fix: Component editor not checking connectors (strip/blocks) for reserved import strings. V1.70 Bug fix: Handle selection of rotated shapes in component editor. Bug fix: Make netlist import handle connectors (strip/blocks) with different numbers of pins. V1.69 New feature: Allow netlist import in OrcadPCB2 format (so KiCad can be used as schematic editor). V1.68 Bug fix: Component Editor not drawing footprint area with dashed line. V1.67 Bug fix: Rotating a track pattern did not correctly handle competing diagonals. Bug fix: Couldn't use keys to move/rotate a track pattern unless components were also selected. V1.66 New feature: Allow shapes to be filled with colors. V1.65 Bug fix: Wire hole-sharing under an IC only worked with wire-crossing enabled. Improvement: Render wires as rounded rectangles so hole-sharing looks clearer. V1.64 Bug fix: Fixed algorithm for stacking wires. New feature: Allow 2 wires to share a hole. Added "Wire Options" dialog to set allowed wire operations. V1.63 Bug fix: 1.62 could crash or corrupt the layout if stacking wires under an IC. V1.62 Bug fix: Don't allow parts/tracks selected by area to be manipulated if a control slider is hiding some of the selection. Bug fix: Don't show selected area if both control sliders are moved to Off. New feature: Allow wires to cross, and allow up to two wires to be stacked next to each other (but no hole sharing yet). V1.61 Improvement: Auto-router respects manually painted track between two pins. Allow manual over-painting of auto-routed track, and show all auto-routed tracks with hatched lines (including the current selection). Split "Paste" and "Tidy" buttons, and only allow "Tidy" on completed circuits. V1.60 Bug fix: Since V1.58, connected tracks were not always rendered properly. Improvement: Added option to disable "Fast" routing (to try reduce Bad Nodes). V1.59 Improvement: Added Key/Mouse Actions dialog under Help menu. V1.58 Improvement: Faster routing and connectivity checking. V1.57 Improvement: Faster routing algorithm. V1.56 Tweaked dialog layouts to better handle 11 point fonts. V1.55 Improvement: List recent VRT files in File menu. V1.54 Added Zoom buttons to toolbar. Changed executable name, folder names, and file names to lowercase. Made program search for "tutorials" folder in standard locations. V1.53 Improvement: Added Undo/Redo buttons to toolbar. Improvement: Allow Undo/Redo in Component Editor mode. V1.52 Bug fix: Missing Templates folder would disable Undo/Redo. Bug fix: Changing component type using Control Dialog (e.g. from Diode to LED) not working properly. History and Templates folders now auto-created in OS/application specific locations. V1.51 Bug fix: Floating track pattern could not be placed over unpainted wires on the board. Improvement: Made buttons to move component labels use a smaller step size. V1.50 Bug fix: Clicking on a floating track pattern should not place floating components. Moved the Pad/Track/Hole/Gap controls to the Rendering Options dialog. Updated the tutorials. V1.49 Restrict labels to 2 orientations. (Left to right, or bottom to top). Improvement: Add rendering options to show target board area. V1.48 Bug fix: Possible crash during auto-routing while moving wires. Improvement: Speed up algorithm for routing/connectivity checking. V1.47 Bug fix: Version 1.46 would produce duplicate shapes when loading parts from VRT. Bug fix: Changing DIP width wasn't changing the component outline. New feature: Component editor can define "holes" (i.e. non-paintable grid points). V1.46 Bug fix: Fixed error in loaded old VRTs with strip connectors. V1.45 Bug fix: Prevent mouse from dragging shapes off screen in the component editor. Bug fix: Fix shape selection in the component editor. V1.44 Bug fix: Fixed bad TRCD Relay. New feature: Added component editor. V1.43 Bug fix: Stop potential crash when defining areas for part/track selection. Improvement: Add toolbar button to select part/tracks by area. V1.42 Improvement: Added Rendering dialog controls for component text size. Bug fix: Correct footprints for GTR-2 relays. Improved outline sizes for relays and Bourns trimpots. V1.41 Bug fix: Menu and toolbars were being blanked while drawing rectangles with the "R" key. Bug fix: The status of the diagonals mode was not always restored when toggling between vero and non-vero styles. Improvement: Prevent copying of textboxes with no text. Improvement: Show text box outline in dark grey instead of black, so it can be seen in ground-fill mode. Improvement: When zooming in/out, try to keep the view showing the same centre point. Improvement: Draw pin labels in black instead of grey so they are easier to read. V1.40 Minor improvements: Automatically delete textboxes with no text. Show board size in mm in the window title bar. Show drawn rectangle size in mm in the status bar. Color toolbar icons to differentiate track styles / diagonal modes. V1.39 Moved some controls from the control dialog to the toolbar. Reduced heights of control dialog and templates dialog. V1.38 Added more component types: TO-39 package, pin strips, terminal blocks, inductor, wide film cap, fuse holder, relays. V1.37 Bug fix: Trying to undo "Delete text" could cause a crash. New feature: Text color can now be chosen. New feature: Hitting "V" key will copy+paste a selected text box. V1.36 Bug fix: Buttons in Text Label Editor weren't always reflecting text style. Bug fix: Prevent user from selecting text boxes in "Hide Text" mode. New feature: Added painting by "flood-fill". V1.35 New feature: Replace "Mirror" with "Flip-H" and "Flip-V" options. New feature: Add->Text menu item for putting labels on the grid. V1.34 Bug fix: Merge was not clearing existing user-defined areas. New feature: Added margin control for auto-crop. New feature: While the user draws a rectangle, show its size in the status bar. V1.33 New feature: Allow horizontal veroboard strips. Tweaked color assignment algorithm. V1.32 New feature: "File->Open (merge into current)". V1.31 Improvement: User-defined areas select tracks as well as components. V1.30 Improvement: Duplicating components copies their Value too if it's different to the name. Added more component types. (Relays, Switches, Trimpots). Changed default lengths of resistors and diodes to 400 mil. Updated gEDA/TinyCAD import code for RESISTOR/DIODE/CAP_CERAMIC/CAP_FILM so that appending an optional integer number to the footprint name sets the length in 100s of mil. (e.g. RESISTOR3 = 300mil) Updated gEDA library with resistors and caps of different lengths. Added ability to select components/wipe tracks within area (hold down "R" to draw areas). V1.29 Added Crystal component type and gEDA library symbol. V1.28 Improvements: Added "Toggle Grid" and "Toggle Mirror" as View menu items. List part types in B.O.M. Allow pin labels for TO packages as well as DIPs, SIPs. New feature: Added "Parts/Templates Dialog" so user can build a parts library for ICs and TO packages (avoids defining pin labels with each new circuit). Double-clicking on any listed part adds it to the circuit. V1.27 Bug fix: Deleting a component was not immediately updating the Bad Nodes lists. Bug fix: V1.26 allowed components to be dragged while user was painting pins. V1.26 Bug fix: Holding down "P" and SPACE at the same time would allow mouse move to modify component pins. Usability tweak: Holding down SPACE now allows un-painting the board under a placed component pin, or painting the board under the pin to match the existing NodeId on the pin. V1.25 Usability tweaks: Slow down the grid auto-pan/resize when moving components with the mouse. Selecting a NodeID in the "Broken" list should also highlight it in the "Floating" list if it's there. Added a Spin FV-1 IC and serial EEPROM to the gEDA library. V1.24 Added IC Pin Labels dialog. V1.23 Fixed memory leak on shutdown. Updated Tutorial 19 with info on creating a registry key for MS Windows. Added more JFETs to the symbol libraries.//"1.22"; // Added command line options to specify VRT file and path to VeroRoute home directory. Support drag and drop of VRT files from file explorer. Allow multiple VeroRoute instances to run at the same time. Improved error reporting during netlist import. Added color saturation slider. Changed rendering behaviour when clicking on an item in the Broken list. Added gEDA symbol libraries. V1.21 Improved rendering speed by avoiding pointless repaints. Control dialog rearranged so a checkbox controls ground-fill. Draw foil capacitors with thinner shape to better match the footprint. Draw floating component text in red. Made export to PDF centre on grid bounds instead of circuit bounds. Write status bar messages. V1.20 Added Grid checkbox. PDF shows bounding box and can show grid. Increased max pins per component to 255. When writing to file, append ". vrt", ".pdf", ".png" to filename as needed. V1.19 Add separate "Paste" and "Paste+Tidy" buttons for auto-routing. Updated tutorials. V1.18 Bug fix: Info dialog edits weren't treated as changes so "Save" was broken, but "Save As" was OK. V1.17 Added ground-fill. V1.16 Fixed mouse-wheel behaviour on windows. Added View menu option to show IC pins as numbers. V1.15 Added more Edit menu items. Check for Tutorials and History folders at start-up. V1.14 Added Help menu item to check if a new version is available. V1.13 Bug fixes: PDF write was broken since V1.10. "Add" menu item was enabled when view was mirrored. V1.12 Fixed TinyCAD package names for NP capacitors. Make netlist import allow spaces in Name and Value fields. V1.11 Fixed crash on importing unknown package. Increased maximum number of pins per component to over 200. V1.10 Added import of netlist from TinyCAD schematic. Hide old Import/Export. V1.01 Added scroll bars. Place new components in top-left of visible view and float them if needed. V1.00 Disable component text buttons when appropriate. Tidy code. Drop Beta. V0.999 Bug fix: Fix possible crash if adding new wire while auto-routing is enabled. V0.998 Bug fix: After "Paste" auto-routed wire, color should stay on board when wire moved. V0.997 Added part type combo. Added width buttons for DIP gap resizing instead of "E","R" keys. V0.996 Bug fix: Deleting grouped components could cause a crash later. Allow DIP gap resizing with "E","R" keys. V0.995 Check if circuit has been saved before launching Tutorials. Don't auto-raise Info window on Undo/Redo. V0.994 Bug fix: Erasing under floating pins while auto-routing. V0.993 Routing improvement. V0.992 Improve routing. V0.991 Bug fix: Redraw when toggling track styles. V0.99 Added new part types including multi-pole switches. V0.981 Bug fix: Undo/Redo. V0.98 Added Undo/Redo. V0.97 Added new part types. Improved TO-92 outline. Auto-centre when writing to PDF. V0.96 Show File menu-shortcuts. Fixed tutorial description of polarised component Export. V0.95 Added save to PNG. V0.94 Added B.O.M. V0.93 Try auto-generate unique Name when adding new part. V0.92 Add Ctrl shortcuts for File menu options. Changed tutorials. Fixed origId bug. V0.91 Fixed bad write to PDF. Allow backspace to work as delete. V0.90 First release to Sourceforge. VeroRoute/Src/TemplateManager.h000644 001750 001750 00000012056 14026402641 016705 0ustar00alexalex000000 000000 /* VeroRoute - Qt based Veroboard/Perfboard/PCB layout & routing application. Copyright (C) 2017 Alex Lawrow ( dralx@users.sourceforge.net ) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #pragma once #include "Template.h" // Manager class to handle component templates class TemplateManager : public Persist { public: TemplateManager() {} virtual ~TemplateManager() {} TemplateManager(const TemplateManager& o) { *this = o; } TemplateManager& operator=(const TemplateManager& o) { for (int i = 0; i < 2; i++ ) { const bool bGeneric = (i == 0); auto& listThis = bGeneric ? m_listGeneric : m_listUser; auto& listOther = bGeneric ? o.m_listGeneric : o.m_listUser; listThis.clear(); for (const auto& r : listOther) listThis.push_back( Template(r) ); } return *this; } const std::string& GetPathStr() const { return m_pathStr; } void SetPathStr(const std::string& str) { m_pathStr = str; } size_t GetSize(bool bGeneric) const { return bGeneric ? m_listGeneric.size() : m_listUser.size(); } const Component& GetNth(bool bGeneric, size_t N) const { assert( N < GetSize(bGeneric) ); auto iter = bGeneric ? m_listGeneric.begin() : m_listUser.begin(); for (size_t i = 0; i < N; i++) iter++; return *iter; } bool GetFromImportStr(const std::string& importStr, Component& out) const { for (const auto& o : m_listUser) if ( o.GetType() == COMP::CUSTOM && o.GetImportStr() == importStr ) { out = o; return true; } return false; } void AddDefaults() { std::string nameStr(""), valueStr(""); for (const auto& eType : CompTypes::GetListCompTypes()) { if ( eType == COMP::TRACKS ) continue; // Not a real component if ( eType == COMP::VERO_NUMBER ) continue; // Not a real component if ( eType == COMP::VERO_LETTER ) continue; // Not a real component if ( eType == COMP::CUSTOM ) continue; // Don't show custom components in the left pane const int numPins = CompTypes::GetDefaultNumPins(eType); std::vector nodeList; nodeList.resize(static_cast(numPins), BAD_NODEID); Component comp(nameStr, valueStr, eType, nodeList); comp.SetId(BAD_COMPID); // This indicates a component template Add(true, comp); // true ==> generic } } bool Add(bool bGeneric, const Component& comp, std::string* pErrorStr = nullptr) { Template entry; if ( !entry.MakeTemplate(comp) ) return false; auto& lst = bGeneric ? m_listGeneric : m_listUser; // Custom components need unique strings if ( comp.GetType() == COMP::CUSTOM ) { assert( !bGeneric ); for (const auto& o : lst) { if ( comp.GetTypeStr() == o.GetTypeStr() && comp.GetValueStr() == o.GetValueStr() ) { if ( pErrorStr ) *pErrorStr = "The template (Type = " + o.GetTypeStr() + ") " + "(Value = " + o.GetValueStr() + ") already exists"; return false; } else if ( !comp.GetImportStr().empty() && comp.GetImportStr() == o.GetImportStr() ) { if ( pErrorStr ) *pErrorStr = "The template (Type = " + o.GetTypeStr() + ") " + "(Value = " + o.GetValueStr() + ") " + "already has the Import string " + o.GetImportStr(); return false; } } } auto iter = lst.begin(); bool bOK = iter == lst.end() || entry.IsLessThan(*iter, bGeneric); if ( bOK ) lst.insert(iter, entry); while( iter != lst.end() && !bOK ) { Template& prev = *iter; ++iter; bOK = prev.IsLessThan(entry, bGeneric) && ( iter == lst.end() || entry.IsLessThan(*iter, bGeneric) ); if ( bOK ) lst.insert(iter, entry); } return bOK; } bool Remove(const Component& comp) { Template entry; if ( !entry.MakeTemplate(comp) ) return false; const auto iter = std::find(m_listUser.begin(), m_listUser.end(), entry); const bool bOK = ( iter != m_listUser.end() ); if ( bOK ) m_listUser.erase(iter); // Erase entry if it exists return bOK; } // Persist interface functions virtual void Load(DataStream& inStream) override { m_listUser.clear(); unsigned int iSize(0); inStream.Load(iSize); for (unsigned int i = 0; i < iSize; i++) { Template entry; entry.Load(inStream); m_listUser.push_back(entry); } } virtual void Save(DataStream& outStream) override { const unsigned int iSize = static_cast( m_listUser.size() ); outStream.Save(iSize); for (auto& o : m_listUser) o.Save(outStream); } private: std::string m_pathStr; // Path to the "templates" folder std::list